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wdenk935ecca2002-08-06 20:46:37 +00001/*----------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002| This source code is dual-licensed. You may use it under the terms of
3| the GNU General Public License version 2, or under the license below.
wdenk935ecca2002-08-06 20:46:37 +00004|
5| This source code has been made available to you by IBM on an AS-IS
6| basis. Anyone receiving this source is licensed under IBM
7| copyrights to use it in any way he or she deems fit, including
8| copying it, modifying it, compiling it, and redistributing it either
9| with or without modifications. No license under IBM patents or
10| patent applications is to be implied by the copyright license.
11|
12| Any user of this software should understand that IBM cannot provide
13| technical support for this software and will not be responsible for
14| any consequences resulting from the use of this software.
15|
16| Any person who transfers this source code or any derivative work
17| must include the IBM copyright notice, this paragraph, and the
18| preceding two paragraphs in the transferred software.
19|
20| COPYRIGHT I B M CORPORATION 1999
21| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22+----------------------------------------------------------------------------*/
23
24#ifndef __PPC4XX_H__
25#define __PPC4XX_H__
26
Stefan Roese36ea16f2008-06-02 14:57:41 +020027/*
28 * Configure which SDRAM/DDR/DDR2 controller is equipped
29 */
30#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
31 defined(CONFIG_AP1000) || defined(CONFIG_ML2)
32#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
33#endif
34
35#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
36 defined(CONFIG_440EP) || defined(CONFIG_440GR)
37#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
38#endif
39
40#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
41#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
42#endif
43
44#if defined(CONFIG_405EX) || \
45 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Feng Kan96e5fc02008-07-08 22:48:07 -070046 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
47 defined(CONFIG_460SX)
Stefan Roese36ea16f2008-06-02 14:57:41 +020048#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
49#endif
50
Stefan Roese5d841fa2009-05-20 10:58:01 +020051#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
52 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
53 defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
54 defined(CONFIG_460EX) || defined(CONFIG_460GT)
55#define CONFIG_NAND_NDFC
56#endif
57
Prodyut Hazarika079589b2008-08-20 09:38:51 -070058/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
59#if defined(CONFIG_405EX) || \
60 defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
61 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
62 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
63 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
64 defined(CONFIG_460SX)
65
66#define PLB_ARBITER_BASE 0x80
67
Stefan Roesed1c3b272009-09-09 16:25:29 +020068#define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
69#define PLB0_ACR_PPM_MASK 0xF0000000
70#define PLB0_ACR_PPM_FIXED 0x00000000
71#define PLB0_ACR_PPM_FAIR 0xD0000000
72#define PLB0_ACR_HBU_MASK 0x08000000
73#define PLB0_ACR_HBU_DISABLED 0x00000000
74#define PLB0_ACR_HBU_ENABLED 0x08000000
75#define PLB0_ACR_RDP_MASK 0x06000000
76#define PLB0_ACR_RDP_DISABLED 0x00000000
77#define PLB0_ACR_RDP_2DEEP 0x02000000
78#define PLB0_ACR_RDP_3DEEP 0x04000000
79#define PLB0_ACR_RDP_4DEEP 0x06000000
80#define PLB0_ACR_WRP_MASK 0x01000000
81#define PLB0_ACR_WRP_DISABLED 0x00000000
82#define PLB0_ACR_WRP_2DEEP 0x01000000
Prodyut Hazarika079589b2008-08-20 09:38:51 -070083
Stefan Roesed1c3b272009-09-09 16:25:29 +020084#define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
85#define PLB1_ACR_PPM_MASK 0xF0000000
86#define PLB1_ACR_PPM_FIXED 0x00000000
87#define PLB1_ACR_PPM_FAIR 0xD0000000
88#define PLB1_ACR_HBU_MASK 0x08000000
89#define PLB1_ACR_HBU_DISABLED 0x00000000
90#define PLB1_ACR_HBU_ENABLED 0x08000000
91#define PLB1_ACR_RDP_MASK 0x06000000
92#define PLB1_ACR_RDP_DISABLED 0x00000000
93#define PLB1_ACR_RDP_2DEEP 0x02000000
94#define PLB1_ACR_RDP_3DEEP 0x04000000
95#define PLB1_ACR_RDP_4DEEP 0x06000000
96#define PLB1_ACR_WRP_MASK 0x01000000
97#define PLB1_ACR_WRP_DISABLED 0x00000000
98#define PLB1_ACR_WRP_2DEEP 0x01000000
Prodyut Hazarika079589b2008-08-20 09:38:51 -070099
100#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
101
wdenk935ecca2002-08-06 20:46:37 +0000102#if defined(CONFIG_440)
Stefan Roesef2302d42008-08-06 14:05:38 +0200103/*
104 * Enable long long (%ll ...) printf format on 440 PPC's since most of
105 * them support 36bit physical addressing
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_64BIT_VSPRINTF
108#define CONFIG_SYS_64BIT_STRTOUL
wdenk935ecca2002-08-06 20:46:37 +0000109#include <ppc440.h>
110#else
111#include <ppc405.h>
112#endif
113
Stefan Roese36ea16f2008-06-02 14:57:41 +0200114#include <asm/ppc4xx-sdram.h>
Stefan Roese7ee26192008-06-24 17:18:50 +0200115#include <asm/ppc4xx-ebc.h>
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200116#if !defined(CONFIG_XILINX_440)
Stefan Roese4fb25a32008-06-25 10:59:22 +0200117#include <asm/ppc4xx-uic.h>
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200118#endif
Stefan Roese36ea16f2008-06-02 14:57:41 +0200119
Stefan Roese087dfdb2007-10-21 08:12:41 +0200120/*
Grant Ericksonc821b5f2008-05-22 14:44:14 -0700121 * Macro for generating register field mnemonics
122 */
123#define PPC_REG_BITS 32
124#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
125
126/*
127 * Elide casts when assembling register mnemonics
128 */
129#ifndef __ASSEMBLY__
130#define static_cast(type, val) (type)(val)
131#else
132#define static_cast(type, val) (val)
133#endif
134
135/*
Stefan Roese087dfdb2007-10-21 08:12:41 +0200136 * Common stuff for 4xx (405 and 440)
137 */
138
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200139#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
Stefan Roese087dfdb2007-10-21 08:12:41 +0200140#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
141
142#define RESET_VECTOR 0xfffffffc
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200143#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
144 cache line aligned data. */
Stefan Roese087dfdb2007-10-21 08:12:41 +0200145
146#define CPR0_DCR_BASE 0x0C
Stefan Roesed1c3b272009-09-09 16:25:29 +0200147#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
148#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200149
150#define SDR_DCR_BASE 0x0E
Stefan Roesed1c3b272009-09-09 16:25:29 +0200151#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
152#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200153
154#define SDRAM_DCR_BASE 0x10
Stefan Roesed1c3b272009-09-09 16:25:29 +0200155#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
156#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200157
158#define EBC_DCR_BASE 0x12
Stefan Roesed1c3b272009-09-09 16:25:29 +0200159#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
160#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200161
162/*
163 * Macros for indirect DCR access
164 */
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200165#define mtcpr(reg, d) \
166 do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
167#define mfcpr(reg, d) \
168 do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200169
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200170#define mtebc(reg, d) \
171 do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
172#define mfebc(reg, d) \
173 do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200174
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200175#define mtsdram(reg, d) \
176 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
177#define mfsdram(reg, d) \
178 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200179
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200180#define mtsdr(reg, d) \
181 do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
182#define mfsdr(reg, d) \
183 do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
Stefan Roese087dfdb2007-10-21 08:12:41 +0200184
185#ifndef __ASSEMBLY__
186
187typedef struct
188{
189 unsigned long freqDDR;
190 unsigned long freqEBC;
191 unsigned long freqOPB;
192 unsigned long freqPCI;
193 unsigned long freqPLB;
194 unsigned long freqTmrClk;
195 unsigned long freqUART;
196 unsigned long freqProcessor;
197 unsigned long freqVCOHz;
198 unsigned long freqVCOMhz; /* in MHz */
199 unsigned long pciClkSync; /* PCI clock is synchronous */
200 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
201 unsigned long pllExtBusDiv;
202 unsigned long pllFbkDiv;
203 unsigned long pllFwdDiv;
204 unsigned long pllFwdDivA;
205 unsigned long pllFwdDivB;
206 unsigned long pllOpbDiv;
207 unsigned long pllPciDiv;
208 unsigned long pllPlbDiv;
209} PPC4xx_SYS_INFO;
210
Adam Grahamf6b6c452008-09-03 12:26:59 -0700211static inline u32 get_mcsr(void)
212{
213 u32 val;
214
215 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
216 return val;
217}
218
219static inline void set_mcsr(u32 val)
220{
221 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
222}
223
Stefan Roese087dfdb2007-10-21 08:12:41 +0200224#endif /* __ASSEMBLY__ */
225
Adam Grahamc9c11d72008-10-08 10:13:19 -0700226/* for multi-cpu support */
227#define NA_OR_UNKNOWN_CPU -1
228
wdenk935ecca2002-08-06 20:46:37 +0000229#endif /* __PPC4XX_H__ */