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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk71f95112003-06-15 22:40:42 +00008 */
9
10#ifndef _MMC_H_
11#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000012
Andy Fleming272cc702008-10-30 16:41:01 -050013#include <linux/list.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000014#include <linux/compiler.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020015#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050016
17#define SD_VERSION_SD 0x20000
Jaehoon Chung1741c642013-01-29 22:58:16 +000018#define SD_VERSION_3 (SD_VERSION_SD | 0x300)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000019#define SD_VERSION_2 (SD_VERSION_SD | 0x200)
20#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100)
21#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
Andy Fleming272cc702008-10-30 16:41:01 -050022#define MMC_VERSION_MMC 0x10000
23#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000024#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102)
25#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104)
26#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202)
27#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300)
28#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400)
29#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401)
30#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402)
31#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
32#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
33#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
Andy Fleming272cc702008-10-30 16:41:01 -050034
35#define MMC_MODE_HS 0x001
36#define MMC_MODE_HS_52MHz 0x010
37#define MMC_MODE_4BIT 0x100
38#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000039#define MMC_MODE_SPI 0x400
Łukasz Majewskib1f1e822011-07-05 02:19:44 +000040#define MMC_MODE_HC 0x800
Andy Fleming272cc702008-10-30 16:41:01 -050041
Łukasz Majewski62722032012-03-12 22:07:18 +000042#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
43#define MMC_MODE_WIDTH_BITS_SHIFT 8
44
Andy Fleming272cc702008-10-30 16:41:01 -050045#define SD_DATA_4BIT 0x00040000
46
Albin Tonnerre79b91de2009-08-22 14:21:53 +020047#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050048
49#define MMC_DATA_READ 1
50#define MMC_DATA_WRITE 2
51
52#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
53#define UNUSABLE_ERR -17 /* Unusable Card */
54#define COMM_ERR -18 /* Communications Error */
55#define TIMEOUT -19
Che-Liang Chioue9550442012-11-28 15:21:13 +000056#define IN_PROGRESS -20 /* operation is in progress */
Andy Fleming272cc702008-10-30 16:41:01 -050057
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020058#define MMC_CMD_GO_IDLE_STATE 0
59#define MMC_CMD_SEND_OP_COND 1
60#define MMC_CMD_ALL_SEND_CID 2
61#define MMC_CMD_SET_RELATIVE_ADDR 3
62#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050063#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020064#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050065#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020066#define MMC_CMD_SEND_CSD 9
67#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050068#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020069#define MMC_CMD_SEND_STATUS 13
70#define MMC_CMD_SET_BLOCKLEN 16
71#define MMC_CMD_READ_SINGLE_BLOCK 17
72#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050073#define MMC_CMD_WRITE_SINGLE_BLOCK 24
74#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +000075#define MMC_CMD_ERASE_GROUP_START 35
76#define MMC_CMD_ERASE_GROUP_END 36
77#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020078#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000079#define MMC_CMD_SPI_READ_OCR 58
80#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +053081#define MMC_CMD_RES_MAN 62
82
83#define MMC_CMD62_ARG1 0xefac62ec
84#define MMC_CMD62_ARG2 0xcbaea7
85
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020086
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020087#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050088#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020089#define SD_CMD_SEND_IF_COND 8
90
91#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wene6f99a52011-06-22 17:03:31 +000092#define SD_CMD_ERASE_WR_BLK_START 32
93#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020094#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -050095#define SD_CMD_APP_SEND_SCR 51
96
97/* SCR definitions in different words */
98#define SD_HIGHSPEED_BUSY 0x00020000
99#define SD_HIGHSPEED_SUPPORTED 0x00020000
100
101#define MMC_HS_TIMING 0x00000100
102#define MMC_HS_52MHZ 0x2
103
Thomas Chouabe2c932011-04-19 03:48:31 +0000104#define OCR_BUSY 0x80000000
105#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000106#define OCR_VOLTAGE_MASK 0x007FFF80
107#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500108
Lei Wene6f99a52011-06-22 17:03:31 +0000109#define SECURE_ERASE 0x80000000
110
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000111#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000112#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
113#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000114#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000115
Jan Kloetzked617c422012-02-05 22:29:12 +0000116#define MMC_STATE_PRG (7 << 9)
117
Andy Fleming272cc702008-10-30 16:41:01 -0500118#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
119#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
120#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
121#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
122#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
123#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
124#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
125#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
126#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
127#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
128#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
129#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
130#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
131#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
132#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
133#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
134#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
135
136#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
137#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
138 addressed by index which are
139 1 in value field */
140#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
141 addressed by index, which are
142 1 in value field */
143#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
144
145#define SD_SWITCH_CHECK 0
146#define SD_SWITCH_SWITCH 1
147
148/*
149 * EXT_CSD fields
150 */
Stephen Warrenf866a462013-06-11 15:14:01 -0600151#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200152#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Lei Wen0560db12011-10-03 20:35:10 +0000153#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500154#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600155#define EXT_CSD_RPMB_MULT 168 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000156#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530157#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000158#define EXT_CSD_PART_CONF 179 /* R/W */
159#define EXT_CSD_BUS_WIDTH 183 /* R/W */
160#define EXT_CSD_HS_TIMING 185 /* R/W */
161#define EXT_CSD_REV 192 /* RO */
162#define EXT_CSD_CARD_TYPE 196 /* RO */
163#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600164#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000165#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000166#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500167
168/*
169 * EXT_CSD field definitions
170 */
171
Thomas Chouabe2c932011-04-19 03:48:31 +0000172#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
173#define EXT_CSD_CMD_SET_SECURE (1 << 1)
174#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500175
Thomas Chouabe2c932011-04-19 03:48:31 +0000176#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
177#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500178
179#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
180#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
181#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200182
Amar3690d6d2013-04-27 11:42:58 +0530183#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
184#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
185#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
186#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
187
188#define EXT_CSD_BOOT_ACK(x) (x << 6)
189#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
190#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
191
Tom Rini5a99b9d2014-02-05 10:24:22 -0500192#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
193#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
194#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530195
Andy Fleming1de97f92008-10-30 16:31:39 -0500196#define R1_ILLEGAL_COMMAND (1 << 22)
197#define R1_APP_CMD (1 << 5)
198
Andy Fleming272cc702008-10-30 16:41:01 -0500199#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000200#define MMC_RSP_136 (1 << 1) /* 136 bit response */
201#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
202#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
203#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500204
Thomas Chouabe2c932011-04-19 03:48:31 +0000205#define MMC_RSP_NONE (0)
206#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500207#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
208 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000209#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
210#define MMC_RSP_R3 (MMC_RSP_PRESENT)
211#define MMC_RSP_R4 (MMC_RSP_PRESENT)
212#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
213#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
214#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500215
Lei Wenbc897b12011-05-02 16:26:26 +0000216#define MMCPART_NOAVAILABLE (0xff)
217#define PART_ACCESS_MASK (0x7)
218#define PART_SUPPORT (0x1)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200219#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000220
Simon Glass8bfa1952013-04-03 08:54:30 +0000221/* Maximum block size for MMC */
222#define MMC_MAX_BLOCK_LEN 512
223
Amar3690d6d2013-04-27 11:42:58 +0530224/* The number of MMC physical partitions. These consist of:
225 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
226 */
227#define MMC_NUM_BOOT_PARTITION 2
228
Andy Fleming1de97f92008-10-30 16:31:39 -0500229struct mmc_cid {
230 unsigned long psn;
231 unsigned short oid;
232 unsigned char mid;
233 unsigned char prv;
234 unsigned char mdt;
235 char pnm[7];
236};
237
Andy Fleming272cc702008-10-30 16:41:01 -0500238struct mmc_cmd {
239 ushort cmdidx;
240 uint resp_type;
241 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530242 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500243};
244
245struct mmc_data {
246 union {
247 char *dest;
248 const char *src; /* src buffers don't get written to */
249 };
250 uint flags;
251 uint blocks;
252 uint blocksize;
253};
254
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200255/* forward decl. */
256struct mmc;
257
258struct mmc_ops {
259 int (*send_cmd)(struct mmc *mmc,
260 struct mmc_cmd *cmd, struct mmc_data *data);
261 void (*set_ios)(struct mmc *mmc);
262 int (*init)(struct mmc *mmc);
263 int (*getcd)(struct mmc *mmc);
264 int (*getwp)(struct mmc *mmc);
265};
266
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200267struct mmc_config {
268 const char *name;
269 const struct mmc_ops *ops;
270 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500271 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500272 uint f_min;
273 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200274 uint b_max;
275 unsigned char part_type;
276};
277
278/* TODO struct mmc should be in mmc_private but it's hard to fix right now */
279struct mmc {
280 struct list_head link;
281 const struct mmc_config *cfg; /* provided configuration */
282 uint version;
283 void *priv;
284 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500285 int high_capacity;
286 uint bus_width;
287 uint clock;
288 uint card_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500289 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100290 uint dsr;
291 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500292 uint scr[2];
293 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530294 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500295 ushort rca;
Lei Wenbc897b12011-05-02 16:26:26 +0000296 char part_config;
297 char part_num;
Andy Fleming272cc702008-10-30 16:41:01 -0500298 uint tran_speed;
299 uint read_bl_len;
300 uint write_bl_len;
Lei Wene6f99a52011-06-22 17:03:31 +0000301 uint erase_grp_size;
Andy Fleming272cc702008-10-30 16:41:01 -0500302 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600303 u64 capacity_user;
304 u64 capacity_boot;
305 u64 capacity_rpmb;
306 u64 capacity_gp[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500307 block_dev_desc_t block_dev;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000308 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
309 char init_in_progress; /* 1 if we have done mmc_start_init() */
310 char preinit; /* start init as early as possible */
311 uint op_cond_response; /* the response byte from the last op_cond */
Andy Fleming272cc702008-10-30 16:41:01 -0500312};
313
314int mmc_register(struct mmc *mmc);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200315struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
316void mmc_destroy(struct mmc *mmc);
Andy Fleming272cc702008-10-30 16:41:01 -0500317int mmc_initialize(bd_t *bis);
318int mmc_init(struct mmc *mmc);
319int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000320void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500321struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700322int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500323void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000324int get_mmc_num(void);
Thierry Reding314284b2012-01-02 01:15:36 +0000325int board_mmc_getcd(struct mmc *mmc);
Lei Wenbc897b12011-05-02 16:26:26 +0000326int mmc_switch_part(int dev_num, unsigned int part_num);
Thierry Reding48972d92012-01-02 01:15:37 +0000327int mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000328int mmc_getwp(struct mmc *mmc);
Markus Niebelab711882013-12-16 13:40:46 +0100329int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530330/* Function to change the size of boot partition and rpmb partitions */
331int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
332 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500333/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
334int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500335/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
336int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500337/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
338int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Andy Fleming272cc702008-10-30 16:41:01 -0500339
Che-Liang Chioue9550442012-11-28 15:21:13 +0000340/**
341 * Start device initialization and return immediately; it does not block on
342 * polling OCR (operation condition register) status. Then you should call
343 * mmc_init, which would block on polling OCR status and complete the device
344 * initializatin.
345 *
346 * @param mmc Pointer to a MMC device struct
347 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
348 */
349int mmc_start_init(struct mmc *mmc);
350
351/**
352 * Set preinit flag of mmc device.
353 *
354 * This will cause the device to be pre-inited during mmc_initialize(),
355 * which may save boot time if the device is not accessed until later.
356 * Some eMMC devices take 200-300ms to init, but unfortunately they
357 * must be sent a series of commands to even get them to start preparing
358 * for operation.
359 *
360 * @param mmc Pointer to a MMC device struct
361 * @param preinit preinit flag value
362 */
363void mmc_set_preinit(struct mmc *mmc, int preinit);
364
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200365#ifdef CONFIG_GENERIC_MMC
Paul Burton8687d5c2013-09-04 16:12:26 +0100366#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400367#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100368#else
369#define mmc_host_is_spi(mmc) 0
370#endif
Thomas Choud52ebf12010-12-24 13:12:21 +0000371struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200372#else
Andy Fleming272cc702008-10-30 16:41:01 -0500373int mmc_legacy_init(int verbose);
374#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200375
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200376int board_mmc_init(bd_t *bis);
377
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200378/* Set block count limit because of 16 bit register limit on some hardware*/
379#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
380#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
381#endif
382
wdenk71f95112003-06-15 22:40:42 +0000383#endif /* _MMC_H_ */