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wdenk71f95112003-06-15 22:40:42 +00001/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00002 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05003 * Andy Fleming
4 *
5 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00006 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Thomas Chouabe2c932011-04-19 03:48:31 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk71f95112003-06-15 22:40:42 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef _MMC_H_
27#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000028
Andy Fleming272cc702008-10-30 16:41:01 -050029#include <linux/list.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000030#include <linux/compiler.h>
Andy Fleming272cc702008-10-30 16:41:01 -050031
32#define SD_VERSION_SD 0x20000
Jaehoon Chung1741c642013-01-29 22:58:16 +000033#define SD_VERSION_3 (SD_VERSION_SD | 0x300)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000034#define SD_VERSION_2 (SD_VERSION_SD | 0x200)
35#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100)
36#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a)
Andy Fleming272cc702008-10-30 16:41:01 -050037#define MMC_VERSION_MMC 0x10000
38#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC)
Jaehoon Chung64f4a612013-01-29 19:31:16 +000039#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102)
40#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104)
41#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202)
42#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300)
43#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400)
44#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401)
45#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402)
46#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
47#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
48#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
Andy Fleming272cc702008-10-30 16:41:01 -050049
50#define MMC_MODE_HS 0x001
51#define MMC_MODE_HS_52MHz 0x010
52#define MMC_MODE_4BIT 0x100
53#define MMC_MODE_8BIT 0x200
Thomas Choud52ebf12010-12-24 13:12:21 +000054#define MMC_MODE_SPI 0x400
Łukasz Majewskib1f1e822011-07-05 02:19:44 +000055#define MMC_MODE_HC 0x800
Andy Fleming272cc702008-10-30 16:41:01 -050056
Łukasz Majewski62722032012-03-12 22:07:18 +000057#define MMC_MODE_MASK_WIDTH_BITS (MMC_MODE_4BIT | MMC_MODE_8BIT)
58#define MMC_MODE_WIDTH_BITS_SHIFT 8
59
Andy Fleming272cc702008-10-30 16:41:01 -050060#define SD_DATA_4BIT 0x00040000
61
Albin Tonnerre79b91de2009-08-22 14:21:53 +020062#define IS_SD(x) (x->version & SD_VERSION_SD)
Andy Fleming272cc702008-10-30 16:41:01 -050063
64#define MMC_DATA_READ 1
65#define MMC_DATA_WRITE 2
66
67#define NO_CARD_ERR -16 /* No SD/MMC card inserted */
68#define UNUSABLE_ERR -17 /* Unusable Card */
69#define COMM_ERR -18 /* Communications Error */
70#define TIMEOUT -19
Che-Liang Chioue9550442012-11-28 15:21:13 +000071#define IN_PROGRESS -20 /* operation is in progress */
Andy Fleming272cc702008-10-30 16:41:01 -050072
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020073#define MMC_CMD_GO_IDLE_STATE 0
74#define MMC_CMD_SEND_OP_COND 1
75#define MMC_CMD_ALL_SEND_CID 2
76#define MMC_CMD_SET_RELATIVE_ADDR 3
77#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050078#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020079#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050080#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020081#define MMC_CMD_SEND_CSD 9
82#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -050083#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020084#define MMC_CMD_SEND_STATUS 13
85#define MMC_CMD_SET_BLOCKLEN 16
86#define MMC_CMD_READ_SINGLE_BLOCK 17
87#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Andy Fleming272cc702008-10-30 16:41:01 -050088#define MMC_CMD_WRITE_SINGLE_BLOCK 24
89#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +000090#define MMC_CMD_ERASE_GROUP_START 35
91#define MMC_CMD_ERASE_GROUP_END 36
92#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020093#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +000094#define MMC_CMD_SPI_READ_OCR 58
95#define MMC_CMD_SPI_CRC_ON_OFF 59
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020096
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020097#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -050098#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020099#define SD_CMD_SEND_IF_COND 8
100
101#define SD_CMD_APP_SET_BUS_WIDTH 6
Lei Wene6f99a52011-06-22 17:03:31 +0000102#define SD_CMD_ERASE_WR_BLK_START 32
103#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200104#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500105#define SD_CMD_APP_SEND_SCR 51
106
107/* SCR definitions in different words */
108#define SD_HIGHSPEED_BUSY 0x00020000
109#define SD_HIGHSPEED_SUPPORTED 0x00020000
110
111#define MMC_HS_TIMING 0x00000100
112#define MMC_HS_52MHZ 0x2
113
Thomas Chouabe2c932011-04-19 03:48:31 +0000114#define OCR_BUSY 0x80000000
115#define OCR_HCS 0x40000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000116#define OCR_VOLTAGE_MASK 0x007FFF80
117#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500118
Lei Wene6f99a52011-06-22 17:03:31 +0000119#define SECURE_ERASE 0x80000000
120
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000121#define MMC_STATUS_MASK (~0x0206BF7F)
Thomas Chouabe2c932011-04-19 03:48:31 +0000122#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
123#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000124#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000125
Jan Kloetzked617c422012-02-05 22:29:12 +0000126#define MMC_STATE_PRG (7 << 9)
127
Andy Fleming272cc702008-10-30 16:41:01 -0500128#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
129#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
130#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
131#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
132#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
133#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
134#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
135#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
136#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
137#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
138#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
139#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
140#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
141#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
142#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
143#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
144#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
145
146#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
147#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
148 addressed by index which are
149 1 in value field */
150#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
151 addressed by index, which are
152 1 in value field */
153#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
154
155#define SD_SWITCH_CHECK 0
156#define SD_SWITCH_SWITCH 1
157
158/*
159 * EXT_CSD fields
160 */
Lei Wen0560db12011-10-03 20:35:10 +0000161#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
162#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
163#define EXT_CSD_PART_CONF 179 /* R/W */
164#define EXT_CSD_BUS_WIDTH 183 /* R/W */
165#define EXT_CSD_HS_TIMING 185 /* R/W */
166#define EXT_CSD_REV 192 /* RO */
167#define EXT_CSD_CARD_TYPE 196 /* RO */
168#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
169#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000170#define EXT_CSD_BOOT_MULT 226 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500171
172/*
173 * EXT_CSD field definitions
174 */
175
Thomas Chouabe2c932011-04-19 03:48:31 +0000176#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
177#define EXT_CSD_CMD_SET_SECURE (1 << 1)
178#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500179
Thomas Chouabe2c932011-04-19 03:48:31 +0000180#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
181#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Andy Fleming272cc702008-10-30 16:41:01 -0500182
183#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
184#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
185#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200186
Andy Fleming1de97f92008-10-30 16:31:39 -0500187#define R1_ILLEGAL_COMMAND (1 << 22)
188#define R1_APP_CMD (1 << 5)
189
Andy Fleming272cc702008-10-30 16:41:01 -0500190#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000191#define MMC_RSP_136 (1 << 1) /* 136 bit response */
192#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
193#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
194#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500195
Thomas Chouabe2c932011-04-19 03:48:31 +0000196#define MMC_RSP_NONE (0)
197#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500198#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
199 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000200#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
201#define MMC_RSP_R3 (MMC_RSP_PRESENT)
202#define MMC_RSP_R4 (MMC_RSP_PRESENT)
203#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
204#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
205#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500206
Lei Wenbc897b12011-05-02 16:26:26 +0000207#define MMCPART_NOAVAILABLE (0xff)
208#define PART_ACCESS_MASK (0x7)
209#define PART_SUPPORT (0x1)
wdenk71f95112003-06-15 22:40:42 +0000210
Simon Glass8bfa1952013-04-03 08:54:30 +0000211/* Maximum block size for MMC */
212#define MMC_MAX_BLOCK_LEN 512
213
Andy Fleming1de97f92008-10-30 16:31:39 -0500214struct mmc_cid {
215 unsigned long psn;
216 unsigned short oid;
217 unsigned char mid;
218 unsigned char prv;
219 unsigned char mdt;
220 char pnm[7];
221};
222
Andy Fleming272cc702008-10-30 16:41:01 -0500223struct mmc_cmd {
224 ushort cmdidx;
225 uint resp_type;
226 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530227 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500228};
229
230struct mmc_data {
231 union {
232 char *dest;
233 const char *src; /* src buffers don't get written to */
234 };
235 uint flags;
236 uint blocks;
237 uint blocksize;
238};
239
240struct mmc {
241 struct list_head link;
242 char name[32];
243 void *priv;
244 uint voltages;
245 uint version;
Lei Wenbc897b12011-05-02 16:26:26 +0000246 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500247 uint f_min;
248 uint f_max;
249 int high_capacity;
250 uint bus_width;
251 uint clock;
252 uint card_caps;
253 uint host_caps;
254 uint ocr;
255 uint scr[2];
256 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530257 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500258 ushort rca;
Lei Wenbc897b12011-05-02 16:26:26 +0000259 char part_config;
260 char part_num;
Andy Fleming272cc702008-10-30 16:41:01 -0500261 uint tran_speed;
262 uint read_bl_len;
263 uint write_bl_len;
Lei Wene6f99a52011-06-22 17:03:31 +0000264 uint erase_grp_size;
Andy Fleming272cc702008-10-30 16:41:01 -0500265 u64 capacity;
266 block_dev_desc_t block_dev;
267 int (*send_cmd)(struct mmc *mmc,
268 struct mmc_cmd *cmd, struct mmc_data *data);
269 void (*set_ios)(struct mmc *mmc);
270 int (*init)(struct mmc *mmc);
Thierry Reding48972d92012-01-02 01:15:37 +0000271 int (*getcd)(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000272 int (*getwp)(struct mmc *mmc);
Sandeep Paulraj57418d22010-12-20 20:01:21 -0500273 uint b_max;
Che-Liang Chioue9550442012-11-28 15:21:13 +0000274 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
275 char init_in_progress; /* 1 if we have done mmc_start_init() */
276 char preinit; /* start init as early as possible */
277 uint op_cond_response; /* the response byte from the last op_cond */
Andy Fleming272cc702008-10-30 16:41:01 -0500278};
279
280int mmc_register(struct mmc *mmc);
281int mmc_initialize(bd_t *bis);
282int mmc_init(struct mmc *mmc);
283int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Jerry Huang4a6ee172010-11-25 17:06:07 +0000284void mmc_set_clock(struct mmc *mmc, uint clock);
Andy Fleming272cc702008-10-30 16:41:01 -0500285struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700286int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500287void print_mmc_devices(char separator);
Lei Wenea6ebe22011-05-02 16:26:25 +0000288int get_mmc_num(void);
Thierry Reding314284b2012-01-02 01:15:36 +0000289int board_mmc_getcd(struct mmc *mmc);
Lei Wenbc897b12011-05-02 16:26:26 +0000290int mmc_switch_part(int dev_num, unsigned int part_num);
Thierry Reding48972d92012-01-02 01:15:37 +0000291int mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000292int mmc_getwp(struct mmc *mmc);
Lad, Prabhakar0d986e62012-06-24 21:35:20 +0000293void spl_mmc_load(void) __noreturn;
Andy Fleming272cc702008-10-30 16:41:01 -0500294
Che-Liang Chioue9550442012-11-28 15:21:13 +0000295/**
296 * Start device initialization and return immediately; it does not block on
297 * polling OCR (operation condition register) status. Then you should call
298 * mmc_init, which would block on polling OCR status and complete the device
299 * initializatin.
300 *
301 * @param mmc Pointer to a MMC device struct
302 * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
303 */
304int mmc_start_init(struct mmc *mmc);
305
306/**
307 * Set preinit flag of mmc device.
308 *
309 * This will cause the device to be pre-inited during mmc_initialize(),
310 * which may save boot time if the device is not accessed until later.
311 * Some eMMC devices take 200-300ms to init, but unfortunately they
312 * must be sent a series of commands to even get them to start preparing
313 * for operation.
314 *
315 * @param mmc Pointer to a MMC device struct
316 * @param preinit preinit flag value
317 */
318void mmc_set_preinit(struct mmc *mmc, int preinit);
319
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200320#ifdef CONFIG_GENERIC_MMC
Thomas Choud52ebf12010-12-24 13:12:21 +0000321#define mmc_host_is_spi(mmc) ((mmc)->host_caps & MMC_MODE_SPI)
322struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200323#else
Andy Fleming272cc702008-10-30 16:41:01 -0500324int mmc_legacy_init(int verbose);
325#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200326
wdenk71f95112003-06-15 22:40:42 +0000327#endif /* _MMC_H_ */