Blame - include/955x.h - codeaurora/quic/qsdk/oss/boot/u-boot-2016

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)

850

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)

851

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1

852

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23

853

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23

854

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000

855

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)

856

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)

857

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0

858

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22

859

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22

860

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000

861

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)

862

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)

863

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0

864

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MSB 21

865

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21

866

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000

867

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB)

868

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)

869

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_RESET 0x0

870

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MSB 20

871

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20

872

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000

873

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB)

874

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)

875

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_RESET 0x0 // 0

876

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19

877

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15

878

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000

879

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)

880

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)

881

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0

882

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14

883

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10

884

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00

885

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)

886

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)

887

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0

888

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9

889

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5

890

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0

891

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)

892

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)

893

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0

894

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4

895

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4

896

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010

897

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)

898

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)

899

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1

900

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3

901

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3

902

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008

903

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)

904

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)

905

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1

906

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2

907

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2

908

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004

909

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)

910

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)

911

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1

912

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1

913

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1

914

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002

915

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)

916

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)

917

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0

918

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0

919

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0

920

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001

921

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)

922

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)

923

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0

924

#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008

925

926

#define PCIE_PLL_CONFIG_UPDATING_MSB 31

927

#define PCIE_PLL_CONFIG_UPDATING_LSB 31

928

#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000

929

#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)

930

#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)

931

#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0

932

#define PCIE_PLL_CONFIG_PLLPWD_MSB 30

933

#define PCIE_PLL_CONFIG_PLLPWD_LSB 30

934

#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000

935

#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)

936

#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)

937

#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1

938

#define PCIE_PLL_CONFIG_BYPASS_MSB 16

939

#define PCIE_PLL_CONFIG_BYPASS_LSB 16

940

#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000

941

#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)

942

#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)

943

#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1

944

#define PCIE_PLL_CONFIG_REFDIV_MSB 14

945

#define PCIE_PLL_CONFIG_REFDIV_LSB 10

946

#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00

947

#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)

948

#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)

949

#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1

950

#define PCIE_PLL_CONFIG_ADDRESS 0x1805000c

951

952

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31

953

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31

954

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000

955

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)

956

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)

957

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1

958

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30

959

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30

960

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000

961

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)

962

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)

963

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1

964

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20

965

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15

966

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000

967

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)

968

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)

969

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19

970

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14

971

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1

972

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe

973

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)

974

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)

975

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383

976

#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050010

977

978

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20

979

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15

980

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000

981

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)

982

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)

983

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19

984

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14

985

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1

986

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe

987

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)

988

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)

989

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749

990

#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050014

991

992

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31

993

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28

994

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000

995

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)

996

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)

997

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0

998

#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24

999

#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15

1000

#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000

1001

#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)

1002

#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)

1003

#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0

1004

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14

1005

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1

1006

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe

1007

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)

1008

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)

1009

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10

1010

#define PCIE_PLL_DITHER_STEP_ADDRESS 0x18050018

1011

1012

#define LDO_POWER_CONTROL_PKG_SEL_MSB 5

1013

#define LDO_POWER_CONTROL_PKG_SEL_LSB 5

1014

#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020

1015

#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)

1016

#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)

1017

#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0

1018

#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4

1019

#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4

1020

#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010

1021

#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)

1022

#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)

1023

#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0

1024

#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3

1025

#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3

1026

#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008

1027

#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)

1028

#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)

1029

#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0

1030

#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2

1031

#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1

1032

#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006

1033

#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)

1034

#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)

1035

#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3

1036

#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0

1037

#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0

1038

#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001

1039

#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)

1040

#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)

1041

#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0

1042

#define LDO_POWER_CONTROL_ADDRESS 0x1805001c

1043

1044

#define SWITCH_CLOCK_SPARE_SPARE_MSB 31

1045

#define SWITCH_CLOCK_SPARE_SPARE_LSB 16

1046

#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xffff0000

1047

#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)

1048

#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)

1049

#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0

1050

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MSB 15

1051

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB 15

1052

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK 0x00008000

1053

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB)

1054

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK)

1055

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_RESET 0x0 // 0

1056

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MSB 14

1057

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB 14

1058

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK 0x00004000

1059

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB)

1060

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK)

1061

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_RESET 0x0 // 0

1062

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MSB 13

1063

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB 13

1064

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK 0x00002000

1065

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB)

1066

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK)

1067

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_RESET 0x0 // 0

1068

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MSB 12

1069

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB 12

1070

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK 0x00001000

1071

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB)

1072

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK)

1073

#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_RESET 0x0 // 0

1074

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11

1075

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8

1076

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00

1077

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)

1078

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)

1079

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5

1080

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7

1081

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7

1082

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080

1083

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)

1084

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)

1085

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0

1086

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MSB 6

1087

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB 6

1088

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK 0x00000040

1089

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB)

1090

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK)

1091

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_RESET 0x0 // 0

1092

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MSB 5

1093

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB 5

1094

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK 0x00000020

1095

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB)

1096

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK)

1097

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_RESET 0x0 // 0

1098

#define SWITCH_CLOCK_SPARE_SPARE_0_MSB 4

1099

#define SWITCH_CLOCK_SPARE_SPARE_0_LSB 0

1100

#define SWITCH_CLOCK_SPARE_SPARE_0_MASK 0x0000001f

1101

#define SWITCH_CLOCK_SPARE_SPARE_0_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_0_MASK) >> SWITCH_CLOCK_SPARE_SPARE_0_LSB)

1102

#define SWITCH_CLOCK_SPARE_SPARE_0_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_0_LSB) & SWITCH_CLOCK_SPARE_SPARE_0_MASK)

1103

#define SWITCH_CLOCK_SPARE_SPARE_0_RESET 0x0 // 0

1104

#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050020

1105

1106

#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20

1107

#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15

1108

#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000

1109

#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)

1110

#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)

1111

#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1

1112

#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13

1113

#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0

1114

#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff

1115

#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)

1116

#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)

1117

#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0

1118

#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050024

1119

1120

#define ETH_XMII_TX_INVERT_MSB 31

1121

#define ETH_XMII_TX_INVERT_LSB 31

1122

#define ETH_XMII_TX_INVERT_MASK 0x80000000

1123

#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)

1124

#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)

1125

#define ETH_XMII_TX_INVERT_RESET 0x0 // 0

1126

#define ETH_XMII_GIGE_QUAD_MSB 30

1127

#define ETH_XMII_GIGE_QUAD_LSB 30

1128

#define ETH_XMII_GIGE_QUAD_MASK 0x40000000

1129

#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)

1130

#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)

1131

#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0

1132

#define ETH_XMII_RX_DELAY_MSB 29

1133

#define ETH_XMII_RX_DELAY_LSB 28

1134

#define ETH_XMII_RX_DELAY_MASK 0x30000000

1135

#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)

1136

#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)

1137

#define ETH_XMII_RX_DELAY_RESET 0x0 // 0

1138

#define ETH_XMII_TX_DELAY_MSB 27

1139

#define ETH_XMII_TX_DELAY_LSB 26

1140

#define ETH_XMII_TX_DELAY_MASK 0x0c000000

1141

#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)

1142

#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)

1143

#define ETH_XMII_TX_DELAY_RESET 0x0 // 0

1144

#define ETH_XMII_GIGE_MSB 25

1145

#define ETH_XMII_GIGE_LSB 25

1146

#define ETH_XMII_GIGE_MASK 0x02000000

1147

#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)

1148

#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)

1149

#define ETH_XMII_GIGE_RESET 0x0 // 0

1150

#define ETH_XMII_OFFSET_PHASE_MSB 24

1151

#define ETH_XMII_OFFSET_PHASE_LSB 24

1152

#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000

1153

#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)

1154

#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)

1155

#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0

1156

#define ETH_XMII_OFFSET_COUNT_MSB 23

1157

#define ETH_XMII_OFFSET_COUNT_LSB 16

1158

#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000

1159

#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)

1160

#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)

1161

#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0

1162

#define ETH_XMII_PHASE1_COUNT_MSB 15

1163

#define ETH_XMII_PHASE1_COUNT_LSB 8

1164

#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00

1165

#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)

1166

#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)

1167

#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1

1168

#define ETH_XMII_PHASE0_COUNT_MSB 7

1169

#define ETH_XMII_PHASE0_COUNT_LSB 0

1170

#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff

1171

#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)

1172

#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)

1173

#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1

1174

#define ETH_XMII_ADDRESS 0x18050028

1175

1176

#define AUDIO_PLL_CONFIG_UPDATING_MSB 31

1177

#define AUDIO_PLL_CONFIG_UPDATING_LSB 31

1178

#define AUDIO_PLL_CONFIG_UPDATING_MASK 0x80000000

1179

#define AUDIO_PLL_CONFIG_UPDATING_GET(x) (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB)

1180

#define AUDIO_PLL_CONFIG_UPDATING_SET(x) (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK)

1181

#define AUDIO_PLL_CONFIG_UPDATING_RESET 0x1 // 1

1182

#define AUDIO_PLL_CONFIG_EXT_DIV_MSB 14

1183

#define AUDIO_PLL_CONFIG_EXT_DIV_LSB 12

1184

#define AUDIO_PLL_CONFIG_EXT_DIV_MASK 0x00007000

1185

#define AUDIO_PLL_CONFIG_EXT_DIV_GET(x) (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB)

1186

#define AUDIO_PLL_CONFIG_EXT_DIV_SET(x) (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK)

1187

#define AUDIO_PLL_CONFIG_EXT_DIV_RESET 0x1 // 1

1188

#define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB 9

1189

#define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB 7

1190

#define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK 0x00000380

1191

#define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB)

1192

#define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK)

1193

#define AUDIO_PLL_CONFIG_POSTPLLDIV_RESET 0x1 // 1

1194

#define AUDIO_PLL_CONFIG_PLLPWD_MSB 5

1195

#define AUDIO_PLL_CONFIG_PLLPWD_LSB 5

1196

#define AUDIO_PLL_CONFIG_PLLPWD_MASK 0x00000020

1197

#define AUDIO_PLL_CONFIG_PLLPWD_GET(x) (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB)

1198

#define AUDIO_PLL_CONFIG_PLLPWD_SET(x) (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK)

1199

#define AUDIO_PLL_CONFIG_PLLPWD_RESET 0x1 // 1

1200

#define AUDIO_PLL_CONFIG_BYPASS_MSB 4

1201

#define AUDIO_PLL_CONFIG_BYPASS_LSB 4

1202

#define AUDIO_PLL_CONFIG_BYPASS_MASK 0x00000010

1203

#define AUDIO_PLL_CONFIG_BYPASS_GET(x) (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB)

1204

#define AUDIO_PLL_CONFIG_BYPASS_SET(x) (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK)

1205

#define AUDIO_PLL_CONFIG_BYPASS_RESET 0x1 // 1

1206

#define AUDIO_PLL_CONFIG_REFDIV_MSB 3

1207

#define AUDIO_PLL_CONFIG_REFDIV_LSB 0

1208

#define AUDIO_PLL_CONFIG_REFDIV_MASK 0x0000000f

1209

#define AUDIO_PLL_CONFIG_REFDIV_GET(x) (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB)

1210

#define AUDIO_PLL_CONFIG_REFDIV_SET(x) (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK)

1211

#define AUDIO_PLL_CONFIG_REFDIV_RESET 0x3 // 3

1212

#define AUDIO_PLL_CONFIG_ADDRESS 0x1805002c

1213

1214

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB 28

1215

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB 11

1216

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK 0x1ffff800

1217

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB)

1218

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK)

1219

#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_RESET 0x148fe // 84222

1220

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB 6

1221

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB 1

1222

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK 0x0000007e

1223

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB)

1224

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK)

1225

#define AUDIO_PLL_MODULATION_TGT_DIV_INT_RESET 0x14 // 20

1226

#define AUDIO_PLL_MODULATION_START_MSB 0

1227

#define AUDIO_PLL_MODULATION_START_LSB 0

1228

#define AUDIO_PLL_MODULATION_START_MASK 0x00000001

1229

#define AUDIO_PLL_MODULATION_START_GET(x) (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB)

1230

#define AUDIO_PLL_MODULATION_START_SET(x) (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK)

1231

#define AUDIO_PLL_MODULATION_START_RESET 0x0 // 0

1232

#define AUDIO_PLL_MODULATION_ADDRESS 0x18050030

1233

1234

#define AUDIO_PLL_MOD_STEP_FRAC_MSB 31

1235

#define AUDIO_PLL_MOD_STEP_FRAC_LSB 14

1236

#define AUDIO_PLL_MOD_STEP_FRAC_MASK 0xffffc000

1237

#define AUDIO_PLL_MOD_STEP_FRAC_GET(x) (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB)

1238

#define AUDIO_PLL_MOD_STEP_FRAC_SET(x) (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK)

1239

#define AUDIO_PLL_MOD_STEP_FRAC_RESET 0x1 // 1

1240

#define AUDIO_PLL_MOD_STEP_INT_MSB 13

1241

#define AUDIO_PLL_MOD_STEP_INT_LSB 4

1242

#define AUDIO_PLL_MOD_STEP_INT_MASK 0x00003ff0

1243

#define AUDIO_PLL_MOD_STEP_INT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB)

1244

#define AUDIO_PLL_MOD_STEP_INT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK)

1245

#define AUDIO_PLL_MOD_STEP_INT_RESET 0x0 // 0

1246

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB 3

1247

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB 0

1248

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK 0x0000000f

1249

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x) (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB)

1250

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x) (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK)

1251

#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_RESET 0x0 // 0

1252

#define AUDIO_PLL_MOD_STEP_ADDRESS 0x18050034

1253

1254

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB 27

1255

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB 10

1256

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK 0x0ffffc00

1257

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB)

1258

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK)

1259

#define CURRENT_AUDIO_PLL_MODULATION_FRAC_RESET 0x1 // 1

1260

#define CURRENT_AUDIO_PLL_MODULATION_INT_MSB 6

1261

#define CURRENT_AUDIO_PLL_MODULATION_INT_LSB 1

1262

#define CURRENT_AUDIO_PLL_MODULATION_INT_MASK 0x0000007e

1263

#define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB)

1264

#define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK)

1265

#define CURRENT_AUDIO_PLL_MODULATION_INT_RESET 0x0 // 0

1266

#define CURRENT_AUDIO_PLL_MODULATION_ADDRESS 0x18050038

1267

1268

#define BB_PLL_CONFIG_UPDATING_MSB 31

1269

#define BB_PLL_CONFIG_UPDATING_LSB 31

1270

#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000

1271

#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)

1272

#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)

1273

#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1

1274

#define BB_PLL_CONFIG_PLLPWD_MSB 30

1275

#define BB_PLL_CONFIG_PLLPWD_LSB 30

1276

#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000

1277

#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)

1278

#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)

1279

#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1

1280

#define BB_PLL_CONFIG_SPARE_MSB 29

1281

#define BB_PLL_CONFIG_SPARE_LSB 29

1282

#define BB_PLL_CONFIG_SPARE_MASK 0x20000000

1283

#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)

1284

#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)

1285

#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0

1286

#define BB_PLL_CONFIG_REFDIV_MSB 28

1287

#define BB_PLL_CONFIG_REFDIV_LSB 24

1288

#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000

1289

#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)

1290

#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)

1291

#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1

1292

#define BB_PLL_CONFIG_NINT_MSB 21

1293

#define BB_PLL_CONFIG_NINT_LSB 16

1294

#define BB_PLL_CONFIG_NINT_MASK 0x003f0000

1295

#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)

1296

#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)

1297

#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2

1298

#define BB_PLL_CONFIG_NFRAC_MSB 13

1299

#define BB_PLL_CONFIG_NFRAC_LSB 0

1300

#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff

1301

#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)

1302

#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)

1303

#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276

1304

#define BB_PLL_CONFIG_ADDRESS 0x1805003c

1305

1306

#define DDR_PLL_DITHER_DITHER_EN_MSB 31

1307

#define DDR_PLL_DITHER_DITHER_EN_LSB 31

1308

#define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000

1309

#define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)

1310

#define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)

1311

#define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0

1312

#define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30

1313

#define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27

1314

#define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000

1315

#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)

1316

#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)

1317

#define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15

1318

#define DDR_PLL_DITHER_NFRAC_STEP_MSB 26

1319

#define DDR_PLL_DITHER_NFRAC_STEP_LSB 20

1320

#define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000

1321

#define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)

1322

#define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)

1323

#define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1

1324

#define DDR_PLL_DITHER_NFRAC_MIN_MSB 19

1325

#define DDR_PLL_DITHER_NFRAC_MIN_LSB 10

1326

#define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00

1327

#define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)

1328

#define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)

1329

#define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25

1330

#define DDR_PLL_DITHER_NFRAC_MAX_MSB 9

1331

#define DDR_PLL_DITHER_NFRAC_MAX_LSB 0

1332

#define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff

1333

#define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)

1334

#define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)

1335

#define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000

1336

#define DDR_PLL_DITHER_ADDRESS 0x18050040

1337

1338

#define CPU_PLL_DITHER_DITHER_EN_MSB 31

1339

#define CPU_PLL_DITHER_DITHER_EN_LSB 31

1340

#define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000

1341

#define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)

1342

#define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)

1343

#define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0

1344

#define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23

1345

#define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18

1346

#define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000

1347

#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)

1348

#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)

1349

#define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20

1350

#define CPU_PLL_DITHER_NFRAC_STEP_MSB 17

1351

#define CPU_PLL_DITHER_NFRAC_STEP_LSB 12

1352

#define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000

1353

#define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)

1354

#define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)

1355

#define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1

1356

#define CPU_PLL_DITHER_NFRAC_MIN_MSB 11

1357

#define CPU_PLL_DITHER_NFRAC_MIN_LSB 6

1358

#define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0

1359

#define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)

1360

#define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)

1361

#define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3

1362

#define CPU_PLL_DITHER_NFRAC_MAX_MSB 5

1363

#define CPU_PLL_DITHER_NFRAC_MAX_LSB 0

1364

#define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f

1365

#define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)

1366

#define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)

1367

#define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60

1368

#define CPU_PLL_DITHER_ADDRESS 0x18050044

1369

1370

#define RST_RESET_HOST_RESET_MSB 31

1371

#define RST_RESET_HOST_RESET_LSB 31

1372

#define RST_RESET_HOST_RESET_MASK 0x80000000

1373

#define RST_RESET_HOST_RESET_GET(x) (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)

1374

#define RST_RESET_HOST_RESET_SET(x) (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)

1375

#define RST_RESET_HOST_RESET_RESET 0x0 // 0

1376

#define RST_RESET_SLIC_RESET_MSB 30

1377

#define RST_RESET_SLIC_RESET_LSB 30

1378

#define RST_RESET_SLIC_RESET_MASK 0x40000000

1379

#define RST_RESET_SLIC_RESET_GET(x) (((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB)

1380

#define RST_RESET_SLIC_RESET_SET(x) (((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK)

1381

#define RST_RESET_SLIC_RESET_RESET 0x0 // 0

1382

#define RST_RESET_HDMA_RESET_MSB 29

1383

#define RST_RESET_HDMA_RESET_LSB 29

1384

#define RST_RESET_HDMA_RESET_MASK 0x20000000

1385

#define RST_RESET_HDMA_RESET_GET(x) (((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB)

1386

#define RST_RESET_HDMA_RESET_SET(x) (((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK)

1387

#define RST_RESET_HDMA_RESET_RESET 0x1 // 1

1388

#define RST_RESET_EXTERNAL_RESET_MSB 28

1389

#define RST_RESET_EXTERNAL_RESET_LSB 28

1390

#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000

1391

#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)

1392

#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)

1393

#define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0

1394

#define RST_RESET_RTC_RESET_MSB 27

1395

#define RST_RESET_RTC_RESET_LSB 27

1396

#define RST_RESET_RTC_RESET_MASK 0x08000000

1397

#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)

1398

#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)

1399

#define RST_RESET_RTC_RESET_RESET 0x1 // 1

1400

#define RST_RESET_PCIEEP_RST_INT_MSB 26

1401

#define RST_RESET_PCIEEP_RST_INT_LSB 26

1402

#define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000

1403

#define RST_RESET_PCIEEP_RST_INT_GET(x) (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)

1404

#define RST_RESET_PCIEEP_RST_INT_SET(x) (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)

1405

#define RST_RESET_PCIEEP_RST_INT_RESET 0x0 // 0

1406

#define RST_RESET_CHKSUM_ACC_RESET_MSB 25

1407

#define RST_RESET_CHKSUM_ACC_RESET_LSB 25

1408

#define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000

1409

#define RST_RESET_CHKSUM_ACC_RESET_GET(x) (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB)

1410

#define RST_RESET_CHKSUM_ACC_RESET_SET(x) (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK)

1411

#define RST_RESET_CHKSUM_ACC_RESET_RESET 0x0 // 0

1412

#define RST_RESET_FULL_CHIP_RESET_MSB 24

1413

#define RST_RESET_FULL_CHIP_RESET_LSB 24

1414

#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000

1415

#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)

1416

#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)

1417

#define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0

1418

#define RST_RESET_GE1_MDIO_RESET_MSB 23

1419

#define RST_RESET_GE1_MDIO_RESET_LSB 23

1420

#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000

1421

#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)

1422

#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)

1423

#define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1

1424

#define RST_RESET_GE0_MDIO_RESET_MSB 22

1425

#define RST_RESET_GE0_MDIO_RESET_LSB 22

1426

#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000

1427

#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)

1428

#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)

1429

#define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1

1430

#define RST_RESET_CPU_NMI_MSB 21

1431

#define RST_RESET_CPU_NMI_LSB 21

1432

#define RST_RESET_CPU_NMI_MASK 0x00200000

1433

#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)

1434

#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)

1435

#define RST_RESET_CPU_NMI_RESET 0x0 // 0

1436

#define RST_RESET_CPU_COLD_RESET_MSB 20

1437

#define RST_RESET_CPU_COLD_RESET_LSB 20

1438

#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000

1439

#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)

1440

#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)

1441

#define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0

1442

#define RST_RESET_HOST_RESET_INT_MSB 19

1443

#define RST_RESET_HOST_RESET_INT_LSB 19

1444

#define RST_RESET_HOST_RESET_INT_MASK 0x00080000

1445

#define RST_RESET_HOST_RESET_INT_GET(x) (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)

1446

#define RST_RESET_HOST_RESET_INT_SET(x) (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)

1447

#define RST_RESET_HOST_RESET_INT_RESET 0x0 // 0

1448

#define RST_RESET_PCIEEP_RESET_MSB 18

1449

#define RST_RESET_PCIEEP_RESET_LSB 18

1450

#define RST_RESET_PCIEEP_RESET_MASK 0x00040000

1451

#define RST_RESET_PCIEEP_RESET_GET(x) (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)

1452

#define RST_RESET_PCIEEP_RESET_SET(x) (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)

1453

#define RST_RESET_PCIEEP_RESET_RESET 0x0 // 0

1454

#define RST_RESET_UART1_RESET_MSB 17

1455

#define RST_RESET_UART1_RESET_LSB 17

1456

#define RST_RESET_UART1_RESET_MASK 0x00020000

1457

#define RST_RESET_UART1_RESET_GET(x) (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)

1458

#define RST_RESET_UART1_RESET_SET(x) (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)

1459

#define RST_RESET_UART1_RESET_RESET 0x0 // 0

1460

#define RST_RESET_DDR_RESET_MSB 16

1461

#define RST_RESET_DDR_RESET_LSB 16

1462

#define RST_RESET_DDR_RESET_MASK 0x00010000

1463

#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)

1464

#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)

1465

#define RST_RESET_DDR_RESET_RESET 0x0 // 0

1466

#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15

1467

#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15

1468

#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000

1469

#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)

1470

#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)

1471

#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0

1472

#define RST_RESET_NANDF_RESET_MSB 14

1473

#define RST_RESET_NANDF_RESET_LSB 14

1474

#define RST_RESET_NANDF_RESET_MASK 0x00004000

1475

#define RST_RESET_NANDF_RESET_GET(x) (((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB)

1476

#define RST_RESET_NANDF_RESET_SET(x) (((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK)

1477

#define RST_RESET_NANDF_RESET_RESET 0x1 // 1

1478

#define RST_RESET_GE1_MAC_RESET_MSB 13

1479

#define RST_RESET_GE1_MAC_RESET_LSB 13

1480

#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000

1481

#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)

1482

#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)

1483

#define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1

1484

#define RST_RESET_ETH_SGMII_ARESET_MSB 12

1485

#define RST_RESET_ETH_SGMII_ARESET_LSB 12

1486

#define RST_RESET_ETH_SGMII_ARESET_MASK 0x00001000

1487

#define RST_RESET_ETH_SGMII_ARESET_GET(x) (((x) & RST_RESET_ETH_SGMII_ARESET_MASK) >> RST_RESET_ETH_SGMII_ARESET_LSB)

1488

#define RST_RESET_ETH_SGMII_ARESET_SET(x) (((x) << RST_RESET_ETH_SGMII_ARESET_LSB) & RST_RESET_ETH_SGMII_ARESET_MASK)

1489

#define RST_RESET_ETH_SGMII_ARESET_RESET 0x1 // 1

1490

#define RST_RESET_USB_PHY_ARESET_MSB 11

1491

#define RST_RESET_USB_PHY_ARESET_LSB 11

1492

#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800

1493

#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)

1494

#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)

1495

#define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1

1496

#define RST_RESET_HOST_DMA_INT_MSB 10

1497

#define RST_RESET_HOST_DMA_INT_LSB 10

1498

#define RST_RESET_HOST_DMA_INT_MASK 0x00000400

1499

#define RST_RESET_HOST_DMA_INT_GET(x) (((x) & RST_RESET_HOST_DMA_INT_MASK) >> RST_RESET_HOST_DMA_INT_LSB)

1500

#define RST_RESET_HOST_DMA_INT_SET(x) (((x) << RST_RESET_HOST_DMA_INT_LSB) & RST_RESET_HOST_DMA_INT_MASK)

1501

#define RST_RESET_HOST_DMA_INT_RESET 0x0 // 0

1502

#define RST_RESET_GE0_MAC_RESET_MSB 9

1503

#define RST_RESET_GE0_MAC_RESET_LSB 9

1504

#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200

1505

#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)

1506

#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)

1507

#define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1

1508

#define RST_RESET_ETH_SGMII_RESET_MSB 8

1509

#define RST_RESET_ETH_SGMII_RESET_LSB 8

1510

#define RST_RESET_ETH_SGMII_RESET_MASK 0x00000100

1511

#define RST_RESET_ETH_SGMII_RESET_GET(x) (((x) & RST_RESET_ETH_SGMII_RESET_MASK) >> RST_RESET_ETH_SGMII_RESET_LSB)

1512

#define RST_RESET_ETH_SGMII_RESET_SET(x) (((x) << RST_RESET_ETH_SGMII_RESET_LSB) & RST_RESET_ETH_SGMII_RESET_MASK)

1513

#define RST_RESET_ETH_SGMII_RESET_RESET 0x1 // 1

1514

#define RST_RESET_PCIE_PHY_RESET_MSB 7

1515

#define RST_RESET_PCIE_PHY_RESET_LSB 7

1516

#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080

1517

#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)

1518

#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)

1519

#define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1

1520

#define RST_RESET_PCIE_RESET_MSB 6

1521

#define RST_RESET_PCIE_RESET_LSB 6

1522

#define RST_RESET_PCIE_RESET_MASK 0x00000040

1523

#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)

1524

#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)

1525

#define RST_RESET_PCIE_RESET_RESET 0x1 // 1

1526

#define RST_RESET_USB_HOST_RESET_MSB 5

1527

#define RST_RESET_USB_HOST_RESET_LSB 5

1528

#define RST_RESET_USB_HOST_RESET_MASK 0x00000020

1529

#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)

1530

#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)

1531

#define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1

1532

#define RST_RESET_USB_PHY_RESET_MSB 4

1533

#define RST_RESET_USB_PHY_RESET_LSB 4

1534

#define RST_RESET_USB_PHY_RESET_MASK 0x00000010

1535

#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)

1536

#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)

1537

#define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1

1538

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3

1539

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3

1540

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008

1541

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)

1542

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)

1543

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0

1544

#define RST_RESET_LUT_RESET_MSB 2

1545

#define RST_RESET_LUT_RESET_LSB 2

1546

#define RST_RESET_LUT_RESET_MASK 0x00000004

1547

#define RST_RESET_LUT_RESET_GET(x) (((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB)

1548

#define RST_RESET_LUT_RESET_SET(x) (((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK)

1549

#define RST_RESET_LUT_RESET_RESET 0x0 // 0

1550

#define RST_RESET_MBOX_RESET_MSB 1

1551

#define RST_RESET_MBOX_RESET_LSB 1

1552

#define RST_RESET_MBOX_RESET_MASK 0x00000002

1553

#define RST_RESET_MBOX_RESET_GET(x) (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)

1554

#define RST_RESET_MBOX_RESET_SET(x) (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)

1555

#define RST_RESET_MBOX_RESET_RESET 0x0 // 0

1556

#define RST_RESET_I2S_RESET_MSB 0

1557

#define RST_RESET_I2S_RESET_LSB 0

1558

#define RST_RESET_I2S_RESET_MASK 0x00000001

1559

#define RST_RESET_I2S_RESET_GET(x) (((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB)

1560

#define RST_RESET_I2S_RESET_SET(x) (((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK)

1561

#define RST_RESET_I2S_RESET_RESET 0x0 // 0

1562

#define RST_RESET_ADDRESS 0x1806001c

1563

1564

#define RST_MISC2_PCIEEP_LINK_UP_MSB 30

1565

#define RST_MISC2_PCIEEP_LINK_UP_LSB 30

1566

#define RST_MISC2_PCIEEP_LINK_UP_MASK 0x40000000

1567

#define RST_MISC2_PCIEEP_LINK_UP_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_UP_MASK) >> RST_MISC2_PCIEEP_LINK_UP_LSB)

1568

#define RST_MISC2_PCIEEP_LINK_UP_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_UP_LSB) & RST_MISC2_PCIEEP_LINK_UP_MASK)

1569

#define RST_MISC2_PCIEEP_LINK_UP_RESET 0x0 // 0

1570

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MSB 29

1571

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB 29

1572

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK 0x20000000

1573

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_GET(x) (((x) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK) >> RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB)

1574

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_SET(x) (((x) << RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK)

1575

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_RESET 0x0 // 0

1576

#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 28

1577

#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 28

1578

#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x10000000

1579

#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)

1580

#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)

1581

#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0

1582

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MSB 27

1583

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB 27

1584

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK 0x08000000

1585

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_GET(x) (((x) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK) >> RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB)

1586

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_SET(x) (((x) << RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK)

1587

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_RESET 0x0 // 0

1588

#define RST_MISC2_WOW_STATUS_MSB 26

1589

#define RST_MISC2_WOW_STATUS_LSB 26

1590

#define RST_MISC2_WOW_STATUS_MASK 0x04000000

1591

#define RST_MISC2_WOW_STATUS_GET(x) (((x) & RST_MISC2_WOW_STATUS_MASK) >> RST_MISC2_WOW_STATUS_LSB)

1592

#define RST_MISC2_WOW_STATUS_SET(x) (((x) << RST_MISC2_WOW_STATUS_LSB) & RST_MISC2_WOW_STATUS_MASK)

1593

#define RST_MISC2_WOW_STATUS_RESET 0x0 // 0

1594

#define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB 25

1595

#define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB 25

1596

#define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK 0x02000000

1597

#define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB)

1598

#define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK)

1599

#define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET 0x0 // 0

1600

#define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB 24

1601

#define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB 24

1602

#define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK 0x01000000

1603

#define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB)

1604

#define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK)

1605

#define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET 0x0 // 0

1606

#define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB 23

1607

#define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB 23

1608

#define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK 0x00800000

1609

#define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB)

1610

#define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK)

1611

#define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET 0x0 // 0

1612

#define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB 22

1613

#define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB 22

1614

#define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK 0x00400000

1615

#define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB)

1616

#define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK)

1617

#define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET 0x0 // 0

1618

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB 21

1619

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB 21

1620

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK 0x00200000

1621

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB)

1622

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK)

1623

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET 0x0 // 0

1624

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB 20

1625

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB 20

1626

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK 0x00100000

1627

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB)

1628

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK)

1629

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET 0x0 // 0

1630

#define RST_MISC2_PCIEEP_REGWR_EN_MSB 19

1631

#define RST_MISC2_PCIEEP_REGWR_EN_LSB 19

1632

#define RST_MISC2_PCIEEP_REGWR_EN_MASK 0x00080000

1633

#define RST_MISC2_PCIEEP_REGWR_EN_GET(x) (((x) & RST_MISC2_PCIEEP_REGWR_EN_MASK) >> RST_MISC2_PCIEEP_REGWR_EN_LSB)

1634

#define RST_MISC2_PCIEEP_REGWR_EN_SET(x) (((x) << RST_MISC2_PCIEEP_REGWR_EN_LSB) & RST_MISC2_PCIEEP_REGWR_EN_MASK)

1635

#define RST_MISC2_PCIEEP_REGWR_EN_RESET 0x1 // 1

1636

#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18

1637

#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18

1638

#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000

1639

#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)

1640

#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)

1641

#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0

1642

#define RST_MISC2_PCIEEP_RST_INT_MSB 17

1643

#define RST_MISC2_PCIEEP_RST_INT_LSB 17

1644

#define RST_MISC2_PCIEEP_RST_INT_MASK 0x00020000

1645

#define RST_MISC2_PCIEEP_RST_INT_GET(x) (((x) & RST_MISC2_PCIEEP_RST_INT_MASK) >> RST_MISC2_PCIEEP_RST_INT_LSB)

1646

#define RST_MISC2_PCIEEP_RST_INT_SET(x) (((x) << RST_MISC2_PCIEEP_RST_INT_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK)

1647

#define RST_MISC2_PCIEEP_RST_INT_RESET 0x0 // 0

1648

#define RST_MISC2_HOST_RESET_INT_MSB 16

1649

#define RST_MISC2_HOST_RESET_INT_LSB 16

1650

#define RST_MISC2_HOST_RESET_INT_MASK 0x00010000

1651

#define RST_MISC2_HOST_RESET_INT_GET(x) (((x) & RST_MISC2_HOST_RESET_INT_MASK) >> RST_MISC2_HOST_RESET_INT_LSB)

1652

#define RST_MISC2_HOST_RESET_INT_SET(x) (((x) << RST_MISC2_HOST_RESET_INT_LSB) & RST_MISC2_HOST_RESET_INT_MASK)

1653

#define RST_MISC2_HOST_RESET_INT_RESET 0x0 // 0

1654

#define RST_MISC2_CPU_HOST_WA_MSB 15

1655

#define RST_MISC2_CPU_HOST_WA_LSB 15

1656

#define RST_MISC2_CPU_HOST_WA_MASK 0x00008000

1657

#define RST_MISC2_CPU_HOST_WA_GET(x) (((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB)

1658

#define RST_MISC2_CPU_HOST_WA_SET(x) (((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK)

1659

#define RST_MISC2_CPU_HOST_WA_RESET 0x0 // 0

1660

#define RST_MISC2_PERSTN_RCPHY2_MSB 14

1661

#define RST_MISC2_PERSTN_RCPHY2_LSB 14

1662

#define RST_MISC2_PERSTN_RCPHY2_MASK 0x00004000

1663

#define RST_MISC2_PERSTN_RCPHY2_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY2_MASK) >> RST_MISC2_PERSTN_RCPHY2_LSB)

1664

#define RST_MISC2_PERSTN_RCPHY2_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY2_LSB) & RST_MISC2_PERSTN_RCPHY2_MASK)

1665

#define RST_MISC2_PERSTN_RCPHY2_RESET 0x1 // 1

1666

#define RST_MISC2_PERSTN_RCPHY_MSB 13

1667

#define RST_MISC2_PERSTN_RCPHY_LSB 13

1668

#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000

1669

#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)

1670

#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)

1671

#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1

1672

#define RST_MISC2_PCIEEP_LTSSM_STATE_MSB 12

1673

#define RST_MISC2_PCIEEP_LTSSM_STATE_LSB 8

1674

#define RST_MISC2_PCIEEP_LTSSM_STATE_MASK 0x00001f00

1675

#define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x) (((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB)

1676

#define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x) (((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK)

1677

#define RST_MISC2_PCIEEP_LTSSM_STATE_RESET 0x0 // 0

1678

#define RST_MISC2_PCIEEP_LINK_STATUS_MSB 4

1679

#define RST_MISC2_PCIEEP_LINK_STATUS_LSB 4

1680

#define RST_MISC2_PCIEEP_LINK_STATUS_MASK 0x00000010

1681

#define RST_MISC2_PCIEEP_LINK_STATUS_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB)

1682

#define RST_MISC2_PCIEEP_LINK_STATUS_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK)

1683

#define RST_MISC2_PCIEEP_LINK_STATUS_RESET 0x0 // 0

1684

#define RST_MISC2_WOW_DETECT_MSB 3

1685

#define RST_MISC2_WOW_DETECT_LSB 3

1686

#define RST_MISC2_WOW_DETECT_MASK 0x00000008

1687

#define RST_MISC2_WOW_DETECT_GET(x) (((x) & RST_MISC2_WOW_DETECT_MASK) >> RST_MISC2_WOW_DETECT_LSB)

1688

#define RST_MISC2_WOW_DETECT_SET(x) (((x) << RST_MISC2_WOW_DETECT_LSB) & RST_MISC2_WOW_DETECT_MASK)

1689

#define RST_MISC2_WOW_DETECT_RESET 0x0 // 0

1690

#define RST_MISC2_PCIEEP_RXDETECT_DONE_MSB 2

1691

#define RST_MISC2_PCIEEP_RXDETECT_DONE_LSB 2

1692

#define RST_MISC2_PCIEEP_RXDETECT_DONE_MASK 0x00000004

1693

#define RST_MISC2_PCIEEP_RXDETECT_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK) >> RST_MISC2_PCIEEP_RXDETECT_DONE_LSB)

1694

#define RST_MISC2_PCIEEP_RXDETECT_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_RXDETECT_DONE_LSB) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK)

1695

#define RST_MISC2_PCIEEP_RXDETECT_DONE_RESET 0x0 // 0

1696

#define RST_MISC2_PCIEEP_WOW_INT_MSB 1

1697

#define RST_MISC2_PCIEEP_WOW_INT_LSB 1

1698

#define RST_MISC2_PCIEEP_WOW_INT_MASK 0x00000002

1699

#define RST_MISC2_PCIEEP_WOW_INT_GET(x) (((x) & RST_MISC2_PCIEEP_WOW_INT_MASK) >> RST_MISC2_PCIEEP_WOW_INT_LSB)

1700

#define RST_MISC2_PCIEEP_WOW_INT_SET(x) (((x) << RST_MISC2_PCIEEP_WOW_INT_LSB) & RST_MISC2_PCIEEP_WOW_INT_MASK)

1701

#define RST_MISC2_PCIEEP_WOW_INT_RESET 0x0 // 0

1702

#define RST_MISC2_PCIEEP_CFG_DONE_MSB 0

1703

#define RST_MISC2_PCIEEP_CFG_DONE_LSB 0

1704

#define RST_MISC2_PCIEEP_CFG_DONE_MASK 0x00000001

1705

#define RST_MISC2_PCIEEP_CFG_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB)

1706

#define RST_MISC2_PCIEEP_CFG_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK)

1707

#define RST_MISC2_PCIEEP_CFG_DONE_RESET 0x0 // 0

1708

#define RST_MISC2_ADDRESS 0x180600bc

1709

1710

#define PCIE_APP_CFG_TYPE_MSB 21

1711

#define PCIE_APP_CFG_TYPE_LSB 20

1712

#define PCIE_APP_CFG_TYPE_MASK 0x00300000

1713

#define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)

1714

#define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)

1715

#define PCIE_APP_CFG_TYPE_RESET 0x0 // 0

1716

#define PCIE_APP_PCIE_BAR_MSN_MSB 19

1717

#define PCIE_APP_PCIE_BAR_MSN_LSB 16

1718

#define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000

1719

#define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)

1720

#define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)

1721

#define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1

1722

#define PCIE_APP_CFG_BE_MSB 15

1723

#define PCIE_APP_CFG_BE_LSB 12

1724

#define PCIE_APP_CFG_BE_MASK 0x0000f000

1725

#define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)

1726

#define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)

1727

#define PCIE_APP_CFG_BE_RESET 0xf // 15

1728

#define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11

1729

#define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6

1730

#define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0

1731

#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)

1732

#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)

1733

#define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63

1734

#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5

1735

#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4

1736

#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030

1737

#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)

1738

#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)

1739

#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0

1740

#define PCIE_APP_INIT_RST_MSB 3

1741

#define PCIE_APP_INIT_RST_LSB 3

1742

#define PCIE_APP_INIT_RST_MASK 0x00000008

1743

#define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)

1744

#define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)

1745

#define PCIE_APP_INIT_RST_RESET 0x0 // 0

1746

#define PCIE_APP_PM_XMT_TURNOFF_MSB 2

1747

#define PCIE_APP_PM_XMT_TURNOFF_LSB 2

1748

#define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004

1749

#define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)

1750

#define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)

1751

#define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0

1752

#define PCIE_APP_UNLOCK_MSG_MSB 1

1753

#define PCIE_APP_UNLOCK_MSG_LSB 1

1754

#define PCIE_APP_UNLOCK_MSG_MASK 0x00000002

1755

#define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)

1756

#define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)

1757

#define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0

1758

#define PCIE_APP_LTSSM_ENABLE_MSB 0

1759

#define PCIE_APP_LTSSM_ENABLE_LSB 0

1760

#define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001

1761

#define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)

1762

#define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)

1763

#define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0

1764

#define PCIE_APP_ADDRESS 0x180f0000

1765

1766

1767

#define XTAL_TCXODET_MSB 31

1768

#define XTAL_TCXODET_LSB 31

1769

#define XTAL_TCXODET_MASK 0x80000000

1770

#define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB)

1771

#define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK)

1772

#define XTAL_TCXODET_RESET 0x0 // 0

1773

#define XTAL_XTAL_CAPINDAC_MSB 30

1774

#define XTAL_XTAL_CAPINDAC_LSB 24

1775

#define XTAL_XTAL_CAPINDAC_MASK 0x7f000000

1776

#define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB)

1777

#define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK)

1778

#define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75

1779

#define XTAL_XTAL_CAPOUTDAC_MSB 23

1780

#define XTAL_XTAL_CAPOUTDAC_LSB 17

1781

#define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000

1782

#define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB)

1783

#define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK)

1784

#define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75

1785

#define XTAL_XTAL_DRVSTR_MSB 16

1786

#define XTAL_XTAL_DRVSTR_LSB 15

1787

#define XTAL_XTAL_DRVSTR_MASK 0x00018000

1788

#define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB)

1789

#define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK)

1790

#define XTAL_XTAL_DRVSTR_RESET 0x0 // 0

1791

#define XTAL_XTAL_SHORTXIN_MSB 14

1792

#define XTAL_XTAL_SHORTXIN_LSB 14

1793

#define XTAL_XTAL_SHORTXIN_MASK 0x00004000

1794

#define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB)

1795

#define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK)

1796

#define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0

1797

#define XTAL_XTAL_LOCALBIAS_MSB 13

1798

#define XTAL_XTAL_LOCALBIAS_LSB 13

1799

#define XTAL_XTAL_LOCALBIAS_MASK 0x00002000

1800

#define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB)

1801

#define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK)

1802

#define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1

1803

#define XTAL_XTAL_PWDCLKD_MSB 12

1804

#define XTAL_XTAL_PWDCLKD_LSB 12

1805

#define XTAL_XTAL_PWDCLKD_MASK 0x00001000

1806

#define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB)

1807

#define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK)

1808

#define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0

1809

#define XTAL_XTAL_BIAS2X_MSB 11

1810

#define XTAL_XTAL_BIAS2X_LSB 11

1811

#define XTAL_XTAL_BIAS2X_MASK 0x00000800

1812

#define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB)

1813

#define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK)

1814

#define XTAL_XTAL_BIAS2X_RESET 0x1 // 1

1815

#define XTAL_XTAL_LBIAS2X_MSB 10

1816

#define XTAL_XTAL_LBIAS2X_LSB 10

1817

#define XTAL_XTAL_LBIAS2X_MASK 0x00000400

1818

#define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB)

1819

#define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK)

1820

#define XTAL_XTAL_LBIAS2X_RESET 0x1 // 1

1821

#define XTAL_XTAL_ATBVREG_MSB 9

1822

#define XTAL_XTAL_ATBVREG_LSB 9

1823

#define XTAL_XTAL_ATBVREG_MASK 0x00000200

1824

#define XTAL_XTAL_ATBVREG_GET(x) (((x) & XTAL_XTAL_ATBVREG_MASK) >> XTAL_XTAL_ATBVREG_LSB)

1825

#define XTAL_XTAL_ATBVREG_SET(x) (((x) << XTAL_XTAL_ATBVREG_LSB) & XTAL_XTAL_ATBVREG_MASK)

1826

#define XTAL_XTAL_ATBVREG_RESET 0x0 // 0

1827

#define XTAL_XTAL_OSCON_MSB 8

1828

#define XTAL_XTAL_OSCON_LSB 8

1829

#define XTAL_XTAL_OSCON_MASK 0x00000100

1830

#define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB)

1831

#define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK)

1832

#define XTAL_XTAL_OSCON_RESET 0x1 // 1

1833

#define XTAL_XTAL_PWDCLKIN_MSB 7

1834

#define XTAL_XTAL_PWDCLKIN_LSB 7

1835

#define XTAL_XTAL_PWDCLKIN_MASK 0x00000080

1836

#define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB)

1837

#define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK)

1838

#define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0

1839

#define XTAL_LOCAL_XTAL_MSB 6

1840

#define XTAL_LOCAL_XTAL_LSB 6

1841

#define XTAL_LOCAL_XTAL_MASK 0x00000040

1842

#define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB)

1843

#define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK)

1844

#define XTAL_LOCAL_XTAL_RESET 0x0 // 0

1845

#define XTAL_PWD_SWREGCLK_MSB 5

1846

#define XTAL_PWD_SWREGCLK_LSB 5

1847

#define XTAL_PWD_SWREGCLK_MASK 0x00000020

1848

#define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB)

1849

#define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK)

1850

#define XTAL_PWD_SWREGCLK_RESET 0x0 // 0

1851

#define XTAL_SWREGCLK_EDGE_SEL_MSB 4

1852

#define XTAL_SWREGCLK_EDGE_SEL_LSB 4

1853

#define XTAL_SWREGCLK_EDGE_SEL_MASK 0x00000010

1854

#define XTAL_SWREGCLK_EDGE_SEL_GET(x) (((x) & XTAL_SWREGCLK_EDGE_SEL_MASK) >> XTAL_SWREGCLK_EDGE_SEL_LSB)

1855

#define XTAL_SWREGCLK_EDGE_SEL_SET(x) (((x) << XTAL_SWREGCLK_EDGE_SEL_LSB) & XTAL_SWREGCLK_EDGE_SEL_MASK)

1856

#define XTAL_SWREGCLK_EDGE_SEL_RESET 0x0 // 0

1857

#define XTAL_SPARE_MSB 3

1858

#define XTAL_SPARE_LSB 0

1859

#define XTAL_SPARE_MASK 0x0000000f

1860

#define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB)

1861

#define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK)

1862

#define XTAL_SPARE_RESET 0xf // 15

1863

#define XTAL_ADDRESS 0x18116290

1864

1865

#define RST_REVISION_ID_ADDRESS 0x18060090

1866

#define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000))

1867

1868

#define RST_BOOTSTRAP_BOOT_INTF_SEL_MSB 17

1869

#define RST_BOOTSTRAP_BOOT_INTF_SEL_LSB 16

1870

#define RST_BOOTSTRAP_BOOT_INTF_SEL_MASK 0x00030000

1871

#define RST_BOOTSTRAP_BOOT_INTF_SEL_GET(x) (((x) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK) >> RST_BOOTSTRAP_BOOT_INTF_SEL_LSB)

1872

#define RST_BOOTSTRAP_BOOT_INTF_SEL_SET(x) (((x) << RST_BOOTSTRAP_BOOT_INTF_SEL_LSB) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK)

1873

#define RST_BOOTSTRAP_BOOT_INTF_SEL_RESET 0x0 // 0

1874

#define RST_BOOTSTRAP_RES0_MSB 15

1875

#define RST_BOOTSTRAP_RES0_LSB 13

1876

#define RST_BOOTSTRAP_RES0_MASK 0x0000e000

1877

#define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)

1878

#define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)

1879

#define RST_BOOTSTRAP_RES0_RESET 0x0 // 0

1880

#define RST_BOOTSTRAP_SW_OPTION2_MSB 12

1881

#define RST_BOOTSTRAP_SW_OPTION2_LSB 12

1882

#define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000

1883

#define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)

1884

#define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)

1885

#define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0

1886

#define RST_BOOTSTRAP_SW_OPTION1_MSB 11

1887

#define RST_BOOTSTRAP_SW_OPTION1_LSB 11

1888

#define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800

1889

#define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)

1890

#define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)

1891

#define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0

1892

#define RST_BOOTSTRAP_TESTROM_DISABLE_MSB 10

1893

#define RST_BOOTSTRAP_TESTROM_DISABLE_LSB 10

1894

#define RST_BOOTSTRAP_TESTROM_DISABLE_MASK 0x00000400

1895

#define RST_BOOTSTRAP_TESTROM_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK) >> RST_BOOTSTRAP_TESTROM_DISABLE_LSB)

1896

#define RST_BOOTSTRAP_TESTROM_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_DISABLE_LSB) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK)

1897

#define RST_BOOTSTRAP_TESTROM_DISABLE_RESET 0x1 // 1

1898

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MSB 9

1899

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB 9

1900

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK 0x00000200

1901

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_GET(x) (((x) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK) >> RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB)

1902

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_SET(x) (((x) << RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK)

1903

#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_RESET 0x0 // 0

1904

#define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8

1905

#define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8

1906

#define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100

1907

#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)

1908

#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)

1909

#define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0

1910

#define RST_BOOTSTRAP_USB_MODE_MSB 7

1911

#define RST_BOOTSTRAP_USB_MODE_LSB 7

1912

#define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080

1913

#define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)

1914

#define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)

1915

#define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0

1916

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MSB 6

1917

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB 6

1918

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK 0x00000040

1919

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_GET(x) (((x) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK) >> RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB)

1920

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_SET(x) (((x) << RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)

1921

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_RESET 0x0 // 0

1922

#define RST_BOOTSTRAP_JTAG_MODE_MSB 5

1923

#define RST_BOOTSTRAP_JTAG_MODE_LSB 5

1924

#define RST_BOOTSTRAP_JTAG_MODE_MASK 0x00000020

1925

#define RST_BOOTSTRAP_JTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_JTAG_MODE_MASK) >> RST_BOOTSTRAP_JTAG_MODE_LSB)

1926

#define RST_BOOTSTRAP_JTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_JTAG_MODE_LSB) & RST_BOOTSTRAP_JTAG_MODE_MASK)

1927

#define RST_BOOTSTRAP_JTAG_MODE_RESET 0x1 // 1

1928

#define RST_BOOTSTRAP_REF_CLK_MSB 4

1929

#define RST_BOOTSTRAP_REF_CLK_LSB 4

1930

#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010

1931

#define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)

1932

#define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)

1933

#define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0

1934

#define RST_BOOTSTRAP_DDR_WIDTH_MSB 3

1935

#define RST_BOOTSTRAP_DDR_WIDTH_LSB 3

1936

#define RST_BOOTSTRAP_DDR_WIDTH_MASK 0x00000008

1937

#define RST_BOOTSTRAP_DDR_WIDTH_GET(x) (((x) & RST_BOOTSTRAP_DDR_WIDTH_MASK) >> RST_BOOTSTRAP_DDR_WIDTH_LSB)

1938

#define RST_BOOTSTRAP_DDR_WIDTH_SET(x) (((x) << RST_BOOTSTRAP_DDR_WIDTH_LSB) & RST_BOOTSTRAP_DDR_WIDTH_MASK)

1939

#define RST_BOOTSTRAP_DDR_WIDTH_RESET 0x0 // 0

1940

#define RST_BOOTSTRAP_BOOT_SELECT_MSB 2

1941

#define RST_BOOTSTRAP_BOOT_SELECT_LSB 2

1942

#define RST_BOOTSTRAP_BOOT_SELECT_MASK 0x00000004

1943

#define RST_BOOTSTRAP_BOOT_SELECT_GET(x) (((x) & RST_BOOTSTRAP_BOOT_SELECT_MASK) >> RST_BOOTSTRAP_BOOT_SELECT_LSB)

1944

#define RST_BOOTSTRAP_BOOT_SELECT_SET(x) (((x) << RST_BOOTSTRAP_BOOT_SELECT_LSB) & RST_BOOTSTRAP_BOOT_SELECT_MASK)

1945

#define RST_BOOTSTRAP_BOOT_SELECT_RESET 0x0 // 0

1946

#define RST_BOOTSTRAP_SDRAM_DISABLE_MSB 1

1947

#define RST_BOOTSTRAP_SDRAM_DISABLE_LSB 1

1948

#define RST_BOOTSTRAP_SDRAM_DISABLE_MASK 0x00000002

1949

#define RST_BOOTSTRAP_SDRAM_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK) >> RST_BOOTSTRAP_SDRAM_DISABLE_LSB)

1950

#define RST_BOOTSTRAP_SDRAM_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_DISABLE_LSB) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK)

1951

#define RST_BOOTSTRAP_SDRAM_DISABLE_RESET 0x0 // 0

1952

#define RST_BOOTSTRAP_DDR_SELECT_MSB 0

1953

#define RST_BOOTSTRAP_DDR_SELECT_LSB 0

1954

#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001

1955

#define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)

1956

#define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)

1957

#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0

1958

#define RST_BOOTSTRAP_ADDRESS 0x180600b0

1959

1960

#define GPIO_OE_ADDRESS 0x18040000

1961

#define GPIO_OUT_ADDRESS 0x18040008

1962

#define GPIO_SPARE_ADDRESS 0x18040028

1963

1964

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31

1965

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24

1966

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000

1967

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)

1968

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)

1969

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb // 11

1970

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23

1971

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16

1972

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000

1973

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)

1974

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)

1975

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa // 10

1976

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15

1977

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8

1978

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00

1979

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)

1980

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)

1981

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9

1982

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7

1983

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0

1984

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff

1985

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)

1986

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)

1987

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20

1988

#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030

1989

1990

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31

1991

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24

1992

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000

1993

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)

1994

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)

1995

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0

1996

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23

1997

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16

1998

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000

1999

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)

2000

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)

2001

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0

2002

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15

2003

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8

2004

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00

2005

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)

2006

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)

2007

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0

2008

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7

2009

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0

2010

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff

2011

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)

2012

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)

2013

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0

2014

#define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034

2015

2016

#define GPIO_IN_ENABLE0_UART_SIN_MSB 15

2017

#define GPIO_IN_ENABLE0_UART_SIN_LSB 8

2018

#define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00

2019

#define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)

2020

#define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)

2021

#define GPIO_IN_ENABLE0_UART_SIN_RESET 0x0 // 0

2022

#define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7

2023

#define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0

2024

#define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff

2025

#define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB)

2026

#define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK)

2027

#define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8

2028

#define GPIO_IN_ENABLE0_ADDRESS 0x18040044

2029

2030

2031

#define GPIO_IN_ENABLE3_MII_GE1_MDI_MSB 23

2032

#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16

2033

#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000

2034

#define GPIO_IN_ENABLE3_MII_GE1_MDI_GET(x) (((x) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) >> GPIO_IN_ENABLE3_MII_GE1_MDI_LSB)

2035

#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)

2036

#define GPIO_IN_ENABLE3_MII_GE1_MDI_RESET 0x80 // 128

2037

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MSB 15

2038

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB 8

2039

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK 0x0000ff00

2040

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_GET(x) (((x) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK) >> GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB)

2041

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_SET(x) (((x) << GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK)

2042

#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_RESET 0x80 // 128

2043

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_MSB 7

2044

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB 0

2045

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK 0x000000ff

2046

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_GET(x) (((x) & GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK) >> GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB)

2047

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_SET(x) (((x) << GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB) & GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK)

2048

#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_RESET 0x80 // 128

2049

#define GPIO_IN_ENABLE3_ADDRESS 0x18040050

2050

2051

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31

2052

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24

2053

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000

2054

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB)

2055

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK)

2056

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0

2057

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23

2058

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16

2059

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000

2060

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB)

2061

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK)

2062

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0

2063

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15

2064

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8

2065

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00

2066

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB)

2067

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK)

2068

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0

2069

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7

2070

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0

2071

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff

2072

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB)

2073

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK)

2074

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0

2075

#define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038

2076

2077

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MSB 31

2078

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24

2079

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000

2080

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB)

2081

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)

2082

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_RESET 0x0 // 0

2083

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MSB 23

2084

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB 16

2085

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK 0x00ff0000

2086

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB)

2087

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK)

2088

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_RESET 0x0 // 0

2089

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15

2090

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8

2091

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00

2092

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)

2093

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)

2094

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x0 // 0

2095

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7

2096

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0

2097

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff

2098

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)

2099

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)

2100

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0

2101

#define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c

2102

2103

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MSB 11

2104

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB 11

2105

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK 0x00000800

2106

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB)

2107

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK)

2108

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_RESET 0x0 // 0

2109

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MSB 10

2110

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB 10

2111

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK 0x00000400

2112

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB)

2113

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK)

2114

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_RESET 0x0 // 0

2115

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MSB 9

2116

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB 9

2117

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK 0x00000200

2118

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB)

2119

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK)

2120

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_RESET 0x0 // 0

2121

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8

2122

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8

2123

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100

2124

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB)

2125

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK)

2126

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0

2127

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7

2128

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7

2129

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080

2130

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB)

2131

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK)

2132

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x1 // 1

2133

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6

2134

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6

2135

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040

2136

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB)

2137

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK)

2138

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0

2139

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5

2140

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5

2141

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020

2142

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB)

2143

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK)

2144

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x0 // 0

2145

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4

2146

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4

2147

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010

2148

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB)

2149

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK)

2150

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0

2151

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3

2152

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3

2153

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008

2154

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB)

2155

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK)

2156

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0

2157

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2

2158

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2

2159

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004

2160

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB)

2161

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK)

2162

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0

2163

#define GPIO_FUNCTION_DISABLE_JTAG_MSB 1

2164

#define GPIO_FUNCTION_DISABLE_JTAG_LSB 1

2165

#define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002

2166

#define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB)

2167

#define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK)

2168

#define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0

2169

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0

2170

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0

2171

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001

2172

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB)

2173

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK)

2174

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0

2175

#define GPIO_FUNCTION_ADDRESS 0x1804006c

#define PCIE_RESET_EP_RESET_L_MSB 2

2180

#define PCIE_RESET_EP_RESET_L_LSB 2

2181

#define PCIE_RESET_EP_RESET_L_MASK 0x00000004

2182

#define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB)

2183

#define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK)

2184

#define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0

2185

#define PCIE_RESET_LINK_REQ_RESET_MSB 1

2186

#define PCIE_RESET_LINK_REQ_RESET_LSB 1

2187

#define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002

2188

#define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB)

2189

#define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK)

2190

#define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0

2191

#define PCIE_RESET_LINK_UP_MSB 0

2192

#define PCIE_RESET_LINK_UP_LSB 0

2193

#define PCIE_RESET_LINK_UP_MASK 0x00000001

2194

#define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB)

2195

#define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK)

2196

#define PCIE_RESET_LINK_UP_RESET 0x0 // 0

2197

#define PCIE_RESET_ADDRESS 0x180f0018

2198

2199

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MSB 2

2200

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB 2

2201

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK 0x00000004

2202

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_GET(x) (((x) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK) >> ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB)

2203

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_SET(x) (((x) << ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK)

2204

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_RESET 0x0 // 0

2205

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MSB 1

2206

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB 1

2207

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK 0x00000002

2208

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_GET(x) (((x) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK) >> ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB)

2209

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_SET(x) (((x) << ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK)

2210

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_RESET 0x0 // 0

2211

#define ETH_SGMII_SERDES_EN_PLL_MSB 0

2212

#define ETH_SGMII_SERDES_EN_PLL_LSB 0

2213

#define ETH_SGMII_SERDES_EN_PLL_MASK 0x00000001

2214

#define ETH_SGMII_SERDES_EN_PLL_GET(x) (((x) & ETH_SGMII_SERDES_EN_PLL_MASK) >> ETH_SGMII_SERDES_EN_PLL_LSB)

2215

#define ETH_SGMII_SERDES_EN_PLL_SET(x) (((x) << ETH_SGMII_SERDES_EN_PLL_LSB) & ETH_SGMII_SERDES_EN_PLL_MASK)

2216

#define ETH_SGMII_SERDES_EN_PLL_RESET 0x1 // 1

2217

#define ETH_SGMII_SERDES_ADDRESS 0x1805004c

2218

2219

2220

#define ETH_CFG_ETH_SPARE_MSB 31

2221

#define ETH_CFG_ETH_SPARE_LSB 22

2222

#define ETH_CFG_ETH_SPARE_MASK 0xffc00000

2223

#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)

2224

#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)

2225

#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0

2226

#define ETH_CFG_ETH_TXEN_DELAY_MSB 21

2227

#define ETH_CFG_ETH_TXEN_DELAY_LSB 20

2228

#define ETH_CFG_ETH_TXEN_DELAY_MASK 0x00300000

2229

#define ETH_CFG_ETH_TXEN_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB)

2230

#define ETH_CFG_ETH_TXEN_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK)

2231

#define ETH_CFG_ETH_TXEN_DELAY_RESET 0x0 // 0

2232

#define ETH_CFG_ETH_TXD_DELAY_MSB 19

2233

#define ETH_CFG_ETH_TXD_DELAY_LSB 18

2234

#define ETH_CFG_ETH_TXD_DELAY_MASK 0x000c0000

2235

#define ETH_CFG_ETH_TXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB)

2236

#define ETH_CFG_ETH_TXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK)

2237

#define ETH_CFG_ETH_TXD_DELAY_RESET 0x0 // 0

2238

#define ETH_CFG_ETH_RXDV_DELAY_MSB 17

2239

#define ETH_CFG_ETH_RXDV_DELAY_LSB 16

2240

#define ETH_CFG_ETH_RXDV_DELAY_MASK 0x00030000

2241

#define ETH_CFG_ETH_RXDV_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB)

2242

#define ETH_CFG_ETH_RXDV_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK)

2243

#define ETH_CFG_ETH_RXDV_DELAY_RESET 0x0 // 0

2244

#define ETH_CFG_ETH_RXD_DELAY_MSB 15

2245

#define ETH_CFG_ETH_RXD_DELAY_LSB 14

2246

#define ETH_CFG_ETH_RXD_DELAY_MASK 0x0000c000

2247

#define ETH_CFG_ETH_RXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB)

2248

#define ETH_CFG_ETH_RXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK)

2249

#define ETH_CFG_ETH_RXD_DELAY_RESET 0x0 // 0

2250

#define ETH_CFG_RMII_GE0_MASTER_MSB 12

2251

#define ETH_CFG_RMII_GE0_MASTER_LSB 12

2252

#define ETH_CFG_RMII_GE0_MASTER_MASK 0x00001000

2253

#define ETH_CFG_RMII_GE0_MASTER_GET(x) (((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB)

2254

#define ETH_CFG_RMII_GE0_MASTER_SET(x) (((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK)

2255

#define ETH_CFG_RMII_GE0_MASTER_RESET 0x1 // 1

2256

#define ETH_CFG_MII_CNTL_SPEED_MSB 11

2257

#define ETH_CFG_MII_CNTL_SPEED_LSB 11

2258

#define ETH_CFG_MII_CNTL_SPEED_MASK 0x00000800

2259

#define ETH_CFG_MII_CNTL_SPEED_GET(x) (((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB)

2260

#define ETH_CFG_MII_CNTL_SPEED_SET(x) (((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK)

2261

#define ETH_CFG_MII_CNTL_SPEED_RESET 0x0 // 0

2262

#define ETH_CFG_RMII_GE0_MSB 10

2263

#define ETH_CFG_RMII_GE0_LSB 10

2264

#define ETH_CFG_RMII_GE0_MASK 0x00000400

2265

#define ETH_CFG_RMII_GE0_GET(x) (((x) & ETH_CFG_RMII_GE0_MASK) >> ETH_CFG_RMII_GE0_LSB)

2266

#define ETH_CFG_RMII_GE0_SET(x) (((x) << ETH_CFG_RMII_GE0_LSB) & ETH_CFG_RMII_GE0_MASK)

2267

#define ETH_CFG_RMII_GE0_RESET 0x0 // 0

2268

#define ETH_CFG_GE0_SGMII_MSB 6

2269

#define ETH_CFG_GE0_SGMII_LSB 6

2270

#define ETH_CFG_GE0_SGMII_MASK 0x00000040

2271

#define ETH_CFG_GE0_SGMII_GET(x) (((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB)

2272

#define ETH_CFG_GE0_SGMII_SET(x) (((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK)

2273

#define ETH_CFG_GE0_SGMII_RESET 0x0 // 0

2274

#define ETH_CFG_GE0_ERR_EN_MSB 5

2275

#define ETH_CFG_GE0_ERR_EN_LSB 5

2276

#define ETH_CFG_GE0_ERR_EN_MASK 0x00000020

2277

#define ETH_CFG_GE0_ERR_EN_GET(x) (((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB)

2278

#define ETH_CFG_GE0_ERR_EN_SET(x) (((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK)

2279

#define ETH_CFG_GE0_ERR_EN_RESET 0x0 // 0

2280

#define ETH_CFG_MII_GE0_SLAVE_MSB 4

2281

#define ETH_CFG_MII_GE0_SLAVE_LSB 4

2282

#define ETH_CFG_MII_GE0_SLAVE_MASK 0x00000010

2283

#define ETH_CFG_MII_GE0_SLAVE_GET(x) (((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB)

2284

#define ETH_CFG_MII_GE0_SLAVE_SET(x) (((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK)

2285

#define ETH_CFG_MII_GE0_SLAVE_RESET 0x0 // 0

2286

#define ETH_CFG_MII_GE0_MASTER_MSB 3

2287

#define ETH_CFG_MII_GE0_MASTER_LSB 3

2288

#define ETH_CFG_MII_GE0_MASTER_MASK 0x00000008

2289

#define ETH_CFG_MII_GE0_MASTER_GET(x) (((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB)

2290

#define ETH_CFG_MII_GE0_MASTER_SET(x) (((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK)

2291

#define ETH_CFG_MII_GE0_MASTER_RESET 0x0 // 0

2292

#define ETH_CFG_GMII_GE0_MSB 2

2293

#define ETH_CFG_GMII_GE0_LSB 2

2294

#define ETH_CFG_GMII_GE0_MASK 0x00000004

2295

#define ETH_CFG_GMII_GE0_GET(x) (((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB)

2296

#define ETH_CFG_GMII_GE0_SET(x) (((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK)

2297

#define ETH_CFG_GMII_GE0_RESET 0x0 // 0

2298

#define ETH_CFG_MII_GE0_MSB 1

2299

#define ETH_CFG_MII_GE0_LSB 1

2300

#define ETH_CFG_MII_GE0_MASK 0x00000002

2301

#define ETH_CFG_MII_GE0_GET(x) (((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB)

2302

#define ETH_CFG_MII_GE0_SET(x) (((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK)

2303

#define ETH_CFG_MII_GE0_RESET 0x0 // 0

2304

#define ETH_CFG_RGMII_GE0_MSB 0

2305

#define ETH_CFG_RGMII_GE0_LSB 0

2306

#define ETH_CFG_RGMII_GE0_MASK 0x00000001

2307

#define ETH_CFG_RGMII_GE0_GET(x) (((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB)

2308

#define ETH_CFG_RGMII_GE0_SET(x) (((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK)

2309

#define ETH_CFG_RGMII_GE0_RESET 0x0 // 0

2310

#define ETH_CFG_ADDRESS 0x18070000

#define SGMII_SERDES_VCO_REG_MSB 30

2315

#define SGMII_SERDES_VCO_REG_LSB 27

2316

#define SGMII_SERDES_VCO_REG_MASK 0x78000000

2317

#define SGMII_SERDES_VCO_REG_GET(x) (((x) & SGMII_SERDES_VCO_REG_MASK) >> SGMII_SERDES_VCO_REG_LSB)

2318

#define SGMII_SERDES_VCO_REG_SET(x) (((x) << SGMII_SERDES_VCO_REG_LSB) & SGMII_SERDES_VCO_REG_MASK)

2319

#define SGMII_SERDES_VCO_REG_RESET 0x3 // 3

2320

#define SGMII_SERDES_RES_CALIBRATION_MSB 26

2321

#define SGMII_SERDES_RES_CALIBRATION_LSB 23

2322

#define SGMII_SERDES_RES_CALIBRATION_MASK 0x07800000

2323

#define SGMII_SERDES_RES_CALIBRATION_GET(x) (((x) & SGMII_SERDES_RES_CALIBRATION_MASK) >> SGMII_SERDES_RES_CALIBRATION_LSB)

2324

#define SGMII_SERDES_RES_CALIBRATION_SET(x) (((x) << SGMII_SERDES_RES_CALIBRATION_LSB) & SGMII_SERDES_RES_CALIBRATION_MASK)

2325

#define SGMII_SERDES_RES_CALIBRATION_RESET 0x0 // 0

2326

#define SGMII_SERDES_FIBER_MODE_MSB 21

2327

#define SGMII_SERDES_FIBER_MODE_LSB 20

2328

#define SGMII_SERDES_FIBER_MODE_MASK 0x00300000

2329

#define SGMII_SERDES_FIBER_MODE_GET(x) (((x) & SGMII_SERDES_FIBER_MODE_MASK) >> SGMII_SERDES_FIBER_MODE_LSB)

2330

#define SGMII_SERDES_FIBER_MODE_SET(x) (((x) << SGMII_SERDES_FIBER_MODE_LSB) & SGMII_SERDES_FIBER_MODE_MASK)

2331

#define SGMII_SERDES_FIBER_MODE_RESET 0x0 // 0

2332

#define SGMII_SERDES_THRESHOLD_CTRL_MSB 19

2333

#define SGMII_SERDES_THRESHOLD_CTRL_LSB 18

2334

#define SGMII_SERDES_THRESHOLD_CTRL_MASK 0x000c0000

2335

#define SGMII_SERDES_THRESHOLD_CTRL_GET(x) (((x) & SGMII_SERDES_THRESHOLD_CTRL_MASK) >> SGMII_SERDES_THRESHOLD_CTRL_LSB)

2336

#define SGMII_SERDES_THRESHOLD_CTRL_SET(x) (((x) << SGMII_SERDES_THRESHOLD_CTRL_LSB) & SGMII_SERDES_THRESHOLD_CTRL_MASK)

2337

#define SGMII_SERDES_THRESHOLD_CTRL_RESET 0x0 // 0

2338

#define SGMII_SERDES_FIBER_SDO_MSB 17

2339

#define SGMII_SERDES_FIBER_SDO_LSB 17

2340

#define SGMII_SERDES_FIBER_SDO_MASK 0x00020000

2341

#define SGMII_SERDES_FIBER_SDO_GET(x) (((x) & SGMII_SERDES_FIBER_SDO_MASK) >> SGMII_SERDES_FIBER_SDO_LSB)

2342

#define SGMII_SERDES_FIBER_SDO_SET(x) (((x) << SGMII_SERDES_FIBER_SDO_LSB) & SGMII_SERDES_FIBER_SDO_MASK)

2343

#define SGMII_SERDES_FIBER_SDO_RESET 0x0 // 0

2344

#define SGMII_SERDES_EN_SIGNAL_DETECT_MSB 16

2345

#define SGMII_SERDES_EN_SIGNAL_DETECT_LSB 16

2346

#define SGMII_SERDES_EN_SIGNAL_DETECT_MASK 0x00010000

2347

#define SGMII_SERDES_EN_SIGNAL_DETECT_GET(x) (((x) & SGMII_SERDES_EN_SIGNAL_DETECT_MASK) >> SGMII_SERDES_EN_SIGNAL_DETECT_LSB)

2348

#define SGMII_SERDES_EN_SIGNAL_DETECT_SET(x) (((x) << SGMII_SERDES_EN_SIGNAL_DETECT_LSB) & SGMII_SERDES_EN_SIGNAL_DETECT_MASK)

2349

#define SGMII_SERDES_EN_SIGNAL_DETECT_RESET 0x1 // 1

2350

#define SGMII_SERDES_LOCK_DETECT_STATUS_MSB 15

2351

#define SGMII_SERDES_LOCK_DETECT_STATUS_LSB 15

2352

#define SGMII_SERDES_LOCK_DETECT_STATUS_MASK 0x00008000

2353

#define SGMII_SERDES_LOCK_DETECT_STATUS_GET(x) (((x) & SGMII_SERDES_LOCK_DETECT_STATUS_MASK) >> SGMII_SERDES_LOCK_DETECT_STATUS_LSB)

2354

#define SGMII_SERDES_LOCK_DETECT_STATUS_SET(x) (((x) << SGMII_SERDES_LOCK_DETECT_STATUS_LSB) & SGMII_SERDES_LOCK_DETECT_STATUS_MASK)

2355

#define SGMII_SERDES_LOCK_DETECT_STATUS_RESET 0x0 // 0

2356

#define SGMII_SERDES_SPARE0_MSB 14

2357

#define SGMII_SERDES_SPARE0_LSB 11

2358

#define SGMII_SERDES_SPARE0_MASK 0x00007800

2359

#define SGMII_SERDES_SPARE0_GET(x) (((x) & SGMII_SERDES_SPARE0_MASK) >> SGMII_SERDES_SPARE0_LSB)

2360

#define SGMII_SERDES_SPARE0_SET(x) (((x) << SGMII_SERDES_SPARE0_LSB) & SGMII_SERDES_SPARE0_MASK)

2361

#define SGMII_SERDES_SPARE0_RESET 0x0 // 0

2362

#define SGMII_SERDES_VCO_SLOW_MSB 10

2363

#define SGMII_SERDES_VCO_SLOW_LSB 10

2364

#define SGMII_SERDES_VCO_SLOW_MASK 0x00000400

2365

#define SGMII_SERDES_VCO_SLOW_GET(x) (((x) & SGMII_SERDES_VCO_SLOW_MASK) >> SGMII_SERDES_VCO_SLOW_LSB)

2366

#define SGMII_SERDES_VCO_SLOW_SET(x) (((x) << SGMII_SERDES_VCO_SLOW_LSB) & SGMII_SERDES_VCO_SLOW_MASK)

2367

#define SGMII_SERDES_VCO_SLOW_RESET 0x0 // 0

2368

#define SGMII_SERDES_VCO_FAST_MSB 9

2369

#define SGMII_SERDES_VCO_FAST_LSB 9

2370

#define SGMII_SERDES_VCO_FAST_MASK 0x00000200

2371

#define SGMII_SERDES_VCO_FAST_GET(x) (((x) & SGMII_SERDES_VCO_FAST_MASK) >> SGMII_SERDES_VCO_FAST_LSB)

2372

#define SGMII_SERDES_VCO_FAST_SET(x) (((x) << SGMII_SERDES_VCO_FAST_LSB) & SGMII_SERDES_VCO_FAST_MASK)

2373

#define SGMII_SERDES_VCO_FAST_RESET 0x0 // 0

2374

#define SGMII_SERDES_PLL_BW_MSB 8

2375

#define SGMII_SERDES_PLL_BW_LSB 8

2376

#define SGMII_SERDES_PLL_BW_MASK 0x00000100

2377

#define SGMII_SERDES_PLL_BW_GET(x) (((x) & SGMII_SERDES_PLL_BW_MASK) >> SGMII_SERDES_PLL_BW_LSB)

2378

#define SGMII_SERDES_PLL_BW_SET(x) (((x) << SGMII_SERDES_PLL_BW_LSB) & SGMII_SERDES_PLL_BW_MASK)

2379

#define SGMII_SERDES_PLL_BW_RESET 0x1 // 1

2380

#define SGMII_SERDES_TX_IMPEDANCE_MSB 7

2381

#define SGMII_SERDES_TX_IMPEDANCE_LSB 7

2382

#define SGMII_SERDES_TX_IMPEDANCE_MASK 0x00000080

2383

#define SGMII_SERDES_TX_IMPEDANCE_GET(x) (((x) & SGMII_SERDES_TX_IMPEDANCE_MASK) >> SGMII_SERDES_TX_IMPEDANCE_LSB)

2384

#define SGMII_SERDES_TX_IMPEDANCE_SET(x) (((x) << SGMII_SERDES_TX_IMPEDANCE_LSB) & SGMII_SERDES_TX_IMPEDANCE_MASK)

2385

#define SGMII_SERDES_TX_IMPEDANCE_RESET 0x0 // 0

2386

#define SGMII_SERDES_TX_DR_CTRL_MSB 6

2387

#define SGMII_SERDES_TX_DR_CTRL_LSB 4

2388

#define SGMII_SERDES_TX_DR_CTRL_MASK 0x00000070

2389

#define SGMII_SERDES_TX_DR_CTRL_GET(x) (((x) & SGMII_SERDES_TX_DR_CTRL_MASK) >> SGMII_SERDES_TX_DR_CTRL_LSB)

2390

#define SGMII_SERDES_TX_DR_CTRL_SET(x) (((x) << SGMII_SERDES_TX_DR_CTRL_LSB) & SGMII_SERDES_TX_DR_CTRL_MASK)

2391

#define SGMII_SERDES_TX_DR_CTRL_RESET 0x1 // 1

2392

#define SGMII_SERDES_HALF_TX_MSB 3

2393

#define SGMII_SERDES_HALF_TX_LSB 3

2394

#define SGMII_SERDES_HALF_TX_MASK 0x00000008

2395

#define SGMII_SERDES_HALF_TX_GET(x) (((x) & SGMII_SERDES_HALF_TX_MASK) >> SGMII_SERDES_HALF_TX_LSB)

2396

#define SGMII_SERDES_HALF_TX_SET(x) (((x) << SGMII_SERDES_HALF_TX_LSB) & SGMII_SERDES_HALF_TX_MASK)

2397

#define SGMII_SERDES_HALF_TX_RESET 0x0 // 0

2398

#define SGMII_SERDES_CDR_BW_MSB 2

2399

#define SGMII_SERDES_CDR_BW_LSB 1

2400

#define SGMII_SERDES_CDR_BW_MASK 0x00000006

2401

#define SGMII_SERDES_CDR_BW_GET(x) (((x) & SGMII_SERDES_CDR_BW_MASK) >> SGMII_SERDES_CDR_BW_LSB)

2402

#define SGMII_SERDES_CDR_BW_SET(x) (((x) << SGMII_SERDES_CDR_BW_LSB) & SGMII_SERDES_CDR_BW_MASK)

2403

#define SGMII_SERDES_CDR_BW_RESET 0x3 // 3

2404

#define SGMII_SERDES_RX_IMPEDANCE_MSB 0

2405

#define SGMII_SERDES_RX_IMPEDANCE_LSB 0

2406

#define SGMII_SERDES_RX_IMPEDANCE_MASK 0x00000001

2407

#define SGMII_SERDES_RX_IMPEDANCE_GET(x) (((x) & SGMII_SERDES_RX_IMPEDANCE_MASK) >> SGMII_SERDES_RX_IMPEDANCE_LSB)

2408

#define SGMII_SERDES_RX_IMPEDANCE_SET(x) (((x) << SGMII_SERDES_RX_IMPEDANCE_LSB) & SGMII_SERDES_RX_IMPEDANCE_MASK)

2409

#define SGMII_SERDES_RX_IMPEDANCE_RESET 0x0 // 0

2410

#define SGMII_SERDES_ADDRESS 0x18070018

2411

2412

#define RST_RESET2_SPARE_MSB 31

2413

#define RST_RESET2_SPARE_LSB 19

2414

#define RST_RESET2_SPARE_MASK 0xfff80000

2415

#define RST_RESET2_SPARE_GET(x) (((x) & RST_RESET2_SPARE_MASK) >> RST_RESET2_SPARE_LSB)

2416

#define RST_RESET2_SPARE_SET(x) (((x) << RST_RESET2_SPARE_LSB) & RST_RESET2_SPARE_MASK)

2417

#define RST_RESET2_SPARE_RESET 0x0 // 0

2418

#define RST_RESET2_EP_MODE_MSB 18

2419

#define RST_RESET2_EP_MODE_LSB 18

2420

#define RST_RESET2_EP_MODE_MASK 0x00040000

2421

#define RST_RESET2_EP_MODE_GET(x) (((x) & RST_RESET2_EP_MODE_MASK) >> RST_RESET2_EP_MODE_LSB)

2422

#define RST_RESET2_EP_MODE_SET(x) (((x) << RST_RESET2_EP_MODE_LSB) & RST_RESET2_EP_MODE_MASK)

2423

#define RST_RESET2_EP_MODE_RESET 0x0 // 0

2424

#define RST_RESET2_USB2_EXT_PWR_SEQ_MSB 17

2425

#define RST_RESET2_USB2_EXT_PWR_SEQ_LSB 17

2426

#define RST_RESET2_USB2_EXT_PWR_SEQ_MASK 0x00020000

2427

#define RST_RESET2_USB2_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB2_EXT_PWR_SEQ_LSB)

2428

#define RST_RESET2_USB2_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET2_USB2_EXT_PWR_SEQ_LSB) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK)

2429

#define RST_RESET2_USB2_EXT_PWR_SEQ_RESET 0x1 // 1

2430

#define RST_RESET2_USB1_EXT_PWR_SEQ_MSB 16

2431

#define RST_RESET2_USB1_EXT_PWR_SEQ_LSB 16

2432

#define RST_RESET2_USB1_EXT_PWR_SEQ_MASK 0x00010000

2433

#define RST_RESET2_USB1_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB1_EXT_PWR_SEQ_LSB)

2434

#define RST_RESET2_USB1_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET2_USB1_EXT_PWR_SEQ_LSB) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK)

2435

#define RST_RESET2_USB1_EXT_PWR_SEQ_RESET 0x1 // 1

2436

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MSB 15

2437

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB 15

2438

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK 0x00008000

2439

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_GET(x) (((x) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK) >> RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB)

2440

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(x) (((x) << RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK)

2441

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_RESET 0x0 // 0

2442

#define RST_RESET2_USB_PHY2_ARESET_MSB 11

2443

#define RST_RESET2_USB_PHY2_ARESET_LSB 11

2444

#define RST_RESET2_USB_PHY2_ARESET_MASK 0x00000800

2445

#define RST_RESET2_USB_PHY2_ARESET_GET(x) (((x) & RST_RESET2_USB_PHY2_ARESET_MASK) >> RST_RESET2_USB_PHY2_ARESET_LSB)

2446

#define RST_RESET2_USB_PHY2_ARESET_SET(x) (((x) << RST_RESET2_USB_PHY2_ARESET_LSB) & RST_RESET2_USB_PHY2_ARESET_MASK)

2447

#define RST_RESET2_USB_PHY2_ARESET_RESET 0x1 // 1

2448

#define RST_RESET2_PCIE2_PHY_RESET_MSB 7

2449

#define RST_RESET2_PCIE2_PHY_RESET_LSB 7

2450

#define RST_RESET2_PCIE2_PHY_RESET_MASK 0x00000080

2451

#define RST_RESET2_PCIE2_PHY_RESET_GET(x) (((x) & RST_RESET2_PCIE2_PHY_RESET_MASK) >> RST_RESET2_PCIE2_PHY_RESET_LSB)

2452

#define RST_RESET2_PCIE2_PHY_RESET_SET(x) (((x) << RST_RESET2_PCIE2_PHY_RESET_LSB) & RST_RESET2_PCIE2_PHY_RESET_MASK)

2453

#define RST_RESET2_PCIE2_PHY_RESET_RESET 0x1 // 1

2454

#define RST_RESET2_PCIE2_RESET_MSB 6

2455

#define RST_RESET2_PCIE2_RESET_LSB 6

2456

#define RST_RESET2_PCIE2_RESET_MASK 0x00000040

2457

#define RST_RESET2_PCIE2_RESET_GET(x) (((x) & RST_RESET2_PCIE2_RESET_MASK) >> RST_RESET2_PCIE2_RESET_LSB)

2458

#define RST_RESET2_PCIE2_RESET_SET(x) (((x) << RST_RESET2_PCIE2_RESET_LSB) & RST_RESET2_PCIE2_RESET_MASK)

2459

#define RST_RESET2_PCIE2_RESET_RESET 0x1 // 1

2460

#define RST_RESET2_USB_HOST2_RESET_MSB 5

2461

#define RST_RESET2_USB_HOST2_RESET_LSB 5

2462

#define RST_RESET2_USB_HOST2_RESET_MASK 0x00000020

2463

#define RST_RESET2_USB_HOST2_RESET_GET(x) (((x) & RST_RESET2_USB_HOST2_RESET_MASK) >> RST_RESET2_USB_HOST2_RESET_LSB)

2464

#define RST_RESET2_USB_HOST2_RESET_SET(x) (((x) << RST_RESET2_USB_HOST2_RESET_LSB) & RST_RESET2_USB_HOST2_RESET_MASK)

2465

#define RST_RESET2_USB_HOST2_RESET_RESET 0x1 // 1

2466

#define RST_RESET2_USB_PHY2_RESET_MSB 4

2467

#define RST_RESET2_USB_PHY2_RESET_LSB 4

2468

#define RST_RESET2_USB_PHY2_RESET_MASK 0x00000010

2469

#define RST_RESET2_USB_PHY2_RESET_GET(x) (((x) & RST_RESET2_USB_PHY2_RESET_MASK) >> RST_RESET2_USB_PHY2_RESET_LSB)

2470

#define RST_RESET2_USB_PHY2_RESET_SET(x) (((x) << RST_RESET2_USB_PHY2_RESET_LSB) & RST_RESET2_USB_PHY2_RESET_MASK)

2471

#define RST_RESET2_USB_PHY2_RESET_RESET 0x1 // 1

2472

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MSB 3

2473

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB 3

2474

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK 0x00000008

2475

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK) >> RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB)

2476

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK)

2477

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_RESET 0x0 // 0

2478

#define RST_RESET2_USB2_MODE_MSB 0

2479

#define RST_RESET2_USB2_MODE_LSB 0

2480

#define RST_RESET2_USB2_MODE_MASK 0x00000001

2481

#define RST_RESET2_USB2_MODE_GET(x) (((x) & RST_RESET2_USB2_MODE_MASK) >> RST_RESET2_USB2_MODE_LSB)

2482

#define RST_RESET2_USB2_MODE_SET(x) (((x) << RST_RESET2_USB2_MODE_LSB) & RST_RESET2_USB2_MODE_MASK)

2483

#define RST_RESET2_USB2_MODE_RESET 0x1 // 1

2484

#define RST_RESET2_ADDRESS 0x180600c4

2485

2486

#define PCIE2_RESET_EP_RESET_L_MSB 2

2487

#define PCIE2_RESET_EP_RESET_L_LSB 2

2488

#define PCIE2_RESET_EP_RESET_L_MASK 0x00000004

2489

#define PCIE2_RESET_EP_RESET_L_GET(x) (((x) & PCIE2_RESET_EP_RESET_L_MASK) >> PCIE2_RESET_EP_RESET_L_LSB)

2490

#define PCIE2_RESET_EP_RESET_L_SET(x) (((x) << PCIE2_RESET_EP_RESET_L_LSB) & PCIE2_RESET_EP_RESET_L_MASK)

2491

#define PCIE2_RESET_EP_RESET_L_RESET 0x0 // 0

2492

#define PCIE2_RESET_LINK_REQ_RESET_MSB 1

2493

#define PCIE2_RESET_LINK_REQ_RESET_LSB 1

2494

#define PCIE2_RESET_LINK_REQ_RESET_MASK 0x00000002

2495

#define PCIE2_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE2_RESET_LINK_REQ_RESET_MASK) >> PCIE2_RESET_LINK_REQ_RESET_LSB)

2496

#define PCIE2_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE2_RESET_LINK_REQ_RESET_LSB) & PCIE2_RESET_LINK_REQ_RESET_MASK)

2497

#define PCIE2_RESET_LINK_REQ_RESET_RESET 0x0 // 0

2498

#define PCIE2_RESET_LINK_UP_MSB 0

2499

#define PCIE2_RESET_LINK_UP_LSB 0

2500

#define PCIE2_RESET_LINK_UP_MASK 0x00000001

2501

#define PCIE2_RESET_LINK_UP_GET(x) (((x) & PCIE2_RESET_LINK_UP_MASK) >> PCIE2_RESET_LINK_UP_LSB)

2502

#define PCIE2_RESET_LINK_UP_SET(x) (((x) << PCIE2_RESET_LINK_UP_LSB) & PCIE2_RESET_LINK_UP_MASK)

2503

#define PCIE2_RESET_LINK_UP_RESET 0x0 // 0

2504

#define PCIE2_RESET_ADDRESS 0x18280018

2505

2506

#define PCIE2_APP_CFG_TYPE_MSB 21

2507

#define PCIE2_APP_CFG_TYPE_LSB 20

2508

#define PCIE2_APP_CFG_TYPE_MASK 0x00300000

2509

#define PCIE2_APP_CFG_TYPE_GET(x) (((x) & PCIE2_APP_CFG_TYPE_MASK) >> PCIE2_APP_CFG_TYPE_LSB)

2510

#define PCIE2_APP_CFG_TYPE_SET(x) (((x) << PCIE2_APP_CFG_TYPE_LSB) & PCIE2_APP_CFG_TYPE_MASK)

2511

#define PCIE2_APP_CFG_TYPE_RESET 0x0 // 0

2512

#define PCIE2_APP_PCIE2_BAR_MSN_MSB 19

2513

#define PCIE2_APP_PCIE2_BAR_MSN_LSB 16

2514

#define PCIE2_APP_PCIE2_BAR_MSN_MASK 0x000f0000

2515

#define PCIE2_APP_PCIE2_BAR_MSN_GET(x) (((x) & PCIE2_APP_PCIE2_BAR_MSN_MASK) >> PCIE2_APP_PCIE2_BAR_MSN_LSB)

2516

#define PCIE2_APP_PCIE2_BAR_MSN_SET(x) (((x) << PCIE2_APP_PCIE2_BAR_MSN_LSB) & PCIE2_APP_PCIE2_BAR_MSN_MASK)

2517

#define PCIE2_APP_PCIE2_BAR_MSN_RESET 0x1 // 1

2518

#define PCIE2_APP_CFG_BE_MSB 15

2519

#define PCIE2_APP_CFG_BE_LSB 12

2520

#define PCIE2_APP_CFG_BE_MASK 0x0000f000

2521

#define PCIE2_APP_CFG_BE_GET(x) (((x) & PCIE2_APP_CFG_BE_MASK) >> PCIE2_APP_CFG_BE_LSB)

2522

#define PCIE2_APP_CFG_BE_SET(x) (((x) << PCIE2_APP_CFG_BE_LSB) & PCIE2_APP_CFG_BE_MASK)

2523

#define PCIE2_APP_CFG_BE_RESET 0xf // 15

2524

#define PCIE2_APP_SLV_RESP_ERR_MAP_MSB 11

2525

#define PCIE2_APP_SLV_RESP_ERR_MAP_LSB 6

2526

#define PCIE2_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0

2527

#define PCIE2_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE2_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE2_APP_SLV_RESP_ERR_MAP_LSB)

2528

#define PCIE2_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE2_APP_SLV_RESP_ERR_MAP_LSB) & PCIE2_APP_SLV_RESP_ERR_MAP_MASK)

2529

#define PCIE2_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63

2530

#define PCIE2_APP_MSTR_RESP_ERR_MAP_MSB 5

2531

#define PCIE2_APP_MSTR_RESP_ERR_MAP_LSB 4

2532

#define PCIE2_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030

2533

#define PCIE2_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE2_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE2_APP_MSTR_RESP_ERR_MAP_LSB)

2534

#define PCIE2_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE2_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE2_APP_MSTR_RESP_ERR_MAP_MASK)

2535

#define PCIE2_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0

2536

#define PCIE2_APP_INIT_RST_MSB 3

2537

#define PCIE2_APP_INIT_RST_LSB 3

2538

#define PCIE2_APP_INIT_RST_MASK 0x00000008

2539

#define PCIE2_APP_INIT_RST_GET(x) (((x) & PCIE2_APP_INIT_RST_MASK) >> PCIE2_APP_INIT_RST_LSB)

2540

#define PCIE2_APP_INIT_RST_SET(x) (((x) << PCIE2_APP_INIT_RST_LSB) & PCIE2_APP_INIT_RST_MASK)

2541

#define PCIE2_APP_INIT_RST_RESET 0x0 // 0

2542

#define PCIE2_APP_PM_XMT_TURNOFF_MSB 2

2543

#define PCIE2_APP_PM_XMT_TURNOFF_LSB 2

2544

#define PCIE2_APP_PM_XMT_TURNOFF_MASK 0x00000004

2545

#define PCIE2_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE2_APP_PM_XMT_TURNOFF_MASK) >> PCIE2_APP_PM_XMT_TURNOFF_LSB)

2546

#define PCIE2_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE2_APP_PM_XMT_TURNOFF_LSB) & PCIE2_APP_PM_XMT_TURNOFF_MASK)

2547

#define PCIE2_APP_PM_XMT_TURNOFF_RESET 0x0 // 0

2548

#define PCIE2_APP_UNLOCK_MSG_MSB 1

2549

#define PCIE2_APP_UNLOCK_MSG_LSB 1

2550

#define PCIE2_APP_UNLOCK_MSG_MASK 0x00000002

2551

#define PCIE2_APP_UNLOCK_MSG_GET(x) (((x) & PCIE2_APP_UNLOCK_MSG_MASK) >> PCIE2_APP_UNLOCK_MSG_LSB)

2552

#define PCIE2_APP_UNLOCK_MSG_SET(x) (((x) << PCIE2_APP_UNLOCK_MSG_LSB) & PCIE2_APP_UNLOCK_MSG_MASK)

2553

#define PCIE2_APP_UNLOCK_MSG_RESET 0x0 // 0

2554

#define PCIE2_APP_LTSSM_ENABLE_MSB 0

2555

#define PCIE2_APP_LTSSM_ENABLE_LSB 0

2556

#define PCIE2_APP_LTSSM_ENABLE_MASK 0x00000001

2557

#define PCIE2_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE2_APP_LTSSM_ENABLE_MASK) >> PCIE2_APP_LTSSM_ENABLE_LSB)

2558

#define PCIE2_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE2_APP_LTSSM_ENABLE_LSB) & PCIE2_APP_LTSSM_ENABLE_MASK)

2559

#define PCIE2_APP_LTSSM_ENABLE_RESET 0x0 // 0

2560

#define PCIE2_APP_ADDRESS 0x18280000

//#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ /*Moved to qca955x board config*/

2566

2567

//#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */ /*Moved to qca955x board config*/

2568

2569

//#define CONFIG_BAUDRATE 115200 /*Moved to qca955x board config*/

2570

//#define CFG_BAUDRATE_TABLE {115200} /*Moved to qca955x board config*/

2571

2572

//#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /*Moved to qca955x board config*/

2573

2574

#define CONFIG_ROOTFS_RD

2575

2576

#define CONFIG_BOOTARGS_RD "console=ttyS0,115200 root=01:00 rd_start=0x802d0000 rd_size=5242880 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),4096k(rootfs),2048k(uImage)"

2577

2578

/* XXX - putting rootfs in last partition results in jffs errors */

2579

#define CONFIG_BOOTARGS_FL "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),2048k(uImage)"

2580

2581

#ifdef CONFIG_ROOTFS_FLASH

2582

#define CONFIG_BOOTARGS CONFIG_BOOTARGS_FL

2583

#else

2584

#define CONFIG_BOOTARGS ""

#endif

/*

* Miscellaneous configurable options

2589

*/

2590

#define CFG_LONGHELP /* undef to save memory */

2591

#define CFG_PROMPT "ath> " /* Monitor Command Prompt */

2592

#define CFG_CBSIZE 512 /* Console I/O Buffer Size */

2593

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

2594

#define CFG_MAXARGS 16 /* max number of command args*/

2595

2596

//#define CFG_MALLOC_LEN (128*1024) /*Moved to qca955x board config*/

2597

2598

#define CFG_BOOTPARAMS_LEN (128*1024)

2599

2600

//#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ /*Moved to qca955x board config */

2601

//#define CFG_SDRAM_BASE 0xa0000000 /* Cached addr */

2602

2603

//#define CFG_LOAD_ADDR 0x81000000 /* default load address */ /* Moved to qca955x board config */

2604

//#define CFG_LOAD_ADDR 0xa1000000 /* default load address */

2605

2606

#define CFG_MEMTEST_START 0x80100000

2607

#undef CFG_MEMTEST_START

2608

#define CFG_MEMTEST_START 0x80200000

2609

#define CFG_MEMTEST_END 0x83800000

2610

2611

/*------------------------------------------------------------------------

2612

* * * JFFS2

2613

*/

2614

#define CFG_JFFS_CUSTOM_PART /* board defined part */

2615

#define CONFIG_JFFS2_CMDLINE

2616

#define MTDIDS_DEFAULT "nor0=ath-nor0"

2617

2618

#define CONFIG_MEMSIZE_IN_BYTES

2619

2620

//#define CFG_RX_ETH_BUFFER 16 /* Moved to qca955x board config */

2621

2622

2623

/*-----------------------------------------------------------------------

2624

* Cache Configuration

2625

*/

2626

//#define CFG_DCACHE_SIZE 32768 /* Moved to qca955x board config */

2627

//#define CFG_ICACHE_SIZE 65536 /* Moved to qca955x board config */

2628

//#define CFG_CACHELINE_SIZE 32 /* Moved to qca955x board config */

/*

* Address map

*/

#define ATH_PCI_MEM_BASE 0x10000000 /* 128M */

2634

#define ATH_APB_BASE 0x18000000 /* 384M */

2635

#define ATH_GE0_BASE 0x19000000 /* 16M */

2636

#define ATH_GE1_BASE 0x1a000000 /* 16M */

2637

#define ATH_USB_OHCI_BASE 0x1b000000

2638

#define ATH_USB_EHCI_BASE 0x1b000000

2639

#define ATH_USB_EHCI_BASE_1 0x1b000000

2640

#define ATH_USB_EHCI_BASE_2 0x1b400000

2641

#define ATH_SPI_BASE 0x1f000000

2642

2643

/*

2644

* Added the PCI LCL RESET register from u-boot

2645

* ath_soc.h so that we can query the PCI LCL RESET

2646

* register for the presence of WLAN H/W.

2647

*/

2648

#define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x000f0000)

2649

#define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00)

2650

#define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18)

/*

* APB block

*/

#define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000

2656

#define ATH_CPU_BASE ATH_APB_BASE+0x00010000

2657

#define ATH_UART_BASE ATH_APB_BASE+0x00020000

2658

#define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000

2659

#define ATH_GPIO_BASE ATH_APB_BASE+0x00040000

2660

#define ATH_PLL_BASE ATH_APB_BASE+0x00050000

2661

#define ATH_RESET_BASE ATH_APB_BASE+0x00060000

2662

#define ATH_DMA_BASE ATH_APB_BASE+0x000A0000

2663

#define ATH_SLIC_BASE ATH_APB_BASE+0x000A9000

2664

#define ATH_STEREO_BASE ATH_APB_BASE+0x000B0000

2665

#define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x000F0000

2666

#define ATH_OTP_BASE ATH_APB_BASE+0x00130000

2667

#define ATH_NAND_FLASH_BASE 0x1b800000u

/*

* DDR Config values

*/

#define ATH_DDR_CONFIG_16BIT (1 << 31)

2674

#define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30)

2675

#define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27

2676

#define ATH_DDR_CONFIG_TMRD_SHIFT 23

2677

#define ATH_DDR_CONFIG_TRFC_SHIFT 17

2678

#define ATH_DDR_CONFIG_TRRD_SHIFT 13

2679

#define ATH_DDR_CONFIG_TRP_SHIFT 9

2680

#define ATH_DDR_CONFIG_TRCD_SHIFT 5

2681

#define ATH_DDR_CONFIG_TRAS_SHIFT 0

2682

2683

#define ATH_DDR_CONFIG2_BL2 (2 << 0)

2684

#define ATH_DDR_CONFIG2_BL4 (4 << 0)

2685

#define ATH_DDR_CONFIG2_BL8 (8 << 0)

2686

2687

#define ATH_DDR_CONFIG2_BT_IL (1 << 4)

2688

#define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5)

2689

#define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6)

2690

#define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7)

2691

#define ATH_DDR_CONFIG2_TWR_SHIFT 8

2692

#define ATH_DDR_CONFIG2_TRTW_SHIFT 12

2693

#define ATH_DDR_CONFIG2_TRTP_SHIFT 17

2694

#define ATH_DDR_CONFIG2_TWTR_SHIFT 21

2695

#define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31)

2696

2697

#define ATH_DDR_TAP_DEFAULT 0x18

2698

2699

/*

2700

* DDR block, gmac flushing

2701

*/

2702

#define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c

2703

#define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0

2704

#define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4

2705

#define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0x88

2706

2707

#define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000

2708

#define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006

/*

* PLL block/CPU

*/

#define ATH_PLL_CONFIG ATH_PLL_BASE+0x0

2715

#define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x8

2716

2717

2718

#define PLL_DIV_SHIFT 0

2719

#define PLL_DIV_MASK 0x3ff

2720

#define REF_DIV_SHIFT 10

2721

#define REF_DIV_MASK 0xf

2722

#define AHB_DIV_SHIFT 19

2723

#define AHB_DIV_MASK 0x1

2724

#define DDR_DIV_SHIFT 22

2725

#define DDR_DIV_MASK 0x1

2726

#define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x4

2727

#define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x2c

2728

#define ATH_AUDIO_PLL_CONFIG ATH_PLL_BASE+0x30

2729

2730

#define ATH_ETH_INT0_CLK ATH_PLL_BASE+0x14

2731

#define ATH_ETH_INT1_CLK ATH_PLL_BASE+0x18

/*

* USB block

*/

#define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE

2738

#define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4

2739

#define ATH_USB_WINDOW 0x10000

2740

#define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8

/*

* PCI block

*/

#define ATH_PCI_WINDOW 0x8000000 /* 128MB */

2746

#define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c

2747

#define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80

2748

#define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84

2749

#define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88

2750

#define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c

2751

#define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90

2752

#define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94

2753

#define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98

2754

2755

#define ATH_PCI_WINDOW0_VAL 0x10000000

2756

#define ATH_PCI_WINDOW1_VAL 0x11000000

2757

#define ATH_PCI_WINDOW2_VAL 0x12000000

2758

#define ATH_PCI_WINDOW3_VAL 0x13000000

2759

#define ATH_PCI_WINDOW4_VAL 0x14000000

2760

#define ATH_PCI_WINDOW5_VAL 0x15000000

2761

#define ATH_PCI_WINDOW6_VAL 0x16000000

2762

#define ATH_PCI_WINDOW7_VAL 0x07000000

2763

2764

#define ath_write_pci_window(_no) \

2765

ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL);

2766

2767

/*

2768

* CRP. To access the host controller config and status registers

2769

*/

2770

#define ATH_PCI_CRP 0x180c0000

2771

#define ATH_PCI_DEV_CFGBASE 0x14000000

2772

#define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP

2773

#define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4

2774

#define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8

2775

#define ATH_PCI_ERROR ATH_PCI_CRP+0x1c

2776

#define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20

2777

#define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24

2778

#define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28

2779

2780

#define ATH_CRP_CMD_WRITE 0x00010000

2781

#define ATH_CRP_CMD_READ 0x00000000

2782

2783

/*

2784

* PCI CFG. To generate config cycles

2785

*/

2786

#define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc

2787

#define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10

2788

#define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14

2789

#define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18

2790

#define ATH_CFG_CMD_READ 0x0000000a

2791

#define ATH_CFG_CMD_WRITE 0x0000000b

2792

2793

#define ATH_PCI_IDSEL_ADLINE_START 17

2794

2795

#define ATH_SPI_FS (ATH_SPI_BASE+0x00)

2796

#define ATH_SPI_READ (ATH_SPI_BASE+0x00)

2797

#define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04)

2798

#define ATH_SPI_WRITE (ATH_SPI_BASE+0x08)

2799

#define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c)

2800

#define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10)

2801

#define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14)

2802

#define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18)

2803

#define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */

2804

#define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */

2805

2806

#define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */

2807

#define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */

2808

#define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */

2809

#define ATH_SPI_CS_DIS 0x70000

2810

#define ATH_SPI_CE_LOW 0x60000

2811

#define ATH_SPI_CE_HIGH 0x60100

2812

2813

#define ATH_SPI_SECTOR_SIZE (1024*64)

2814

#define ATH_SPI_PAGE_SIZE 256

2815

2816

#define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1)

2817

#define ATH_RESET_GE0_PHY (0) // Nothing similar to wasp??

2818

#define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1)

2819

#define ATH_RESET_GE1_PHY (0) // Nothing similar to wasp??

2820

#define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1)

2821

#define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1)

/*

* SOC

*/

#define ATH_SPI_CMD_WRITE_SR 0x01

2827

#define ATH_SPI_CMD_WREN 0x06

2828

#define ATH_SPI_CMD_RD_STATUS 0x05

2829

#define ATH_SPI_CMD_FAST_READ 0x0b

2830

#define ATH_SPI_CMD_PAGE_PROG 0x02

2831

#define ATH_SPI_CMD_SECTOR_ERASE 0xd8

2832

#define ATH_SPI_CMD_CHIP_ERASE 0xc7

2833

#define ATH_SPI_CMD_RDID 0x9f

2834

2835

#if defined(CFG_ATH_EMULATION)

2836

2837

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(2) // 80 MHz

2838

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(1) // 40 MHz

2839

2840

#elif (CFG_PLL_FREQ == CFG_PLL_720_600_200)

2841

2842

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

2843

2844

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18)

2845

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

2846

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

2847

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

2848

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

2849

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

2850

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

2851

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

2852

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

2853

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2854

2855

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15)

2856

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

2857

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

2858

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

2859

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

2860

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

2861

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

2862

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

2863

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

2864

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2865

2866

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)

2867

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)

2868

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

2869

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

2870

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

2871

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

2872

2873

#elif (CFG_PLL_FREQ == CFG_PLL_720_600_300)

2874

2875

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

2876

2877

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18)

2878

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

2879

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

2880

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

2881

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

2882

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

2883

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

2884

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

2885

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

2886

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2887

2888

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15)

2889

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

2890

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

2891

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

2892

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

2893

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

2894

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

2895

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

2896

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

2897

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2898

2899

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)

2900

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)

2901

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

2902

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

2903

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

2904

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

2905

2906

#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200)

2907

2908

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

2909

2910

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(10)

2911

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

2912

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

2913

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

2914

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

2915

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

2916

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

2917

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

2918

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

2919

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2920

2921

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(10)

2922

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

2923

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

2924

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

2925

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

2926

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

2927

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

2928

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

2929

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

2930

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2931

2932

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)

2933

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)

2934

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

2935

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

2936

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

2937

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

2938

2939

#elif (CFG_PLL_FREQ == CFG_PLL_720_680_240)

2940

2941

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

2942

2943

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18)

2944

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

2945

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

2946

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

2947

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

2948

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

2949

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

2950

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

2951

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

2952

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2953

2954

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17)

2955

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

2956

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

2957

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

2958

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

2959

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

2960

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

2961

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

2962

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

2963

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2964

2965

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)

2966

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

2967

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

2968

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

2969

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

2970

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

2971

2972

#elif (CFG_PLL_FREQ == CFG_PLL_720_600_240)

2973

2974

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

2975

2976

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18)

2977

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

2978

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

2979

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

2980

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

2981

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

2982

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

2983

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

2984

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

2985

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2986

2987

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15)

2988

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

2989

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

2990

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

2991

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

2992

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

2993

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

2994

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

2995

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

2996

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

2997

2998

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)

2999

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3000

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3001

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3002

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3003

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3004

3005

#elif (CFG_PLL_FREQ == CFG_PLL_560_450_220)

3006

3007

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3008

3009

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(14)

3010

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

3011

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

3012

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3013

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3014

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

3015

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

3016

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

3017

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

3018

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

3019

3020

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(11)

3021

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

3022

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

3023

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3024

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3025

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

3026

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

3027

DDR_PLL_DITHER_NFRAC_MIN_SET(0x100) | \

3028

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

3029

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

3030

3031

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1)

3032

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)

3033

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3034

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3035

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3036

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3037

3038

#elif (CFG_PLL_FREQ == CFG_PLL_680_680_226)

3039

3040

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1)

3041

3042

#define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(17)

3043

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1)

3044

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1)

3045

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3046

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3047

#define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \

3048

CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \

3049

CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \

3050

CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \

3051

CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf)

3052

3053

#define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17)

3054

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1)

3055

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1)

3056

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3057

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3058

#define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \

3059

DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \

3060

DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \

3061

DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \

3062

DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf)

3063

3064

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2)

3065

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1)

3066

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(1)

3067

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3068

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3069

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3070

3071

#else

3072

# error "CFG_PLL_FREQ not set"

3073

#endif // CFG_PLL_FREQ

3074

3075

#if CPU_AND_DDR_CLK_FROM_DDR && CPU_AND_DDR_CLK_FROM_CPU

3076

# error "Incorrect settings. Both 'from CPU' and 'from DDR' set"

#endif

#define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000)

3082

#define __cpu_hz_40(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 40))

3083

#define __cpu_hz_25(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 25))

3084

3085

/* Since the count is incremented every other tick, divide by 2 */

3086

#define CFG_HZ (__cpu_hz_40(CPU_PLL_CONFIG_NINT_VAL) / 2)

/* SGMII DEFINES */

// 32'h18070034 (SGMII_CONFIG)

3091

#define SGMII_CONFIG_BERT_ENABLE_MSB 14

3092

#define SGMII_CONFIG_BERT_ENABLE_LSB 14

3093

#define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000

3094

#define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB)

3095

#define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK)

3096

#define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0

3097

#define SGMII_CONFIG_PRBS_ENABLE_MSB 13

3098

#define SGMII_CONFIG_PRBS_ENABLE_LSB 13

3099

#define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000

3100

#define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB)

3101

#define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK)

3102

#define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0

3103

#define SGMII_CONFIG_MDIO_COMPLETE_MSB 12

3104

#define SGMII_CONFIG_MDIO_COMPLETE_LSB 12

3105

#define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000

3106

#define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB)

3107

#define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK)

3108

#define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0

3109

#define SGMII_CONFIG_MDIO_PULSE_MSB 11

3110

#define SGMII_CONFIG_MDIO_PULSE_LSB 11

3111

#define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800

3112

#define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB)

3113

#define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK)

3114

#define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0

3115

#define SGMII_CONFIG_MDIO_ENABLE_MSB 10

3116

#define SGMII_CONFIG_MDIO_ENABLE_LSB 10

3117

#define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400

3118

#define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB)

3119

#define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK)

3120

#define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0

3121

#define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9

3122

#define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9

3123

#define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200

3124

#define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB)

3125

#define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK)

3126

#define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0

3127

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8

3128

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8

3129

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100

3130

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB)

3131

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK)

3132

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0

3133

#define SGMII_CONFIG_SPEED_MSB 7

3134

#define SGMII_CONFIG_SPEED_LSB 6

3135

#define SGMII_CONFIG_SPEED_MASK 0x000000c0

3136

#define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB)

3137

#define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK)

3138

#define SGMII_CONFIG_SPEED_RESET 0x0 // 0

3139

#define SGMII_CONFIG_FORCE_SPEED_MSB 5

3140

#define SGMII_CONFIG_FORCE_SPEED_LSB 5

3141

#define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020

3142

#define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB)

3143

#define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK)

3144

#define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0

3145

#define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4

3146

#define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4

3147

#define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010

3148

#define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB)

3149

#define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK)

3150

#define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0

3151

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3

3152

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3

3153

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008

3154

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB)

3155

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK)

3156

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0

3157

#define SGMII_CONFIG_MODE_CTRL_MSB 2

3158

#define SGMII_CONFIG_MODE_CTRL_LSB 0

3159

#define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007

3160

#define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB)

3161

#define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK)

3162

#define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0

3163

#define SGMII_CONFIG_ADDRESS 0x18070034

// 32'h1807001c (MR_AN_CONTROL)

3168

#define MR_AN_CONTROL_PHY_RESET_MSB 15

3169

#define MR_AN_CONTROL_PHY_RESET_LSB 15

3170

#define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000

3171

#define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB)

3172

#define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK)

3173

#define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0

3174

#define MR_AN_CONTROL_LOOPBACK_MSB 14

3175

#define MR_AN_CONTROL_LOOPBACK_LSB 14

3176

#define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000

3177

#define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB)

3178

#define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK)

3179

#define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0

3180

#define MR_AN_CONTROL_SPEED_SEL0_MSB 13

3181

#define MR_AN_CONTROL_SPEED_SEL0_LSB 13

3182

#define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000

3183

#define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB)

3184

#define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK)

3185

#define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0

3186

#define MR_AN_CONTROL_AN_ENABLE_MSB 12

3187

#define MR_AN_CONTROL_AN_ENABLE_LSB 12

3188

#define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000

3189

#define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB)

3190

#define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK)

3191

#define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1

3192

#define MR_AN_CONTROL_POWER_DOWN_MSB 11

3193

#define MR_AN_CONTROL_POWER_DOWN_LSB 11

3194

#define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800

3195

#define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB)

3196

#define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK)

3197

#define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0

3198

#define MR_AN_CONTROL_RESTART_AN_MSB 9

3199

#define MR_AN_CONTROL_RESTART_AN_LSB 9

3200

#define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200

3201

#define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB)

3202

#define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK)

3203

#define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0

3204

#define MR_AN_CONTROL_DUPLEX_MODE_MSB 8

3205

#define MR_AN_CONTROL_DUPLEX_MODE_LSB 8

3206

#define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100

3207

#define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB)

3208

#define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK)

3209

#define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1

3210

#define MR_AN_CONTROL_SPEED_SEL1_MSB 6

3211

#define MR_AN_CONTROL_SPEED_SEL1_LSB 6

3212

#define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040

3213

#define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB)

3214

#define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK)

3215

#define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1

3216

#define MR_AN_CONTROL_ADDRESS 0x1807001c

// 32'h18070014 (SGMII_RESET)

3223

#define SGMII_RESET_HW_RX_125M_N_MSB 4

3224

#define SGMII_RESET_HW_RX_125M_N_LSB 4

3225

#define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010

3226

#define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB)

3227

#define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK)

3228

#define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0

3229

#define SGMII_RESET_TX_125M_N_MSB 3

3230

#define SGMII_RESET_TX_125M_N_LSB 3

3231

#define SGMII_RESET_TX_125M_N_MASK 0x00000008

3232

#define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB)

3233

#define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK)

3234

#define SGMII_RESET_TX_125M_N_RESET 0x0 // 0

3235

#define SGMII_RESET_RX_125M_N_MSB 2

3236

#define SGMII_RESET_RX_125M_N_LSB 2

3237

#define SGMII_RESET_RX_125M_N_MASK 0x00000004

3238

#define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB)

3239

#define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK)

3240

#define SGMII_RESET_RX_125M_N_RESET 0x0 // 0

3241

#define SGMII_RESET_TX_CLK_N_MSB 1

3242

#define SGMII_RESET_TX_CLK_N_LSB 1

3243

#define SGMII_RESET_TX_CLK_N_MASK 0x00000002

3244

#define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB)

3245

#define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK)

3246

#define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0

3247

#define SGMII_RESET_RX_CLK_N_MSB 0

3248

#define SGMII_RESET_RX_CLK_N_LSB 0

3249

#define SGMII_RESET_RX_CLK_N_MASK 0x00000001

3250

#define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB)

3251

#define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK)

3252

#define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0

3253

#define SGMII_RESET_ADDRESS 0x18070014

// 32'h18070038 (SGMII_MAC_RX_CONFIG)

3258

#define SGMII_MAC_RX_CONFIG_LINK_MSB 15

3259

#define SGMII_MAC_RX_CONFIG_LINK_LSB 15

3260

#define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000

3261

#define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB)

3262

#define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK)

3263

#define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0

3264

#define SGMII_MAC_RX_CONFIG_ACK_MSB 14

3265

#define SGMII_MAC_RX_CONFIG_ACK_LSB 14

3266

#define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000

3267

#define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB)

3268

#define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK)

3269

#define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0

3270

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12

3271

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12

3272

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000

3273

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB)

3274

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK)

3275

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0

3276

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11

3277

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10

3278

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00

3279

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB)

3280

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK)

3281

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0

3282

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8

3283

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8

3284

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100

3285

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB)

3286

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK)

3287

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0

3288

#define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7

3289

#define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7

3290

#define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080

3291

#define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB)

3292

#define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK)

3293

#define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0

3294

#define SGMII_MAC_RX_CONFIG_RES0_MSB 0

3295

#define SGMII_MAC_RX_CONFIG_RES0_LSB 0

3296

#define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001

3297

#define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB)

3298

#define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK)

3299

#define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1

3300

#define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038

3301

3302

// 32'h18070058 (SGMII_DEBUG)

3303

#define SGMII_DEBUG_ARB_STATE_MSB 27

3304

#define SGMII_DEBUG_ARB_STATE_LSB 24

3305

#define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000

3306

#define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB)

3307

#define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK)

3308

#define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0

3309

#define SGMII_DEBUG_RX_SYNC_STATE_MSB 23

3310

#define SGMII_DEBUG_RX_SYNC_STATE_LSB 16

3311

#define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000

3312

#define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB)

3313

#define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK)

3314

#define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0

3315

#define SGMII_DEBUG_RX_STATE_MSB 15

3316

#define SGMII_DEBUG_RX_STATE_LSB 8

3317

#define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00

3318

#define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB)

3319

#define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK)

3320

#define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0

3321

#define SGMII_DEBUG_TX_STATE_MSB 7

3322

#define SGMII_DEBUG_TX_STATE_LSB 0

3323

#define SGMII_DEBUG_TX_STATE_MASK 0x000000ff

3324

#define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB)

3325

#define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK)

3326

#define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0

3327

#define SGMII_DEBUG_ADDRESS 0x18070058

3328

#define SGMII_DEBUG_OFFSET 0x0058

// 32'h18070060 (SGMII_INTERRUPT_MASK)

3333

#define SGMII_INTERRUPT_MASK_MASK_MSB 7

3334

#define SGMII_INTERRUPT_MASK_MASK_LSB 0

3335

#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff

3336

#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)

3337

#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)

3338

#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0

3339

#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060

// 32'h1807005c (SGMII_INTERRUPT)

3345

#define SGMII_INTERRUPT_INTR_MSB 7

3346

#define SGMII_INTERRUPT_INTR_LSB 0

3347

#define SGMII_INTERRUPT_INTR_MASK 0x000000ff

3348

#define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB)

3349

#define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK)

3350

#define SGMII_INTERRUPT_INTR_RESET 0x0 // 0

3351

#define SGMII_INTERRUPT_ADDRESS 0x1807005c

3352

#define SGMII_INTERRUPT_OFFSET 0x005c

3353

// SW modifiable bits

3354

#define SGMII_INTERRUPT_SW_MASK 0x000000ff

3355

// bits defined at reset

3356

#define SGMII_INTERRUPT_RSTMASK 0xffffffff

3357

// reset value (ignore bits undefined at reset)

3358

#define SGMII_INTERRUPT_RESET 0x00000000

3359

3360

// 32'h18070060 (SGMII_INTERRUPT_MASK)

3361

#define SGMII_INTERRUPT_MASK_MASK_MSB 7

3362

#define SGMII_INTERRUPT_MASK_MASK_LSB 0

3363

#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff

3364

#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)

3365

#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)

3366

#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0

3367

#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060

3368

3369

3370

#define SGMII_LINK_FAIL (1 << 0)

3371

#define SGMII_DUPLEX_ERR (1 << 1)

3372

#define SGMII_MR_AN_COMPLETE (1 << 2)

3373

#define SGMII_LINK_MAC_CHANGE (1 << 3)

3374

#define SGMII_DUPLEX_MODE_CHANGE (1 << 4)

3375

#define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5)

3376

#define SGMII_RX_QUIET_CHANGE (1 << 6)

3377

#define SGMII_RX_MDIO_COMP_CHANGE (1 << 7)

3378

3379

#define SGMII_INTR SGMII_LINK_FAIL | \

3380

SGMII_LINK_MAC_CHANGE | \

3381

SGMII_DUPLEX_MODE_CHANGE | \

3382

SGMII_SPEED_MODE_MAC_CHANGE

3383

3384

3385

// 32'h18050048 (ETH_SGMII)

3386

#define ETH_SGMII_TX_INVERT_MSB 31

3387

#define ETH_SGMII_TX_INVERT_LSB 31

3388

#define ETH_SGMII_TX_INVERT_MASK 0x80000000

3389

#define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB)

3390

#define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK)

3391

#define ETH_SGMII_TX_INVERT_RESET 0x0 // 0

3392

#define ETH_SGMII_GIGE_QUAD_MSB 30

3393

#define ETH_SGMII_GIGE_QUAD_LSB 30

3394

#define ETH_SGMII_GIGE_QUAD_MASK 0x40000000

3395

#define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB)

3396

#define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK)

3397

#define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0

3398

#define ETH_SGMII_RX_DELAY_MSB 29

3399

#define ETH_SGMII_RX_DELAY_LSB 28

3400

#define ETH_SGMII_RX_DELAY_MASK 0x30000000

3401

#define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB)

3402

#define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK)

3403

#define ETH_SGMII_RX_DELAY_RESET 0x0 // 0

3404

#define ETH_SGMII_TX_DELAY_MSB 27

3405

#define ETH_SGMII_TX_DELAY_LSB 26

3406

#define ETH_SGMII_TX_DELAY_MASK 0x0c000000

3407

#define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB)

3408

#define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK)

3409

#define ETH_SGMII_TX_DELAY_RESET 0x0 // 0

3410

#define ETH_SGMII_CLK_SEL_MSB 25

3411

#define ETH_SGMII_CLK_SEL_LSB 25

3412

#define ETH_SGMII_CLK_SEL_MASK 0x02000000

3413

#define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB)

3414

#define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK)

3415

#define ETH_SGMII_CLK_SEL_RESET 0x1 // 1

3416

#define ETH_SGMII_GIGE_MSB 24

3417

#define ETH_SGMII_GIGE_LSB 24

3418

#define ETH_SGMII_GIGE_MASK 0x01000000

3419

#define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB)

3420

#define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK)

3421

#define ETH_SGMII_GIGE_RESET 0x1 // 1

3422

#define ETH_SGMII_PHASE1_COUNT_MSB 15

3423

#define ETH_SGMII_PHASE1_COUNT_LSB 8

3424

#define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00

3425

#define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB)

3426

#define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK)

3427

#define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1

3428

#define ETH_SGMII_PHASE0_COUNT_MSB 7

3429

#define ETH_SGMII_PHASE0_COUNT_LSB 0

3430

#define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff

3431

#define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB)

3432

#define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK)

3433

#define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1

3434

#define ETH_SGMII_ADDRESS 0x18050048

3435

3436

3437

#define OTP_INTF2_ADDRESS 0x18131008

3438

#define OTP_LDO_CONTROL_ADDRESS 0x18131024

3439

3440

#define OTP_LDO_STATUS_POWER_ON_MSB 0

3441

#define OTP_LDO_STATUS_POWER_ON_LSB 0

3442

#define OTP_LDO_STATUS_POWER_ON_MASK 0x00000001

3443

#define OTP_LDO_STATUS_POWER_ON_GET(x) (((x) & OTP_LDO_STATUS_POWER_ON_MASK) >> OTP_LDO_STATUS_POWER_ON_LSB)

3444

#define OTP_LDO_STATUS_POWER_ON_SET(x) (((x) << OTP_LDO_STATUS_POWER_ON_LSB) & OTP_LDO_STATUS_POWER_ON_MASK)

3445

#define OTP_LDO_STATUS_POWER_ON_RESET 0x0 // 0

3446

#define OTP_LDO_STATUS_ADDRESS 0x1813102c

3447

3448

#define OTP_MEM_0_ADDRESS 0x18130000

3449

3450

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_MSB 2

3451

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB 2

3452

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK 0x00000004

3453

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_GET(x) (((x) & OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK) >> OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB)

3454

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_SET(x) (((x) << OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB) & OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK)

3455

#define OTP_STATUS0_EFUSE_READ_DATA_VALID_RESET 0x0 // 0

3456

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_MSB 1

3457

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB 1

3458

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK 0x00000002

3459

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_GET(x) (((x) & OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK) >> OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB)

3460

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_SET(x) (((x) << OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB) & OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK)

3461

#define OTP_STATUS0_EFUSE_ACCESS_BUSY_RESET 0x0 // 0

3462

#define OTP_STATUS0_OTP_SM_BUSY_MSB 0

3463

#define OTP_STATUS0_OTP_SM_BUSY_LSB 0

3464

#define OTP_STATUS0_OTP_SM_BUSY_MASK 0x00000001

3465

#define OTP_STATUS0_OTP_SM_BUSY_GET(x) (((x) & OTP_STATUS0_OTP_SM_BUSY_MASK) >> OTP_STATUS0_OTP_SM_BUSY_LSB)

3466

#define OTP_STATUS0_OTP_SM_BUSY_SET(x) (((x) << OTP_STATUS0_OTP_SM_BUSY_LSB) & OTP_STATUS0_OTP_SM_BUSY_MASK)

3467

#define OTP_STATUS0_OTP_SM_BUSY_RESET 0x0 // 0

3468

#define OTP_STATUS0_ADDRESS 0x18131018

3469

3470

#define OTP_STATUS1_ADDRESS 0x1813101c

#endif /* _QCA955X_H */