Merge "[qca-nss-drv] Setup the NSS DDR start MMU address based on active nss cores"
diff --git a/exports/nss_n2h.h b/exports/nss_n2h.h
index fce2926..e5d210b 100644
--- a/exports/nss_n2h.h
+++ b/exports/nss_n2h.h
@@ -278,6 +278,8 @@
struct nss_mmu_ddr_info {
uint32_t ddr_size; /**< Total size of the DDR. */
uint32_t start_address; /**< System start address. */
+ uint32_t num_active_cores;
+ /**< Number of active cores. */
};
/**
diff --git a/nss_cmn.c b/nss_cmn.c
index 55131b7..38290f8 100644
--- a/nss_cmn.c
+++ b/nss_cmn.c
@@ -131,7 +131,7 @@
struct nss_subsystem_dataplane_register *nsdr;
nss_assert(dev != 0);
- for (core = 0; core < NSS_MAX_CORES; core++) {
+ for (core = 0; core < nss_top_main.num_nss; core++) {
for (i = 0; i < NSS_MAX_NET_INTERFACES; i++) {
nsdr = &nss_top_main.nss[core].subsys_dp_register[i];
if (dev == nsdr->ndev && type == nsdr->type) {
diff --git a/nss_core.c b/nss_core.c
index 0f3357b..595d8ef 100644
--- a/nss_core.c
+++ b/nss_core.c
@@ -397,6 +397,7 @@
si_meminfo(&vals);
cached = global_page_state(NR_FILE_PAGES);
avail_ddr = (vals.totalram + cached + vals.sharedram) * vals.mem_unit;
+ mmu->num_active_cores = nss_top_main.num_nss;
/*
* Since "memory" has not been used by anyone, the format is not final.
@@ -439,9 +440,9 @@
n_items = 0;
if (n_items) {
of_node_put(node);
- nss_info_always("%s: %x %u (avl %u) items %d\n",
+ nss_info_always("%s: %x %u (avl %u) items %d active_cores %d\n",
name, mmu->start_address, mmu->ddr_size,
- avail_ddr, n_items);
+ avail_ddr, n_items, mmu->num_active_cores);
/*
* if DTS mechanism goes wrong, use available
* DDR and round it up to 64MB for maximum DDR.
@@ -856,7 +857,7 @@
/*
* Check if core_id value is valid.
*/
- if (core_id > NSS_MAX_CORES) {
+ if (core_id > nss_top_main.num_nss) {
nss_warning("%p: Invalid core id: %d", nss_ctx, core_id);
return;
}
@@ -1972,7 +1973,7 @@
* up core. No NSS core knows the state of other other cores in system so
* NSS driver needs to mediate and kick start C2C between them
*/
- for (i = 0; i < NSS_MAX_CORES; i++) {
+ for (i = 0; i < nss_top_main.num_nss; i++) {
/*
* Loop through all NSS cores and send exchange C2C addresses
* TODO: Current implementation utilizes the fact that there are
diff --git a/nss_init.c b/nss_init.c
index e0393bc..43b4ec2 100644
--- a/nss_init.c
+++ b/nss_init.c
@@ -1,6 +1,6 @@
/*
**************************************************************************
- * Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -665,7 +665,11 @@
if (of_machine_is_compatible("qcom,ipq807x")) {
nss_top_main.hal_ops = &nss_hal_ipq807x_ops;
nss_top_main.data_plane_ops = &nss_data_plane_edma_ops;
+#if defined(NSS_MEM_PROFILE_LOW)
+ nss_top_main.num_nss = 1;
+#else
nss_top_main.num_nss = 2;
+#endif
}
#endif
#if defined(NSS_HAL_IPQ60XX_SUPPORT)