Merge "[qca-nss-drv] Support multiple H2N rings"
diff --git a/Makefile b/Makefile
index 4e50bbd..53cc9ee 100644
--- a/Makefile
+++ b/Makefile
@@ -117,7 +117,7 @@
nss_hal/ipq807x/nss_hal_pvt.o \
nss_dtls_cmn.o \
nss_crypto_cmn.o
-ccflags-y += -I$(obj)/nss_hal/ipq807x -DNSS_HAL_IPQ807x_SUPPORT
+ccflags-y += -I$(obj)/nss_hal/ipq807x -DNSS_HAL_IPQ807x_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
endif
ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1
diff --git a/exports/arch/nss_ipq807x.h b/exports/arch/nss_ipq807x.h
index d5770d1..9ed8330 100644
--- a/exports/arch/nss_ipq807x.h
+++ b/exports/arch/nss_ipq807x.h
@@ -31,7 +31,7 @@
#define NSS_PPE_SUPPORTED /**< PPE supported flag for the IPQ807x chipsets. */
#define NSS_N2H_RING_COUNT 5 /**< Number of N2H rings for the IPQ807x chipsets. */
-#define NSS_H2N_RING_COUNT 4 /**< Number of H2N rings for the IPQ807x chipsets. */
+#define NSS_H2N_RING_COUNT 11 /**< Number of H2N rings for the IPQ807x chipsets. */
#define NSS_RING_SIZE 128 /**< Ring size for the IPQ807x chipsets. */
/**
diff --git a/exports/arch/nss_ipq807x_64.h b/exports/arch/nss_ipq807x_64.h
index 091b532..7921a00 100644
--- a/exports/arch/nss_ipq807x_64.h
+++ b/exports/arch/nss_ipq807x_64.h
@@ -31,7 +31,7 @@
#define NSS_PPE_SUPPORTED /**< PPE supported flag for the IPQ807x 64-bit chipsets. */
#define NSS_N2H_RING_COUNT 5 /**< Number of N2H rings for the IPQ807x 64-bit chipsets. */
-#define NSS_H2N_RING_COUNT 4 /**< Number of H2N rings for the IPQ807x 64-bit chipsets. */
+#define NSS_H2N_RING_COUNT 11 /**< Number of H2N rings for the IPQ807x 64-bit chipsets. */
#define NSS_RING_SIZE 128 /**< Ring size for the IPQ807x 64-bit chipsets. */
/**
diff --git a/nss_core.c b/nss_core.c
index 45461d1..7687d3c 100644
--- a/nss_core.c
+++ b/nss_core.c
@@ -657,12 +657,13 @@
unsigned int interface_num,
struct sk_buff *nbuf,
struct napi_struct *napi,
- uint16_t flags)
+ uint16_t flags, uint16_t qid)
{
struct nss_top_instance *nss_top = nss_ctx->nss_top;
struct nss_subsystem_dataplane_register *subsys_dp_reg = &nss_ctx->subsys_dp_register[interface_num];
struct net_device *ndev = NULL;
nss_phys_if_rx_callback_t cb;
+ uint16_t queue_offset = qid - NSS_IF_N2H_DATA_QUEUE_0;
NSS_PKT_STATS_INCREMENT(nss_ctx, &nss_top->stats_drv[NSS_STATS_DRV_RX_PACKET]);
@@ -693,6 +694,13 @@
return;
}
+ /*
+ * Record RX queue if the netdev has that many RX queues
+ */
+ if (queue_offset < ndev->real_num_rx_queues) {
+ skb_record_rx_queue(nbuf, queue_offset);
+ }
+
cb(ndev, (void *)nbuf, napi);
return;
}
@@ -755,7 +763,7 @@
* Receive a pbuf from the NSS into Linux.
*/
static inline void nss_core_rx_pbuf(struct nss_ctx_instance *nss_ctx, struct napi_struct *napi,
- uint8_t buffer_type, struct sk_buff *nbuf, uint32_t desc_ifnum, uint32_t bit_flags)
+ uint8_t buffer_type, struct sk_buff *nbuf, uint32_t desc_ifnum, uint32_t bit_flags, uint16_t qid)
{
unsigned int interface_num = NSS_INTERFACE_NUM_GET(desc_ifnum);
unsigned int core_id = NSS_INTERFACE_NUM_GET_COREID(desc_ifnum);
@@ -798,7 +806,7 @@
break;
case N2H_BUFFER_PACKET:
- nss_core_handle_buffer_pkt(nss_ctx, interface_num, nbuf, napi, bit_flags);
+ nss_core_handle_buffer_pkt(nss_ctx, interface_num, nbuf, napi, bit_flags, qid);
break;
case N2H_BUFFER_PACKET_EXT:
@@ -1405,7 +1413,7 @@
}
consume:
- nss_core_rx_pbuf(nss_ctx, &(int_ctx->napi), buffer_type, nbuf, n2h_desc_ring->interface_num, n2h_desc_ring->bit_flags);
+ nss_core_rx_pbuf(nss_ctx, &(int_ctx->napi), buffer_type, nbuf, n2h_desc_ring->interface_num, n2h_desc_ring->bit_flags, qid);
next:
@@ -2838,6 +2846,7 @@
int32_t nss_core_send_packet(struct nss_ctx_instance *nss_ctx, struct sk_buff *nbuf, uint32_t if_num, uint32_t flag)
{
int32_t status;
+ int32_t queue_id = 0;
NSS_VERIFY_CTX_MAGIC(nss_ctx);
if (unlikely(nss_ctx->state != NSS_CORE_STATE_INITIALIZED)) {
@@ -2845,13 +2854,26 @@
return NSS_TX_FAILURE_NOT_READY;
}
- status = nss_core_send_buffer(nss_ctx, if_num, nbuf, NSS_IF_H2N_DATA_QUEUE, H2N_BUFFER_PACKET, flag);
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+ queue_id = (skb_get_queue_mapping(nbuf) & (NSS_HOST_CORES - 1)) << 1;
+ if (nbuf->priority & 0x7) {
+ queue_id++;
+ }
+#endif
+ status = nss_core_send_buffer(nss_ctx, if_num, nbuf, NSS_IF_H2N_DATA_QUEUE + queue_id, H2N_BUFFER_PACKET, flag);
if (status != NSS_CORE_STATUS_SUCCESS) {
nss_warning("%p: interface: %d unable to enqueue packet status %d\n", nss_ctx, if_num, status);
return status;
}
nss_hal_send_interrupt(nss_ctx, NSS_H2N_INTR_DATA_COMMAND_QUEUE);
+
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+ /*
+ * Count per queue and aggregate packet count
+ */
+ NSS_PKT_STATS_INCREMENT(nss_ctx, &nss_ctx->nss_top->stats_drv[NSS_STATS_DRV_TX_PACKET_QUEUE_0 + queue_id]);
+#endif
NSS_PKT_STATS_INCREMENT(nss_ctx, &nss_ctx->nss_top->stats_drv[NSS_STATS_DRV_TX_PACKET]);
return status;
}
diff --git a/nss_core.h b/nss_core.h
index 9533934..693b59a 100644
--- a/nss_core.h
+++ b/nss_core.h
@@ -328,6 +328,16 @@
NSS_STATS_DRV_CHAIN_SEG_PROCESSED, /* N2H SKB Chain Processed Count */
NSS_STATS_DRV_FRAG_SEG_PROCESSED, /* N2H Frag Processed Count */
NSS_STATS_DRV_TX_CMD_QUEUE_FULL, /* Tx H2N Control packets fail due to queue full */
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+ NSS_STATS_DRV_TX_PACKET_QUEUE_0, /* H2N Data packets on queue0 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_1, /* H2N Data packets on queue1 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_2, /* H2N Data packets on queue2 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_3, /* H2N Data packets on queue3 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_4, /* H2N Data packets on queue4 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_5, /* H2N Data packets on queue5 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_6, /* H2N Data packets on queue6 */
+ NSS_STATS_DRV_TX_PACKET_QUEUE_7, /* H2N Data packets on queue7 */
+#endif
NSS_STATS_DRV_MAX,
};
diff --git a/nss_stats.c b/nss_stats.c
index efd7d43..71fca9d 100644
--- a/nss_stats.c
+++ b/nss_stats.c
@@ -56,6 +56,16 @@
"rx_chain_seg_processed",
"rx_frag_seg_processed",
"tx_buffers_cmd_queue_full",
+#ifdef NSS_MULTI_H2N_DATA_RING_SUPPORT
+ "tx_buffers_data_queue_0",
+ "tx_buffers_data_queue_1",
+ "tx_buffers_data_queue_2",
+ "tx_buffers_data_queue_3",
+ "tx_buffers_data_queue_4",
+ "tx_buffers_data_queue_5",
+ "tx_buffers_data_queue_6",
+ "tx_buffers_data_queue_7",
+#endif
};
/*