Merge "[qca-nss-drv] PPTP Logging"
diff --git a/Makefile b/Makefile
index 4e84f4e..ae16573 100644
--- a/Makefile
+++ b/Makefile
@@ -141,6 +141,16 @@
ccflags-y += -I$(obj)/nss_hal/ipq807x -DNSS_HAL_IPQ807x_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
endif
+ifeq ($(SoC),$(filter $(SoC),ipq60xx ipq60xx_64))
+qca-nss-drv-objs += nss_data_plane/nss_data_plane_edma.o \
+ nss_hal/ipq60xx/nss_hal_pvt.o \
+ nss_dtls_cmn.o \
+ nss_dtls_cmn_log.o \
+ nss_crypto_cmn.o \
+ nss_crypto_cmn_log.o
+ccflags-y += -I$(obj)/nss_hal/ipq60xx -DNSS_HAL_IPQ60XX_SUPPORT -DNSS_MULTI_H2N_DATA_RING_SUPPORT
+endif
+
ccflags-y += -I$(obj)/nss_hal/include -I$(obj)/nss_data_plane/include -I$(obj)/exports -DNSS_DEBUG_LEVEL=0 -DNSS_PKT_STATS_ENABLED=1
ccflags-y += -DNSS_PM_DEBUG_LEVEL=0 -DNSS_SKB_REUSE_SUPPORT=1
diff --git a/exports/arch/nss_ipq60xx.h b/exports/arch/nss_ipq60xx.h
new file mode 100644
index 0000000..129bfef
--- /dev/null
+++ b/exports/arch/nss_ipq60xx.h
@@ -0,0 +1,47 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq60xx.h
+ * Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ60XX_H
+#define __NSS_IPQ60XX_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq60xx
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4 /**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4 /**< Number of host cores. */
+#define NSS_PPE_SUPPORTED /**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5 /**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11 /**< Number of H2N rings. */
+#define NSS_RING_SIZE 128 /**< Ring size. */
+
+/*
+ * <TODO: Needs to be removed
+ */
+#define NSS_IMEM_START 0x0 /**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE 0x0 /**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ60XX_H */
diff --git a/exports/arch/nss_ipq60xx_64.h b/exports/arch/nss_ipq60xx_64.h
new file mode 100644
index 0000000..86e8ba4
--- /dev/null
+++ b/exports/arch/nss_ipq60xx_64.h
@@ -0,0 +1,47 @@
+/*
+ **************************************************************************
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ **************************************************************************
+ */
+
+/**
+ * @file nss_ipq60xx_64.h
+ * Architecture dependent parameters.
+ */
+#ifndef __NSS_IPQ60XX_64_H
+#define __NSS_IPQ60XX_64_H
+
+/**
+ * @addtogroup nss_arch_macros_ipq60xx_64
+ * @{
+ */
+
+#define NSS_MAX_NUM_PRI 4 /**< Maximum number of priority queues in NSS. */
+#define NSS_HOST_CORES 4 /**< Number of host cores. */
+#define NSS_PPE_SUPPORTED /**< PPE supported flag. */
+
+#define NSS_N2H_RING_COUNT 5 /**< Number of N2H rings. */
+#define NSS_H2N_RING_COUNT 11 /**< Number of H2N rings. */
+#define NSS_RING_SIZE 128 /**< Ring size. */
+
+/*
+ * <TODO: Needs to be removed
+ */
+#define NSS_IMEM_START 0x0 /**< NSS IMEM start address. */
+#define NSS_IMEM_SIZE 0x0 /**< NSS IMEM size per core. */
+
+/**
+ * @}
+ */
+
+#endif /** __NSS_IPQ60XX_64_H */
diff --git a/nss_core.h b/nss_core.h
index 60757db..38a4402 100644
--- a/nss_core.h
+++ b/nss_core.h
@@ -195,7 +195,7 @@
/*
* NSS maximum IRQ per interrupt instance/core
*/
-#if defined(NSS_HAL_IPQ807x_SUPPORT)
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
#define NSS_MAX_IRQ_PER_INSTANCE 6
#define NSS_MAX_IRQ_PER_CORE 9
#else
diff --git a/nss_hal/include/nss_hal.h b/nss_hal/include/nss_hal.h
index e16f975..52ed690 100644
--- a/nss_hal/include/nss_hal.h
+++ b/nss_hal/include/nss_hal.h
@@ -1,6 +1,6 @@
/*
**************************************************************************
- * Copyright (c) 2013, 2016-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013, 2016-2018 The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -40,6 +40,9 @@
#if defined(NSS_HAL_IPQ807x_SUPPORT)
extern struct nss_hal_ops nss_hal_ipq807x_ops;
#endif
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+extern struct nss_hal_ops nss_hal_ipq60xx_ops;
+#endif
#if defined(NSS_HAL_FSM9010_SUPPORT)
extern struct nss_hal_ops nss_hal_fsm9010_ops;
#endif
diff --git a/nss_hal/ipq60xx/nss_hal_pvt.c b/nss_hal/ipq60xx/nss_hal_pvt.c
new file mode 100644
index 0000000..f2194c7
--- /dev/null
+++ b/nss_hal/ipq60xx/nss_hal_pvt.c
@@ -0,0 +1,675 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * nss_hal_pvt.c
+ * NSS HAL private APIs.
+ */
+
+#include <linux/err.h>
+#include <linux/version.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include "nss_hal.h"
+#include "nss_core.h"
+
+#define NSS_QGIC_IPC_REG_OFFSET 0x8
+
+#define NSS0_H2N_INTR_BASE 13
+
+/*
+ * Common CLKs
+ */
+#define NSS_NOC_CLK "nss-noc-clk"
+#define NSS_PTP_REF_CLK "nss-ptp-ref-clk"
+#define NSS_CSR_CLK "nss-csr-clk"
+#define NSS_CFG_CLK "nss-cfg-clk"
+#define NSS_NSSNOC_QOSGEN_REF_CLK "nss-nssnoc-qosgen-ref-clk"
+#define NSS_MEM_NOC_NSS_AXI_CLK "nss-mem-noc-nss-axi-clk"
+#define NSS_NSSNOC_SNOC_CLK "nss-nssnoc-snoc-clk"
+#define NSS_NSSNOC_TIMEOUT_REF_CLK "nss-nssnoc-timeout-ref-clk"
+#define NSS_CE_AXI_CLK "nss-ce-axi-clk"
+#define NSS_CE_APB_CLK "nss-ce-apb-clk"
+#define NSS_NSSNOC_CE_AXI_CLK "nss-nssnoc-ce-axi-clk"
+#define NSS_NSSNOC_CE_APB_CLK "nss-nssnoc-ce-apb-clk"
+
+/*
+ * Per-core CLKS
+ */
+#define NSS_NSSNOC_AHB_CLK "nss-nssnoc-ahb-clk"
+#define NSS_CORE_CLK "nss-core-clk"
+#define NSS_AHB_CLK "nss-ahb-clk"
+#define NSS_AXI_CLK "nss-axi-clk"
+#define NSS_NC_AXI_CLK "nss-nc-axi-clk"
+
+/*
+ * Voltage values
+ */
+#define NOMINAL_VOLTAGE 1
+#define TURBO_VOLTAGE 2
+
+/*
+ * Core reset part 1
+ */
+#define NSS_CORE_GCC_RESET_1 0x00000020
+
+/*
+ * Core reset part 2
+ */
+#define NSS_CORE_GCC_RESET_2 0x00000017
+
+/*
+ * Voltage regulator
+ */
+struct regulator *npu_reg;
+
+/*
+ * GCC reset
+ */
+void __iomem *nss_misc_reset;
+void __iomem *nss_misc_reset_flag;
+void __iomem *nss_misc_reset_addr;
+
+/*
+ * Purpose of each interrupt index: This should match the order defined in the NSS firmware
+ */
+enum nss_hal_n2h_intr_purpose {
+ NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS = 0,
+ NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE = 1,
+ NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED = 2,
+ NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0 = 3,
+ NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1 = 4,
+ NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2 = 5,
+ NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3 = 6,
+ NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE = 7,
+ NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS = 8,
+ NSS_HAL_N2H_INTR_PURPOSE_MAX = 9,
+};
+
+/*
+ * Interrupt type to cause vector.
+ */
+static uint32_t intr_cause[NSS_MAX_CORES][NSS_H2N_INTR_TYPE_MAX] = {
+ /* core0 */
+ {(1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_BUFFER_QUEUE)),
+ (1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_DATA_COMMAND_QUEUE)),
+ (1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TX_UNBLOCKED)),
+ (1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_TRIGGER_COREDUMP)),
+ (1 << (NSS0_H2N_INTR_BASE + NSS_H2N_INTR_EMPTY_PAGED_BUFFER_QUEUE))}
+};
+
+/*
+ * nss_hal_wq_function()
+ * Added to Handle BH requests to kernel
+ */
+void nss_hal_wq_function(struct work_struct *work)
+{
+ kfree((void *)work);
+}
+
+/*
+ * nss_hal_handle_irq()
+ */
+static irqreturn_t nss_hal_handle_irq(int irq, void *ctx)
+{
+ struct int_ctx_instance *int_ctx = (struct int_ctx_instance *) ctx;
+
+ disable_irq_nosync(irq);
+ napi_schedule(&int_ctx->napi);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * __nss_hal_of_get_pdata()
+ * Retrieve platform data from device node.
+ */
+static struct nss_platform_data *__nss_hal_of_get_pdata(struct platform_device *pdev)
+{
+ struct device_node *np = of_node_get(pdev->dev.of_node);
+ struct nss_platform_data *npd;
+ struct nss_ctx_instance *nss_ctx = NULL;
+ struct nss_top_instance *nss_top = &nss_top_main;
+ struct resource res_nphys, res_qgic_phys;
+ int32_t i;
+
+ npd = devm_kzalloc(&pdev->dev, sizeof(struct nss_platform_data), GFP_KERNEL);
+ if (!npd) {
+ return NULL;
+ }
+
+ if (of_property_read_u32(np, "qcom,id", &npd->id)
+ || of_property_read_u32(np, "qcom,load-addr", &npd->load_addr)
+ || of_property_read_u32(np, "qcom,num-queue", &npd->num_queue)
+ || of_property_read_u32(np, "qcom,num-irq", &npd->num_irq)) {
+ pr_err("%s: error reading critical device node properties\n", np->name);
+ goto out;
+ }
+
+ /*
+ * Read frequencies. If failure, load default values.
+ */
+ of_property_read_u32(np, "qcom,low-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency);
+ of_property_read_u32(np, "qcom,mid-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency);
+ of_property_read_u32(np, "qcom,max-frequency", &nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency);
+
+ if (npd->num_irq > NSS_MAX_IRQ_PER_CORE) {
+ pr_err("%s: exceeds maximum interrupt numbers per core\n", np->name);
+ goto out;
+ }
+
+ nss_ctx = &nss_top->nss[npd->id];
+ nss_ctx->id = npd->id;
+
+ if (of_address_to_resource(np, 0, &res_nphys) != 0) {
+ nss_info_always("%p: nss%d: of_address_to_resource() fail for nphys\n", nss_ctx, nss_ctx->id);
+ goto out;
+ }
+
+ if (of_address_to_resource(np, 1, &res_qgic_phys) != 0) {
+ nss_info_always("%p: nss%d: of_address_to_resource() fail for qgic_phys\n", nss_ctx, nss_ctx->id);
+ goto out;
+ }
+
+ /*
+ * Save physical addresses
+ */
+ npd->nphys = res_nphys.start;
+ npd->qgic_phys = res_qgic_phys.start;
+
+ npd->nmap = ioremap_nocache(npd->nphys, resource_size(&res_nphys));
+ if (!npd->nmap) {
+ nss_info_always("%p: nss%d: ioremap() fail for nphys\n", nss_ctx, nss_ctx->id);
+ goto out;
+ }
+
+ npd->qgic_map = ioremap_nocache(npd->qgic_phys, resource_size(&res_qgic_phys));
+ if (!npd->qgic_map) {
+ nss_info_always("%p: nss%d: ioremap() fail for qgic map\n", nss_ctx, nss_ctx->id);
+ goto out;
+ }
+
+ NSS_CORE_DSB();
+
+ /*
+ * Get IRQ numbers
+ */
+ for (i = 0 ; i < npd->num_irq; i++) {
+ npd->irq[i] = irq_of_parse_and_map(np, i);
+ if (!npd->irq[i]) {
+ nss_info_always("%p: nss%d: irq_of_parse_and_map() fail for irq %d\n", nss_ctx, nss_ctx->id, i);
+ goto out;
+ }
+ }
+
+ nss_hal_dt_parse_features(np, npd);
+
+ of_node_put(np);
+ return npd;
+
+out:
+ if (npd->nmap) {
+ iounmap(npd->nmap);
+ }
+
+ if (npd->vmap) {
+ iounmap(npd->vmap);
+ }
+
+ devm_kfree(&pdev->dev, npd);
+ of_node_put(np);
+ return NULL;
+}
+
+/*
+ * __nss_hal_core_reset()
+ */
+static int __nss_hal_core_reset(struct platform_device *nss_dev, void __iomem *map, uint32_t addr, uint32_t clk_src)
+{
+ /*
+ * De-assert reset for first set
+ */
+ nss_write_32(nss_misc_reset, 0x0, 0x0);
+
+ /*
+ * Minimum 10 - 20 cycles delay is required after
+ * de-asserting NSS reset clamp
+ */
+ usleep_range(10, 20);
+
+ /*
+ * Load instruction to NSS UTCM
+ * TODO: Can uncomment uTCM later for booting.
+ */
+ //nss_write_32(nss_misc_reset_addr, 0, 0xD6E00000);
+ nss_write_32(nss_misc_reset_addr, 0x400, 0xD6E00000);
+
+ /*
+ * Release NSS from Reset
+ */
+ nss_write_32(map, 0x4, 0x1);
+
+ /*
+ * NSS code location
+ * TODO: Can unncomment to support UTCM
+ */
+ //nss_write_32(map, 0, 0x3e000000);
+ nss_write_32(map, 0x10, addr);
+
+ /*
+ * Program address configuration
+ */
+ nss_write_32(map, 0xc, 0x1);
+ nss_write_32(map, 0x8, 0x3C000000);
+ nss_write_32(map, 0x4, 0x0);
+
+ /*
+ * Clear flag between A53 and NSS for print
+ */
+ nss_write_32(nss_misc_reset_flag, 0, 0x0);
+
+ return 0;
+}
+
+/*
+ * __nss_hal_debug_enable()
+ * Enable NSS debug
+ */
+static void __nss_hal_debug_enable(void)
+{
+
+}
+
+/*
+ * nss_hal_clock_set_and_enable()
+ */
+static int nss_hal_clock_set_and_enable(struct device *dev, const char *id, unsigned long rate)
+{
+ struct clk *nss_clk = NULL;
+ int err;
+
+ nss_clk = devm_clk_get(dev, id);
+ if (IS_ERR(nss_clk)) {
+ pr_err("%p: cannot get clock: %s\n", dev, id);
+ return -EFAULT;
+ }
+
+ if (rate) {
+ err = clk_set_rate(nss_clk, rate);
+ if (err) {
+ pr_err("%p: cannot set %s freq\n", dev, id);
+ return -EFAULT;
+ }
+ }
+
+ err = clk_prepare_enable(nss_clk);
+ if (err) {
+ pr_err("%p: cannot enable clock: %s\n", dev, id);
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+/*
+ * __nss_hal_common_reset
+ * Do reset/clock configuration common to all cores
+ */
+static int __nss_hal_common_reset(struct platform_device *nss_dev)
+{
+
+ struct device_node *cmn = NULL;
+ struct resource res_nss_misc_reset;
+ struct resource res_nss_misc_reset_flag;
+ struct resource res_nss_misc_reset_addr;
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NOC_CLK, 461500000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_PTP_REF_CLK, 150000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CSR_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CFG_CLK, 100000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_QOSGEN_REF_CLK, 19200000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_MEM_NOC_NSS_AXI_CLK, 461500000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_SNOC_CLK, 266600000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_TIMEOUT_REF_CLK, 4800000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_AXI_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CE_APB_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_AXI_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_CE_APB_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ /*
+ * Get reference to NSS common device node
+ */
+ cmn = of_find_node_by_name(NULL, "nss-common");
+ if (!cmn) {
+ pr_err("%p: Unable to find nss-common node\n", nss_dev);
+ return -EFAULT;
+ }
+
+ if (of_address_to_resource(cmn, 0, &res_nss_misc_reset) != 0) {
+ pr_err("%p: of_address_to_resource() return error for nss_misc_reset\n", nss_dev);
+ of_node_put(cmn);
+ return -EFAULT;
+ }
+
+ if (of_address_to_resource(cmn, 1, &res_nss_misc_reset_flag) != 0) {
+ pr_err("%p: of_address_to_resource() return error for nss_misc_reset_flag\n", nss_dev);
+ of_node_put(cmn);
+ return -EFAULT;
+ }
+
+ if (of_address_to_resource(cmn, 2, &res_nss_misc_reset_addr) != 0) {
+ pr_err("%p: of_address_to_resource() return error for nss_misc_reset_addr\n", nss_dev);
+ of_node_put(cmn);
+ return -EFAULT;
+ }
+
+ of_node_put(cmn);
+
+ nss_misc_reset = ioremap_nocache(res_nss_misc_reset.start, resource_size(&res_nss_misc_reset));
+ if (!nss_misc_reset) {
+ pr_err("%p: ioremap fail for nss_misc_reset\n", nss_dev);
+ return -EFAULT;
+ }
+
+ nss_misc_reset_flag = ioremap_nocache(res_nss_misc_reset_flag.start, resource_size(&res_nss_misc_reset_flag));
+ if (!nss_misc_reset_flag) {
+ pr_err("%p: ioremap fail for nss_misc_reset_flag\n", nss_dev);
+ return -EFAULT;
+ }
+
+ nss_misc_reset_addr = ioremap_nocache(res_nss_misc_reset_addr.start, resource_size(&res_nss_misc_reset_addr));
+ if (!nss_misc_reset_addr) {
+ pr_err("%p: ioremap fail for nss_misc_reset_addr\n", nss_dev);
+ return -EFAULT;
+ }
+
+ nss_top_main.nss_hal_common_init_done = true;
+ nss_info("nss_hal_common_reset Done\n");
+
+ return 0;
+}
+
+/*
+ * __nss_hal_clock_configure()
+ */
+static int __nss_hal_clock_configure(struct nss_ctx_instance *nss_ctx, struct platform_device *nss_dev, struct nss_platform_data *npd)
+{
+ int i;
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NSSNOC_AHB_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AHB_CLK, 200000000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_AXI_CLK, 461500000)) {
+ return -EFAULT;
+ }
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_NC_AXI_CLK, 461500000)) {
+ return -EFAULT;
+ }
+
+ /*
+ * No entries, then just load default
+ */
+ if ((nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency == 0) ||
+ (nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency == 0) ||
+ (nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency == 0)) {
+ nss_runtime_samples.freq_scale[NSS_FREQ_LOW_SCALE].frequency = NSS_FREQ_187;
+ nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency = NSS_FREQ_748;
+ nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency = NSS_FREQ_1497;
+ nss_info_always("Running default frequencies\n");
+ }
+
+ /*
+ * Test frequency from dtsi, if fail, try to set default frequency.
+ */
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_HIGH_SCALE].frequency)) {
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, NSS_FREQ_1497)) {
+ return -EFAULT;
+ }
+ }
+
+ /*
+ * Setup ranges, test frequency, and display.
+ */
+ for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+ if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+ nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_187_MIN;
+ nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_187_MAX;
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+ nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_748_MIN;
+ nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_748_MAX;
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+ nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1497_MIN;
+ nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1497_MAX;
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+ nss_runtime_samples.freq_scale[i].minimum = NSS_FREQ_1689_MIN;
+ nss_runtime_samples.freq_scale[i].maximum = NSS_FREQ_1689_MAX;
+ } else {
+ nss_info_always("Frequency not found %d\n", nss_runtime_samples.freq_scale[i].frequency);
+ return -EFAULT;
+ }
+
+ /*
+ * Test the frequency, if fail, then default to safe frequency and abort
+ */
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[i].frequency)) {
+ return -EFAULT;
+ }
+ }
+
+ nss_info_always("Supported Frequencies - ");
+ for (i = 0; i < NSS_FREQ_MAX_SCALE; i++) {
+ if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_187) {
+ nss_info_always("187.2 MHz ");
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_748) {
+ nss_info_always("748.8 MHz ");
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1497) {
+ nss_info_always("1.4976 GHz ");
+ } else if (nss_runtime_samples.freq_scale[i].frequency == NSS_FREQ_1689) {
+ nss_info_always("1.6896 GHz ");
+ } else {
+ nss_info_always("Error\nNo Table/Invalid Frequency Found\n");
+ return -EFAULT;
+ }
+ }
+ nss_info_always("\n");
+
+ /*
+ * Set values only once for core0. Grab the proper clock.
+ */
+ nss_core0_clk = clk_get(&nss_dev->dev, NSS_CORE_CLK);
+
+ if (nss_hal_clock_set_and_enable(&nss_dev->dev, NSS_CORE_CLK, nss_runtime_samples.freq_scale[NSS_FREQ_MID_SCALE].frequency)) {
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+/*
+ * __nss_hal_read_interrupt_cause()
+ */
+static void __nss_hal_read_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t *cause)
+{
+}
+
+/*
+ * __nss_hal_clear_interrupt_cause()
+ */
+static void __nss_hal_clear_interrupt_cause(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_disable_interrupt()
+ */
+static void __nss_hal_disable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_enable_interrupt()
+ */
+static void __nss_hal_enable_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t shift_factor, uint32_t cause)
+{
+}
+
+/*
+ * __nss_hal_send_interrupt()
+ */
+static void __nss_hal_send_interrupt(struct nss_ctx_instance *nss_ctx, uint32_t type)
+{
+ /*
+ * Check if core and type is Valid
+ */
+ nss_assert(nss_ctx->id < NSS_MAX_CORES);
+ nss_assert(type < NSS_H2N_INTR_TYPE_MAX);
+
+ nss_write_32(nss_ctx->qgic_map, NSS_QGIC_IPC_REG_OFFSET, intr_cause[nss_ctx->id][type]);
+}
+
+/*
+ * __nss_hal_request_irq()
+ */
+static int __nss_hal_request_irq(struct nss_ctx_instance *nss_ctx, struct nss_platform_data *npd, int irq_num)
+{
+ struct int_ctx_instance *int_ctx = &nss_ctx->int_ctx[irq_num];
+ int err = -1, irq = npd->irq[irq_num];
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_SOS) {
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+ int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFERS_SOS;
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_sos", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_EMPTY_BUFFER_QUEUE) {
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_EMPTY_BUFFER_RETURN_PROCESSING_WEIGHT);
+ int_ctx->cause = NSS_N2H_INTR_EMPTY_BUFFER_QUEUE;
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_empty_buf_queue", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_TX_UNBLOCKED) {
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_TX_UNBLOCKED_PROCESSING_WEIGHT);
+ int_ctx->cause = NSS_N2H_INTR_TX_UNBLOCKED;
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss-tx-unblock", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_0) {
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+ int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_0;
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue0", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_1) {
+ int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_1;
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue1", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_2) {
+ int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_2;
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue2", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_DATA_QUEUE_3) {
+ int_ctx->cause = NSS_N2H_INTR_DATA_QUEUE_3;
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_queue, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_queue3", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_COREDUMP_COMPLETE) {
+ int_ctx->cause = NSS_N2H_INTR_COREDUMP_COMPLETE;
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_emergency, NSS_DATA_COMMAND_BUFFER_PROCESSING_WEIGHT);
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_coredump_complete", int_ctx);
+ }
+
+ if (irq_num == NSS_HAL_N2H_INTR_PURPOSE_PAGED_EMPTY_BUFFER_SOS) {
+ netif_napi_add(int_ctx->ndev, &int_ctx->napi, nss_core_handle_napi_non_queue, NSS_EMPTY_BUFFER_SOS_PROCESSING_WEIGHT);
+ int_ctx->cause = NSS_N2H_INTR_PAGED_EMPTY_BUFFERS_SOS;
+ err = request_irq(irq, nss_hal_handle_irq, 0, "nss_paged_empty_buf_sos", int_ctx);
+ }
+
+ if (err) {
+ return err;
+ }
+
+ int_ctx->irq = irq;
+ return 0;
+}
+
+/*
+ * nss_hal_ipq60xx_ops
+ */
+struct nss_hal_ops nss_hal_ipq60xx_ops = {
+ .common_reset = __nss_hal_common_reset,
+ .core_reset = __nss_hal_core_reset,
+ .clock_configure = __nss_hal_clock_configure,
+ .firmware_load = nss_hal_firmware_load,
+ .debug_enable = __nss_hal_debug_enable,
+ .of_get_pdata = __nss_hal_of_get_pdata,
+ .request_irq = __nss_hal_request_irq,
+ .send_interrupt = __nss_hal_send_interrupt,
+ .enable_interrupt = __nss_hal_enable_interrupt,
+ .disable_interrupt = __nss_hal_disable_interrupt,
+ .clear_interrupt_cause = __nss_hal_clear_interrupt_cause,
+ .read_interrupt_cause = __nss_hal_read_interrupt_cause,
+};
diff --git a/nss_hal/nss_hal.c b/nss_hal/nss_hal.c
index 88ff1a1..7d6cf61 100644
--- a/nss_hal/nss_hal.c
+++ b/nss_hal/nss_hal.c
@@ -399,7 +399,7 @@
*/
if (npd->crypto_enabled == NSS_FEATURE_ENABLED) {
nss_top->crypto_handler_id = nss_dev->id;
-#if defined(NSS_HAL_IPQ807x_SUPPORT)
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
nss_crypto_cmn_register_handler();
#else
nss_top->crypto_enabled = 1;
@@ -442,7 +442,7 @@
if (npd->dtls_enabled == NSS_FEATURE_ENABLED) {
nss_top->dtls_handler_id = nss_dev->id;
-#if defined(NSS_HAL_IPQ807x_SUPPORT)
+#if defined(NSS_HAL_IPQ807x_SUPPORT) || defined(NSS_HAL_IPQ60XX_SUPPORT)
nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_INNER] = nss_dev->id;
nss_top->dynamic_interface_table[NSS_DYNAMIC_INTERFACE_TYPE_DTLS_CMN_OUTER] = nss_dev->id;
nss_dtls_cmn_register_handler();
diff --git a/nss_init.c b/nss_init.c
index 380a1bd..3f9248f 100644
--- a/nss_init.c
+++ b/nss_init.c
@@ -666,6 +666,12 @@
nss_top_main.data_plane_ops = &nss_data_plane_edma_ops;
}
#endif
+#if defined(NSS_HAL_IPQ60XX_SUPPORT)
+ if (of_machine_is_compatible("qcom,ipq6018")) {
+ nss_top_main.hal_ops = &nss_hal_ipq60xx_ops;
+ nss_top_main.data_plane_ops = &nss_data_plane_edma_ops;
+ }
+#endif
#if defined(NSS_HAL_FSM9010_SUPPORT)
if (of_machine_is_compatible("qcom,fsm9010")) {
nss_top_main.hal_ops = &nss_hal_fsm9010_ops;
@@ -801,7 +807,7 @@
/*
* INIT ppe on supported platform
*/
- if (of_machine_is_compatible("qcom,ipq807x")) {
+ if (of_machine_is_compatible("qcom,ipq807x") || of_machine_is_compatible("qcom,ipq6018")) {
nss_ppe_init();
}
@@ -855,7 +861,7 @@
/*
* cleanup ppe on supported platform
*/
- if (of_machine_is_compatible("qcom,ipq807x")) {
+ if (of_machine_is_compatible("qcom,ipq807x") || of_machine_is_compatible("qcom,ipq6018")) {
nss_ppe_free();
}
diff --git a/nss_ipsec.c b/nss_ipsec.c
index 65b7085..4b44f50 100644
--- a/nss_ipsec.c
+++ b/nss_ipsec.c
@@ -39,6 +39,11 @@
#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_RULE_INTERFACE
#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_RULE_INTERFACE
+#elif defined(NSS_HAL_IPQ60XX_SUPPORT)
+#define NSS_IPSEC_ENCAP_INTERFACE_NUM NSS_IPSEC_RULE_INTERFACE
+#define NSS_IPSEC_DECAP_INTERFACE_NUM NSS_IPSEC_RULE_INTERFACE
+#define NSS_IPSEC_DATA_INTERFACE_NUM NSS_IPSEC_RULE_INTERFACE
+
#else
#define NSS_IPSEC_ENCAP_INTERFACE_NUM -1
#define NSS_IPSEC_DECAP_INTERFACE_NUM -1