blob: 20289481d0d0cc5132cd56d62e9a96a219732d06 [file] [log] [blame]
Casey Chencfa28352018-04-21 01:03:02 -07001/*
2 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * nss_meminfo.c
19 * NSS meminfo subsystem
20 */
21
22#include <linux/seq_file_net.h>
23#include "nss_tx_rx_common.h"
24#include "nss_core.h"
25#include "nss_arch.h"
26#include "nss_meminfo.h"
27
28/*
29 * Store user configuration
30 */
31static char nss_meminfo_user_config[NSS_MEMINFO_USER_CONFIG_MAXLEN];
32module_param_string(meminfo_user_config, nss_meminfo_user_config,
33 NSS_MEMINFO_USER_CONFIG_MAXLEN, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP);
34MODULE_PARM_DESC(nss_meminfo_user_config, "meminfo user configuration");
35
36static bool nss_meminfo_debugfs_exist;
37
38/*
39 * Name table of memory type presented to user.
40 */
41char *nss_meminfo_memtype_table[NSS_MEMINFO_MEMTYPE_MAX] = {"IMEM", "SDRAM"};
42
43/*
44 * nss_meminfo_alloc_sdram()
45 * Allocate a SDRAM block.
46 */
47static unsigned long nss_meminfo_alloc_sdram(struct nss_ctx_instance *nss_ctx, uint32_t size)
48{
49 unsigned long addr = 0;
50
51 /*
52 * kmalloc() return cache line aligned buffer.
53 */
54 addr = (unsigned long)kmalloc(size, GFP_KERNEL | __GFP_ZERO);
55 if (!addr)
56 nss_info_always("%p: failed to alloc a sdram block of size %u\n", nss_ctx, size);
57
58 return addr;
59}
60
61/*
62 * nss_meminfo_free_sdram()
63 * Free SDRAM memory.
64 */
65static inline void nss_meminfo_free_sdram(struct nss_ctx_instance *nss_ctx, uint32_t dma_addr,
66 unsigned long kern_addr, uint32_t size)
67{
68 /*
69 * Unmap it since every SDRAM memory had been mapped.
70 */
71 dma_unmap_single(nss_ctx->dev, dma_addr, size, DMA_FROM_DEVICE);
72 kfree((void *)kern_addr);
73}
74
75/*
76 * nss_meminfo_alloc_imem()
77 * Allocate an IMEM block in a sequential way.
78 */
79static uint32_t nss_meminfo_alloc_imem(struct nss_ctx_instance *nss_ctx, uint32_t size, int alignment)
80{
81 struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
82 uint32_t new_tail;
83 uint32_t addr = 0;
84 int mask;
85
86 mask = alignment - 1;
87
88 /*
89 * Alignment has to be a power of 2.
90 */
91 nss_assert(!(alignment & mask));
92
93 new_tail = mem_ctx->imem_tail;
94
95 /*
96 * Align up the address if it not aligned.
97 */
98 if (new_tail & mask)
99 new_tail = (new_tail + mask) & ~mask;
100
101 if (size > (mem_ctx->imem_end - new_tail)) {
102 nss_info_always("%p: failed to alloc an IMEM block of size %u\n", nss_ctx, size);
103 return addr;
104 }
105
106 addr = new_tail;
107 mem_ctx->imem_tail = new_tail + size;
108
109 return addr;
110}
111
112/*
113 * nss_meminfo_free_imem()
114 * Free an IMEM block. Ignore the padding bytes for alignment requirement.
115 */
116static void nss_meminfo_free_imem(struct nss_ctx_instance *nss_ctx, uint32_t addr, uint32_t size)
117{
118 struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
119 mem_ctx->imem_tail -= size;
120}
121
122/*
123 * nss_meminfo_if_user_overwrite()
124 * Return user configured memory type. Otherwise, return -1.
125 */
126static int nss_meminfo_if_user_overwrite(struct nss_ctx_instance *nss_ctx, const char *name)
127{
128 char *user_config;
129 char **mtype_table;
130 char needle[NSS_MEMINFO_BLOCK_NAME_MAXLEN + 6];
131 char user_choice[NSS_MEMINFO_MEMTYPE_NAME_MAXLEN];
132 int i;
133 char *p;
134
135 user_config = nss_meminfo_user_config;
136 mtype_table = nss_meminfo_memtype_table;
137
138 snprintf(needle, sizeof(needle), "<%1d, %s, ", nss_ctx->id, name);
139
140 p = strstr(user_config, needle);
141 if (!p)
142 return -1;
143
144 p += strlen(needle);
145
146 for (i = 0; i < NSS_MEMINFO_MEMTYPE_NAME_MAXLEN - 1; i++) {
147 /*
148 * Each user config is like <core_id, object_name, memory_type>,
149 * it starts with '<' and ends with '>'.
150 */
151 if (*p == '>' || *p == '\0')
152 break;
153 user_choice[i] = *p;
154 p++;
155 }
156
157 user_choice[i] = '\0';
158
159 for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++)
160 if (!strcmp(mtype_table[i], user_choice))
161 return i;
162
163 return -1;
164}
165
166/*
167 * nss_meminfo_free_block_lists()
168 * Free block node and memory associated with each each memory object.
169 */
170static void nss_meminfo_free_block_lists(struct nss_ctx_instance *nss_ctx)
171{
172 struct nss_meminfo_ctx *mem_ctx;
173 struct nss_meminfo_block_list *l;
174 int i;
175
176 mem_ctx = &nss_ctx->meminfo_ctx;
177 for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++) {
178 struct nss_meminfo_block *b;
179 l = &mem_ctx->block_lists[i];
180 b = l->head;
181 while (b) {
182 struct nss_meminfo_block *tmp;
183 /*
184 * Free IMEM/SDRAM memory.
185 */
186 switch (i) {
187 case NSS_MEMINFO_MEMTYPE_IMEM:
188 nss_meminfo_free_imem(nss_ctx, b->dma_addr, b->size);
189 break;
190 case NSS_MEMINFO_MEMTYPE_SDRAM:
191 nss_meminfo_free_sdram(nss_ctx, b->dma_addr, b->kern_addr, b->size);
192 break;
193 }
194
195 /*
196 * Free the struct nss_meminfo_block itself.
197 */
198 tmp = b;
199 b = b->next;
200 kfree(tmp);
201 }
202 }
203}
204
205/*
206 * nss_meminfo_init_block_lists()
207 * Initialize block lists and allocate memory for each block.
208 */
209static bool nss_meminfo_init_block_lists(struct nss_ctx_instance *nss_ctx)
210{
211 struct nss_meminfo_ctx *mem_ctx;
212 struct nss_meminfo_block_list *l;
213 struct nss_meminfo_request *r;
214 struct nss_meminfo_map *map;
215 int mtype;
216 unsigned long kern_addr;
217 uint32_t dma_addr;
218 int i;
219
220 mem_ctx = &nss_ctx->meminfo_ctx;
221
222 /*
223 * Fill memory type for each block list.
224 */
225 for (i = 0; i < NSS_MEMINFO_MEMTYPE_MAX; i++)
226 mem_ctx->block_lists[i].memtype = i;
227
228 map = &mem_ctx->meminfo_map;
229
230 /*
231 * Loop through all meminfo requests by checking the per-request magic.
232 */
233 for (r = map->requests; r->magic == NSS_MEMINFO_REQUEST_MAGIC; r++) {
234 struct nss_meminfo_block *b = (struct nss_meminfo_block *)
235 kmalloc(sizeof(struct nss_meminfo_block), GFP_KERNEL);
236 if (!b) {
237 nss_info_always("%p: failed to allocate meminfo block\n", nss_ctx);
238 goto cleanup;
239 }
240
241 b->index = map->num_requests++;
242 b->size = r->size;
243
244 /*
245 * Look up the user-defined memory type.
246 * Return user-defined memory type if exists. Otherwise, return -1.
247 */
248 mtype = nss_meminfo_if_user_overwrite(nss_ctx, r->name);
249 if (mtype == -1)
250 mtype = r->memtype_default;
251 r->memtype_user = mtype;
252
253 switch (mtype) {
254 case NSS_MEMINFO_MEMTYPE_IMEM:
255 /*
256 * Return SoC real address for IMEM as DMA address.
257 */
258 dma_addr = nss_meminfo_alloc_imem(nss_ctx, r->size, r->alignment);
259 if (!dma_addr) {
260 nss_info_always("%p: failed to alloc IMEM block\n", nss_ctx);
261 goto cleanup;
262 }
263
264 /*
265 * Calulate offset to the kernel address (vmap) where the
266 * whole IMEM is mapped onto instead of calling ioremap().
267 */
268 kern_addr = (unsigned long)nss_ctx->vmap + dma_addr - nss_ctx->vphys;
269 break;
270 case NSS_MEMINFO_MEMTYPE_SDRAM:
271 kern_addr = nss_meminfo_alloc_sdram(nss_ctx, r->size);
272 if (!kern_addr) {
273 nss_info_always("%p: failed to alloc SDRAM block\n", nss_ctx);
274 goto cleanup;
275 }
276
277 dma_addr = dma_map_single(nss_ctx->dev, (void *)kern_addr, r->size, DMA_TO_DEVICE);
278 if (unlikely(dma_mapping_error(nss_ctx->dev, dma_addr))) {
279 nss_info_always("%p: failed to map SDRAM block\n", nss_ctx);
280 goto cleanup;
281 }
282 break;
283 default:
284 nss_info_always("%p: %d unsupported memory type\n", nss_ctx, mtype);
285 goto cleanup;
286 }
287
288 /*
289 * Update the request with DMA address for the memory that only be used by FW.
290 */
291 r->addr = dma_addr;
292
293 /*
294 * nss_if_mem_map settings
295 */
296 if (!strcmp(r->name, "nss_if_mem_map_inst")) {
297 mem_ctx->if_map_memtype = mtype;
298 mem_ctx->if_map_dma = dma_addr;
299 mem_ctx->if_map = (struct nss_if_mem_map *)kern_addr;
300 }
301
302 /*
303 * Flush the updated meminfo request.
304 */
305 NSS_CORE_DMA_CACHE_MAINT(r, sizeof(struct nss_meminfo_request), DMA_TO_DEVICE);
306 NSS_CORE_DSB();
307
308 /*
309 * Update the list
310 */
311 l = &mem_ctx->block_lists[mtype];
312 l->num_blks++;
313 l->total_size += r->size;
314
315 b->next = l->head;
316 l->head = b;
317 }
318
319 /*
320 * Verify memory map end magic
321 */
322 if (*((uint16_t *)r) != NSS_MEMINFO_MAP_END_MAGIC)
323 goto cleanup;
324
325 return true;
326
327cleanup:
328 nss_meminfo_free_block_lists(nss_ctx);
329 return false;
330}
331
332/*
333 * nss_meminfo_init_imem()
334 * Initialize IMEM information.
335 */
336static void nss_meminfo_init_imem(struct nss_ctx_instance *nss_ctx)
337{
338 struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
339
340 mem_ctx->imem_head = NSS_IMEM_START + NSS_IMEM_SIZE * nss_ctx->id;
341 mem_ctx->imem_end = mem_ctx->imem_head + NSS_IMEM_SIZE;
342 mem_ctx->imem_tail = mem_ctx->imem_head;
343
344 nss_info("%p: IMEM init: head: 0x%x end: 0x%x tail: 0x%x\n", nss_ctx,
345 mem_ctx->imem_head, mem_ctx->imem_end, mem_ctx->imem_tail);
346}
347
348
349/*
350 * nss_meminfo_allocate_n2h_h2n_rings()
351 * Allocate N2H/H2N rings.
352 */
353static bool nss_meminfo_allocate_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx,
354 struct nss_meminfo_n2h_h2n_info *info)
355{
356 switch (info->memtype) {
357 case NSS_MEMINFO_MEMTYPE_SDRAM:
358 info->kern_addr = nss_meminfo_alloc_sdram(nss_ctx, info->total_size);
359 if (!info->kern_addr)
360 return false;
361
362 info->dma_addr = dma_map_single(nss_ctx->dev, (void *)info->kern_addr,
363 info->total_size, DMA_TO_DEVICE);
364 if (unlikely(dma_mapping_error(nss_ctx->dev, info->dma_addr))) {
365 kfree((void *)info->kern_addr);
366 return false;
367 }
368 break;
369 case NSS_MEMINFO_MEMTYPE_IMEM:
370 info->dma_addr = nss_meminfo_alloc_imem(nss_ctx, info->total_size, L1_CACHE_BYTES);
371 if (!info->dma_addr)
372 return false;
373
374 info->kern_addr = (unsigned long)(nss_ctx->vmap) + info->dma_addr - nss_ctx->vphys;
375 break;
376 default:
377 return false;
378 }
379
380 return true;
381}
382
383/*
384 * nss_meminfo_configure_n2h_h2n_rings()
385 * Configure N2H/H2N rings and if_map.
386 */
387static bool nss_meminfo_configure_n2h_h2n_rings(struct nss_ctx_instance *nss_ctx)
388{
389 struct nss_meminfo_ctx *mem_ctx = &nss_ctx->meminfo_ctx;
390 struct nss_meminfo_n2h_h2n_info *h2n_info;
391 struct nss_meminfo_n2h_h2n_info *n2h_info;
392 struct nss_if_mem_map *if_map;
393 int i;
394 int mtype;
395
396 h2n_info = &mem_ctx->h2n_info;
397 n2h_info = &mem_ctx->n2h_info;
398
399 /*
400 * Check memory type. SDRAM is the default option.
401 */
402 mtype = nss_meminfo_if_user_overwrite(nss_ctx, "h2n_rings");
403 if (mtype == -1)
404 mtype = NSS_MEMINFO_MEMTYPE_SDRAM;
405
406 h2n_info->memtype = mtype;
407
408 mtype = nss_meminfo_if_user_overwrite(nss_ctx, "n2h_rings");
409 if (mtype == -1)
410 mtype = NSS_MEMINFO_MEMTYPE_SDRAM;
411
412 n2h_info->memtype = mtype;
413
414 n2h_info->total_size = sizeof(struct n2h_descriptor) * NSS_N2H_RING_COUNT * (NSS_RING_SIZE + 2);
415 h2n_info->total_size = sizeof(struct h2n_descriptor) * NSS_H2N_RING_COUNT * (NSS_RING_SIZE + 2);
416
417 /*
418 * N2H ring allocations
419 */
420 if (!(nss_meminfo_allocate_n2h_h2n_rings(nss_ctx, n2h_info))) {
421 nss_info_always("%p: failed to allocate/map n2h rings\n", nss_ctx);
422 return false;
423 }
424
425 /*
426 * H2N ring allocations
427 */
428 if (!(nss_meminfo_allocate_n2h_h2n_rings(nss_ctx, h2n_info))) {
429 nss_info_always("%p: failed to allocate/map h2n_rings\n", nss_ctx);
430 goto cleanup;
431 }
432
433 /*
434 * Bring a fresh copy of if_map from memory in order to read it correctly.
435 */
436 if_map = mem_ctx->if_map;
437 NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_FROM_DEVICE);
438 NSS_CORE_DSB();
439
440 if_map->n2h_rings = NSS_N2H_RING_COUNT;
441 if_map->h2n_rings = NSS_H2N_RING_COUNT;
442
443 /*
444 * N2H ring settings
445 */
446 for (i = 0; i < NSS_N2H_RING_COUNT; i++) {
447 struct hlos_n2h_desc_ring *n2h_desc_ring = &nss_ctx->n2h_desc_ring[i];
448 n2h_desc_ring->desc_ring.desc = (struct n2h_descriptor *)(n2h_info->kern_addr + i * sizeof(struct n2h_descriptor) * (NSS_RING_SIZE + 2));
449 n2h_desc_ring->desc_ring.size = NSS_RING_SIZE;
450 n2h_desc_ring->hlos_index = if_map->n2h_hlos_index[i];
451
452 if_map->n2h_desc_if[i].size = NSS_RING_SIZE;
453 if_map->n2h_desc_if[i].desc_addr = n2h_info->dma_addr + i * sizeof(struct n2h_descriptor) * (NSS_RING_SIZE + 2);
454 nss_info("%p: N2H ring %d, size %d, addr = %x\n", nss_ctx, i, if_map->n2h_desc_if[i].size, if_map->n2h_desc_if[i].desc_addr);
455 }
456
457 /*
458 * H2N ring settings
459 */
460 for (i = 0; i < NSS_H2N_RING_COUNT; i++) {
461 struct hlos_h2n_desc_rings *h2n_desc_ring = &nss_ctx->h2n_desc_rings[i];
462 h2n_desc_ring->desc_ring.desc = (struct h2n_descriptor *)(h2n_info->kern_addr + i * sizeof(struct h2n_descriptor) * (NSS_RING_SIZE + 2));
463 h2n_desc_ring->desc_ring.size = NSS_RING_SIZE;
464 h2n_desc_ring->hlos_index = if_map->h2n_hlos_index[i];
465 spin_lock_init(&h2n_desc_ring->lock);
466
467 if_map->h2n_desc_if[i].size = NSS_RING_SIZE;
468 if_map->h2n_desc_if[i].desc_addr = h2n_info->dma_addr + i * sizeof(struct h2n_descriptor) * (NSS_RING_SIZE + 2);
469 nss_info("%p: H2N ring %d, size %d, addr = %x\n", nss_ctx, i, if_map->h2n_desc_if[i].size, if_map->h2n_desc_if[i].desc_addr);
470 }
471
472 /*
473 * Flush the updated nss_if_mem_map.
474 */
475 NSS_CORE_DMA_CACHE_MAINT((void *)if_map, sizeof(struct nss_if_mem_map), DMA_TO_DEVICE);
476 NSS_CORE_DSB();
477
478 return true;
479
480cleanup:
481 if (n2h_info->memtype == NSS_MEMINFO_MEMTYPE_SDRAM)
482 nss_meminfo_free_sdram(nss_ctx, n2h_info->dma_addr, n2h_info->kern_addr, n2h_info->total_size);
483 else
484 nss_meminfo_free_imem(nss_ctx, n2h_info->dma_addr, n2h_info->total_size);
485
486 nss_meminfo_free_block_lists(nss_ctx);
487 return false;
488}
489
490/*
491 * nss_meminfo_config_show()
492 * function to show meinfo configuration per core.
493 */
494static int nss_meminfo_config_show(struct seq_file *seq, void *v)
495{
496 struct nss_ctx_instance *nss_ctx;
497 struct nss_meminfo_ctx *mem_ctx;
498 struct nss_meminfo_n2h_h2n_info *n2h_info;
499 struct nss_meminfo_n2h_h2n_info *h2n_info;
500 struct nss_meminfo_map *map;
501 struct nss_meminfo_request *r;
502 int nss_id;
503 int i;
504
505 /*
506 * i_private is passed to us by debug_fs_create()
507 */
508 nss_id = (int)(nss_ptr_t)seq->private;
509 if (nss_id < 0 || nss_id >= NSS_MAX_CORES) {
510 nss_warning("nss_id: %d is not valid\n", nss_id);
511 return -ENODEV;
512 }
513
514 nss_ctx = &nss_top_main.nss[nss_id];
515 NSS_VERIFY_CTX_MAGIC(nss_ctx);
516
517 mem_ctx = &nss_ctx->meminfo_ctx;
518 map = &mem_ctx->meminfo_map;
519 n2h_info = &mem_ctx->n2h_info;
520 h2n_info = &mem_ctx->h2n_info;
521
522 seq_printf(seq, "%-5s %-32s %-7s %-7s %-10s %-10s\n",
523 "Index", "Name", "Default", "User", "Size", "DMA Addr");
524 seq_printf(seq, "%-5s %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
525 "N/A", "n2h_rings", "SDRAM",
526 nss_meminfo_memtype_table[n2h_info->memtype],
527 n2h_info->total_size, n2h_info->dma_addr);
528 seq_printf(seq, "%-5s %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
529 "N/A", "h2n_rings", "SDRAM",
530 nss_meminfo_memtype_table[h2n_info->memtype],
531 h2n_info->total_size, h2n_info->dma_addr);
532
533 r = map->requests;
534 for (i = 0; i < map->num_requests; i++) {
535 seq_printf(seq, "%-5d %-32s %-7s %-7s 0x%-8x 0x%-8x\n",
536 i, r[i].name,
537 nss_meminfo_memtype_table[r[i].memtype_default],
538 nss_meminfo_memtype_table[r[i].memtype_user],
539 r[i].size, r[i].addr);
540 }
541
542 seq_printf(seq, "Available IMEM: 0x%x\n", mem_ctx->imem_end - mem_ctx->imem_tail);
543 seq_printf(seq, "How to configure? \n");
544 seq_printf(seq, "Overwrite the /etc/modules.d/32-qca-nss-drv with following contents then reboot\n\n");
545 seq_printf(seq, "qca-nss-drv meminfo_user_config=\"<core_id, name, memory_type>, ..\"\n\n");
546 seq_printf(seq, "For example, <1, h2n_rings, IMEM> stands for: h2n_rings of core 1 is on IMEM\n");
547
548 return 0;
549}
550
551/*
552 * nss_meminfo_debugfs_file_open()
553 * function to open meminfo debugfs.
554 */
555static int nss_meminfo_debugfs_file_open(struct inode *inode, struct file *file)
556{
557 return single_open(file, nss_meminfo_config_show, inode->i_private);
558}
559
560static struct file_operations nss_meminfo_debugfs_ops = {
561 .owner = THIS_MODULE,
562 .open = nss_meminfo_debugfs_file_open,
563 .read = seq_read,
564 .llseek = seq_lseek,
565 .release = single_release,
566};
567
568/*
569 * nss_meminfo_init_debugfs()
570 * Init meminfo debugfs.
571 */
572static void nss_meminfo_init_debugfs(struct nss_ctx_instance *nss_ctx)
573{
574 int i;
575 struct dentry *meminfo_main_dentry;
576 struct dentry *meminfo_core_dentries[NSS_MAX_CORES];
577
578 if (nss_meminfo_debugfs_exist)
579 return;
580
581 /*
582 * Create directory for showing meminfo configuration of each core.
583 */
584 meminfo_main_dentry = debugfs_create_dir("meminfo", nss_top_main.top_dentry);
585 if (unlikely(!meminfo_main_dentry)) {
586 nss_warning("Failed to create qca-nss-drv/meminfo directory in debugfs\n");
587 return;
588 }
589
590 for (i = 0; i < NSS_MAX_CORES; i++) {
591 char file[10];
592 snprintf(file, sizeof(file), "core%d", i);
593 meminfo_core_dentries[i] = debugfs_create_file(file, 0400, meminfo_main_dentry,
594 (void *)(nss_ptr_t)i, &nss_meminfo_debugfs_ops);
595 if (unlikely(!meminfo_core_dentries[i])) {
596 int j;
597 for (j = 0; j < i; j++)
598 debugfs_remove(meminfo_core_dentries[j]);
599 debugfs_remove(meminfo_main_dentry);
600 nss_warning("Failed to create qca-nss-drv/meminfo/%s file in debugfs", file);
601 return;
602 }
603 }
604
605 nss_meminfo_debugfs_exist = true;
606 nss_info("nss meminfo user config: %s\n", nss_meminfo_user_config);
607}
608
609/*
610 * nss_meminfo_init
611 * Initilization
612 *
613 */
614bool nss_meminfo_init(struct nss_ctx_instance *nss_ctx)
615{
616 struct nss_meminfo_ctx *mem_ctx;
617 uint32_t *meminfo_start;
618 struct nss_meminfo_map *map;
619
620 NSS_VERIFY_CTX_MAGIC(nss_ctx);
621 mem_ctx = &nss_ctx->meminfo_ctx;
622
623 /*
624 * meminfo_start is the label where the start address of meminfo map is stored.
625 */
626 meminfo_start = (uint32_t *)ioremap_nocache(nss_ctx->load + NSS_MEMINFO_MAP_START_OFFSET,
627 NSS_MEMINFO_RESERVE_AREA_SIZE);
628 if (!meminfo_start) {
629 nss_info_always("%p: cannot remap meminfo start\n", nss_ctx);
630 return false;
631 }
632
633 /*
634 * Check meminfo start magic
635 */
636 if ((uint16_t)meminfo_start[0] != NSS_MEMINFO_RESERVE_AREA_MAGIC) {
637 nss_info_always("%p: failed to verify meminfo start magic\n", nss_ctx);
638 return false;
639 }
640
641 map = &mem_ctx->meminfo_map;
642 map->start = (uint32_t *)ioremap_cache(meminfo_start[1], NSS_MEMINFO_MAP_SIZE);
643 if (!map->start) {
644 nss_info_always("%p: failed to remap meminfo map\n", nss_ctx);
645 return false;
646 }
647
648 /*
649 * Check meminfo map magic
650 */
651 if ((uint16_t)map->start[0] != NSS_MEMINFO_MAP_START_MAGIC) {
652 nss_info_always("%p: failed to verify meminfo map magic\n", nss_ctx);
653 return false;
654 }
655
656 /*
657 * Meminfo map settings
658 */
659 map->num_requests = 0;
660 map->requests = (struct nss_meminfo_request *)(map->start + 1);
661
662 /*
663 * Init IMEM
664 */
665 nss_meminfo_init_imem(nss_ctx);
666
667 /*
668 * Init meminfo block lists
669 */
670 if (!nss_meminfo_init_block_lists(nss_ctx)) {
671 nss_info_always("%p: failed to initialize meminfo block lists\n", nss_ctx);
672 return false;
673 }
674
675 /*
676 * Configure N2H/H2N rings and nss_if_mem_map
677 */
678 if (!nss_meminfo_configure_n2h_h2n_rings(nss_ctx))
679 return false;
680
681 nss_meminfo_init_debugfs(nss_ctx);
682
683 nss_info_always("%p: meminfo init succeed\n", nss_ctx);
684 return true;
685}