first code checkin for qca-ssdk component
Signed-off-by: Yue Lun <luny@codeaurora.org>
diff --git a/ChangeLog b/ChangeLog
new file mode 100644
index 0000000..547dba4
--- /dev/null
+++ b/ChangeLog
@@ -0,0 +1,129 @@
+============================================================
+Changes for SSDK 1.0.3:
+============================================================
+
+* Support HORUS:
+ - Add chip type HORUS and related source code.
+
+
+
+
+============================================================
+Changes for SSDK 1.0.4:
+============================================================
+
+* Support ISIS:
+ - Add chip type ISIS and related source code.
+
+
+
+
+============================================================
+Changes for SSDK 1.0.5:
+============================================================
+
+* Speed up FDB entry next operation.
+* Support linux 2.6.31 version.
+
+
+
+
+============================================================
+Changes for SSDK 1.0.6:
+============================================================
+
+* New APIs pppoe_session_id_set/get are supported for ISIS chip.
+* Fix parameter speed check bug in API isis_port_speed_set.
+
+
+
+
+============================================================
+Changes for SSDK 1.0.7:
+============================================================
+* Fix address bytes order bug in API _isis_ip6_base_addr_set/get.
+* Change the socket call for user space and kernel communication to nonblocking way.
+* Remove force routing function for ISIS acl action.
+* Add configuration for ISIS register accessing speed up feature in ./config file.
+* Add configuration for ISIS NAT helper feature in ./config.file.
+
+
+
+
+============================================================
+Changes for SSDK 1.0.8:
+============================================================
+* Offer ioctl based method for linux kernel&user space communication
+* Remove some port property logic limitation for ISIS.
+* Remove FDB CRC mode setting in ISIS init.
+* Add some operation mode flag for ISIS NAPT entry next operation.
+* Add some operation mode flag for ISIS NAPT del opertion.
+* Fix one bug for fdb entry extendnext command parsing when shell works at slient mode.
+* Fix one bug in ISIS ACL rule delete operation(isis_acl_rule_delete).
+* Fix one bug in ISIS queue shapper get operation(isis_rate_queue_shaper_get).
+* Add new API for ISIS MAC based VLAN translation.(isis_port_mac_vlan_xlt_set/isis_port_mac_vlan_xlt_get).
+* Add new API for ISIS add/delete port to/from an exist FDB entry.(isis_fdb_port_add/isis_fdb_port_del).
+* Add new API for ISIS ACL rules active/deactive. (isis_acl_rule_active/isis_acl_rule_deactive).
+* Add new API for ISIS wcmp hash mode setting. (isis_ip_wcmp_hash_mode_set/isis_ip_wcmp_hash_mode_get).
+* Add new API for ISIS host entry aging time setting. (isis_ip_age_time_set/isis_ip_age_time_get).
+* Add new API for ISIS interrupt operation. (isis_intr_mask_set/isis_intr_mask_get/isis_intr_status_get/
+ isis_intr_status_clear/isis_intr_port_link_mask_set/isis_intr_port_link_mask_get/isis_intr_port_link_status_get).
+* Add new API for ISIS port MAC mode setting. (isis_interface_mac_mode_set/isis_interface_mac_mode_get).
+* Add new API for ISIS port PHY mode setting. (isis_interface_phy_mode_set/isis_interface_phy_mode_get).
+* Add new API for ISIS 802.3az setting. (isis_port_3az_status_set/isis_port_3az_status_get).
+* Add new API for ISIS link status getting. (isis_port_link_status_get).
+* Add new API for ISIS MAC TX status setting. (isis_port_txmac_status_set/isis_port_txmac_status_get).
+* Add new API for ISIS MAC RX status setting. (isis_port_rxmac_status_set/isis_port_rxmac_status_get).
+* Add new API for ISIS MAC TX flow control setting. (isis_port_txfc_status_set/isis_port_txfc_status_get).
+* Add new API for ISIS MAC RX flow control setting. (isis_port_rxfc_status_set/isis_port_rxfc_status_get).
+* Add new API for ISIS MAC back pressure setting. (isis_port_bp_status_set/isis_port_bp_status_get).
+* Add new API for ISIS link force mode setting. (isis_port_link_forcemode_set/isis_port_link_forcemode_get).
+* Fix one bug in Giga PHY device autoneg ability setting operation.
+* Makefile change for ISIS NAT helper refactoring.
+
+============================================================
+Changes for SSDK 1.1.x:
+============================================================
+* Add support for QCA833x family (ISISC, S17c).
+* Add support for out-of-band register access through ethernet packets with Atheros header. (S17/S17c)
+* Add IPV6 Hardware Routing (ISISC, S17c).
+* Add new API for set/get status of one ACL rule source filter. (S17c only)
+* Add new API for set/get arl search mode as ivl or svl when vlan invalid. (S17c only)
+* Add new API for interface control:
+fal_interface_fx100_ctrl_set/fal_interface_fx100_ctrl_get/fal_interface_fx100_status_get/fal_interface_fx100_status_set/fal_interface_mac06_exch_get/fal_interface_mac06_exch_set. (S17c only)
+* Add new API for MIB counter:
+fal_mib_port_flush_counters/fal_mib_cpukeep_set/fal_mib_cpukeep_get. (S17c only)
+*Add new API for Misc:
+fal_intr_mask_mac_linkchg_set/fal_intr_mask_mac_linkchg_get/fal_intr_status_mac_linkchg_get/fal_cpu_vid_en_set/fal_cpu_vid_en_get/fal_rtd_pppoe_en_set/fal_rtd_pppoe_en_get/fal_intr_status_mac_linkchg_clear (S17c only)
+* Add new API for nat: nat_prv_base_mask_set/nat_prv_base_mask_get. (S17c only)
+* Add new API for port ctrl:
+fal_port_mac_loopback_set/fal_port_mac_loopback_set. (S17c only)
+* Add new API for port vlan:
+fal_netisolate_set/fal_netisolate_get/fal_eg_trans_filter_bypass_en_set/fal_eg_trans_filter_bypass_en_get. (S17c only)
+* Add new API for QoS:
+fal_qos_port_force_spri_status_set/fal_qos_port_force_spri_status_get/fal_qos_port_force_cpri_status_set/fal_qos_port_force_cpri_status_get. (S17c only)
+* Add new API for Rate limit:
+fal_rate_port_add_rate_byte_set/fal_rate_port_add_rate_byte_get/fal_rate_port_gol_flow_en_set/fal_rate_port_gol_flow_en_get.
+
+============================================================
+Changes for SSDK 1.1.1:
+============================================================
+* Add IGMP mldv2 support
+
+============================================================
+Changes for SSDK 1.1.2:
+============================================================
+* Add API for Trunk support
+* Add API for MAC loopback support
+
+============================================================
+Changes for SSDK 1.1.3:
+============================================================
+* Support CHIP_TYPE=ALL_CHIP
+============================================================
+Changes for SSDK 1.1.3.2:
+============================================================
+* Add hsl_shared_api.h (sync from Perforce server)
+* Add support for Linux Kernel 3.2.0
+* Add support for LITTLE ENDIAN (especially for HNAT)
+* Add support for ARM CPU
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..acf59b5
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,51 @@
+include ./config
+
+ifndef PRJ_PATH
+ PRJ_PATH=$(shell pwd)
+endif
+export PRJ_PATH
+
+include ./make/config.mk
+include ./make/tools.mk
+include ./make/$(OS)_opt.mk
+
+SUB_DIR=$(patsubst %/, %, $(dir $(wildcard src/*/Makefile)))
+SUB_LIB=$(subst src/, , $(SUB_DIR))
+
+all: $(BIN_DIR) kslib uslib shell
+ mkdir -p ./temp/;cd ./temp;cp ../build/bin/ssdk_ks_km.a ./;ar -x ssdk_ks_km.a; cp ../ko_Makefile ./Makefile;
+ make -C $(SYS_PATH) M=$(PRJ_PATH)/temp/ CROSS_COMPILE=arm-openwrt-linux-uclibcgnueabi- modules
+ cp temp/*.ko build/bin;pwd; ls;
+ #rm -Rf ./temp .tmp_versions *.symvers *.order *.mod.c *.o;
+ @echo "---Build [SSDK-$(VERSION)] at $(BUILD_DATE) finished."
+
+kslib:kslib_o
+ $(AR) -r $(BIN_DIR)/$(KS_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/KSLIB/*.o)
+
+kslib_o:
+ $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=KSLIB -C src/$i all || exit 1;)
+
+uslib:uslib_o
+ $(AR) -r $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a $(wildcard $(BLD_DIR)/USLIB/*.o)
+
+uslib_o:
+ $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=USLIB -C src/$i all || exit 1;)
+
+shell:uslib shell_o
+ $(CP) $(BLD_DIR)/SHELL/$(SHELLOBJ) $(BIN_DIR)/$(SHELLOBJ)
+ $(STRIP) $(BIN_DIR)/$(SHELLOBJ)
+
+shell_o:
+ $(foreach i, $(SUB_LIB), $(MAKE) MODULE_TYPE=SHELL -C src/$i all || exit 1;)
+
+$(BIN_DIR):
+ $(MKDIR) -p $@
+
+release:
+ @cd make; ./release.sh $(VER)
+
+clean:
+ $(RM) -f $(BLD_DIR)/KSLIB/*
+ $(RM) -f $(BLD_DIR)/USLIB/*
+ $(RM) -f $(BLD_DIR)/SHELL/*
+ $(RM) -f $(BIN_DIR)/*
diff --git a/app/nathelper/linux/host_helper.c b/app/nathelper/linux/host_helper.c
new file mode 100644
index 0000000..588c7e4
--- /dev/null
+++ b/app/nathelper/linux/host_helper.c
@@ -0,0 +1,1615 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/netfilter_arp.h>
+#include <linux/inetdevice.h>
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <linux/in.h>
+#include <linux/ip.h>
+#include <linux/udp.h>
+#include <linux/tcp.h>
+#include <linux/icmp.h>
+#ifdef KVER32
+#include <linux/export.h>
+#endif
+#include <net/netfilter/nf_conntrack.h>
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#include <linux/if_vlan.h>
+#endif
+#if defined (CONFIG_BRIDGE)
+#include <net/bridge/br_private.h>
+#endif
+#include <linux/ppp_defs.h>
+#include <linux/filter.h>
+#include <linux/if_pppox.h>
+#include <linux/if_ppp.h>
+#include <linux/ppp_channel.h>
+#include <linux/ppp-comp.h>
+#include <net/sock.h>
+#include <net/route.h>
+#include <net/netevent.h>
+#include <net/ipv6.h>
+#include <net/ip_fib.h>
+#include "hsl_api.h"
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl.h"
+#include "nat_helper.h"
+#include "napt_acl.h"
+#include "lib/nat_helper_hsl.h"
+#include "lib/nat_helper_dt.h"
+#include "hsl_shared_api.h"
+
+#ifdef ISISC
+#define CONFIG_IPV6_HWACCEL 1
+#else
+#undef CONFIG_IPV6_HWACCEL
+#endif
+
+#ifdef CONFIG_IPV6_HWACCEL
+#include <net/ndisc.h>
+#include <net/neighbour.h>
+#include <net/netevent.h>
+#include <net/ipv6.h>
+#include <net/ip6_route.h>
+#include <linux/ipv6.h>
+#include <linux/netfilter_ipv6.h>
+#endif
+
+#define MAC_LEN 6
+#define IP_LEN 4
+#define ARP_HEADER_LEN 8
+
+#define ARP_ENTRY_MAX 128
+
+/* P6 is used by loop dev. */
+#define S17_P6PAD_MODE_REG_VALUE 0x01000000
+
+#define MULTIROUTE_WR
+
+extern struct net init_net;
+
+char *nat_wan_dev_list = "eth0.2";
+char *nat_lan_dev_list = "eth0.1";
+
+static int wan_fid = 0xffff;
+static fal_pppoe_session_t pppoetbl = {0};
+static uint32_t pppoe_gwid = 0;
+static char nat_bridge_dev[IFNAMSIZ*4];
+static uint8_t lanip[4] = {0}, wanip[4] = {0};
+static struct in6_addr wan6ip = IN6ADDR_ANY_INIT;
+static struct in6_addr lan6ip = IN6ADDR_ANY_INIT;
+
+#ifdef ISISC
+struct ipv6_default_route_binding
+{
+ struct in6_addr next_hop;
+ uint32_t nh_entry_id;
+};
+#endif
+
+#ifdef MULTIROUTE_WR
+#define MAX_HOST 8
+struct wan_next_hop
+{
+ u_int32_t host_ip;
+ u_int32_t entry_id;
+ u_int32_t in_acl;
+ u_int32_t in_use;
+ u_int8_t host_mac[6];
+};
+static struct net_device *multi_route_indev = NULL;
+static struct wan_next_hop wan_nh_ent[MAX_HOST] = {{0}};
+
+static int wan_nh_get(u_int32_t host_ip)
+{
+ int i;
+
+ host_ip = htonl(host_ip);
+
+ for (i=0; i<MAX_HOST; i++)
+ {
+ if ((wan_nh_ent[i].host_ip != 0) && !memcmp(&wan_nh_ent[i].host_ip, &host_ip, 4))
+ {
+ // printk("%s %d\n", __FUNCTION__, __LINE__);
+ // if ((wan_nh_ent[i].entry_id != 0) && (wan_nh_ent[i].in_acl != 1))
+ if (wan_nh_ent[i].in_acl != 1)
+ {
+ wan_nh_ent[i].in_acl = 1;
+
+ return i;
+ }
+ // printk("%s %d\n", __FUNCTION__, __LINE__);
+ }
+ printk("%s %d wan_nh_ent 0x%08x host_ip 0x%08x\n", __FUNCTION__, __LINE__, wan_nh_ent[i].host_ip, host_ip);
+ }
+
+ return -1;
+}
+
+static void wan_nh_add(u_int8_t *host_ip , u_int8_t *host_mac, u_int32_t id)
+{
+ int i;
+
+ for( i = 0 ; i < MAX_HOST ; i++ )
+ {
+ if((wan_nh_ent[i].host_ip != 0) && !memcmp(&wan_nh_ent[i].host_ip, host_ip, 4))
+ {
+ if (host_mac == NULL) break;
+
+ if(!memcmp(&wan_nh_ent[i].host_mac, host_mac,6))
+ return;
+ else
+ break ;
+ }
+
+ if(wan_nh_ent[i].host_ip == 0)
+ break;
+ }
+
+ if (i < MAX_HOST)
+ {
+ if ((wan_nh_ent[i].in_use) && (wan_nh_ent[i].in_acl)) return;
+
+ memcpy(&wan_nh_ent[i].host_ip, host_ip, 4);
+ if (host_mac != NULL)
+ {
+ memcpy(wan_nh_ent[i].host_mac, host_mac, 6);
+ wan_nh_ent[i].entry_id = id;
+ if ((wan_nh_ent[i].in_use) && !(wan_nh_ent[i].in_acl))
+ {
+ droute_add_acl_rules(*(uint32_t *)&lanip, id);
+ /* set the in_acl flag */
+ wan_nh_ent[i].in_acl = 1;
+ }
+ }
+ else
+ {
+ /* set the in_use flag */
+ wan_nh_ent[i].in_use = 1;
+ }
+ aos_printk("%s: ip %08x (%d)\n" ,__func__, wan_nh_ent[i].host_ip, i);
+ }
+}
+
+static uint32_t get_next_hop( uint32_t daddr , uint32_t saddr )
+{
+ struct fib_result res;
+#ifdef KVER32
+ struct flowi4 fl =
+ {
+ .flowi4_iif = multi_route_indev->ifindex,
+ .flowi4_mark = 0,
+ .flowi4_tos = 0,
+ .flowi4_scope = RT_SCOPE_UNIVERSE,
+ .daddr = htonl(daddr),
+ .saddr = htonl(saddr),
+ };
+#else
+ struct flowi fl = { .nl_u = { .ip4_u =
+ {
+ .daddr = daddr,
+ .saddr = saddr,
+ .tos = 0,
+ .scope = RT_SCOPE_UNIVERSE,
+ }
+ },
+ .mark = 0,
+ .iif = multi_route_indev->ifindex
+ };
+#endif
+ struct net * net = dev_net(multi_route_indev);
+ struct fib_nh *mrnh = NULL;
+
+ if (fib_lookup(net, &fl, &res) != 0)
+ {
+ return 0;
+ }
+ else
+ {
+ mrnh = res.fi->fib_nh;
+ if (NULL == mrnh)
+ {
+ return 0;
+ }
+ }
+
+ return ntohl(mrnh->nh_gw);
+}
+
+uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr)
+{
+ sw_error_t rv;
+
+ /* search for the next hop (s) */
+ if (!(get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE)))
+ {
+ if (multi_route_indev && \
+ (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOE) && (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOES0))
+ {
+ uint32_t next_hop = get_next_hop(dst_addr, src_addr);
+
+ aos_printk("Next hop: %08x\n", next_hop);
+ if (next_hop != 0)
+ {
+ fal_host_entry_t arp_entry;
+
+ memset(&arp_entry, 0, sizeof(arp_entry));
+ arp_entry.ip4_addr = next_hop;
+ arp_entry.flags = FAL_IP_IP4_ADDR;
+ rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &arp_entry);
+ if (rv != SW_OK)
+ {
+ printk("%s: IP_HOST_GET error... (non-existed host: %08x?) \n", __func__, next_hop);
+ /* add into the nh_ent */
+ wan_nh_add((u_int8_t *)&next_hop, (u_int8_t *)NULL, 0);
+ }
+ else
+ {
+ if (wan_nh_get(next_hop) != -1)
+ droute_add_acl_rules(*(uint32_t *)&lanip, arp_entry.entry_id);
+ else
+ printk("%s %d\n", __FUNCTION__, __LINE__);
+ }
+ }
+ else
+ {
+ aos_printk("no need to set the default route... \n");
+ // set_aclrulemask (S17_ACL_LIST_DROUTE);
+ }
+ }
+ else
+ {
+ printk("multi_route_indev %p nf_athrs17_hnat_wan_type %d\n", multi_route_indev, nf_athrs17_hnat_wan_type);
+ }
+ }
+ /* end next hop (s) */
+
+ return SW_OK;
+}
+#endif /* MULTIROUTE_WR */
+
+static void qcaswitch_hostentry_flush(void)
+{
+ fal_host_entry_t hostentry;
+ sw_error_t ret;
+
+ do
+ {
+ memset(&hostentry, 0, sizeof(fal_host_entry_t));
+ hostentry.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ ret = IP_HOST_NEXT (0, FAL_IP_ENTRY_ID_EN, &hostentry);
+ if (SW_OK == ret)
+ {
+ IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, &hostentry);
+ }
+ }while (SW_OK == ret);
+
+ return;
+}
+
+#ifdef CONFIG_IPV6_HWACCEL /* only for S17c */
+static struct in6_addr* get_ipv6_default_gateway(void)
+{
+ /* ip_route_output_key can't return correct default nexhop
+ * routes are less than 4 and it only searches in route
+ * hash, not in fib, so use fib_lookup.
+ */
+ struct in6_addr *ip6addr = NULL;
+ struct in6_addr des_addr = IN6ADDR_ANY_INIT;
+ struct rt6_info *rt = rt6_lookup(&init_net, &des_addr, NULL, 0, 0);
+
+ if (rt)
+ {
+ ip6addr = &rt->rt6i_gateway;
+ }
+
+ return ip6addr;
+}
+
+static int add_pppoev6_host_entry(void)
+{
+ struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT;
+ unsigned long flags;
+ int ppp_sid, ppp_sid2;
+ unsigned char ppp_peer_mac[ETH_ALEN];
+ unsigned char ppp_peer_mac2[ETH_ALEN];
+ a_uint32_t ppp_peer_ip = 0;
+ int wvid;
+ fal_host_entry_t nh_arp_entry;
+ sw_error_t rv;
+ a_uint32_t droute_entry_id = 0;
+ a_bool_t ena;
+ static fal_pppoe_session_t pppoev6_sid_table = {0};
+ struct in6_addr *next_hop;
+
+ local_irq_save(flags);
+ memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr));
+ ppp_sid2 = nf_athrs17_hnat_ppp_id2;
+ ppp_sid = nf_athrs17_hnat_ppp_id;
+ ppp_peer_ip = nf_athrs17_hnat_ppp_peer_ip;
+ memcpy(ppp_peer_mac, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+ memcpy(ppp_peer_mac2, nf_athrs17_hnat_ppp_peer_mac2, ETH_ALEN);
+ wvid = wan_fid;
+ local_irq_restore(flags);
+
+ if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type)
+ {
+ return SW_BAD_STATE;
+ }
+
+ if (__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY)
+ {
+ /* Cannot get lanip6 successfully. */
+ return SW_BAD_STATE;
+ }
+ if (0xffff == wvid)
+ {
+ printk("%s: Cannot get WAN vid!\n", __FUNCTION__);
+ return SW_FAIL;
+ }
+
+ if (0 == nf_athrs17_hnat_ppp_peer_ip)
+ {
+ return SW_FAIL;
+ }
+
+ next_hop = get_ipv6_default_gateway();
+ if (NULL == next_hop)
+ {
+ printk("No IPv6 Gateway!\n");
+ return SW_BAD_STATE;
+ }
+
+ if (0 != ppp_sid)
+ {
+ if ((ppp_sid == ppp_sid2)||(0 == ppp_sid2)) /* v4 and v6 have the same session id */
+ {
+ memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+ nh_arp_entry.ip4_addr = ppp_peer_ip;
+ nh_arp_entry.flags = FAL_IP_IP4_ADDR;
+ rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+ if (rv != SW_OK)
+ {
+ printk("%s: IP_HOST_GET error (0x%08x)\n", __func__, ppp_peer_ip);
+ if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+ {
+ if (!ena)
+ {
+ if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK)
+ {
+ aos_printk("Cannot enable the PPPoE mode\n");
+ return SW_FAIL;
+ }
+ }
+ }
+ pppoev6_sid_table.session_id = ppp_sid;
+ pppoev6_sid_table.multi_session = 1;
+ pppoev6_sid_table.uni_session = 1;
+ pppoev6_sid_table.entry_id = 0;
+ /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+ rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table);
+ if (rv == SW_OK)
+ {
+ a_int32_t a_entry_id = -1;
+
+ PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id);
+ aos_printk("pppoe session: %d, entry_id: %d\n",
+ pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id);
+ /* create the peer host ARP entry */
+ a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)&ppp_peer_ip, (void *)ppp_peer_mac, 0);
+ if (a_entry_id >= 0) /* hostentry creation okay */
+ {
+ rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE);
+ if ( rv != SW_OK)
+ {
+ aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n",
+ a_entry_id, rv);
+ PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+ return SW_FAIL;
+ }
+ droute_entry_id = a_entry_id;
+ }
+ else
+ {
+ PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ aos_printk("PPPoE session add failed.. (id: %d)\n",
+ pppoev6_sid_table.session_id);
+ aos_printk("rv: %d\n", rv);
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ droute_entry_id = nh_arp_entry.entry_id;
+ }
+ ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id);
+ }
+ else /* Not the same session id */
+ {
+ if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+ {
+ if (!ena)
+ {
+ if (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK)
+ {
+ aos_printk("Cannot enable the PPPoE mode\n");
+ return SW_FAIL;
+ }
+ }
+ }
+ memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+ memcpy((void *)&nh_arp_entry.ip6_addr, (void *)next_hop, sizeof(nh_arp_entry.ip6_addr));
+ nh_arp_entry.flags = FAL_IP_IP6_ADDR;
+ rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+ if (rv != SW_OK)
+ {
+ /* ARP alread setup. */
+ return SW_OK;
+ }
+ pppoev6_sid_table.session_id = ppp_sid2;
+ pppoev6_sid_table.multi_session = 1;
+ pppoev6_sid_table.uni_session = 1;
+ pppoev6_sid_table.entry_id = 0;
+ /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+ rv = PPPOE_SESSION_TABLE_ADD(0, &pppoev6_sid_table);
+ if (rv == SW_OK)
+ {
+ a_int32_t a_entry_id = -1;
+
+ PPPOE_SESSION_ID_SET(0, pppoev6_sid_table.entry_id, pppoev6_sid_table.session_id);
+ aos_printk("pppoe session: %d, entry_id: %d\n",
+ pppoev6_sid_table.session_id, pppoev6_sid_table.entry_id);
+ /* create the peer host ARP entry */
+ a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, (void *)next_hop, ppp_peer_mac2, 1);
+ if (a_entry_id >= 0) /* hostentry creation okay */
+ {
+ rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoev6_sid_table.entry_id, A_TRUE);
+ if ( rv != SW_OK)
+ {
+ aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n",
+ a_entry_id, rv);
+ PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+ return SW_FAIL;
+ }
+ droute_entry_id = a_entry_id;
+ }
+ else
+ {
+ PPPOE_SESSION_TABLE_DEL(0, &pppoev6_sid_table);
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ aos_printk("PPPoE session add failed.. (id: %d)\n",
+ pppoev6_sid_table.session_id);
+ aos_printk("rv: %d\n", rv);
+ return SW_FAIL;
+ }
+ ipv6_droute_add_acl_rules(&local_lan6ip, droute_entry_id);
+ }
+ }
+
+ return SW_OK;
+}
+
+uint32_t napt_set_ipv6_default_route(void)
+{
+ sw_error_t rv;
+ static a_bool_t ipv6_droute_setup = A_FALSE;
+ static struct ipv6_default_route_binding ipv6_droute_bind = {IN6ADDR_ANY_INIT,0};
+ struct in6_addr local_lan6ip = IN6ADDR_ANY_INIT;
+ unsigned long flags;
+
+ /* search for the next hop (s)*/
+ if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type)
+ {
+ struct in6_addr *next_hop = get_ipv6_default_gateway();
+
+ // printk("IPv6 next hop: %pI6\n", next_hop);
+
+ if (next_hop != NULL)
+ {
+ fal_host_entry_t ipv6_neigh_entry;
+
+ if (__ipv6_addr_type(next_hop) == IPV6_ADDR_LINKLOCAL)
+ return SW_OK;
+
+ local_irq_save(flags);
+ memcpy(&local_lan6ip, &lan6ip, sizeof(struct in6_addr));
+ local_irq_restore(flags);
+
+ memset(&ipv6_neigh_entry, 0, sizeof(ipv6_neigh_entry));
+ memcpy(&ipv6_neigh_entry.ip6_addr, next_hop, 16);
+ ipv6_neigh_entry.flags = FAL_IP_IP6_ADDR;
+ rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &ipv6_neigh_entry);
+ if ((rv != SW_OK)||(__ipv6_addr_type(&local_lan6ip) == IPV6_ADDR_ANY))
+ {
+ if (ipv6_droute_setup)
+ {
+ ipv6_droute_del_acl_rules();
+ memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind));
+ ipv6_droute_setup = A_FALSE;
+ }
+ }
+ else
+ {
+ if (ipv6_droute_setup)
+ {
+ if (!ipv6_addr_equal(&ipv6_droute_bind.next_hop, next_hop) ||
+ ipv6_droute_bind.nh_entry_id != ipv6_neigh_entry.entry_id)
+ {
+ ipv6_droute_del_acl_rules();
+ }
+ }
+ ipv6_droute_bind.next_hop = *next_hop;
+ ipv6_droute_bind.nh_entry_id = ipv6_neigh_entry.entry_id;
+
+ ipv6_droute_add_acl_rules(&local_lan6ip, ipv6_neigh_entry.entry_id);
+ ipv6_droute_setup = A_TRUE;
+ }
+ }
+ else
+ {
+ if (ipv6_droute_setup)
+ {
+ ipv6_droute_del_acl_rules();
+ memset(&ipv6_droute_bind, 0, sizeof(ipv6_droute_bind));
+ ipv6_droute_setup = A_FALSE;
+ }
+ }
+ }
+ else if (NF_S17_WAN_TYPE_IP == nf_athrs17_hnat_wan_type)
+ {
+ add_pppoev6_host_entry();
+ }
+
+ return SW_OK;
+}
+#endif /* ifdef CONFIG_IPV6_HWACCEL */
+
+static sw_error_t setup_interface_entry(char *list_if, int is_wan)
+{
+ char temp[IFNAMSIZ*4]; /* Max 4 interface entries right now. */
+ char *dev_name, *list_all;
+ struct net_device *nat_dev;
+ struct in_device *in_device_lan = NULL;
+ uint8_t *devmac, if_mac_addr[MAC_LEN];
+ char *br_name;
+ uint32_t vid = 0;
+ sw_error_t setup_error;
+ uint32_t ipv6 = 0;
+
+ memcpy(temp, list_if, strlen(list_if)+1);
+ list_all = temp;
+
+ setup_error = SW_FAIL;
+ while ((dev_name = strsep(&list_all, " ")) != NULL)
+ {
+ nat_dev = dev_get_by_name(&init_net, dev_name);
+ if (NULL == nat_dev)
+ {
+ // printk("%s: Cannot get device %s by name!\n", __FUNCTION__, dev_name);
+ setup_error = SW_FAIL;
+ continue;
+ }
+#if defined (CONFIG_BRIDGE)
+#ifdef KVER32
+ if (NULL != br_port_get_rcu(nat_dev)) /* under bridge interface. */
+ {
+ /* Get bridge interface name */
+ br_name = (char *)(br_port_get_rcu(nat_dev)->br->dev->name);
+ memcpy (nat_bridge_dev, br_name, sizeof(br_name));
+ /* Get dmac */
+ devmac = (uint8_t *)(br_port_get_rcu(nat_dev)->br->dev->dev_addr);
+ }
+#else
+ if (NULL != nat_dev->br_port) /* under bridge interface. */
+ {
+ /* Get bridge interface name */
+ br_name = (char *)nat_dev->br_port->br->dev->name;
+ memcpy (nat_bridge_dev, br_name, sizeof(br_name));
+ /* Get dmac */
+ devmac = (uint8_t *)nat_dev->br_port->br->dev->dev_addr;
+ }
+#endif
+ else
+#endif /* CONFIG_BRIDGE */
+ {
+ devmac = (uint8_t *)nat_dev->dev_addr;
+ }
+ /* get vid */
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+ vid = vlan_dev_vlan_id(nat_dev);
+#else
+ vid = 0;
+#endif
+#ifdef CONFIG_IPV6_HWACCEL
+ ipv6 = 1;
+ if (is_wan)
+ {
+ wan_fid = vid;
+ }
+#else
+ ipv6 = 0;
+ if (is_wan)
+ {
+ if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type)
+ ipv6 = 1;
+ wan_fid = vid;
+ }
+#endif
+#ifdef ISISC
+ if (0 == is_wan) /* Not WAN -> LAN */
+ {
+ /* Setup private and netmask as soon as possible */
+ if (NULL != nat_dev->br_port) /* under bridge interface. */
+ {
+#ifdef KVER32
+ in_device_lan = (struct in_device *) (br_port_get_rcu(nat_dev)->br->dev->ip_ptr);
+#else
+ in_device_lan = (struct in_device *) nat_dev->br_port->br->dev->ip_ptr;
+#endif
+ }
+ else
+ {
+ in_device_lan = (struct in_device *) nat_dev->ip_ptr;
+ }
+ if ((NULL == in_device_lan)||(NULL == in_device_lan->ifa_list))
+ {
+ setup_error = SW_FAIL;
+ continue;
+ }
+ nat_hw_prv_mask_set((a_uint32_t)(in_device_lan->ifa_list->ifa_mask));
+ nat_hw_prv_base_set((a_uint32_t)(in_device_lan->ifa_list->ifa_address));
+ printk("Set private base 0x%08x for %s\n", (a_uint32_t)(in_device_lan->ifa_list->ifa_address), nat_dev->br_port->br->dev->name);
+ memcpy(&lanip, (void *)&(in_device_lan->ifa_list->ifa_address), 4); /* copy Lan port IP. */
+#ifndef ISISC
+ redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules((a_uint32_t)(in_device_lan->ifa_list->ifa_address),
+ (a_uint32_t)(in_device_lan->ifa_list->ifa_mask));
+#endif
+ }
+#endif
+ memcpy(if_mac_addr, devmac, MAC_LEN);
+ devmac = if_mac_addr;
+ dev_put(nat_dev);
+
+ HNAT_PRINTK("DMAC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
+ devmac[0], devmac[1], devmac[2],
+ devmac[3], devmac[4], devmac[5]);
+ HNAT_PRINTK("VLAN id: %d\n", vid);
+
+ if(if_mac_add(devmac, vid, ipv6) != 0)
+ {
+ setup_error = SW_FAIL;
+ continue;
+ }
+ else
+ {
+ setup_error = SW_OK;
+ }
+ }
+
+ return setup_error;
+}
+
+static int setup_all_interface_entry(void)
+{
+ static int setup_wan_if = 0;
+ static int setup_lan_if=0;
+ static int setup_default_vid = 0;
+ int i = 0;
+
+ if (0 == setup_default_vid)
+ {
+ for (i=0; i<7; i++) /* For AR8327/AR8337, only 7 port */
+ {
+ PORTVLAN_ROUTE_DEFV_SET(0, i);
+ }
+ setup_default_vid = 1;
+ }
+
+ if (0 == setup_lan_if)
+ {
+#ifdef ISISC
+ MISC_ARP_CMD_SET(0, FAL_MAC_FRWRD); /* Should be put in init function. */
+ MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU);
+#endif
+ if (SW_OK == setup_interface_entry(nat_lan_dev_list, 0))
+ {
+ setup_lan_if = 1; /* setup LAN interface entry success */
+ printk("Setup LAN interface entry done!\n");
+ }
+ }
+
+ if (0 == setup_wan_if)
+ {
+ if (SW_OK == setup_interface_entry(nat_wan_dev_list, 1))
+ {
+ setup_wan_if = 1; /* setup WAN interface entry success */
+ printk("Setup WAN interface entry done!\n");
+ }
+ }
+#ifndef ISISC /* For S17c only */
+ if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) ||
+ (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6))
+ {
+ uint8_t buf[6];
+
+ memcpy(buf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+ HNAT_PRINTK("Peer MAC: %s ", buf);
+ /* add the peer interface with VID */
+ if_mac_add(buf, wan_fid, 0);
+ HNAT_PRINTK(" --> (%.2x-%.2x-%.2x-%.2x-%.2x-%.2x)\n", \
+ buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4);
+ }
+#endif
+
+ return 1;
+}
+
+/* check for pppoe session change */
+static void isis_pppoe_check_for_redial(void)
+{
+ if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_IP)
+ return;
+
+ if(((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) \
+ || (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)) \
+ && (pppoetbl.session_id != 0))
+ {
+ if(pppoetbl.session_id != nf_athrs17_hnat_ppp_id)
+ {
+ aos_printk("%s: PPPoE session ID changed... \n", __func__);
+ if (nf_athrs17_hnat_wan_type != NF_S17_WAN_TYPE_PPPOEV6)
+ {
+ if (PPPOE_SESSION_TABLE_DEL(0, &pppoetbl) != SW_OK)
+ {
+ aos_printk("delete old pppoe session %d entry_id %d failed.. \n", pppoetbl.session_id, pppoetbl.entry_id);
+ return;
+ }
+
+ /* force PPPoE parser for multi- and uni-cast packets; for v1.0.7+ */
+ pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+ pppoetbl.multi_session = 1;
+ pppoetbl.uni_session = 1;
+ pppoetbl.entry_id = 0;
+ /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+ if (PPPOE_SESSION_TABLE_ADD(0, &pppoetbl) == SW_OK)
+ {
+ PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+ printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id);
+ }
+ }
+ else /* nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6 */
+ {
+ /* reset the session Id only */
+ aos_printk("IPV6 PPPOE mode... \n");
+ pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+ PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+ printk("%s: new pppoe session id: %x, entry_id: %x\n", __func__, pppoetbl.session_id, pppoetbl.entry_id);
+ }
+ /* read back the WAN IP */
+ memcpy(&wanip, (void *)&nf_athrs17_hnat_wan_ip, 4);
+ aos_printk("Read the WAN IP back... %.8x\n", *(uint32_t *)&wanip);
+ /* change the PPPoE ACL to ensure the packet is correctly forwarded by the HNAT engine */
+ pppoe_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, pppoe_gwid);
+ }
+ }
+}
+
+#ifdef ISIS /* only for S17 */
+static void pppoev6_mac6_loop_dev(void)
+{
+#define PPPOEV6_SESSION_ID 0xfffe
+ fal_pppoe_session_t ptbl;
+
+ memset(&ptbl, 0, sizeof(fal_pppoe_session_t));
+
+ aos_printk("%s: set MAC6 as loopback device\n", __func__);
+
+ ptbl.session_id = PPPOEV6_SESSION_ID;
+ ptbl.multi_session = 1;
+ ptbl.uni_session = 1;
+ ptbl.entry_id = 0xe;
+
+ /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+ if (PPPOE_SESSION_TABLE_ADD(0, &ptbl) == SW_OK)
+ {
+ PPPOE_SESSION_ID_SET(0, ptbl.entry_id, ptbl.session_id);
+ aos_printk("%s: pppoe session id: %d added into entry: %d \n", __func__, ptbl.session_id, ptbl.entry_id);
+ }
+ else
+ {
+ aos_printk("%s: failed on adding pppoe session id: %d\n", __func__, ptbl.session_id);
+ }
+
+ /* PPPoE entry 0 */
+ athrs17_reg_write(0x2200, PPPOEV6_SESSION_ID);
+
+ aos_printk("%s: end of function... \n", __func__);
+}
+
+static void pppoev6_remove_parser(uint32_t entry_id)
+{
+ aos_printk("%s: clear entry id: %d\n", __func__, entry_id);
+ /* clear the session id in the PPPoE parser engine */
+ athrs17_reg_write(PPPOE_SESSION_OFFSET + PPPOE_SESSION_E_OFFSET * entry_id, 0);
+}
+
+static void pppoev6_mac6_stop_learning(void)
+{
+ /* do not disable this port if some other registers are already filled in
+ to prevent setting conflict */
+ int val = S17_P6PAD_MODE_REG_VALUE;
+
+ if ( val != (1<<24))
+ {
+ aos_printk("%s: MAC 6 already being used!\n", __FUNCTION__);
+ return;
+ }
+
+
+ /* clear the MAC6 learning bit */
+ athrs17_reg_write(0x6a8, athrs17_reg_read(0x6a8) & ~(1<<20));
+
+ /* force loopback mode */
+ athrs17_reg_write(0x94, 0x7e);
+ athrs17_reg_write(0xb4, 0x10);
+}
+#endif // ifdef ISIS
+
+static int add_pppoe_host_entry(uint32_t sport, a_int32_t arp_entry_id)
+{
+ a_bool_t ena;
+ int rv = SW_OK;
+ fal_host_entry_t nh_arp_entry;
+
+ if (0xffff == wan_fid)
+ {
+ printk("%s: Cannot get WAN vid!\n", __FUNCTION__);
+ return SW_FAIL;
+ }
+
+ if (PPPOE_STATUS_GET(0, &ena) != SW_OK)
+ {
+ aos_printk("Cannot get the PPPoE mode\n");
+ ena = 0;
+ }
+#ifdef ISIS
+ if (!ena)
+#else /* For S17c only */
+ memset(&nh_arp_entry, 0, sizeof(nh_arp_entry));
+ nh_arp_entry.ip4_addr = nf_athrs17_hnat_ppp_peer_ip;
+ nh_arp_entry.flags = FAL_IP_IP4_ADDR;
+ rv = IP_HOST_GET(0, FAL_IP_ENTRY_IPADDR_EN, &nh_arp_entry);
+ if (SW_OK != rv)
+#endif
+ {
+ if ((!ena) && (PPPOE_STATUS_SET(0, A_TRUE) != SW_OK))
+ aos_printk("Cannot enable the PPPoE mode\n");
+
+ aos_printk("PPPoE enable mode: %d\n", ena);
+
+ pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+ pppoetbl.multi_session = 1;
+ pppoetbl.uni_session = 1;
+ pppoetbl.entry_id = 0;
+
+ /* set the PPPoE edit reg (0x2200), and PPPoE session reg (0x5f000) */
+ rv = PPPOE_SESSION_TABLE_ADD(0, &pppoetbl);
+ if (rv == SW_OK)
+ {
+ uint8_t mbuf[6], ibuf[4];
+ a_int32_t a_entry_id = -1;
+
+ PPPOE_SESSION_ID_SET(0, pppoetbl.entry_id, pppoetbl.session_id);
+ aos_printk("pppoe session: %d, entry_id: %d\n", pppoetbl.session_id, pppoetbl.entry_id);
+
+ /* create the peer host ARP entry */
+ memcpy(ibuf, (void *)&nf_athrs17_hnat_ppp_peer_ip, 4);
+ memcpy(mbuf, nf_athrs17_hnat_ppp_peer_mac, ETH_ALEN);
+
+ a_entry_id = arp_hw_add(S17_WAN_PORT, wan_fid, ibuf, mbuf, 0);
+ if (a_entry_id >= 0) /* hostentry creation okay */
+ {
+ aos_printk("(1)Bind PPPoE session ID: %d, entry_id: %d to host entry: %d\n", \
+ pppoetbl.session_id, pppoetbl.entry_id, a_entry_id);
+
+ rv = IP_HOST_PPPOE_BIND(0, a_entry_id, pppoetbl.entry_id, A_TRUE);
+ if ( rv != SW_OK)
+ {
+ aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", a_entry_id, rv);
+ }
+
+ aos_printk("adding ACLs \n");
+ pppoe_gwid = a_entry_id;
+ pppoe_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, a_entry_id);
+ aos_printk("ACL creation okay... \n");
+ }
+ }
+ else
+ {
+ aos_printk("PPPoE session add failed.. (id: %d)\n", pppoetbl.session_id);
+ aos_printk("rv: %d\n", rv);
+ }
+
+#ifdef ISIS
+ if (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6)
+ {
+ aos_printk("IPV6 PPPOE mode... (share the same ID with IPV4's)\n");
+ pppoev6_mac6_loop_dev();
+ pppoev6_remove_parser(pppoetbl.entry_id);
+
+ /* bind the first LAN host to the pseudo PPPoE ID */
+ rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE);
+ if ( rv != SW_OK)
+ {
+ aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv);
+ }
+ }
+#endif // ifdef ISIS
+ }
+#ifdef ISIS
+ else /* ena */
+ {
+ if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6) &&
+ (sport != S17_WAN_PORT)&& (arp_entry_id != 0))
+ {
+ aos_printk("IPV6 PPPoE mode\n");
+ /* bind LAN hosts to the pseudo PPPoE ID */
+ rv = IP_HOST_PPPOE_BIND(0, arp_entry_id, 0, A_TRUE);
+ if ( rv != SW_OK)
+ {
+ aos_printk("IP_HOST_PPPOE_BIND failed (entry: %d, rv: %d)... \n", arp_entry_id, rv);
+ }
+ }
+ }
+#endif // ifdef ISIS
+
+ return SW_OK;
+}
+
+static int
+arp_is_reply(struct sk_buff *skb)
+{
+ struct arphdr *arp = arp_hdr(skb);
+
+ if (!arp)
+ {
+ HNAT_PRINTK("%s: Packet has no ARP data\n", __func__);
+ return 0;
+ }
+
+ if (skb->len < sizeof(struct arphdr))
+ {
+ HNAT_PRINTK("%s: Packet is too small to be an ARP\n", __func__);
+ return 0;
+ }
+
+ if (arp->ar_op != htons(ARPOP_REPLY))
+ {
+ return 0;
+ }
+
+ return 1;
+}
+
+static int
+dev_check(char *in_dev, char *dev_list)
+{
+ char *list_dev;
+ char temp[100] = {0};
+ char *list;
+
+ if(!in_dev || !dev_list)
+ {
+ return 0;
+ }
+
+ strcpy(temp, dev_list);
+ list = temp;
+
+ HNAT_PRINTK("%s: list:%s\n", __func__, list);
+ while ((list_dev = strsep(&list, " ")) != NULL)
+ {
+ HNAT_PRINTK("%s: strlen:%d list_dev:%s in_dev:%s\n",
+ __func__, strlen(list_dev), list_dev, in_dev);
+
+ if (!strncmp(list_dev, in_dev, strlen(list_dev)))
+ {
+ HNAT_PRINTK("%s: %s\n", __FUNCTION__, list_dev);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+#ifndef ISISC
+static uint32_t get_netmask_from_netdevice(const struct net_device *in_net_dev)
+{
+ struct in_device *my_in_device = NULL;
+ uint32_t result = 0xffffff00;
+
+ if((in_net_dev) && (in_net_dev->ip_ptr != NULL))
+ {
+ my_in_device = (struct in_device *)(in_net_dev->ip_ptr);
+ if(my_in_device->ifa_list != NULL)
+ {
+ result = my_in_device->ifa_list->ifa_mask;
+ }
+ }
+
+ return result;
+}
+#endif
+
+static unsigned int
+arp_in(unsigned int hook,
+ struct sk_buff *skb,
+ const struct net_device *in,
+ const struct net_device *out,
+ int (*okfn) (struct sk_buff *))
+{
+ struct arphdr *arp = NULL;
+ uint8_t *sip, *dip, *smac, *dmac;
+ uint8_t dev_is_lan = 0;
+ uint32_t sport = 0, vid = 0;
+#ifdef ISIS
+ uint32_t lan_netmask = 0;
+ a_bool_t prvbasemode = 1;
+#endif
+ a_int32_t arp_entry_id = -1;
+
+ /* check for PPPoE redial here, to reduce overheads */
+ isis_pppoe_check_for_redial();
+
+ /* do not write out host table if HNAT is disabled */
+ if (!nf_athrs17_hnat)
+ return NF_ACCEPT;
+
+ setup_all_interface_entry();
+
+ if(dev_check((char *)in->name, (char *)nat_wan_dev_list))
+ {
+
+ }
+ else if (dev_check((char *)in->name, (char *)nat_bridge_dev))
+ {
+ dev_is_lan = 1;
+ }
+ else
+ {
+ HNAT_PRINTK("Not Support device: %s\n", (char *)in->name);
+ return NF_ACCEPT;
+ }
+
+ if(!arp_is_reply(skb))
+ {
+ return NF_ACCEPT;
+ }
+
+ if(arp_if_info_get((void *)(skb->head), &sport, &vid) != 0)
+ {
+ printk("Cannot get header info!!\n");
+ return NF_ACCEPT;
+ }
+
+ arp = arp_hdr(skb);
+ smac = ((uint8_t *) arp) + ARP_HEADER_LEN;
+ sip = smac + MAC_LEN;
+ dmac = sip + IP_LEN;
+ dip = dmac + MAC_LEN;
+
+ arp_entry_id = arp_hw_add(sport, vid, sip, smac, 0);
+ if(arp_entry_id < 0)
+ {
+ printk("ARP entry error!!\n");
+ return NF_ACCEPT;
+ }
+
+ if (0 == dev_is_lan)
+ {
+ memcpy(&wanip, dip, 4);
+#ifdef MULTIROUTE_WR
+ wan_nh_add(sip, smac, arp_entry_id);
+#endif
+ }
+
+ if(dev_is_lan && nat_hw_prv_base_can_update())
+ {
+ nat_hw_flush();
+ nat_hw_prv_base_update_disable();
+#ifdef MULTIROUTE_WR
+ multi_route_indev = in;
+#endif
+ }
+
+ if ((nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOE) ||
+ (nf_athrs17_hnat_wan_type == NF_S17_WAN_TYPE_PPPOEV6))
+ {
+ add_pppoe_host_entry(sport, arp_entry_id);
+ }
+
+#ifdef ISIS
+ /* check for SIP and DIP range */
+ if ((lanip[0] != 0) && (wanip[0] != 0))
+ {
+ if (NAT_PRV_ADDR_MODE_GET(0, &prvbasemode) != SW_OK)
+ {
+ aos_printk("Private IP base mode check failed: %d\n", prvbasemode);
+ }
+
+ if (!prvbasemode) /* mode 0 */
+ {
+ if ((lanip[0] == wanip[0]) && (lanip[1] == wanip[1]))
+ {
+ if ((lanip[2] & 0xf0) == (wanip[2] & 0xf0))
+ {
+ if (get_aclrulemask()& (1 << S17_ACL_LIST_IPCONF))
+ return NF_ACCEPT;
+
+ aos_printk("LAN IP and WAN IP conflict... \n");
+ /* set h/w acl to filter out this case */
+#ifdef MULTIROUTE_WR
+ // if ( (wan_nh_ent[0].host_ip != 0) && (wan_nh_ent[0].entry_id != 0))
+ if ( (wan_nh_ent[0].host_ip != 0))
+ ip_conflict_add_acl_rules(*(uint32_t *)&wanip, *(uint32_t *)&lanip, wan_nh_ent[0].entry_id);
+#endif
+ return NF_ACCEPT;
+ }
+ }
+ }
+ else /* mode 1*/
+ {
+ ;; /* do nothing */
+ }
+ }
+#endif /* ifdef ISIS */
+
+ return NF_ACCEPT;
+}
+
+static struct
+ nf_hook_ops arpinhook =
+{
+ .hook = arp_in,
+ .hooknum = NF_ARP_IN,
+ .owner = THIS_MODULE,
+ .pf = NFPROTO_ARP,
+ .priority = NF_IP_PRI_FILTER,
+};
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+static int qcaswitch_pppoe_ip_event(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+ struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
+ struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev;
+ struct ppp *ppp = netdev_priv(dev);
+ struct list_head *list;
+ struct channel *pch;
+ struct sock *sk;
+ struct pppox_sock *po;
+ unsigned long flags;
+ static int connection_count = 0;
+ fal_pppoe_session_t del_pppoetbl;
+
+ if (!((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT)))
+ return NOTIFY_DONE;
+
+ if (dev_net(dev) != &init_net)
+ return NOTIFY_DONE;
+
+ setup_all_interface_entry();
+
+ switch (event)
+ {
+ case NETDEV_UP:
+ local_irq_save(flags);
+ list = &ppp->channels;
+ if (list_empty(list))
+ {
+ local_irq_restore(flags);
+ return NOTIFY_DONE;
+ }
+ if ((ppp->flags & SC_MULTILINK) == 0)
+ {
+ /* not doing multilink: send it down the first channel */
+ list = list->next;
+ pch = list_entry(list, struct channel, clist);
+ if (pch->chan)
+ {
+ if (pch->chan->private)
+ {
+ /* the NETDEV_UP event will be sent many times
+ * because of ifa operation ifa->ifa_local != ifa->ifa_address
+ * means that remote ip is really added.
+ */
+ if (ifa->ifa_local == ifa->ifa_address)
+ {
+ local_irq_restore(flags);
+ return NOTIFY_DONE;
+ }
+ sk = (struct sock *)pch->chan->private;
+ po = (struct pppox_sock*)sk;
+ connection_count++;
+ if (((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) &&
+ (0 != nf_athrs17_hnat_ppp_id))) /* another session for IPv6 */
+ {
+ nf_athrs17_hnat_ppp_id2 = po->num;
+ memcpy(nf_athrs17_hnat_ppp_peer_mac2, po->pppoe_pa.remote, ETH_ALEN);
+ }
+ else
+ {
+ nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_PPPOE;
+ nf_athrs17_hnat_wan_ip = ifa->ifa_local;
+ nf_athrs17_hnat_ppp_peer_ip = ifa->ifa_address;
+ memcpy(nf_athrs17_hnat_ppp_peer_mac, po->pppoe_pa.remote, ETH_ALEN);
+ nf_athrs17_hnat_ppp_id = po->num;
+ }
+ }
+ }
+ else
+ {
+ local_irq_restore(flags);
+ /* channel got unregistered */
+ return NOTIFY_DONE;
+ }
+ }
+ local_irq_restore(flags);
+ break;
+
+ case NETDEV_DOWN:
+ if (NF_S17_WAN_TYPE_PPPOE != nf_athrs17_hnat_wan_type)
+ {
+ return NOTIFY_DONE;
+ }
+ printk("DOWN: local: "NIPQUAD_FMT"\n", NIPQUAD(ifa->ifa_local));
+ printk("DOWN: address: "NIPQUAD_FMT"\n", NIPQUAD(ifa->ifa_address));
+ connection_count--;
+ local_irq_save(flags);
+ if (ifa->ifa_local == nf_athrs17_hnat_wan_ip)
+ {
+ /* PPPoE Interface really down */
+ ipv6_droute_del_acl_rules();
+ del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id;
+ del_pppoetbl.multi_session = 1;
+ del_pppoetbl.uni_session = 1;
+ del_pppoetbl.entry_id = 0;
+ PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl);
+ nf_athrs17_hnat_wan_type = NF_S17_WAN_TYPE_IP;
+ nf_athrs17_hnat_wan_ip = 0;
+ nf_athrs17_hnat_ppp_peer_ip = 0;
+ nf_athrs17_hnat_ppp_id = 0;
+ memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN);
+ }
+ else
+ {
+ if (0 != nf_athrs17_hnat_ppp_id2)
+ {
+ del_pppoetbl.session_id = nf_athrs17_hnat_ppp_id2;
+ del_pppoetbl.multi_session = 1;
+ del_pppoetbl.uni_session = 1;
+ del_pppoetbl.entry_id = 0;
+ PPPOE_SESSION_TABLE_DEL(0, &del_pppoetbl);
+ }
+ nf_athrs17_hnat_ppp_id2 = 0;
+ memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN);
+ }
+ qcaswitch_hostentry_flush();
+ local_irq_restore(flags);
+ break;
+
+ default:
+ break;
+ }
+ return NOTIFY_DONE;
+}
+
+/* a linux interface is configured with ipaddr, then
+ * it becomes a L3 routing interface
+ * add the router mac of this interface to the table
+ */
+/* FIXME: only hande pppoe event right now. */
+static int qcaswitch_ip_event(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+ struct in_ifaddr *ifa = (struct in_ifaddr *)ptr;
+ struct net_device *dev = (struct net_device *)ifa->ifa_dev->dev;
+
+ if ((dev->type == ARPHRD_PPP) && (dev->flags & IFF_POINTOPOINT))
+ {
+ return qcaswitch_pppoe_ip_event(this, event, ptr);
+ }
+
+ return NOTIFY_DONE;
+}
+
+
+static struct notifier_block qcaswitch_ip_notifier =
+{
+ .notifier_call = qcaswitch_ip_event,
+ .priority = 100,
+};
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+#define HOST_AGEOUT_STATUS 1
+void host_check_aging(void)
+{
+ fal_host_entry_t *host_entry_p, host_entry= {0};
+ sw_error_t rv;
+ int cnt = 0;
+ unsigned long flags;
+ fal_napt_entry_t src_napt = {0}, pub_napt = {0};
+
+ host_entry_p = &host_entry;
+ host_entry_p->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+
+ local_irq_save(flags);
+ while (1)
+ {
+ host_entry_p->status = HOST_AGEOUT_STATUS;
+ /* FIXME: now device id is set to 0. */
+ rv = IP_HOST_NEXT (0, FAL_IP_ENTRY_STATUS_EN, host_entry_p);
+ // rv = IP_HOST_NEXT (0, 0, host_entry_p);
+ if (SW_OK != rv)
+ break;
+ if (cnt >= ARP_ENTRY_MAX) // arp entry number
+ break;
+
+ if (ARP_AGE_NEVER == host_entry_p->status)
+ continue;
+
+ if ((S17_WAN_PORT == host_entry_p->port_id) &&
+ (host_entry_p->counter_en))
+ {
+ if (0 != host_entry_p->packet)
+ {
+ // arp entry is using, update it.
+ host_entry.status = ARP_AGE;
+ printk("Update WAN port hostentry!\n");
+ IP_HOST_ADD(0, host_entry_p);
+ }
+ else
+ {
+ printk("Del WAN port hostentry!\n");
+ IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p);
+ }
+ continue;
+ }
+
+ src_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ memcpy(&src_napt.src_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t));
+ pub_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ memcpy(&pub_napt.trans_addr, &host_entry_p->ip4_addr, sizeof(fal_ip4_addr_t));
+ if((NAPT_NEXT(0, FAL_NAT_ENTRY_SOURCE_IP_EN ,&src_napt) !=0) && \
+ (NAPT_NEXT(0, FAL_NAT_ENTRY_PUBLIC_IP_EN ,&pub_napt) != 0))
+ {
+ /* Cannot find naptentry */
+ printk("ARP id 0x%x: Cannot find NAPT entry!\n", host_entry_p->entry_id);
+ IP_HOST_DEL(0, FAL_IP_ENTRY_IPADDR_EN, host_entry_p);
+ continue;
+ }
+ // arp entry is using, update it.
+ host_entry_p->status = ARP_AGE;
+ IP_HOST_ADD(0, host_entry_p);
+ printk("update entry 0x%x port %d\n", host_entry_p->entry_id, host_entry_p->port_id);
+ cnt++;
+ }
+ local_irq_restore(flags);
+}
+
+#ifdef CONFIG_IPV6_HWACCEL
+#define IPV6_LEN 16
+#define MAC_LEN 6
+#define PROTO_ICMPV6 0x3a
+#define NEIGHBOUR_SOL 135
+#define NEIGHBOUR_AD 136
+
+struct icmpv6_option
+{
+ __u8 type;
+ __u8 len;
+ __u8 mac[MAC_LEN];
+};
+
+static unsigned int ipv6_handle(unsigned int hooknum,
+ struct sk_buff *skb,
+ const struct net_device *in,
+ const struct net_device *out,
+ int (*okfn)(struct sk_buff *))
+{
+ struct ipv6hdr *iph6 = ipv6_hdr(skb);
+ struct icmp6hdr *icmp6 = icmp6_hdr(skb);
+ __u8 *sip = ((__u8 *)icmp6)+sizeof(struct icmp6hdr);
+ struct icmpv6_option *icmpv6_opt = (struct icmpv6_option *)(sip+IPV6_LEN);
+ __u8 *sa = icmpv6_opt->mac;
+
+ uint32_t sport = 0, vid = 0;
+ struct inet6_ifaddr *in_device_addr = NULL;
+ uint8_t dev_is_lan = 0;
+
+ /* do not write out host table if HNAT is disabled */
+ if (!nf_athrs17_hnat)
+ return NF_ACCEPT;
+
+ setup_all_interface_entry();
+
+ if(dev_check((char *)in->name, (char *)nat_wan_dev_list))
+ {
+ dev_is_lan = 0;
+ }
+ else if (dev_check((char *)in->name, (char *)nat_bridge_dev))
+ {
+ dev_is_lan = 1;
+ }
+ else
+ {
+ HNAT_PRINTK("Not Support device: %s\n", (char *)in->name);
+ return NF_ACCEPT;
+ }
+
+ if(PROTO_ICMPV6 == iph6->nexthdr)
+ {
+ if(NEIGHBOUR_AD == icmp6->icmp6_type)
+ {
+ if (__ipv6_addr_type((struct in6_addr*)sip) & IPV6_ADDR_LINKLOCAL)
+ return NF_ACCEPT;
+
+ if(arp_if_info_get((void *)(skb->head), &sport, &vid) != 0)
+ {
+ return NF_ACCEPT;
+ }
+
+ if ((0 == vid)||(0 == sport))
+ {
+ printk("Error: Null sport or vid!!\n");
+ return NF_ACCEPT;
+ }
+
+ if ((0 == dev_is_lan) && (S17_WAN_PORT != sport))
+ {
+ printk("Error: WAN port %d\n", sport);
+ return NF_ACCEPT;
+ }
+
+ HNAT_PRINTK("ND Reply %x %x\n",icmpv6_opt->type,icmpv6_opt->len);
+ HNAT_PRINTK("isis_v6: incoming packet, sip = %02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x:%02x%02x\n"
+ ,sip[0],sip[1],sip[2],sip[3],sip[4],sip[5],sip[6],sip[7]
+ ,sip[8],sip[9],sip[10],sip[11],sip[12],sip[13],sip[14],sip[15]
+ );
+ HNAT_PRINTK("isis_v6: incoming packet, sa = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
+ HNAT_PRINTK("isis_v6: vid = %d sport = %d\n", vid, sport);
+
+ //add nd entry
+ if((2 == icmpv6_opt->type) && (1 == icmpv6_opt->len))
+ {
+ arp_hw_add(sport, vid, sip, sa, 1);
+ }
+ else /* ND AD packets without option filed? Fix Me!! */
+ {
+ sa = skb->mac_header + MAC_LEN;
+ HNAT_PRINTK("isis_v6 Changed sa = %.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]);
+ arp_hw_add(sport, vid, sip, sa, 1);
+ }
+
+ if ((NULL != in->ip6_ptr) && (NULL != ((struct inet6_dev *)in->ip6_ptr)->addr_list))
+ {
+ in_device_addr = ((struct inet6_dev *)in->ip6_ptr)->addr_list;
+ if (0 == dev_is_lan)
+ {
+ /* WAN ipv6 address*/
+ memcpy(&wan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr));
+ HNAT_PRINTK("%s: ipv6 wanip %pI6\n", in->name, &wan6ip);
+ }
+ else
+ {
+ /* LAN ipv6 address*/
+ memcpy(&lan6ip, (__u8 *)&in_device_addr->addr, sizeof(struct in6_addr));
+ HNAT_PRINTK("%s: ipv6 lanip %pI6\n", in->name, &lan6ip);
+ }
+ }
+ }
+ }
+
+ return NF_ACCEPT;
+}
+
+static struct nf_hook_ops ipv6_inhook =
+{
+ .hook = ipv6_handle,
+ .owner = THIS_MODULE,
+ .pf = PF_INET6,
+ .hooknum = NF_INET_PRE_ROUTING,
+ .priority = NF_IP6_PRI_CONNTRACK,
+};
+#endif /* CONFIG_IPV6_HWACCEL */
+
+extern int napt_procfs_init(void);
+extern void napt_procfs_exit(void);
+
+void host_helper_init(void)
+{
+ int i;
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ /* header len 4 with type 0xaaaa */
+ HEADER_TYPE_SET(0, A_TRUE, 0xaaaa);
+#ifdef ISISC
+ /* For S17c (ISISC), it is not necessary to make all frame with header */
+ PORT_TXHDR_MODE_SET(0, 0, FAL_ONLY_MANAGE_FRAME_EN);
+ /* Fix tag disappear problem, set TO_CPU_VID_CHG_EN, 0xc00 bit1 */
+ CPU_VID_EN_SET(0, A_TRUE);
+ /* set RM_RTD_PPPOE_EN, 0xc00 bit0 */
+ RTD_PPPOE_EN_SET(0, A_TRUE);
+ /* Enable ARP ack frame as management frame. */
+ for (i=1; i<6; i++)
+ {
+ PORT_ARP_ACK_STATUS_SET(0, i, A_TRUE);
+ }
+ MISC_ARP_CMD_SET(0, FAL_MAC_FRWRD);
+ /* Avoid ARP response storm for HUB, now this fix only apply on PORT5 */
+ MISC_ARP_SP_NOT_FOUND_SET(0, FAL_MAC_RDT_TO_CPU);
+ MISC_ARP_GUARD_SET(0, S17_WAN_PORT, FAL_MAC_IP_PORT_GUARD);
+ /* set VLAN_TRANS_TEST register bit, to block packets from WAN port has private dip */
+ NETISOLATE_SET(0, A_TRUE);
+#else
+ PORT_TXHDR_MODE_SET(0, 0, FAL_ALL_TYPE_FRAME_EN);
+#endif
+ CPU_PORT_STATUS_SET(0, A_TRUE);
+ IP_ROUTE_STATUS_SET(0, A_TRUE);
+
+ /* CPU port with VLAN tag, others w/o VLAN */
+ entry = 0x01111112;
+ HSL_REG_ENTRY_SET(rv, 0, ROUTER_EG, 0, (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+ napt_procfs_init();
+ memcpy(nat_bridge_dev, nat_lan_dev_list, strlen(nat_lan_dev_list)+1);
+
+ nf_register_hook(&arpinhook);
+#ifdef CONFIG_IPV6_HWACCEL
+ aos_printk("Registering IPv6 hooks... \n");
+ nf_register_hook(&ipv6_inhook);
+#endif
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+ register_inetaddr_notifier(&qcaswitch_ip_notifier);
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+ /* Enable ACLs to handle MLD packets */
+ upnp_ssdp_add_acl_rules();
+ ipv6_snooping_solicted_node_add_acl_rules();
+ ipv6_snooping_sextuple0_group_add_acl_rules();
+ ipv6_snooping_quintruple0_1_group_add_acl_rules();
+}
+
+void host_helper_exit(void)
+{
+ napt_procfs_exit();
+
+ nf_unregister_hook(&arpinhook);
+#ifdef CONFIG_IPV6_HWACCEL
+ nf_unregister_hook(&ipv6_inhook);
+#endif
+}
+
diff --git a/app/nathelper/linux/lib/nat_helper_dt.c b/app/nathelper/linux/lib/nat_helper_dt.c
new file mode 100644
index 0000000..c914a9f
--- /dev/null
+++ b/app/nathelper/linux/lib/nat_helper_dt.c
@@ -0,0 +1,982 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/kthread.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+#include <net/netfilter/nf_conntrack_acct.h>
+
+#include "../nat_helper.h"
+#include "../napt_helper.h"
+
+#include "nat_helper_dt.h"
+#include "nat_helper_hsl.h"
+#include "fal_type.h"
+#include "fal_nat.h"
+
+extern uint32_t napt_set_default_route(fal_ip4_addr_t dst_addr, fal_ip4_addr_t src_addr);
+extern uint32_t napt_set_ipv6_default_route(void);
+
+#define NAPT_BUFFER_HASH_SIZE (NAPT_TABLE_SIZE)
+#define NAPT_BUFFER_SIZE ((NAPT_BUFFER_HASH_SIZE)*8)
+
+struct napt_ct
+{
+ struct napt_ct *next;
+ a_uint32_t ct_addr;
+ a_uint64_t ct_packets;
+ a_uint8_t in_hw;
+ a_uint16_t hw_index;
+ a_uint8_t deny;
+};
+
+struct nhlist_head
+{
+ struct napt_ct *next;
+};
+
+static struct nhlist_head *ct_buf_hash_head = NULL;
+static struct napt_ct *ct_buf = NULL;
+static a_uint32_t ct_buf_ct_cnt = 0;
+
+static a_int32_t
+napt_hash_buf_init(struct napt_ct **hash, struct nhlist_head **hash_head)
+{
+ a_uint32_t hash_size = NAPT_BUFFER_HASH_SIZE;
+ a_uint32_t buffer_size = NAPT_BUFFER_SIZE;
+
+ *hash = (struct napt_ct *)kmalloc(sizeof(struct napt_ct)*buffer_size, GFP_ATOMIC);
+ if(!(*hash))
+ {
+ HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!");
+ return -1;
+ }
+
+ *hash_head = (struct nhlist_head *)kmalloc(sizeof(struct nhlist_head)*hash_size, GFP_ATOMIC);
+ if(!(*hash_head))
+ {
+ HNAT_PRINTK("NAPT INIT ERROR! No Sufficient Memory!");
+ kfree(*hash);
+ return -1;
+ }
+
+ memset(*hash,0,sizeof(struct napt_ct)*buffer_size);
+ memset(*hash_head,0,sizeof(struct nhlist_head)*hash_size);
+
+ return 0;
+}
+
+#define NAPT_CT_HASH(ct_addr) (((ct_addr) * (0x9e370001UL)) >> 22)
+
+static struct napt_ct *
+napt_hash_add(a_uint32_t ct_addr, a_uint32_t *hash_cnt,
+ struct napt_ct *hash, struct nhlist_head *hash_head)
+{
+ struct napt_ct *entry = 0,*last = 0,*node = 0;
+ struct nhlist_head *head = 0;
+ a_uint32_t hash_index = NAPT_CT_HASH(ct_addr);
+
+ if(*hash_cnt >= NAPT_BUFFER_SIZE)
+ {
+ return NULL;
+ }
+ head = &(hash_head[hash_index]);
+ entry = head->next;
+
+ while(entry)
+ {
+ if(ct_addr == entry->ct_addr)
+ {
+ return entry;
+ }
+ else
+ {
+ last = entry;
+ entry = entry->next;
+ }
+ }
+
+ node = &(hash[*hash_cnt]);
+ node->ct_addr = ct_addr;
+ node->ct_packets = 0;
+ node->in_hw = 0;
+ node->hw_index = 0;
+ node->deny = 0;
+
+ if(head->next == 0)
+ {
+ head->next = node;
+ }
+ else
+ {
+ last->next = node;
+ }
+ (*hash_cnt)++;
+
+ return node;
+}
+
+static struct napt_ct *
+napt_hash_find(a_uint32_t ct_addr, a_uint32_t *hash_cnt,
+ struct napt_ct *hash, struct nhlist_head *hash_head)
+{
+ struct napt_ct *entry = 0;
+ struct nhlist_head *head = 0;
+ a_uint32_t hash_index = NAPT_CT_HASH(ct_addr);
+
+ if(*hash_cnt == 0)
+ {
+ return NULL;
+ }
+#if 0 /* prevent empty entries. */
+ if(*hash_cnt >= NAPT_BUFFER_SIZE)
+ {
+ return NULL;
+ }
+#endif
+
+ head = &(hash_head[hash_index]);
+
+ if(head->next == 0)
+ {
+ return NULL;
+ }
+ entry = head->next;
+ do
+ {
+ if(ct_addr == entry->ct_addr)
+ {
+ return entry;
+ }
+
+ entry = entry->next;
+ }
+ while(entry);
+
+ return NULL;
+}
+
+static a_int32_t
+napt_ct_buf_init(void)
+{
+ return napt_hash_buf_init(&ct_buf, &ct_buf_hash_head);
+}
+
+static void
+napt_ct_buf_exit(void)
+{
+ if(ct_buf_hash_head)
+ kfree(ct_buf_hash_head);
+
+ if(ct_buf)
+ kfree(ct_buf);
+}
+
+static void
+napt_ct_buf_flush(void)
+{
+ ct_buf_ct_cnt = 0;
+ memset(ct_buf,0,sizeof(struct napt_ct)*NAPT_BUFFER_SIZE);
+ memset(ct_buf_hash_head,0,sizeof(struct nhlist_head)*NAPT_BUFFER_HASH_SIZE);
+}
+
+static a_uint32_t
+napt_ct_cnt_get(void)
+{
+ return ct_buf_ct_cnt;
+}
+
+static struct napt_ct *
+napt_ct_buf_ct_find(a_uint32_t ct_addr)
+{
+ return napt_hash_find(ct_addr, &ct_buf_ct_cnt,
+ ct_buf, ct_buf_hash_head);
+}
+
+static a_uint64_t
+napt_ct_buf_pkts_get(struct napt_ct *napt_ct)
+{
+ return napt_ct->ct_packets;
+}
+
+static void
+napt_ct_buf_pkts_update(struct napt_ct *napt_ct, a_uint64_t packets)
+{
+ napt_ct->ct_packets = packets;
+}
+
+static a_uint8_t
+napt_ct_buf_deny_get(struct napt_ct *napt_ct)
+{
+ return napt_ct->deny;
+}
+
+static void
+napt_ct_buf_deny_set(struct napt_ct *napt_ct, a_uint8_t deny)
+{
+ napt_ct->deny = deny;
+}
+
+static void
+napt_ct_buf_deny_clear(struct napt_ct *napt_ct)
+{
+ napt_ct->deny = 0;
+}
+
+static a_uint8_t
+napt_ct_buf_in_hw_get(struct napt_ct *napt_ct, a_uint16_t *hw_index)
+{
+ *hw_index = napt_ct->hw_index;
+ return napt_ct->in_hw;
+}
+
+static void
+napt_ct_buf_in_hw_set(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+ napt_ct->in_hw = 1;
+ napt_ct->hw_index = hw_index;
+}
+
+static void
+napt_ct_buf_in_hw_clear(struct napt_ct *napt_ct)
+{
+ napt_ct->in_hw = 0;
+ napt_ct->hw_index = 0;
+}
+
+static void
+napt_ct_buf_ct_info_clear(struct napt_ct *napt_ct)
+{
+ napt_ct->ct_addr = 0;
+ napt_ct->ct_packets = 0;
+}
+
+static struct napt_ct *
+napt_ct_buf_ct_add(a_uint32_t ct_addr)
+{
+ struct napt_ct *napt_ct;
+ napt_ct = napt_hash_add(ct_addr, &ct_buf_ct_cnt,
+ ct_buf, ct_buf_hash_head);
+
+ if(napt_ct)
+ {
+ /*ct pkts initial*/
+ napt_ct_buf_pkts_update(napt_ct, NAPT_CT_PKTS_GET(ct_addr));
+ }
+
+ return napt_ct;
+}
+
+#define NAPT_CT_PERMANENT_DENY 5
+static a_uint32_t napt_ct_addr[NAPT_TABLE_SIZE] = {0};
+
+#define NAPT_CT_PACKET_THRES_BASE (50)
+static a_uint64_t packets_bdir_total = 0;
+static a_uint64_t packets_bdir_thres = 0;
+
+static inline a_int32_t
+before(a_uint64_t seq1, a_uint64_t seq2)
+{
+ return ((int64_t)(seq1-seq2) < 0);
+}
+
+static a_uint8_t
+napt_ct_pkts_reach_thres(a_uint32_t ct_addr, struct napt_ct *napt_ct,
+ a_uint8_t pkts_sum)
+{
+ a_uint64_t packets_bdir_old = napt_ct_buf_pkts_get(napt_ct);
+ a_uint64_t packets_bdir_new = NAPT_CT_PKTS_GET(ct_addr);
+
+ if(pkts_sum)
+ {
+ if(packets_bdir_new > packets_bdir_old)
+ {
+ packets_bdir_total += (packets_bdir_new - packets_bdir_old);
+ }
+ }
+
+ napt_ct_buf_pkts_update(napt_ct, packets_bdir_new);
+
+ HNAT_PRINTK("<%s> ct:%x packets_bdir_old:%lld ==> packets_bdir_new:%lld\n",
+ __func__, ct_addr, packets_bdir_old, packets_bdir_new);
+
+ if(before((packets_bdir_old+packets_bdir_thres), packets_bdir_new))
+ {
+ return 1;
+ }
+
+ return 0;
+}
+
+static a_int32_t
+napt_ct_hw_add(a_uint32_t ct_addr, a_uint16_t *hw_index)
+{
+ napt_entry_t napt = {0};
+ a_uint32_t index;
+
+ if (!ct_addr)
+ return -1;
+
+ NAPT_CT_TO_HW_ENTRY(ct_addr, &napt);
+
+ if(nat_hw_pub_ip_add(napt.trans_addr, &index) == 0)
+ {
+ napt.trans_addr = index;
+
+ }
+ else
+ {
+ HNAT_ERR_PRINTK("####%s##nat_hw_pub_ip_add fail!\n", __func__);
+ return -1;
+ }
+
+ sw_error_t rv = napt_hw_add(&napt);
+
+ if(rv == 0)
+ {
+ HNAT_PRINTK("%s: success entry_id:0x%x ct 0x%x\n", __func__, napt.entry_id, ct_addr);
+
+ if(napt_ct_addr[napt.entry_id])
+ {
+ HNAT_ERR_PRINTK("fault: napt HW:%x can not be overwrited!\n",
+ napt.entry_id);
+
+ }
+ else
+ {
+ napt_ct_addr[napt.entry_id] = ct_addr;
+ *hw_index = napt.entry_id;
+ // Added from 1.0.7 for default route.
+ napt_set_default_route(napt.dst_addr, napt.src_addr);
+
+ return 0;
+ }
+ }
+ else
+ {
+ HNAT_PRINTK("%s:fail rv:%d entry_id:%x(maybe full)\n",
+ __func__,rv, napt.entry_id);
+ nat_hw_pub_ip_del(napt.trans_addr);
+ }
+
+ return -1;
+}
+
+static a_int32_t
+napt_ct_hw_del (napt_entry_t *napt)
+{
+ if(napt_hw_del(napt)!= 0)
+ {
+ HNAT_ERR_PRINTK("%s: isis_napt_del fail\n", __func__);
+ return -1;
+ }
+ if(nat_hw_pub_ip_del(napt->trans_addr) != 0)
+ {
+ HNAT_ERR_PRINTK("%s: public_ip_del fail\n", __func__);
+ //return -1;
+ }
+ return 0;
+}
+
+static a_int32_t
+napt_ct_del(struct napt_ct *napt_ct, napt_entry_t *napt)
+{
+ a_uint16_t hw_index = napt->entry_id;
+
+ HNAT_PRINTK("%s: 0x%x ct 0x%x\n", __FUNCTION__, hw_index, napt_ct_addr[hw_index]);
+
+ if(napt_ct_hw_del(napt) != 0)
+ {
+ return -1;
+ }
+
+ NAPT_CT_AGING_ENABLE(napt_ct_addr[hw_index]);
+ napt_ct_addr[hw_index] = 0;
+
+ if(napt_ct)
+ {
+ napt_ct_buf_in_hw_clear(napt_ct);
+
+ if(napt_ct_buf_deny_get(napt_ct) != NAPT_CT_PERMANENT_DENY)
+ {
+ napt_ct_buf_ct_info_clear(napt_ct);
+ }
+ }
+
+ return 0;
+}
+
+static a_int32_t
+napt_ct_del_by_index (struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+ napt_entry_t napt = {0};
+
+ if(napt_hw_get_by_index(&napt, hw_index) != 0)
+ {
+ return -1;
+ }
+
+ return napt_ct_del(napt_ct, &napt);
+}
+
+static a_int32_t
+napt_ct_in_hw_sanity_check(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+ if(!napt_ct)
+ {
+ HNAT_ERR_PRINTK("<%s>hw_index:%d error napt_ct can't find\n",
+ __func__, hw_index);
+ return -1;
+ }
+
+ a_uint16_t ct_hw_index;
+ if(napt_ct_buf_in_hw_get(napt_ct, &ct_hw_index) == 0)
+ {
+ HNAT_ERR_PRINTK("<%s>hw_index:%d in_hw:0 error\n",
+ __func__, hw_index);
+ return -1;
+ }
+
+ if(hw_index != ct_hw_index)
+ {
+ HNAT_ERR_PRINTK("<%s>hw_index:%d buf_hw_index:%d\n",
+ __func__, hw_index, ct_hw_index);
+ return -1;
+ }
+
+ return 0;
+}
+
+void
+napt_ct_hw_aging(void)
+{
+#define NAPT_AGEOUT_STATUS 1
+
+ a_uint32_t ct_addr;
+ napt_entry_t napt = {0};
+
+ HNAT_PRINTK("[aging_scan start]\n");
+
+ if(napt_hw_first_by_age(&napt, NAPT_AGEOUT_STATUS) != 0)
+ {
+ return;
+ }
+
+ do
+ {
+ a_uint16_t hw_index = napt.entry_id;
+ ct_addr = napt_ct_addr[hw_index];
+
+ struct napt_ct *napt_ct = NULL;
+
+ if(ct_addr)
+ {
+ napt_ct = napt_ct_buf_ct_find(ct_addr);
+ if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0)
+ {
+ HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__);
+ continue;
+ }
+
+ if(napt_ct_pkts_reach_thres(ct_addr, napt_ct, 0))
+ {
+ printk("<aging>set PERMANENT deny ct:%x\n", ct_addr);
+ napt_ct_buf_deny_set(napt_ct, NAPT_CT_PERMANENT_DENY);
+ }
+ }
+ else
+ {
+ HNAT_ERR_PRINTK("<aging> error: in_hw but ct = NULL hw_index:%x\n", hw_index);
+ }
+
+ napt_ct_del(napt_ct, &napt);
+
+ }
+ while(napt_hw_next_by_age(&napt, NAPT_AGEOUT_STATUS) != -1);
+
+#if 0
+ if(napt_hw_used_count_get() == 0)
+ {
+ nat_hw_prv_base_update_enable();
+ }
+#endif
+
+ HNAT_PRINTK("[aging_scan end]\n");
+
+ return;
+}
+
+
+#define NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index) \
+ ((napt_ct_valid[hw_index] == 0) && \
+ (napt_ct_addr[hw_index] != 0))
+static a_uint32_t
+napt_ct_hw_sync(a_uint8_t napt_ct_valid[])
+{
+ a_uint16_t hw_index;
+ a_uint32_t napt_ct_offload_cnt = 0;
+
+ for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++)
+ {
+ if(NAPT_INVALID_CT_NEED_HW_CLEAR(hw_index))
+ {
+
+ a_uint32_t ct_addr = napt_ct_addr[hw_index];
+ struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr);
+
+ if(napt_ct_in_hw_sanity_check(napt_ct, hw_index) != 0)
+ {
+ HNAT_ERR_PRINTK("<%s> napt_ct_in_hw_sanity_check fail\n", __func__);
+ continue;
+ }
+
+ if(napt_ct_del_by_index(napt_ct, hw_index) == 0)
+ {
+ napt_ct_buf_deny_clear(napt_ct);
+ }
+ else
+ {
+ HNAT_ERR_PRINTK("<napt_ct_hw_sync>hw_index:%d napt_hw_del_by_index fail\n",
+ hw_index);
+ }
+ }
+
+ if(napt_ct_valid[hw_index])
+ {
+ napt_ct_offload_cnt++;
+ }
+ }
+
+ return napt_ct_offload_cnt;
+}
+
+static void
+napt_ct_frag_hw_yield(struct napt_ct *napt_ct, a_uint16_t hw_index)
+{
+ napt_entry_t napt = {0};
+
+ /*os and hw are both traffic; hw offload giveup*/
+ if(napt_hw_get_by_index(&napt, hw_index) == 0)
+ {
+ if(napt.status == 0xe)
+ {
+ a_uint8_t deny = napt_ct_buf_deny_get(napt_ct);
+ napt_ct_buf_deny_set(napt_ct, (++deny));
+
+ if(deny >= NAPT_CT_PERMANENT_DENY)
+ {
+ /*os service only*/
+ HNAT_ERR_PRINTK("<napt_ct_frag_hw_yield> hw service deny\n");
+ napt_ct_del(napt_ct, &napt);
+ }
+
+ printk("<napt_ct_frag_hw_yield> deny:%d\n", deny);
+ }
+ }
+}
+
+#define NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr) ((in_hw) && \
+ NAPT_CT_AGING_IS_ENABLE(ct_addr))
+static a_int32_t
+napt_ct_check_add_one(a_uint32_t ct_addr, a_uint8_t *napt_ct_valid)
+{
+ struct napt_ct *napt_ct = NULL;
+ a_uint16_t hw_index;
+ a_uint8_t in_hw;
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+
+ if((napt_ct = napt_ct_buf_ct_find(ct_addr)) == NULL)
+ {
+ if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL)
+ {
+ HNAT_ERR_PRINTK("<napt_ct_scan> error hash full\n");
+ return -1;
+ }
+ }
+
+ if(napt_ct_buf_deny_get(napt_ct) >= NAPT_CT_PERMANENT_DENY)
+ {
+ printk("<napt_ct_scan> ct:%x is PERMANENT deny\n",
+ ct_addr);
+ return -1;
+
+ }
+ else
+ {
+ if (napt_ct_pkts_reach_thres(ct_addr, napt_ct, 1))
+ {
+ if(napt_ct_buf_in_hw_get(napt_ct, &hw_index))
+ {
+ printk("<napt_ct_scan> ct:%x* is exist\n",
+ ct_addr);
+ napt_ct_frag_hw_yield(napt_ct, hw_index);
+
+ }
+ else
+ {
+ if(napt_ct_hw_add(ct_addr, &hw_index) == 0)
+ {
+ NAPT_CT_AGING_DISABLE(ct_addr);
+ napt_ct_buf_in_hw_set(napt_ct, hw_index);
+ ct->in_hnat = 1; /* contrack in HNAT now. */
+ }
+ }
+ }
+
+ in_hw = napt_ct_buf_in_hw_get(napt_ct, &hw_index);
+ if(in_hw)
+ {
+ if(!NAPT_CT_IS_REUSED_BY_OS(in_hw, ct_addr))
+ {
+ napt_ct_valid[hw_index] = 1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static void
+napt_ct_pkts_thres_calc_init(void)
+{
+ packets_bdir_total = 0;
+ packets_bdir_thres = NAPT_CT_PACKET_THRES_BASE;
+
+}
+
+a_uint64_t
+uint64_div_uint32(a_uint64_t div, a_uint32_t base)
+{
+ register a_uint32_t i;
+ a_uint64_t result;
+
+ union
+ {
+ a_uint64_t n64[2];
+ struct
+ {
+ a_uint32_t l0;// 0
+ a_uint32_t h0;// 1
+ a_uint32_t l1;// 2
+ a_uint32_t h1;// 3
+ } n32;
+ } n;
+
+ if(base == 0)
+ {
+ return 0;
+ }
+
+ if(div < base)
+ {
+ return 0;
+ }
+
+ n.n64[0] = div;
+ n.n64[1] = 0;
+ result = 0;
+ i = 0;
+
+ //if div is 32bits, set start from 32
+ if(n.n32.h0 == 0)
+ {
+ n.n32.h0 = n.n32.l0;
+ n.n32.l0 = 0;
+ i = 32;
+ }
+
+ //left shift until highest bit
+ for(; i<64; ++i)
+ {
+ if((n.n32.h0 & 0x80000000) == 0x80000000)
+ {
+ break;
+ }
+ else
+ {
+ n.n64[0] = n.n64[0] << 1;
+ }
+ }
+
+ for (; i<64; ++i)
+ {
+ n.n64[1] = (n.n64[1] << 1) + (n.n64[0] >> 63);
+ n.n64[0] = (n.n64[0] << 1);
+ result = result << 1 ;
+
+ if(n.n64[1] >= base)
+ {
+ n.n64[1] = n.n64[1]- base;
+ ++result;
+ }
+ }
+
+ return result;
+}
+
+static void
+napt_ct_pkts_thres_calc(a_uint32_t cnt, a_uint32_t napt_ct_offload_cnt)
+{
+ a_uint64_t packets_bdir_avg = 0;
+ a_uint64_t packets_bdir_thres_temp = 0;
+
+ /*ct_avg_pkts* (1+ (ct_offload_cnt/ct_hw_max) )*/
+ packets_bdir_avg = uint64_div_uint32(packets_bdir_total, cnt);
+ packets_bdir_thres_temp = packets_bdir_avg +
+ uint64_div_uint32((packets_bdir_avg *(a_uint64_t)napt_ct_offload_cnt),
+ NAPT_TABLE_SIZE);
+
+ if(packets_bdir_thres_temp > NAPT_CT_PACKET_THRES_BASE)
+ {
+ packets_bdir_thres = packets_bdir_thres_temp;
+ }
+
+ //HNAT_ERR_PRINTK("###<%s> total:%lld cnt:%d avg:%lld threshold:%lld###\n", __func__,
+ // packets_bdir_total, cnt, packets_bdir_avg, packets_bdir_thres);
+ HNAT_ERR_PRINTK("calc pkts avg:%lld offload_cnt:%d threshold:%lld\n",
+ packets_bdir_avg, napt_ct_offload_cnt, packets_bdir_thres);
+}
+
+#define NAPT_CT_SHOULD_CARE(ct) ((ct) && \
+ NAPT_CT_TYPE_IS_NAT(ct) && \
+ NAPT_CT_STATUS_IS_ESTAB(ct) &&\
+ nat_hw_prv_base_is_match( \
+ NAPT_CT_PRIV_IP_GET(ct)))
+static a_int32_t
+napt_ct_check_add(void)
+{
+ a_uint32_t ct_addr = 0;
+ a_uint32_t ct_buf_valid_cnt = 0;
+ a_uint32_t hash = 0, iterate = 0;
+ a_uint8_t napt_ct_valid[NAPT_TABLE_SIZE] = {0};
+
+ napt_ct_pkts_thres_calc_init();
+
+ NAPT_CT_LIST_LOCK();
+
+ while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate)))
+ {
+ if (NAPT_CT_SHOULD_CARE(ct_addr))
+ {
+ if(napt_ct_check_add_one(ct_addr, napt_ct_valid) != -1)
+ {
+ ct_buf_valid_cnt++;
+ }
+ }
+ }
+
+ NAPT_CT_LIST_UNLOCK();
+
+ a_uint32_t napt_ct_offload_cnt = napt_ct_hw_sync(napt_ct_valid);
+
+ napt_ct_pkts_thres_calc(ct_buf_valid_cnt, napt_ct_offload_cnt);
+
+ return ct_buf_valid_cnt;
+}
+
+static a_int32_t
+napt_ct_add(a_uint32_t ct_addr, a_uint8_t *napt_ct_valid)
+{
+ struct napt_ct *napt_ct;
+
+ if((napt_ct = napt_ct_buf_ct_add(ct_addr)) == NULL)
+ {
+ HNAT_ERR_PRINTK("<napt_ct_buffer_update> error hash full\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static a_int32_t
+napt_ct_buffer_ct_status_update(void)
+{
+ a_uint32_t ct_addr = 0;
+ a_uint32_t hash = 0;
+ a_uint32_t iterate = 0;
+
+ NAPT_CT_LIST_LOCK();
+
+ while((ct_addr = NAPT_CT_LIST_ITERATE(&hash, &iterate)))
+ {
+ if (NAPT_CT_SHOULD_CARE(ct_addr))
+ {
+ napt_ct_add(ct_addr, NULL);
+ }
+ }
+
+ NAPT_CT_LIST_UNLOCK();
+
+ return 0;
+}
+
+static void
+napt_ct_buffer_hw_status_update(void)
+{
+ a_uint16_t hw_index;
+
+ for(hw_index = 0; hw_index < NAPT_TABLE_SIZE; hw_index++)
+ {
+ a_uint32_t ct_addr = napt_ct_addr[hw_index];
+ if(ct_addr)
+ {
+ struct napt_ct *napt_ct = napt_ct_buf_ct_find(ct_addr);
+ if(napt_ct)
+ {
+ napt_ct_buf_in_hw_set(napt_ct, hw_index);
+
+ }
+ else
+ {
+ if(napt_ct_del_by_index(napt_ct, hw_index) != 0)
+ {
+ HNAT_ERR_PRINTK("<%s>hw_index:%d napt_ct_del_by_index fail\n",
+ __func__, hw_index);
+ }
+ }
+ }
+ }
+
+ return;
+}
+
+static void
+napt_ct_buffer_refresh(void)
+{
+ HNAT_PRINTK("napt_ct_buffer_refresh\n");
+
+ napt_ct_buf_flush();
+
+ napt_ct_buffer_ct_status_update();
+ napt_ct_buffer_hw_status_update();
+}
+
+static void
+napt_ct_buffer_refresh_check(a_uint32_t ct_buf_valid_cnt)
+{
+#define NAPT_CT_BUF_REFRESH_THRES 1000
+ HNAT_ERR_PRINTK("ct_buffer_hash_cnt:%d cnt:%d max:%d\n",
+ napt_ct_cnt_get(), ct_buf_valid_cnt/2, NAPT_CT_BUF_REFRESH_THRES);
+
+ if((napt_ct_cnt_get() - ct_buf_valid_cnt/2) > NAPT_CT_BUF_REFRESH_THRES)
+ {
+ napt_ct_buffer_refresh();
+ }
+}
+
+static void
+napt_ct_hw_exit(void)
+{
+ a_uint8_t napt_ct_valid[NAPT_TABLE_SIZE];
+
+ /*set all ct invalid to cleanup*/
+ memset(napt_ct_valid, 0, sizeof(napt_ct_valid));
+
+ napt_ct_hw_sync(napt_ct_valid);
+}
+
+void
+napt_ct_scan(void)
+{
+ a_uint32_t ct_buf_valid_cnt = 0;
+
+ ct_buf_valid_cnt = napt_ct_check_add();
+
+ napt_ct_buffer_refresh_check(ct_buf_valid_cnt);
+}
+
+
+static a_int32_t
+napt_ct_init(void)
+{
+ napt_hw_mode_init();
+
+ if(napt_ct_buf_init() != 0)
+ {
+ HNAT_PRINTK("*****napt_ct_buf_init fail*******\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static a_int32_t
+napt_ct_exit(void)
+{
+ napt_ct_hw_exit();
+ napt_ct_buf_exit();
+
+ return 0;
+}
+
+static a_int32_t
+napt_ct_scan_thread(void *param)
+{
+#define NAPT_CT_POLLING_SEC 5
+#define NAPT_CT_AGING_SEC 20
+#define ARP_CHECK_AGING_SEC 40
+
+ a_uint32_t times = (NAPT_CT_AGING_SEC/NAPT_CT_POLLING_SEC);
+ a_uint32_t arp_check_time = (ARP_CHECK_AGING_SEC/NAPT_CT_POLLING_SEC);
+ // a_bool_t l3_enable;
+
+ if(napt_ct_init() != 0)
+ {
+ HNAT_PRINTK("*****napt_ct_init fail*******\n");
+ return 0;
+ }
+
+ while(1)
+ {
+ napt_ct_scan();
+
+ if((--times) == 0)
+ {
+ napt_ct_hw_aging();
+ times = (NAPT_CT_AGING_SEC/NAPT_CT_POLLING_SEC);
+ }
+
+ if((--arp_check_time) == 0)
+ {
+ host_check_aging();
+ arp_check_time = (ARP_CHECK_AGING_SEC/NAPT_CT_POLLING_SEC);
+ }
+
+#ifdef ISISC /* only for S17c */
+ napt_set_ipv6_default_route();
+#endif
+
+ if (NAPT_CT_TASK_SHOULD_STOP())
+ break;
+
+ NAPT_CT_TASK_SLEEP(NAPT_CT_POLLING_SEC);
+ }
+
+ napt_ct_exit();
+
+ return 0;
+}
+
+void
+napt_helper_init(void)
+{
+ const char napt_thread_name[] = "napt_ct_scan";
+
+ NAPT_CT_TASK_START(napt_ct_scan_thread, napt_thread_name);
+}
+
+
+void
+napt_helper_exit(void)
+{
+ NAPT_CT_TASK_STOP();
+}
+
diff --git a/app/nathelper/linux/lib/nat_helper_dt.h b/app/nathelper/linux/lib/nat_helper_dt.h
new file mode 100644
index 0000000..f949bba
--- /dev/null
+++ b/app/nathelper/linux/lib/nat_helper_dt.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _NAT_HELPER_DT_H
+#define _NAT_HELPER_DT_H
+
+extern void host_check_aging(void);
+
+#endif /*_NAT_HELPER_DT_H*/
diff --git a/app/nathelper/linux/lib/nat_helper_hsl.c b/app/nathelper/linux/lib/nat_helper_hsl.c
new file mode 100644
index 0000000..443bae9
--- /dev/null
+++ b/app/nathelper/linux/lib/nat_helper_hsl.c
@@ -0,0 +1,667 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+#include <linux/netfilter_arp.h>
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <net/netfilter/nf_conntrack.h>
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+
+#include "hsl_api.h"
+#include "hsl.h"
+#include "hsl_shared_api.h"
+#include "../nat_helper.h"
+#include "nat_helper_hsl.h"
+#include "../napt_acl.h"
+
+static a_uint8_t
+hw_debug_counter_get(void)
+{
+ static a_uint32_t debug_counter = 0;
+
+ return ((debug_counter++) & 0x7);
+}
+
+a_int32_t
+nat_hw_add(nat_entry_t *nat)
+{
+ fal_nat_entry_t hw_nat = {0};
+
+ hw_nat.flags = nat->flags;
+ hw_nat.src_addr = nat->src_addr;
+ hw_nat.trans_addr = nat->trans_addr;
+ hw_nat.port_num = nat->port_num;
+ hw_nat.port_range = nat->port_range;
+ hw_nat.counter_en = 1;
+ hw_nat.counter_id = hw_debug_counter_get();
+
+ if(NAT_ADD(0, &hw_nat) != 0)
+ {
+ return -1;
+ }
+ nat->entry_id = hw_nat.entry_id;
+
+ return 0;
+}
+
+a_int32_t
+nat_hw_del_by_index(a_uint32_t index)
+{
+ fal_nat_entry_t nat_entry = {0};
+
+ HNAT_PRINTK("NAT_DEL(1) index=%d########\n", index);
+
+ nat_entry.entry_id = index;
+ if(NAT_DEL(0, FAL_NAT_ENTRY_ID_EN, &nat_entry)!= 0)
+ {
+ return -1;
+ }
+
+ return 0;
+}
+
+a_int32_t
+nat_hw_flush(void)
+{
+ if(NAT_DEL(0, 0, 0)!= 0)
+ {
+ return -1;
+ }
+
+ return 0;
+}
+
+a_int32_t
+napt_hw_flush(void)
+{
+ if(NAPT_DEL(0, 0, 0)!= 0)
+ {
+ return -1;
+ }
+
+ return 0;
+}
+
+static a_uint32_t private_ip_can_update = 1;
+a_int32_t
+nat_hw_prv_base_can_update(void)
+{
+ return private_ip_can_update;
+}
+
+void
+nat_hw_prv_base_update_enable(void)
+{
+ private_ip_can_update = 1;
+}
+
+void
+nat_hw_prv_base_update_disable(void)
+{
+ private_ip_can_update = 0;
+}
+
+static a_uint32_t private_ip_base = 0xc0a80000;
+static a_uint32_t private_net_mask = 0xffffff00;
+a_int32_t
+nat_hw_prv_base_set(a_uint32_t ip)
+{
+#define PRIVATE_IP_MASK 0xfffff000
+
+ ip = ntohl(ip);
+#ifdef ISIS
+ private_ip_base = ip & PRIVATE_IP_MASK;
+#else
+ private_ip_base = ip & nat_hw_prv_mask_get();
+#endif
+
+ if (NAT_PRV_BASE_ADDR_SET(0, (fal_ip4_addr_t)ip) != 0)
+ {
+ return -1;
+ }
+
+ HNAT_PRINTK("%s: private_ip_base:%x private_ip_can_update:%d\n",
+ __func__, private_ip_base, private_ip_can_update);
+
+ return 0;
+}
+
+a_uint32_t
+nat_hw_prv_base_get(void)
+{
+ return private_ip_base;
+}
+
+#ifdef ISISC
+a_int32_t
+nat_hw_prv_mask_set(a_uint32_t ipmask)
+{
+ ipmask = ntohl(ipmask);
+
+ if (NAT_PRV_BASE_MASK_SET(0, (fal_ip4_addr_t)ipmask) != 0)
+ {
+ return -1;
+ }
+ private_net_mask = ipmask;
+
+ HNAT_PRINTK("%s: 0x%08x\n", __FUNCTION__, private_net_mask);
+
+ return 0;
+}
+
+a_uint32_t
+nat_hw_prv_mask_get(void)
+{
+ return private_net_mask;
+}
+#endif
+
+a_int32_t
+nat_hw_prv_base_is_match(a_uint32_t ip)
+{
+#define PRIVATE_IP_MASK 0xfffff000
+
+ a_uint32_t prv_base = private_ip_base;
+ a_uint32_t prv_mask;
+
+#ifdef ISIS
+ if((prv_base & PRIVATE_IP_MASK) == (ip & PRIVATE_IP_MASK))
+#else
+ prv_mask = nat_hw_prv_mask_get();
+ if((prv_base & prv_mask) == (ip & prv_mask))
+#endif
+ {
+ return 1;
+ }
+
+ HNAT_PRINTK("%s: private_ip_base:%x usaddr:%x mismatch\n",
+ __func__, prv_base, ip);
+
+ return 0;
+}
+
+static a_int32_t
+_arp_hw_if_mac_add(fal_intf_mac_entry_t *if_mac_entry)
+{
+ return IP_INTF_ENTRY_ADD(0, if_mac_entry);
+}
+
+a_int32_t
+if_mac_add(a_uint8_t *mac, a_uint8_t vid, uint32_t ipv6)
+{
+ /* support 4 different interfaces (or 4 VLANs) */
+ static fal_intf_mac_entry_t if_mac_entry[MAX_INTF_NUM] = {{0}};
+ static a_uint8_t if_mac_count = 0;
+ a_uint8_t i = 0;
+
+ for(i = 0; i < if_mac_count; i++)
+ {
+ if((!memcmp(if_mac_entry[i].mac_addr.uc, mac, 6)) &&
+ (if_mac_entry[i].vid_low == vid))
+ {
+ HNAT_PRINTK("%s: mac exist id:%d\n", __func__,
+ if_mac_entry[if_mac_count].entry_id);
+ return 0;
+ }
+ }
+
+ if(if_mac_count == MAX_INTF_NUM)
+ {
+ HNAT_PRINTK("%s: reach mac count max\n", __func__);
+ return -1;
+ }
+
+ memset(&if_mac_entry[if_mac_count], 0, sizeof(fal_intf_mac_entry_t));
+ memcpy(if_mac_entry[if_mac_count].mac_addr.uc, mac, 6);
+
+ if_mac_entry[if_mac_count].entry_id = if_mac_count;
+ if (1 == ipv6)
+ {
+ if_mac_entry[if_mac_count].ip6_route = 1;
+ }
+ else
+ {
+ if_mac_entry[if_mac_count].ip6_route = 0;
+ }
+ if_mac_entry[if_mac_count].ip4_route = 1;
+
+ if (vid == 0)
+ {
+ if_mac_entry[if_mac_count].vid_low = 0;
+ if_mac_entry[if_mac_count].vid_high = 511;
+ }
+ else
+ {
+ if_mac_entry[if_mac_count].vid_low = vid;
+ if_mac_entry[if_mac_count].vid_high = vid;
+ }
+
+ if(_arp_hw_if_mac_add(&if_mac_entry[if_mac_count])!= 0)
+ {
+ return -1;
+ }
+
+ HNAT_PRINTK("%s: count:%d index:%d vid:%d mac:%02x-%02x-%02x-%02x-%02x-%02x\n",
+ __func__, if_mac_count, if_mac_entry[if_mac_count].entry_id, vid,
+ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]);
+ if_mac_count ++;
+
+ return 0;
+}
+
+static a_int32_t
+_arp_hw_add(fal_host_entry_t *arp_entry)
+{
+ return IP_HOST_ADD(0, arp_entry);
+}
+
+a_int32_t
+arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry)
+{
+ fal_host_entry_t arp_entry;
+
+#ifdef ISIS /* Only for AR8337(S17) */
+ if (NF_S17_WAN_TYPE_PPPOEV6 == nf_athrs17_hnat_wan_type)
+ {
+ memset(&arp_entry,0,sizeof(arp_entry));
+ memcpy(&arp_entry.ip4_addr, ip, 4);
+ memcpy(arp_entry.mac_addr.uc, mac, 6);
+ arp_entry.status = ARP_AGE_NEVER;
+ if (port == S17_WAN_PORT)
+ {
+ arp_entry.port_id = port;
+ }
+ else
+ {
+ arp_entry.port_id = 6; /* always assigned to MAC 6 */
+ }
+ arp_entry.flags = FAL_IP_IP4_ADDR;
+ }
+ else
+#endif /* not ISIS */
+ {
+ memset(&arp_entry,0,sizeof(arp_entry));
+ if (0 == is_ipv6_entry)
+ {
+ memcpy(&arp_entry.ip4_addr, ip, 4);
+ arp_entry.ip4_addr = ntohl(arp_entry.ip4_addr);
+ arp_entry.flags = FAL_IP_IP4_ADDR;
+ }
+ else
+ {
+ memcpy(&arp_entry.ip6_addr, ip, 16);
+ arp_entry.flags = FAL_IP_IP6_ADDR;
+ }
+ memcpy(arp_entry.mac_addr.uc, mac, 6);
+ if ((NF_S17_WAN_TYPE_PPPOE == nf_athrs17_hnat_wan_type) && \
+ (S17_WAN_PORT == port))
+ {
+ arp_entry.status = ARP_AGE_NEVER;
+ }
+ else
+ {
+ arp_entry.status = ARP_AGE;
+ }
+ arp_entry.port_id = port;
+ }
+
+ arp_entry.intf_id = intf_id;
+
+ arp_entry.counter_en = 1;
+ if (S17_WAN_PORT == port)
+ {
+ arp_entry.counter_id = 0xf;
+ }
+ else
+ {
+ arp_entry.counter_id = hw_debug_counter_get();
+ }
+
+ if(_arp_hw_add(&arp_entry) != 0)
+ {
+ printk("%s: fail\n", __func__);
+ return -1;
+ }
+
+ if (0 == is_ipv6_entry)
+ {
+ HNAT_PRINTK("%s: index:%x port:%d ip:%d.%d.%d.%d\n",
+ __func__, arp_entry.entry_id, port,
+ *(ip), *(ip+1), *(ip+2), *(ip+3));
+ }
+
+ if (0 != (arp_entry.entry_id & 0xFFFFFC00))
+ {
+ printk("Warning: arp_entry id should be only 10 bits!\n");
+ }
+
+ return arp_entry.entry_id;
+}
+
+#define AOS_HEADER_MAGIC 0xC0DE
+
+a_int32_t
+arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid)
+{
+ if((data==0) || (sport==0) || (vid==0))
+ {
+ return -1;
+ }
+
+ aos_header_t *athr_header = (aos_header_t *)data;
+
+#if 0
+ /*atheros header magic check*/
+ if(athr_header->magic != AOS_HEADER_MAGIC)
+ {
+ return -1;
+ }
+#endif
+
+ *sport = athr_header->sport;
+ *vid = athr_header->vid;
+
+ return 0;
+}
+
+#define MAX_PUBLIC_IP_CNT 16
+struct public_ip_shadow
+{
+ a_uint32_t ip;
+ a_uint32_t use_cnt;
+};
+
+static struct public_ip_shadow public_ip_shadow[MAX_PUBLIC_IP_CNT]= {{0}};
+static a_uint32_t public_ip_cnt = 0;
+
+a_int32_t
+nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index)
+{
+ sw_error_t rv;
+ a_uint32_t hw_index;
+ a_uint32_t i;
+
+ for(i=0; i<MAX_PUBLIC_IP_CNT; i++)
+ {
+ if((ip == public_ip_shadow[i].ip) && (public_ip_shadow[i].use_cnt))
+ {
+ public_ip_shadow[i].use_cnt++;
+ *index = i;
+ return 0;
+ }
+ }
+
+ if(public_ip_cnt >= MAX_PUBLIC_IP_CNT)
+ {
+ return -1;
+ }
+
+ fal_nat_pub_addr_t ip_entry = {0};
+ ip_entry.pub_addr = ip;
+ rv = NAT_PUB_ADDR_ADD(0,&ip_entry);
+ if(rv != 0)
+ {
+ return -1;
+ }
+
+ public_ip_cnt++;
+ hw_index = ip_entry.entry_id;
+ public_ip_shadow[hw_index].ip = ip;
+ public_ip_shadow[hw_index].use_cnt++;
+ *index = hw_index;
+
+ HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
+ __func__, public_ip_cnt, hw_index, public_ip_shadow[hw_index].ip);
+ return 0;
+}
+
+
+void
+napt_hw_mode_init(void)
+{
+ sw_error_t rv;
+ /* age_speedup+age_thres_1/4+age_step_4+age_timer_28s*1+
+ stop_age_when1+overwrite_disable */
+ /* Also set NAT mode Port strict mode/symmetric mode */
+ a_uint32_t entry = 0x5F01CB;
+
+ HSL_REG_ENTRY_SET(rv, 0, NAT_CTRL, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+
+ HSL_REG_ENTRY_GET(rv, 0, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+ /*set locktime 100us*/
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, GLB_LOCKTIME, 1, entry);
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, ARP_AGE_MODE, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, 0, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+}
+
+a_int32_t
+nat_hw_pub_ip_del(a_uint32_t index)
+{
+ sw_error_t rv;
+
+ if(public_ip_shadow[index].use_cnt>0)
+ {
+ public_ip_shadow[index].use_cnt--;
+ if(public_ip_shadow[index].use_cnt == 0)
+ {
+ HNAT_PRINTK("%s: public_ip_cnt:%d index:%d ip:0x%x\n",
+ __func__, public_ip_cnt, index, public_ip_shadow[index].ip);
+
+ fal_nat_pub_addr_t ip_entry;
+ memset(&ip_entry,0,sizeof(ip_entry));
+ ip_entry.pub_addr = public_ip_shadow[index].ip;
+ rv = NAT_PUB_ADDR_DEL(0, 1, &ip_entry);
+ if(rv != 0)
+ {
+ return -1;
+ }
+
+ public_ip_cnt--;
+ }
+ return 0;
+ }
+
+ return -1;
+}
+
+#define napt_entry_cp(to, from) \
+{ \
+ (to)->entry_id = (from)->entry_id; \
+ (to)->status = (from)->status; \
+ (to)->flags = (from)->flags; \
+ (to)->src_addr = (from)->src_addr; \
+ (to)->src_port = (from)->src_port; \
+ (to)->dst_addr = (from)->dst_addr; \
+ (to)->dst_port = (from)->dst_port; \
+ (to)->trans_addr = (from)->trans_addr; \
+ (to)->trans_port = (from)->trans_port; \
+}
+
+a_int32_t
+napt_hw_add(napt_entry_t *napt)
+{
+ a_int32_t ret = 0;
+ fal_napt_entry_t fal_napt = {0};
+
+ napt_entry_cp(&fal_napt, napt);
+
+ fal_napt.flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+ fal_napt.counter_en = 1;
+ fal_napt.counter_id = hw_debug_counter_get();
+ fal_napt.action = FAL_MAC_FRWRD;
+
+ ret = NAPT_ADD(0, &fal_napt);
+
+ napt->entry_id = fal_napt.entry_id;
+ return ret;
+}
+
+a_int32_t
+napt_hw_del(napt_entry_t *napt)
+{
+ a_int32_t ret = 0;
+
+ fal_napt_entry_t fal_napt = {0};
+
+ napt_entry_cp(&fal_napt, napt);
+
+ ret = NAPT_DEL(0, FAL_NAT_ENTRY_KEY_EN, &fal_napt);
+
+ if(ret != 0)
+ {
+ return -1;
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+a_int32_t
+napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age)
+{
+ a_int32_t ret = 0;
+ fal_napt_entry_t fal_napt = {0};
+
+ fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ fal_napt.status = age;
+
+ if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
+ {
+ ret = -1;
+ }
+
+ napt_entry_cp(napt, &fal_napt);
+
+ return ret;
+}
+
+a_int32_t
+napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age)
+{
+ a_int32_t ret = 0;
+ fal_napt_entry_t fal_napt = {0};
+
+ fal_napt.entry_id = napt->entry_id;
+ fal_napt.status = age;
+
+ if(NAPT_NEXT(0, FAL_NAT_ENTRY_AGE_EN ,&fal_napt) !=0)
+ {
+ ret = -1;
+ }
+
+ napt_entry_cp(napt, &fal_napt);
+
+ return ret;
+}
+
+a_int32_t
+napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index)
+{
+ fal_napt_entry_t fal_napt = {0};
+
+ if(hw_index == 0)
+ {
+ fal_napt.entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ }
+ else
+ {
+ fal_napt.entry_id = hw_index - 1;
+ }
+ sw_error_t rv;
+ if((rv = NAPT_NEXT(0, 0, &fal_napt)) != 0)
+ {
+ HNAT_ERR_PRINTK("<napt_hw_get_by_index>[rv:%d] error hw:%x sw:%x\n",
+ rv, napt->entry_id, hw_index);
+ return -1;
+ }
+
+ napt_entry_cp(napt, &fal_napt);
+
+ if(napt->entry_id != hw_index)
+ {
+ HNAT_ERR_PRINTK("<napt_hw_get_by_index>hw_index error hw:%x sw:%x\n",
+ napt->entry_id, hw_index);
+ return -1;
+ }
+
+ return 0;
+}
+
+a_uint32_t
+napt_hw_used_count_get(void)
+{
+#define NAPT_USED_COUNT
+#define NAPT_USED_COUNT_OFFSET 0x0e44 /*was:0x0e38*/
+#define NAPT_USED_COUNT_E_LENGTH 11
+#define NAPT_USED_COUNT_E_OFFSET 0x0
+#define NAPT_USED_COUNT_NR_E 1
+ sw_error_t rv;
+
+ a_uint32_t count = 0;
+ HSL_REG_ENTRY_GET(rv, 0, NAPT_USED_COUNT, 0, (a_uint8_t *) (&count),
+ sizeof (a_uint32_t));
+
+ return count;
+}
+
+sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, L3_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
diff --git a/app/nathelper/linux/lib/nat_helper_hsl.h b/app/nathelper/linux/lib/nat_helper_hsl.h
new file mode 100644
index 0000000..fa761fc
--- /dev/null
+++ b/app/nathelper/linux/lib/nat_helper_hsl.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _NAT_HELPER_HSL_H
+#define _NAT_HELPER_HSL_H
+
+#include <linux/if_ether.h>
+
+#define NAT_HW_NUM 32
+#define NAT_HW_PORT_RANGE_MAX 255
+
+#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1
+#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2
+#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4
+#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8
+#define FAL_NAT_ENTRY_PORT_CHECK 0x20
+
+#define MAX_INTF_NUM 4
+
+/* WAN connection types */
+#define NF_S17_WAN_TYPE_IP 0 /* DHCP, static IP connection */
+#define NF_S17_WAN_TYPE_PPPOE 1 /* PPPoE connection */
+#define NF_S17_WAN_TYPE_GRE 2 /* GRE connections, ex: PPTP */
+#define NF_S17_WAN_TYPE_PPPOEV6 3 /* IPv6 PPPoE connection using the same session as IPv4 connection */
+#define NF_S17_WAN_TYPE_PPPOES0 4 /* PPPoE connection but not yet connected */
+/* define the H/W Age mode for NAPT entries */
+#define ARP_AGE_NEVER 7
+#define ARP_AGE 6
+
+extern int nf_athrs17_hnat;
+extern int nf_athrs17_hnat_wan_type;
+extern int nf_athrs17_hnat_ppp_id;
+extern int nf_athrs17_hnat_udp_thresh;
+extern a_uint32_t nf_athrs17_hnat_wan_ip;
+extern a_uint32_t nf_athrs17_hnat_ppp_peer_ip;
+extern unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN];
+extern unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN];
+
+extern int nf_athrs17_hnat_ppp_id2;
+extern unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN];
+
+typedef struct
+{
+ a_uint32_t entry_id;
+ a_uint32_t flags;
+ a_uint32_t src_addr;
+ a_uint32_t trans_addr;
+ a_uint16_t port_num;
+ a_uint16_t port_range;
+} nat_entry_t;
+
+typedef struct
+{
+ a_uint32_t entry_id;
+ a_uint32_t flags;
+ a_uint32_t status;
+ a_uint32_t src_addr;
+ a_uint32_t dst_addr;
+ a_uint16_t src_port;
+ a_uint16_t dst_port;
+ a_uint32_t trans_addr;
+ a_uint16_t trans_port;
+} napt_entry_t;
+
+#if defined (__BIG_ENDIAN)
+typedef struct
+{
+ a_uint16_t ver:2;
+ a_uint16_t pri:3;
+ a_uint16_t type:5;
+ a_uint16_t rev:2;
+ a_uint16_t with_tag:1;
+ a_uint16_t sport:3;
+ a_uint16_t vid;
+ a_uint16_t magic;
+} aos_header_t;
+#elif defined (__LITTLE_ENDIAN)
+typedef struct
+{
+ a_uint16_t vid;
+ a_uint16_t sport:3;
+ a_uint16_t with_tag:1;
+ a_uint16_t rev:2;
+ a_uint16_t type:5;
+ a_uint16_t pri:3;
+ a_uint16_t ver:2;
+} aos_header_t;
+#else
+#error "no ENDIAN"
+#endif
+
+a_int32_t
+nat_hw_add(nat_entry_t *nat);
+a_int32_t
+nat_hw_del_by_index(a_uint32_t index);
+a_int32_t
+nat_hw_flush(void);
+a_int32_t
+napt_hw_flush(void);
+a_int32_t
+nat_hw_prv_base_can_update(void);
+void
+nat_hw_prv_base_update_enable(void);
+void
+nat_hw_prv_base_update_disable(void);
+a_int32_t
+nat_hw_prv_base_set(a_uint32_t ip);
+a_uint32_t
+nat_hw_prv_base_get(void);
+a_int32_t
+nat_hw_prv_mask_set(a_uint32_t ipmask);
+a_uint32_t
+nat_hw_prv_mask_get(void);
+a_int32_t
+nat_hw_prv_base_is_match(a_uint32_t ip);
+a_int32_t
+if_mac_add(uint8_t *mac, uint8_t vid, uint32_t ipv6);
+a_int32_t
+arp_hw_add(a_uint32_t port, a_uint32_t intf_id, a_uint8_t *ip, a_uint8_t *mac, int is_ipv6_entry);
+a_int32_t
+arp_if_info_get(void *data, a_uint32_t *sport, a_uint32_t *vid);
+a_int32_t
+nat_hw_pub_ip_add(a_uint32_t ip, a_uint32_t *index);
+void
+napt_hw_mode_init(void);
+a_int32_t
+nat_hw_pub_ip_del(a_uint32_t index);
+a_int32_t
+napt_hw_add(napt_entry_t *napt_entry);
+a_int32_t
+napt_hw_del(napt_entry_t *napt_entry);
+a_int32_t
+napt_hw_first_by_age(napt_entry_t *napt, a_uint32_t age);
+a_int32_t
+napt_hw_next_by_age(napt_entry_t *napt, a_uint32_t age);
+a_int32_t
+napt_hw_get_by_index(napt_entry_t *napt, a_uint16_t hw_index);
+a_uint32_t
+napt_hw_used_count_get(void);
+
+sw_error_t napt_l3_status_set(a_uint32_t dev_id, a_bool_t enable);
+sw_error_t napt_l3_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif /*_NAT_HELPER_HSL_H*/
+
diff --git a/app/nathelper/linux/napt_acl.c b/app/nathelper/linux/napt_acl.c
new file mode 100644
index 0000000..64c86fc
--- /dev/null
+++ b/app/nathelper/linux/napt_acl.c
@@ -0,0 +1,1507 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/if_arp.h>
+#include <linux/netdevice.h>
+
+#include "napt_acl.h"
+#include "lib/nat_helper_hsl.h"
+#include "hsl_shared_api.h"
+
+static uint32_t aclrulemask = 0;
+
+uint32_t
+get_aclrulemask(void)
+{
+ uint32_t ret;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ ret = aclrulemask;
+ local_irq_restore(flags);
+
+ return ret;
+}
+
+void
+set_aclrulemask(uint32_t acl_list)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ aclrulemask |= 1<<acl_list;
+ local_irq_restore(flags);
+
+ return;
+}
+
+void
+unset_aclrulemask(uint32_t acl_list)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+ aclrulemask &= ~(1<<acl_list);
+ local_irq_restore(flags);
+
+ return;
+}
+
+/*
+ * set the IPv4 default route (to the next hop)
+ */
+void
+droute_add_acl_rules(uint32_t local_ip, uint32_t gw_entry_id)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_DROUTE))
+ return;
+
+ aos_printk("Adding ACL rules %d - Default Route \n", S17_ACL_LIST_DROUTE);
+
+ printk("%s %d: 0x%08x\n", __FUNCTION__, __LINE__, ntohl(local_ip));
+
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.dest_ip4_val = ntohl(local_ip);
+ myacl.dest_ip4_mask = ntohl(0xffffff00);
+ /*
+ IPv4 rule, with DIP field
+ if DIP != Lan IP, force the ARP index redirect to the next hop
+ enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+ ARP_INDEX_EN, to the next hop ARP index, bind on LAN ports
+ */
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP4_DIP );
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_ARP_EN );
+
+ myacl.arp_ptr = gw_entry_id;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_DROUTE, S17_ACL_LIST_PRIO_HIGH);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n" );
+ aos_printk("already created!? \n");
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD (0, S17_ACL_LIST_DROUTE, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "ACL_RULE_ADD ERROR...\n" );
+ return ;
+ }
+
+ ACL_LIST_BIND (0, S17_ACL_LIST_DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND (0, S17_ACL_LIST_DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND (0, S17_ACL_LIST_DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND (0, S17_ACL_LIST_DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ /* check for the ACL enable bit */
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+
+ set_aclrulemask(S17_ACL_LIST_DROUTE);
+}
+
+/*
+ * set the IPv6 default route (to the next hop)
+ */
+void
+ipv6_droute_add_acl_rules(struct in6_addr *local_ip, uint32_t gw_entry_id)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_IPV6DROUTE))
+ return;
+
+ printk("Adding ACL rules %d - IPv6 Default Route \n", S17_ACL_LIST_IPV6DROUTE);
+
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+ myacl.rule_type = FAL_ACL_RULE_IP6;
+
+ myacl.dest_ip6_val.ul[0] = local_ip->s6_addr32[0]; /* FF02::1:FF00:0000/104 */
+ myacl.dest_ip6_val.ul[1] = local_ip->s6_addr32[1];
+ myacl.dest_ip6_val.ul[2] = local_ip->s6_addr32[2];
+ myacl.dest_ip6_val.ul[3] = local_ip->s6_addr32[3];
+ myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_ARP_EN );
+
+ myacl.arp_ptr = gw_entry_id;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPV6DROUTE, S17_ACL_LIST_PRIO_HIGH);
+ if ( rtnval != SW_OK )
+ {
+ printk("qcaswitch_acl_list_creat ERROR...\n" );
+ printk("already created!? \n");
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD (0, S17_ACL_LIST_IPV6DROUTE, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ printk ( "qcaswitch_acl_rule_add ERROR...\n" );
+ return ;
+ }
+
+
+ ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND (0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ /* check for the ACL enable bit */
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+
+ set_aclrulemask(S17_ACL_LIST_IPV6DROUTE);
+}
+
+/*
+ * Del Default Route ACL rules
+ */
+void ipv6_droute_del_acl_rules(void)
+{
+ printk("IPv6 default route del rule #%d\n", S17_ACL_LIST_IPV6DROUTE);
+
+ if (!(get_aclrulemask() & (1 << S17_ACL_LIST_IPV6DROUTE)))
+ return;
+
+ ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_UNBIND(0, S17_ACL_LIST_IPV6DROUTE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ ACL_RULE_DEL(0, S17_ACL_LIST_IPV6DROUTE, 0, 1);
+
+
+ ACL_LIST_DESTROY(0, S17_ACL_LIST_IPV6DROUTE);
+
+ unset_aclrulemask(S17_ACL_LIST_IPV6DROUTE);
+}
+
+#ifdef ISIS
+static int isis_pppoe_del_rule0(void)
+{
+ int rtnval;
+
+ rtnval = ACL_LIST_UNBIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+ if (rtnval != SW_OK)
+ aos_printk("unbind error... \n");
+
+ rtnval = ACL_RULE_DEL(0, S17_ACL_LIST_PPPOE, 0, 1);
+ if (rtnval != SW_OK)
+ aos_printk("delete error... \n");
+
+ rtnval = ACL_LIST_DESTROY(0, S17_ACL_LIST_PPPOE);
+ if (rtnval != SW_OK)
+ aos_printk("destroy error... \n");
+
+ return rtnval;
+}
+#endif
+
+/*
+ * PPPoE ACL rules
+ * Force ARP_INDEX_EN to the next hop for CPU port
+ * Force SNAT and ARP_INDEX_EN to the next hop for LAN ports
+ */
+void pppoe_add_acl_rules(uint32_t wan_ip, uint32_t local_ip, uint32_t gw_entry_id)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval, cnt;
+ a_bool_t val;
+
+ /* do the 1st, 2nd and 3rd rules */
+ for (cnt = 0; cnt < 3; cnt++)
+ {
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+ switch (cnt)
+ {
+ case 0:
+#ifdef ISIS
+ aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE);
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.src_ip4_val = wan_ip;
+ myacl.src_ip4_mask = 0xffffffff;
+ aos_printk("WAN IP: %.8x\n", wan_ip);
+ /*
+ IPv4 rule, with SIP field
+ IF SIP == WAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX
+ enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+ ARP_INDEX_EN, to the PPPoE peer ARP index,
+ Change the CVID to WAN_VID (2)
+ Bind to CPU port
+ */
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+
+ myacl.arp_ptr = gw_entry_id;
+ /* fixed with CVID = 2 */
+ myacl.ctag_vid = 2;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ aos_printk("PPPoE Session ID changed !? \n");
+ /* delete the old ACL list */
+ rtnval = isis_pppoe_del_rule0();
+ if (rtnval != SW_OK)
+ aos_printk("pppoe_del_rule0: %d \n", rtnval);
+
+ /* create the ACL list again */
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ break;
+ }
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_RULE_ADD ERROR...\n");
+ break;
+ }
+
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+#endif
+ break;
+
+ case 1:
+ aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+1);
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.dest_ip4_val = local_ip;
+ myacl.dest_ip4_mask = 0xffffff00;
+
+ /*
+ IPv4 rule, with DIP field
+ IF DIP != LAN IP, FORCE the ARP_INDEX_EN to the PPPoE ARP INDEX
+ AND FORCE L3 SNAT
+ ARP_INDEX_EN, to the PPPoE peer ARP index
+ Bind to LAN ports
+ */
+
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+ myacl.arp_ptr = gw_entry_id;
+ myacl.policy_fwd = FAL_ACL_POLICY_SNAT;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE+1, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ break;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE+1, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_RULE_ADD ERROR...\n");
+ break;
+ }
+ /* bind to LAN ports (1-4) */
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ break;
+
+ case 2:
+ /*
+ User defined filter ACL
+ filter out 0x8100000288641100 packets and set the CVID to
+ a predefined VID (100 in this case)
+ ARP_INDEX_EN, to the PPPoE peer ARP index
+ Bind to CPU port
+ */
+ aos_printk("PPPoE adding rule #%d\n", S17_ACL_LIST_PPPOE+2);
+ myacl.rule_type = FAL_ACL_RULE_UDF;
+ /* set the UDP ACL type as L2, with length 8, offset 12 */
+ ACL_PORT_UDF_PROFILE_SET(0, S17_CPU_PORT, FAL_ACL_UDF_TYPE_L2, 12, 8);
+ myacl.udf_len = 8;
+ myacl.udf_offset = 12;
+ myacl.udf_type = FAL_ACL_UDF_TYPE_L2;
+ memset(&myacl.udf_val, 0, sizeof(myacl.udf_val));
+ memset(&myacl.udf_mask, 0, sizeof(myacl.udf_mask));
+ /* UDF filter to check for 0x8100000288641100 packets */
+ myacl.udf_val[0] = 0x81;
+ myacl.udf_val[1] = 0x00;
+ myacl.udf_val[2] = 0x00;
+ myacl.udf_val[3] = 0x02;
+ myacl.udf_val[4] = 0x88;
+ myacl.udf_val[5] = 0x64;
+ myacl.udf_val[6] = 0x11;
+ myacl.udf_val[7] = 0x00;
+
+ myacl.udf_mask[0] = 0xff;
+ myacl.udf_mask[1] = 0xff;
+ myacl.udf_mask[2] = 0xff;
+ myacl.udf_mask[3] = 0xff;
+ myacl.udf_mask[4] = 0xff;
+ myacl.udf_mask[5] = 0xff;
+ myacl.udf_mask[6] = 0xff;
+ myacl.udf_mask[7] = 0xff;
+
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_UDF);
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+
+ myacl.arp_ptr = gw_entry_id;
+ /* fixed with CVID = 100 */
+ myacl.ctag_vid = 100;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_PPPOE + 2, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ break;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_PPPOE + 2, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_RULE_ADD ERROR...\n");
+ break;
+ }
+
+ ACL_LIST_BIND(0, S17_ACL_LIST_PPPOE + 2, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+ break;
+ }
+ }
+
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+/*
+ * When LAN & WAN IPs are too close, apply this ACL
+ * ex: WAN 192.168.1.x, LAN 192.168.0.x
+ */
+void
+ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval, cnt;
+ a_bool_t val;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_IPCONF)) return;
+
+ for (cnt = 0; cnt < 2; cnt++)
+ {
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+ aos_printk("IP conflict adding rule #%d\n", cnt);
+
+ switch (cnt)
+ {
+ case 0:
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.dest_ip4_val = lan_ip;
+ myacl.dest_ip4_mask = 0xffffff00;
+ myacl.src_ip4_val = lan_ip;
+ myacl.src_ip4_mask = 0xffffff00;
+
+ /*
+ IPv4 rule, with DIP & SIP field
+ for DIP and SIP = LAN IP, do the next step
+ */
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ break;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_RULE_ADD ERROR...\n");
+ break;
+ }
+
+ /* bind to LAN ports */
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ aclrulemask |= (1 << S17_ACL_LIST_IPCONF);
+ set_aclrulemask(S17_ACL_LIST_IPCONF);
+
+ break;
+
+ case 1:
+ aos_printk("ARP index entry_id: %d\n", gw_entry_id);
+
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.src_ip4_val = lan_ip;
+ myacl.src_ip4_mask = 0xffffff00;
+
+ /*
+ IPv4 rule, with SIP field
+ enable packet forwarding & forward only. i.e. no FORCE_L3_MODE
+ ARP_INDEX_EN, to the PPPoE peer ARP index
+ */
+
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+ myacl.arp_ptr = gw_entry_id;
+ myacl.policy_fwd = FAL_ACL_POLICY_SNAT;
+
+ /* rule no. 4 */
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_IPCONF+1, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_LIST_CREATE ERROR...\n");
+ break;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_IPCONF+1, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("ACL_RULE_ADD ERROR...\n");
+ break;
+ }
+ /* bind to LAN ports (1-4) */
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND(0, S17_ACL_LIST_IPCONF+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+/*
+solicted_node address
+ FF02::1:FF00:0000/104 => Solicited-Node Address
+*/
+void
+ipv6_snooping_solicted_node_add_acl_rules ( void )
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SOLICITED_NODE, __func__);
+ myacl.rule_type = FAL_ACL_RULE_IP6;
+ myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::1:FF00:0000/104 */
+ myacl.dest_ip6_val.ul[1] = 0x00000000;
+ myacl.dest_ip6_val.ul[2] = 0x00000001;
+ myacl.dest_ip6_val.ul[3] = 0xff000000;
+
+ myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ /* ACL action destination port, WAN, LAN and CPU ports */
+ myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+ /* ACL action destination port, LAN and CPU ports */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+ myacl.vid_val = 0x1;
+ myacl.vid_mask = 0xfff;
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+ return;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+ return;
+ }
+
+ // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SOLICITED_NODE, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3 );
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+
+/*
+Node Information Queries (RFC 4620 is experimental)
+ FF02:0:0:0:0:2:FF00::/104 => Node Information Queries
+*/
+void
+ipv6_snooping_nodeinfo_query_add_acl_rules ( void )
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_NODEINFO_QUERY, __func__);
+ myacl.rule_type = FAL_ACL_RULE_IP6;
+ myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:2:FF00::/104 */
+ myacl.dest_ip6_val.ul[1] = 0x00000000;
+ myacl.dest_ip6_val.ul[2] = 0x00000002;
+ myacl.dest_ip6_val.ul[3] = 0xff000000;
+
+ myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[3] = 0xff000000;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ /* ACL action destination port, WAN, LAN and CPU ports */
+ myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+ /* ACL action destination port, LAN and CPU ports */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+ myacl.vid_val = 0x1;
+ myacl.vid_mask = 0xfff;
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+ return;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+ return;
+ }
+
+ // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_NODEINFO_QUERY, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3 );
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+
+/*
+sextuple0_group_acl_rules contains following addresses:
+ FF02:0:0:0:0:0:0:1 => All Nodes Address
+ FF02:0:0:0:0:0:0:2 => All Routers Address
+ FF02:0:0:0:0:0:0:9 => RIP Routers
+ FF02:0:0:0:0:0:0:C => SSDP
+ FF02:0:0:0:0:0:0:16 => All MLDv2-capable routers
+ FF02:0:0:0:0:0:0:FB => mDNSv6
+*/
+void
+ipv6_snooping_sextuple0_group_add_acl_rules ( void )
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, __func__);
+ myacl.rule_type = FAL_ACL_RULE_IP6;
+ myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02::/120 */
+ myacl.dest_ip6_val.ul[1] = 0x00000000;
+ myacl.dest_ip6_val.ul[2] = 0x00000000;
+ myacl.dest_ip6_val.ul[3] = 0x00000000;
+
+ myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[3] = 0xffffff00;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ /* ACL action destination port, WAN, LAN and CPU ports */
+ myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+ /* ACL action destination port, LAN and CPU ports */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+ myacl.vid_val = 0x1;
+ myacl.vid_mask = 0xfff;
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+ return;
+ }
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+ return;
+ }
+
+ // ACL pattern source port
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3 );
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+
+/*
+quintruple0_1_group_acl_rules contains following addresses:
+ FF02:0:0:0:0:0:1:2 => All-dhcp-agents
+ FF02:0:0:0:0:0:1:3 => LLMNR
+*/
+void
+ipv6_snooping_quintruple0_1_group_add_acl_rules ( void )
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, __func__);
+ myacl.rule_type = FAL_ACL_RULE_IP6;
+ myacl.dest_ip6_val.ul[0] = 0xff020000; /* FF02:0:0:0:0:0:1::/125 */
+ myacl.dest_ip6_val.ul[1] = 0x00000000;
+ myacl.dest_ip6_val.ul[2] = 0x00000000;
+ myacl.dest_ip6_val.ul[3] = 0x00010000;
+
+ myacl.dest_ip6_mask.ul[0] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[1] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[2] = 0xffffffff;
+ myacl.dest_ip6_mask.ul[3] = 0xfffffff8;
+
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ myacl.ports = (1 << S17_WAN_PORT) | (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+#else
+ /* ACL action destination port, LAN and CPU ports */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+ myacl.vid_val = 0x1;
+ myacl.vid_mask = 0xfff;
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP6_DIP );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_VID );
+#endif
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __func__, rtnval );
+ return;
+ }
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "%s: ACL_RULE_ADD ERROR...(%d)\n", __func__, rtnval );
+ return;
+ }
+
+ /* ACL pattern soruce port */
+#ifdef CONFIG_ATH_8327_ACL_IPV6_PASSTHROUGH
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT );
+#endif
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3 );
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+/*
+When HW IGMPSNOOPING Enabled, we need to let UPnP SSDP Multicast packets send to lan
+*/
+void upnp_ssdp_add_acl_rules(void)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_UPNP_SSDP, __func__);
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.dest_ip4_val = 0xeffffffa; // 239.255.255.250
+ myacl.dest_ip4_mask = 0xffffffff;
+ /* ACL action destination port, LAN and CPU ports */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_IP4_DIP );
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, S17_ACL_LIST_UPNP_SSDP, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ if(rtnval == SW_ALREADY_EXIST)
+ {
+ aos_printk ( "upnp_ssdp_acl_rules: rules acl list already exists !\n");
+ }
+ else
+ {
+ aos_printk ( "upnp_ssdp_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+ }
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_UPNP_SSDP, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "upnp_ssdp_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval );
+ return ;
+ }
+
+ // Pattern source port
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2 );
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_UPNP_SSDP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3 );
+
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+}
+
+void filter_power_cord_acl_rules(void)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_PLC_FILTER, __func__);
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+ myacl.rule_type = FAL_ACL_RULE_MAC;
+
+ myacl.ethtype_val = 0x88e1;
+ myacl.ethtype_mask = 0xffff;
+
+ /* ACL action destination port PLC port */
+ myacl.ports = (1 << S17_CPU_PORT) | (1 << 6);
+
+ /* Set pattern type*/
+ memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE ); // set ethtype as pattern
+
+ /* Set action type*/
+ memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT); // set action as DENY, FAL_ACL_ACTION_DENY
+
+ /*
+ memcpy ( myacl.dest_mac_val.uc, mac, 6 );
+ memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+ */
+
+ rtnval = ACL_LIST_CREATE (0, S17_ACL_LIST_PLC_FILTER, S17_ACL_LIST_PRIO_HIGH);
+ if(rtnval != SW_OK)
+ {
+ aos_printk ( "filter_power_cord_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+ return;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, S17_ACL_LIST_PLC_FILTER, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "filter_power_cord_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+ return;
+ }
+
+ // ACL pattern source port
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_CPU_PORT);
+ ACL_LIST_BIND ( 0, S17_ACL_LIST_PLC_FILTER, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, 6);
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET ( 0, A_TRUE );
+ }
+ }
+}
+
+/* enable pppoe_passthrough by default */
+static int isis_pppoe_passthrough = 0;
+
+unsigned int isis_pppoe_passthrough_process(struct sk_buff *skb, aos_header_t *athr_header)
+{
+ unsigned char *smac = &skb->data[6];
+
+ if ( isis_pppoe_passthrough == 0 )
+ return -1;
+
+ if ( ( ( skb->data[20] == 0x88 && ( skb->data[21] == 0x63 ) ) || ( skb->data[16] == 0x88 && ( skb->data[17] == 0x63 ) ) )
+ && ( athr_header->sport != S17_WAN_PORT ) )
+ {
+ pppoe_passthrough_acl_rules ( 0, smac );
+ }
+
+ return 0;
+}
+
+unsigned int isis_set_pppoe_passthrough ( int enable )
+{
+ if ( enable )
+ isis_pppoe_passthrough = 1;
+ else
+ isis_pppoe_passthrough = 0;
+
+ printk ( "## isis_set_pppoe_passthrough %s !\n", enable != 0 ? "enabled" : "disabled" );
+
+ return 0;
+}
+
+unsigned int isis_enable_pppoe_discovery_acl(void)
+{
+#if 0
+ printk ( "## isis_enable_pppoe_discovery_acl !\n");
+
+ athrs17_reg_write ( MOD_ENABLE_OFFSET, athrs17_reg_read ( MOD_ENABLE_OFFSET ) | ( 1 << MOD_ENABLE_ACL_EN_BOFFSET ) );
+ printk ( "athrs17_reg_write(MOD_ENABLE_OFFSET) = 0x%08x\n", athrs17_reg_read ( MOD_ENABLE_OFFSET ) );
+#endif
+ return 0;
+}
+
+
+int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac)
+{
+ fal_acl_rule_t myacl;
+ uint32_t rtnval;
+ a_bool_t val;
+ uint32_t rule_list_id;
+ unsigned char mac_mask[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+ if (isis_pppoe_passthrough > MAX_PPPOE_PASSTHROUGH_NUM)
+ {
+ aos_printk("Support %d PPPoE passthrough hosts only... \n", MAX_PPPOE_PASSTHROUGH_NUM);
+ return -1;
+ }
+
+ {
+ /* lan -> wan, pppoe discovery */
+ rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2;
+ printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+ myacl.rule_type = FAL_ACL_RULE_MAC;
+ memcpy ( myacl.src_mac_val.uc, mac, 6 );
+ memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 );
+ myacl.ethtype_val = 0x8863;
+ myacl.ethtype_mask = 0xffff;
+
+ myacl.ports = (1 << S17_WAN_PORT);
+
+ memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_SA );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+ memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE (0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+ return -1;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+ return -1;
+ }
+
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+ }
+
+ {
+ /* lan -> wan, pppoe session */
+ rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN + (isis_pppoe_passthrough - 1) * 2 + 1;
+
+ printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+ myacl.rule_type = FAL_ACL_RULE_MAC;
+ memcpy ( myacl.src_mac_val.uc, mac, 6 );
+ memcpy ( myacl.src_mac_mask.uc, mac_mask, 6 );
+
+ myacl.ethtype_val = 0x8864;
+ myacl.ethtype_mask = 0xffff;
+
+ myacl.ports = ( 1<<S17_WAN_PORT /* WAN */ );
+
+ memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_SA );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+ memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR...(%d)\n",rtnval );
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+ }
+
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+ }
+
+ {
+ /* lan <- wan, pppoe discovery */
+ rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN + (isis_pppoe_passthrough - 1) * 2;
+
+ printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+ myacl.rule_type = FAL_ACL_RULE_MAC;
+ memcpy ( myacl.dest_mac_val.uc, mac, 6 );
+ memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+
+ myacl.ethtype_val = 0x8863;
+ myacl.ethtype_mask = 0xffff;
+
+ myacl.ports = (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+ memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE (0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR (%d)\n",rtnval );
+ return -1;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+ return -1;
+ }
+
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+ }
+
+ {
+ /* lan <- wan, pppoe session */
+ rule_list_id = S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN + (isis_pppoe_passthrough - 1) * 2 + 1;
+
+ printk ( "creating ACL list_id: %d \n", rule_list_id );
+
+ memset ( &myacl, 0, sizeof ( fal_acl_rule_t ) );
+ myacl.rule_type = FAL_ACL_RULE_MAC;
+ memcpy ( myacl.dest_mac_val.uc, mac, 6 );
+ memcpy ( myacl.dest_mac_mask.uc, mac_mask, 6 );
+
+ myacl.ethtype_val = 0x8864;
+ myacl.ethtype_mask = 0xffff;
+
+ myacl.ports = (1 << S17_LAN_PORT0) |
+ (1 << S17_LAN_PORT1) | (1 << S17_LAN_PORT2) | (1 << S17_LAN_PORT3);
+
+ memset ( &myacl.field_flg, 0, sizeof ( myacl.field_flg ) );
+
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_DA );
+ FAL_FIELD_FLG_SET ( myacl.field_flg, FAL_ACL_FIELD_MAC_ETHTYPE );
+
+ memset ( &myacl.action_flg, 0, sizeof ( myacl.action_flg ) );
+
+ FAL_ACTION_FLG_SET ( myacl.action_flg, FAL_ACL_ACTION_REDPT );
+
+ rtnval = ACL_LIST_CREATE ( 0, rule_list_id, S17_ACL_LIST_PRIO_MID);
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_LIST_CREATE ERROR...(%d)\n",rtnval );
+ return -1;
+ }
+
+ rtnval = ACL_RULE_ADD ( 0, rule_list_id, 0, 1, &myacl );
+
+ if ( rtnval != SW_OK )
+ {
+ aos_printk ( "pppoe_passthrough_acl_rules: ACL_RULE_ADD ERROR...(%d)\n", rtnval );
+ return -1;
+ }
+
+ ACL_LIST_BIND ( 0, rule_list_id, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+ }
+
+ if ( ACL_STATUS_GET ( 0, &val ) == SW_OK )
+ {
+ if ( val != A_TRUE )
+ {
+ aos_printk ( "ACL is not yet enabled. Enabling... \n" );
+ ACL_STATUS_SET ( 0, A_TRUE );
+ }
+ }
+
+ /* add the counter */
+ isis_pppoe_passthrough++;
+
+ return 0;
+}
+
+void icmp_from_wan_acl_rule(void)
+{
+ fal_acl_rule_t myacl;
+ a_uint32_t rtnval;
+
+ printk("WAN ICMP ACL Rules\n");
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ myacl.ip_proto_val = 0x1; /* ICMP */
+ myacl.ip_proto_mask = 0xff;
+
+ /* dest port : CPU Port */
+ myacl.ports = 1 << S17_CPU_PORT;
+
+ FAL_FIELD_FLG_SET (myacl.field_flg, FAL_ACL_FIELD_IP_PROTO);
+ FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_ICMP_FROM_WAN, S17_ACL_LIST_PRIO_HIGH);
+
+ if (rtnval != SW_OK)
+ {
+ if(rtnval == SW_ALREADY_EXIST)
+ {
+ aos_printk ( "athrs17_icmp_from_wan_acl_rules: rules acl list already exists !\n");
+ }
+ else
+ {
+ aos_printk ( "athrs17_icmp_from_wan_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+ }
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_ICMP_FROM_WAN, 0, 1, &myacl);
+
+ if (rtnval != SW_OK)
+ {
+ ACL_LIST_DESTROY(0, S17_ACL_ICMP_FROM_WAN);
+ aos_printk("athrs17_icmp_from_wan_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval);
+ return ;
+ }
+
+ /* source port : WAN Port */
+ ACL_LIST_BIND(0, S17_ACL_ICMP_FROM_WAN, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+}
+
+/*
+Once
+1. Both lan and wan interface entry have been created
+2. Lan size PC's host entry has been created
+3. Wan has receive the packet destination IP belong to PC on Lan
+Force to redirect it to CPU
+*/
+void redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules(uint32_t lan_ip, uint32_t lan_netmask)
+{
+ fal_acl_rule_t myacl;
+ a_uint32_t rtnval;
+ a_bool_t val;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN)) return;
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, __func__);
+
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+ //myacl.ip_proto_val = 0x1; /* ICMP */
+ //myacl.ip_proto_mask = 0xff;
+ printk("redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules, Lan: %u.%u.%u.%u / %u.%u.%u.%u\n"
+ ,((unsigned char *)&lan_ip)[0] ,((unsigned char *)&lan_ip)[1]
+ ,((unsigned char *)&lan_ip)[2] ,((unsigned char *)&lan_ip)[3]
+ ,((unsigned char *)&lan_netmask)[0] ,((unsigned char *)&lan_netmask)[1]
+ ,((unsigned char *)&lan_netmask)[2] ,((unsigned char *)&lan_netmask)[3]
+ );
+
+ myacl.dest_ip4_val = lan_ip;
+ myacl.dest_ip4_mask = lan_netmask;
+
+ /* dest port : CPU Port */
+ myacl.ports = 1 << S17_CPU_PORT;
+
+ //FAL_FIELD_FLG_SET (myacl.field_flg, FAL_ACL_FIELD_IP_PROTO);
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+ FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_RDTCPU);
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, S17_ACL_LIST_PRIO_HIGH);
+
+ if (rtnval != SW_OK)
+ {
+ if(rtnval == SW_ALREADY_EXIST)
+ {
+ aos_printk ( "redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: rules acl list already exists !\n");
+ }
+ else
+ {
+ aos_printk ( "redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: ACL_LIST_CREATE ERROR (%d)...\n",rtnval );
+ }
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, 0, 1, &myacl);
+
+ if (rtnval != SW_OK)
+ {
+ ACL_LIST_DESTROY(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN);
+ aos_printk("redirect_internal_ip_packets_to_cpu_on_wan_add_acl_rules: ACL_RULE_ADD ERROR...(%d)\n" ,rtnval);
+ return ;
+ }
+
+ /* source port : WAN Port */
+ ACL_LIST_BIND(0, S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+
+ /* check for the ACL enable bit */
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+ set_aclrulemask(S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN);
+}
+
+void udp_checksum_zero_acl_rule(uint32_t gw_entry_id)
+{
+ fal_acl_rule_t myacl;
+ a_uint32_t rtnval;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_UDP0)) return;
+
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+
+ /*
+ User defined filter ACL
+ filter out UDP(0x11) checksum (0x0000) packets
+ and set FORCE_L3_MODE ARP_INDEX_OVER_EN=1 ARP_INDEX=default route
+ Bind to WAN/LAN port
+ */
+ aos_printk("UDP checksum adding rule #%d\n", S17_ACL_LIST_UDP0);
+ myacl.rule_type = FAL_ACL_RULE_UDF;
+ /* set the UDP ACL type as L3, with length 1, offset 9 */
+ /* set the UDP ACL type as L4, with length 2, offset 6 */
+
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT0, FAL_ACL_UDF_TYPE_L3, 9, 1);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT0, FAL_ACL_UDF_TYPE_L4, 6, 2);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT1, FAL_ACL_UDF_TYPE_L3, 9, 1);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT1, FAL_ACL_UDF_TYPE_L4, 6, 2);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT2, FAL_ACL_UDF_TYPE_L3, 9, 1);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT2, FAL_ACL_UDF_TYPE_L4, 6, 2);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT3, FAL_ACL_UDF_TYPE_L3, 9, 1);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_LAN_PORT3, FAL_ACL_UDF_TYPE_L4, 6, 2);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_WAN_PORT, FAL_ACL_UDF_TYPE_L3, 9, 1);
+ ACL_PORT_UDF_PROFILE_SET(0, S17_WAN_PORT, FAL_ACL_UDF_TYPE_L4, 6, 2);
+
+ myacl.udf_len = 3;
+ myacl.udf_offset = 0;
+ myacl.udf_type = FAL_ACL_UDF_TYPE_L2;
+ memset(&myacl.udf_val, 0, sizeof(myacl.udf_val));
+ memset(&myacl.udf_mask, 0, sizeof(myacl.udf_mask));
+ /* UDF filter to check for UDP checksum 0 packets */
+ myacl.udf_val[0] = 0x11;
+ myacl.udf_val[1] = 0x00;
+ myacl.udf_val[2] = 0x00;
+ myacl.udf_val[3] = 0x00;
+ myacl.udf_val[4] = 0x00;
+ myacl.udf_val[5] = 0x00;
+ myacl.udf_val[6] = 0x00;
+ myacl.udf_val[7] = 0x00;
+
+ myacl.udf_mask[0] = 0xff;
+ myacl.udf_mask[1] = 0xff;
+ myacl.udf_mask[2] = 0xff;
+ myacl.udf_mask[3] = 0x00;
+ myacl.udf_mask[4] = 0x00;
+ myacl.udf_mask[5] = 0x00;
+ myacl.udf_mask[6] = 0x00;
+ myacl.udf_mask[7] = 0x00;
+
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_UDF);
+ FAL_ACTION_FLG_SET(myacl.action_flg, FAL_ACL_ACTION_ARP_EN);
+
+ myacl.arp_ptr = gw_entry_id;
+ myacl.policy_fwd = FAL_ACL_POLICY_ROUTE;
+
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_UDP0, S17_ACL_LIST_PRIO_HIGH);
+ if (rtnval != SW_OK)
+ {
+ aos_printk("#%d, ACL_LIST_CREATE ERROR...%d\n",S17_ACL_LIST_UDP0,rtnval);
+ return;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_UDP0, 0, 1, &myacl);
+ if (rtnval != SW_OK)
+ {
+ ACL_LIST_DESTROY(0, S17_ACL_LIST_UDP0);
+ aos_printk("#%d, ACL_RULE_ADD ERROR...%d\n",S17_ACL_LIST_UDP0,rtnval);
+ return;
+ }
+
+ ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+ ACL_LIST_BIND(0, S17_ACL_LIST_UDP0, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_WAN_PORT);
+
+ set_aclrulemask(S17_ACL_LIST_UDP0);
+}
+
+
+void dscp_remap_acl_rule(uint32_t ori_dscp, uint32_t dscp)
+{
+ fal_acl_rule_t myacl;
+ a_uint32_t rtnval;
+ uint32_t ori_tos, tos_val;
+ a_bool_t val;
+
+ ori_tos = ori_dscp << 2;
+ tos_val = dscp << 2;
+
+ if (get_aclrulemask() & (1 << S17_ACL_LIST_DSCP_REMAP))
+ return;
+
+ aos_printk("Adding ACL rules %d - %s\n", S17_ACL_LIST_DSCP_REMAP, __func__);
+ memset(&myacl, 0, sizeof(fal_acl_rule_t));
+ myacl.rule_type = FAL_ACL_RULE_IP4;
+
+ aos_printk("Remap DSCP value from %d to %d\n", ori_dscp, dscp);
+ myacl.ip_dscp_val = ori_tos;
+ myacl.ip_dscp_mask = 0xff;
+
+ FAL_FIELD_FLG_SET(myacl.field_flg, FAL_ACL_FIELD_IP_DSCP);
+ FAL_ACTION_FLG_SET (myacl.action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+
+ /* Action : new DSCP value */
+ myacl.dscp = tos_val;
+
+ rtnval = ACL_LIST_CREATE(0, S17_ACL_LIST_DSCP_REMAP, S17_ACL_LIST_PRIO_HIGH);
+
+ if (rtnval != SW_OK)
+ {
+ if(rtnval == SW_ALREADY_EXIST)
+ {
+ aos_printk ( "%s: rules acl list already exists !\n", __FUNCTION__);
+ }
+ else
+ {
+ aos_printk ( "%s: ACL_LIST_CREATE ERROR (%d)...\n", __FUNCTION__, rtnval );
+ }
+ return ;
+ }
+
+ rtnval = ACL_RULE_ADD(0, S17_ACL_LIST_DSCP_REMAP, 0, 1, &myacl);
+
+ if (rtnval != SW_OK)
+ {
+ ACL_LIST_DESTROY(0, S17_ACL_LIST_DSCP_REMAP);
+ aos_printk("%s: ACL_RULE_ADD ERROR...(%d)\n", __FUNCTION__, rtnval);
+ return ;
+ }
+
+ /* source port : LAN Ports */
+ ACL_LIST_BIND(0, S17_ACL_LIST_DSCP_REMAP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT0);
+ ACL_LIST_BIND(0, S17_ACL_LIST_DSCP_REMAP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT1);
+ ACL_LIST_BIND(0, S17_ACL_LIST_DSCP_REMAP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT2);
+ ACL_LIST_BIND(0, S17_ACL_LIST_DSCP_REMAP, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, S17_LAN_PORT3);
+
+ /* check for the ACL enable bit */
+ if (ACL_STATUS_GET(0, &val) == SW_OK)
+ {
+ if (val != A_TRUE)
+ {
+ aos_printk("ACL is not yet enabled. Enabling... \n");
+ ACL_STATUS_SET(0, A_TRUE);
+ }
+ }
+ set_aclrulemask(S17_ACL_LIST_DSCP_REMAP);
+}
+
diff --git a/app/nathelper/linux/napt_acl.h b/app/nathelper/linux/napt_acl.h
new file mode 100644
index 0000000..ef644ca
--- /dev/null
+++ b/app/nathelper/linux/napt_acl.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "hsl.h"
+
+#ifdef ISISC
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#else
+#include "isis_acl.h"
+#include "isis_reg.h"
+#endif
+
+#define MAX_PPPOE_PASSTHROUGH_NUM 4
+/* ACL list priority */
+#define S17_ACL_LIST_PRIO_HIGH 0
+#define S17_ACL_LIST_PRIO_MID 1
+#define S17_ACL_LIST_PRIO_LOW 2
+#define S17_ACL_LIST_PRIO_LOWEST 3
+
+#define S17_ACL_LIST_IPCONF 0
+#define S17_ACL_LIST_UDP0 1
+#define S17_ACL_LIST_DROUTE 2
+#define S17_ACL_LIST_PPPOE 3
+#define S17_ACL_LIST_IPV6MLD 5
+#define S17_ACL_LIST_IPV6_SOLICITED_NODE 7
+#define S17_ACL_LIST_IPV6_NODEINFO_QUERY 9
+#define S17_ACL_LIST_IPV6_SEXTUPLE0_GROUP 11
+#define S17_ACL_LIST_IPV6_QUINTRUPLE0_1_GROUP 13
+#define S17_ACL_LIST_UPNP_SSDP 15
+#define S17_ACL_LIST_PPPOE_PASSTHROUGH_LAN_TO_WAN 17
+#define S17_ACL_LIST_PPPOE_PASSTHROUGH_WAN_TO_LAN 19
+#define S17_ACL_LIST_PLC_FILTER 22
+#define S17_ACL_LIST_REDIRECT_INTERNAL_IP_TO_CPU_ON_WAN 26
+#define S17_ACL_ICMP_FROM_WAN 27
+#define S17_ACL_LIST_IPV6DROUTE 28
+#define S17_ACL_LIST_DSCP_REMAP 29
+
+
+/* port # of WAN, 1 for DB120 demo board */
+#define S17_WAN_PORT 5
+#define S17_CPU_PORT 0
+
+#define S17_LAN_PORT0 1
+#define S17_LAN_PORT1 2
+#define S17_LAN_PORT2 3
+#define S17_LAN_PORT3 4
+
+extern void athrs17_reg_write(unsigned int reg_addr, unsigned int reg_val);
+extern unsigned int athrs17_reg_read(unsigned int reg_addr);
+
+uint32_t get_aclrulemask(void);
+void set_aclrulemask(uint32_t acl_list);
+
+void droute_add_acl_rules(uint32_t local_ip, uint32_t gw_entry_id);
+void ipv6_droute_del_acl_rules(void);
+void ipv6_droute_add_acl_rules(struct in6_addr *local_ip, uint32_t gw_entry_id);
+void pppoe_add_acl_rules(uint32_t wan_ip, uint32_t local_ip, uint32_t gw_entry_id);
+void ip_conflict_add_acl_rules(uint32_t wan_ip, uint32_t lan_ip, uint32_t gw_entry_id);
+void ipv6_snooping_solicted_node_add_acl_rules(void);
+void ipv6_snooping_nodeinfo_query_add_acl_rules(void);
+void ipv6_snooping_sextuple0_group_add_acl_rules(void);
+void ipv6_snooping_quintruple0_1_group_add_acl_rules ( void );
+void upnp_ssdp_add_acl_rules(void);
+unsigned int isis_set_pppoe_passthrough(int enable);
+unsigned int isis_enable_pppoe_discovery_acl(void);
+int pppoe_passthrough_acl_rules(uint32_t gw_entry_id, unsigned char *mac);
diff --git a/app/nathelper/linux/napt_helper.c b/app/nathelper/linux/napt_helper.c
new file mode 100644
index 0000000..eff3fdd
--- /dev/null
+++ b/app/nathelper/linux/napt_helper.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/kthread.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+#ifdef KVER32
+#include <linux/rcupdate.h>
+#endif
+#include <net/netfilter/nf_conntrack_acct.h>
+#include <net/netfilter/nf_conntrack.h>
+#include "nat_helper.h"
+#include "napt_acl.h"
+
+#include "lib/nat_helper_hsl.h"
+
+extern struct net init_net;
+static struct task_struct *ct_task;
+
+/*#undef HNAT_PRINTK
+#define HNAT_PRINTK(x...) aos_printk(x)*/
+
+#ifdef KVER32
+extern void __rcu_read_lock(void);
+extern void __rcu_read_unlock(void);
+extern unsigned int nf_conntrack_htable_size;
+#endif
+
+void
+napt_ct_aging_disable(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+
+ if (timer_pending(&ct->timeout))
+ {
+ del_timer(&ct->timeout);
+ }
+}
+
+int
+napt_ct_aging_is_enable(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return 0;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+
+ return timer_pending(&(((struct nf_conn *)ct)->timeout));
+}
+
+void
+napt_ct_aging_enable(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return;
+ }
+
+ if(napt_ct_aging_is_enable(ct_addr))
+ {
+ return;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+ uint16_t l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
+ uint8_t protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
+
+ ct->timeout.expires = jiffies+10*HZ;
+
+ if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
+ {
+ if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
+ {
+ ct->timeout.expires = jiffies+(5*24*60*60*HZ);
+ }
+ }
+
+ ct->in_hnat = 0; /* once timmer is enabled, contrack not in HNAT anymore. */
+
+ HNAT_PRINTK("<aging> ct:[%x] add timeout again\n", ct_addr);
+ add_timer(&ct->timeout);
+}
+
+void
+napt_ct_to_hw_entry(uint32_t ct_addr, napt_entry_t *napt)
+{
+ if(!ct_addr)
+ {
+ return;
+ }
+
+#define NAPT_AGE 0xe
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+ struct nf_conntrack_tuple *org_tuple, *rep_tuple;
+
+ if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat
+ {
+ org_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+ rep_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
+
+ }
+ else //dnat
+ {
+ org_tuple = &(ct->tuplehash[IP_CT_DIR_REPLY].tuple);
+ rep_tuple = &(ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple);
+ }
+
+ uint8_t protonum = org_tuple->dst.protonum;
+
+ if(org_tuple->src.l3num == AF_INET)
+ {
+ if(protonum == IPPROTO_TCP)
+ {
+ napt->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
+
+ }
+ else if(protonum == IPPROTO_UDP)
+ {
+ napt->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
+
+ }
+ }
+
+ napt->src_addr = ntohl(org_tuple->src.u3.ip);
+ napt->src_port = ntohs(org_tuple->src.u.all);
+ napt->dst_addr = ntohl(org_tuple->dst.u3.ip);
+ napt->dst_port = ntohs(org_tuple->dst.u.all);
+ napt->trans_addr = ntohl(rep_tuple->dst.u3.ip);
+ napt->trans_port = ntohs(rep_tuple->dst.u.all);
+ napt->status = NAPT_AGE;
+
+ return;
+}
+
+uint64_t
+napt_ct_pkts_get(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return 0;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+ struct nf_conn_counter *cct = nf_conn_acct_find(ct);
+
+ if(cct)
+ {
+ return (cct[IP_CT_DIR_ORIGINAL].packets +
+ cct[IP_CT_DIR_REPLY].packets);
+ }
+ else
+ {
+ return 0;
+ }
+}
+
+int
+napt_ct_type_is_nat(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return 0;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+
+ return ((IPS_NAT_MASK & (ct)->status)?1:0);
+}
+
+int
+napt_ct_status_is_estab(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return 0;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+ uint16_t l3num = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num;
+ uint8_t protonum = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.dst.protonum;
+
+ if ((l3num == AF_INET) && (protonum == IPPROTO_TCP))
+ {
+ if (ct->proto.tcp.state == TCP_CONNTRACK_ESTABLISHED)
+ {
+ return 1;
+ }
+ }
+ else if ((l3num == AF_INET) && (protonum == IPPROTO_UDP))
+ {
+ return 1;
+ }
+
+ return 0;
+}
+
+uint32_t
+napt_ct_priv_ip_get(uint32_t ct_addr)
+{
+ if(!ct_addr)
+ {
+ return 0;
+ }
+
+ struct nf_conn *ct = (struct nf_conn *)ct_addr;
+ uint32_t usaddr;
+
+ if ((ct->status & IPS_NAT_MASK) == IPS_SRC_NAT) //snat
+ {
+ usaddr = ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.u3.ip;
+ }
+ else
+ {
+ usaddr = ct->tuplehash[IP_CT_DIR_REPLY].tuple.src.u3.ip;
+ }
+
+ usaddr = ntohl(usaddr);
+
+ return usaddr;
+}
+
+void
+napt_ct_list_lock(void)
+{
+ rcu_read_lock();
+}
+
+void
+napt_ct_list_unlock(void)
+{
+ rcu_read_unlock();
+}
+
+uint32_t
+napt_ct_list_iterate(uint32_t *hash, uint32_t *iterate)
+{
+ struct net *net = &init_net;
+ struct nf_conntrack_tuple_hash *h = NULL;
+ struct nf_conn *ct = NULL;
+ struct hlist_nulls_node *pos = (struct hlist_nulls_node *) (*iterate);
+
+ while(*hash < nf_conntrack_htable_size)
+ {
+ if(pos == 0)
+ {
+ /*get head for list*/
+ pos = rcu_dereference((&net->ct.hash[*hash])->first);
+ }
+
+ hlist_nulls_for_each_entry_from(h, pos, hnnode)
+ {
+ (*iterate) = (uint32_t)(pos->next);
+ ct = nf_ct_tuplehash_to_ctrack(h);
+ return (uint32_t) ct;
+ }
+
+ ++(*hash);
+ pos = 0;
+ }
+
+ return 0;
+}
+
+int
+napt_ct_task_should_stop(void)
+{
+ return kthread_should_stop();
+}
+
+void
+napt_ct_task_start(int (*task)(void*), const char *task_name)
+{
+ ct_task = kthread_create(task, NULL, task_name);
+
+ if(IS_ERR(ct_task))
+ {
+ aos_printk("thread: %s create fail\n", task_name);
+ return;
+ }
+
+ wake_up_process(ct_task);
+
+ HNAT_PRINTK("thread: %s create success pid:%d\n",
+ task_name, ct_task->pid);
+}
+
+void
+napt_ct_task_stop(void)
+{
+ if(ct_task)
+ {
+ kthread_stop(ct_task);
+ }
+}
+
+void
+napt_ct_task_sleep(int secs)
+{
+ msleep_interruptible(secs*1000);
+}
diff --git a/app/nathelper/linux/napt_helper.h b/app/nathelper/linux/napt_helper.h
new file mode 100644
index 0000000..bbe05fb
--- /dev/null
+++ b/app/nathelper/linux/napt_helper.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _NAPT_HELPER_H
+#define _NAPT_HELPER_H
+
+
+
+#define USING_LINUX2631 1
+
+#ifdef USING_LINUX2631
+
+void
+napt_ct_task_start(int (*task)(void*), const char *task_name);
+void
+napt_ct_task_stop(void);
+int
+napt_ct_task_should_stop(void);
+void
+napt_ct_task_sleep(int secs);
+void
+napt_ct_list_lock(void);
+void
+napt_ct_list_unlock(void);
+uint32_t
+napt_ct_list_iterate(uint32_t *hash, uint32_t *pos) ;
+void
+napt_ct_to_hw_entry(uint32_t ct_addr, void *napt);
+void
+napt_ct_aging_enable(uint32_t ct_addr);
+void
+napt_ct_aging_disable(uint32_t ct_addr);
+int
+napt_ct_aging_is_enable(uint32_t ct_addr);
+uint64_t
+napt_ct_pkts_get(uint32_t ct_addr);
+int
+napt_ct_type_is_nat(uint32_t ct_addr);
+int
+napt_ct_status_is_estab(uint32_t ct_addr);
+uint32_t
+napt_ct_priv_ip_get(uint32_t ct_addr);
+
+
+
+#define NAPT_CT_TASK_START napt_ct_task_start
+#define NAPT_CT_TASK_STOP napt_ct_task_stop
+#define NAPT_CT_TASK_SHOULD_STOP napt_ct_task_should_stop
+#define NAPT_CT_TASK_SLEEP napt_ct_task_sleep
+
+#define NAPT_CT_LIST_LOCK napt_ct_list_lock
+#define NAPT_CT_LIST_UNLOCK napt_ct_list_unlock
+#define NAPT_CT_LIST_ITERATE napt_ct_list_iterate
+
+#define NAPT_CT_AGING_IS_ENABLE napt_ct_aging_is_enable
+#define NAPT_CT_AGING_ENABLE napt_ct_aging_enable
+#define NAPT_CT_AGING_DISABLE napt_ct_aging_disable
+
+#define NAPT_CT_TYPE_IS_NAT napt_ct_type_is_nat
+#define NAPT_CT_STATUS_IS_ESTAB napt_ct_status_is_estab
+#define NAPT_CT_PRIV_IP_GET napt_ct_priv_ip_get
+#define NAPT_CT_PKTS_GET napt_ct_pkts_get
+#define NAPT_CT_TO_HW_ENTRY napt_ct_to_hw_entry
+
+
+#else
+
+
+
+#endif
+
+//#define HNAT_DEBUG 1
+
+#ifdef HNAT_DEBUG
+#define HNAT_PRINTK(x...) aos_printk(x)
+#else
+#define HNAT_PRINTK(x...)
+#endif
+
+#endif
diff --git a/app/nathelper/linux/napt_procfs.c b/app/nathelper/linux/napt_procfs.c
new file mode 100644
index 0000000..4d97f98
--- /dev/null
+++ b/app/nathelper/linux/napt_procfs.c
@@ -0,0 +1,375 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * napt_procfs.c - create files in /proc
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/proc_fs.h>
+#include <linux/if_ether.h>
+#include <asm/uaccess.h> /* for copy_from_user */
+#include "aos_types.h"
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#define NF_PROCFS_PERM 0444
+#else
+#define NF_PROCFS_PERM 0644
+#endif
+
+#define ATHRS17_MAC_LEN 13 // 12+1
+#define ATHRS17_IP_LEN 9 // 8+1
+#define ATHRS17_CHAR_MAX_LEN ATHRS17_MAC_LEN
+
+#define NF_PROCFS_DIR "qca_switch"
+
+#define NF_ATHRS17_HNAT_NAME "nf_athrs17_hnat"
+#define NF_ATHRS17_HNAT_WAN_TYPE_NAME "nf_athrs17_hnat_wan_type"
+#define NF_ATHRS17_HNAT_PPP_ID_NAME "nf_athrs17_hnat_ppp_id"
+#define NF_ATHRS17_HNAT_UDP_THRESH_NAME "nf_athrs17_hnat_udp_thresh"
+#define NF_ATHRS17_HNAT_WAN_IP_NAME "nf_athrs17_hnat_wan_ip"
+#define NF_ATHRS17_HNAT_PPP_PEER_IP_NAME "nf_athrs17_hnat_ppp_peer_ip"
+#define NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME "nf_athrs17_hnat_ppp_peer_mac"
+#define NF_ATHRS17_HNAT_WAN_MAC_NAME "nf_athrs17_hnat_wan_mac"
+
+#define NF_ATHRS17_HNAT_PPP_ID2_NAME "nf_athrs17_hnat_ppp_id2"
+#define NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME "nf_athrs17_hnat_ppp_peer_mac2"
+
+/* for PPPoE */
+int nf_athrs17_hnat = 0;
+int nf_athrs17_hnat_wan_type = 0;
+int nf_athrs17_hnat_ppp_id = 0;
+int nf_athrs17_hnat_udp_thresh = 0;
+a_uint32_t nf_athrs17_hnat_wan_ip = 0;
+a_uint32_t nf_athrs17_hnat_ppp_peer_ip = 0;
+unsigned char nf_athrs17_hnat_ppp_peer_mac[ETH_ALEN] = {0};
+unsigned char nf_athrs17_hnat_wan_mac[ETH_ALEN] = {0};
+
+/* for IPv6 over PPPoE (only for S17c)*/
+int nf_athrs17_hnat_ppp_id2 = 0;
+unsigned char nf_athrs17_hnat_ppp_peer_mac2[ETH_ALEN] = {0};
+
+/**
+ * This structure hold information about the /proc file
+ *
+ */
+static struct proc_dir_entry *qca_switch_dir;
+
+static struct proc_dir_entry *nf_athrs17_hnat_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_type_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_id_file;
+static struct proc_dir_entry *nf_athrs17_hnat_udp_thresh_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_ip_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_ip_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac_file;
+static struct proc_dir_entry *nf_athrs17_hnat_wan_mac_file;
+
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_id2_file;
+static struct proc_dir_entry *nf_athrs17_hnat_ppp_peer_mac2_file;
+
+/**
+ * This function is called then the /proc file is read
+ *
+ */
+static int procfile_read_int(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ int ret;
+ int *prv_data = (int *)data;
+
+ // printk("[read] prv_data 0x%p -> 0x%08x\n", prv_data, *prv_data);
+ ret = sprintf(page, "%d\n", *prv_data);
+
+ return ret;
+}
+
+static int procfile_read_ip(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ int ret;
+ unsigned char *prv_data = (unsigned char *)data;
+
+ ret = sprintf(page, "%d.%d.%d.%d\n", prv_data[0], prv_data[1], prv_data[2], prv_data[3]);
+
+ return ret;
+}
+
+static int procfile_read_mac(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+ int ret;
+ unsigned char *prv_data = (unsigned char *)data;
+ unsigned long long *ptr_ull;
+
+ ret = sprintf(page, "%.2x-%.2x-%.2x-%.2x-%.2x-%.2x\n", prv_data[0], prv_data[1], prv_data[2], prv_data[3], prv_data[4], prv_data[5]);
+
+ ptr_ull = (unsigned long long *)prv_data;
+
+ return ret;
+}
+
+/**
+ * This function is called with the /proc file is written
+ *
+ */
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#define procfile_write_int NULL
+#define procfile_write_ip NULL
+#define procfile_write_mac NULL
+#else
+static int procfile_write_int(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+ int len;
+ uint8_t tmp_buf[9] = {'0', '0', '0', '0', '0', '0', '0', '0', '0'};
+ unsigned int *prv_data = (unsigned int *)data;
+
+ if(count > sizeof(tmp_buf))
+ len = sizeof(tmp_buf);
+ else
+ len = count;
+
+ if(copy_from_user(tmp_buf, buffer, len))
+ return -EFAULT;
+
+ *prv_data = simple_strtol((const char *)tmp_buf, NULL, 10);
+
+ // printk("[write] prv_data 0x%p -> 0x%08x\n", prv_data, *prv_data);
+
+ return len;
+}
+
+static int procfile_write_ip(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+ int ret;
+ int len;
+ unsigned char tmp_buf[ATHRS17_IP_LEN];
+ unsigned long *prv_data = (unsigned long *)data;
+
+ if(count > ATHRS17_IP_LEN)
+ len = ATHRS17_IP_LEN;
+ else
+ len = count;
+
+ if(copy_from_user(tmp_buf, buffer, len))
+ return -EFAULT;
+
+ tmp_buf[len-1] = '\0';
+
+ *prv_data = simple_strtoul((const char *)tmp_buf, NULL, 16);
+
+ return ret;
+}
+
+static int procfile_write_mac(struct file *file, const char *buffer, unsigned long count, void *data)
+{
+ int ret;
+ int len;
+ unsigned char tmp_buf[ATHRS17_MAC_LEN];
+ unsigned char *ptr_char;
+ unsigned long long *prv_data = (unsigned long long *)data;
+
+ if(count > ATHRS17_MAC_LEN)
+ len = ATHRS17_MAC_LEN;
+ else
+ len = count;
+
+ if(copy_from_user((void *)tmp_buf, buffer, len))
+ return -EFAULT;
+
+ tmp_buf[len-1] = 't';
+
+ *prv_data = simple_strtoull((const char *)tmp_buf, NULL, 16);
+ *prv_data = cpu_to_be64p(prv_data);
+ ptr_char = (unsigned char *)prv_data;
+ ptr_char[0] = ptr_char[2];
+ ptr_char[1] = ptr_char[3];
+ ptr_char[2] = ptr_char[4];
+ ptr_char[3] = ptr_char[5];
+ ptr_char[4] = ptr_char[6];
+ ptr_char[5] = ptr_char[7];
+
+ return ret;
+}
+#endif // ifdef AUTO_UPDATE_PPPOE_INFO
+
+static void setup_proc_entry(void)
+{
+ nf_athrs17_hnat = 1;
+ nf_athrs17_hnat_wan_type = 0;
+ nf_athrs17_hnat_ppp_id = 0;
+ memset(&nf_athrs17_hnat_ppp_peer_mac, 0, ETH_ALEN);
+ memset(&nf_athrs17_hnat_wan_mac, 0, ETH_ALEN);
+ nf_athrs17_hnat_ppp_peer_ip = 0;
+ nf_athrs17_hnat_wan_ip = 0;
+
+ nf_athrs17_hnat_ppp_id2 = 0;
+ memset(&nf_athrs17_hnat_ppp_peer_mac2, 0, ETH_ALEN);
+}
+
+int napt_procfs_init(void)
+{
+ int ret = 0;
+
+ setup_proc_entry();
+
+ /* create directory */
+ qca_switch_dir = proc_mkdir(NF_PROCFS_DIR, NULL);
+ if(qca_switch_dir == NULL)
+ {
+ ret = -ENOMEM;
+ goto err_out;
+ }
+
+ /* create the /proc file */
+ nf_athrs17_hnat_file = create_proc_entry(NF_ATHRS17_HNAT_NAME, 0644, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+ goto no_athrs17_hnat;
+ }
+ nf_athrs17_hnat_file->data = &nf_athrs17_hnat;
+ nf_athrs17_hnat_file->read_proc = procfile_read_int;
+ nf_athrs17_hnat_file->write_proc = procfile_write_int;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+
+ nf_athrs17_hnat_wan_type_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_wan_type_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME);
+ goto no_athrs17_hnat_wan_type;
+ }
+ nf_athrs17_hnat_wan_type_file->data = &nf_athrs17_hnat_wan_type;
+ nf_athrs17_hnat_wan_type_file->read_proc = procfile_read_int;
+ nf_athrs17_hnat_wan_type_file->write_proc = procfile_write_int;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_TYPE_NAME);
+
+ nf_athrs17_hnat_ppp_id_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_ppp_id_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME);
+ goto no_athrs17_hnat_ppp_id;
+ }
+ nf_athrs17_hnat_ppp_id_file->data = &nf_athrs17_hnat_ppp_id;
+ nf_athrs17_hnat_ppp_id_file->read_proc = procfile_read_int;
+ nf_athrs17_hnat_ppp_id_file->write_proc = procfile_write_int;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID_NAME);
+
+ nf_athrs17_hnat_udp_thresh_file = create_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_udp_thresh_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME);
+ goto no_athrs17_hnat_udp_thresh;
+ }
+ nf_athrs17_hnat_udp_thresh_file->data = &nf_athrs17_hnat_udp_thresh;
+ nf_athrs17_hnat_udp_thresh_file->read_proc = procfile_read_int;
+ nf_athrs17_hnat_udp_thresh_file->write_proc = procfile_write_int;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_UDP_THRESH_NAME);
+
+ nf_athrs17_hnat_wan_ip_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_wan_ip_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME);
+ goto no_athrs17_hnat_wan_ip;
+ }
+ nf_athrs17_hnat_wan_ip_file->data = &nf_athrs17_hnat_wan_ip;
+ nf_athrs17_hnat_wan_ip_file->read_proc = procfile_read_ip;
+ nf_athrs17_hnat_wan_ip_file->write_proc = procfile_write_ip;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_IP_NAME);
+
+ nf_athrs17_hnat_ppp_peer_ip_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_ppp_peer_ip_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME);
+ goto no_athrs17_hnat_ppp_peer_ip;
+ }
+ nf_athrs17_hnat_ppp_peer_ip_file->data = &nf_athrs17_hnat_ppp_peer_ip;
+ nf_athrs17_hnat_ppp_peer_ip_file->read_proc = procfile_read_ip;
+ nf_athrs17_hnat_ppp_peer_ip_file->write_proc = procfile_write_ip;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_IP_NAME);
+
+ nf_athrs17_hnat_ppp_peer_mac_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_ppp_peer_mac_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+ goto no_athrs17_hnat_ppp_peer_mac;
+ }
+ nf_athrs17_hnat_ppp_peer_mac_file->data = &nf_athrs17_hnat_ppp_peer_mac;
+ nf_athrs17_hnat_ppp_peer_mac_file->read_proc = procfile_read_mac;
+ nf_athrs17_hnat_ppp_peer_mac_file->write_proc = procfile_write_mac;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+
+ nf_athrs17_hnat_wan_mac_file = create_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_wan_mac_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME);
+ goto no_athrs17_hnat_wan_mac;
+ }
+ nf_athrs17_hnat_wan_mac_file->data = &nf_athrs17_hnat_wan_mac;
+ nf_athrs17_hnat_wan_mac_file->read_proc = procfile_read_mac;
+ nf_athrs17_hnat_wan_mac_file->write_proc = procfile_write_mac;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_WAN_MAC_NAME);
+
+ nf_athrs17_hnat_ppp_id2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_ID2_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_ppp_id2_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME);
+ goto no_athrs17_hnat_ppp_id;
+ }
+ nf_athrs17_hnat_ppp_id2_file->data = &nf_athrs17_hnat_ppp_id2;
+ nf_athrs17_hnat_ppp_id2_file->read_proc = procfile_read_int;
+ nf_athrs17_hnat_ppp_id2_file->write_proc = procfile_write_int;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_ID2_NAME);
+
+ nf_athrs17_hnat_ppp_peer_mac2_file = create_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME, NF_PROCFS_PERM, qca_switch_dir);
+ if (NULL == nf_athrs17_hnat_ppp_peer_mac2_file)
+ {
+ printk("Error: Can not create /proc/%s/%s\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC2_NAME);
+ goto no_athrs17_hnat_ppp_peer_mac;
+ }
+ nf_athrs17_hnat_ppp_peer_mac2_file->data = &nf_athrs17_hnat_ppp_peer_mac2;
+ nf_athrs17_hnat_ppp_peer_mac2_file->read_proc = procfile_read_mac;
+ nf_athrs17_hnat_ppp_peer_mac2_file->write_proc = procfile_write_mac;
+ printk("/proc/%s/%s is created\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME);
+
+ return 0;
+
+no_athrs17_hnat_wan_mac:
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_peer_mac:
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_peer_ip:
+ remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir);
+no_athrs17_hnat_wan_ip:
+ remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir);
+no_athrs17_hnat_udp_thresh:
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir);
+no_athrs17_hnat_ppp_id:
+ remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir);
+no_athrs17_hnat_wan_type:
+ remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir);
+no_athrs17_hnat:
+ remove_proc_entry(NF_PROCFS_DIR, NULL);
+err_out:
+ return ret;
+}
+
+void napt_procfs_exit(void)
+{
+ remove_proc_entry(NF_ATHRS17_HNAT_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_WAN_TYPE_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_ID_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_UDP_THRESH_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_WAN_IP_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_IP_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_PPP_PEER_MAC_NAME, qca_switch_dir);
+ remove_proc_entry(NF_ATHRS17_HNAT_WAN_MAC_NAME, qca_switch_dir);
+ remove_proc_entry(NF_PROCFS_DIR, NULL);
+ printk(KERN_INFO "/proc/%s/%s removed\n", NF_PROCFS_DIR, NF_ATHRS17_HNAT_NAME);
+}
+
+
diff --git a/app/nathelper/linux/nat_helper.c b/app/nathelper/linux/nat_helper.c
new file mode 100644
index 0000000..30866dd
--- /dev/null
+++ b/app/nathelper/linux/nat_helper.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "nat_helper.h"
+
+sw_error_t
+nat_helper_init(uint32_t dev_id)
+{
+ host_helper_init();
+ napt_helper_init();
+ // nat_ipt_helper_init();
+
+ aos_printk("Hello, nat helper module for 1.1!\n");
+
+ return SW_OK;
+}
+
+sw_error_t
+nat_helper_cleanup(uint32_t dev_id)
+{
+ host_helper_exit();
+ napt_helper_exit();
+ // nat_ipt_helper_exit();
+
+ aos_printk("Goodbye, nat helper module!\n");
+
+ return SW_OK;
+}
+
diff --git a/app/nathelper/linux/nat_helper.h b/app/nathelper/linux/nat_helper.h
new file mode 100644
index 0000000..46e114f
--- /dev/null
+++ b/app/nathelper/linux/nat_helper.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _NAT_HELPER_H
+#define _NAT_HELPER_H
+
+#include "sw.h"
+
+#define NAPT_TABLE_SIZE 1024
+
+void host_helper_init(void);
+void host_helper_exit(void);
+void napt_helper_init(void);
+void napt_helper_exit(void);
+void nat_ipt_helper_init(void);
+void nat_ipt_helper_exit(void);
+
+//#define HNAT_DEBUG 1
+
+#ifdef HNAT_DEBUG
+#define HNAT_PRINTK(x...) aos_printk(x)
+#else
+#define HNAT_PRINTK(x...)
+#endif
+
+//#define HNAT_ERR_DEBUG 1
+
+#ifdef HNAT_ERR_DEBUG
+#define HNAT_ERR_PRINTK(x...) aos_printk(x)
+#else
+#define HNAT_ERR_PRINTK(x...)
+#endif
+
+
+
+#endif
diff --git a/app/nathelper/linux/nat_ipt_helper.c b/app/nathelper/linux/nat_ipt_helper.c
new file mode 100644
index 0000000..e472c87
--- /dev/null
+++ b/app/nathelper/linux/nat_ipt_helper.c
@@ -0,0 +1,690 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#include <linux/netfilter_ipv4/ip_tables.h>
+#include <linux/netfilter_ipv4/ipt_multiport.h>
+#include <net/netfilter/nf_nat.h>
+#include "nat_helper.h"
+
+#include "lib/nat_helper_hsl.h"
+#include "lib/nat_helper_dt.h"
+
+
+#define IPT_BUFFER_INIT_LEN 1000
+#define NF_NAT_INIT_ENTRIES_NUM 4 //nf_nat_rule.c
+
+static int
+nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len);
+static int
+nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len);
+
+/*those initial value will be overwrited by orignal iptables sockopts*/
+static struct nf_sockopt_ops orgi_ipt_sockopts =
+{
+ /*pls check linux/in.h*/
+#define IPT_TEMP_BASE_CTL 60
+#define IPT_TEMP_SET_MAX (IPT_TEMP_BASE_CTL+1)
+#define IPT_TEMP_GET_MAX (IPT_TEMP_BASE_CTL+2)
+ .pf = PF_INET,
+ .set_optmin = IPT_TEMP_BASE_CTL,
+ .set_optmax = IPT_TEMP_SET_MAX,
+ .set = nat_ipt_set_ctl,
+ .get_optmin = IPT_TEMP_BASE_CTL,
+ .get_optmax = IPT_TEMP_GET_MAX,
+ .get = nat_ipt_get_ctl
+};
+
+static struct nf_sockopt_ops *ipt_sockopts = NULL;
+static uint32_t snat_seq = 0;
+static uint32_t hw_nat_ipt_seq[NAT_HW_NUM] = {0};
+static uint32_t hw_nat_pip_idx[NAT_HW_NUM] = {0};
+static uint8_t *gbuffer, *sbuffer;
+static unsigned int glen, slen;
+static struct ipt_replace old_replace;
+
+static void
+nat_ipt_del(struct ipt_replace ireplace)
+{
+ int i, j;
+ struct ipt_entry *gentry = NULL;
+ struct ipt_entry *sentry = NULL;
+ struct xt_entry_target *gtarget = NULL;
+ struct xt_entry_target *starget = NULL;
+ struct nf_nat_multi_range_compat *grange = NULL;
+ struct nf_nat_multi_range_compat *srange = NULL;
+ uint8_t *gptr, *sptr;
+ gptr = gbuffer;
+ sptr = sbuffer;
+ unsigned int oldnum = ireplace.num_counters;
+ unsigned int seq = 1;
+
+ HNAT_PRINTK("into nat_ipt_del\n");
+ for (i = oldnum; i >= NF_NAT_INIT_ENTRIES_NUM; i--)
+ {
+ gentry = (struct ipt_entry *)gptr;
+ sentry = (struct ipt_entry *)sptr;
+ gtarget = (struct xt_entry_target *)((uint8_t *) gentry + gentry->target_offset);
+ starget = (struct xt_entry_target *)((uint8_t *) sentry + sentry->target_offset);
+ grange = (struct nf_nat_multi_range_compat *)((uint8_t *) gtarget + sizeof (*gtarget));
+ srange = (struct nf_nat_multi_range_compat *)((uint8_t *) starget + sizeof (*starget));
+
+ HNAT_PRINTK("(0)isis_nat_del name %s:%s#####(%x:%x %x)###\n",
+ gtarget->u.user.name, starget->u.user.name,
+ gentry->ip.src.s_addr, gentry->ip.dst.s_addr,
+ grange->range[0].min.all);
+
+ if (strcmp(gtarget->u.user.name, starget->u.user.name))
+ {
+ /*if (!strcmp(gtarget->u.user.name, "DNAT")) {
+ if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
+ || grange->range[0].min.all)
+ return;
+ goto delete;
+ } else */
+ if (!strcmp(gtarget->u.user.name, "SNAT"))
+ {
+ if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
+ || grange->range[0].min.all)
+ return;
+ goto delete;
+ }
+ return;
+ } /*else if (!strcmp(gtarget->u.user.name, "DNAT")) {
+ if (memcmp(gentry, sentry, gentry->next_offset)) {
+ if (gentry->ip.src.s_addr || !gentry->ip.dst.s_addr
+ || grange->range[0].min.all)
+ return;
+ goto delete;
+ }
+ } */else if (!strcmp(gtarget->u.user.name, "SNAT"))
+ {
+ if (memcmp(gentry, sentry, gentry->next_offset))
+ {
+ if (!gentry->ip.src.s_addr || gentry->ip.dst.s_addr
+ || grange->range[0].min.all)
+ return;
+ goto delete;
+ }
+ }
+ gptr += gentry->next_offset;
+ sptr += gentry->next_offset;
+ if(!strcmp(gtarget->u.user.name, "SNAT"))
+ {
+ seq++;
+ }
+ }
+ HNAT_PRINTK("NONE to delete\n");
+ return;
+
+delete:
+ HNAT_PRINTK("READY to delete one\n");
+ for (j = 0; j < NAT_HW_NUM; j++)
+ {
+ HNAT_PRINTK("ready [%d] (hw)%x:(sw)%x######\n",
+ j, hw_nat_ipt_seq[j], seq);
+ if (hw_nat_ipt_seq[j] == seq)
+ {
+ if(nat_hw_del_by_index(j) != 0)
+ {
+ return;
+ }
+ //public_ip_del(hw_nat_pip_idx[j]);
+ }
+ }
+
+ for(i = 0; i < NAT_HW_NUM; i++)
+ {
+ if(hw_nat_ipt_seq[i] > seq)
+ {
+ hw_nat_ipt_seq[i]--;
+ }
+ else if(hw_nat_ipt_seq[i] == seq)
+ {
+ hw_nat_ipt_seq[i]=0;
+ }
+ }
+
+ return;
+}
+
+static void
+nat_ipt_to_hw_entry(struct ipt_entry *e,
+ nat_entry_t *nat)
+{
+#define P_ANY 0
+#define P_TCP 6
+#define P_UDP 17
+
+ struct ipt_entry_target *t = ipt_get_target(e);
+
+ const struct nf_nat_multi_range_compat *mr =
+ (struct nf_nat_multi_range_compat *)t->data;
+ const struct nf_nat_range *range = &mr->range[0];
+
+ uint32_t sip = e->ip.src.s_addr;
+ uint32_t pip = range->min_ip;
+ uint16_t proto = e->ip.proto;
+
+ memset((void *) nat, 0, sizeof (nat_entry_t));
+
+ nat->src_addr = sip;
+ nat->trans_addr = pip;
+
+ if (proto == P_TCP)
+ {
+ nat->flags = FAL_NAT_ENTRY_PROTOCOL_TCP;
+ }
+ else if (proto == P_UDP)
+ {
+ nat->flags = FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (proto == P_ANY)
+ {
+ nat->flags = FAL_NAT_ENTRY_PROTOCOL_ANY;
+ }
+}
+
+static int
+nat_ipt_hw_add(nat_entry_t *nat)
+{
+ if(nat_hw_add(nat) != 0)
+ {
+ return -1;
+ }
+
+ hw_nat_ipt_seq[nat->entry_id] = snat_seq;
+ HNAT_PRINTK("###nat_ipt_hw_add hw_nat_ipt_seq[%d]:%d###\n",
+ nat->entry_id, snat_seq);
+
+ hw_nat_pip_idx[nat->entry_id] = nat->trans_addr;
+
+ if(nat_hw_prv_base_can_update())
+ {
+ nat_hw_prv_base_set(nat->src_addr);
+ nat_hw_prv_base_update_disable();
+ }
+
+ uint32_t index;
+ if(nat_hw_pub_ip_add(nat->trans_addr, &index)!= 0)
+ {
+ return -1;
+ }
+
+ return 0;
+}
+
+static int
+nat_ipt_hw_port_range_add(nat_entry_t *nat,
+ uint16_t port_start, uint16_t port_end,
+ struct xt_multiport *xport)
+{
+ unsigned int i;
+
+ nat->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+
+ if(xport)
+ {
+ //some discontinuous ports
+ for (i = 0; i < xport->count; i++)
+ {
+
+ nat->port_num = xport->ports[i];
+ nat->port_range = 1;
+
+ if(nat_ipt_hw_add(nat))
+ {
+ HNAT_PRINTK("isis_nat_add(xport:%d) fail!\n", nat->port_num);
+ return -1;
+ }
+
+ HNAT_PRINTK("(1)isis_nat_add(xport:%d) success\n", nat->port_num);
+ }
+ }
+ else
+ {
+ //one port or port range
+ uint16_t port_min, port_max;
+
+ for (i = port_start; i <= port_end; i+= NAT_HW_PORT_RANGE_MAX)
+ {
+ port_min = i;
+ if((port_end-port_min)>(NAT_HW_PORT_RANGE_MAX-1))
+ {
+ port_max = port_min+(NAT_HW_PORT_RANGE_MAX-1);
+ }
+ else
+ {
+ port_max = port_end;
+ }
+
+ nat->port_num = port_min;
+ nat->port_range = (port_max - port_min + 1);
+
+ if(nat_ipt_hw_add(nat))
+ {
+ HNAT_PRINTK("isis_nat_add(range port:%d~%d) fail!\n",
+ port_min, port_max);
+ return -1;
+ }
+
+ HNAT_PRINTK("(2)isis_nat_add(range port:%d~%d) success\n", port_min, port_max);
+ }
+ }
+
+ return 0;
+}
+
+static int
+nat_ipt_check_none_matches(struct ipt_entry *e)
+{
+ nat_entry_t nat = {0};
+
+ nat_ipt_to_hw_entry(e, &nat);
+
+ if(nat_ipt_hw_add(&nat) != 0)
+ {
+ HNAT_PRINTK("(1)isis_nat_add(none port)fail!\n");
+ return -1;
+ }
+
+ HNAT_PRINTK("(1)isis_nat_add(none port) success\n");
+
+ return 0;
+}
+static int
+nat_ipt_check_matches(struct ipt_entry_match *m,
+ struct ipt_entry *e,
+ unsigned int *j)
+{
+ int ret = 0;
+
+ nat_entry_t nat = {0};
+ uint16_t port_start = 0, port_end = 0;
+ struct xt_multiport *xport = NULL;
+
+ if(strcmp(m->u.user.name, "udp") == 0)
+ {
+ struct xt_udp *udpinfo = (struct xt_udp *)m->data;
+ port_start = udpinfo->spts[0];
+ port_end = udpinfo->spts[1];
+
+ }
+ else if(strcmp(m->u.user.name, "tcp") == 0)
+ {
+ struct xt_tcp *tcpinfo = (struct xt_tcp *)m->data;
+ port_start = tcpinfo->spts[0];
+ port_end = tcpinfo->spts[1];
+
+ }
+ else if(strcmp(m->u.user.name, "multiport") == 0)
+ {
+ struct xt_multiport xport_data = {0};
+ xport = &xport_data;
+
+ struct ipt_entry_target *t = ipt_get_target(e);
+
+ if(t->u.user.revision == 0)
+ {
+ xport = (struct xt_multiport *)m->data;
+
+ }
+ else if(t->u.user.revision == 1)
+ {
+ const struct xt_multiport_v1 *xportv1 =
+ (struct xt_multiport_v1 *)m->data;
+ memcpy(xport->ports, xportv1->ports, sizeof(xportv1->ports));
+ xport->count = xportv1->count;
+ }
+
+ if(xport->flags != XT_MULTIPORT_SOURCE)
+ {
+ memset(xport->ports, 0, sizeof(xport->ports));
+ }
+
+ }
+ else
+ {
+ (*j)++ ;
+ HNAT_PRINTK("###no support matches m->u.user.name:%s\n",
+ m->u.user.name);
+ return -1;
+ }
+
+ nat_ipt_to_hw_entry(e, &nat);
+ ret = nat_ipt_hw_port_range_add(&nat, port_start, port_end, xport);
+
+ (*j)++ ;
+
+ return ret;
+}
+
+//check netmask !=32
+#define NAT_IPT_RULE_IS_FOR_NAPT(e) (((e)->ip.smsk.s_addr) != 0xffffffff)
+#define NAT_IPT_RULE_IS_NONE_MATCHES(e) (((e)->target_offset) == \
+ (sizeof(struct ipt_entry)))
+
+static int
+nat_ipt_find_check_entry(struct ipt_entry *e, unsigned int underflow,
+ unsigned int *i)
+{
+ int ret = 0;
+ static uint16_t next_offset = 0;
+
+ if(*i == 0)
+ {
+ snat_seq = 0;
+ next_offset = e->next_offset;
+ }
+ else
+ {
+ next_offset += e->next_offset;
+ }
+
+ struct ipt_entry_target *t = ipt_get_target(e);
+
+ if (!strcmp(t->u.user.name, "SNAT"))
+ {
+ ++snat_seq;
+
+ if(NAT_IPT_RULE_IS_FOR_NAPT(e))
+ {
+ HNAT_PRINTK("this ipt rule only for HW napt offload\n");
+
+ }
+ else
+ {
+ /*for basic nat offload*/
+ HNAT_PRINTK("[%d]next_offset:%d underflow:%d\n",
+ *i, next_offset, underflow);
+
+ if(next_offset == underflow) //new one
+ {
+
+ if(NAT_IPT_RULE_IS_NONE_MATCHES(e))
+ {
+ /*none matches*/
+ ret = nat_ipt_check_none_matches(e);
+
+ }
+ else
+ {
+ unsigned int j = 0;
+ /*iterate matches*/
+ ret = IPT_MATCH_ITERATE(e, nat_ipt_check_matches, e, &j);
+ }
+ }
+ }
+ }
+
+ (*i)++ ;
+
+ return ret;
+}
+
+static void
+nat_ipt_data_cleanup(void)
+{
+ if (gbuffer)
+ kfree(gbuffer);
+
+ gbuffer = NULL;
+
+ if (sbuffer)
+ kfree(sbuffer);
+
+ sbuffer = NULL;
+}
+
+static void
+nat_ipt_data_init(void)
+{
+ /*alloc initial set buffer*/
+ sbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
+
+ if(sbuffer)
+ {
+ memset(sbuffer, 0, IPT_BUFFER_INIT_LEN);
+ slen = IPT_BUFFER_INIT_LEN;
+ }
+ else
+ {
+ HNAT_PRINTK("%s sbuffer memory allocate fail\n", __func__);
+ }
+
+ /*alloc initial get buffer*/
+ gbuffer = kmalloc(IPT_BUFFER_INIT_LEN, GFP_ATOMIC);
+
+ if(gbuffer)
+ {
+ memset(gbuffer, 0, IPT_BUFFER_INIT_LEN);
+ glen = IPT_BUFFER_INIT_LEN;
+ }
+ else
+ {
+ HNAT_PRINTK("%s gbuffer memory allocate fail\n", __func__);
+ }
+
+
+ /*set initial underflow: nf_nat_rule.c*/
+ memset(&old_replace, 0, sizeof (old_replace));
+
+ old_replace.underflow[NF_INET_PRE_ROUTING] =
+ 0;
+ old_replace.underflow[NF_INET_POST_ROUTING] =
+ sizeof(struct ipt_standard);
+ old_replace.underflow[NF_INET_LOCAL_OUT] =
+ sizeof(struct ipt_standard) * 2;
+
+ /*record ipt rule(SNAT) sequence for hw nat*/
+ memset(hw_nat_ipt_seq, 0, NAT_HW_NUM);
+
+ /*record ipt rule(SNAT) pubip index for hw nat*/
+ memset(hw_nat_pip_idx, 0, NAT_HW_NUM);
+}
+
+static void
+nat_ipt_flush(void)
+{
+ napt_hw_flush();
+
+ nat_hw_flush();
+
+ nat_ipt_data_cleanup();
+ nat_ipt_data_init();
+
+ HNAT_PRINTK("------(nat flush done)------\n");
+}
+
+static void
+nat_ipt_add(struct ipt_replace ireplace)
+{
+ unsigned int i = 0;
+
+ IPT_ENTRY_ITERATE(sbuffer,
+ ireplace.size,
+ nat_ipt_find_check_entry,
+ ireplace.underflow[NF_INET_POST_ROUTING],
+ &i);
+}
+
+static int
+nat_ipt_hook_type_check(struct ipt_replace ireplace)
+{
+ int ret = -1;
+
+ HNAT_PRINTK("------we only support SNAT------\n");
+
+ if (old_replace.underflow[NF_INET_PRE_ROUTING] !=
+ ireplace.underflow[NF_INET_PRE_ROUTING])
+ {
+ HNAT_PRINTK("------this is PREROUTING(DNAT):no!------\n");
+
+ }
+ else if(old_replace.underflow[NF_INET_POST_ROUTING] !=
+ ireplace.underflow[NF_INET_POST_ROUTING])
+ {
+ HNAT_PRINTK("------this is POSTROUTING(SNAT):yes!------\n");
+ ret = 0;
+
+ }
+ else if(old_replace.underflow[NF_INET_LOCAL_OUT] !=
+ ireplace.underflow[NF_INET_LOCAL_OUT])
+ {
+ HNAT_PRINTK("------this is OUTPUT:no!------\n");
+
+ }
+ else
+ {
+ HNAT_PRINTK("------this is UNKNOW:no!------\n");
+
+ }
+
+ return ret;
+}
+
+static void
+nat_ipt_rules_cp_from_user(void **buf, unsigned int *buf_len,
+ void __user *user, unsigned int user_len)
+{
+ if((*buf == 0) || (user == 0))
+ {
+ return;
+ }
+
+ if (*buf_len < user_len)
+ {
+ if(*buf)
+ {
+ kfree(*buf);
+ *buf = kmalloc(user_len, GFP_ATOMIC);
+ *buf_len = user_len;
+ }
+ }
+ HNAT_PRINTK("(2)nat_ipt_rules_cp_from_user *buf:%x user:%x user_len:%d\n",
+ (unsigned int)*buf, (unsigned int)user, user_len);
+ copy_from_user(*buf, user, user_len);
+
+ return;
+}
+
+static int
+nat_ipt_set_ctl(struct sock *sk, int cmd, void __user * user, unsigned int len)
+{
+ struct ipt_replace ireplace;
+
+ HNAT_PRINTK("NAT set hook\n");
+
+ if (cmd != IPT_SO_SET_REPLACE)
+ goto normal;
+
+ copy_from_user(&ireplace, user, sizeof (ireplace));
+
+ if (strcmp(ireplace.name, "nat")
+ || (ireplace.num_entries == ireplace.num_counters))
+ {
+ HNAT_PRINTK("none NAT or no new entry %d", ireplace.num_entries);
+ goto normal;
+ }
+
+ if (ireplace.num_entries == NF_NAT_INIT_ENTRIES_NUM)
+ {
+ nat_ipt_flush();
+ goto normal;
+ }
+
+ if (nat_ipt_hook_type_check(ireplace) != 0)
+ {
+ goto normal;
+ }
+
+ nat_ipt_rules_cp_from_user((void **)&sbuffer, &slen,
+ (user + sizeof (ireplace)),
+ ireplace.size);
+
+ if (ireplace.num_entries > ireplace.num_counters)
+ {
+ nat_ipt_add(ireplace);
+ }
+ else
+ {
+ nat_ipt_del(ireplace);
+ }
+
+normal:
+ /*save old_replace for next hook type check*/
+ old_replace = ireplace;
+
+ return orgi_ipt_sockopts.set(sk, cmd, user, len);
+}
+
+static int
+nat_ipt_get_ctl(struct sock *sk, int cmd, void __user * user, int *len)
+{
+ int k = orgi_ipt_sockopts.get(sk, cmd, user, len);
+
+ if (cmd == IPT_SO_GET_ENTRIES)
+ {
+
+ struct ipt_get_entries entries;
+
+ copy_from_user(&entries, user, sizeof (entries));
+ HNAT_PRINTK("IPT_SO_GET_ENTRIES: %s %d\n", entries.name, entries.size);
+
+ nat_ipt_rules_cp_from_user((void **)&gbuffer, &glen,
+ (user + sizeof (struct ipt_get_entries)),
+ (*len - sizeof (entries)));
+ }
+ return k;
+}
+
+static void
+nat_ipt_sockopts_replace(void)
+{
+ /*register an temp sockopts to find ipt_sockopts*/
+ nf_register_sockopt(&orgi_ipt_sockopts);
+ list_for_each_entry(ipt_sockopts, orgi_ipt_sockopts.list.next, list)
+ {
+ if (ipt_sockopts->set_optmin == IPT_BASE_CTL)
+ {
+ break;
+ }
+ }
+ nf_unregister_sockopt(&orgi_ipt_sockopts);
+
+ /*save orginal ipt_sockopts*/
+ orgi_ipt_sockopts = *ipt_sockopts;
+
+ /*replace ipt_sockopts with our opts*/
+ ipt_sockopts->set = nat_ipt_set_ctl;
+ ipt_sockopts->get = nat_ipt_get_ctl;
+}
+
+static void
+nat_ipt_sockopts_restore(void)
+{
+ ipt_sockopts->set = orgi_ipt_sockopts.set;
+ ipt_sockopts->get = orgi_ipt_sockopts.get;
+}
+
+void
+nat_ipt_helper_init(void)
+{
+ nat_ipt_sockopts_replace();
+ nat_ipt_data_init();
+}
+
+void
+nat_ipt_helper_exit(void)
+{
+ nat_ipt_sockopts_restore();
+ nat_ipt_data_cleanup();
+}
+
diff --git a/config b/config
new file mode 100644
index 0000000..3d89aa1
--- /dev/null
+++ b/config
@@ -0,0 +1,110 @@
+CPU=mips
+
+OS=linux
+
+ifndef OS_VER
+OS_VER=2_6
+endif
+# OS subversion, 2.6.31 for WASP (db120)
+#OS_SUB=31
+# GCC version, 3 or 4
+#GCC_VER=4
+
+#For MIPS Linux2.6
+ #pb45
+ #TOOL_PATH=/disk/pb45/sw/build/gcc-3.4.4-2.16.1/build_mips_nofpu/bin
+ #SYS_PATH=/disk/pb45/sw/linux/kernels/mips-linux-2.6.15
+
+ #ap81
+# compatiable with OpenWRT
+ifndef TOOL_PATH
+TOOL_PATH=/disk/ap81fus/sw/build/gcc-3.4.4-2.16.1/build_mips/bin
+endif
+ifndef SYS_PATH
+SYS_PATH=/disk/ap81fus/sw/linux/kernels/mips-linux-2.6.15
+endif
+ifeq ($(ARCH), mips)
+ CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+endif
+
+
+#db120
+ifeq ($(BOARD_TYPE),db12x)
+OS_SUB=31
+GCC_VER=4
+TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
+SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
+CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+endif
+
+ifeq ($(ARCH), arm)
+ CPU_CFLAG=-D__LINUX_ARM_ARCH__=7 -DMODULE -fno-common -DCONFIG_MMU
+endif
+
+ifeq ($(BOARD_TYPE), ap136)
+OS_SUB=31
+GCC_VER=4
+TOOL_PATH=$(TOPDIR)/build/gcc-4.3.3/build_mips/staging_dir/usr/bin
+SYS_PATH=$(TOPDIR)/linux/kernels/mips-linux-2.6.31
+CPU_CFLAG=-Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+endif
+
+#For MIPS Linux2.4
+ #TOOL_PATH=/home/perforce/kernel2.4/5.3.1.20/tools/gcc-3.3.3-2.4.25/toolchain_mips/bin
+ #SYS_PATH=/home/perforce/kernel2.4/5.3.1.20/src/kernels/mips-linux-2.4.25
+
+ #TOOLPREFIX=$(CPU)-$(OS)-
+ #CPU_CFLAG=-Wstrict-prototypes -Wundef -fomit-frame-pointer -G 0 -mno-abicalls -Wno-trigraphs -fno-strict-aliasing -fno-common -ffreestanding -O2 -fno-pic -pipe -mabi=32 -march=r4600 -Wa,-32 -Wa,-march=r4600 -Wa,--trap -DMODULE -mlong-calls -DEXPORT_SYMTAB
+
+
+KERNEL_MODE=TRUE
+#compatiable with OpenWRT
+ifeq ($(SWITCH_SSDK_MODE),user)
+KERNEL_MODE=FLASE
+endif
+
+#FAL=FALSE or not define FAL, FAL will not be included in SSDK
+FAL=FALSE
+
+#CHIP_TYPE can be defined as ATHENA, GARUDA, SHIVA, HORUS, ISIS, ISISC and ALL_CHIP(ALL_CHIP means GARUDA, SHIVA, HORUS and ISIS)
+CHIP_TYPE=ISISC
+
+#UK_IF=FALSE or not define UK_IF, UK_IF will not be included in SSDK
+#when UK_IF=TRUE one of UK_NETLINK,UK_IOCTL must be defined as TRUE
+UK_IF=TRUE
+#UK_IOCTL=TRUE define user-kernel space communication based on ioctl
+UK_IOCTL=TRUE
+UK_MINOR_DEV=254
+
+#API_LOCK=FALSE or not define API_LOCK, API_LOCK will not be included in SSDK
+API_LOCK=FALSE
+
+#REG_ACCESS_SPEEDUP=FALSE or not define REG_ACCESS_SPEEDUP, REG_ACCESS_SPEEDUP will not be enabled, now only ISIS supports
+REG_ACCESS_SPEEDUP=FALSE
+
+#ALL supported features:
+#ACL FDB IGMP LEAKY LED MIB MIRROR MISC PORTCONTROL PORTVLAN QOS RATE STP VLAN
+#IN_X=FALSE or not define IN_X, X will not be included in SSDK
+IN_ACL=TRUE
+IN_FDB=TRUE
+IN_IGMP=TRUE
+IN_LEAKY=TRUE
+IN_LED=TRUE
+IN_MIB=TRUE
+IN_MIRROR=TRUE
+IN_MISC=TRUE
+IN_PORTCONTROL=TRUE
+IN_PORTVLAN=TRUE
+IN_QOS=TRUE
+IN_RATE=TRUE
+IN_STP=TRUE
+IN_VLAN=TRUE
+IN_REDUCED_ACL=FALSE
+IN_COSMAP=TRUE
+IN_IP=TRUE
+IN_NAT=TRUE
+IN_TRUNK=TRUE
+IN_SEC=TRUE
+IN_NAT_HELPER=FALSE
+IN_INTERFACECONTROL=TRUE
+IN_MACBLOCK=FALSE
diff --git a/include/api/api_access.h b/include/api/api_access.h
new file mode 100644
index 0000000..ef1c45c
--- /dev/null
+++ b/include/api/api_access.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _API_ACCESS_H
+#define _API_ACCESS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ sw_api_func_t *
+ sw_api_func_find(a_uint32_t api_id);
+
+ sw_api_param_t *
+ sw_api_param_find(a_uint32_t api_id);
+
+ a_uint32_t
+ sw_api_param_nums(a_uint32_t api_id);
+
+ sw_error_t
+ sw_api_get(sw_api_t *sw_api);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _API_ACCESS_H */
diff --git a/include/api/api_desc.h b/include/api/api_desc.h
new file mode 100644
index 0000000..4bad209
--- /dev/null
+++ b/include/api/api_desc.h
@@ -0,0 +1,2173 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _API_DESC_H_
+#define _API_DESC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define SW_API_PT_DUPLEX_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_GET, SW_DUPLEX, sizeof(fal_port_duplex_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "duplex"),
+
+#define SW_API_PT_DUPLEX_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_DUPLEX_SET, SW_DUPLEX, sizeof(fal_port_duplex_t), SW_PARAM_IN, \
+ "duplex"),
+
+#define SW_API_PT_SPEED_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_SPEED_GET, SW_SPEED, sizeof(fal_port_speed_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "speed"),
+
+#define SW_API_PT_SPEED_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_SPEED_SET, SW_SPEED, sizeof(fal_port_speed_t), SW_PARAM_IN, \
+ "speed"),
+
+#define SW_API_PT_AN_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_AN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_AN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"),
+
+
+#define SW_API_PT_AN_ENABLE_DESC \
+ SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_AN_ENABLE, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+
+#define SW_API_PT_AN_RESTART_DESC \
+ SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_AN_RESTART, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+#define SW_API_PT_AN_ADV_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_GET, SW_CAP, 4, SW_PARAM_PTR|SW_PARAM_OUT, "autoneg"),
+
+#define SW_API_PT_AN_ADV_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_AN_ADV_SET, SW_CAP, 4, SW_PARAM_IN, "autoneg"),
+
+#define SW_API_PT_HDR_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_HDR_SET, SW_ENABLE, 4, SW_PARAM_IN, "Header"),
+
+#define SW_API_PT_HDR_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_HDR_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Header"),
+
+#define SW_API_PT_FLOWCTRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Flow control"),
+
+#define SW_API_PT_FLOWCTRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Flow control"),
+
+#define SW_API_PT_FLOWCTRL_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force mode"),
+
+#define SW_API_PT_FLOWCTRL_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FLOWCTRL_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force mode"),
+
+#define SW_API_PT_POWERSAVE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Powersave Status"),
+
+#define SW_API_PT_POWERSAVE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_POWERSAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Powersave Status"),
+
+#define SW_API_PT_HIBERNATE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Hibernate status"),
+
+#define SW_API_PT_HIBERNATE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_HIBERNATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hibernate Status"),
+
+#define SW_API_PT_CDT_DESC \
+ SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_CDT, SW_UINT32, 4, SW_PARAM_IN, "MDI Pair ID"), \
+ SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLESTATUS, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable status"), \
+ SW_PARAM_DEF(SW_API_PT_CDT, SW_CABLELEN, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cable len"),
+
+#define SW_API_PT_TXHDR_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_SET, SW_HDRMODE, sizeof(fal_port_header_mode_t), \
+ SW_PARAM_IN, "HdrMode"),
+
+#define SW_API_PT_TXHDR_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_TXHDR_GET, SW_HDRMODE, sizeof(fal_port_header_mode_t), \
+ SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"),
+
+#define SW_API_PT_RXHDR_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_SET, SW_HDRMODE, sizeof(fal_port_header_mode_t), \
+ SW_PARAM_IN, "HdrMode"),
+
+#define SW_API_PT_RXHDR_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_RXHDR_GET, SW_HDRMODE, sizeof(fal_port_header_mode_t), \
+ SW_PARAM_PTR|SW_PARAM_OUT, "HdrMode"),
+
+#define SW_API_HEADER_TYPE_SET_DESC \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_SET, SW_UINT32, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_HEADER_TYPE_GET_DESC \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+ SW_PARAM_DEF(SW_API_HEADER_TYPE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_TXMAC_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_TXMAC_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_TXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_RXMAC_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_RXMAC_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_RXMAC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_TXFC_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_TXFC_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_TXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_RXFC_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_RXFC_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_RXFC_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_BP_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_BP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_BP_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_BP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_PT_LINK_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Value"),
+
+#define SW_API_PT_LINK_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Value"),
+
+#define SW_API_PT_LINK_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_LINK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PT_MAC_LOOPBACK_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_MAC_LOOPBACK_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_LOOPBACK_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+
+#define SW_API_VLAN_ADD_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_VLAN_DEL_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_VLAN_MEM_UPDATE_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_IN, \
+ "Member Port Map"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEM_UPDATE, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_IN, \
+ "U Member Port Map"),
+
+#define SW_API_VLAN_FIND_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_FIND, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+ SW_PARAM_DEF(SW_API_VLAN_FIND, SW_VLAN, sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "Vlan Entry"),
+
+#define SW_API_VLAN_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"), \
+ SW_PARAM_DEF(SW_API_VLAN_NEXT, SW_VLAN, sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "Vlan Entry"),
+
+#define SW_API_VLAN_APPEND_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_APPEND, SW_VLAN, sizeof(fal_vlan_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Entry"),
+
+#define SW_API_VLAN_FLUSH_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_FLUSH, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_VLAN_FID_SET_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_FID_SET, SW_UINT32, 4, SW_PARAM_IN, "FDB ID"),
+
+#define SW_API_VLAN_FID_GET_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_FID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "FDB ID"),
+
+#define SW_API_VLAN_MEMBER_ADD_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_ADD, SW_EGMODE, sizeof(fal_pt_1q_egmode_t), \
+ SW_PARAM_IN, "Port Info"),
+
+#define SW_API_VLAN_MEMBER_DEL_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_MEMBER_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_VLAN_LEARN_STATE_SET_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_VLAN_LEARN_STATE_GET_DESC \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Vlan ID"), \
+ SW_PARAM_DEF(SW_API_VLAN_LEARN_STATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+
+#define SW_API_PT_ING_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_GET, SW_1QMODE, sizeof(fal_pt_1qmode_t), \
+ SW_PARAM_PTR|SW_PARAM_OUT, "1qmode"),
+
+#define SW_API_PT_ING_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_ING_MODE_SET, SW_1QMODE, sizeof(fal_pt_1qmode_t), \
+ SW_PARAM_IN, "1qmode"),
+
+#define SW_API_PT_EG_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_GET, SW_EGMODE, sizeof(fal_pt_1q_egmode_t),\
+ SW_PARAM_PTR|SW_PARAM_OUT, "egvlan"),
+
+#define SW_API_PT_EG_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_EG_MODE_SET, SW_EGMODE, sizeof(fal_pt_1q_egmode_t), \
+ SW_PARAM_IN, "egvlan"),
+
+#define SW_API_PT_VLAN_MEM_ADD_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_ADD, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"),
+
+#define SW_API_PT_VLAN_MEM_DEL_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_DEL, SW_UINT32, 4, SW_PARAM_IN, "Member Port Id"),
+
+#define SW_API_PT_VLAN_MEM_UPDATE_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_UPDATE, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_IN, \
+ "Member Port Bitmap"),
+
+#define SW_API_PT_VLAN_MEM_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_MEM_GET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "Member Port Bitmap"),
+
+#define SW_API_PT_DEF_VID_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."), \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Vlan Id"),
+
+#define SW_API_PT_DEF_VID_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID."), \
+ SW_PARAM_DEF(SW_API_PT_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Id"),
+
+#define SW_API_PT_FORCE_DEF_VID_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"),
+
+#define SW_API_PT_FORCE_DEF_VID_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_DEF_VID_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"),
+
+#define SW_API_PT_FORCE_PORTVLAN_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Force"),
+
+#define SW_API_PT_FORCE_PORTVLAN_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_FORCE_PORTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Force"),
+
+#define SW_API_PT_NESTVLAN_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Nestvlan"),
+
+#define SW_API_PT_NESTVLAN_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_NESTVLAN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Nestvlan"),
+
+#define SW_API_NESTVLAN_TPID_SET_DESC \
+ SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NESTVLAN_TPID_SET, SW_UINT32, 4, SW_PARAM_IN, "TPID"),
+
+#define SW_API_NESTVLAN_TPID_GET_DESC \
+ SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NESTVLAN_TPID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "TPID"),
+
+#define SW_API_PT_IN_VLAN_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_SET, SW_INVLAN, sizeof(fal_pt_invlan_mode_t), SW_PARAM_IN, "Invlan"),
+
+#define SW_API_PT_IN_VLAN_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_IN_VLAN_MODE_GET, SW_INVLAN, sizeof(fal_pt_invlan_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Invlan"),
+
+#define SW_API_PT_TLS_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_TLS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_TLS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_TLS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_PRI_PROPAGATION_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_PT_PRI_PROPAGATION_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_PRI_PROPAGATION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_DEF_SVID_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_SET, SW_UINT32, 4, SW_PARAM_IN, "svid"),
+
+#define SW_API_PT_DEF_SVID_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_SVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "svid"),
+
+#define SW_API_PT_DEF_CVID_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_SET, SW_UINT32, 4, SW_PARAM_IN, "cvid"),
+
+#define SW_API_PT_DEF_CVID_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DEF_CVID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "cvid"),
+
+#define SW_API_PT_VLAN_PROPAGATION_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_SET, SW_VLANPROPAGATION, sizeof(fal_vlan_propagation_mode_t), SW_PARAM_IN, "Vlan propagation"),
+
+#define SW_API_PT_VLAN_PROPAGATION_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_VLAN_PROPAGATION_GET, SW_VLANPROPAGATION, sizeof(fal_vlan_propagation_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vlan propagation"),
+
+#define SW_API_PT_VLAN_TRANS_ADD_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ADD, SW_VLANTRANSLATION, sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"),
+
+#define SW_API_PT_VLAN_TRANS_DEL_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_DEL, SW_VLANTRANSLATION, sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Vlan Translation"),
+
+#define SW_API_PT_VLAN_TRANS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_GET, SW_VLANTRANSLATION, sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Vlan Translation"),
+
+#define SW_API_QINQ_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_QINQ_MODE_SET, SW_QINQMODE, sizeof(fal_qinq_mode_t), SW_PARAM_IN, "qinq mode"),
+
+#define SW_API_QINQ_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_QINQ_MODE_GET, SW_QINQMODE, sizeof(fal_qinq_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq mode"),
+
+#define SW_API_PT_QINQ_ROLE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_SET, SW_QINQROLE, sizeof(fal_qinq_port_role_t), SW_PARAM_IN, "qinq role"),
+
+#define SW_API_PT_QINQ_ROLE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_QINQ_ROLE_GET, SW_QINQROLE, sizeof(fal_qinq_port_role_t), SW_PARAM_PTR|SW_PARAM_OUT, "qinq role"),
+
+#define SW_API_PT_VLAN_TRANS_ITERATE_DESC \
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+ SW_PARAM_DEF(SW_API_PT_VLAN_TRANS_ITERATE, SW_VLANTRANSLATION, sizeof(fal_vlan_trans_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Vlan Translation"),
+
+#define SW_API_PT_MAC_VLAN_XLT_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_PT_MAC_VLAN_XLT_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MAC_VLAN_XLT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NETISOLATE_SET_DESC \
+ SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NETISOLATE_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_NETISOLATE_GET_DESC \
+ SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NETISOLATE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_EG_FLTR_BYPASS_EN_SET_DESC \
+ SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_EG_FLTR_BYPASS_EN_GET_DESC \
+ SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_FDB_ADD_DESC \
+ SW_PARAM_DEF(SW_API_FDB_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_ADD, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"),
+
+#define SW_API_FDB_DELALL_DESC \
+ SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_DELALL, SW_UINT32, 4, SW_PARAM_IN, "Flag"),
+
+#define SW_API_FDB_DELPORT_DESC \
+ SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_DELPORT, SW_UINT32, 4, SW_PARAM_IN, "Flag"),
+
+#define SW_API_FDB_DELMAC_DESC \
+ SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_DELMAC, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Entry"),
+
+#define SW_API_FDB_FIRST_DESC \
+ SW_PARAM_DEF(SW_API_FDB_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_FIRST, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_FDB_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_NEXT, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_FIND_DESC \
+ SW_PARAM_DEF(SW_API_FDB_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_FIND, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_PT_LEARN_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Learn"),
+
+#define SW_API_FDB_PT_LEARN_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Learn"),
+
+#define SW_API_FDB_AGE_CTRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Age"),
+
+#define SW_API_FDB_AGE_CTRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_AGE_CTRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Age"),
+
+#define SW_API_FDB_VLAN_IVL_SVL_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, SW_FDBSMODE, 4, SW_PARAM_IN, "Smode"),
+
+#define SW_API_FDB_VLAN_IVL_SVL_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, SW_FDBSMODE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Smode"),
+
+#define SW_API_FDB_AGE_TIME_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"),
+
+#define SW_API_FDB_AGE_TIME_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_FDB_ITERATE_DESC \
+ SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+ SW_PARAM_DEF(SW_API_FDB_ITERATE, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_EXTEND_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBOPRATION, sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_NEXT, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_EXTEND_FIRST_DESC \
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBOPRATION, sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_TRANSFER_DESC \
+ SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "Old Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "New Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+ SW_PARAM_DEF(SW_API_FDB_TRANSFER, SW_FDBOPRATION, sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),
+
+#define SW_API_PT_FDB_LEARN_LIMIT_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_PT_FDB_LEARN_LIMIT_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_FDB_LEARN_LIMIT_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_FDB_LEARN_LIMIT_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_FDB_LEARN_EXCEED_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_FDB_LEARN_EXCEED_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_FDB_RESV_ADD_DESC \
+ SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_RESV_ADD, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_DEL_DESC \
+ SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_RESV_DEL, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_FIND_DESC \
+ SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_RESV_FIND, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Resv Entry"),
+
+#define SW_API_FDB_RESV_ITERATE_DESC \
+ SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Iterator"),\
+ SW_PARAM_DEF(SW_API_FDB_RESV_ITERATE, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_OUT, "Fdb Resv Entry"),
+
+#define SW_API_FDB_EXTEND_FIRST_DESC \
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBOPRATION, sizeof(fal_fdb_op_t), SW_PARAM_PTR|SW_PARAM_IN, "OperateOption"),\
+ SW_PARAM_DEF(SW_API_FDB_EXTEND_FIRST, SW_FDBENTRY, sizeof(fal_fdb_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Fdb Entry"),
+
+#define SW_API_FDB_PT_LEARN_STATIC_SET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "LearnStatic"),
+
+#define SW_API_FDB_PT_LEARN_STATIC_GET_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatic"),
+
+#define SW_API_FDB_PORT_ADD_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_MACADDR, sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_FDB_PORT_DEL_DESC \
+ SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "FID"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_MACADDR, sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "Address"),\
+ SW_PARAM_DEF(SW_API_FDB_PORT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+
+
+
+#define SW_API_ACL_LIST_CREAT_DESC \
+ SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_CREAT, SW_UINT32, 4, SW_PARAM_IN, "List Priority"),
+
+#define SW_API_ACL_LIST_DESTROY_DESC \
+ SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_DESTROY, SW_UINT32, 4, SW_PARAM_IN, "List ID"),
+
+#define SW_API_ACL_RULE_ADD_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ADD, SW_ACLRULE, sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_IN, "Rule"),
+
+#define SW_API_ACL_RULE_DELETE_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DELETE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_QUERY_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_QUERY, SW_ACLRULE, sizeof(fal_acl_rule_t), SW_PARAM_PTR|SW_PARAM_OUT, "Rule"),
+
+#define SW_API_ACL_LIST_BIND_DESC \
+ SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_LIST_UNBIND_DESC \
+ SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Direction"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Type"),\
+ SW_PARAM_DEF(SW_API_ACL_LIST_UNBIND, SW_UINT32, 4, SW_PARAM_IN, "Object Index"),
+
+#define SW_API_ACL_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_ACL_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_ACL_LIST_DUMP_DESC \
+ SW_PARAM_DEF(SW_API_ACL_LIST_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_RULE_DUMP_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_DUMP, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_ACL_PT_UDF_PROFILE_SET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_ACL_UDF_TYPE, sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_offset"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, SW_UINT32, 4, SW_PARAM_IN, "udf_length"),
+
+#define SW_API_ACL_PT_UDF_PROFILE_GET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_ACL_UDF_TYPE, sizeof(fal_acl_udf_type_t), SW_PARAM_IN, "udf_type"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "udf_offset"),\
+ SW_PARAM_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "udf_length"),
+
+#define SW_API_ACL_RULE_ACTIVE_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_ACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_DEACTIVE_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "List ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_DEACTIVE, SW_UINT32, 4, SW_PARAM_IN, "Rule Number"),
+
+#define SW_API_ACL_RULE_SRC_FILTER_STS_SET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_ACL_RULE_SRC_FILTER_STS_GET_DESC \
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_UINT32, 4, SW_PARAM_IN, "Rule ID"),\
+ SW_PARAM_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_QOS_SCH_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_SCH, sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_SET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_IN, "Weight"),
+
+#define SW_API_QOS_SCH_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_SCH, sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\
+ SW_PARAM_DEF(SW_API_QOS_SCH_MODE_GET, SW_UINT_A, 16, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"),
+
+#define SW_API_QOS_QU_TX_BUF_ST_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"),
+
+#define SW_API_QOS_QU_TX_BUF_ST_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"),
+
+#define SW_API_QOS_QU_TX_BUF_NR_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_QU_TX_BUF_NR_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_TX_BUF_ST_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Buffer limit"),
+
+#define SW_API_QOS_PT_TX_BUF_ST_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Buffer limit"),
+
+#define SW_API_QOS_PT_RED_EN_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "enable"),
+
+#define SW_API_QOS_PT_RED_EN_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RED_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_QOS_PT_TX_BUF_NR_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_TX_BUF_NR_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_RX_BUF_NR_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_QOS_PT_RX_BUF_NR_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Buffer Number"),
+
+#define SW_API_COSMAP_UP_QU_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_UP_QU_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"),\
+ SW_PARAM_DEF(SW_API_COSMAP_UP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_DSCP_QU_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_DSCP_QU_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"),\
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_QOS_PT_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_QOS, sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_QOS, sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_QOS_PT_MODE_PRI_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_QOS, sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_QOS_PT_MODE_PRI_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_QOS, sizeof(fal_qos_mode_t), SW_PARAM_IN, "Qos mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_MODE_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_QOS_PORT_DEF_UP_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_SET, SW_UINT32, 4, SW_PARAM_IN, "default up"),
+
+#define SW_API_QOS_PORT_DEF_UP_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_DEF_UP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default up"),
+
+#define SW_API_QOS_PORT_SCH_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_SCH, sizeof(fal_sch_mode_t), SW_PARAM_IN, "Schedule mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_SET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_IN, "Weight"),
+
+#define SW_API_QOS_PORT_SCH_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_SCH, sizeof(fal_sch_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Schedule mode"),\
+ SW_PARAM_DEF(SW_API_QOS_PORT_SCH_MODE_GET, SW_UINT_A, 24, SW_PARAM_PTR|SW_PARAM_OUT, "Weight"),
+
+#define SW_API_QOS_PT_DEF_SPRI_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default spri"),
+
+#define SW_API_QOS_PT_DEF_SPRI_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_SPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default spri"),
+
+#define SW_API_QOS_PT_DEF_CPRI_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_SET, SW_UINT32, 4, SW_PARAM_IN, "default cpri"),
+
+
+#define SW_API_QOS_PT_FORCE_SPRI_ST_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_SPRI_ST_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_CPRI_ST_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_PT_FORCE_CPRI_ST_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+#define SW_API_QOS_PT_DEF_CPRI_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_PT_DEF_CPRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "default cpri"),
+
+
+#define SW_API_QOS_QUEUE_REMARK_SET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_QOS_QUEUE_REMARK_GET_DESC \
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Table ID"), \
+ SW_PARAM_DEF(SW_API_QOS_QUEUE_REMARK_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+
+
+
+#define SW_API_PT_IGMPS_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "IGMP snooping"),
+
+#define SW_API_PT_IGMPS_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_IGMPS_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "IGMP snooping"),
+
+#define SW_API_IGMP_MLD_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_IGMP_MLD_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_MLD_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_IGMP_PT_JOIN_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Join"),
+
+#define SW_API_IGMP_PT_JOIN_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_JOIN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Join"),
+
+#define SW_API_IGMP_PT_LEAVE_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Leave"),
+
+#define SW_API_IGMP_PT_LEAVE_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_PT_LEAVE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Leave"),
+
+#define SW_API_IGMP_RP_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_RP_SET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_IN, "Ports"),
+
+#define SW_API_IGMP_RP_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_RP_GET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Ports"),
+
+#define SW_API_IGMP_ENTRY_CREAT_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_SET, SW_ENABLE, 4, SW_PARAM_IN, "creat Entry"),
+
+#define SW_API_IGMP_ENTRY_CREAT_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_CREAT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "creat Entry"),
+
+#define SW_API_IGMP_ENTRY_STATIC_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_SET, SW_ENABLE, 4, SW_PARAM_IN, "static"),
+
+#define SW_API_IGMP_ENTRY_STATIC_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_STATIC_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "static"),
+
+#define SW_API_IGMP_ENTRY_LEAKY_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, SW_ENABLE, 4, SW_PARAM_IN, "leaky"),
+
+#define SW_API_IGMP_ENTRY_LEAKY_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "leaky"),
+
+#define SW_API_IGMP_ENTRY_V3_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_SET, SW_ENABLE, 4, SW_PARAM_IN, "version3"),
+
+#define SW_API_IGMP_ENTRY_V3_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_V3_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "version3"),
+
+#define SW_API_IGMP_ENTRY_QUEUE_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_ENABLE, 4, SW_PARAM_IN, "queue"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, SW_UINT32, 4, SW_PARAM_IN, "queue_id"),
+
+#define SW_API_IGMP_ENTRY_QUEUE_GET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue"), \
+ SW_PARAM_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "queue_id"),
+
+#define SW_API_PT_IGMP_LEARN_LIMIT_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, SW_UINT32, 4, SW_PARAM_IN, "LimitCnt"),
+
+#define SW_API_PT_IGMP_LEARN_LIMIT_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"), \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LimitCnt"),
+
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_IGMP_SG_ENTRY_SET_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SET, SW_SGENTRY, sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"),
+
+#define SW_API_IGMP_SG_ENTRY_CLEAR_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, SW_SGENTRY, sizeof(fal_igmp_sg_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "entry"),
+
+#define SW_API_IGMP_SG_ENTRY_SHOW_DESC \
+ SW_PARAM_DEF(SW_API_IGMP_SG_ENTRY_SHOW, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+
+
+#define SW_API_UC_LEAKY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_SET, SW_LEAKY, sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Uc Leaky mode"),
+
+#define SW_API_UC_LEAKY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_UC_LEAKY_MODE_GET, SW_LEAKY, sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Uc Leaky mode"),
+
+#define SW_API_MC_LEAKY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_SET, SW_LEAKY, sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_IN, "Mc Leaky mode"),
+
+#define SW_API_MC_LEAKY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MC_LEAKY_MODE_GET, SW_LEAKY, sizeof(fal_leaky_ctrl_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mc Leaky mode"),
+
+#define SW_API_ARP_LEAKY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Arp leaky"),
+
+#define SW_API_ARP_LEAKY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_ARP_LEAKY_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Arp leaky"),
+
+#define SW_API_PT_UC_LEAKY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Unicast leaky"),
+
+#define SW_API_PT_UC_LEAKY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UC_LEAKY_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Port Uc leaky"),
+
+#define SW_API_PT_MC_LEAKY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_SET, SW_ENABLE, 4, SW_PARAM_IN, "Port Multicast leaky"),
+
+#define SW_API_PT_MC_LEAKY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_MC_LEAKY_MODE_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Port Mc leaky"),
+
+
+
+#define SW_API_MIRROR_ANALY_PT_SET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),
+
+#define SW_API_MIRROR_ANALY_PT_GET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_ANALY_PT_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Port ID"),
+
+#define SW_API_MIRROR_IN_PT_SET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Ingerss mirror"),
+
+#define SW_API_MIRROR_IN_PT_GET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_IN_PT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Ingeress mirror"),
+
+#define SW_API_MIRROR_EG_PT_SET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_SET, SW_ENABLE, 4, SW_PARAM_IN, "Egerss mirror"),
+
+#define SW_API_MIRROR_EG_PT_GET_DESC \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MIRROR_EG_PT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Egeress mirror"),
+
+
+
+#define SW_API_RATE_QU_EGRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_QU_EGRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_QU_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_RATE_PT_EGRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_PT_EGRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_EGRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_RATE_PT_INRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_SET, SW_ENABLE, 4, SW_PARAM_IN, "Rate limit"),
+
+#define SW_API_RATE_PT_INRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_INRL_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Rate limit"),
+
+#define SW_API_STORM_CTRL_FRAME_SET_DESC \
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_STORM, sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_SET, SW_ENABLE, 4, SW_PARAM_IN, "strom contrl"),
+
+#define SW_API_STORM_CTRL_FRAME_GET_DESC \
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_STORM, sizeof(fal_storm_type_t), SW_PARAM_IN, "Frame type"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_FRAME_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "strom contrl"),
+
+#define SW_API_STORM_CTRL_RATE_SET_DESC \
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Speed"),
+
+#define SW_API_STORM_CTRL_RATE_GET_DESC \
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STORM_CTRL_RATE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Speed"),
+
+#define SW_API_RATE_PORT_POLICER_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_SET, SW_INGPOLICER, sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_PORT_POLICER_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_POLICER_GET, SW_INGPOLICER, sizeof(fal_port_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_PORT_SHAPER_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"), \
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_SET, SW_EGSHAPER, sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_PORT_SHAPER_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+ SW_PARAM_DEF(SW_API_RATE_PORT_SHAPER_GET, SW_EGSHAPER, sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_QUEUE_SHAPER_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"), \
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_SET, SW_EGSHAPER, sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_QUEUE_SHAPER_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_UINT32, 4, SW_PARAM_IN, "Queue ID"),\
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+ SW_PARAM_DEF(SW_API_RATE_QUEUE_SHAPER_GET, SW_EGSHAPER, sizeof(fal_egress_shaper_t), SW_PARAM_PTR|SW_PARAM_OUT, "Shaper"),
+
+#define SW_API_RATE_ACL_POLICER_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_SET, SW_ACLPOLICER, sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_ACL_POLICER_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_UINT32, 4, SW_PARAM_IN, "Policer ID"),\
+ SW_PARAM_DEF(SW_API_RATE_ACL_POLICER_GET, SW_ACLPOLICER, sizeof(fal_acl_policer_t), SW_PARAM_PTR|SW_PARAM_OUT, "Policer"),
+
+#define SW_API_RATE_PT_ADDRATEBYTE_SET_DESC\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, SW_UINT32, 4, SW_PARAM_IN, "AddRateByte"),
+
+#define SW_API_RATE_PT_ADDRATEBYTE_GET_DESC\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "AddRateByte"),
+
+#define SW_API_RATE_PT_GOL_FLOW_EN_SET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_RATE_PT_GOL_FLOW_EN_GET_DESC \
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_STP_PT_STATE_SET_DESC \
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_SET, SW_STP, sizeof(fal_stp_state_t), SW_PARAM_IN, "Port State"),
+
+#define SW_API_STP_PT_STATE_GET_DESC \
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Spaning tree ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"),\
+ SW_PARAM_DEF(SW_API_STP_PT_STATE_GET, SW_STP, sizeof(fal_stp_state_t), SW_PARAM_PTR|SW_PARAM_OUT, "Port State"),
+
+
+
+
+#define SW_API_PT_MIB_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_UINT32, 4, SW_PARAM_IN, "Port No."), \
+ SW_PARAM_DEF(SW_API_PT_MIB_GET, SW_MIB, sizeof(fal_mib_info_t), SW_PARAM_PTR|SW_PARAM_OUT, \
+ "MIB info"),
+
+#define SW_API_MIB_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIB_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "MIB status"),
+
+#define SW_API_MIB_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIB_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "MIB status"),
+
+#define SW_API_PT_MIB_FLUSH_COUNTERS_DESC\
+ SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, SW_UINT32, 4, SW_PARAM_IN, "Port No."),
+
+#define SW_API_MIB_CPU_KEEP_SET_DESC \
+ SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_SET, SW_ENABLE, 4, SW_PARAM_IN, "CPU_KEEP Set"),
+
+#define SW_API_MIB_CPU_KEEP_GET_DESC \
+ SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MIB_CPU_KEEP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "CPU_KEEP Get"),
+
+
+
+
+
+
+#define SW_API_ARP_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP acknowledge"),
+
+#define SW_API_ARP_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ARP acknowledge"),
+
+#define SW_API_FRAME_MAX_SIZE_SET_DESC \
+ SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_SET, SW_UINT32, 4, SW_PARAM_IN, "Frame Size"),
+
+#define SW_API_FRAME_MAX_SIZE_GET_DESC \
+ SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FRAME_MAX_SIZE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Frame Size"),
+
+#define SW_API_PT_UNK_SA_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_PT_UNK_SA_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_SA_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PT_UNK_UC_FILTER_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_UNK_UC_FILTER_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_UC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_PT_UNK_MC_FILTER_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_UNK_MC_FILTER_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_UNK_MC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_PT_BC_FILTER_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_SET, SW_ENABLE, 4, SW_PARAM_IN, "Filter"),
+
+#define SW_API_PT_BC_FILTER_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_BC_FILTER_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Filter"),
+
+#define SW_API_CPU_PORT_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu port"),
+
+#define SW_API_CPU_PORT_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_CPU_PORT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu port"),
+
+#define SW_API_BC_TO_CPU_PORT_SET_DESC \
+ SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_SET, SW_ENABLE, 4, SW_PARAM_IN, "ToCpu"),
+
+#define SW_API_BC_TO_CPU_PORT_GET_DESC \
+ SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_BC_TO_CPU_PORT_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ToCpu"),
+
+#define SW_API_PPPOE_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_PPPOE_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PPPOE_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "PPPOE"),
+
+#define SW_API_PPPOE_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "PPPOE"),
+
+#define SW_API_PT_DHCP_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DHCP_SET, SW_ENABLE, 4, SW_PARAM_IN, "DHCP"),
+
+#define SW_API_PT_DHCP_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_DHCP_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DHCP"),
+
+#define SW_API_ARP_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_ARP_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_EAPOL_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "cmd"),
+
+#define SW_API_EAPOL_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "cmd"),
+
+#define SW_API_PPPOE_SESSION_ADD_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ADD, SW_ENABLE, 4, SW_PARAM_IN, "StripHdr"),
+
+#define SW_API_PPPOE_SESSION_DEL_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_DEL, SW_UINT32, 4, SW_PARAM_IN, "Session ID"),
+
+#define SW_API_PPPOE_SESSION_GET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_UINT32, 4, SW_PARAM_IN, "Session ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "StripHdr"),
+
+#define SW_API_EAPOL_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_EAPOL_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_EAPOL_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_RIPV1_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RIPV1_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_RIPV1_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RIPV1_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_PT_ARP_REQ_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Req acknowledge"),
+
+#define SW_API_PT_ARP_REQ_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_REQ_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ARP Req acknowledge"),
+
+#define SW_API_PT_ARP_ACK_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "ARP Ack acknowledge"),
+
+#define SW_API_PT_ARP_ACK_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PT_ARP_ACK_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ARP Ack acknowledge"),
+
+#define SW_API_PPPOE_SESSION_TABLE_ADD_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, SW_PPPOE, sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"),
+
+#define SW_API_PPPOE_SESSION_TABLE_DEL_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, SW_PPPOE, sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN, "Session"),
+
+#define SW_API_PPPOE_SESSION_TABLE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_TABLE_GET, SW_PPPOE, sizeof(fal_pppoe_session_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Session"),
+
+#define SW_API_PPPOE_SESSION_ID_SET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_SET, SW_UINT32, 4, SW_PARAM_IN, "ID"),
+
+#define SW_API_PPPOE_SESSION_ID_GET_DESC \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_IN, "Index"), \
+ SW_PARAM_DEF(SW_API_PPPOE_SESSION_ID_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "ID"),
+
+#define SW_API_INTR_MASK_SET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"),
+
+#define SW_API_INTR_MASK_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"),
+
+#define SW_API_INTR_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_INTR_STATUS_CLEAR_DESC \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_INTR_PORT_LINK_MASK_SET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Mask"),
+
+#define SW_API_INTR_PORT_LINK_MASK_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_MASK_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Mask"),
+
+#define SW_API_INTR_PORT_LINK_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_INTR_MASK_MAC_LINKCHG_SET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_INTR_MASK_MAC_LINKCHG_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Enable"),
+
+#define SW_API_INTR_STATUS_MAC_LINKCHG_GET_DESC \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Intr Port Bitmap"),
+
+#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR_DESC \
+ SW_PARAM_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#define SW_API_CPU_VID_EN_SET_DESC \
+ SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_CPU_VID_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "Cpu vid"),
+
+#define SW_API_CPU_VID_EN_GET_DESC \
+ SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_CPU_VID_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Cpu vid"),
+
+#define SW_API_RTD_PPPOE_EN_SET_DESC \
+ SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_SET, SW_ENABLE, 4, SW_PARAM_IN, "RTD PPPoE"),
+
+#define SW_API_RTD_PPPOE_EN_GET_DESC \
+ SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_RTD_PPPOE_EN_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "RTD PPPoE"),
+
+
+#define SW_API_LED_PATTERN_SET_DESC \
+ SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_SET, SW_LEDPATTERN, sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_IN, "Pattern"),
+
+#define SW_API_LED_PATTERN_GET_DESC \
+ SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern Group"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_UINT32, 4, SW_PARAM_IN, "Pattern ID"),\
+ SW_PARAM_DEF(SW_API_LED_PATTERN_GET, SW_LEDPATTERN, sizeof(led_ctrl_pattern_t), SW_PARAM_PTR|SW_PARAM_OUT, "Pattern"),
+
+
+#define SW_API_PHY_GET_DESC \
+ SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\
+ SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\
+ SW_PARAM_DEF(SW_API_PHY_GET, SW_UINT16, 2, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),
+
+
+#define SW_API_PHY_SET_DESC \
+ SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"),\
+ SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg ID"),\
+ SW_PARAM_DEF(SW_API_PHY_SET, SW_UINT16, 2, SW_PARAM_IN, "Data"),
+
+#define SW_API_REG_GET_DESC \
+ SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+ SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+ SW_PARAM_DEF(SW_API_REG_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_SET_DESC \
+ SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+ SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+ SW_PARAM_DEF(SW_API_REG_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_FIELD_GET_DESC \
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Data"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_GET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+#define SW_API_REG_FIELD_SET_DESC \
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Reg Addr"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Bit Offset"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Field Len"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "Data"),\
+ SW_PARAM_DEF(SW_API_REG_FIELD_SET, SW_UINT32, 4, SW_PARAM_IN, "Data Len"),
+
+
+
+
+#define SW_API_COSMAP_DSCP_TO_PRI_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_PRI_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_DSCP_TO_DP_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_DSCP_TO_DP_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "DSCP"), \
+ SW_PARAM_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_UP_TO_PRI_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_PRI_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_PRI_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Priority"),
+
+#define SW_API_COSMAP_UP_TO_DP_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_SET, SW_UINT32, 4, SW_PARAM_IN, "DP"),
+
+#define SW_API_COSMAP_UP_TO_DP_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dot1p"), \
+ SW_PARAM_DEF(SW_API_COSMAP_UP_TO_DP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "DP"),
+
+#define SW_API_COSMAP_PRI_TO_QU_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_QU_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_QU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_EHQU_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, SW_UINT32, 4, SW_PARAM_IN, "Queue"),
+
+#define SW_API_COSMAP_PRI_TO_EHQU_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_IN, "Priority"), \
+ SW_PARAM_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Queue"),
+
+#define SW_API_COSMAP_EG_REMARK_SET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_SET, SW_REMARKENTRY, sizeof(fal_egress_remark_table_t), SW_PARAM_IN|SW_PARAM_PTR, "Table Entry"),
+
+#define SW_API_COSMAP_EG_REMARK_GET_DESC \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_UINT32, 4, SW_PARAM_IN, "Table ID"), \
+ SW_PARAM_DEF(SW_API_COSMAP_EG_REMARK_GET, SW_REMARKENTRY, sizeof(fal_egress_remark_table_t), SW_PARAM_OUT|SW_PARAM_PTR, "Table Entry"),
+
+
+
+#define SW_API_SEC_NORM_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \
+ SW_PARAM_DEF(SW_API_SEC_NORM_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_NORM_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_IN, "NormItem"), \
+ SW_PARAM_DEF(SW_API_SEC_NORM_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_MAC_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_MAC_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_MAC_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_SEC_MAC, 4, SW_PARAM_IN, "MAC related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_MAC_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_SEC_IP, 4, SW_PARAM_IN, "IP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP4_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP4_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_SEC_IP4, 4, SW_PARAM_IN, "IP4 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_IP6_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_IP6_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_SEC_IP6, 4, SW_PARAM_IN, "IP6 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_IP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_TCP_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_TCP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_TCP_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_SEC_TCP, 4, SW_PARAM_IN, "TCP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_TCP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_UDP_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_UDP_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_UDP_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_SEC_UDP, 4, SW_PARAM_IN, "UDP related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_UDP_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_ICMP4_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_SEC_ICMP4, 4, SW_PARAM_IN, "ICMP4 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_ICMP4_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_SEC_ICMP4, 4, SW_PARAM_IN, "ICMP4 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP4_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_SEC_ICMP6_SET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_SEC_ICMP6, 4, SW_PARAM_IN, "ICMP6 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN, "NormVal"),
+
+#define SW_API_SEC_ICMP6_GET_DESC \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_SEC_ICMP6, 4, SW_PARAM_IN, "ICMP6 related normalized item"), \
+ SW_PARAM_DEF(SW_API_SEC_ICMP6_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "NormVal"),
+
+#define SW_API_IP_HOST_ADD_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_ADD, SW_IP_HOSTENTRY, sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_DEL_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_DEL, SW_IP_HOSTENTRY, sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Hostentry"),
+
+#define SW_API_IP_HOST_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_GET, SW_IP_HOSTENTRY, sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_NEXT, SW_IP_HOSTENTRY, sizeof(fal_host_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Hostentry"),
+
+#define SW_API_IP_HOST_COUNTER_BIND_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+ SW_PARAM_DEF(SW_API_IP_HOST_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_IP_HOST_PPPOE_BIND_DESC \
+ SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_UINT32, 4, SW_PARAM_IN, "PPPoEID"), \
+ SW_PARAM_DEF(SW_API_IP_HOST_PPPOE_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_IP_PT_ARP_LEARN_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "LearnStatus"),
+
+#define SW_API_IP_PT_ARP_LEARN_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_PT_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "LearnStatus"),
+
+#define SW_API_IP_ARP_LEARN_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_LEARN_SET, SW_ARP_LEARNMODE, sizeof(fal_arp_learn_mode_t), SW_PARAM_IN, "LearnMode"),
+
+#define SW_API_IP_ARP_LEARN_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_LEARN_GET, SW_ARP_LEARNMODE, sizeof(fal_arp_learn_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "LearnMode"),
+
+#define SW_API_IP_SOURCE_GUARD_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_SET, SW_IP_GUARDMODE, sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"),
+
+#define SW_API_IP_SOURCE_GUARD_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_SOURCE_GUARD_GET, SW_IP_GUARDMODE, sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"),
+
+#define SW_API_IP_ARP_GUARD_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_SET, SW_IP_GUARDMODE, sizeof(fal_source_guard_mode_t), SW_PARAM_IN, "GuardMode"),
+
+#define SW_API_IP_ARP_GUARD_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_IP_ARP_GUARD_GET, SW_IP_GUARDMODE, sizeof(fal_source_guard_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "GuardMode"),
+
+#define SW_API_IP_ROUTE_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_IP_ROUTE_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_ROUTE_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_IP_INTF_ENTRY_ADD_DESC \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_ADD, SW_INTFMACENTRY, sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"),
+
+#define SW_API_IP_INTF_ENTRY_DEL_DESC \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Del Mode"), \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_DEL, SW_INTFMACENTRY, sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Entry"),
+
+#define SW_API_IP_INTF_ENTRY_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Next Mode"), \
+ SW_PARAM_DEF(SW_API_IP_INTF_ENTRY_NEXT, SW_INTFMACENTRY, sizeof(fal_intf_mac_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Entry"),
+
+#define SW_API_IP_UNK_SOURCE_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_IP_UNK_SOURCE_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_ARP_UNK_SOURCE_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_ARP_UNK_SOURCE_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_IP_AGE_TIME_SET_DESC \
+ SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_AGE_TIME_SET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Time"),
+
+#define SW_API_IP_AGE_TIME_GET_DESC \
+ SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_IP_AGE_TIME_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Time"),
+
+#define SW_API_WCMP_HASH_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"),
+
+#define SW_API_WCMP_HASH_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_WCMP_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"),
+
+
+
+
+#define SW_API_NAT_ADD_DESC \
+ SW_PARAM_DEF(SW_API_NAT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_ADD, SW_NATENTRY, sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_DEL_DESC \
+ SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \
+ SW_PARAM_DEF(SW_API_NAT_DEL, SW_NATENTRY, sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Natentry"),
+
+#define SW_API_NAT_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \
+ SW_PARAM_DEF(SW_API_NAT_GET, SW_NATENTRY, sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \
+ SW_PARAM_DEF(SW_API_NAT_NEXT, SW_NATENTRY, sizeof(fal_nat_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Natentry"),
+
+#define SW_API_NAT_COUNTER_BIND_DESC \
+ SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \
+ SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+ SW_PARAM_DEF(SW_API_NAT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_NAPT_ADD_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_ADD, SW_NAPTENTRY, sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_DEL_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \
+ SW_PARAM_DEF(SW_API_NAPT_DEL, SW_NAPTENTRY, sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN, "Naptentry"),
+
+#define SW_API_NAPT_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_GET, SW_UINT32, 4, SW_PARAM_IN, "GetMode"), \
+ SW_PARAM_DEF(SW_API_NAPT_GET, SW_NAPTENTRY, sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \
+ SW_PARAM_DEF(SW_API_NAPT_NEXT, SW_NAPTENTRY, sizeof(fal_napt_entry_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "Naptentry"),
+
+#define SW_API_NAPT_COUNTER_BIND_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "EntryID"), \
+ SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_UINT32, 4, SW_PARAM_IN, "CounterID"),\
+ SW_PARAM_DEF(SW_API_NAPT_COUNTER_BIND, SW_ENABLE, 4, SW_PARAM_IN, "Enable"),
+
+#define SW_API_NAT_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_NAT_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NAT_HASH_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_HASH_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Hashmode"),
+
+#define SW_API_NAT_HASH_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_HASH_MODE_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hashmode"),
+
+#define SW_API_NAPT_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_STATUS_SET, SW_ENABLE, 4, SW_PARAM_IN, "Status"),
+
+#define SW_API_NAPT_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_STATUS_GET, SW_ENABLE, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_NAPT_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_MODE_SET, SW_NAPTMODE, sizeof(fal_napt_mode_t), SW_PARAM_IN, "Mode"),
+
+#define SW_API_NAPT_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAPT_MODE_GET, SW_NAPTMODE, sizeof(fal_napt_mode_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"),
+
+#define SW_API_PRV_BASE_ADDR_SET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_SET, SW_IP4ADDR, sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseAddr"),
+
+#define SW_API_PRV_BASE_ADDR_GET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_BASE_ADDR_GET, SW_IP4ADDR, sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseAddr"),
+
+#define SW_API_PRV_ADDR_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "Mode"),
+
+#define SW_API_PRV_ADDR_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_ADDR_MODE_GET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Mode"),
+
+#define SW_API_PUB_ADDR_ENTRY_ADD_DESC \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_ADD, SW_PUBADDRENTRY, sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "PubAddrEntry"),
+
+#define SW_API_PUB_ADDR_ENTRY_DEL_DESC \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_UINT32, 4, SW_PARAM_IN, "DelMode"), \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_DEL, SW_PUBADDRENTRY, sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "PubAddrEntry"),
+
+#define SW_API_PUB_ADDR_ENTRY_NEXT_DESC \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_UINT32, 4, SW_PARAM_IN, "NextMode"), \
+ SW_PARAM_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, SW_PUBADDRENTRY, sizeof(fal_nat_pub_addr_t), SW_PARAM_PTR|SW_PARAM_IN|SW_PARAM_OUT, "PubAddrEntry"),
+
+#define SW_API_NAT_UNK_SESSION_CMD_SET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_IN, "Forwarding"),
+
+#define SW_API_NAT_UNK_SESSION_CMD_GET_DESC \
+ SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, SW_MACCMD, sizeof(fal_fwd_cmd_t), SW_PARAM_PTR|SW_PARAM_OUT, "Forwarding"),
+
+#define SW_API_PRV_BASE_MASK_SET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_BASE_MASK_SET, SW_IP4ADDR, sizeof(fal_ip4_addr_t), SW_PARAM_IN, "BaseMask"),
+
+#define SW_API_PRV_BASE_MASK_GET_DESC \
+ SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PRV_BASE_MASK_GET, SW_IP4ADDR, sizeof(fal_ip4_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "BaseMask"),
+
+
+#define SW_API_TRUNK_GROUP_SET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "Status"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_SET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_IN, "Member Port Bitmap"),
+
+#define SW_API_TRUNK_GROUP_GET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_UINT32, 4, SW_PARAM_IN, "Trunk ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"), \
+ SW_PARAM_DEF(SW_API_TRUNK_GROUP_GET, SW_PBMP, sizeof(fal_pbmp_t), SW_PARAM_PTR|SW_PARAM_OUT, "Member Port Bitmap"),
+
+#define SW_API_TRUNK_HASH_SET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_HASH_SET, SW_UINT32, 4, SW_PARAM_IN, "Hash Mode"),
+
+#define SW_API_TRUNK_HASH_GET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_HASH_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "Hash Mode"),
+
+#define SW_API_TRUNK_MAN_SA_SET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_SET, SW_MACADDR, sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_IN, "[Manipulable SA]:"),
+
+#define SW_API_TRUNK_MAN_SA_GET_DESC \
+ SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_TRUNK_MAN_SA_GET, SW_MACADDR, sizeof(fal_mac_addr_t), SW_PARAM_PTR|SW_PARAM_OUT, "[Manipulable SA]:"),
+
+
+#define SW_API_MAC_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MAC_MODE_SET, SW_MACCONFIG, sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_IN, "MAC config"),
+
+#define SW_API_MAC_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_MAC_MODE_GET, SW_MACCONFIG, sizeof(fal_mac_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "MAC config"),
+
+#define SW_API_PORT_3AZ_STATUS_SET_DESC \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "Status"),
+
+#define SW_API_PORT_3AZ_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Port ID"), \
+ SW_PARAM_DEF(SW_API_PORT_3AZ_STATUS_GET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "Status"),
+
+#define SW_API_PHY_MODE_SET_DESC \
+ SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \
+ SW_PARAM_DEF(SW_API_PHY_MODE_SET, SW_PHYCONFIG, sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_IN, "PHY config"),
+
+#define SW_API_PHY_MODE_GET_DESC \
+ SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_UINT32, 4, SW_PARAM_IN, "Phy ID"), \
+ SW_PARAM_DEF(SW_API_PHY_MODE_GET, SW_PHYCONFIG, sizeof(fal_phy_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "PHY config"),
+
+#define SW_API_FX100_CTRL_SET_DESC \
+ SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FX100_CTRL_SET, SW_FX100CONFIG, sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_IN, "fx100 config"),
+
+#define SW_API_FX100_CTRL_GET_DESC \
+ SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FX100_CTRL_GET, SW_FX100CONFIG, sizeof(fal_fx100_ctrl_config_t), SW_PARAM_PTR|SW_PARAM_OUT, "fx100 config"),
+
+#define SW_API_FX100_STATUS_GET_DESC \
+ SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_FX100_STATUS_GET, SW_UINT32, 4, SW_PARAM_PTR|SW_PARAM_OUT, "fx100 status"),
+
+
+#define SW_API_MAC06_EXCH_SET_DESC \
+ SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MAC06_EXCH_SET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_IN, "enable"),
+
+#define SW_API_MAC06_EXCH_GET_DESC \
+ SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_MAC06_EXCH_GET, SW_ENABLE, sizeof(a_bool_t), SW_PARAM_PTR|SW_PARAM_OUT, "enable"),
+
+#define SW_API_DESC(api_id) api_id##_DESC
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _API_DESC_H_ */
+
diff --git a/include/api/sw_api.h b/include/api/sw_api.h
new file mode 100644
index 0000000..c718d28
--- /dev/null
+++ b/include/api/sw_api.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_API_H
+#define _SW_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+
+#define SW_MAX_API_BUF 1024
+#define SW_MAX_API_PARAM 12 /* cmd type + return value + ten parameters */
+#define SW_MAX_PAYLOAD (SW_MAX_API_PARAM << 2) /* maximum payload size for netlink msg*/
+#define SW_PARAM_IN 0x1
+#define SW_PARAM_OUT 0x2
+#define SW_PARAM_PTR 0x4
+
+#define SW_API_DEF(ioctl, name) {ioctl, name}
+#if (!defined(KERNEL_MODULE))
+#define SW_PARAM_DEF(ioctl, data, size, type, name) \
+ {ioctl, size, data, type, name}
+#else
+#define SW_PARAM_DEF(ioctl, data, size, type, name) {ioctl, size, data, type}
+#endif
+
+ typedef enum
+ {
+ SW_UINT8 = 1,
+ SW_INT8,
+ SW_UINT16,
+ SW_INT16,
+ SW_UINT32,
+ SW_INT32,
+ SW_UINT64,
+ SW_INT64,
+ SW_ENABLE,
+ SW_SPEED,
+ SW_DUPLEX,
+ SW_1QMODE,
+ SW_EGMODE,
+ SW_CAP,
+ SW_VLAN,
+ SW_PBMP,
+ SW_MIB,
+ SW_MACADDR,
+ SW_FDBENTRY,
+ SW_SCH,
+ SW_QOS,
+ SW_STORM,
+ SW_STP,
+ SW_LEAKY,
+ SW_MACCMD,
+ SW_UINT_A,
+ SW_ACLRULE,
+ SW_LEDPATTERN,
+ SW_INVLAN,
+ SW_VLANPROPAGATION,
+ SW_VLANTRANSLATION,
+ SW_QINQMODE,
+ SW_QINQROLE,
+ SW_CABLESTATUS,
+ SW_CABLELEN,
+ SW_SSDK_CFG,
+ SW_HDRMODE,
+ SW_FDBOPRATION,
+ SW_PPPOE,
+ SW_ACL_UDF_TYPE,
+ SW_IP_HOSTENTRY,
+ SW_ARP_LEARNMODE,
+ SW_IP_GUARDMODE,
+ SW_NATENTRY,
+ SW_NAPTENTRY,
+ SW_NAPTMODE,
+ SW_IP4ADDR,
+ SW_IP6ADDR,
+ SW_INTFMACENTRY,
+ SW_PUBADDRENTRY,
+ SW_INGPOLICER,
+ SW_EGSHAPER,
+ SW_ACLPOLICER,
+ SW_MACCONFIG,
+ SW_PHYCONFIG,
+ SW_DATA_MAX,
+ SW_FDBSMODE,
+ SW_FX100CONFIG,
+ SW_SGENTRY,
+ SW_SEC_MAC,
+ SW_SEC_IP,
+ SW_SEC_IP4,
+ SW_SEC_IP6,
+ SW_SEC_TCP,
+ SW_SEC_UDP,
+ SW_SEC_ICMP4,
+ SW_SEC_ICMP6,
+ SW_REMARKENTRY,
+ } sw_data_type_e;
+
+ typedef struct
+ {
+ a_uint32_t api_id;
+ void *func;
+ } sw_api_func_t;
+
+ typedef struct
+ {
+ a_uint32_t api_id;
+ a_uint16_t data_size;
+ a_uint8_t data_type;
+ a_uint8_t param_type;
+#if (!defined(KERNEL_MODULE))
+ a_uint8_t param_name[20];
+#endif
+ } sw_api_param_t;
+
+ typedef struct
+ {
+ a_uint32_t api_id;
+ sw_api_func_t *api_fp;
+ sw_api_param_t *api_pp;
+ a_uint32_t api_nr;
+ } sw_api_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_API_H */
diff --git a/include/api/sw_ioctl.h b/include/api/sw_ioctl.h
new file mode 100644
index 0000000..e765539
--- /dev/null
+++ b/include/api/sw_ioctl.h
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_IOCTL_H_
+#define _SW_IOCTL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ /*init*/
+#define SW_API_INIT_OFFSET 10
+#define SW_API_SWITCH_INIT (0 + SW_API_INIT_OFFSET)
+#define SW_API_SWITCH_RESET (1 + SW_API_INIT_OFFSET)
+#define SW_API_SSDK_CFG (2 + SW_API_INIT_OFFSET)
+
+ /*port ctrl*/
+#define SW_API_PORT_OFFSET 30
+#define SW_API_PT_DUPLEX_GET (0 + SW_API_PORT_OFFSET)
+#define SW_API_PT_DUPLEX_SET (1 + SW_API_PORT_OFFSET)
+#define SW_API_PT_SPEED_GET (2 + SW_API_PORT_OFFSET)
+#define SW_API_PT_SPEED_SET (3 + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ADV_GET (4 + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ADV_SET (5 + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_GET (6 + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_ENABLE (7 + SW_API_PORT_OFFSET)
+#define SW_API_PT_AN_RESTART (8 + SW_API_PORT_OFFSET)
+#define SW_API_PT_HDR_SET (9 + SW_API_PORT_OFFSET)
+#define SW_API_PT_HDR_GET (10 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_SET (11 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_GET (12 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_MODE_SET (13 + SW_API_PORT_OFFSET)
+#define SW_API_PT_FLOWCTRL_MODE_GET (14 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWERSAVE_SET (15 + SW_API_PORT_OFFSET)
+#define SW_API_PT_POWERSAVE_GET (16 + SW_API_PORT_OFFSET)
+#define SW_API_PT_HIBERNATE_SET (17 + SW_API_PORT_OFFSET)
+#define SW_API_PT_HIBERNATE_GET (18 + SW_API_PORT_OFFSET)
+#define SW_API_PT_CDT (19 + SW_API_PORT_OFFSET)
+#define SW_API_PT_TXHDR_SET (20 + SW_API_PORT_OFFSET)
+#define SW_API_PT_TXHDR_GET (21 + SW_API_PORT_OFFSET)
+#define SW_API_PT_RXHDR_SET (22 + SW_API_PORT_OFFSET)
+#define SW_API_PT_RXHDR_GET (23 + SW_API_PORT_OFFSET)
+#define SW_API_HEADER_TYPE_SET (24 + SW_API_PORT_OFFSET)
+#define SW_API_HEADER_TYPE_GET (25 + SW_API_PORT_OFFSET)
+#define SW_API_TXMAC_STATUS_SET (26 + SW_API_PORT_OFFSET)
+#define SW_API_TXMAC_STATUS_GET (27 + SW_API_PORT_OFFSET)
+#define SW_API_RXMAC_STATUS_SET (28 + SW_API_PORT_OFFSET)
+#define SW_API_RXMAC_STATUS_GET (29 + SW_API_PORT_OFFSET)
+#define SW_API_TXFC_STATUS_SET (30 + SW_API_PORT_OFFSET)
+#define SW_API_TXFC_STATUS_GET (31 + SW_API_PORT_OFFSET)
+#define SW_API_RXFC_STATUS_SET (32 + SW_API_PORT_OFFSET)
+#define SW_API_RXFC_STATUS_GET (33 + SW_API_PORT_OFFSET)
+#define SW_API_BP_STATUS_SET (34 + SW_API_PORT_OFFSET)
+#define SW_API_BP_STATUS_GET (35 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LINK_MODE_SET (36 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LINK_MODE_GET (37 + SW_API_PORT_OFFSET)
+#define SW_API_PT_LINK_STATUS_GET (38 + SW_API_PORT_OFFSET)
+#define SW_API_PT_MAC_LOOPBACK_SET (39+ SW_API_PORT_OFFSET)
+#define SW_API_PT_MAC_LOOPBACK_GET (40+ SW_API_PORT_OFFSET)
+
+ /*vlan*/
+#define SW_API_VLAN_OFFSET 100
+#define SW_API_VLAN_ADD (0 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_DEL (1 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEM_UPDATE (2 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FIND (3 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_NEXT (4 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_APPEND (5 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FLUSH (6 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FID_SET (7 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_FID_GET (8 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEMBER_ADD (9 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_MEMBER_DEL (10 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_LEARN_STATE_SET (11 + SW_API_VLAN_OFFSET)
+#define SW_API_VLAN_LEARN_STATE_GET (12 + SW_API_VLAN_OFFSET)
+
+
+ /*portvlan*/
+#define SW_API_PORTVLAN_OFFSET 200
+#define SW_API_PT_ING_MODE_GET (0 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_ING_MODE_SET (1 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_EG_MODE_GET (2 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_EG_MODE_SET (3 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_ADD (4 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_DEL (5 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_UPDATE (6 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_MEM_GET (7 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_VID_GET (8 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_VID_SET (9 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_DEF_VID_SET (10 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_DEF_VID_GET (11 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_PORTVLAN_SET (12 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_FORCE_PORTVLAN_GET (13 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_NESTVLAN_SET (14 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_NESTVLAN_GET (15 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NESTVLAN_TPID_SET (16 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NESTVLAN_TPID_GET (17 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_IN_VLAN_MODE_SET (18 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_IN_VLAN_MODE_GET (19 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TLS_SET (20 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_TLS_GET (21 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_PRI_PROPAGATION_SET (22 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_PRI_PROPAGATION_GET (23 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_SVID_SET (24 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_SVID_GET (25 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_CVID_SET (26 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_DEF_CVID_GET (27 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_PROPAGATION_SET (28 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_PROPAGATION_GET (29 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ADD (30 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_DEL (31 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_GET (32 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_QINQ_MODE_SET (33 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_QINQ_MODE_GET (34 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_QINQ_ROLE_SET (35 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_QINQ_ROLE_GET (36 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_VLAN_TRANS_ITERATE (37 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_MAC_VLAN_XLT_SET (38 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_PT_MAC_VLAN_XLT_GET (39 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NETISOLATE_SET (40 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_NETISOLATE_GET (41 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EG_FLTR_BYPASS_EN_SET (42 + SW_API_PORTVLAN_OFFSET)
+#define SW_API_EG_FLTR_BYPASS_EN_GET (43 + SW_API_PORTVLAN_OFFSET)
+
+ /*fdb*/
+#define SW_API_FDB_OFFSET 300
+#define SW_API_FDB_ADD (0 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELALL (1 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELPORT (2 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_DELMAC (3 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_FIRST (4 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_NEXT (5 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_FIND (6 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_SET (7 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_GET (8 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_CTRL_SET (9 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_CTRL_GET (10 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_TIME_SET (11 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_AGE_TIME_GET (12 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_ITERATE (13 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_EXTEND_NEXT (14 + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_LIMIT_SET (15 + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_LIMIT_GET (16 + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_SET (17 + SW_API_FDB_OFFSET)
+#define SW_API_PT_FDB_LEARN_EXCEED_CMD_GET (18 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_LIMIT_SET (19 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_LIMIT_GET (20 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_EXCEED_CMD_SET (21 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_LEARN_EXCEED_CMD_GET (22 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_ADD (23 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_DEL (24 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_FIND (25 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_RESV_ITERATE (26 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_EXTEND_FIRST (27 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_STATIC_SET (28 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PT_LEARN_STATIC_GET (29 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_TRANSFER (30 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PORT_ADD (31 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_PORT_DEL (32 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_VLAN_IVL_SVL_SET (33 + SW_API_FDB_OFFSET)
+#define SW_API_FDB_VLAN_IVL_SVL_GET (34 + SW_API_FDB_OFFSET)
+
+
+ /*acl*/
+#define SW_API_ACL_OFFSET 400
+#define SW_API_ACL_LIST_CREAT (0 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_DESTROY (1 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_ADD (2 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DELETE (3 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_QUERY (4 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_BIND (5 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_UNBIND (6 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_STATUS_SET (7 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_STATUS_GET (8 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_LIST_DUMP (9 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DUMP (10 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_PT_UDF_PROFILE_SET (11 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_PT_UDF_PROFILE_GET (12 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_ACTIVE (13 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_DEACTIVE (14 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_SRC_FILTER_STS_SET (15 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_SRC_FILTER_STS_GET (16 + SW_API_ACL_OFFSET)
+#define SW_API_ACL_RULE_GET_OFFSET (17 + SW_API_ACL_OFFSET)
+
+ /*qos*/
+#define SW_API_QOS_OFFSET 500
+#define SW_API_QOS_SCH_MODE_SET (0 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_SCH_MODE_GET (1 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_ST_SET (2 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_ST_GET (3 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_NR_SET (4 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QU_TX_BUF_NR_GET (5 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_ST_SET (6 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_ST_GET (7 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_NR_SET (8 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_TX_BUF_NR_GET (9 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RX_BUF_NR_SET (10 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RX_BUF_NR_GET (11 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_SET (12 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_GET (13 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_PRI_SET (14 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_MODE_PRI_GET (15 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_DEF_UP_SET (16 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_DEF_UP_GET (17 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCH_MODE_SET (18 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PORT_SCH_MODE_GET (19 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_SPRI_SET (20 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_SPRI_GET (21 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_CPRI_SET (22 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_DEF_CPRI_GET (23 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_SPRI_ST_SET (24 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_SPRI_ST_GET (25 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_CPRI_ST_SET (26 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_FORCE_CPRI_ST_GET (27 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_REMARK_SET (28 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_QUEUE_REMARK_GET (29 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RED_EN_SET (30 + SW_API_QOS_OFFSET)
+#define SW_API_QOS_PT_RED_EN_GET (31 + SW_API_QOS_OFFSET)
+
+ /* igmp */
+#define SW_API_IGMP_OFFSET 600
+#define SW_API_PT_IGMPS_MODE_SET (0 + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMPS_MODE_GET (1 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_MLD_CMD_SET (2 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_MLD_CMD_GET (3 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_JOIN_SET (4 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_JOIN_GET (5 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_LEAVE_SET (6 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_PT_LEAVE_GET (7 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_RP_SET (8 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_RP_GET (9 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_CREAT_SET (10 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_CREAT_GET (11 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_STATIC_SET (12 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_STATIC_GET (13 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_LEAKY_SET (14 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_LEAKY_GET (15 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_V3_SET (16 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_V3_GET (17 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_QUEUE_SET (18 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_ENTRY_QUEUE_GET (19 + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_LIMIT_SET (20 + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_LIMIT_GET (21 + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET (22 + SW_API_IGMP_OFFSET)
+#define SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET (23 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_SET (24 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_CLEAR (25 + SW_API_IGMP_OFFSET)
+#define SW_API_IGMP_SG_ENTRY_SHOW (26 + SW_API_IGMP_OFFSET)
+
+ /* leaky */
+#define SW_API_LEAKY_OFFSET 700
+#define SW_API_UC_LEAKY_MODE_SET (0 + SW_API_LEAKY_OFFSET)
+#define SW_API_UC_LEAKY_MODE_GET (1 + SW_API_LEAKY_OFFSET)
+#define SW_API_MC_LEAKY_MODE_SET (2 + SW_API_LEAKY_OFFSET)
+#define SW_API_MC_LEAKY_MODE_GET (3 + SW_API_LEAKY_OFFSET)
+#define SW_API_ARP_LEAKY_MODE_SET (4 + SW_API_LEAKY_OFFSET)
+#define SW_API_ARP_LEAKY_MODE_GET (5 + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_UC_LEAKY_MODE_SET (6 + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_UC_LEAKY_MODE_GET (7 + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_MC_LEAKY_MODE_SET (8 + SW_API_LEAKY_OFFSET)
+#define SW_API_PT_MC_LEAKY_MODE_GET (9 + SW_API_LEAKY_OFFSET)
+
+ /*mirror*/
+#define SW_API_MIR_OFFSET 800
+#define SW_API_MIRROR_ANALY_PT_SET (0 + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_ANALY_PT_GET (1 + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_IN_PT_SET (2 + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_IN_PT_GET (3 + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_EG_PT_SET (4 + SW_API_MIR_OFFSET)
+#define SW_API_MIRROR_EG_PT_GET (5 + SW_API_MIR_OFFSET)
+
+ /*rate*/
+#define SW_API_RATE_OFFSET 900
+#define SW_API_RATE_QU_EGRL_SET (0 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QU_EGRL_GET (1 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_EGRL_SET (2 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_EGRL_GET (3 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_INRL_SET (4 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_INRL_GET (5 + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_FRAME_SET (6 + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_FRAME_GET (7 + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_RATE_SET (8 + SW_API_RATE_OFFSET)
+#define SW_API_STORM_CTRL_RATE_GET (9 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_POLICER_SET (10 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_POLICER_GET (11 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_SHAPER_SET (12 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PORT_SHAPER_GET (13 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QUEUE_SHAPER_SET (14 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_QUEUE_SHAPER_GET (15 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_ACL_POLICER_SET (16 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_ACL_POLICER_GET (17 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_ADDRATEBYTE_SET (18 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_ADDRATEBYTE_GET (19 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_GOL_FLOW_EN_SET (20 + SW_API_RATE_OFFSET)
+#define SW_API_RATE_PT_GOL_FLOW_EN_GET (21 + SW_API_RATE_OFFSET)
+
+ /*stp*/
+#define SW_API_STP_OFFSET 1000
+#define SW_API_STP_PT_STATE_SET (0 + SW_API_STP_OFFSET)
+#define SW_API_STP_PT_STATE_GET (1 + SW_API_STP_OFFSET)
+
+ /*mib*/
+#define SW_API_MIB_OFFSET 1100
+#define SW_API_PT_MIB_GET (0 + SW_API_MIB_OFFSET)
+#define SW_API_MIB_STATUS_SET (1 + SW_API_MIB_OFFSET)
+#define SW_API_MIB_STATUS_GET (2 + SW_API_MIB_OFFSET)
+#define SW_API_PT_MIB_FLUSH_COUNTERS (3+ SW_API_MIB_OFFSET)
+#define SW_API_MIB_CPU_KEEP_SET (4+ SW_API_MIB_OFFSET)
+#define SW_API_MIB_CPU_KEEP_GET (5+ SW_API_MIB_OFFSET)
+
+ /*misc*/
+#define SW_API_MISC_OFFSET 1200
+#define SW_API_ARP_STATUS_SET (0 + SW_API_MISC_OFFSET)
+#define SW_API_ARP_STATUS_GET (1 + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_MAX_SIZE_SET (2 + SW_API_MISC_OFFSET)
+#define SW_API_FRAME_MAX_SIZE_GET (3 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_SA_CMD_SET (4 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_SA_CMD_GET (5 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_UC_FILTER_SET (6 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_UC_FILTER_GET (7 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_MC_FILTER_SET (8 + SW_API_MISC_OFFSET)
+#define SW_API_PT_UNK_MC_FILTER_GET (9 + SW_API_MISC_OFFSET)
+#define SW_API_PT_BC_FILTER_SET (10 + SW_API_MISC_OFFSET)
+#define SW_API_PT_BC_FILTER_GET (11 + SW_API_MISC_OFFSET)
+#define SW_API_CPU_PORT_STATUS_SET (12 + SW_API_MISC_OFFSET)
+#define SW_API_CPU_PORT_STATUS_GET (13 + SW_API_MISC_OFFSET)
+#define SW_API_BC_TO_CPU_PORT_SET (14 + SW_API_MISC_OFFSET)
+#define SW_API_BC_TO_CPU_PORT_GET (15 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_CMD_SET (16 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_CMD_GET (17 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_STATUS_SET (18 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_STATUS_GET (19 + SW_API_MISC_OFFSET)
+#define SW_API_PT_DHCP_SET (20 + SW_API_MISC_OFFSET)
+#define SW_API_PT_DHCP_GET (21 + SW_API_MISC_OFFSET)
+#define SW_API_ARP_CMD_SET (22 + SW_API_MISC_OFFSET)
+#define SW_API_ARP_CMD_GET (23 + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_CMD_SET (24 + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_CMD_GET (25 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ADD (26 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_DEL (27 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_GET (28 + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_STATUS_SET (29 + SW_API_MISC_OFFSET)
+#define SW_API_EAPOL_STATUS_GET (30 + SW_API_MISC_OFFSET)
+#define SW_API_RIPV1_STATUS_SET (31 + SW_API_MISC_OFFSET)
+#define SW_API_RIPV1_STATUS_GET (32 + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_REQ_STATUS_SET (33 + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_REQ_STATUS_GET (34 + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_ACK_STATUS_SET (35 + SW_API_MISC_OFFSET)
+#define SW_API_PT_ARP_ACK_STATUS_GET (36 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_ADD (37 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_DEL (38 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_TABLE_GET (39 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ID_SET (40 + SW_API_MISC_OFFSET)
+#define SW_API_PPPOE_SESSION_ID_GET (41 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_SET (42 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_GET (43 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_GET (44 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_CLEAR (45 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_MASK_SET (46 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_MASK_GET (47 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_PORT_LINK_STATUS_GET (48 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_MAC_LINKCHG_SET (49 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_MASK_MAC_LINKCHG_GET (50 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_MAC_LINKCHG_GET (51 + SW_API_MISC_OFFSET)
+#define SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR (52 + SW_API_MISC_OFFSET)
+#define SW_API_CPU_VID_EN_SET (53 + SW_API_MISC_OFFSET)
+#define SW_API_CPU_VID_EN_GET (54 + SW_API_MISC_OFFSET)
+#define SW_API_RTD_PPPOE_EN_SET (55 + SW_API_MISC_OFFSET)
+#define SW_API_RTD_PPPOE_EN_GET (56 + SW_API_MISC_OFFSET)
+
+
+ /*led*/
+#define SW_API_LED_OFFSET 1300
+#define SW_API_LED_PATTERN_SET (0 + SW_API_LED_OFFSET)
+#define SW_API_LED_PATTERN_GET (1 + SW_API_LED_OFFSET)
+
+ /* cosmap */
+#define SW_API_COSMAP_OFFSET 1400
+#define SW_API_COSMAP_UP_QU_SET (0 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_QU_GET (1 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_QU_SET (2 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_QU_GET (3 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_PRI_SET (4 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_PRI_GET (5 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_DP_SET (6 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_DSCP_TO_DP_GET (7 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_PRI_SET (8 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_PRI_GET (9 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_DP_SET (10 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_UP_TO_DP_GET (11 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_QU_SET (12 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_QU_GET (13 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_EHQU_SET (14 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_PRI_TO_EHQU_GET (15 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_EG_REMARK_SET (16 + SW_API_COSMAP_OFFSET)
+#define SW_API_COSMAP_EG_REMARK_GET (17 + SW_API_COSMAP_OFFSET)
+
+ /* sec */
+#define SW_API_SEC_OFFSET 1500
+#define SW_API_SEC_NORM_SET (0 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_NORM_GET (1 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_MAC_SET (2 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_MAC_GET (3 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP_SET (4 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP_GET (5 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP4_SET (6 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP4_GET (7 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP6_SET (8 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_IP6_GET (9 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_TCP_SET (10 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_TCP_GET (11 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_UDP_SET (12 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_UDP_GET (13 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP4_SET (14 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP4_GET (15 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP6_SET (16 + SW_API_SEC_OFFSET)
+#define SW_API_SEC_ICMP6_GET (17 + SW_API_SEC_OFFSET)
+
+ /* ip */
+#define SW_API_IP_OFFSET 1600
+#define SW_API_IP_HOST_ADD (0 + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_DEL (1 + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_GET (2 + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_NEXT (3 + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_COUNTER_BIND (4 + SW_API_IP_OFFSET)
+#define SW_API_IP_HOST_PPPOE_BIND (5 + SW_API_IP_OFFSET)
+#define SW_API_IP_PT_ARP_LEARN_SET (6 + SW_API_IP_OFFSET)
+#define SW_API_IP_PT_ARP_LEARN_GET (7 + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_LEARN_SET (8 + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_LEARN_GET (9 + SW_API_IP_OFFSET)
+#define SW_API_IP_SOURCE_GUARD_SET (10 + SW_API_IP_OFFSET)
+#define SW_API_IP_SOURCE_GUARD_GET (11 + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_GUARD_SET (12 + SW_API_IP_OFFSET)
+#define SW_API_IP_ARP_GUARD_GET (13 + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_STATUS_SET (14 + SW_API_IP_OFFSET)
+#define SW_API_IP_ROUTE_STATUS_GET (15 + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_ADD (16 + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_DEL (17 + SW_API_IP_OFFSET)
+#define SW_API_IP_INTF_ENTRY_NEXT (18 + SW_API_IP_OFFSET)
+#define SW_API_IP_UNK_SOURCE_CMD_SET (19 + SW_API_IP_OFFSET)
+#define SW_API_IP_UNK_SOURCE_CMD_GET (20 + SW_API_IP_OFFSET)
+#define SW_API_ARP_UNK_SOURCE_CMD_SET (21 + SW_API_IP_OFFSET)
+#define SW_API_ARP_UNK_SOURCE_CMD_GET (22 + SW_API_IP_OFFSET)
+#define SW_API_IP_AGE_TIME_SET (23 + SW_API_IP_OFFSET)
+#define SW_API_IP_AGE_TIME_GET (24 + SW_API_IP_OFFSET)
+#define SW_API_WCMP_HASH_MODE_SET (25 + SW_API_IP_OFFSET)
+#define SW_API_WCMP_HASH_MODE_GET (26 + SW_API_IP_OFFSET)
+
+ /* nat */
+#define SW_API_NAT_OFFSET 1700
+#define SW_API_NAT_ADD (0 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_DEL (1 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_GET (2 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_NEXT (3 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_COUNTER_BIND (4 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_ADD (5 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_DEL (6 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_GET (7 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_NEXT (8 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_COUNTER_BIND (9 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_STATUS_SET (10 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_STATUS_GET (11 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_HASH_MODE_SET (12 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_HASH_MODE_GET (13 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_STATUS_SET (14 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_STATUS_GET (15 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_MODE_SET (16 + SW_API_NAT_OFFSET)
+#define SW_API_NAPT_MODE_GET (17 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_ADDR_SET (18 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_ADDR_GET (19 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_ADDR_MODE_SET (20 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_ADDR_MODE_GET (21 + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_ADD (22 + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_DEL (23 + SW_API_NAT_OFFSET)
+#define SW_API_PUB_ADDR_ENTRY_NEXT (24 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_UNK_SESSION_CMD_SET (25 + SW_API_NAT_OFFSET)
+#define SW_API_NAT_UNK_SESSION_CMD_GET (26 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_MASK_SET (27 + SW_API_NAT_OFFSET)
+#define SW_API_PRV_BASE_MASK_GET (28 + SW_API_NAT_OFFSET)
+
+ /* trunk */
+#define SW_API_TRUNK_OFFSET 1800
+#define SW_API_TRUNK_GROUP_SET (0 + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_GROUP_GET (1 + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_HASH_SET (2 + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_HASH_GET (3 + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_MAN_SA_SET (4 + SW_API_TRUNK_OFFSET)
+#define SW_API_TRUNK_MAN_SA_GET (5 + SW_API_TRUNK_OFFSET)
+
+ /* Interface Control */
+#define SW_API_INTERFACE_OFFSET 1900
+#define SW_API_MAC_MODE_SET (0 + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC_MODE_GET (1 + SW_API_INTERFACE_OFFSET)
+#define SW_API_PORT_3AZ_STATUS_SET (2 + SW_API_INTERFACE_OFFSET)
+#define SW_API_PORT_3AZ_STATUS_GET (3 + SW_API_INTERFACE_OFFSET)
+#define SW_API_PHY_MODE_SET (4 + SW_API_INTERFACE_OFFSET)
+#define SW_API_PHY_MODE_GET (5 + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_CTRL_SET (6 + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_CTRL_GET (7 + SW_API_INTERFACE_OFFSET)
+#define SW_API_FX100_STATUS_GET (8 + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC06_EXCH_SET (9 + SW_API_INTERFACE_OFFSET)
+#define SW_API_MAC06_EXCH_GET (10 + SW_API_INTERFACE_OFFSET)
+
+ /*debug*/
+#define SW_API_DEBUG_OFFSET 10000
+#define SW_API_PHY_GET (0 + SW_API_DEBUG_OFFSET)
+#define SW_API_PHY_SET (1 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_GET (2 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_SET (3 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_ENTRY_GET (4 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_ENTRY_SET (5 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_FIELD_GET (6 + SW_API_DEBUG_OFFSET)
+#define SW_API_REG_FIELD_SET (7 + SW_API_DEBUG_OFFSET)
+
+
+#define SW_API_MAX 0xffff
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SW_IOCTL_H_ */
diff --git a/include/common/aos_head.h b/include/common/aos_head.h
new file mode 100644
index 0000000..675aba0
--- /dev/null
+++ b/include/common/aos_head.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sal/os/aos_mem.h"
+#include "sal/os/aos_timer.h"
+#include "sal/os/aos_lock.h"
+#include "sal/os/aos_types.h"
+
diff --git a/include/common/shared_func.h b/include/common/shared_func.h
new file mode 100644
index 0000000..09644eb
--- /dev/null
+++ b/include/common/shared_func.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SHARED_FUNC_H
+#define _SHARED_FUNC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define SW_RTN_ON_ERROR(rtn) \
+ do { if (rtn != SW_OK) return(rtn); } while(0);
+
+#define SW_OUT_ON_ERROR(rtn) \
+ do { \
+ if (rtn != SW_OK) { \
+ rv = rtn; \
+ goto out;\
+ } \
+ } while(0);
+
+#define SW_RTN_ON_ERROR_EXCEPT_COND1(rtn, cond1) \
+ do { \
+ if ((rtn != SW_OK) && (rtn != cond1)) \
+ return rtn; \
+ }while(0);
+
+#define SW_RTN_ON_NULL(op) \
+ do { \
+ if ((op) == NULL) \
+ return SW_NOT_INITIALIZED;\
+ }while(0);
+
+ /* register functions */
+#define SW_BIT_MASK_U32(nr) (~(0xFFFFFFFF << (nr)))
+
+#define SW_FIELD_MASK_U32(offset, len) \
+ ((SW_BIT_MASK_U32(len) << (offset)))
+
+#define SW_FIELD_MASK_NOT_U32(offset,len) \
+ (~(SW_BIT_MASK_U32(len) << (offset)))
+
+#define SW_FIELD_2_REG(field_val, bit_offset) \
+ (field_val << (bit_offset) )
+
+#define SW_REG_2_FIELD(reg_val, bit_offset, field_len) \
+ (((reg_val) >> (bit_offset)) & ((1 << (field_len)) - 1))
+
+#define SW_REG_SET_BY_FIELD_U32(reg_value, field_value, bit_offset, field_len)\
+ do { \
+ (reg_value) = \
+ (((reg_value) & SW_FIELD_MASK_NOT_U32((bit_offset),(field_len))) \
+ | (((field_value) & SW_BIT_MASK_U32(field_len)) << (bit_offset)));\
+ } while (0)
+
+#define SW_FIELD_GET_BY_REG_U32(reg_value, field_value, bit_offset, field_len)\
+ do { \
+ (field_value) = \
+ (((reg_value) >> (bit_offset)) & SW_BIT_MASK_U32(field_len)); \
+ } while (0)
+
+#define SW_SWAP_BITS_U8(x) \
+ ((((x)&0x80)>>7) | (((x)&0x40)>>5) | (((x)&0x20)>>3) | (((x)&0x10)>>1) \
+ |(((x)&0x1)<<7) | (((x)&0x2)<<5) | (((x)&0x4)<<3) |(((x)&0x8)<<1) )
+
+
+#define SW_OFFSET_U8_2_U16(byte_offset) ((byte_offset) >> 1)
+
+#define SW_OFFSET_U16_2_U8(word16_offset) ((word16_offset) << 1)
+
+#define SW_OFFSET_BIT_2_U8_ALIGN16(bit_offset) (((bit_offset) / 16) * 2)
+
+#define SW_SET_REG_BY_FIELD(reg, field, field_value, reg_value) \
+ SW_REG_SET_BY_FIELD_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+#define SW_GET_FIELD_BY_REG(reg, field, field_value, reg_value) \
+ SW_FIELD_GET_BY_REG_U32(reg_value, field_value, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+ /* port bitmap functions */
+#define SW_IS_PBMP_MEMBER(pbm, port) ((pbm & (1 << port)) ? A_TRUE: A_FALSE)
+#define SW_IS_PBMP_EQ(pbm0, pbm1) ((pbm0 == pbm1) ? A_TRUE: A_FALSE)
+
+#define SW_PBMP_AND(pbm0, pbm1) ((pbm0) &= (pbm1))
+#define SW_PBMP_OR(pbm0, pbm1) ((pbm0) |= (pbm1))
+#define SW_IS_PBMP_INCLUDE(pbm0, pbm1) \
+ ((pbm1 == SW_PBMP_AND(pbm0, pbm1)) ? A_TRUE: A_FALSE)
+
+#define SW_PBMP_CLEAR(pbm) ((pbm) = 0)
+#define SW_PBMP_ADD_PORT(pbm, port) ((pbm) |= (1U << (port)))
+#define SW_PBMP_DEL_PORT(pbm,port) ((pbm) &= ~(1U << (port)))
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHARED_FUNC_H */
diff --git a/include/common/sw.h b/include/common/sw.h
new file mode 100644
index 0000000..3662d4a
--- /dev/null
+++ b/include/common/sw.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_H_
+#define _SW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw_config.h"
+#include "common/aos_head.h"
+#include "common/sw_error.h"
+#include "common/shared_func.h"
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SW_H_ */
+
diff --git a/include/common/sw_config.h b/include/common/sw_config.h
new file mode 100644
index 0000000..d8fb8a6
--- /dev/null
+++ b/include/common/sw_config.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_CONFIG_H
+#define _SW_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define SW_MAX_NR_DEV 1
+#define SW_MAX_NR_PORT 32
+
+#ifdef HSL_STANDALONG
+#define HSL_LOCAL
+#else
+#define HSL_LOCAL static
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/include/common/sw_error.h b/include/common/sw_error.h
new file mode 100644
index 0000000..47e7695
--- /dev/null
+++ b/include/common/sw_error.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_ERROR_H
+#define _SW_ERROR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ typedef enum {
+ SW_OK = 0, /* Operation succeeded */
+ SW_FAIL = -1, /* Operation failed */
+ SW_BAD_VALUE = -2, /* Illegal value */
+ SW_OUT_OF_RANGE = -3, /* Value is out of range */
+ SW_BAD_PARAM = -4, /* Illegal parameter(s) */
+ SW_BAD_PTR = -5, /* Illegal pointer value */
+ SW_BAD_LEN = -6, /* Wrong length */
+ SW_BAD_STATE = -7, /* Wrong state of state machine */
+ SW_READ_ERROR = -8, /* Read operation failed */
+ SW_WRITE_ERROR = -9, /* Write operation failed */
+ SW_CREATE_ERROR = -10, /* Fail in creating an entry */
+ SW_DELETE_ERROR = -11, /* Fail in deleteing an entry */
+ SW_NOT_FOUND = -12, /* Entry not found */
+ SW_NO_CHANGE = -13, /* The parameter(s) is the same */
+ SW_NO_MORE = -14, /* No more entry found */
+ SW_NO_SUCH = -15, /* No such entry */
+ SW_ALREADY_EXIST = -16, /* Tried to create existing entry */
+ SW_FULL = -17, /* Table is full */
+ SW_EMPTY = -18, /* Table is empty */
+ SW_NOT_SUPPORTED = -19, /* This request is not support */
+ SW_NOT_IMPLEMENTED = -20, /* This request is not implemented */
+ SW_NOT_INITIALIZED = -21, /* The item is not initialized */
+ SW_BUSY = -22, /* Operation is still running */
+ SW_TIMEOUT = -23, /* Operation Time Out */
+ SW_DISABLE = -24, /* Operation is disabled */
+ SW_NO_RESOURCE = -25, /* Resource not available (memory ...) */
+ SW_INIT_ERROR = -26, /* Error occured while INIT process */
+ SW_NOT_READY = -27, /* The other side is not ready yet */
+ SW_OUT_OF_MEM = -28, /* Cpu memory allocation failed. */
+ SW_ABORTED = -29 /* Operation has been aborted. */
+ } sw_error_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_ERROR_H */
+
diff --git a/include/common/util.h b/include/common/util.h
new file mode 100644
index 0000000..e0a7246
--- /dev/null
+++ b/include/common/util.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _UTIL_H_
+#define _UTIL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define LL_IN_ORDER 0x1
+#define LL_FIX_NDNR 0x2
+
+ typedef enum {
+ LL_CMP_EQUAL = 0,
+ LL_CMP_GREATER = 1,
+ LL_CMP_SMALLER = 2
+ }
+ ll_cmp_rslt_t;
+
+ typedef ll_cmp_rslt_t(*ll_nd_cmp) (void *src, void *dest);
+
+ typedef void (*ll_nd_dump) (void *data);
+
+ typedef struct _sll_node_t
+ {
+ struct _sll_node_t *next;
+ void *data;
+ } sll_node_t;
+
+ typedef struct
+ {
+ sll_node_t *fst_nd;
+ a_uint32_t nd_nr;
+ a_uint32_t flag;
+ ll_nd_cmp nd_cmp;
+ ll_nd_dump nd_dump;
+ sll_node_t *free_nd;
+ } sll_head_t;
+
+ sll_head_t *sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func,
+ a_uint32_t flag, a_uint32_t nd_nr);
+
+ void sll_destroy(sll_head_t * sll);
+
+ void sll_lock(sll_head_t * sll);
+
+ void sll_unlock(sll_head_t * sll);
+
+ void *sll_nd_find(const sll_head_t * sll, void *data,
+ a_uint32_t * iterator);
+
+ void *sll_nd_next(const sll_head_t * sll, a_uint32_t * iterator);
+
+ sw_error_t sll_nd_insert(sll_head_t * sll, void *data);
+
+ sw_error_t sll_nd_delete(sll_head_t * sll, void *data);
+
+ typedef struct
+ {
+ a_uint32_t id_ptr;
+ a_uint32_t id_nr;
+ a_uint32_t id_min;
+ a_uint32_t id_size;
+ void *id_pool;
+ } sid_pool_t;
+
+ sid_pool_t *sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id);
+
+ void sid_pool_destroy(sid_pool_t * pool);
+
+ sw_error_t sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id);
+
+ sw_error_t sid_pool_id_free(sid_pool_t * pool, a_uint32_t id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _UTIL_H_ */
diff --git a/include/fal/fal.h b/include/fal/fal.h
new file mode 100644
index 0000000..df08169
--- /dev/null
+++ b/include/fal/fal.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _FAL_H
+#define _FAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal_misc.h"
+#include "fal_port_ctrl.h"
+#include "fal_vlan.h"
+#include "fal_fdb.h"
+#include "fal_portvlan.h"
+#include "fal_qos.h"
+#include "fal_stp.h"
+#include "fal_rate.h"
+#include "fal_mirror.h"
+#include "fal_leaky.h"
+#include "fal_igmp.h"
+#include "fal_mib.h"
+#include "fal_acl.h"
+#include "fal_led.h"
+#include "fal_reg_access.h"
+#include "fal_init.h"
+#include "fal_cosmap.h"
+#include "fal_ip.h"
+#include "fal_nat.h"
+#include "fal_sec.h"
+#include "fal_trunk.h"
+#include "fal_interface_ctrl.h"
+#include "fal_fdb.h"
+#include "fal_multi.h"
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_H */
diff --git a/include/fal/fal_acl.h b/include/fal/fal_acl.h
new file mode 100644
index 0000000..277cfc7
--- /dev/null
+++ b/include/fal/fal_acl.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_acl FAL_ACL
+ * @{
+ */
+#ifndef _FAL_ACL_H_
+#define _FAL_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+ /**
+ @brief This enum defines the ACL rule type.
+ */
+ typedef enum {
+ FAL_ACL_RULE_MAC = 0, /**< include MAC, udf fields*/
+ FAL_ACL_RULE_IP4, /**< include MAC, IP4 and Tcp/Udp udf fields*/
+ FAL_ACL_RULE_IP6, /**< include MAC, IP6 and Tcp/Udp udf fields*/
+ FAL_ACL_RULE_UDF, /**< only include user defined fields*/
+ FAL_ACL_RULE_BUTT,
+ }
+ fal_acl_rule_type_t;
+
+
+ /**
+ @brief This enum defines the ACL field operation type.
+ */
+ typedef enum
+ {
+ FAL_ACL_FIELD_MASK = 0, /**< match operation is mask*/
+ FAL_ACL_FIELD_RANGE, /**< match operation is range*/
+ FAL_ACL_FIELD_LE, /**< match operation is less and equal*/
+ FAL_ACL_FIELD_GE, /**< match operation is great and equal*/
+ FAL_ACL_FIELD_NE, /**<- match operation is not equal*/
+ FAL_ACL_FIELD_OP_BUTT,
+ } fal_acl_field_op_t;
+
+
+ typedef enum
+ {
+ FAL_ACL_POLICY_ROUTE = 0,
+ FAL_ACL_POLICY_SNAT,
+ FAL_ACL_POLICY_DNAT,
+ FAL_ACL_POLICY_RESERVE,
+ } fal_policy_forward_t;
+
+ typedef enum
+ {
+ FAL_ACL_COMBINED_NONE = 0,
+ FAL_ACL_COMBINED_START,
+ FAL_ACL_COMBINED_CONTINUE,
+ FAL_ACL_COMBINED_END,
+ } fal_combined_t;
+
+ /**
+ @brief This enum defines the ACL field operation type.
+ */
+ typedef enum
+ {
+ FAL_ACL_UDF_TYPE_L2 = 0, /**< */
+ FAL_ACL_UDF_TYPE_L3, /**< */
+ FAL_ACL_UDF_TYPE_L4, /**< */
+ FAL_ACL_UDF_TYPE_L2_SNAP, /**< */
+ FAL_ACL_UDF_TYPE_L3_PLUS, /**< */
+ FAL_ACL_UDF_TYPE_BUTT,
+ } fal_acl_udf_type_t;
+
+#define FAL_ACL_FIELD_MAC_DA 0
+#define FAL_ACL_FIELD_MAC_SA 1
+#define FAL_ACL_FIELD_MAC_ETHTYPE 2
+#define FAL_ACL_FIELD_MAC_TAGGED 3
+#define FAL_ACL_FIELD_MAC_UP 4
+#define FAL_ACL_FIELD_MAC_VID 5
+#define FAL_ACL_FIELD_IP4_SIP 6
+#define FAL_ACL_FIELD_IP4_DIP 7
+#define FAL_ACL_FIELD_IP6_LABEL 8
+#define FAL_ACL_FIELD_IP6_SIP 9
+#define FAL_ACL_FIELD_IP6_DIP 10
+#define FAL_ACL_FIELD_IP_PROTO 11
+#define FAL_ACL_FIELD_IP_DSCP 12
+#define FAL_ACL_FIELD_L4_SPORT 13
+#define FAL_ACL_FIELD_L4_DPORT 14
+#define FAL_ACL_FIELD_UDF 15
+#define FAL_ACL_FIELD_MAC_CFI 16
+#define FAL_ACL_FIELD_ICMP_TYPE 17
+#define FAL_ACL_FIELD_ICMP_CODE 18
+#define FAL_ACL_FIELD_TCP_FLAG 19
+#define FAL_ACL_FIELD_RIPV1 20
+#define FAL_ACL_FIELD_DHCPV4 21
+#define FAL_ACL_FIELD_DHCPV6 22
+#define FAL_ACL_FIELD_MAC_STAG_VID 23
+#define FAL_ACL_FIELD_MAC_STAG_PRI 24
+#define FAL_ACL_FIELD_MAC_STAG_DEI 25
+#define FAL_ACL_FIELD_MAC_STAGGED 26
+#define FAL_ACL_FIELD_MAC_CTAG_VID 27
+#define FAL_ACL_FIELD_MAC_CTAG_PRI 28
+#define FAL_ACL_FIELD_MAC_CTAG_CFI 29
+#define FAL_ACL_FIELD_MAC_CTAGGED 30
+#define FAL_ACL_FIELD_INVERSE_ALL 31
+
+
+#define FAL_ACL_ACTION_PERMIT 0
+#define FAL_ACL_ACTION_DENY 1
+#define FAL_ACL_ACTION_REDPT 2
+#define FAL_ACL_ACTION_RDTCPU 3
+#define FAL_ACL_ACTION_CPYCPU 4
+#define FAL_ACL_ACTION_MIRROR 5
+#define FAL_ACL_ACTION_MODIFY_VLAN 6
+#define FAL_ACL_ACTION_NEST_VLAN 7
+#define FAL_ACL_ACTION_REMARK_UP 8
+#define FAL_ACL_ACTION_REMARK_QUEUE 9
+#define FAL_ACL_ACTION_REMARK_STAG_VID 10
+#define FAL_ACL_ACTION_REMARK_STAG_PRI 11
+#define FAL_ACL_ACTION_REMARK_STAG_DEI 12
+#define FAL_ACL_ACTION_REMARK_CTAG_VID 13
+#define FAL_ACL_ACTION_REMARK_CTAG_PRI 14
+#define FAL_ACL_ACTION_REMARK_CTAG_CFI 15
+#define FAL_ACL_ACTION_REMARK_LOOKUP_VID 16
+#define FAL_ACL_ACTION_REMARK_DSCP 17
+#define FAL_ACL_ACTION_POLICER_EN 18
+#define FAL_ACL_ACTION_WCMP_EN 19
+#define FAL_ACL_ACTION_ARP_EN 20
+#define FAL_ACL_ACTION_POLICY_FORWARD_EN 21
+#define FAL_ACL_ACTION_BYPASS_EGRESS_TRANS 22
+#define FAL_ACL_ACTION_MATCH_TRIGGER_INTR 23
+
+
+
+ /**
+ * @brief This type defines the action in Acl rule.
+ * @details Comments:
+ * It's a bit map type, we can access it through macro FAL_ACTION_FLG_SET,
+ * FAL_ACTION_FLG_CLR and FAL_ACTION_FLG_TST.
+ */
+ typedef a_uint32_t fal_acl_action_map_t;
+
+#define FAL_ACTION_FLG_SET(flag, action) \
+ (flag) |= (0x1UL << (action))
+
+#define FAL_ACTION_FLG_CLR(flag, action) \
+ (flag) &= (~(0x1UL << (action)))
+
+#define FAL_ACTION_FLG_TST(flag, action) \
+ ((flag) & (0x1UL << (action))) ? 1 : 0
+
+
+ /**
+ * @brief This type defines the field in Acl rule.
+ * @details Comments:
+ * It's a bit map type, we can access it through macro FAL_FIELD_FLG_SET,
+ * FAL_FIELD_FLG_CLR and FAL_FIELD_FLG_TST.
+ */
+ typedef a_uint32_t fal_acl_field_map_t[2];
+
+#define FAL_FIELD_FLG_SET(flag, field) \
+ (flag[(field) / 32]) |= (0x1UL << ((field) % 32))
+
+#define FAL_FIELD_FLG_CLR(flag, field) \
+ (flag[(field) / 32]) &= (~(0x1UL << ((field) % 32)))
+
+#define FAL_FIELD_FLG_TST(flag, field) \
+ ((flag[(field) / 32]) & (0x1UL << ((field) % 32))) ? 1 : 0
+
+#define FAL_ACL_UDF_MAX_LENGTH 16
+
+ /**
+ * @brief This structure defines the Acl rule.
+ * @details Fields description:
+ *
+ *
+ * vid_val - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field value.
+ * If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field low value. If
+ * vid_op equals other value it's the compared value.
+ *
+ * vid_mask - If vid_op equals FAL_ACL_FIELD_MASK it's vlan id field mask.
+ * If vid_op equals FAL_ACL_FIELD_RANGE it's vlan id field high value. If vid_op
+ * equals other value it's meaningless.
+ *
+ *
+ * ip_dscp_val - It's eight bits field we can set any value between 0 - 255.
+ * ip_dscp_mask - It's eight bits field we can set any value between 0 - 255.
+ *
+ *
+ * src_l4port_val - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+ * source port field value. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
+ * layer four source port field low value. If src_l4port_op equals other value
+ * it's the compared value.
+ *
+ *
+ * src_l4port_mask - If src_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+ * source port field mask. If src_l4port_op equals FAL_ACL_FIELD_RANGE it's
+ * layer four source port field high value. If src_l4port_op equals other value
+ * it's meaningless.
+ *
+ *
+ * dest_l4port_val - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+ * destination port field value. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
+ * layer four source port field low value. If dest_l4port_op equals other value
+ * it's the compared value.
+ *
+ *
+ * dest_l4port_mask - If dest_l4port_op equals FAL_ACL_FIELD_MASK it's layer four
+ * source port field mask. If dest_l4port_op equals FAL_ACL_FIELD_RANGE it's
+ * layer four source port field high value. If dest_l4port_op equals other value
+ * it's meaningless.
+ *
+ *
+ * ports - If FAL_ACL_ACTION_REDPT bit is setted in action_flg it's redirect
+ * destination ports.
+ *
+ *
+ * dot1p - If FAL_ACL_ACTION_REMARK_DOT1P bit is setted in action_flg it's
+ * the expected dot1p value.
+ *
+ *
+ * queue - If FAL_ACL_ACTION_REMARK_QUEUE bit is setted in action_flg it's
+ * the expected queue value.
+ *
+ *
+ * vid - If FAL_ACL_ACTION_MODIFY_VLAN or FAL_ACL_ACTION_NEST_VLAN bit is
+ * setted in action_flg it's the expected vlan id value.
+ */
+ typedef struct
+ {
+ fal_acl_rule_type_t rule_type;
+ fal_acl_field_map_t field_flg;
+
+ /* fields of mac rule */
+ fal_mac_addr_t src_mac_val;
+ fal_mac_addr_t src_mac_mask;
+ fal_mac_addr_t dest_mac_val;
+ fal_mac_addr_t dest_mac_mask;
+ a_uint16_t ethtype_val;
+ a_uint16_t ethtype_mask;
+ a_uint16_t vid_val;
+ a_uint16_t vid_mask;
+ fal_acl_field_op_t vid_op;
+ a_uint8_t tagged_val;
+ a_uint8_t tagged_mask;
+ a_uint8_t up_val;
+ a_uint8_t up_mask;
+ a_uint8_t cfi_val;
+ a_uint8_t cfi_mask;
+ a_uint16_t resv0;
+
+ /* fields of enhanced mac rule*/
+ a_uint8_t stagged_val;
+ a_uint8_t stagged_mask;
+ a_uint8_t ctagged_val;
+ a_uint8_t ctagged_mask;
+ a_uint16_t stag_vid_val;
+ a_uint16_t stag_vid_mask;
+ fal_acl_field_op_t stag_vid_op;
+ a_uint16_t ctag_vid_val;
+ a_uint16_t ctag_vid_mask;
+ fal_acl_field_op_t ctag_vid_op;
+ a_uint8_t stag_pri_val;
+ a_uint8_t stag_pri_mask;
+ a_uint8_t ctag_pri_val;
+ a_uint8_t ctag_pri_mask;
+ a_uint8_t stag_dei_val;
+ a_uint8_t stag_dei_mask;
+ a_uint8_t ctag_cfi_val;
+ a_uint8_t ctag_cfi_mask;
+
+
+ /* fields of ip4 rule */
+ fal_ip4_addr_t src_ip4_val;
+ fal_ip4_addr_t src_ip4_mask;
+ fal_ip4_addr_t dest_ip4_val;
+ fal_ip4_addr_t dest_ip4_mask;
+
+ /* fields of ip6 rule */
+ a_uint32_t ip6_lable_val;
+ a_uint32_t ip6_lable_mask;
+ fal_ip6_addr_t src_ip6_val;
+ fal_ip6_addr_t src_ip6_mask;
+ fal_ip6_addr_t dest_ip6_val;
+ fal_ip6_addr_t dest_ip6_mask;
+
+ /* fields of ip rule */
+ a_uint8_t ip_proto_val;
+ a_uint8_t ip_proto_mask;
+ a_uint8_t ip_dscp_val;
+ a_uint8_t ip_dscp_mask;
+
+ /* fields of layer four */
+ a_uint16_t src_l4port_val;
+ a_uint16_t src_l4port_mask;
+ fal_acl_field_op_t src_l4port_op;
+ a_uint16_t dest_l4port_val;
+ a_uint16_t dest_l4port_mask;
+ fal_acl_field_op_t dest_l4port_op;
+ a_uint8_t icmp_type_val;
+ a_uint8_t icmp_type_mask;
+ a_uint8_t icmp_code_val;
+ a_uint8_t icmp_code_mask;
+ a_uint8_t tcp_flag_val;
+ a_uint8_t tcp_flag_mask;
+ a_uint8_t ripv1_val;
+ a_uint8_t ripv1_mask;
+ a_uint8_t dhcpv4_val;
+ a_uint8_t dhcpv4_mask;
+ a_uint8_t dhcpv6_val;
+ a_uint8_t dhcpv6_mask;
+
+ /* user defined fields */
+ fal_acl_udf_type_t udf_type;
+ a_uint8_t udf_offset;
+ a_uint8_t udf_len;
+ a_uint8_t udf_val[FAL_ACL_UDF_MAX_LENGTH];
+ a_uint8_t udf_mask[FAL_ACL_UDF_MAX_LENGTH];
+
+ /* fields of action */
+ fal_acl_action_map_t action_flg;
+ fal_pbmp_t ports;
+ a_uint32_t match_cnt;
+ a_uint16_t vid;
+ a_uint8_t up;
+ a_uint8_t queue;
+ a_uint16_t stag_vid;
+ a_uint8_t stag_pri;
+ a_uint8_t stag_dei;
+ a_uint16_t ctag_vid;
+ a_uint8_t ctag_pri;
+ a_uint8_t ctag_cfi;
+ a_uint16_t policer_ptr;
+ a_uint16_t arp_ptr;
+ a_uint16_t wcmp_ptr;
+ a_uint8_t dscp;
+ a_uint8_t rsv;
+ fal_policy_forward_t policy_fwd;
+ fal_combined_t combined;
+ } fal_acl_rule_t;
+
+
+ /**
+ @brief This enum defines the ACL will work on which derection traffic.
+ */
+ typedef enum
+ {
+ FAL_ACL_DIREC_IN = 0, /**< Acl will work on ingressive traffic */
+ FAL_ACL_DIREC_EG, /**< Acl will work on egressive traffic */
+ FAL_ACL_DIREC_BOTH, /**< Acl will work on both ingressive and egressive traffic*/
+ } fal_acl_direc_t;
+
+
+ /**
+ @brief This enum defines the ACL will work on which partiualr object.
+ */
+ typedef enum
+ {
+ FAL_ACL_BIND_PORT = 0, /**< Acl wil work on particular port */
+ } fal_acl_bind_obj_t;
+
+
+ sw_error_t
+ fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri);
+
+
+ sw_error_t
+ fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+
+
+ sw_error_t
+ fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr, fal_acl_rule_t * rule);
+
+
+ sw_error_t
+ fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr);
+
+
+ sw_error_t
+ fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ fal_acl_rule_t * rule);
+
+
+
+ sw_error_t
+ fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+ sw_error_t
+ fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+ sw_error_t
+ fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_acl_list_dump(a_uint32_t dev_id);
+
+
+ sw_error_t
+ fal_acl_rule_dump(a_uint32_t dev_id);
+
+
+ sw_error_t
+ fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t offset, a_uint32_t length);
+
+ sw_error_t
+ fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t * offset, a_uint32_t * length);
+
+ sw_error_t
+ fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ sw_error_t
+ fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ sw_error_t
+ fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable);
+
+ sw_error_t
+ fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_api.h b/include/fal/fal_api.h
new file mode 100644
index 0000000..68fa8a5
--- /dev/null
+++ b/include/fal/fal_api.h
@@ -0,0 +1,1123 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _FAL_API_H_
+#define _FAL_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, fal_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, fal_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, fal_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, fal_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, fal_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, fal_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, fal_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, fal_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, fal_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_HDR_SET, fal_port_hdr_status_set), \
+ SW_API_DEF(SW_API_PT_HDR_GET, fal_port_hdr_status_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, fal_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, fal_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, fal_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, fal_port_flowctrl_forcemode_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, fal_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, fal_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, fal_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, fal_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, fal_port_cdt), \
+ SW_API_DEF(SW_API_PT_TXHDR_SET, fal_port_txhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_TXHDR_GET, fal_port_txhdr_mode_get), \
+ SW_API_DEF(SW_API_PT_RXHDR_SET, fal_port_rxhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_RXHDR_GET, fal_port_rxhdr_mode_get), \
+ SW_API_DEF(SW_API_HEADER_TYPE_SET, fal_header_type_set), \
+ SW_API_DEF(SW_API_HEADER_TYPE_GET, fal_header_type_get), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_SET, fal_port_txmac_status_set), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_GET, fal_port_txmac_status_get), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_SET, fal_port_rxmac_status_set), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_GET, fal_port_rxmac_status_get), \
+ SW_API_DEF(SW_API_TXFC_STATUS_SET, fal_port_txfc_status_set), \
+ SW_API_DEF(SW_API_TXFC_STATUS_GET, fal_port_txfc_status_get), \
+ SW_API_DEF(SW_API_RXFC_STATUS_SET, fal_port_rxfc_status_set), \
+ SW_API_DEF(SW_API_RXFC_STATUS_GET, fal_port_rxfc_status_get), \
+ SW_API_DEF(SW_API_BP_STATUS_SET, fal_port_bp_status_set), \
+ SW_API_DEF(SW_API_BP_STATUS_GET, fal_port_bp_status_get), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_SET, fal_port_link_forcemode_set), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_GET, fal_port_link_forcemode_get), \
+ SW_API_DEF(SW_API_PT_LINK_STATUS_GET, fal_port_link_status_get), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, fal_port_mac_loopback_set), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, fal_port_mac_loopback_get),
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_HDR_SET) \
+ SW_API_DESC(SW_API_PT_HDR_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT) \
+ SW_API_DESC(SW_API_PT_TXHDR_SET) \
+ SW_API_DESC(SW_API_PT_TXHDR_GET) \
+ SW_API_DESC(SW_API_PT_RXHDR_SET) \
+ SW_API_DESC(SW_API_PT_RXHDR_GET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_BP_STATUS_SET) \
+ SW_API_DESC(SW_API_BP_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+ SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, fal_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, fal_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_MEM_UPDATE, fal_vlan_member_update), \
+ SW_API_DEF(SW_API_VLAN_FIND, fal_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, fal_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, fal_vlan_entry_append), \
+ SW_API_DEF(SW_API_VLAN_FLUSH, fal_vlan_flush), \
+ SW_API_DEF(SW_API_VLAN_FID_SET, fal_vlan_fid_set), \
+ SW_API_DEF(SW_API_VLAN_FID_GET, fal_vlan_fid_get), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_ADD, fal_vlan_member_add), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_DEL, fal_vlan_member_del), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, fal_vlan_learning_state_set), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, fal_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND) \
+ SW_API_DESC(SW_API_VLAN_FLUSH) \
+ SW_API_DESC(SW_API_VLAN_FID_SET) \
+ SW_API_DESC(SW_API_VLAN_FID_GET) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, fal_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, fal_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, fal_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, fal_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, fal_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, fal_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, fal_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, fal_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_DEF_VID_SET, fal_port_default_vid_set), \
+ SW_API_DEF(SW_API_PT_DEF_VID_GET, fal_port_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, fal_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, fal_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, fal_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, fal_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_PT_NESTVLAN_SET, fal_port_nestvlan_set), \
+ SW_API_DEF(SW_API_PT_NESTVLAN_GET, fal_port_nestvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, fal_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, fal_nestvlan_tpid_get), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, fal_port_invlan_mode_set), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, fal_port_invlan_mode_get), \
+ SW_API_DEF(SW_API_PT_TLS_SET, fal_port_tls_set), \
+ SW_API_DEF(SW_API_PT_TLS_GET, fal_port_tls_get), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, fal_port_pri_propagation_set), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, fal_port_pri_propagation_get), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_SET, fal_port_default_svid_set), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_GET, fal_port_default_svid_get), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_SET, fal_port_default_cvid_set), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_GET, fal_port_default_cvid_get), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, fal_port_vlan_propagation_set), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, fal_port_vlan_propagation_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, fal_port_vlan_trans_add), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, fal_port_vlan_trans_del), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, fal_port_vlan_trans_get), \
+ SW_API_DEF(SW_API_QINQ_MODE_SET, fal_qinq_mode_set), \
+ SW_API_DEF(SW_API_QINQ_MODE_GET, fal_qinq_mode_get), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, fal_port_qinq_role_set), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, fal_port_qinq_role_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, fal_port_vlan_trans_iterate), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, fal_port_mac_vlan_xlt_set), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, fal_port_mac_vlan_xlt_get), \
+ SW_API_DEF(SW_API_NETISOLATE_SET, fal_netisolate_set), \
+ SW_API_DEF(SW_API_NETISOLATE_GET, fal_netisolate_get), \
+ SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, fal_eg_trans_filter_bypass_en_set), \
+ SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, fal_eg_trans_filter_bypass_en_get),
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_PT_NESTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_NESTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \
+ SW_API_DESC(SW_API_PT_TLS_SET) \
+ SW_API_DESC(SW_API_PT_TLS_GET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_GET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \
+ SW_API_DESC(SW_API_QINQ_MODE_SET) \
+ SW_API_DESC(SW_API_QINQ_MODE_GET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) \
+ SW_API_DESC(SW_API_NETISOLATE_SET) \
+ SW_API_DESC(SW_API_NETISOLATE_GET) \
+ SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \
+ SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, fal_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, fal_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,fal_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, fal_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIRST, fal_fdb_first), \
+ SW_API_DEF(SW_API_FDB_NEXT, fal_fdb_next), \
+ SW_API_DEF(SW_API_FDB_FIND, fal_fdb_find), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, fal_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, fal_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, fal_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, fal_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, fal_fdb_vlan_ivl_svl_set),\
+ SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, fal_fdb_vlan_ivl_svl_get),\
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, fal_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, fal_fdb_age_time_get), \
+ SW_API_DEF(SW_API_FDB_ITERATE, fal_fdb_iterate), \
+ SW_API_DEF(SW_API_FDB_EXTEND_NEXT, fal_fdb_extend_next), \
+ SW_API_DEF(SW_API_FDB_EXTEND_FIRST, fal_fdb_extend_first), \
+ SW_API_DEF(SW_API_FDB_TRANSFER, fal_fdb_transfer), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, fal_port_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, fal_port_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, fal_port_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, fal_port_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, fal_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, fal_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, fal_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, fal_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_RESV_ADD, fal_fdb_resv_add), \
+ SW_API_DEF(SW_API_FDB_RESV_DEL, fal_fdb_resv_del), \
+ SW_API_DEF(SW_API_FDB_RESV_FIND, fal_fdb_resv_find), \
+ SW_API_DEF(SW_API_FDB_RESV_ITERATE, fal_fdb_resv_iterate), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, fal_fdb_port_learn_static_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, fal_fdb_port_learn_static_get), \
+ SW_API_DEF(SW_API_FDB_PORT_ADD, fal_fdb_port_add), \
+ SW_API_DEF(SW_API_FDB_PORT_DEL, fal_fdb_port_del),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIRST) \
+ SW_API_DESC(SW_API_FDB_NEXT) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \
+ SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_FDB_ITERATE) \
+ SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \
+ SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+ SW_API_DESC(SW_API_FDB_TRANSFER) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_RESV_ADD) \
+ SW_API_DESC(SW_API_FDB_RESV_DEL) \
+ SW_API_DESC(SW_API_FDB_RESV_FIND) \
+ SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+ SW_API_DESC(SW_API_FDB_PORT_ADD) \
+ SW_API_DESC(SW_API_FDB_PORT_DEL)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+ SW_API_DEF(SW_API_ACL_LIST_CREAT, fal_acl_list_creat), \
+ SW_API_DEF(SW_API_ACL_LIST_DESTROY, fal_acl_list_destroy), \
+ SW_API_DEF(SW_API_ACL_RULE_ADD, fal_acl_rule_add), \
+ SW_API_DEF(SW_API_ACL_RULE_DELETE, fal_acl_rule_delete), \
+ SW_API_DEF(SW_API_ACL_RULE_QUERY, fal_acl_rule_query), \
+ SW_API_DEF(SW_API_ACL_LIST_BIND, fal_acl_list_bind), \
+ SW_API_DEF(SW_API_ACL_LIST_UNBIND, fal_acl_list_unbind), \
+ SW_API_DEF(SW_API_ACL_STATUS_SET, fal_acl_status_set), \
+ SW_API_DEF(SW_API_ACL_STATUS_GET, fal_acl_status_get), \
+ SW_API_DEF(SW_API_ACL_LIST_DUMP, fal_acl_list_dump), \
+ SW_API_DEF(SW_API_ACL_RULE_DUMP, fal_acl_rule_dump), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, fal_acl_port_udf_profile_set), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, fal_acl_port_udf_profile_get), \
+ SW_API_DEF(SW_API_ACL_RULE_ACTIVE, fal_acl_rule_active), \
+ SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, fal_acl_rule_deactive),\
+ SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, fal_acl_rule_src_filter_sts_set),\
+ SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, fal_acl_rule_src_filter_sts_get),\
+
+#define ACL_API_PARAM \
+ SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+ SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+ SW_API_DESC(SW_API_ACL_RULE_ADD) \
+ SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+ SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+ SW_API_DESC(SW_API_ACL_LIST_BIND) \
+ SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+ SW_API_DESC(SW_API_ACL_STATUS_SET) \
+ SW_API_DESC(SW_API_ACL_STATUS_GET) \
+ SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+ SW_API_DESC(SW_API_ACL_RULE_DUMP) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \
+ SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \
+ SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \
+ SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET)\
+ SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)
+
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_SCH_MODE_SET, fal_qos_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_SCH_MODE_GET, fal_qos_sch_mode_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, fal_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, fal_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, fal_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, fal_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, fal_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, fal_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, fal_qos_port_red_en_set), \
+ SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, fal_qos_port_red_en_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, fal_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, fal_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, fal_qos_port_rx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, fal_qos_port_rx_buf_nr_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_SET, fal_cosmap_up_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_GET, fal_cosmap_up_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, fal_cosmap_dscp_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, fal_cosmap_dscp_queue_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, fal_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, fal_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, fal_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, fal_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, fal_qos_port_default_up_set), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, fal_qos_port_default_up_get), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, fal_qos_port_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, fal_qos_port_sch_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, fal_qos_port_default_spri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, fal_qos_port_default_spri_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, fal_qos_port_default_cpri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, fal_qos_port_default_cpri_get), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, fal_qos_port_force_spri_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, fal_qos_port_force_spri_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, fal_qos_port_force_cpri_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, fal_qos_port_force_cpri_status_get), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, fal_qos_queue_remark_table_set), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, fal_qos_queue_remark_table_get),
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RED_EN_SET)\
+ SW_API_DESC(SW_API_QOS_PT_RED_EN_GET)\
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, fal_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, fal_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, fal_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, fal_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, fal_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, fal_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, fal_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, fal_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, fal_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, fal_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, fal_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, fal_igmp_mld_entry_creat_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, fal_igmp_mld_entry_static_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, fal_igmp_mld_entry_static_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, fal_igmp_mld_entry_leaky_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, fal_igmp_mld_entry_leaky_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, fal_igmp_mld_entry_v3_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, fal_igmp_mld_entry_v3_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, fal_igmp_mld_entry_queue_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, fal_igmp_mld_entry_queue_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, fal_port_igmp_mld_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, fal_port_igmp_mld_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, fal_port_igmp_mld_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, fal_port_igmp_mld_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, fal_igmp_sg_entry_set), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, fal_igmp_sg_entry_clear), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, fal_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, fal_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, fal_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, fal_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, fal_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, fal_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, fal_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, fal_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, fal_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, fal_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, fal_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET)\
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, fal_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, fal_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, fal_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, fal_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, fal_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, fal_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_SET, fal_rate_queue_egrl_set), \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_GET, fal_rate_queue_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_SET, fal_rate_port_egrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_GET, fal_rate_port_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_SET, fal_rate_port_inrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_GET, fal_rate_port_inrl_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, fal_storm_ctrl_frame_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, fal_storm_ctrl_frame_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, fal_storm_ctrl_rate_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, fal_storm_ctrl_rate_get), \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, fal_rate_port_policer_set), \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, fal_rate_port_policer_get), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, fal_rate_port_shaper_set), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, fal_rate_port_shaper_get), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, fal_rate_queue_shaper_set), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, fal_rate_queue_shaper_get), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, fal_rate_acl_policer_set), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, fal_rate_acl_policer_get), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, fal_rate_port_add_rate_byte_set), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, fal_rate_port_add_rate_byte_get), \
+ SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, fal_rate_port_gol_flow_en_set), \
+ SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, fal_rate_port_gol_flow_en_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_GET) \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \
+ SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \
+ SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, fal_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, fal_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, fal_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, fal_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, fal_mib_status_get), \
+ SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, fal_mib_port_flush_counters), \
+ SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, fal_mib_cpukeep_set), \
+ SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, fal_mib_cpukeep_get),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \
+ SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \
+ SW_API_DESC(SW_API_MIB_CPU_KEEP_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_ARP_STATUS_SET, fal_arp_status_set), \
+ SW_API_DEF(SW_API_ARP_STATUS_GET, fal_arp_status_get), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, fal_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, fal_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, fal_port_unk_sa_cmd_set), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, fal_port_unk_sa_cmd_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, fal_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, fal_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, fal_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, fal_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_SET, fal_port_bc_filter_set), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_GET, fal_port_bc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, fal_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, fal_cpu_port_status_get), \
+ SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, fal_bc_to_cpu_port_set), \
+ SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, fal_bc_to_cpu_port_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, fal_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, fal_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, fal_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, fal_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, fal_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, fal_port_dhcp_get), \
+ SW_API_DEF(SW_API_ARP_CMD_SET, fal_arp_cmd_set), \
+ SW_API_DEF(SW_API_ARP_CMD_GET, fal_arp_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_CMD_SET, fal_eapol_cmd_set), \
+ SW_API_DEF(SW_API_EAPOL_CMD_GET, fal_eapol_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ADD, fal_pppoe_session_add), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_DEL, fal_pppoe_session_del), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_GET, fal_pppoe_session_get), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_SET, fal_eapol_status_set), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_GET, fal_eapol_status_get), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_SET, fal_ripv1_status_set), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_GET, fal_ripv1_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, fal_port_arp_req_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, fal_port_arp_req_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, fal_port_arp_ack_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, fal_port_arp_ack_status_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, fal_pppoe_session_table_add), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, fal_pppoe_session_table_del), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, fal_pppoe_session_table_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, fal_pppoe_session_id_set), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, fal_pppoe_session_id_get), \
+ SW_API_DEF(SW_API_INTR_MASK_SET, fal_intr_mask_set), \
+ SW_API_DEF(SW_API_INTR_MASK_GET, fal_intr_mask_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_GET, fal_intr_status_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_CLEAR, fal_intr_status_clear), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, fal_intr_port_link_mask_set), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, fal_intr_port_link_mask_get), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, fal_intr_port_link_status_get), \
+ SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, fal_intr_mask_mac_linkchg_set), \
+ SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, fal_intr_mask_mac_linkchg_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, fal_intr_status_mac_linkchg_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, fal_intr_status_mac_linkchg_clear), \
+ SW_API_DEF(SW_API_CPU_VID_EN_SET, fal_cpu_vid_en_set), \
+ SW_API_DEF(SW_API_CPU_VID_EN_GET, fal_cpu_vid_en_get), \
+ SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, fal_rtd_pppoe_en_set), \
+ SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, fal_rtd_pppoe_en_get),
+
+
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_ARP_STATUS_SET) \
+ SW_API_DESC(SW_API_ARP_STATUS_GET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \
+ SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET) \
+ SW_API_DESC(SW_API_ARP_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_GET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+ SW_API_DESC(SW_API_INTR_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \
+ SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \
+ SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \
+ SW_API_DESC(SW_API_CPU_VID_EN_SET) \
+ SW_API_DESC(SW_API_CPU_VID_EN_GET) \
+ SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \
+ SW_API_DESC(SW_API_RTD_PPPOE_EN_GET)
+
+
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, fal_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, fal_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, fal_cosmap_dscp_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, fal_cosmap_dscp_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, fal_cosmap_dscp_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, fal_cosmap_dscp_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, fal_cosmap_up_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, fal_cosmap_up_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, fal_cosmap_up_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, fal_cosmap_up_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, fal_cosmap_pri_to_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, fal_cosmap_pri_to_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, fal_cosmap_pri_to_ehqueue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, fal_cosmap_pri_to_ehqueue_get), \
+ SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, fal_cosmap_egress_remark_set), \
+ SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, fal_cosmap_egress_remark_get),
+
+#define COSMAP_API_PARAM \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \
+ SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \
+ SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+ SW_API_DEF(SW_API_SEC_NORM_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_NORM_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_MAC_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_MAC_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_IP_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_IP_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_IP4_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_IP4_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_IP6_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_IP6_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_TCP_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_TCP_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_UDP_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_UDP_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_ICMP4_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_ICMP4_GET, fal_sec_norm_item_get), \
+ SW_API_DEF(SW_API_SEC_ICMP6_SET, fal_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_ICMP6_GET, fal_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+ SW_API_DESC(SW_API_SEC_NORM_SET) \
+ SW_API_DESC(SW_API_SEC_NORM_GET) \
+ SW_API_DESC(SW_API_SEC_MAC_SET) \
+ SW_API_DESC(SW_API_SEC_MAC_GET) \
+ SW_API_DESC(SW_API_SEC_IP_SET) \
+ SW_API_DESC(SW_API_SEC_IP_GET) \
+ SW_API_DESC(SW_API_SEC_IP4_SET) \
+ SW_API_DESC(SW_API_SEC_IP4_GET) \
+ SW_API_DESC(SW_API_SEC_IP6_SET) \
+ SW_API_DESC(SW_API_SEC_IP6_GET) \
+ SW_API_DESC(SW_API_SEC_TCP_SET) \
+ SW_API_DESC(SW_API_SEC_TCP_GET) \
+ SW_API_DESC(SW_API_SEC_UDP_SET) \
+ SW_API_DESC(SW_API_SEC_UDP_GET) \
+ SW_API_DESC(SW_API_SEC_ICMP4_SET) \
+ SW_API_DESC(SW_API_SEC_ICMP4_GET) \
+ SW_API_DESC(SW_API_SEC_ICMP6_SET) \
+ SW_API_DESC(SW_API_SEC_ICMP6_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+ SW_API_DEF(SW_API_IP_HOST_ADD, fal_ip_host_add), \
+ SW_API_DEF(SW_API_IP_HOST_DEL, fal_ip_host_del), \
+ SW_API_DEF(SW_API_IP_HOST_GET, fal_ip_host_get), \
+ SW_API_DEF(SW_API_IP_HOST_NEXT, fal_ip_host_next), \
+ SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, fal_ip_host_counter_bind), \
+ SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, fal_ip_host_pppoe_bind), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, fal_ip_pt_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, fal_ip_pt_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_SET, fal_ip_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_GET, fal_ip_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, fal_ip_source_guard_set), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, fal_ip_source_guard_get), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_SET, fal_ip_arp_guard_set), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_GET, fal_ip_arp_guard_get), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, fal_ip_route_status_set), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, fal_ip_route_status_get), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, fal_ip_intf_entry_add), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, fal_ip_intf_entry_del), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, fal_ip_intf_entry_next), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, fal_ip_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, fal_ip_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, fal_arp_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, fal_arp_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_SET, fal_ip_age_time_set), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_GET, fal_ip_age_time_get), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, fal_ip_wcmp_hash_mode_set), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, fal_ip_wcmp_hash_mode_get),
+
+#define IP_API_PARAM \
+ SW_API_DESC(SW_API_IP_HOST_ADD) \
+ SW_API_DESC(SW_API_IP_HOST_DEL) \
+ SW_API_DESC(SW_API_IP_HOST_GET) \
+ SW_API_DESC(SW_API_IP_HOST_NEXT) \
+ SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+ SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_GET)
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+ SW_API_DEF(SW_API_NAT_ADD, fal_nat_add), \
+ SW_API_DEF(SW_API_NAT_DEL, fal_nat_del), \
+ SW_API_DEF(SW_API_NAT_GET, fal_nat_get), \
+ SW_API_DEF(SW_API_NAT_NEXT, fal_nat_next), \
+ SW_API_DEF(SW_API_NAT_COUNTER_BIND, fal_nat_counter_bind), \
+ SW_API_DEF(SW_API_NAPT_ADD, fal_napt_add), \
+ SW_API_DEF(SW_API_NAPT_DEL, fal_napt_del), \
+ SW_API_DEF(SW_API_NAPT_GET, fal_napt_get), \
+ SW_API_DEF(SW_API_NAPT_NEXT, fal_napt_next), \
+ SW_API_DEF(SW_API_NAPT_COUNTER_BIND, fal_napt_counter_bind), \
+ SW_API_DEF(SW_API_NAT_STATUS_SET, fal_nat_status_set), \
+ SW_API_DEF(SW_API_NAT_STATUS_GET, fal_nat_status_get), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_SET, fal_nat_hash_mode_set), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_GET, fal_nat_hash_mode_get), \
+ SW_API_DEF(SW_API_NAPT_STATUS_SET, fal_napt_status_set), \
+ SW_API_DEF(SW_API_NAPT_STATUS_GET, fal_napt_status_get), \
+ SW_API_DEF(SW_API_NAPT_MODE_SET, fal_napt_mode_set), \
+ SW_API_DEF(SW_API_NAPT_MODE_GET, fal_napt_mode_get), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, fal_nat_prv_base_addr_set), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, fal_nat_prv_base_addr_get), \
+ SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, fal_nat_prv_addr_mode_set), \
+ SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, fal_nat_prv_addr_mode_get), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, fal_nat_pub_addr_add), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, fal_nat_pub_addr_del), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, fal_nat_pub_addr_next), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, fal_nat_unk_session_cmd_set), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, fal_nat_unk_session_cmd_get), \
+ SW_API_DEF(SW_API_PRV_BASE_MASK_SET, fal_nat_prv_base_mask_set), \
+ SW_API_DEF(SW_API_PRV_BASE_MASK_GET, fal_nat_prv_base_mask_get),
+
+#define NAT_API_PARAM \
+ SW_API_DESC(SW_API_NAT_ADD) \
+ SW_API_DESC(SW_API_NAT_DEL) \
+ SW_API_DESC(SW_API_NAT_GET) \
+ SW_API_DESC(SW_API_NAT_NEXT) \
+ SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAPT_ADD) \
+ SW_API_DESC(SW_API_NAPT_DEL) \
+ SW_API_DESC(SW_API_NAPT_GET) \
+ SW_API_DESC(SW_API_NAPT_NEXT) \
+ SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAPT_MODE_SET) \
+ SW_API_DESC(SW_API_NAPT_MODE_GET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+ SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \
+ SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+ SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \
+ SW_API_DESC(SW_API_PRV_BASE_MASK_GET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+ SW_API_DEF(SW_API_TRUNK_GROUP_SET, fal_trunk_group_set), \
+ SW_API_DEF(SW_API_TRUNK_GROUP_GET, fal_trunk_group_get), \
+ SW_API_DEF(SW_API_TRUNK_HASH_SET, fal_trunk_hash_mode_set), \
+ SW_API_DEF(SW_API_TRUNK_HASH_GET, fal_trunk_hash_mode_get), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, fal_trunk_manipulate_sa_set), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, fal_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+ SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+ SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_SET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_GET) \
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+ SW_API_DEF(SW_API_MAC_MODE_SET, fal_interface_mac_mode_set), \
+ SW_API_DEF(SW_API_MAC_MODE_GET, fal_interface_mac_mode_get), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, fal_port_3az_status_set), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, fal_port_3az_status_get), \
+ SW_API_DEF(SW_API_PHY_MODE_SET, fal_interface_phy_mode_set), \
+ SW_API_DEF(SW_API_PHY_MODE_GET, fal_interface_phy_mode_get), \
+ SW_API_DEF(SW_API_FX100_CTRL_SET, fal_interface_fx100_ctrl_set), \
+ SW_API_DEF(SW_API_FX100_CTRL_GET, fal_interface_fx100_ctrl_get), \
+ SW_API_DEF(SW_API_FX100_STATUS_GET, fal_interface_fx100_status_get),\
+ SW_API_DEF(SW_API_MAC06_EXCH_SET, fal_interface_mac06_exch_set),\
+ SW_API_DEF(SW_API_MAC06_EXCH_GET, fal_interface_mac06_exch_get),
+
+#define INTERFACECTRL_API_PARAM \
+ SW_API_DESC(SW_API_MAC_MODE_SET) \
+ SW_API_DESC(SW_API_MAC_MODE_GET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \
+ SW_API_DESC(SW_API_PHY_MODE_SET) \
+ SW_API_DESC(SW_API_PHY_MODE_GET) \
+ SW_API_DESC(SW_API_FX100_CTRL_SET) \
+ SW_API_DESC(SW_API_FX100_CTRL_GET) \
+ SW_API_DESC(SW_API_FX100_STATUS_GET) \
+ SW_API_DESC(SW_API_MAC06_EXCH_SET) \
+ SW_API_DESC(SW_API_MAC06_EXCH_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, fal_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, fal_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, fal_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, fal_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, fal_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, fal_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, fal_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, fal_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ ACL_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ COSMAP_API \
+ SEC_API \
+ IP_API \
+ NAT_API \
+ TRUNK_API \
+ INTERFACECTRL_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ ACL_API_PARAM \
+ LED_API_PARAM \
+ COSMAP_API_PARAM \
+ SEC_API_PARAM \
+ IP_API_PARAM \
+ NAT_API_PARAM \
+ TRUNK_API_PARAM \
+ INTERFACECTRL_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _FAL_API_H_ */
diff --git a/include/fal/fal_cosmap.h b/include/fal/fal_cosmap.h
new file mode 100644
index 0000000..085d930
--- /dev/null
+++ b/include/fal/fal_cosmap.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_cosmap FAL_COSMAP
+ * @{
+ */
+#ifndef _FAL_COSMAP_H_
+#define _FAL_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ typedef struct
+ {
+ a_bool_t remark_dscp;
+ a_bool_t remark_up;
+ a_uint8_t g_dscp;
+ a_uint8_t y_dscp;
+ a_uint8_t g_up;
+ a_uint8_t y_up;
+ } fal_egress_remark_table_t;
+
+ sw_error_t
+ fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t pri);
+
+ sw_error_t
+ fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri);
+
+ sw_error_t
+ fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t dp);
+
+ sw_error_t
+ fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * dp);
+
+ sw_error_t
+ fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t pri);
+
+ sw_error_t
+ fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * pri);
+
+ sw_error_t
+ fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t dp);
+
+ sw_error_t
+ fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * dp);
+
+ sw_error_t
+ fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ sw_error_t
+ fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ sw_error_t
+ fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ sw_error_t
+ fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ sw_error_t
+ fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+ sw_error_t
+ fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/fal/fal_fdb.h b/include/fal/fal_fdb.h
new file mode 100644
index 0000000..83237b4
--- /dev/null
+++ b/include/fal/fal_fdb.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_fdb FAL_FDB
+ * @{
+ */
+#ifndef _FAL_FDB_H_
+#define _FAL_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @details Fields description:
+
+ portmap_en - If value of portmap_en is A_TRUE then port.map is valid
+ otherwise port.id is valid.
+
+
+ leaky_en - If value of leaky_en is A_TRUE then packets which
+ destination address equals addr in this entry would be leaky.
+
+
+ mirror_en - If value of mirror_en is A_TRUE then packets which
+ destination address equals addr in this entry would be mirrored.
+
+
+ clone_en - If value of clone_en is A_TRUE which means this address is
+ a mac clone address.
+ @brief This structure defines the Fdb entry.
+
+ */
+ typedef struct
+ {
+ fal_mac_addr_t addr;
+ a_uint16_t fid;
+ fal_fwd_cmd_t dacmd;
+ fal_fwd_cmd_t sacmd;
+ union
+ {
+ a_uint32_t id;
+ fal_pbmp_t map;
+ } port;
+ a_bool_t portmap_en;
+ a_bool_t is_multicast;
+ a_bool_t static_en;
+ a_bool_t leaky_en;
+ a_bool_t mirror_en;
+ a_bool_t clone_en;
+ a_bool_t cross_pt_state;
+ a_bool_t da_pri_en;
+ a_uint8_t da_queue;
+ a_bool_t white_list_en;
+ } fal_fdb_entry_t;
+
+#define FAL_FDB_DEL_STATIC 0x1
+
+ typedef struct
+ {
+ a_bool_t port_en;
+ a_bool_t fid_en;
+ a_bool_t multicast_en;
+ } fal_fdb_op_t;
+
+ typedef enum
+ {
+ INVALID_VLAN_SVL=0,
+ INVALID_VLAN_IVL
+ } fal_fdb_smode;
+
+ sw_error_t
+ fal_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+
+ sw_error_t
+ fal_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+
+ sw_error_t
+ fal_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+
+ sw_error_t
+ fal_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t *entry);
+
+
+
+ sw_error_t
+ fal_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ sw_error_t
+ fal_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ sw_error_t
+ fal_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ sw_error_t
+ fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+ sw_error_t
+ fal_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
+
+
+ sw_error_t
+ fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
+
+
+ sw_error_t
+ fal_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+
+ sw_error_t
+ fal_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+
+ sw_error_t
+ fal_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option);
+
+
+ sw_error_t
+ fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+
+ sw_error_t
+ fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+
+ sw_error_t
+ fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+
+ sw_error_t
+ fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt);
+
+
+ sw_error_t
+ fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt);
+
+
+ sw_error_t
+ fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ sw_error_t
+ fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ sw_error_t
+ fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+
+ sw_error_t
+ fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ sw_error_t
+ fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+ sw_error_t
+ fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_igmp.h b/include/fal/fal_igmp.h
new file mode 100644
index 0000000..2653e6d
--- /dev/null
+++ b/include/fal/fal_igmp.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_igmp FAL_IGMP
+ * @{
+ */
+#ifndef _FAL_IGMP_H_
+#define _FAL_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+#include "fal/fal_multi.h"
+
+
+ sw_error_t
+ fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+ sw_error_t
+ fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+ sw_error_t
+ fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+
+ sw_error_t
+ fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+
+ sw_error_t
+ fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+
+ sw_error_t
+ fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t static_en);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * static_en);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+ sw_error_t
+ fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+ sw_error_t
+ fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+
+ sw_error_t
+ fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+
+ sw_error_t
+ fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ sw_error_t
+ fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ sw_error_t
+ fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ sw_error_t
+ fal_igmp_sg_entry_show(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_IGMP_H_ */
+
+/**
+ * @}
+ */
diff --git a/include/fal/fal_init.h b/include/fal/fal_init.h
new file mode 100644
index 0000000..9aefba1
--- /dev/null
+++ b/include/fal/fal_init.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_init FAL_INIT
+ * @{
+ */
+#ifndef _FAL_INIT_H_
+#define _FAL_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+
+ sw_error_t fal_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+
+
+ sw_error_t
+ fal_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode,
+ hsl_access_mode reg_mode);
+
+
+ sw_error_t fal_reset(a_uint32_t dev_id);
+ sw_error_t fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg);
+ sw_error_t fal_cleanup(void);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_interface_ctrl.h b/include/fal/fal_interface_ctrl.h
new file mode 100644
index 0000000..93a2b3d
--- /dev/null
+++ b/include/fal/fal_interface_ctrl.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL
+ * @{
+ */
+#ifndef _FAL_INTERFACECTRL_H_
+#define _FAL_INTERFACECTRL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ typedef enum {
+ FAL_MAC_MODE_RGMII = 0,
+ FAL_MAC_MODE_GMII,
+ FAL_MAC_MODE_MII,
+ FAL_MAC_MODE_SGMII,
+ FAL_MAC_MODE_FIBER,
+ FAL_MAC_MODE_RMII,
+ FAL_MAC_MODE_DEFAULT
+ }
+ fal_interface_mac_mode_t;
+
+ typedef enum
+ {
+ FAL_INTERFACE_CLOCK_MAC_MODE = 0,
+ FAL_INTERFACE_CLOCK_PHY_MODE = 1,
+ } fal_interface_clock_mode_t;
+
+ typedef struct
+ {
+ a_bool_t txclk_delay_cmd;
+ a_bool_t rxclk_delay_cmd;
+ a_uint32_t txclk_delay_sel;
+ a_uint32_t rxclk_delay_sel;
+ } fal_mac_rgmii_config_t;
+
+ typedef struct
+ {
+ a_bool_t master_mode;
+ a_bool_t slave_mode;
+ a_bool_t clock_inverse;
+ a_bool_t pipe_rxclk_sel;
+ } fal_mac_rmii_config_t;
+
+ typedef struct
+ {
+ fal_interface_clock_mode_t clock_mode;
+ a_uint32_t txclk_select;
+ a_uint32_t rxclk_select;
+ } fal_mac_gmii_config_t;
+
+ typedef struct
+ {
+ fal_interface_clock_mode_t clock_mode;
+ a_uint32_t txclk_select;
+ a_uint32_t rxclk_select;
+ } fal_mac_mii_config_t;
+
+ typedef struct
+ {
+ fal_interface_clock_mode_t clock_mode;
+ a_bool_t auto_neg;
+ a_bool_t force_speed;
+ a_bool_t prbs_enable;
+ a_bool_t rem_phy_lpbk;
+ } fal_mac_sgmii_config_t;
+
+ typedef struct
+ {
+ a_bool_t auto_neg;
+ a_bool_t fx100_enable;
+ } fal_mac_fiber_config_t;
+
+ typedef struct
+ {
+ fal_interface_mac_mode_t mac_mode;
+ union
+ {
+ fal_mac_rgmii_config_t rgmii;
+ fal_mac_gmii_config_t gmii;
+ fal_mac_mii_config_t mii;
+ fal_mac_sgmii_config_t sgmii;
+ fal_mac_rmii_config_t rmii;
+ fal_mac_fiber_config_t fiber;
+ } config;
+ } fal_mac_config_t;
+
+ typedef struct
+ {
+ fal_interface_mac_mode_t mac_mode;
+ a_bool_t txclk_delay_cmd;
+ a_bool_t rxclk_delay_cmd;
+ a_uint32_t txclk_delay_sel;
+ a_uint32_t rxclk_delay_sel;
+ } fal_phy_config_t;
+
+ typedef enum
+ {
+ Fx100BASE_MODE = 2,
+ } fx100_ctrl_link_mode_t;
+
+ typedef enum
+ {
+ FX100_SERDS_MODE = 1,
+ } sgmii_fiber_mode_t;
+
+#define FX100_HALF_DUPLEX 0
+#define FX100_FULL_DUPLEX 1
+
+ typedef struct
+ {
+ fx100_ctrl_link_mode_t link_mode;
+ a_bool_t overshoot;
+ a_bool_t loopback;
+ a_bool_t fd_mode;
+ a_bool_t col_test;
+ sgmii_fiber_mode_t sgmii_fiber_mode;
+ a_bool_t crs_ctrl;
+ a_bool_t loopback_ctrl;
+ a_bool_t crs_col_100_ctrl;
+ a_bool_t loop_en;
+ } fal_fx100_ctrl_config_t;
+
+ sw_error_t
+ fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ sw_error_t
+ fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ sw_error_t
+ fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ sw_error_t
+ fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ sw_error_t
+ fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ sw_error_t
+ fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+ sw_error_t
+ fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+ sw_error_t
+ fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status);
+
+ sw_error_t
+ fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_INTERFACECTRL_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_ip.h b/include/fal/fal_ip.h
new file mode 100644
index 0000000..26fec16
--- /dev/null
+++ b/include/fal/fal_ip.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_ip FAL_IP
+ * @{
+ */
+#ifndef _FAL_IP_H_
+#define _FAL_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /* IP WCMP hash key flags */
+#define FAL_WCMP_HASH_KEY_SIP 0x1
+#define FAL_WCMP_HASH_KEY_DIP 0x2
+#define FAL_WCMP_HASH_KEY_SPORT 0x4
+#define FAL_WCMP_HASH_KEY_DPORT 0x8
+
+ /* IP entry operation flags */
+#define FAL_IP_ENTRY_ID_EN 0x1
+#define FAL_IP_ENTRY_INTF_EN 0x2
+#define FAL_IP_ENTRY_PORT_EN 0x4
+#define FAL_IP_ENTRY_STATUS_EN 0x8
+#define FAL_IP_ENTRY_IPADDR_EN 0x10
+
+ /* IP host entry structure flags field */
+#define FAL_IP_IP4_ADDR 0x1
+#define FAL_IP_IP6_ADDR 0x2
+#define FAL_IP_CPU_ADDR 0x4
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ a_uint32_t flags;
+ a_uint32_t status;
+ fal_ip4_addr_t ip4_addr;
+ fal_ip6_addr_t ip6_addr;
+ fal_mac_addr_t mac_addr;
+ a_uint32_t intf_id;
+ a_uint32_t expect_vid;
+ fal_port_t port_id;
+ a_bool_t mirror_en;
+ a_bool_t counter_en;
+ a_uint32_t counter_id;
+ a_uint32_t packet;
+ a_uint32_t byte;
+ a_bool_t pppoe_en;
+ a_uint32_t pppoe_id;
+ fal_fwd_cmd_t action;
+ } fal_host_entry_t;
+
+ typedef enum
+ {
+ FAL_MAC_IP_GUARD = 0,
+ FAL_MAC_IP_PORT_GUARD,
+ FAL_MAC_IP_VLAN_GUARD,
+ FAL_MAC_IP_PORT_VLAN_GUARD,
+ FAL_NO_SOURCE_GUARD,
+ } fal_source_guard_mode_t;
+
+ typedef enum
+ {
+ FAL_ARP_LEARN_LOCAL = 0,
+ FAL_ARP_LEARN_ALL,
+ } fal_arp_learn_mode_t;
+
+ /* IP host entry auto learn arp packets type */
+#define FAL_ARP_LEARN_REQ 0x1
+#define FAL_ARP_LEARN_ACK 0x2
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ a_uint16_t vid_low;
+ a_uint16_t vid_high;
+ fal_mac_addr_t mac_addr;
+ a_bool_t ip4_route;
+ a_bool_t ip6_route;
+ } fal_intf_mac_entry_t;
+
+ typedef struct
+ {
+ a_uint32_t nh_nr;
+ a_uint32_t nh_id[16];
+ } fal_ip_wcmp_t;
+
+ sw_error_t
+ fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+ sw_error_t
+ fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry);
+
+ sw_error_t
+ fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry);
+
+ sw_error_t
+ fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry);
+
+ sw_error_t
+ fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ sw_error_t
+ fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable);
+
+ sw_error_t
+ fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags);
+
+ sw_error_t
+ fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags);
+
+ sw_error_t
+ fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+ sw_error_t
+ fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+ sw_error_t
+ fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ sw_error_t
+ fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ sw_error_t
+ fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ sw_error_t
+ fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ sw_error_t
+ fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+ sw_error_t
+ fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry);
+
+ sw_error_t
+ fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry);
+
+ sw_error_t
+ fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ sw_error_t
+ fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ sw_error_t
+ fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ sw_error_t
+ fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ sw_error_t
+ fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+ sw_error_t
+ fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+ sw_error_t
+ fal_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ sw_error_t
+ fal_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ sw_error_t
+ fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ sw_error_t
+ fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_IP_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_leaky.h b/include/fal/fal_leaky.h
new file mode 100644
index 0000000..e067ddf
--- /dev/null
+++ b/include/fal/fal_leaky.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_leaky FAL_LEAKY
+ * @{
+ */
+#ifndef _FAL_LEAKY_H_
+#define _FAL_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This enum defines the leaky control mode.
+ */
+ typedef enum {
+ FAL_LEAKY_PORT_CTRL = 0, /**< control leaky through port which packets received*/
+ FAL_LEAKY_FDB_CTRL, /**< control leaky through fdb entry*/
+ FAL_LEAKY_CTRL_MODE_BUTT
+ }
+ fal_leaky_ctrl_mode_t;
+
+
+
+ sw_error_t
+ fal_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+ sw_error_t
+ fal_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+ sw_error_t
+ fal_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+ sw_error_t
+ fal_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+ sw_error_t
+ fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_led.h b/include/fal/fal_led.h
new file mode 100644
index 0000000..3c0207e
--- /dev/null
+++ b/include/fal/fal_led.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_led FAL_LED
+ * @{
+ */
+#ifndef _FAL_LED_H_
+#define _FAL_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This enum defines the led group.
+ */
+ typedef enum {
+ LED_LAN_PORT_GROUP = 0, /**< control lan ports*/
+ LED_WAN_PORT_GROUP, /**< control wan ports*/
+ LED_MAC_PORT_GROUP, /**< control mac ports*/
+ LED_GROUP_BUTT
+ }
+ led_pattern_group_t;
+
+ /**
+ @brief This enum defines the led pattern id, each ports has three led
+ and pattern0 relates to led0, pattern1 relates to led1, pattern2 relates to led2.
+ */
+ typedef a_uint32_t led_pattern_id_t;
+
+
+ /**
+ @brief This enum defines the led control pattern mode.
+ */
+ typedef enum
+ {
+ LED_ALWAYS_OFF = 0,
+ LED_ALWAYS_BLINK,
+ LED_ALWAYS_ON,
+ LED_PATTERN_MAP_EN,
+ LED_PATTERN_MODE_BUTT
+ } led_pattern_mode_t;
+
+
+#define FULL_DUPLEX_LIGHT_EN 0
+#define HALF_DUPLEX_LIGHT_EN 1
+#define POWER_ON_LIGHT_EN 2
+#define LINK_1000M_LIGHT_EN 3
+#define LINK_100M_LIGHT_EN 4
+#define LINK_10M_LIGHT_EN 5
+#define COLLISION_BLINK_EN 6
+#define RX_TRAFFIC_BLINK_EN 7
+#define TX_TRAFFIC_BLINK_EN 8
+#define LINKUP_OVERRIDE_EN 9
+
+
+ /**
+ @brief This enum defines the led control pattern map.
+ */
+ typedef a_uint32_t led_pattern_map_t;
+
+
+ /**
+ @brief This enum defines the led control pattern mode.
+ */
+ typedef enum
+ {
+ LED_BLINK_2HZ = 0,
+ LED_BLINK_4HZ,
+ LED_BLINK_8HZ,
+ LED_BLINK_TXRX, /**< Frequency relates to speed, 1000M-8HZ,100M->4HZ,10M->2HZ,Others->4HZ */
+ LED_BLINK_FREQ_BUTT
+ } led_blink_freq_t;
+
+
+ typedef struct
+ {
+ led_pattern_mode_t mode;
+ led_pattern_map_t map;
+ led_blink_freq_t freq;
+ } led_ctrl_pattern_t;
+
+
+
+
+
+ sw_error_t
+ fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+
+ sw_error_t
+ fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_LED_H_ */
+/**
+ * @}
+ */
+
diff --git a/include/fal/fal_mib.h b/include/fal/fal_mib.h
new file mode 100644
index 0000000..0c9d498
--- /dev/null
+++ b/include/fal/fal_mib.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_mib FAL_MIB
+ * @{
+ */
+#ifndef _FAL_MIB_H
+#define _FAL_MIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**@brief This structure defines the mib infomation.
+ */
+ typedef struct
+ {
+ a_uint32_t RxBroad;
+ a_uint32_t RxPause;
+ a_uint32_t RxMulti;
+ a_uint32_t RxFcsErr;
+ a_uint32_t RxAllignErr;
+ a_uint32_t RxRunt;
+ a_uint32_t RxFragment;
+ a_uint32_t Rx64Byte;
+ a_uint32_t Rx128Byte;
+ a_uint32_t Rx256Byte;
+ a_uint32_t Rx512Byte;
+ a_uint32_t Rx1024Byte;
+ a_uint32_t Rx1518Byte;
+ a_uint32_t RxMaxByte;
+ a_uint32_t RxTooLong;
+ a_uint32_t RxGoodByte_lo; /**< low 32 bits of RxGoodByte statistc item */
+ a_uint32_t RxGoodByte_hi; /**< high 32 bits of RxGoodByte statistc item*/
+ a_uint32_t RxBadByte_lo; /**< low 32 bits of RxBadByte statistc item */
+ a_uint32_t RxBadByte_hi; /**< high 32 bits of RxBadByte statistc item */
+ a_uint32_t RxOverFlow;
+ a_uint32_t Filtered;
+ a_uint32_t TxBroad;
+ a_uint32_t TxPause;
+ a_uint32_t TxMulti;
+ a_uint32_t TxUnderRun;
+ a_uint32_t Tx64Byte;
+ a_uint32_t Tx128Byte;
+ a_uint32_t Tx256Byte;
+ a_uint32_t Tx512Byte;
+ a_uint32_t Tx1024Byte;
+ a_uint32_t Tx1518Byte;
+ a_uint32_t TxMaxByte;
+ a_uint32_t TxOverSize;
+ a_uint32_t TxByte_lo; /**< low 32 bits of TxByte statistc item */
+ a_uint32_t TxByte_hi; /**< high 32 bits of TxByte statistc item */
+ a_uint32_t TxCollision;
+ a_uint32_t TxAbortCol;
+ a_uint32_t TxMultiCol;
+ a_uint32_t TxSingalCol;
+ a_uint32_t TxExcDefer;
+ a_uint32_t TxDefer;
+ a_uint32_t TxLateCol;
+ a_uint32_t RxUniCast;
+ a_uint32_t TxUniCast;
+ } fal_mib_info_t;
+
+
+ sw_error_t
+ fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+
+ sw_error_t
+ fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ sw_error_t
+ fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _FAL_MIB_H */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_mirror.h b/include/fal/fal_mirror.h
new file mode 100644
index 0000000..c888f01
--- /dev/null
+++ b/include/fal/fal_mirror.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_mirror FAL_MIRROR
+ * @{
+ */
+#ifndef _FAL_MIRROR_H_
+#define _FAL_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+
+ sw_error_t fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ sw_error_t fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+
+ sw_error_t
+ fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _PORT_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_misc.h b/include/fal/fal_misc.h
new file mode 100644
index 0000000..70646d0
--- /dev/null
+++ b/include/fal/fal_misc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_gen FAL_MISC
+ * @{
+ */
+#ifndef _FAL_MISC_H_
+#define _FAL_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ a_uint32_t session_id;
+ a_bool_t multi_session;
+ a_bool_t uni_session;
+ } fal_pppoe_session_t;
+
+ typedef enum
+ {
+ FAL_LOOP_CHECK_1MS = 0,
+ FAL_LOOP_CHECK_10MS,
+ FAL_LOOP_CHECK_100MS,
+ FAL_LOOP_CHECK_500MS,
+ } fal_loop_check_time_t;
+
+ /* define switch interrupt type bitmap */
+#define FAL_SWITCH_INTR_LINK_STATUS 0x1 /* up/down/speed/duplex status */
+
+ sw_error_t fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ sw_error_t fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+
+ sw_error_t fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+
+ sw_error_t
+ fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+
+ sw_error_t
+ fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+
+
+ sw_error_t
+ fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+ sw_error_t
+ fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+
+ sw_error_t
+ fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ sw_error_t
+ fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ sw_error_t
+ fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
+
+
+ sw_error_t
+ fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id);
+
+
+ sw_error_t
+ fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
+
+ sw_error_t
+ fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ sw_error_t
+ fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ sw_error_t
+ fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ sw_error_t
+ fal_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ sw_error_t
+ fal_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ sw_error_t
+ fal_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ sw_error_t
+ fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id);
+
+
+ sw_error_t
+ fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id);
+
+
+ sw_error_t
+ fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+ sw_error_t
+ fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+ sw_error_t
+ fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+ sw_error_t
+ fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+ sw_error_t
+ fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask);
+
+
+ sw_error_t
+ fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
+
+
+ sw_error_t
+ fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask);
+
+
+ sw_error_t
+ fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+ sw_error_t
+ fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+ sw_error_t
+ fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ sw_error_t
+ fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_MISC_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_multi.h b/include/fal/fal_multi.h
new file mode 100644
index 0000000..82918fc
--- /dev/null
+++ b/include/fal/fal_multi.h
@@ -0,0 +1,53 @@
+
+#ifndef _FAL_MULTI_H_
+#define _FAL_MULTI_H_
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+ FAL_ADDR_IPV4 = 0,
+ FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+ fal_addr_type_t type;
+ union
+ {
+ fal_ip4_addr_t ip4_addr;
+ fal_ip6_addr_t ip6_addr;
+ } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+ fal_igmp_sg_addr_t source;
+ fal_igmp_sg_addr_t group;
+ fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+//#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI 5
+
+#define MULT_ACTION_SET 0
+#define MULT_ACTION_CLEAR 1
+
+// static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+ a_uint8_t index; //MAX is 32
+ fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+
+
+#endif
diff --git a/include/fal/fal_nat.h b/include/fal/fal_nat.h
new file mode 100644
index 0000000..5c9f6c0
--- /dev/null
+++ b/include/fal/fal_nat.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_nat FAL_NAT
+ * @{
+ */
+#ifndef _FAL_NAT_H_
+#define _FAL_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+#define FAL_NAT_ENTRY_PROTOCOL_TCP 0x1
+#define FAL_NAT_ENTRY_PROTOCOL_UDP 0x2
+#define FAL_NAT_ENTRY_PROTOCOL_PPTP 0x4
+#define FAL_NAT_ENTRY_PROTOCOL_ANY 0x8
+#define FAL_NAT_ENTRY_TRANS_IPADDR_INDEX 0x10
+#define FAL_NAT_ENTRY_PORT_CHECK 0x20
+#define FAL_NAT_HASH_KEY_PORT 0x40
+#define FAL_NAT_HASH_KEY_IPADDR 0x80
+
+
+ /* NAT entry operation flags */
+#define FAL_NAT_ENTRY_ID_EN 0x1
+#define FAL_NAT_ENTRY_SRC_IPADDR_EN 0x2
+#define FAL_NAT_ENTRY_TRANS_IPADDR_EN 0x4
+#define FAL_NAT_ENTRY_KEY_EN 0x8
+#define FAL_NAT_ENTRY_PUBLIC_IP_EN 0x10
+#define FAL_NAT_ENTRY_SOURCE_IP_EN 0x20
+#define FAL_NAT_ENTRY_AGE_EN 0x40
+
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ a_uint32_t flags;
+ a_uint32_t status;
+ fal_ip4_addr_t src_addr;
+ fal_ip4_addr_t dst_addr;
+ a_uint16_t src_port;
+ a_uint16_t dst_port;
+ fal_ip4_addr_t trans_addr;
+ a_uint16_t trans_port;
+ a_uint16_t rsv;
+ a_bool_t mirror_en;
+ a_bool_t counter_en;
+ a_uint32_t counter_id;
+ a_uint32_t ingress_packet;
+ a_uint32_t ingress_byte;
+ a_uint32_t egress_packet;
+ a_uint32_t egress_byte;
+ fal_fwd_cmd_t action;
+ } fal_napt_entry_t;
+
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ a_uint32_t flags;
+ a_uint32_t status;
+ fal_ip4_addr_t src_addr;
+ fal_ip4_addr_t trans_addr;
+ a_uint16_t port_num;
+ a_uint16_t port_range;
+ a_uint32_t slct_idx;
+ a_bool_t mirror_en;
+ a_bool_t counter_en;
+ a_uint32_t counter_id;
+ a_uint32_t ingress_packet;
+ a_uint32_t ingress_byte;
+ a_uint32_t egress_packet;
+ a_uint32_t egress_byte;
+ fal_fwd_cmd_t action;
+ } fal_nat_entry_t;
+
+
+ typedef enum
+ {
+ FAL_NAPT_FULL_CONE = 0,
+ FAL_NAPT_STRICT_CONE,
+ FAL_NAPT_PORT_STRICT,
+ FAL_NAPT_SYNMETRIC,
+ } fal_napt_mode_t;
+
+
+ typedef struct
+ {
+ a_uint32_t entry_id;
+ fal_ip4_addr_t pub_addr;
+ } fal_nat_pub_addr_t;
+
+
+ sw_error_t
+ fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+
+ sw_error_t
+ fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * nat_entry);
+
+
+ sw_error_t
+ fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
+
+
+ sw_error_t
+ fal_nat_next(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry);
+
+
+ sw_error_t
+ fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+
+ sw_error_t
+ fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry);
+
+
+ sw_error_t
+ fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry);
+
+
+ sw_error_t
+ fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry);
+
+
+ sw_error_t
+ fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+
+ sw_error_t
+ fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+
+ sw_error_t
+ fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+
+ sw_error_t
+ fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+
+ sw_error_t
+ fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+
+ sw_error_t
+ fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+
+ sw_error_t
+ fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+ sw_error_t
+ fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ sw_error_t
+ fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+
+ sw_error_t
+ fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en);
+
+
+ sw_error_t
+ fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en);
+
+
+ sw_error_t
+ fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+
+ sw_error_t
+ fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_pub_addr_t * entry);
+
+
+ sw_error_t
+ fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_pub_addr_t * entry);
+
+
+ sw_error_t
+ fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ sw_error_t
+ fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_NAT_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/fal/fal_port_ctrl.h b/include/fal/fal_port_ctrl.h
new file mode 100644
index 0000000..619fcfc
--- /dev/null
+++ b/include/fal/fal_port_ctrl.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_port_ctrl FAL_PORT_CONTROL
+ * @{
+ */
+#ifndef _FAL_PORTCTRL_H_
+#define _FAL_PORTCTRL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ typedef enum {
+ FAL_HALF_DUPLEX = 0,
+ FAL_FULL_DUPLEX,
+ FAL_DUPLEX_BUTT = 0xffff
+ }
+ fal_port_duplex_t;
+
+ typedef enum
+ {
+ FAL_SPEED_10 = 10,
+ FAL_SPEED_100 = 100,
+ FAL_SPEED_1000 = 1000,
+ FAL_SPEED_10000 = 10000,
+ FAL_SPEED_BUTT = 0xffff,
+ } fal_port_speed_t;
+
+ typedef enum
+ {
+ FAL_CABLE_STATUS_NORMAL = 0,
+ FAL_CABLE_STATUS_SHORT = 1,
+ FAL_CABLE_STATUS_OPENED = 2,
+ FAL_CABLE_STATUS_INVALID = 3,
+ FAL_CABLE_STATUS_BUTT = 0xffff,
+ } fal_cable_status_t;
+
+#define FAL_ENABLE 1
+#define FAL_DISABLE 0
+
+//phy autoneg adv
+#define FAL_PHY_ADV_10T_HD 0x01
+#define FAL_PHY_ADV_10T_FD 0x02
+#define FAL_PHY_ADV_100TX_HD 0x04
+#define FAL_PHY_ADV_100TX_FD 0x08
+//#define FAL_PHY_ADV_1000T_HD 0x100
+#define FAL_PHY_ADV_1000T_FD 0x200
+#define FAL_PHY_ADV_FE_SPEED_ALL \
+ (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
+ FAL_PHY_ADV_100TX_FD)
+
+#define FAL_PHY_ADV_GE_SPEED_ALL \
+ (FAL_PHY_ADV_10T_HD | FAL_PHY_ADV_10T_FD | FAL_PHY_ADV_100TX_HD |\
+ FAL_PHY_ADV_100TX_FD | FAL_PHY_ADV_1000T_FD)
+
+#define FAL_PHY_ADV_PAUSE 0x10
+#define FAL_PHY_ADV_ASY_PAUSE 0x20
+#define FAL_PHY_FE_ADV_ALL \
+ (FAL_PHY_ADV_FE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
+#define FAL_PHY_GE_ADV_ALL \
+ (FAL_PHY_ADV_GE_SPEED_ALL | FAL_PHY_ADV_PAUSE | FAL_PHY_ADV_ASY_PAUSE)
+
+//phy capablity
+#define FAL_PHY_AUTONEG_CAPS 0x01
+#define FAL_PHY_100T2_HD_CAPS 0x02
+#define FAL_PHY_100T2_FD_CAPS 0x04
+#define FAL_PHY_10T_HD_CAPS 0x08
+#define FAL_PHY_10T_FD_CAPS 0x10
+#define FAL_PHY_100X_HD_CAPS 0x20
+#define FAL_PHY_100X_FD_CAPS 0x40
+#define FAL_PHY_100T4_CAPS 0x80
+//#define FAL_PHY_1000T_HD_CAPS 0x100
+#define FAL_PHY_1000T_FD_CAPS 0x200
+//#define FAL_PHY_1000X_HD_CAPS 0x400
+#define FAL_PHY_1000X_FD_CAPS 0x800
+
+//phy partner capablity
+#define FAL_PHY_PART_10T_HD 0x1
+#define FAL_PHY_PART_10T_FD 0x2
+#define FAL_PHY_PART_100TX_HD 0x4
+#define FAL_PHY_PART_100TX_FD 0x8
+//#define FAL_PHY_PART_1000T_HD 0x10
+#define FAL_PHY_PART_1000T_FD 0x20
+
+//phy interrupt flag
+#define FAL_PHY_INTR_SPEED_CHANGE 0x1
+#define FAL_PHY_INTR_DUPLEX_CHANGE 0x2
+#define FAL_PHY_INTR_STATUS_UP_CHANGE 0x4
+#define FAL_PHY_INTR_STATUS_DOWN_CHANGE 0x8
+
+ typedef enum
+ {
+ FAL_NO_HEADER_EN = 0,
+ FAL_ONLY_MANAGE_FRAME_EN,
+ FAL_ALL_TYPE_FRAME_EN
+ } fal_port_header_mode_t;
+
+ typedef struct
+ {
+ a_uint16_t pair_a_status;
+ a_uint16_t pair_b_status;
+ a_uint16_t pair_c_status;
+ a_uint16_t pair_d_status;
+ a_uint32_t pair_a_len;
+ a_uint32_t pair_b_len;
+ a_uint32_t pair_c_len;
+ a_uint32_t pair_d_len;
+ } fal_port_cdt_t;
+
+ sw_error_t
+ fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+
+ sw_error_t
+ fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+
+ sw_error_t
+ fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+
+ sw_error_t
+ fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+
+ sw_error_t
+ fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+
+ sw_error_t
+ fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ sw_error_t
+ fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ sw_error_t
+ fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+
+ sw_error_t
+ fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+
+ sw_error_t
+ fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ sw_error_t
+ fal_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ sw_error_t
+ fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ sw_error_t
+ fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+ sw_error_t
+ fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ sw_error_t
+ fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ sw_error_t
+ fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ sw_error_t
+ fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ sw_error_t
+ fal_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+
+ sw_error_t
+ fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+
+ sw_error_t
+ fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+ sw_error_t
+ fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_PORTCTRL_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_portvlan.h b/include/fal/fal_portvlan.h
new file mode 100644
index 0000000..d2ff7b0
--- /dev/null
+++ b/include/fal/fal_portvlan.h
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup fal_port_vlan FAL_PORT_VLAN
+ * @{
+ */
+#ifndef _FAL_PORT_VLAN_H_
+#define _FAL_PORT_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This enum defines 802.1q mode type.
+ */
+ typedef enum {
+ FAL_1Q_DISABLE = 0, /**< 802.1q mode disbale, port based vlan */
+ FAL_1Q_SECURE, /**< secure mode, packets which vid isn't in vlan table or source port isn't in vlan port member will be discarded.*/
+ FAL_1Q_CHECK, /**< check mode, packets which vid isn't in vlan table will be discarded, packets which source port isn't in vlan port member will forward base on vlan port member*/
+ FAL_1Q_FALLBACK, /**< fallback mode, packets which vid isn't in vlan table will forwarded base on port vlan, packet's which source port isn't in vlan port member will forward base on vlan port member.*/
+ FAL_1Q_MODE_BUTT
+ }
+ fal_pt_1qmode_t;
+
+ /**
+ @brief This enum defines receive packets tagged mode.
+ */
+ typedef enum
+ {
+ FAL_INVLAN_ADMIT_ALL = 0, /**< receive all packets include tagged and untagged */
+ FAL_INVLAN_ADMIT_TAGGED, /**< only receive tagged packets*/
+ FAL_INVLAN_ADMIT_UNTAGGED, /**< only receive untagged packets include priority tagged */
+ FAL_INVLAN_MODE_BUTT
+ } fal_pt_invlan_mode_t;
+
+ /**
+ @brief This enum defines vlan propagation mode.
+ */
+ typedef enum
+ {
+ FAL_VLAN_PROPAGATION_DISABLE = 0, /**< vlan propagation disable */
+ FAL_VLAN_PROPAGATION_CLONE, /**< vlan paopagation mode is clone */
+ FAL_VLAN_PROPAGATION_REPLACE, /**< vlan paopagation mode is repalce */
+ FAL_VLAN_PROPAGATION_MODE_BUTT
+ } fal_vlan_propagation_mode_t;
+
+ /**
+ @details Fields description:
+
+ o_vid - original vlan id
+ s_vid - service vid id
+ c_vid - custom vid id
+ bi_dir - entry search direction
+ forward_dir - entry search direction only be forward
+ reverse_dir - entry search direction only be reverse
+ o_vid_is_cvid - o_vid in entry means c_vid not s_vid
+ s_vid_enable - s_vid in entry is valid
+ c_vid_enable - c_vid in entry is valid
+ one_2_one_vlan- the entry used for 1:1 vlan
+ @brief This structure defines the vlan translation entry.
+
+ */
+ typedef struct
+ {
+ a_uint32_t o_vid;
+ a_uint32_t s_vid;
+ a_uint32_t c_vid;
+ a_bool_t bi_dir; /**< lookup can be forward and reverse*/
+ a_bool_t forward_dir; /**< lookup direction only can be from o_vid to s_vid and/or c_vid*/
+ a_bool_t reverse_dir; /**< lookup direction only can be from s_vid and/or c_vid to o_vid*/
+ a_bool_t o_vid_is_cvid;
+ a_bool_t s_vid_enable;
+ a_bool_t c_vid_enable;
+ a_bool_t one_2_one_vlan;
+ } fal_vlan_trans_entry_t;
+
+ /**
+ @brief This enum defines qinq working mode.
+ */
+ typedef enum
+ {
+ FAL_QINQ_CTAG_MODE = 0,
+ FAL_QINQ_STAG_MODE,
+ FAL_QINQ_MODE_BUTT
+ } fal_qinq_mode_t;
+
+ /**
+ @brief This enum defines port role in qinq mode.
+ */
+ typedef enum
+ {
+ FAL_QINQ_EDGE_PORT = 0,
+ FAL_QINQ_CORE_PORT,
+ FAL_QINQ_PORT_ROLE_BUTT
+ } fal_qinq_port_role_t;
+
+
+ sw_error_t
+ fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+
+ sw_error_t
+ fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+
+ sw_error_t
+ fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+
+ sw_error_t
+ fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+
+ sw_error_t
+ fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_t mem_port_id);
+
+
+
+ sw_error_t
+ fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_t mem_port_id);
+
+
+
+ sw_error_t
+ fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+
+ sw_error_t
+ fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+
+
+ sw_error_t
+ fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+
+ sw_error_t
+ fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+
+ sw_error_t
+ fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+
+ sw_error_t
+ fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+ sw_error_t
+ fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+
+ sw_error_t
+ fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+
+ sw_error_t
+ fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ sw_error_t
+ fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+ sw_error_t
+ fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ sw_error_t
+ fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+ sw_error_t
+ fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode);
+
+
+ sw_error_t
+ fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode);
+
+
+ sw_error_t
+ fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ sw_error_t
+ fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ sw_error_t
+ fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ sw_error_t
+ fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+ sw_error_t
+ fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+ sw_error_t
+ fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+ sw_error_t
+ fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+ sw_error_t
+ fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+ sw_error_t
+ fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ sw_error_t
+ fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable);
+
+ sw_error_t
+ fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable);
+
+ sw_error_t
+ fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable);
+
+ sw_error_t
+ fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable);
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _PORT_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_qos.h b/include/fal/fal_qos.h
new file mode 100644
index 0000000..1ed079a
--- /dev/null
+++ b/include/fal/fal_qos.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_qos FAL_QOS
+ * @{
+ */
+#ifndef _FAL_QOS_H_
+#define _FAL_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This enum defines traffic scheduling mode.
+ */
+ typedef enum {
+ FAL_SCH_SP_MODE = 0, /**< strict priority scheduling mode */
+ FAL_SCH_WRR_MODE, /**< weight round robin scheduling mode*/
+ FAL_SCH_MIX_MODE, /**< sp and wrr mixed scheduling mode */
+ FAL_SCH_MIX_PLUS_MODE, /**< sp and wrr mixed plus scheduling mode */
+ FAL_SCH_MODE_BUTT
+ }
+ fal_sch_mode_t;
+
+ /**
+ @brief This enum defines qos assignment mode.
+ */
+ typedef enum
+ {
+ FAL_QOS_DA_MODE = 0, /**< qos assignment based on destination mac address*/
+ FAL_QOS_UP_MODE, /**< qos assignment based on 802.1p field in vlan tag*/
+ FAL_QOS_DSCP_MODE, /**< qos assignment based on dscp field in ip header */
+ FAL_QOS_PORT_MODE, /**< qos assignment based on port */
+ FAL_QOS_MODE_BUTT
+ } fal_qos_mode_t;
+
+#define FAL_DOT1P_MIN 0
+#define FAL_DOT1P_MAX 7
+
+#define FAL_DSCP_MIN 0
+#define FAL_DSCP_MAX 63
+
+
+ sw_error_t
+ fal_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+
+ sw_error_t
+ fal_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+
+ sw_error_t
+ fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number);
+
+
+
+ sw_error_t
+ fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number);
+
+
+
+ sw_error_t
+ fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ sw_error_t
+ fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ sw_error_t
+ fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+
+ sw_error_t
+ fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+ sw_error_t
+ fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ sw_error_t
+ fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ sw_error_t
+ fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue);
+
+
+
+ sw_error_t
+ fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue);
+
+
+
+ sw_error_t
+ fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue);
+
+
+
+ sw_error_t
+ fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue);
+
+
+
+ sw_error_t
+ fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+
+ sw_error_t
+ fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+
+ sw_error_t
+ fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up);
+
+
+
+ sw_error_t
+ fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up);
+
+
+ sw_error_t
+ fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+ sw_error_t
+ fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+ sw_error_t
+ fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri);
+
+
+ sw_error_t
+ fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri);
+
+
+ sw_error_t
+ fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri);
+
+
+ sw_error_t
+ fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri);
+
+ sw_error_t
+ fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ sw_error_t
+ fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ sw_error_t
+ fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ sw_error_t
+ fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ sw_error_t
+ fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+ sw_error_t
+ fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _PORT_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_rate.h b/include/fal/fal_rate.h
new file mode 100644
index 0000000..8047415
--- /dev/null
+++ b/include/fal/fal_rate.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_rate FAL_RATE
+ * @{
+ */
+#ifndef _FAL_RATE_H_
+#define _FAL_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This enum defines storm type
+ */
+ typedef enum {
+ FAL_UNICAST_STORM = 0, /**< storm caused by unknown unicast packets */
+ FAL_MULTICAST_STORM, /**< storm caused by unknown multicast packets */
+ FAL_BROADCAST_STORM, /**< storm caused by broadcast packets */
+ FAL_STORM_TYPE_BUTT
+ }
+ fal_storm_type_t;
+
+
+
+ sw_error_t
+ fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t enable);
+
+
+
+ sw_error_t
+ fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type,
+ a_bool_t * enable);
+
+
+
+ sw_error_t
+ fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate);
+
+
+
+ sw_error_t
+ fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate);
+
+
+ typedef enum
+ {
+ FAL_RATE_MI_100US = 0,
+ FAL_RATE_MI_1MS,
+ FAL_RATE_MI_10MS,
+ FAL_RATE_MI_100MS,
+ } fal_rate_mt_t;
+
+
+ typedef struct
+ {
+ fal_traffic_unit_t meter_unit;
+ a_uint32_t cir;
+ a_uint32_t eir;
+ a_uint32_t cbs;
+ a_uint32_t ebs;
+ } fal_egress_shaper_t;
+
+
+#define FAL_INGRESS_POLICING_TCP_CTRL 0x2
+#define FAL_INGRESS_POLICING_MANAGEMENT 0x4
+#define FAL_INGRESS_POLICING_BROAD 0x8
+#define FAL_INGRESS_POLICING_UNK_UNI 0x10
+#define FAL_INGRESS_POLICING_UNK_MUL 0x20
+#define FAL_INGRESS_POLICING_UNI 0x40
+#define FAL_INGRESS_POLICING_MUL 0x80
+
+
+ typedef struct
+ {
+ a_bool_t c_enable;
+ a_bool_t e_enable;
+ a_bool_t combine_mode;
+ fal_traffic_unit_t meter_unit;
+ a_bool_t color_mode;
+ a_bool_t couple_flag;
+ a_bool_t deficit_en;
+ a_uint32_t cir;
+ a_uint32_t eir;
+ a_uint32_t cbs;
+ a_uint32_t ebs;
+ a_uint32_t c_rate_flag;
+ a_uint32_t e_rate_flag;
+ fal_rate_mt_t c_meter_interval;
+ fal_rate_mt_t e_meter_interval;
+ } fal_port_policer_t;
+
+
+ typedef struct
+ {
+ a_bool_t counter_mode;
+ fal_traffic_unit_t meter_unit;
+ fal_rate_mt_t meter_interval;
+ a_bool_t color_mode;
+ a_bool_t couple_flag;
+ a_bool_t deficit_en;
+ a_uint32_t cir;
+ a_uint32_t eir;
+ a_uint32_t cbs;
+ a_uint32_t ebs;
+ a_uint32_t counter_high;
+ a_uint32_t counter_low;
+ } fal_acl_policer_t;
+
+
+ sw_error_t
+ fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+
+ sw_error_t
+ fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+
+ sw_error_t
+ fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper);
+
+
+ sw_error_t
+ fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper);
+
+
+ sw_error_t
+ fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+
+ sw_error_t
+ fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+
+ sw_error_t
+ fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+
+ sw_error_t
+ fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ sw_error_t
+ fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number);
+
+ sw_error_t
+ fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ sw_error_t
+ fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+ sw_error_t
+ fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_reg_access.h b/include/fal/fal_reg_access.h
new file mode 100644
index 0000000..d643155
--- /dev/null
+++ b/include/fal/fal_reg_access.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_reg_access FAL_REG_ACCESS
+ * @{
+ */
+#ifndef _FAL_REG_ACCESS_H_
+#define _FAL_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ sw_error_t
+ fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_REG_ACCESS_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/fal/fal_sec.h b/include/fal/fal_sec.h
new file mode 100644
index 0000000..8911f34
--- /dev/null
+++ b/include/fal/fal_sec.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_sec FAL_SEC
+ * @{
+ */
+#ifndef _FAL_SEC_H_
+#define _FAL_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+ typedef enum {
+ /* define MAC layer related normalization items */
+ FAL_NORM_MAC_RESV_VID_CMD = 0,
+ FAL_NORM_MAC_INVALID_SRC_ADDR_CMD,
+
+ /* define IP layer related normalization items */
+ FAL_NORM_IP_INVALID_VER_CMD,
+ FAL_NROM_IP_SAME_ADDR_CMD,
+ FAL_NROM_IP_TTL_CHANGE_STATUS,
+ FAL_NROM_IP_TTL_VALUE,
+
+ /* define IP4 related normalization items */
+ FAL_NROM_IP4_INVALID_HL_CMD,
+ FAL_NROM_IP4_HDR_OPTIONS_CMD,
+ FAL_NROM_IP4_INVALID_DF_CMD,
+ FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD,
+ FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD,
+ FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD,
+ FAL_NROM_IP4_INVALID_SIP_CMD,
+ FAL_NROM_IP4_INVALID_DIP_CMD,
+ FAL_NROM_IP4_INVALID_CHKSUM_CMD,
+ FAL_NROM_IP4_INVALID_PL_CMD,
+ FAL_NROM_IP4_DF_CLEAR_STATUS,
+ FAL_NROM_IP4_IPID_RANDOM_STATUS,
+ FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE,
+
+ /* define IP4 related normalization items */
+ FAL_NROM_IP6_INVALID_PL_CMD,
+ FAL_NROM_IP6_INVALID_SIP_CMD,
+ FAL_NROM_IP6_INVALID_DIP_CMD,
+
+ /* define TCP related normalization items */
+ FAL_NROM_TCP_BLAT_CMD,
+ FAL_NROM_TCP_INVALID_HL_CMD,
+ FAL_NROM_TCP_INVALID_SYN_CMD,
+ FAL_NROM_TCP_SU_BLOCK_CMD,
+ FAL_NROM_TCP_SP_BLOCK_CMD,
+ FAL_NROM_TCP_SAP_BLOCK_CMD,
+ FAL_NROM_TCP_XMAS_SCAN_CMD,
+ FAL_NROM_TCP_NULL_SCAN_CMD,
+ FAL_NROM_TCP_SR_BLOCK_CMD,
+ FAL_NROM_TCP_SF_BLOCK_CMD,
+ FAL_NROM_TCP_SAR_BLOCK_CMD,
+ FAL_NROM_TCP_RST_SCAN_CMD,
+ FAL_NROM_TCP_SYN_WITH_DATA_CMD,
+ FAL_NROM_TCP_RST_WITH_DATA_CMD,
+ FAL_NROM_TCP_FA_BLOCK_CMD,
+ FAL_NROM_TCP_PA_BLOCK_CMD,
+ FAL_NROM_TCP_UA_BLOCK_CMD,
+ FAL_NROM_TCP_INVALID_CHKSUM_CMD,
+ FAL_NROM_TCP_INVALID_URGPTR_CMD,
+ FAL_NROM_TCP_INVALID_OPTIONS_CMD,
+ FAL_NROM_TCP_MIN_HDR_SIZE,
+
+ /* define UDP related normalization items */
+ FAL_NROM_UDP_BLAT_CMD,
+ FAL_NROM_UDP_INVALID_LEN_CMD,
+ FAL_NROM_UDP_INVALID_CHKSUM_CMD,
+
+ /* define ICMP related normalization items */
+ FAL_NROM_ICMP4_PING_PL_EXCEED_CMD,
+ FAL_NROM_ICMP6_PING_PL_EXCEED_CMD,
+ FAL_NROM_ICMP4_PING_FRAG_CMD,
+ FAL_NROM_ICMP6_PING_FRAG_CMD,
+ FAL_NROM_ICMP4_PING_MAX_PL_VALUE,
+ FAL_NROM_ICMP6_PING_MAX_PL_VALUE,
+ }
+ fal_norm_item_t;
+
+ sw_error_t
+ fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value);
+
+ sw_error_t
+ fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_SEC_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/fal/fal_stp.h b/include/fal/fal_stp.h
new file mode 100644
index 0000000..7ad021e
--- /dev/null
+++ b/include/fal/fal_stp.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_stp FAL_STP
+ * @{
+ */
+#ifndef _FAL_STP_H_
+#define _FAL_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+#define FAL_SINGLE_STP_ID 0
+
+ /**
+ @brief This enum defines port state for spanning tree.
+ */
+ typedef enum {
+ FAL_STP_DISABLED = 0, /**< disable state*/
+ FAL_STP_BLOKING, /**< blocking state*/
+ FAL_STP_LISTENING, /**< listening state*/
+ FAL_STP_LEARNING, /**< learning state*/
+ FAL_STP_FARWARDING, /**< forwarding state*/
+ FAL_STP_STATE_BUTT
+ }
+ fal_stp_state_t;
+
+
+
+ sw_error_t
+ fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+
+ sw_error_t
+ fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_STP_H_ */
+
+/**
+ * @}
+ */
diff --git a/include/fal/fal_trunk.h b/include/fal/fal_trunk.h
new file mode 100644
index 0000000..816510f
--- /dev/null
+++ b/include/fal/fal_trunk.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_trunk FAL_TRUNK
+ * @{
+ */
+#ifndef _FAL_TRUNK_H_
+#define _FAL_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+
+#define FAL_TRUNK_HASH_KEY_DA 0x1
+#define FAL_TRUNK_HASH_KEY_SA 0x2
+#define FAL_TRUNK_HASH_KEY_DIP 0x4
+#define FAL_TRUNK_HASH_KEY_SIP 0x8
+
+
+ sw_error_t
+ fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member);
+
+
+ sw_error_t
+ fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member);
+
+
+ sw_error_t
+ fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+
+ sw_error_t
+ fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+
+ sw_error_t
+ fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+
+ sw_error_t
+ fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_TRUNK_H_ */
+
+/**
+ * @}
+ */
diff --git a/include/fal/fal_type.h b/include/fal/fal_type.h
new file mode 100644
index 0000000..17abd5a
--- /dev/null
+++ b/include/fal/fal_type.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_type FAL_TYPE
+ * @{
+ */
+#ifndef _FAL_TYPE_H_
+#define _FAL_TYPE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ typedef a_uint32_t fal_port_t;
+
+#if (SW_MAX_NR_PORT <= 32)
+ typedef a_uint32_t fal_pbmp_t;
+#else
+ typedef a_uint64_t fal_pbmp_t;
+#endif
+
+ typedef struct
+ {
+ a_uint8_t uc[6];
+ } fal_mac_addr_t;
+
+ typedef a_uint32_t fal_ip4_addr_t;
+
+ typedef struct
+ {
+ a_uint32_t ul[4];
+ } fal_ip6_addr_t;
+
+ /**
+ @brief This enum defines several forwarding command type.
+ * Field description:
+ FAL_MAC_FRWRD - packets are normally forwarded
+ FAL_MAC_DROP - packets are dropped
+ FAL_MAC_CPY_TO_CPU - packets are copyed to cpu
+ FAL_MAC_RDT_TO_CPU - packets are redirected to cpu
+ */
+ typedef enum
+ {
+ FAL_MAC_FRWRD = 0, /**< packets are normally forwarded */
+ FAL_MAC_DROP, /**< packets are dropped */
+ FAL_MAC_CPY_TO_CPU, /**< packets are copyed to cpu */
+ FAL_MAC_RDT_TO_CPU /**< packets are redirected to cpu */
+ } fal_fwd_cmd_t;
+
+ typedef enum
+ {
+ FAL_BYTE_BASED = 0,
+ FAL_FRAME_BASED,
+ FAL_RATE_MODE_BUTT
+ } fal_traffic_unit_t;
+
+ typedef a_uint32_t fal_queue_t;
+
+#define FAL_SVL_FID 0xffff
+
+
+ /**
+ @brief This enum defines packets transmitted out vlan tagged mode.
+ */
+ typedef enum
+ {
+ FAL_EG_UNMODIFIED = 0, /**< egress transmit packets unmodified */
+ FAL_EG_UNTAGGED, /**< egress transmit packets without vlan tag*/
+ FAL_EG_TAGGED, /**< egress transmit packets with vlan tag */
+ FAL_EG_HYBRID, /**< egress transmit packets in hybrid tag mode */
+ FAL_EG_UNTOUCHED,
+ FAL_EG_MODE_BUTT
+ } fal_pt_1q_egmode_t;
+
+#define FAL_NEXT_ENTRY_FIRST_ID 0xffffffff
+
+ typedef struct
+ {
+ a_uint32_t counter_id;
+ a_uint32_t ingress_packet;
+ a_uint32_t ingress_byte;
+ a_uint32_t egress_packet;
+ a_uint32_t egress_byte;
+ } fal_counter_entry_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_TYPE_H_ */
+/**
+ * @}
+ */
diff --git a/include/fal/fal_uk_if.h b/include/fal/fal_uk_if.h
new file mode 100644
index 0000000..c74be77
--- /dev/null
+++ b/include/fal/fal_uk_if.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _FAL_UK_IF_H_
+#define _FAL_UK_IF_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+#include "init/ssdk_init.h"
+
+ sw_error_t
+ sw_uk_exec(a_uint32_t api_id, ...);
+
+ sw_error_t
+ ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+ sw_error_t
+ ssdk_cleanup(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _FAL_UK_IF_H_ */
+
+
diff --git a/include/fal/fal_vlan.h b/include/fal/fal_vlan.h
new file mode 100644
index 0000000..eb8df0c
--- /dev/null
+++ b/include/fal/fal_vlan.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_vlan FAL_VLAN
+ * @{
+ */
+#ifndef _FAL_VLAN_H
+#define _FAL_VLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+#include "fal/fal_type.h"
+
+ /**
+ @brief This structure defines vlan entry.
+ */
+ typedef struct
+ {
+ a_uint16_t vid; /**< vlan entry id */
+ a_uint16_t fid; /**< filter data base id*/
+ fal_pbmp_t mem_ports; /**< member port bit map */
+ fal_pbmp_t tagged_ports; /**< bit map of tagged infomation for member port*/
+ fal_pbmp_t untagged_ports; /**< bit map of untagged infomation for member port*/
+ fal_pbmp_t unmodify_ports;/**< bit map of unmodified infomation for member port*/
+ fal_pbmp_t u_ports;
+ a_bool_t learn_dis; /**< disable address learning*/
+ a_bool_t vid_pri_en; /**< enable 802.1p*/
+ a_uint8_t vid_pri; /**< vlaue of 802.1p when enable vid_pri_en*/
+ } fal_vlan_t;
+
+
+ sw_error_t
+ fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry);
+
+
+
+ sw_error_t
+ fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+ sw_error_t
+ fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ sw_error_t
+ fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ sw_error_t
+ fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+
+ sw_error_t
+ fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+ sw_error_t
+ fal_vlan_reset(a_uint32_t dev_id);
+
+
+ sw_error_t
+ fal_vlan_flush(a_uint32_t dev_id);
+
+
+ sw_error_t
+ fal_vlan_init(a_uint32_t dev_id);
+
+
+ sw_error_t
+ fal_vlan_cleanup(void);
+
+
+ sw_error_t
+ fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+ sw_error_t
+ fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+ sw_error_t
+ fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+ sw_error_t
+ fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+ sw_error_t
+ fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable);
+
+
+ sw_error_t
+ fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _FAL_VLAN_H */
+/**
+ * @}
+ */
diff --git a/include/hsl/athena/athena_api.h b/include/hsl/athena/athena_api.h
new file mode 100644
index 0000000..2917c70
--- /dev/null
+++ b/include/hsl/athena/athena_api.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_API_H_
+#define _ATHENA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, athena_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, athena_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, athena_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, athena_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, athena_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, athena_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, athena_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, athena_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, athena_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, athena_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, athena_port_igmps_status_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, athena_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, athena_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, athena_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, athena_port_hibernate_get),
+
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, athena_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, athena_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_MEM_UPDATE, athena_vlan_member_update), \
+ SW_API_DEF(SW_API_VLAN_FIND, athena_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, athena_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, athena_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, athena_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, athena_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, athena_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, athena_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, athena_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, athena_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, athena_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, athena_portvlan_member_get), \
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, athena_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, athena_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,athena_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, athena_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIRST, athena_fdb_first), \
+ SW_API_DEF(SW_API_FDB_NEXT, athena_fdb_next),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIRST) \
+ SW_API_DESC(SW_API_FDB_NEXT)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, athena_get_mib_info),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, athena_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, athena_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, athena_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, athena_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, athena_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, athena_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, athena_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ MIB_API \
+ PORTCONTROL_API \
+ PORTVLAN_API \
+ VLAN_API \
+ FDB_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL)
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_API_H_ */
diff --git a/include/hsl/athena/athena_fdb.h b/include/hsl/athena/athena_fdb.h
new file mode 100644
index 0000000..f444f0e
--- /dev/null
+++ b/include/hsl/athena/athena_fdb.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_FDB_H
+#define _ATHENA_FDB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t athena_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ATHENA_FDB_INIT(rv, dev_id) \
+ { \
+ rv = athena_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ATHENA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id,
+ a_uint32_t flag);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * addr);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ATHENA_FDB_H */
+
diff --git a/include/hsl/athena/athena_init.h b/include/hsl/athena/athena_init.h
new file mode 100644
index 0000000..4514cec
--- /dev/null
+++ b/include/hsl/athena/athena_init.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_INIT_H_
+#define _ATHENA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+ sw_error_t
+ athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+ sw_error_t
+ athena_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ athena_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_INIT_H_ */
+
+
diff --git a/include/hsl/athena/athena_mib.h b/include/hsl/athena/athena_mib.h
new file mode 100644
index 0000000..71d3b7c
--- /dev/null
+++ b/include/hsl/athena/athena_mib.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_MIB_H
+#define _ATHENA_MIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ athena_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ATHENA_MIB_INIT(rv, dev_id) \
+ { \
+ rv = athena_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ATHENA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_MIB_H */
diff --git a/include/hsl/athena/athena_port_ctrl.h b/include/hsl/athena/athena_port_ctrl.h
new file mode 100644
index 0000000..76c4691
--- /dev/null
+++ b/include/hsl/athena/athena_port_ctrl.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ATHENA_PORT_CTRL_H
+#define _ATHENA_PORT_CTRL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t athena_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ATHENA_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = athena_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ATHENA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ATHENA_PORT_CTRL_H */
diff --git a/include/hsl/athena/athena_portvlan.h b/include/hsl/athena/athena_portvlan.h
new file mode 100644
index 0000000..a71f0cb
--- /dev/null
+++ b/include/hsl/athena/athena_portvlan.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_PORTVLAN_H
+#define _ATHENA_PORTVLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t
+ athena_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ATHENA_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = athena_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ATHENA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t *mem_port_map);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_PORTVLAN_H */
diff --git a/include/hsl/athena/athena_reg.h b/include/hsl/athena/athena_reg.h
new file mode 100644
index 0000000..0ed1f04
--- /dev/null
+++ b/include/hsl/athena/athena_reg.h
@@ -0,0 +1,2148 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_REG_H
+#define _ATHENA_REG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+ /**
+ * Athena Mask Control Register
+ */
+#define MASK_CTL "mask"
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 0
+
+#define SOFT_RST "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define MII_CLK_SEL "mask_clks"
+#define MASK_CTL_MII_CLK_SEL_BOFFSET 24
+#define MASK_CTL_MII_CLK_SEL_BLEN 1
+#define MASK_CTL_MII_CLK_SEL_FLAG HSL_RW
+
+#define RMII_PHY_RX_SEL "mask_prxs"
+#define MASK_CTL_RMII_PHY_RX_SEL_BOFFSET 23
+#define MASK_CTL_RMII_PHY_RX_SEL_BLEN 1
+#define MASK_CTL_RMII_PHY_RX_SEL_FLAG HSL_RW
+
+#define RMII_PHY_TX_SEL "mask_ptxs"
+#define MASK_CTL_RMII_PHY_TX_SEL_BOFFSET 22
+#define MASK_CTL_RMII_PHY_TX_SEL_BLEN 1
+#define MASK_CTL_RMII_PHY_TX_SEL_FLAG HSL_RW
+
+#define RMII_MAC_RX_SEL "mask_mrxs"
+#define MASK_CTL_RMII_MAC_RX_SEL_BOFFSET 21
+#define MASK_CTL_RMII_MAC_RX_SEL_BLEN 1
+#define MASK_CTL_RMII_MAC_RX_SEL_FLAG HSL_RW
+
+#define RMII_MAC_TX_SEL "mask_mtxs"
+#define MASK_CTL_RMII_MAC_TX_SEL_BOFFSET 20
+#define MASK_CTL_RMII_MAC_TX_SEL_BLEN 1
+#define MASK_CTL_RMII_MAC_TX_SEL_FLAG HSL_RW
+
+#define LOAD_EEPROM "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+ /**
+ * Global Interrupt Register
+ */
+#define GLOBAL_INT "gint"
+#define GLOBAL_INT_ID 1
+#define GLOBAL_INT_OFFSET 0x0010
+#define GLOBAL_INT_E_LENGTH 4
+#define GLOBAL_INT_E_OFFSET 0
+#define GLOBAL_INT_NR_E 0
+
+#define GLB_QM_ERR_CNT "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO
+
+#define GLB_LOOKUP_ERR "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLB_QM_ERR "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW
+
+#define GLB_HW_INI_DONE "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW
+
+#define GLB_MIB_INI "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN 1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW
+
+#define GLB_MIB_DONE "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW
+
+#define GLB_BIST_DONE "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW
+
+#define GLB_VT_MISS_VIO "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLB_VT_MEM_VIO "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLB_VT_DONE "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN 1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW
+
+#define GLB_QM_INI "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7
+#define GLOBAL_INT_GLB_QM_INI_BLEN 1
+#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW
+
+#define GLB_AT_INI "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6
+#define GLOBAL_INT_GLB_AT_INI_BLEN 1
+#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW
+
+#define GLB_ARL_FULL "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW
+
+#define GLB_ARL_DONE "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW
+
+#define GLB_MDIO_DONE "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW
+
+#define GLB_PHY_INT "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN 1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW
+
+#define GLB_EEPROM_ERR "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW
+
+#define GLB_EEPROM_INT "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW
+
+ /**
+ * Global Interrupt Mask Register
+ */
+#define GLOBAL_INT_MASK "gintm"
+#define GLOBAL_INT_MASK_ID 2
+#define GLOBAL_INT_MASK_OFFSET 0x0014
+#define GLOBAL_INT_MASK_E_LENGTH 4
+#define GLOBAL_INT_MASK_E_OFFSET 0
+#define GLOBAL_INT_MASK_NR_E 0
+
+#define GLBM_LOOKUP_ERR "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLBM_QM_ERR "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW
+
+#define GLBM_HW_INI_DONE "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW
+
+#define GLBM_MIB_INI "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW
+
+#define GLBM_MIB_DONE "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW
+
+#define GLBM_BIST_DONE "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW
+
+#define GLBM_VT_MISS_VIO "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLBM_VT_MEM_VIO "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLBM_VT_DONE "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW
+
+#define GLBM_QM_INI "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW
+
+#define GLBM_AT_INI "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW
+
+#define GLBM_ARL_FULL "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW
+
+#define GLBM_ARL_DONE "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW
+
+#define GLBM_MDIO_DONE "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW
+
+#define GLBM_PHY_INT "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW
+
+#define GLBM_EEPROM_ERR "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW
+
+#define GLBM_EEPROM_INT "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW
+
+
+ /**
+ * Global MAC Address Register
+ */
+//high
+#define GLOBAL_MAC_ADDR0 "gmac0"
+#define GLOBAL_MAC_ADDR0_ID 3
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 0
+
+#define GLB_BYTE4 "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5 "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+
+//low
+#define GLOBAL_MAC_ADDR1 "gmac1"
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 0
+
+#define GLB_BYTE0 "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1 "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2 "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3 "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+ /**
+ * Global Control Register
+ */
+#define GLOBAL_CTL "gctl"
+#define GLOBAL_CTL_ID 5
+#define GLOBAL_CTL_OFFSET 0x0030
+#define GLOBAL_CTL_E_LENGTH 4
+#define GLOBAL_CTL_E_OFFSET 0
+#define GLOBAL_CTL_NR_E 0
+
+#define WEIGHT_PRIORITY "gctl_wpri"
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET 31
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN 1
+#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG HSL_RW
+
+#define RATE_DROP_EN "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 30
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW
+
+#define QM_PRI_MODE "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 29
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW
+
+#define MIX_PRIORITY "gctl_mpri"
+#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET 28
+#define GLOBAL_CTL_MIX_PRIORITY_BLEN 1
+#define GLOBAL_CTL_MIX_PRIORITY_FLAG HSL_RW
+
+#define RATE_CRE_LIMIT "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW
+
+#define RATE_TIME_SLOT "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW
+
+#define RELOAD_TIMER "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW
+
+#define QM_CNT_LOCK "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO
+
+#define BROAD_DROP_EN "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW
+
+#define BROAD_STORM_CTRL "gctl_bsct"
+#define GLOBAL_CTL_BROAD_STORM_CTRL_BOFFSET 16
+#define GLOBAL_CTL_BROAD_STORM_CTRL_BLEN 2
+#define GLOBAL_CTL_BROAD_STORM_CTRL_FLAG HSL_RW
+
+#define BROAD_STORM_EN "gctl_bsen"
+#define GLOBAL_CTL_BROAD_STORM_EN_BOFFSET 11
+#define GLOBAL_CTL_BROAD_STORM_EN_BLEN 1
+#define GLOBAL_CTL_BROAD_STORM_EN_FLAG HSL_RW
+
+#define MAX_FRAME_SIZE "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 11
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW
+
+ /**
+ * Flow Control Register
+ */
+#define FLOW_CTL "fctl"
+#define FLOW_CTL_ID 6
+#define FLOW_CTL_OFFSET 0x0034
+#define FLOW_CTL_E_LENGTH 4
+#define FLOW_CTL_E_OFFSET 0
+#define FLOW_CTL_NR_E 0
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL_TEST_PAUSE_BLEN 1
+#define FLOW_CTL_TEST_PAUSE_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl_pofft"
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN 7
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_ON_THRES "fctl_pont"
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN 7
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET 8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET 0
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+ /**
+ * QM Control Register
+ */
+#define QM_CTL "qmct"
+#define QM_CTL_ID 7
+#define QM_CTL_OFFSET 0x0038
+#define QM_CTL_E_LENGTH 4
+#define QM_CTL_E_OFFSET 0
+#define QM_CTL_NR_E 0
+
+#define QM_ERR_RST_EN "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31
+#define QM_CTL_QM_ERR_RST_EN_BLEN 1
+#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW
+
+#define LOOKUP_ERR_RST_EN "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW
+
+#define FLOOD_TO_CPU_EN "qmct_fdcpuen"
+#define QM_CTL_FLOOD_TO_CPU_EN_BOFFSET 10
+#define QM_CTL_FLOOD_TO_CPU_EN_BLEN 1
+#define QM_CTL_FLOOD_TO_CPU_EN_FLAG HSL_RW
+
+#define QM_FUNC_TEST "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET 9
+#define QM_CTL_QM_FUNC_TEST_BLEN 1
+#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW
+
+#define MS_FC_EN "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET 8
+#define QM_CTL_MS_FC_EN_BLEN 1
+#define QM_CTL_MS_FC_EN_FLAG HSL_RW
+
+#define FLOW_DROP_EN "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET 7
+#define QM_CTL_FLOW_DROP_EN_BLEN 1
+#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_CNT "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTL_FLOW_DROP_CNT_BLEN 5
+#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW
+
+ /**
+ * QM Error Register
+ */
+#define QM_ERR "qmer"
+#define QM_ERR_ID 8
+#define QM_ERR_OFFSET 0x003C
+#define QM_ERR_E_LENGTH 4
+#define QM_ERR_E_OFFSET 0
+#define QM_ERR_NR_E 0
+
+#define QM_ERR_DATA "qmer_data"
+#define QM_ERR_QM_ERR_DATA_BOFFSET 0
+#define QM_ERR_QM_ERR_DATA_BLEN 32
+#define QM_ERR_QM_ERR_DATA_FLAG HSL_RO
+
+ /**
+ * Vlan Table Function Register
+ */
+//high
+#define VLAN_TABLE_FUNC0 "vtbf0"
+#define VLAN_TABLE_FUNC0_ID 9
+#define VLAN_TABLE_FUNC0_OFFSET 0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 0
+
+#define VT_PRI_EN "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+#define VLAN_ID "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_BUSY "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW
+
+#define VT_FUNC "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW
+
+//low
+#define VLAN_TABLE_FUNC1 "vtbf1"
+#define VLAN_TABLE_FUNC1_ID 10
+#define VLAN_TABLE_FUNC1_OFFSET 0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 0
+
+#define PORT_TAG_EN "vtbf_pgen"
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BOFFSET 12
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_BLEN 20
+#define VLAN_TABLE_FUNC1_PORT_TAG_EN_FLAG HSL_RW
+
+#define VT_VALID "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW
+
+#define VID_MEM "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 10
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW
+
+ /**
+ * Address Table Function Register
+ */
+#define ADDR_TABLE_FUNC0 "atbf0"
+#define ADDR_TABLE_FUNC0_ID 11
+#define ADDR_TABLE_FUNC0_OFFSET 0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 0
+
+#define AT_ADDR_BYTE4 "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5 "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+#define AT_FULL_VIO "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW
+
+#define AT_BUSY "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW
+
+#define AT_FUNC "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW
+
+
+#define ADDR_TABLE_FUNC1 "atbf1"
+#define ADDR_TABLE_FUNC1_ID 12
+#define ADDR_TABLE_FUNC1_OFFSET 0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 0
+
+#define AT_ADDR_BYTE0 "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1 "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+#define AT_ADDR_BYTE2 "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3 "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW
+
+
+#define ADDR_TABLE_FUNC2 "atbf2"
+#define ADDR_TABLE_FUNC2_ID 13
+#define ADDR_TABLE_FUNC2_OFFSET 0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 0
+
+#define COPY_TO_CPU "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define SA_DROP_EN "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 16
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW
+
+#define AT_STATUS "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 14
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 2
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+#define MIRROR_EN "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_PRI "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW
+
+#define DES_PORT "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 10
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW
+
+ /**
+ * Address Table Control Register
+ */
+#define ADDR_TABLE_CTL "atbc"
+#define ADDR_TABLE_CTL_ID 14
+#define ADDR_TABLE_CTL_OFFSET 0x005C
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 0
+
+#define ARP_EN "atbc_arpe"
+#define ADDR_TABLE_CTL_ARP_EN_BOFFSET 20
+#define ADDR_TABLE_CTL_ARP_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARP_EN_FLAG HSL_RW
+
+#define ARL_INI_EN "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define BPDU_EN "atbc_bpdue"
+#define ADDR_TABLE_CTL_BPDU_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_BPDU_EN_BLEN 1
+#define ADDR_TABLE_CTL_BPDU_EN_FLAG HSL_RW
+
+#define AGE_EN "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define AGE_TIME "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+ /**
+ * IP Priority Mapping Register
+ */
+#define IP_PRI_MAPPING0 "imap0"
+#define IP_PRI_MAPPING0_ID 15
+#define IP_PRI_MAPPING0_OFFSET 0x0060
+#define IP_PRI_MAPPING0_E_LENGTH 4
+#define IP_PRI_MAPPING0_E_OFFSET 0
+#define IP_PRI_MAPPING0_NR_E 0
+
+#define IP_0X3C "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW
+
+#define IP_0X38 "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW
+
+#define IP_0X34 "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW
+
+#define IP_0X30 "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW
+
+#define IP_0X2C "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW
+
+#define IP_0X28 "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW
+
+#define IP_0X24 "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW
+
+#define IP_0X20 "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW
+
+#define IP_0X1C "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW
+
+#define IP_0X18 "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW
+
+#define IP_0X14 "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW
+
+#define IP_0X10 "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW
+
+#define IP_0X0C "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW
+
+#define IP_0X08 "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW
+
+#define IP_0X04 "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW
+
+#define IP_0X00 "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW
+
+#define IP_PRI_MAPPING1 "imap1"
+#define IP_PRI_MAPPING1_ID 16
+#define IP_PRI_MAPPING1_OFFSET 0x0064
+#define IP_PRI_MAPPING1_E_LENGTH 4
+#define IP_PRI_MAPPING1_E_OFFSET 0
+#define IP_PRI_MAPPING1_NR_E 0
+
+#define IP_0X7C "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW
+
+#define IP_0X78 "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW
+
+#define IP_0X74 "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW
+
+#define IP_0X70 "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW
+
+#define IP_0X6C "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW
+
+#define IP_0X68 "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW
+
+#define IP_0X64 "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW
+
+#define IP_0X60 "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW
+
+#define IP_0X5C "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW
+
+#define IP_0X58 "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW
+
+#define IP_0X54 "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW
+
+#define IP_0X50 "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW
+
+#define IP_0X4C "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW
+
+#define IP_0X48 "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW
+
+#define IP_0X44 "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW
+
+#define IP_0X40 "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW
+
+
+#define IP_PRI_MAPPING2 "imap2"
+#define IP_PRI_MAPPING2_ID 17
+#define IP_PRI_MAPPING2_OFFSET 0x0068
+#define IP_PRI_MAPPING2_E_LENGTH 4
+#define IP_PRI_MAPPING2_E_OFFSET 0
+#define IP_PRI_MAPPING2_NR_E 0
+
+#define IP_0XBC "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW
+
+#define IP_0XB8 "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW
+
+#define IP_0XB4 "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW
+
+#define IP_0XB0 "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW
+
+#define IP_0XAC "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW
+
+#define IP_0XA8 "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW
+
+#define IP_0XA4 "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW
+
+#define IP_0XA0 "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW
+
+#define IP_0X9C "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW
+
+#define IP_0X98 "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW
+
+#define IP_0X94 "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW
+
+#define IP_0X90 "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW
+
+#define IP_0X8C "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW
+
+#define IP_0X88 "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW
+
+#define IP_0X84 "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW
+
+#define IP_0X80 "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW
+
+#define IP_PRI_MAPPING3 "imap3"
+#define IP_PRI_MAPPING3_ID 18
+#define IP_PRI_MAPPING3_OFFSET 0x006C
+#define IP_PRI_MAPPING3_E_LENGTH 4
+#define IP_PRI_MAPPING3_E_OFFSET 0
+#define IP_PRI_MAPPING3_NR_E 0
+
+#define IP_0XFC "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW
+
+#define IP_0XF8 "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW
+
+#define IP_0XF4 "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW
+
+#define IP_0XF0 "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW
+
+#define IP_0XEC "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW
+
+#define IP_0XE8 "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW
+
+#define IP_0XE4 "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW
+
+#define IP_0XE0 "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW
+
+#define IP_0XDC "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW
+
+#define IP_0XD8 "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW
+
+#define IP_0XD4 "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW
+
+#define IP_0XD0 "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW
+
+#define IP_0XCC "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW
+
+#define IP_0XC8 "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW
+
+#define IP_0XC4 "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW
+
+#define IP_0XC0 "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW
+
+ /**
+ * Tag Priority Mapping Register
+ */
+#define TAG_PRI_MAPPING "tpmap"
+#define TAG_PRI_MAPPING_ID 19
+#define TAG_PRI_MAPPING_OFFSET 0x0070
+#define TAG_PRI_MAPPING_E_LENGTH 4
+#define TAG_PRI_MAPPING_E_OFFSET 0
+#define TAG_PRI_MAPPING_NR_E 0
+
+#define TAG_0X07 "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW
+
+#define TAG_0X06 "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW
+
+#define TAG_0X05 "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW
+
+#define TAG_0X04 "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW
+
+#define TAG_0X03 "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW
+
+#define TAG_0X02 "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW
+
+#define TAG_0X01 "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW
+
+#define TAG_0X00 "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW
+
+ /**
+ * Cpu Port Register
+ */
+#define CPU_PORT "cpup"
+#define CPU_PORT_ID 20
+#define CPU_PORT_OFFSET 0x0078
+#define CPU_PORT_E_LENGTH 4
+#define CPU_PORT_E_OFFSET 0
+#define CPU_PORT_NR_E 0
+
+#define CPU_PORT_EN "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET 8
+#define CPU_PORT_CPU_PORT_EN_BLEN 1
+#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW
+
+#define RMII_CUT "cpup_rmcut"
+#define CPU_PORT_RMII_CUT_BOFFSET 0
+#define CPU_PORT_RMII_CUT_BLEN 1
+#define CPU_PORT_RMII_CUT_FLAG HSL_RW
+
+ /**
+ * MIB Function Register
+ */
+#define MIB_CNT "mibcnt"
+#define MIB_CNT_ID 21
+#define MIB_CNT_OFFSET 0x0080
+#define MIB_CNT_E_LENGTH 4
+#define MIB_CNT_E_OFFSET 0
+#define MIB_CNT_NR_E 0
+
+#define MIB_FUNC "mibcnt_mibf"
+#define MIB_CNT_MIB_FUNC_BOFFSET 24
+#define MIB_CNT_MIB_FUNC_BLEN 3
+#define MIB_CNT_MIB_FUNC_FLAG HSL_RW
+
+#define MIB_BUSY "mibcnt_mibb"
+#define MIB_CNT_MIB_BUSY_BOFFSET 17
+#define MIB_CNT_MIB_BUSY_BLEN 1
+#define MIB_CNT_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN "mibcnt_mibhe"
+#define MIB_CNT_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_CNT_MIB_AT_HALF_EN_BLEN 1
+#define MIB_CNT_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER "mibcnt_mibt"
+#define MIB_CNT_MIB_TIMER_BOFFSET 0
+#define MIB_CNT_MIB_TIMER_BLEN 16
+#define MIB_CNT_MIB_TIMER_FLAG HSL_RW
+
+ /**
+ * SPI Interface Register
+ */
+#define SPI_INTERFACE "spi"
+#define SPI_INTERFACE_ID 22
+#define SPI_INTERFACE_OFFSET 0x0090
+#define SPI_INTERFACE_E_LENGTH 4
+#define SPI_INTERFACE_E_OFFSET 0
+#define SPI_INTERFACE_NR_E 0
+
+#define DEBUG_OEN "spi_dben"
+#define SPI_INTERFACE_DEBUG_OEN_BOFFSET 7
+#define SPI_INTERFACE_DEBUG_OEN_BLEN 25
+#define SPI_INTERFACE_DEBUG_OEN_FLAG HSL_RO
+
+#define SPI_EN "spi_spien"
+#define SPI_INTERFACE_SPI_EN_BOFFSET 5
+#define SPI_INTERFACE_SPI_EN_BLEN 1
+#define SPI_INTERFACE_SPI_EN_FLAG HSL_RO
+
+#define SPI_SPEED "spi_spisp"
+#define SPI_INTERFACE_SPI_SPEED_BOFFSET 4
+#define SPI_INTERFACE_SPI_SPEED_BLEN 1
+#define SPI_INTERFACE_SPI_SPEED_FLAG HSL_RO
+
+#define UART_SPEED "spi_utsp"
+#define SPI_INTERFACE_UART_SPEED_BOFFSET 3
+#define SPI_INTERFACE_UART_SPEED_BLEN 1
+#define SPI_INTERFACE_UART_SPEED_FLAG HSL_RO
+
+#define RMII_EN "spi_rmen"
+#define SPI_INTERFACE_RMII_EN_BOFFSET 2
+#define SPI_INTERFACE_RMII_EN_BLEN 1
+#define SPI_INTERFACE_RMII_EN_FLAG HSL_RO
+
+#define MII_EN "spi_miien"
+#define SPI_INTERFACE_MII_EN_BOFFSET 1
+#define SPI_INTERFACE_MII_EN_BLEN 1
+#define SPI_INTERFACE_MII_EN_FLAG HSL_RO
+
+#define SPI_SIZE "spi_spisz"
+#define SPI_INTERFACE_SPI_SIZE_BOFFSET 0
+#define SPI_INTERFACE_SPI_SIZE_BLEN 1
+#define SPI_INTERFACE_SPI_SIZE_FLAG HSL_RO
+
+ /**
+ * MDIO High Address Register
+ */
+#define MDIO_HIGH_ADDR "mdiohd"
+#define MDIO_HIGH_ADDR_ID 23
+#define MDIO_HIGH_ADDR_OFFSET 0x0094
+#define MDIO_HIGH_ADDR_E_LENGTH 4
+#define MDIO_HIGH_ADDR_E_OFFSET 0
+#define MDIO_HIGH_ADDR_NR_E 0
+
+#define MDIO_HA "mdiohd_ha"
+#define MDIO_HIGH_ADDR_MDIO_HA_BOFFSET 0
+#define MDIO_HIGH_ADDR_MDIO_HA_BLEN 9
+#define MDIO_HIGH_ADDR_MDIO_HA_FLAG HSL_RW
+
+ /**
+ * Destination IP Address Register
+ */
+#define DIP_ADDR "dip"
+#define DIP_ADDR_ID 24
+#define DIP_ADDR_OFFSET 0x0098
+#define DIP_ADDR_E_LENGTH 4
+#define DIP_ADDR_E_OFFSET 0
+#define DIP_ADDR_NR_E 0
+
+#define DES_IP_ADDR "dip_addr"
+#define DIP_ADDR_DES_IP_ADDR_BOFFSET 0
+#define DIP_ADDR_DES_IP_ADDR_BLEN 32
+#define DIP_ADDR_DES_IP_ADDR_FLAG HSL_RW
+
+ /**
+ * BIST Control Register
+ */
+#define BIST_CTL "bctl"
+#define BIST_CTL_ID 25
+#define BIST_CTL_OFFSET 0x00A0
+#define BIST_CTL_E_LENGTH 4
+#define BIST_CTL_E_OFFSET 0
+#define BIST_CTL_NR_E 0
+
+#define BIST_BUSY "bctl_busy"
+#define BIST_CTL_BIST_BUSY_BOFFSET 31
+#define BIST_CTL_BIST_BUSY_BLEN 1
+#define BIST_CTL_BIST_BUSY_FLAG HSL_RW
+
+#define BIST_ERR_MEM "bctl_errmem"
+#define BIST_CTL_BIST_ERR_MEM_BOFFSET 24
+#define BIST_CTL_BIST_ERR_MEM_BLEN 4
+#define BIST_CTL_BIST_ERR_MEM_FLAG HSL_RO
+
+#define BIST_PTN_EN_2 "bctl_ptnen2"
+#define BIST_CTL_BIST_PTN_EN_2_BOFFSET 22
+#define BIST_CTL_BIST_PTN_EN_2_BLEN 1
+#define BIST_CTL_BIST_PTN_EN_2_FLAG HSL_RW
+
+#define BIST_PTN_EN_1 "bctl_ptnen1"
+#define BIST_CTL_BIST_PTN_EN_1_BOFFSET 21
+#define BIST_CTL_BIST_PTN_EN_1_BLEN 1
+#define BIST_CTL_BIST_PTN_EN_1_FLAG HSL_RW
+
+#define BIST_PTN_EN_0 "bctl_ptnen0"
+#define BIST_CTL_BIST_PTN_EN_0_BOFFSET 20
+#define BIST_CTL_BIST_PTN_EN_0_BLEN 1
+#define BIST_CTL_BIST_PTN_EN_0_FLAG HSL_RW
+
+#define BIST_ERR_PTN "bctl_errptn"
+#define BIST_CTL_BIST_ERR_PTN_BOFFSET 16
+#define BIST_CTL_BIST_ERR_PTN_BLEN 2
+#define BIST_CTL_BIST_ERR_PTN_FLAG HSL_RO
+
+#define BIST_ERR_CNT "bctl_errcnt"
+#define BIST_CTL_BIST_ERR_CNT_BOFFSET 13
+#define BIST_CTL_BIST_ERR_CNT_BLEN 3
+#define BIST_CTL_BIST_ERR_CNT_FLAG HSL_RO
+
+#define BIST_ERR_ADDR "bctl_errad"
+#define BIST_CTL_BIST_ERR_ADDR_BOFFSET 0
+#define BIST_CTL_BIST_ERR_ADDR_BLEN 13
+#define BIST_CTL_BIST_ERR_ADDR_FLAG HSL_RO
+
+ /**
+ * Debug Control Register
+ */
+#define DEBUG_CTL0 "dctl0"
+#define DEBUG_CTL0_ID 26
+#define DEBUG_CTL0_OFFSET 0x00F0
+#define DEBUG_CTL0_E_LENGTH 4
+#define DEBUG_CTL0_E_OFFSET 0
+#define DEBUG_CTL0_NR_E 0
+
+#define DEBUG_SEL "dctl_sel"
+#define DEBUG_CTL0_DEBUG_SEL_BOFFSET 16
+#define DEBUG_CTL0_DEBUG_SEL_BLEN 8
+#define DEBUG_CTL0_DEBUG_SEL_FLAG HSL_RW
+
+#define DEBUG_PORT_NUM "dctl_ptnum"
+#define DEBUG_CTL0_DEBUG_PORT_NUM_BOFFSET 8
+#define DEBUG_CTL0_DEBUG_PORT_NUM_BLEN 4
+#define DEBUG_CTL0_DEBUG_PORT_NUM_FLAG HSL_RW
+
+#define DEBUG_ADDR "dctl_addr"
+#define DEBUG_CTL0_DEBUG_ADDR_BOFFSET 0
+#define DEBUG_CTL0_DEBUG_ADDR_BLEN 8
+#define DEBUG_CTL0_DEBUG_ADDR_FLAG HSL_RW
+
+
+#define DEBUG_CTL1 "dctl1"
+#define DEBUG_CTL1_ID 27
+#define DEBUG_CTL1_OFFSET 0x00F4
+#define DEBUG_CTL1_E_LENGTH 4
+#define DEBUG_CTL1_E_OFFSET 0
+#define DEBUG_CTL1_NR_E 0
+
+#define DEBUG_DATA "dctl_data"
+#define DEBUG_CTL1_DEBUG_DATA_BOFFSET 0
+#define DEBUG_CTL1_DEBUG_DATA_BLEN 32
+#define DEBUG_CTL1_DEBUG_DATA_FLAG HSL_RO
+
+ /**
+ * QM Debug Control Register
+ */
+#define QM_DEBUG_CTL "qmdctl"
+#define QM_DEBUG_CTL_ID 28
+#define QM_DEBUG_CTL_OFFSET 0x00F8
+#define QM_DEBUG_CTL_E_LENGTH 4
+#define QM_DEBUG_CTL_E_OFFSET 0
+#define QM_DEBUG_CTL_NR_E 0
+
+#define QM_DBG_CTRL "qmdctl_dbgctl"
+#define QM_DEBUG_CTL_QM_DBG_CTRL_BOFFSET 0
+#define QM_DEBUG_CTL_QM_DBG_CTRL_BLEN 32
+#define QM_DEBUG_CTL_QM_DBG_CTRL_FLAG HSL_RW
+
+ /**
+ * Port Status Register
+ */
+#define PORT_STATUS "ptsts"
+#define PORT_STATUS_ID 29
+#define PORT_STATUS_OFFSET 0x0100
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0100
+#define PORT_STATUS_NR_E 6
+
+#define LINK_ASYN_PAUSE "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO
+
+#define LINK_PAUSE "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET 10
+#define PORT_STATUS_LINK_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO
+
+#define LINK_EN "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define DUPLEX_MODE "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+ /**
+ * Port Control Register
+ */
+#define PORT_CTL "pctl"
+#define PORT_CTL_ID 30
+#define PORT_CTL_OFFSET 0x0104
+#define PORT_CTL_E_LENGTH 4
+#define PORT_CTL_E_OFFSET 0x0100
+#define PORT_CTL_NR_E 6
+
+#define ING_MIRROR_EN "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17
+#define PORT_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define EG_MIRROR_EN "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16
+#define PORT_CTL_EG_MIRROR_EN_BLEN 1
+#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW
+
+#define LEARN_EN "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET 14
+#define PORT_CTL_LEARN_EN_BLEN 1
+#define PORT_CTL_LEARN_EN_FLAG HSL_RW
+
+#define SINGLE_VLAN_EN "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW
+
+#define MAC_LOOP_BACK "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN 1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW
+
+#define HEAD_EN "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET 11
+#define PORT_CTL_HEAD_EN_BLEN 1
+#define PORT_CTL_HEAD_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10
+#define PORT_CTL_IGMP_MLD_EN_BLEN 1
+#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW
+
+#define EG_VLAN_MODE "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8
+#define PORT_CTL_EG_VLAN_MODE_BLEN 2
+#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW
+
+#define LEARN_ONE_LOCK "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW
+
+#define PORT_STATE "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET 0
+#define PORT_CTL_PORT_STATE_BLEN 3
+#define PORT_CTL_PORT_STATE_FLAG HSL_RW
+
+ /**
+ * Port Based Vlan Register
+ */
+#define PORT_BASE_VLAN "pbvlan"
+#define PORT_BASE_VLAN_ID 31
+#define PORT_BASE_VLAN_OFFSET 0x0108
+#define PORT_BASE_VLAN_E_LENGTH 4
+#define PORT_BASE_VLAN_E_OFFSET 0x0100
+#define PORT_BASE_VLAN_NR_E 6
+
+#define DOT1Q_MODE "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW
+
+#define ING_PRI "pbvlan_ingpri"
+#define PORT_BASE_VLAN_ING_PRI_BOFFSET 28
+#define PORT_BASE_VLAN_ING_PRI_BLEN 2
+#define PORT_BASE_VLAN_ING_PRI_FLAG HSL_RW
+
+#define EG_TAG_PRI0 "pbvlan_egtpri"
+#define PORT_BASE_VLAN_EG_TAG_PRI0_BOFFSET 27
+#define PORT_BASE_VLAN_EG_TAG_PRI0_BLEN 1
+#define PORT_BASE_VLAN_EG_TAG_PRI0_FLAG HSL_RW
+
+#define PORT_VID_MEM "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW
+
+#define PORT_VID "pbvlan_ptvid"
+#define PORT_BASE_VLAN_PORT_VID_BOFFSET 0
+#define PORT_BASE_VLAN_PORT_VID_BLEN 12
+#define PORT_BASE_VLAN_PORT_VID_FLAG HSL_RW
+
+ /**
+ * Port Rate Limit Register
+ */
+#define RATE_LIMIT "rlmt"
+#define RATE_LIMIT_ID 32
+#define RATE_LIMIT_OFFSET 0x010C
+#define RATE_LIMIT_E_LENGTH 4
+#define RATE_LIMIT_E_OFFSET 0x0100
+#define RATE_LIMIT_NR_E 6
+
+#define EGRESS_RATE_EN "rlmt_egrateen"
+#define RATE_LIMIT_EGRESS_RATE_EN_BOFFSET 25
+#define RATE_LIMIT_EGRESS_RATE_EN_BLEN 1
+#define RATE_LIMIT_EGRESS_RATE_EN_FLAG HSL_RW
+
+#define INGRESS_RATE_EN "rlmt_ingrateen"
+#define RATE_LIMIT_INGRESS_RATE_EN_BOFFSET 24
+#define RATE_LIMIT_INGRESS_RATE_EN_BLEN 1
+#define RATE_LIMIT_INGRESS_RATE_EN_FLAG HSL_RW
+
+#define EG_RATE "rlmt_egrate"
+#define RATE_LIMIT_EG_RATE_BOFFSET 16
+#define RATE_LIMIT_EG_RATE_BLEN 4
+#define RATE_LIMIT_EG_RATE_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT_ING_RATE_BOFFSET 0
+#define RATE_LIMIT_ING_RATE_BLEN 4
+#define RATE_LIMIT_ING_RATE_FLAG HSL_RW
+
+ /**
+ * Priority Control Register
+ */
+#define PRI_CTL "prctl"
+#define PRI_CTL_ID 33
+#define PRI_CTL_OFFSET 0x0110
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x0100
+#define PRI_CTL_NR_E 6
+
+#define PORT_PRI_EN "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET 19
+#define PRI_CTL_PORT_PRI_EN_BLEN 1
+#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_EN "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+#define PORT_PRI_SEL "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0
+#define PRI_CTL_PORT_PRI_SEL_BLEN 2
+#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW
+
+
+//mib memory info
+#define MIB_RXBROAD "RxBroad"
+#define MIB_RXBROAD_ID 34
+#define MIB_RXBROAD_OFFSET 0x19000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0xa0
+#define MIB_RXBROAD_NR_E 6
+
+#define MIB_RXPAUSE "RxPause"
+#define MIB_RXPAUSE_ID 35
+#define MIB_RXPAUSE_OFFSET 0x19004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0xa0
+#define MIB_RXPAUSE_NR_E 6
+
+#define MIB_RXMULTI "RxMulti"
+#define MIB_RXMULTI_ID 36
+#define MIB_RXMULTI_OFFSET 0x19008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0xa0
+#define MIB_RXMULTI_NR_E 6
+
+#define MIB_RXFCSERR "RxFcsErr"
+#define MIB_RXFCSERR_ID 37
+#define MIB_RXFCSERR_OFFSET 0x1900C
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0xa0
+#define MIB_RXFCSERR_NR_E 6
+
+#define MIB_RXALLIGNERR "RxAllignErr"
+#define MIB_RXALLIGNERR_ID 38
+#define MIB_RXALLIGNERR_OFFSET 0x19010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0xa0
+#define MIB_RXALLIGNERR_NR_E 6
+
+#define MIB_RXRUNT "RxRunt"
+#define MIB_RXRUNT_ID 39
+#define MIB_RXRUNT_OFFSET 0x19014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0xa0
+#define MIB_RXRUNT_NR_E 6
+
+#define MIB_RXFRAGMENT "RxFragment"
+#define MIB_RXFRAGMENT_ID 40
+#define MIB_RXFRAGMENT_OFFSET 0x19018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0xa0
+#define MIB_RXFRAGMENT_NR_E 6
+
+#define MIB_RX64BYTE "Rx64Byte"
+#define MIB_RX64BYTE_ID 41
+#define MIB_RX64BYTE_OFFSET 0x1901C
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0xa0
+#define MIB_RX64BYTE_NR_E 6
+
+#define MIB_RX128BYTE "Rx128Byte"
+#define MIB_RX128BYTE_ID 42
+#define MIB_RX128BYTE_OFFSET 0x19020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0xa0
+#define MIB_RX128BYTE_NR_E 6
+
+#define MIB_RX256BYTE "Rx256Byte"
+#define MIB_RX256BYTE_ID 43
+#define MIB_RX256BYTE_OFFSET 0x19024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0xa0
+#define MIB_RX256BYTE_NR_E 6
+
+#define MIB_RX512BYTE "Rx512Byte"
+#define MIB_RX512BYTE_ID 44
+#define MIB_RX512BYTE_OFFSET 0x19028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0xa0
+#define MIB_RX512BYTE_NR_E 6
+
+#define MIB_RX1024BYTE "Rx1024Byte"
+#define MIB_RX1024BYTE_ID 45
+#define MIB_RX1024BYTE_OFFSET 0x1902C
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0xa0
+#define MIB_RX1024BYTE_NR_E 6
+
+#define MIB_RX1518BYTE "Rx1518Byte" //reserved for s16
+
+#define MIB_RXMAXBYTE "RxMaxByte"
+#define MIB_RXMAXBYTE_ID 46
+#define MIB_RXMAXBYTE_OFFSET 0x19030
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0xa0
+#define MIB_RXMAXBYTE_NR_E 6
+
+#define MIB_RXTOOLONG "RxTooLong"
+#define MIB_RXTOOLONG_ID 47
+#define MIB_RXTOOLONG_OFFSET 0x19034
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0xa0
+#define MIB_RXTOOLONG_NR_E 6
+
+#define MIB_RXGOODBYTE_LO "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID 48
+#define MIB_RXGOODBYTE_LO_OFFSET 0x19038
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0xa0
+#define MIB_RXGOODBYTE_LO_NR_E 6
+
+#define MIB_RXGOODBYTE_HI "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID 49
+#define MIB_RXGOODBYTE_HI_OFFSET 0x1903C
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0xa0
+#define MIB_RXGOODBYTE_HI_NR_E 6
+
+#define MIB_RXBADBYTE_LO "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID 50
+#define MIB_RXBADBYTE_LO_OFFSET 0x19040
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0xa0
+#define MIB_RXBADBYTE_LO_NR_E 6
+
+#define MIB_RXBADBYTE_HI "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID 51
+#define MIB_RXBADBYTE_HI_OFFSET 0x19044
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0xa0
+#define MIB_RXBADBYTE_HI_NR_E 6
+
+#define MIB_RXOVERFLOW "RxOverFlow"
+#define MIB_RXOVERFLOW_ID 52
+#define MIB_RXOVERFLOW_OFFSET 0x19048
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0xa0
+#define MIB_RXOVERFLOW_NR_E 6
+
+#define MIB_FILTERED "Filtered"
+#define MIB_FILTERED_ID 53
+#define MIB_FILTERED_OFFSET 0x1904C
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0xa0
+#define MIB_FILTERED_NR_E 6
+
+#define MIB_TXBROAD "TxBroad"
+#define MIB_TXBROAD_ID 54
+#define MIB_TXBROAD_OFFSET 0x19050
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0xa0
+#define MIB_TXBROAD_NR_E 6
+
+#define MIB_TXPAUSE "TxPause"
+#define MIB_TXPAUSE_ID 55
+#define MIB_TXPAUSE_OFFSET 0x19054
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0xa0
+#define MIB_TXPAUSE_NR_E 6
+
+#define MIB_TXMULTI "TxMulti"
+#define MIB_TXMULTI_ID 56
+#define MIB_TXMULTI_OFFSET 0x19058
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0xa0
+#define MIB_TXMULTI_NR_E 6
+
+#define MIB_TXUNDERRUN "TxUnderRun"
+#define MIB_TXUNDERRUN_ID 57
+#define MIB_TXUNDERRUN_OFFSET 0x1905C
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0xa0
+#define MIB_TXUNDERRUN_NR_E 6
+
+#define MIB_TX64BYTE "Tx64Byte"
+#define MIB_TX64BYTE_ID 58
+#define MIB_TX64BYTE_OFFSET 0x19060
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0xa0
+#define MIB_TX64BYTE_NR_E 6
+
+#define MIB_TX128BYTE "Tx128Byte"
+#define MIB_TX128BYTE_ID 59
+#define MIB_TX128BYTE_OFFSET 0x19064
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0xa0
+#define MIB_TX128BYTE_NR_E 6
+
+#define MIB_TX256BYTE "Tx256Byte"
+#define MIB_TX256BYTE_ID 60
+#define MIB_TX256BYTE_OFFSET 0x19068
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0xa0
+#define MIB_TX256BYTE_NR_E 6
+
+#define MIB_TX512BYTE "Tx512Byte"
+#define MIB_TX512BYTE_ID 61
+#define MIB_TX512BYTE_OFFSET 0x1906C
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0xa0
+#define MIB_TX512BYTE_NR_E 6
+
+#define MIB_TX1024BYTE "Tx1024Byte"
+#define MIB_TX1024BYTE_ID 62
+#define MIB_TX1024BYTE_OFFSET 0x19070
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0xa0
+#define MIB_TX1024BYTE_NR_E 6
+
+#define MIB_TX1518BYTE "Tx1518Byte" //reserved for s16
+
+#define MIB_TXMAXBYTE "TxMaxByte"
+#define MIB_TXMAXBYTE_ID 63
+#define MIB_TXMAXBYTE_OFFSET 0x19074
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0xa0
+#define MIB_TXMAXBYTE_NR_E 6
+
+#define MIB_TXOVERSIZE "TxOverSize"
+#define MIB_TXOVERSIZE_ID 64
+#define MIB_TXOVERSIZE_OFFSET 0x19078
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0xa0
+#define MIB_TXOVERSIZE_NR_E 6
+
+#define MIB_TXBYTE_LO "TxByteLo"
+#define MIB_TXBYTE_LO_ID 65
+#define MIB_TXBYTE_LO_OFFSET 0x1907C
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0xa0
+#define MIB_TXBYTE_LO_NR_E 6
+
+#define MIB_TXBYTE_HI "TxByteHi"
+#define MIB_TXBYTE_HI_ID 66
+#define MIB_TXBYTE_HI_OFFSET 0x19080
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0xa0
+#define MIB_TXBYTE_HI_NR_E 6
+
+#define MIB_TXCOLLISION "TxCollision"
+#define MIB_TXCOLLISION_ID 67
+#define MIB_TXCOLLISION_OFFSET 0x19084
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0xa0
+#define MIB_TXCOLLISION_NR_E 6
+
+#define MIB_TXABORTCOL "TxAbortCol"
+#define MIB_TXABORTCOL_ID 68
+#define MIB_TXABORTCOL_OFFSET 0x19088
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0xa0
+#define MIB_TXABORTCOL_NR_E 6
+
+#define MIB_TXMULTICOL "TxMultiCol"
+#define MIB_TXMULTICOL_ID 69
+#define MIB_TXMULTICOL_OFFSET 0x1908C
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0xa0
+#define MIB_TXMULTICOL_NR_E 6
+
+#define MIB_TXSINGALCOL "TxSingalCol"
+#define MIB_TXSINGALCOL_ID 70
+#define MIB_TXSINGALCOL_OFFSET 0x19090
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0xa0
+#define MIB_TXSINGALCOL_NR_E 6
+
+#define MIB_TXEXCDEFER "TxExcDefer"
+#define MIB_TXEXCDEFER_ID 71
+#define MIB_TXEXCDEFER_OFFSET 0x19094
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0xa0
+#define MIB_TXEXCDEFER_NR_E 6
+
+#define MIB_TXDEFER "TxDefer"
+#define MIB_TXDEFER_ID 72
+#define MIB_TXDEFER_OFFSET 0x19098
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0xa0
+#define MIB_TXDEFER_NR_E 6
+
+#define MIB_TXLATECOL "TxLateCol"
+#define MIB_TXLATECOL_ID 73
+#define MIB_TXLATECOL_OFFSET 0x1909C
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0xa0
+#define MIB_TXLATECOL_NR_E 6
+
+//second mem block
+#define MIB_RXBROAD_2 "RxBroad_2"
+#define MIB_RXBROAD_2_ID 34
+#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH 4
+#define MIB_RXBROAD_2_E_OFFSET 0xa0
+#define MIB_RXBROAD_2_NR_E 6
+
+#define MIB_RXPAUSE_2 "RxPause_2"
+#define MIB_RXPAUSE_2_ID 35
+#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH 4
+#define MIB_RXPAUSE_2_E_OFFSET 0xa0
+#define MIB_RXPAUSE_2_NR_E 6
+
+#define MIB_RXMULTI_2 "RxMulti_2"
+#define MIB_RXMULTI_2_ID 36
+#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH 4
+#define MIB_RXMULTI_2_E_OFFSET 0xa0
+#define MIB_RXMULTI_2_NR_E 6
+
+#define MIB_RXFCSERR_2 "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID 37
+#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH 4
+#define MIB_RXFCSERR_2_E_OFFSET 0xa0
+#define MIB_RXFCSERR_2_NR_E 6
+
+#define MIB_RXALLIGNERR_2 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID 38
+#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH 4
+#define MIB_RXALLIGNERR_2_E_OFFSET 0xa0
+#define MIB_RXALLIGNERR_2_NR_E 6
+
+#define MIB_RXRUNT_2 "RxRunt_2"
+#define MIB_RXRUNT_2_ID 39
+#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH 4
+#define MIB_RXRUNT_2_E_OFFSET 0xa0
+#define MIB_RXRUNT_2_NR_E 6
+
+#define MIB_RXFRAGMENT_2 "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID 40
+#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH 4
+#define MIB_RXFRAGMENT_2_E_OFFSET 0xa0
+#define MIB_RXFRAGMENT_2_NR_E 6
+
+#define MIB_RX64BYTE_2 "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID 41
+#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH 4
+#define MIB_RX64BYTE_2_E_OFFSET 0xa0
+#define MIB_RX64BYTE_2_NR_E 6
+
+#define MIB_RX128BYTE_2 "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID 42
+#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH 4
+#define MIB_RX128BYTE_2_E_OFFSET 0xa0
+#define MIB_RX128BYTE_2_NR_E 6
+
+#define MIB_RX256BYTE_2 "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID 43
+#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH 4
+#define MIB_RX256BYTE_2_E_OFFSET 0xa0
+#define MIB_RX256BYTE_2_NR_E 6
+
+#define MIB_RX512BYTE_2 "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID 44
+#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH 4
+#define MIB_RX512BYTE_2_E_OFFSET 0xa0
+#define MIB_RX512BYTE_2_NR_E 6
+
+#define MIB_RX1024BYTE_2 "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID 45
+#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH 4
+#define MIB_RX1024BYTE_2_E_OFFSET 0xa0
+#define MIB_RX1024BYTE_2_NR_E 6
+
+#define MIB_RXMAXBYTE_2 "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID 46
+#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH 4
+#define MIB_RXMAXBYTE_2_E_OFFSET 0xa0
+#define MIB_RXMAXBYTE_2_NR_E 6
+
+#define MIB_RXTOOLONG_2 "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID 47
+#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH 4
+#define MIB_RXTOOLONG_2_E_OFFSET 0xa0
+#define MIB_RXTOOLONG_2_NR_E 6
+
+#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID 48
+#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa0
+#define MIB_RXGOODBYTE_LO_2_NR_E 6
+
+#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID 49
+#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa0
+#define MIB_RXGOODBYTE_HI_2_NR_E 6
+
+#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID 50
+#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa0
+#define MIB_RXBADBYTE_LO_2_NR_E 6
+
+#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID 51
+#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa0
+#define MIB_RXBADBYTE_HI_2_NR_E 6
+
+#define MIB_RXOVERFLOW_2 "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID 52
+#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH 4
+#define MIB_RXOVERFLOW_2_E_OFFSET 0xa0
+#define MIB_RXOVERFLOW_2_NR_E 6
+
+#define MIB_FILTERED_2 "Filtered_2"
+#define MIB_FILTERED_2_ID 53
+#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH 4
+#define MIB_FILTERED_2_E_OFFSET 0xa0
+#define MIB_FILTERED_2_NR_E 6
+
+#define MIB_TXBROAD_2 "TxBroad_2"
+#define MIB_TXBROAD_2_ID 54
+#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH 4
+#define MIB_TXBROAD_2_E_OFFSET 0xa0
+#define MIB_TXBROAD_2_NR_E 6
+
+#define MIB_TXPAUSE_2 "TxPause_2"
+#define MIB_TXPAUSE_2_ID 55
+#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH 4
+#define MIB_TXPAUSE_2_E_OFFSET 0xa0
+#define MIB_TXPAUSE_2_NR_E 6
+
+#define MIB_TXMULTI_2 "TxMulti_2"
+#define MIB_TXMULTI_2_ID 56
+#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH 4
+#define MIB_TXMULTI_2_E_OFFSET 0xa0
+#define MIB_TXMULTI_2_NR_E 6
+
+#define MIB_TXUNDERRUN_2 "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID 57
+#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH 4
+#define MIB_TXUNDERRUN_2_E_OFFSET 0xa0
+#define MIB_TXUNDERRUN_2_NR_E 6
+
+#define MIB_TX64BYTE_2 "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID 58
+#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH 4
+#define MIB_TX64BYTE_2_E_OFFSET 0xa0
+#define MIB_TX64BYTE_2_NR_E 6
+
+#define MIB_TX128BYTE_2 "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID 59
+#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH 4
+#define MIB_TX128BYTE_2_E_OFFSET 0xa0
+#define MIB_TX128BYTE_2_NR_E 6
+
+#define MIB_TX256BYTE_2 "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID 60
+#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH 4
+#define MIB_TX256BYTE_2_E_OFFSET 0xa0
+#define MIB_TX256BYTE_2_NR_E 6
+
+#define MIB_TX512BYTE_2 "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID 61
+#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH 4
+#define MIB_TX512BYTE_2_E_OFFSET 0xa0
+#define MIB_TX512BYTE_2_NR_E 6
+
+#define MIB_TX1024BYTE_2 "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID 62
+#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH 4
+#define MIB_TX1024BYTE_2_E_OFFSET 0xa0
+#define MIB_TX1024BYTE_2_NR_E 6
+
+#define MIB_TXMAXBYTE_2 "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID 63
+#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH 4
+#define MIB_TXMAXBYTE_2_E_OFFSET 0xa0
+#define MIB_TXMAXBYTE_2_NR_E 6
+
+#define MIB_TXOVERSIZE_2 "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID 64
+#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH 4
+#define MIB_TXOVERSIZE_2_E_OFFSET 0xa0
+#define MIB_TXOVERSIZE_2_NR_E 6
+
+#define MIB_TXBYTE_LO_2 "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID 65
+#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH 4
+#define MIB_TXBYTE_LO_2_E_OFFSET 0xa0
+#define MIB_TXBYTE_LO_2_NR_E 6
+
+#define MIB_TXBYTE_HI_2 "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID 66
+#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH 4
+#define MIB_TXBYTE_HI_2_E_OFFSET 0xa0
+#define MIB_TXBYTE_HI_2_NR_E 6
+
+#define MIB_TXCOLLISION_2 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID 67
+#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH 4
+#define MIB_TXCOLLISION_2_E_OFFSET 0xa0
+#define MIB_TXCOLLISION_2_NR_E 6
+
+#define MIB_TXABORTCOL_2 "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID 68
+#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH 4
+#define MIB_TXABORTCOL_2_E_OFFSET 0xa0
+#define MIB_TXABORTCOL_2_NR_E 6
+
+#define MIB_TXMULTICOL_2 "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID 69
+#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH 4
+#define MIB_TXMULTICOL_2_E_OFFSET 0xa0
+#define MIB_TXMULTICOL_2_NR_E 6
+
+#define MIB_TXSINGALCOL_2 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID 70
+#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH 4
+#define MIB_TXSINGALCOL_2_E_OFFSET 0xa0
+#define MIB_TXSINGALCOL_2_NR_E 6
+
+#define MIB_TXEXCDEFER_2 "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID 71
+#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH 4
+#define MIB_TXEXCDEFER_2_E_OFFSET 0xa0
+#define MIB_TXEXCDEFER_2_NR_E 6
+
+#define MIB_TXDEFER_2 "TxDefer_2"
+#define MIB_TXDEFER_2_ID 72
+#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH 4
+#define MIB_TXDEFER_2_E_OFFSET 0xa0
+#define MIB_TXDEFER_2_NR_E 6
+
+#define MIB_TXLATECOL_2 "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID 73
+#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH 4
+#define MIB_TXLATECOL_2_E_OFFSET 0xa0
+#define MIB_TXLATECOL_2_NR_E 6
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_REG_H */
+
diff --git a/include/hsl/athena/athena_reg_access.h b/include/hsl/athena/athena_reg_access.h
new file mode 100644
index 0000000..02cf67f
--- /dev/null
+++ b/include/hsl/athena/athena_reg_access.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ATHENA_REG_ACCESS_H_
+#define _ATHENA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_REG_ACCESS_H_ */
+
diff --git a/include/hsl/athena/athena_vlan.h b/include/hsl/athena/athena_vlan.h
new file mode 100644
index 0000000..e8fd77f
--- /dev/null
+++ b/include/hsl/athena/athena_vlan.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ATHENA_VLAN_H
+#define _ATHENA_VLAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ athena_vlan_reset(a_uint32_t dev_id);
+
+ sw_error_t
+ athena_vlan_init(a_uint32_t dev_id);
+
+ sw_error_t
+ athena_vlan_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ATHENA_VLAN_RESET(rv, dev_id) \
+ { \
+ rv = athena_vlan_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ATHENA_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = athena_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ATHENA_VLAN_CLEANUP(rv, dev_id) \
+ { \
+ rv = athena_vlan_cleanup(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ATHENA_VLAN_RESET(rv, dev_id)
+#define ATHENA_VLAN_INIT(rv, dev_id)
+#define ATHENA_VLAN_CLEANUP(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+ HSL_LOCAL sw_error_t
+ athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ATHENA_VLAN_H */
diff --git a/include/hsl/garuda/garuda_acl.h b/include/hsl/garuda/garuda_acl.h
new file mode 100644
index 0000000..ffd5369
--- /dev/null
+++ b/include/hsl/garuda/garuda_acl.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_acl GARUDA_ACL
+ * @{
+ */
+#ifndef _GARUDA_ACL_H_
+#define _GARUDA_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+ sw_error_t
+ garuda_acl_init(a_uint32_t dev_id);
+
+ sw_error_t
+ garuda_acl_reset(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define GARUDA_ACL_INIT(rv, dev_id) \
+ { \
+ rv = garuda_acl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define GARUDA_ACL_RESET(rv, dev_id) \
+ { \
+ rv = garuda_acl_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_ACL_INIT(rv, dev_id)
+#define GARUDA_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_list_dump(a_uint32_t dev_id);
+
+ HSL_LOCAL sw_error_t
+ garuda_acl_rule_dump(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_api.h b/include/hsl/garuda/garuda_api.h
new file mode 100644
index 0000000..b508752
--- /dev/null
+++ b/include/hsl/garuda/garuda_api.h
@@ -0,0 +1,522 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _GARUDA_API_H_
+#define _GARUDA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, garuda_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, garuda_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, garuda_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, garuda_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, garuda_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, garuda_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, garuda_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, garuda_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, garuda_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_HDR_SET, garuda_port_hdr_status_set), \
+ SW_API_DEF(SW_API_PT_HDR_GET, garuda_port_hdr_status_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, garuda_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, garuda_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, garuda_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, garuda_port_flowctrl_forcemode_get),\
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, garuda_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, garuda_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, garuda_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, garuda_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, garuda_port_cdt),
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_HDR_SET) \
+ SW_API_DESC(SW_API_PT_HDR_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET)\
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT)
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, garuda_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, garuda_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_MEM_UPDATE, garuda_vlan_member_update), \
+ SW_API_DEF(SW_API_VLAN_FIND, garuda_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, garuda_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, garuda_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, garuda_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, garuda_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, garuda_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, garuda_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, garuda_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, garuda_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, garuda_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, garuda_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_DEF_VID_SET, garuda_port_default_vid_set), \
+ SW_API_DEF(SW_API_PT_DEF_VID_GET, garuda_port_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, garuda_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, garuda_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, garuda_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, garuda_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_PT_NESTVLAN_SET, garuda_port_nestvlan_set), \
+ SW_API_DEF(SW_API_PT_NESTVLAN_GET, garuda_port_nestvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, garuda_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, garuda_nestvlan_tpid_get),
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_PT_NESTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_NESTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, garuda_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, garuda_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,garuda_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, garuda_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIRST, garuda_fdb_first), \
+ SW_API_DEF(SW_API_FDB_NEXT, garuda_fdb_next), \
+ SW_API_DEF(SW_API_FDB_FIND, garuda_fdb_find), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, garuda_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, garuda_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, garuda_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, garuda_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, garuda_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, garuda_fdb_age_time_get),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIRST) \
+ SW_API_DESC(SW_API_FDB_NEXT) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+ SW_API_DEF(SW_API_ACL_LIST_CREAT, garuda_acl_list_creat), \
+ SW_API_DEF(SW_API_ACL_LIST_DESTROY, garuda_acl_list_destroy), \
+ SW_API_DEF(SW_API_ACL_RULE_ADD, garuda_acl_rule_add), \
+ SW_API_DEF(SW_API_ACL_RULE_DELETE, garuda_acl_rule_delete), \
+ SW_API_DEF(SW_API_ACL_RULE_QUERY, garuda_acl_rule_query), \
+ SW_API_DEF(SW_API_ACL_LIST_BIND, garuda_acl_list_bind), \
+ SW_API_DEF(SW_API_ACL_LIST_UNBIND, garuda_acl_list_unbind), \
+ SW_API_DEF(SW_API_ACL_STATUS_SET, garuda_acl_status_set), \
+ SW_API_DEF(SW_API_ACL_STATUS_GET, garuda_acl_status_get), \
+ SW_API_DEF(SW_API_ACL_LIST_DUMP, garuda_acl_list_dump), \
+ SW_API_DEF(SW_API_ACL_RULE_DUMP, garuda_acl_rule_dump),
+
+#define ACL_API_PARAM \
+ SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+ SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+ SW_API_DESC(SW_API_ACL_RULE_ADD) \
+ SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+ SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+ SW_API_DESC(SW_API_ACL_LIST_BIND) \
+ SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+ SW_API_DESC(SW_API_ACL_STATUS_SET) \
+ SW_API_DESC(SW_API_ACL_STATUS_GET) \
+ SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+ SW_API_DESC(SW_API_ACL_RULE_DUMP)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_SCH_MODE_SET, garuda_qos_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_SCH_MODE_GET, garuda_qos_sch_mode_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, garuda_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, garuda_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, garuda_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, garuda_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, garuda_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, garuda_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, garuda_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, garuda_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_SET, garuda_cosmap_up_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_GET, garuda_cosmap_up_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, garuda_cosmap_dscp_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, garuda_cosmap_dscp_queue_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, garuda_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, garuda_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, garuda_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, garuda_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, garuda_qos_port_default_up_set), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, garuda_qos_port_default_up_get),
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_SCH_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, garuda_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, garuda_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, garuda_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, garuda_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, garuda_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, garuda_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, garuda_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, garuda_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, garuda_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, garuda_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, garuda_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, garuda_igmp_mld_entry_creat_get),
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, garuda_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, garuda_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, garuda_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, garuda_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, garuda_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, garuda_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, garuda_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, garuda_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, garuda_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, garuda_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, garuda_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, garuda_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, garuda_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, garuda_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, garuda_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, garuda_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_SET, garuda_rate_queue_egrl_set), \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_GET, garuda_rate_queue_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_SET, garuda_rate_port_egrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_GET, garuda_rate_port_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_SET, garuda_rate_port_inrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_GET, garuda_rate_port_inrl_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, garuda_storm_ctrl_frame_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, garuda_storm_ctrl_frame_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, garuda_storm_ctrl_rate_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, garuda_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, garuda_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, garuda_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, garuda_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, garuda_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, garuda_mib_status_get),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_ARP_STATUS_SET, garuda_arp_status_set), \
+ SW_API_DEF(SW_API_ARP_STATUS_GET, garuda_arp_status_get), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, garuda_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, garuda_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, garuda_port_unk_sa_cmd_set), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, garuda_port_unk_sa_cmd_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, garuda_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, garuda_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, garuda_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, garuda_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, garuda_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, garuda_cpu_port_status_get), \
+ SW_API_DEF(SW_API_BC_TO_CPU_PORT_SET, garuda_bc_to_cpu_port_set), \
+ SW_API_DEF(SW_API_BC_TO_CPU_PORT_GET, garuda_bc_to_cpu_port_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, garuda_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, garuda_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, garuda_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, garuda_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, garuda_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, garuda_port_dhcp_get),
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_ARP_STATUS_SET) \
+ SW_API_DESC(SW_API_ARP_STATUS_GET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_BC_TO_CPU_PORT_SET) \
+ SW_API_DESC(SW_API_BC_TO_CPU_PORT_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, garuda_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, garuda_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, garuda_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, garuda_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, garuda_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, garuda_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, garuda_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, garuda_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, garuda_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ ACL_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ ACL_API_PARAM \
+ LED_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_API_H_ */
diff --git a/include/hsl/garuda/garuda_fdb.h b/include/hsl/garuda/garuda_fdb.h
new file mode 100644
index 0000000..096ce1f
--- /dev/null
+++ b/include/hsl/garuda/garuda_fdb.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_fdb GARUDA_FDB
+ * @{
+ */
+#ifndef _GARUDA_FDB_H_
+#define _GARUDA_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t
+ garuda_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define GARUDA_FDB_INIT(rv, dev_id) \
+ { \
+ rv = garuda_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_del_by_mac(a_uint32_t dev_id,
+ const fal_fdb_entry_t *entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_igmp.h b/include/hsl/garuda/garuda_igmp.h
new file mode 100644
index 0000000..bded887
--- /dev/null
+++ b/include/hsl/garuda/garuda_igmp.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_igmp GARUDA_IGMP
+ * @{
+ */
+#ifndef _GARUDA_IGMP_H_
+#define _GARUDA_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+ sw_error_t
+ garuda_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define GARUDA_IGMP_INIT(rv, dev_id) \
+ { \
+ rv = garuda_igmp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_init.h b/include/hsl/garuda/garuda_init.h
new file mode 100644
index 0000000..8f18185
--- /dev/null
+++ b/include/hsl/garuda/garuda_init.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_init GARUDA_INIT
+ * @{
+ */
+#ifndef _GARUDA_INIT_H_
+#define _GARUDA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+ sw_error_t
+ garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+ sw_error_t
+ garuda_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ garuda_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_INIT_H_ */
+
diff --git a/include/hsl/garuda/garuda_leaky.h b/include/hsl/garuda/garuda_leaky.h
new file mode 100644
index 0000000..3005607
--- /dev/null
+++ b/include/hsl/garuda/garuda_leaky.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_leaky GARUDA_LEAKY
+ * @{
+ */
+#ifndef _GARUDA_LEAKY_H_
+#define _GARUDA_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+ sw_error_t garuda_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define GARUDA_LEAKY_INIT(rv, dev_id) \
+ { \
+ rv = garuda_leaky_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_led.h b/include/hsl/garuda/garuda_led.h
new file mode 100644
index 0000000..97c8065
--- /dev/null
+++ b/include/hsl/garuda/garuda_led.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _GARUDA_LED_H_
+#define _GARUDA_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+ sw_error_t
+ garuda_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define GARUDA_LED_INIT(rv, dev_id) \
+ { \
+ rv = garuda_led_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_LED_H_ */
diff --git a/include/hsl/garuda/garuda_mib.h b/include/hsl/garuda/garuda_mib.h
new file mode 100644
index 0000000..1601df6
--- /dev/null
+++ b/include/hsl/garuda/garuda_mib.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_mib GARUDA_MIB
+ * @{
+ */
+#ifndef _GARUDA_MIB_H_
+#define _GARUDA_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ garuda_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define GARUDA_MIB_INIT(rv, dev_id) \
+ { \
+ rv = garuda_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_mirror.h b/include/hsl/garuda/garuda_mirror.h
new file mode 100644
index 0000000..7812fcd
--- /dev/null
+++ b/include/hsl/garuda/garuda_mirror.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_mirror GARUDA_MIRROR
+ * @{
+ */
+#ifndef _GARUDA_MIRROR_H_
+#define _GARUDA_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+ sw_error_t garuda_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define GARUDA_MIRR_INIT(rv, dev_id) \
+ { \
+ rv = garuda_mirr_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_misc.h b/include/hsl/garuda/garuda_misc.h
new file mode 100644
index 0000000..dfc11a5
--- /dev/null
+++ b/include/hsl/garuda/garuda_misc.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _GARUDA_MISC_H_
+#define _GARUDA_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+ sw_error_t garuda_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define GARUDA_MISC_INIT(rv, dev_id) \
+ { \
+ rv = garuda_misc_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_MISC_H_ */
diff --git a/include/hsl/garuda/garuda_port_ctrl.h b/include/hsl/garuda/garuda_port_ctrl.h
new file mode 100644
index 0000000..14a9bd1
--- /dev/null
+++ b/include/hsl/garuda/garuda_port_ctrl.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL
+ * @{
+ */
+#ifndef _GARUDA_PORT_CTRL_H_
+#define _GARUDA_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t garuda_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define GARUDA_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = garuda_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+ HSL_LOCAL sw_error_t
+ garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_portvlan.h b/include/hsl/garuda/garuda_portvlan.h
new file mode 100644
index 0000000..d9fdd78
--- /dev/null
+++ b/include/hsl/garuda/garuda_portvlan.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_port_vlan GARUDA_PORT_VLAN
+ * @{
+ */
+#ifndef _GARUDA_PORTVLAN_H_
+#define _GARUDA_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t garuda_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define GARUDA_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = garuda_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ATHENA_PORTVLAN_H */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_qos.h b/include/hsl/garuda/garuda_qos.h
new file mode 100644
index 0000000..3328796
--- /dev/null
+++ b/include/hsl/garuda/garuda_qos.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_qos GARUDA_QOS
+ * @{
+ */
+#ifndef _GARUDA_QOS_H_
+#define _GARUDA_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+ sw_error_t garuda_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define GARUDA_QOS_INIT(rv, dev_id) \
+ { \
+ rv = garuda_qos_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_rate.h b/include/hsl/garuda/garuda_rate.h
new file mode 100644
index 0000000..4d28adc
--- /dev/null
+++ b/include/hsl/garuda/garuda_rate.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_rate GARUDA_RATE
+ * @{
+ */
+#ifndef _GARUDA_RATE_H_
+#define _GARUDA_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+ sw_error_t garuda_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define GARUDA_RATE_INIT(rv, dev_id) \
+ { \
+ rv = garuda_rate_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_reduced_acl.h b/include/hsl/garuda/garuda_reduced_acl.h
new file mode 100644
index 0000000..959e8a8
--- /dev/null
+++ b/include/hsl/garuda/garuda_reduced_acl.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _GARUDA_REDUCED_ACL_H_
+#define _GARUDA_REDUCED_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8]);
+
+ sw_error_t
+ garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act);
+
+ sw_error_t
+ garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8]);
+
+ sw_error_t
+ garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8]);
+
+ sw_error_t
+ garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t * act);
+
+ sw_error_t
+ garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8]);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_REDUCED_ACL_H_ */
+
diff --git a/include/hsl/garuda/garuda_reg.h b/include/hsl/garuda/garuda_reg.h
new file mode 100644
index 0000000..27f0a60
--- /dev/null
+++ b/include/hsl/garuda/garuda_reg.h
@@ -0,0 +1,3605 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _GARUDA_REG_H_
+#define _GARUDA_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+ /* GARUDA Mask Control Register */
+#define MASK_CTL "mask"
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 1
+
+#define SOFT_RST "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define MII_CLK5_SEL "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21
+#define MASK_CTL_MII_CLK5_SEL_BLEN 1
+#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW
+
+#define MII_CLK0_SEL "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20
+#define MASK_CTL_MII_CLK0_SEL_BLEN 1
+#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW
+
+#define LOAD_EEPROM "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+
+ /* GARUDA Mask Control Register */
+#define POSTRIP "postrip"
+#define POSTRIP_ID 0
+#define POSTRIP_OFFSET 0x0008
+#define POSTRIP_E_LENGTH 4
+#define POSTRIP_E_OFFSET 0
+#define POSTRIP_NR_E 1
+
+#define POWER_ON_SEL "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET 31
+#define POSTRIP_POWER_ON_SEL_BLEN 1
+#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW
+
+#define RXDELAY_S1 "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET 26
+#define POSTRIP_RXDELAY_S1_BLEN 1
+#define POSTRIP_RXDELAY_S1_FLAG HSL_RW
+
+#define SPI_EN "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET 25
+#define POSTRIP_SPI_EN_BLEN 1
+#define POSTRIP_SPI_EN_FLAG HSL_RW
+
+#define LED_OPEN_EN "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET 24
+#define POSTRIP_LED_OPEN_EN_BLEN 1
+#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW
+
+#define RXDELAY_S0 "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET 23
+#define POSTRIP_RXDELAY_S0_BLEN 1
+#define POSTRIP_RXDELAY_S0_FLAG HSL_RW
+
+#define TXDELAY_S1 "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET 22
+#define POSTRIP_TXDELAY_S1_BLEN 1
+#define POSTRIP_TXDELAY_S1_FLAG HSL_RW
+
+#define TXDELAY_S0 "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET 21
+#define POSTRIP_TXDELAY_S0_BLEN 1
+#define POSTRIP_TXDELAY_S0_FLAG HSL_RW
+
+#define LPW_EXIT "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET 20
+#define POSTRIP_LPW_EXIT_BLEN 1
+#define POSTRIP_LPW_EXIT_FLAG HSL_RW
+
+#define PHY_PLL_ON "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET 19
+#define POSTRIP_PHY_PLL_ON_BLEN 1
+#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW
+
+#define MAN_ENABLE "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET 18
+#define POSTRIP_MAN_ENABLE_BLEN 1
+#define POSTRIP_MAN_ENABLE_FLAG HSL_RW
+
+#define LPW_STATE_EN "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET 17
+#define POSTRIP_LPW_STATE_EN_BLEN 1
+#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW
+
+#define POWER_DOWN_HW "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET 16
+#define POSTRIP_POWER_DOWN_HW_BLEN 1
+#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW
+
+#define MAC5_PHY_MODE "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15
+#define POSTRIP_MAC5_PHY_MODE_BLEN 1
+#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW
+
+#define MAC5_MAC_MODE "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14
+#define POSTRIP_MAC5_MAC_MODE_BLEN 1
+#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW
+
+#define DBG_MODE_I "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET 13
+#define POSTRIP_DBG_MODE_I_BLEN 1
+#define POSTRIP_DBG_MODE_I_FLAG HSL_RW
+
+#define HIB_PULSE_HW "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET 12
+#define POSTRIP_HIB_PULSE_HW_BLEN 1
+#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW
+
+#define SEL_CLK25M "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET 11
+#define POSTRIP_SEL_CLK25M_BLEN 1
+#define POSTRIP_SEL_CLK25M_FLAG HSL_RW
+
+#define GATE_25M_EN "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET 10
+#define POSTRIP_GATE_25M_EN_BLEN 1
+#define POSTRIP_GATE_25M_EN_FLAG HSL_RW
+
+#define SEL_ANA_RST "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET 9
+#define POSTRIP_SEL_ANA_RST_BLEN 1
+#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW
+
+#define SERDES_EN "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET 8
+#define POSTRIP_SERDES_EN_BLEN 1
+#define POSTRIP_SERDES_EN_FLAG HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RTL_MODE "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET 5
+#define POSTRIP_RTL_MODE_BLEN 1
+#define POSTRIP_RTL_MODE_FLAG HSL_RW
+
+#define MAC0_MAC_MODE "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4
+#define POSTRIP_MAC0_MAC_MODE_BLEN 1
+#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW
+
+#define PHY4_RGMII_EN "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3
+#define POSTRIP_PHY4_RGMII_EN_BLEN 1
+#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW
+
+#define PHY4_GMII_EN "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET 2
+#define POSTRIP_PHY4_GMII_EN_BLEN 1
+#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_EN "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1
+#define POSTRIP_MAC0_RGMII_EN_BLEN 1
+#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW
+
+#define MAC0_GMII_EN "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET 0
+#define POSTRIP_MAC0_GMII_EN_BLEN 1
+#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW
+
+
+
+ /* Global Interrupt Register */
+#define GLOBAL_INT "gint"
+#define GLOBAL_INT_ID 1
+#define GLOBAL_INT_OFFSET 0x0010
+#define GLOBAL_INT_E_LENGTH 4
+#define GLOBAL_INT_E_OFFSET 0
+#define GLOBAL_INT_NR_E 1
+
+#define GLB_QM_ERR_CNT "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO
+
+#define GLB_LOOKUP_ERR "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLB_QM_ERR "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW
+
+#define GLB_HW_INI_DONE "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW
+
+#define GLB_MIB_INI "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN 1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW
+
+#define GLB_MIB_DONE "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW
+
+#define GLB_BIST_DONE "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW
+
+#define GLB_VT_MISS_VIO "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLB_VT_MEM_VIO "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLB_VT_DONE "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN 1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW
+
+#define GLB_QM_INI "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7
+#define GLOBAL_INT_GLB_QM_INI_BLEN 1
+#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW
+
+#define GLB_AT_INI "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6
+#define GLOBAL_INT_GLB_AT_INI_BLEN 1
+#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW
+
+#define GLB_ARL_FULL "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW
+
+#define GLB_ARL_DONE "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW
+
+#define GLB_MDIO_DONE "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW
+
+#define GLB_PHY_INT "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN 1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW
+
+#define GLB_EEPROM_ERR "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW
+
+#define GLB_EEPROM_INT "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK "gintm"
+#define GLOBAL_INT_MASK_ID 2
+#define GLOBAL_INT_MASK_OFFSET 0x0014
+#define GLOBAL_INT_MASK_E_LENGTH 4
+#define GLOBAL_INT_MASK_E_OFFSET 0
+#define GLOBAL_INT_MASK_NR_E 1
+
+#define GLBM_LOOKUP_ERR "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLBM_QM_ERR "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW
+
+#define GLBM_HW_INI_DONE "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW
+
+#define GLBM_MIB_INI "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW
+
+#define GLBM_MIB_DONE "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW
+
+#define GLBM_BIST_DONE "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW
+
+#define GLBM_VT_MISS_VIO "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLBM_VT_MEM_VIO "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLBM_VT_DONE "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW
+
+#define GLBM_QM_INI "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW
+
+#define GLBM_AT_INI "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW
+
+#define GLBM_ARL_FULL "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW
+
+#define GLBM_ARL_DONE "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW
+
+#define GLBM_MDIO_DONE "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW
+
+#define GLBM_PHY_INT "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW
+
+#define GLBM_EEPROM_ERR "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW
+
+#define GLBM_EEPROM_INT "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0 "gmac0"
+#define GLOBAL_MAC_ADDR0_ID 3
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 1
+
+#define GLB_BYTE4 "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5 "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+#define GLOBAL_MAC_ADDR1 "gmac1"
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 1
+
+#define GLB_BYTE0 "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1 "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2 "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3 "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+
+ /* Flood Mask Register */
+#define FLOOD_MASK "fmask"
+#define FLOOD_MASK_ID 5
+#define FLOOD_MASK_OFFSET 0x002c
+#define FLOOD_MASK_E_LENGTH 4
+#define FLOOD_MASK_E_OFFSET 0
+#define FLOOD_MASK_NR_E 1
+
+#define BROAD_TO_CPU "fmask_btocpu"
+#define FLOOD_MASK_BROAD_TO_CPU_BOFFSET 26
+#define FLOOD_MASK_BROAD_TO_CPU_BLEN 1
+#define FLOOD_MASK_BROAD_TO_CPU_FLAG HSL_RW
+
+#define ARL_MUL_LEAKY "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 25
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW
+
+#define ARL_UNI_LEAKY "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW
+
+#define MUL_FLOOD_DP "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 6
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW
+
+#define IGMP_DP "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET 8
+#define FLOOD_MASK_IGMP_DP_BLEN 6
+#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW
+
+#define UNI_FLOOD_DP "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 6
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW
+
+
+ /* Global Control Register */
+#define GLOBAL_CTL "gctl"
+#define GLOBAL_CTL_ID 5
+#define GLOBAL_CTL_OFFSET 0x0030
+#define GLOBAL_CTL_E_LENGTH 4
+#define GLOBAL_CTL_E_OFFSET 0
+#define GLOBAL_CTL_NR_E 1
+
+#define WEIGHT_PRIORITY "gctl_wpri"
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BOFFSET 31
+#define GLOBAL_CTL_WEIGHT_PRIORITY_BLEN 1
+#define GLOBAL_CTL_WEIGHT_PRIORITY_FLAG HSL_RW
+
+#define RATE_DROP_EN "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 30
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW
+
+#define QM_PRI_MODE "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 29
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW
+
+#define MIX_PRIORITY "gctl_mpri"
+#define GLOBAL_CTL_MIX_PRIORITY_BOFFSET 28
+#define GLOBAL_CTL_MIX_PRIORITY_BLEN 1
+#define GLOBAL_CTL_MIX_PRIORITY_FLAG HSL_RW
+
+#define RATE_CRE_LIMIT "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW
+
+#define RATE_TIME_SLOT "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW
+
+#define RELOAD_TIMER "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW
+
+#define QM_CNT_LOCK "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO
+
+#define BROAD_DROP_EN "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW
+
+#define MAX_FRAME_SIZE "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW
+
+
+ /* Flow Control Register */
+#define FLOW_CTL "fctl"
+#define FLOW_CTL_ID 6
+#define FLOW_CTL_OFFSET 0x0034
+#define FLOW_CTL_E_LENGTH 4
+#define FLOW_CTL_E_OFFSET 0
+#define FLOW_CTL_NR_E 1
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL_TEST_PAUSE_BLEN 1
+#define FLOW_CTL_TEST_PAUSE_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl_pofft"
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BOFFSET 24
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_BLEN 7
+#define FLOW_CTL_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_ON_THRES "fctl_pont"
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_BLEN 7
+#define FLOW_CTL_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BOFFSET 8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BOFFSET 0
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+
+ /* QM Control Register */
+#define QM_CTL "qmct"
+#define QM_CTL_ID 7
+#define QM_CTL_OFFSET 0x003c
+#define QM_CTL_E_LENGTH 4
+#define QM_CTL_E_OFFSET 0
+#define QM_CTL_NR_E 1
+
+#define QM_ERR_RST_EN "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31
+#define QM_CTL_QM_ERR_RST_EN_BLEN 1
+#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW
+
+#define LOOKUP_ERR_RST_EN "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW
+
+#define IGMP_CREAT_EN "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22
+#define QM_CTL_IGMP_CREAT_EN_BLEN 1
+#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW
+
+#define ACL_EN "qmct_aclen"
+#define QM_CTL_ACL_EN_BOFFSET 21
+#define QM_CTL_ACL_EN_BLEN 1
+#define QM_CTL_ACL_EN_FLAG HSL_RW
+
+#define PPPOE_RDT_EN "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20
+#define QM_CTL_PPPOE_RDT_EN_BLEN 1
+#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW
+
+#define IGMP_COPY_EN "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET 11
+#define QM_CTL_IGMP_COPY_EN_BLEN 1
+#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW
+
+#define PPPOE_EN "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET 10
+#define QM_CTL_PPPOE_EN_BLEN 1
+#define QM_CTL_PPPOE_EN_FLAG HSL_RW
+
+#define QM_FUNC_TEST "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET 9
+#define QM_CTL_QM_FUNC_TEST_BLEN 1
+#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW
+
+#define MS_FC_EN "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET 8
+#define QM_CTL_MS_FC_EN_BLEN 1
+#define QM_CTL_MS_FC_EN_FLAG HSL_RW
+
+#define FLOW_DROP_EN "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET 7
+#define QM_CTL_FLOW_DROP_EN_BLEN 1
+#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_CNT "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTL_FLOW_DROP_CNT_BLEN 6
+#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW
+
+
+ /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0 "vtbf0"
+#define VLAN_TABLE_FUNC0_ID 9
+#define VLAN_TABLE_FUNC0_OFFSET 0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 1
+
+#define VT_PRI_EN "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+#define VLAN_ID "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_BUSY "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW
+
+#define VT_FUNC "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW
+
+#define VLAN_TABLE_FUNC1 "vtbf1"
+#define VLAN_TABLE_FUNC1_ID 10
+#define VLAN_TABLE_FUNC1_OFFSET 0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 1
+
+#define VT_VALID "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW
+
+#define VID_MEM "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 10
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW
+
+
+ /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0 "atbf0"
+#define ADDR_TABLE_FUNC0_ID 11
+#define ADDR_TABLE_FUNC0_OFFSET 0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 1
+
+#define AT_ADDR_BYTE4 "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5 "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+#define AT_FULL_VIO "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW
+
+#define FLUSH_ST_EN "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW
+
+#define AT_BUSY "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW
+
+#define AT_FUNC "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC1 "atbf1"
+#define ADDR_TABLE_FUNC1_ID 12
+#define ADDR_TABLE_FUNC1_OFFSET 0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 0
+
+#define AT_ADDR_BYTE0 "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1 "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+#define AT_ADDR_BYTE2 "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3 "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC2 "atbf2"
+#define ADDR_TABLE_FUNC2_ID 13
+#define ADDR_TABLE_FUNC2_OFFSET 0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 0
+
+#define COPY_TO_CPU "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define LEAKY_EN "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW
+
+#define AT_STATUS "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+#define CLONE_EN "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW
+
+#define SA_DROP_EN "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW
+
+#define MIRROR_EN "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_PRI "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW
+
+#define DES_PORT "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 6
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW
+
+
+ /* Address Table Control Register */
+#define ADDR_TABLE_CTL "atbc"
+#define ADDR_TABLE_CTL_ID 14
+#define ADDR_TABLE_CTL_OFFSET 0x005C
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 1
+
+#define ARP_EN "atbc_arpe"
+#define ADDR_TABLE_CTL_ARP_EN_BOFFSET 20
+#define ADDR_TABLE_CTL_ARP_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARP_EN_FLAG HSL_RW
+
+#define ARL_INI_EN "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define LEARN_CHANGE_EN "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW
+
+#define AGE_EN "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define AGE_TIME "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING "imap"
+#define IP_PRI_MAPPING_ID 15
+#define IP_PRI_MAPPING_OFFSET 0x0060
+#define IP_PRI_MAPPING_E_LENGTH 4
+#define IP_PRI_MAPPING_E_OFFSET 0
+#define IP_PRI_MAPPING_NR_E 1
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0 "imap0"
+#define IP_PRI_MAPPING0_ID 15
+#define IP_PRI_MAPPING0_OFFSET 0x0060
+#define IP_PRI_MAPPING0_E_LENGTH 4
+#define IP_PRI_MAPPING0_E_OFFSET 0
+#define IP_PRI_MAPPING0_NR_E 0
+
+#define IP_0X3C "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW
+
+#define IP_0X38 "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW
+
+#define IP_0X34 "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW
+
+#define IP_0X30 "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW
+
+#define IP_0X2C "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW
+
+#define IP_0X28 "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW
+
+#define IP_0X24 "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW
+
+#define IP_0X20 "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW
+
+#define IP_0X1C "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW
+
+#define IP_0X18 "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW
+
+#define IP_0X14 "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW
+
+#define IP_0X10 "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW
+
+#define IP_0X0C "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW
+
+#define IP_0X08 "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW
+
+#define IP_0X04 "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW
+
+#define IP_0X00 "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW
+
+#define IP_PRI_MAPPING1 "imap1"
+#define IP_PRI_MAPPING1_ID 16
+#define IP_PRI_MAPPING1_OFFSET 0x0064
+#define IP_PRI_MAPPING1_E_LENGTH 4
+#define IP_PRI_MAPPING1_E_OFFSET 0
+#define IP_PRI_MAPPING1_NR_E 0
+
+#define IP_0X7C "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW
+
+#define IP_0X78 "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW
+
+#define IP_0X74 "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW
+
+#define IP_0X70 "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW
+
+#define IP_0X6C "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW
+
+#define IP_0X68 "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW
+
+#define IP_0X64 "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW
+
+#define IP_0X60 "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW
+
+#define IP_0X5C "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW
+
+#define IP_0X58 "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW
+
+#define IP_0X54 "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW
+
+#define IP_0X50 "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW
+
+#define IP_0X4C "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW
+
+#define IP_0X48 "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW
+
+#define IP_0X44 "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW
+
+#define IP_0X40 "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW
+
+
+#define IP_PRI_MAPPING2 "imap2"
+#define IP_PRI_MAPPING2_ID 17
+#define IP_PRI_MAPPING2_OFFSET 0x0068
+#define IP_PRI_MAPPING2_E_LENGTH 4
+#define IP_PRI_MAPPING2_E_OFFSET 0
+#define IP_PRI_MAPPING2_NR_E 0
+
+#define IP_0XBC "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW
+
+#define IP_0XB8 "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW
+
+#define IP_0XB4 "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW
+
+#define IP_0XB0 "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW
+
+#define IP_0XAC "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW
+
+#define IP_0XA8 "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW
+
+#define IP_0XA4 "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW
+
+#define IP_0XA0 "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW
+
+#define IP_0X9C "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW
+
+#define IP_0X98 "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW
+
+#define IP_0X94 "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW
+
+#define IP_0X90 "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW
+
+#define IP_0X8C "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW
+
+#define IP_0X88 "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW
+
+#define IP_0X84 "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW
+
+#define IP_0X80 "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW
+
+#define IP_PRI_MAPPING3 "imap3"
+#define IP_PRI_MAPPING3_ID 18
+#define IP_PRI_MAPPING3_OFFSET 0x006C
+#define IP_PRI_MAPPING3_E_LENGTH 4
+#define IP_PRI_MAPPING3_E_OFFSET 0
+#define IP_PRI_MAPPING3_NR_E 0
+
+#define IP_0XFC "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW
+
+#define IP_0XF8 "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW
+
+#define IP_0XF4 "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW
+
+#define IP_0XF0 "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW
+
+#define IP_0XEC "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW
+
+#define IP_0XE8 "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW
+
+#define IP_0XE4 "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW
+
+#define IP_0XE0 "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW
+
+#define IP_0XDC "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW
+
+#define IP_0XD8 "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW
+
+#define IP_0XD4 "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW
+
+#define IP_0XD0 "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW
+
+#define IP_0XCC "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW
+
+#define IP_0XC8 "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW
+
+#define IP_0XC4 "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW
+
+#define IP_0XC0 "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW
+
+
+ /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING "tpmap"
+#define TAG_PRI_MAPPING_ID 19
+#define TAG_PRI_MAPPING_OFFSET 0x0070
+#define TAG_PRI_MAPPING_E_LENGTH 4
+#define TAG_PRI_MAPPING_E_OFFSET 0
+#define TAG_PRI_MAPPING_NR_E 1
+
+#define TAG_0X07 "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW
+
+#define TAG_0X06 "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW
+
+#define TAG_0X05 "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW
+
+#define TAG_0X04 "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW
+
+#define TAG_0X03 "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW
+
+#define TAG_0X02 "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW
+
+#define TAG_0X01 "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW
+
+#define TAG_0X00 "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW
+
+
+ /* Service tag Register */
+#define SERVICE_TAG "servicetag"
+#define SERVICE_TAG_ID 20
+#define SERVICE_TAG_OFFSET 0x0074
+#define SERVICE_TAG_E_LENGTH 4
+#define SERVICE_TAG_E_OFFSET 0
+#define SERVICE_TAG_NR_E 1
+
+#define TAG_VALUE "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET 0
+#define SERVICE_TAG_TAG_VALUE_BLEN 16
+#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW
+
+
+ /* Cpu Port Register */
+#define CPU_PORT "cpup"
+#define CPU_PORT_ID 20
+#define CPU_PORT_OFFSET 0x0078
+#define CPU_PORT_E_LENGTH 4
+#define CPU_PORT_E_OFFSET 0
+#define CPU_PORT_NR_E 0
+
+#define CPU_PORT_EN "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET 8
+#define CPU_PORT_CPU_PORT_EN_BLEN 1
+#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW
+
+
+ /* MIB Function Register */
+#define MIB_FUNC "mibfunc"
+#define MIB_FUNC_ID 21
+#define MIB_FUNC_OFFSET 0x0080
+#define MIB_FUNC_E_LENGTH 4
+#define MIB_FUNC_E_OFFSET 0
+#define MIB_FUNC_NR_E 1
+
+#define MAC_CRC_EN "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31
+#define MIB_FUNC_MAC_CRC_EN_BLEN 1
+#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW
+
+#define MIB_EN "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET 30
+#define MIB_FUNC_MIB_EN_BLEN 1
+#define MIB_FUNC_MIB_EN_FLAG HSL_RW
+
+#define MIB_FUN "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET 24
+#define MIB_FUNC_MIB_FUN_BLEN 3
+#define MIB_FUNC_MIB_FUN_FLAG HSL_RW
+
+#define MIB_BUSY "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET 17
+#define MIB_FUNC_MIB_BUSY_BLEN 1
+#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET 0
+#define MIB_FUNC_MIB_TIMER_BLEN 16
+#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW
+
+
+ /* Mdio control Register */
+#define MDIO_CTRL "mctrl"
+#define MDIO_CTRL_ID 24
+#define MDIO_CTRL_OFFSET 0x0098
+#define MDIO_CTRL_E_LENGTH 4
+#define MDIO_CTRL_E_OFFSET 0
+#define MDIO_CTRL_NR_E 1
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define CMD "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET 27
+#define MDIO_CTRL_CMD_BLEN 1
+#define MDIO_CTRL_CMD_FLAG HSL_RW
+
+#define SUP_PRE "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET 26
+#define MDIO_CTRL_SUP_PRE_BLEN 1
+#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW
+
+#define PHY_ADDR "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET 21
+#define MDIO_CTRL_PHY_ADDR_BLEN 5
+#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW
+
+#define REG_ADDR "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET 16
+#define MDIO_CTRL_REG_ADDR_BLEN 5
+#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW
+
+#define DATA "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET 0
+#define MDIO_CTRL_DATA_BLEN 16
+#define MDIO_CTRL_DATA_FLAG HSL_RW
+
+
+
+
+ /* BIST control Register */
+#define BIST_CTRL "bctrl"
+#define BIST_CTRL_ID 24
+#define BIST_CTRL_OFFSET 0x00a0
+#define BIST_CTRL_E_LENGTH 4
+#define BIST_CTRL_E_OFFSET 0
+#define BIST_CTRL_NR_E 1
+
+#define BIST_BUSY "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET 31
+#define BIST_CTRL_BIST_BUSY_BLEN 1
+#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW
+
+#define ONE_ERR "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET 30
+#define BIST_CTRL_ONE_ERR_BLEN 1
+#define BIST_CTRL_ONE_ERR_FLAG HSL_RO
+
+#define ERR_MEM "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET 24
+#define BIST_CTRL_ERR_MEM_BLEN 4
+#define BIST_CTRL_ERR_MEM_FLAG HSL_RO
+
+#define PTN_EN2 "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET 22
+#define BIST_CTRL_PTN_EN2_BLEN 1
+#define BIST_CTRL_PTN_EN2_FLAG HSL_RW
+
+#define PTN_EN1 "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET 21
+#define BIST_CTRL_PTN_EN1_BLEN 1
+#define BIST_CTRL_PTN_EN1_FLAG HSL_RW
+
+#define PTN_EN0 "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET 20
+#define BIST_CTRL_PTN_EN0_BLEN 1
+#define BIST_CTRL_PTN_EN0_FLAG HSL_RW
+
+#define ERR_PTN "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET 16
+#define BIST_CTRL_ERR_PTN_BLEN 2
+#define BIST_CTRL_ERR_PTN_FLAG HSL_RO
+
+#define ERR_CNT "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET 13
+#define BIST_CTRL_ERR_CNT_BLEN 3
+#define BIST_CTRL_ERR_CNT_FLAG HSL_RO
+
+#define ERR_ADDR "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET 0
+#define BIST_CTRL_ERR_ADDR_BLEN 13
+#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO
+
+
+
+
+ /* BIST recover Register */
+#define BIST_RCV "brcv"
+#define BIST_RCV_ID 24
+#define BIST_RCV_OFFSET 0x00a4
+#define BIST_RCV_E_LENGTH 4
+#define BIST_RCV_E_OFFSET 0
+#define BIST_RCV_NR_E 1
+
+#define RCV_EN "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET 31
+#define BIST_RCV_RCV_EN_BLEN 1
+#define BIST_RCV_RCV_EN_FLAG HSL_RW
+
+#define RCV_ADDR "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET 0
+#define BIST_RCV_RCV_ADDR_BLEN 13
+#define BIST_RCV_RCV_ADDR_FLAG HSL_RW
+
+
+
+
+ /* LED control Register */
+#define LED_CTRL "ledctrl"
+#define LED_CTRL_ID 25
+#define LED_CTRL_OFFSET 0x00b0
+#define LED_CTRL_E_LENGTH 4
+#define LED_CTRL_E_OFFSET 0
+#define LED_CTRL_NR_E 1
+
+#define PATTERN_EN "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET 14
+#define LED_CTRL_PATTERN_EN_BLEN 2
+#define LED_CTRL_PATTERN_EN_FLAG HSL_RW
+
+#define FULL_LIGHT_EN "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN 1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW
+
+#define HALF_LIGHT_EN "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN 1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW
+
+#define POWERON_LIGHT_EN "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW
+
+#define GE_LIGHT_EN "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10
+#define LED_CTRL_GE_LIGHT_EN_BLEN 1
+#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW
+
+#define FE_LIGHT_EN "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9
+#define LED_CTRL_FE_LIGHT_EN_BLEN 1
+#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW
+
+#define ETH_LIGHT_EN "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN 1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW
+
+#define COL_BLINK_EN "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET 7
+#define LED_CTRL_COL_BLINK_EN_BLEN 1
+#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW
+
+#define RX_BLINK_EN "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET 5
+#define LED_CTRL_RX_BLINK_EN_BLEN 1
+#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW
+
+#define TX_BLINK_EN "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET 4
+#define LED_CTRL_TX_BLINK_EN_BLEN 1
+#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW
+
+#define LINKUP_OVER_EN "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN 1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW
+
+#define BLINK_FREQ "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET 0
+#define LED_CTRL_BLINK_FREQ_BLEN 2
+#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW
+
+
+ /* Port Status Register */
+#define PORT_STATUS "ptsts"
+#define PORT_STATUS_ID 29
+#define PORT_STATUS_OFFSET 0x0100
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0100
+#define PORT_STATUS_NR_E 6
+
+#define FLOW_LINK_EN "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN 1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW
+
+
+#define LINK_ASYN_PAUSE "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO
+
+#define LINK_PAUSE "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET 10
+#define PORT_STATUS_LINK_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO
+
+#define LINK_EN "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW
+
+#define DUPLEX_MODE "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+
+ /* Port Control Register */
+#define PORT_CTL "pctl"
+#define PORT_CTL_ID 30
+#define PORT_CTL_OFFSET 0x0104
+#define PORT_CTL_E_LENGTH 4
+#define PORT_CTL_E_OFFSET 0x0100
+#define PORT_CTL_NR_E 6
+
+#define LEAVE_EN "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET 21
+#define PORT_CTL_LEAVE_EN_BLEN 1
+#define PORT_CTL_LEAVE_EN_FLAG HSL_RW
+
+#define JOIN_EN "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET 20
+#define PORT_CTL_JOIN_EN_BLEN 1
+#define PORT_CTL_JOIN_EN_FLAG HSL_RW
+
+#define DHCP_EN "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET 19
+#define PORT_CTL_DHCP_EN_BLEN 1
+#define PORT_CTL_DHCP_EN_FLAG HSL_RW
+
+#define ING_MIRROR_EN "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17
+#define PORT_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define EG_MIRROR_EN "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16
+#define PORT_CTL_EG_MIRROR_EN_BLEN 1
+#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW
+
+#define DTAG_EN "pctl_dtagen"
+#define PORT_CTL_DTAG_EN_BOFFSET 15
+#define PORT_CTL_DTAG_EN_BLEN 1
+#define PORT_CTL_DTAG_EN_FLAG HSL_RW
+
+#define LEARN_EN "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET 14
+#define PORT_CTL_LEARN_EN_BLEN 1
+#define PORT_CTL_LEARN_EN_FLAG HSL_RW
+
+#define SINGLE_VLAN_EN "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW
+
+#define MAC_LOOP_BACK "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN 1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW
+
+#define HEAD_EN "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET 11
+#define PORT_CTL_HEAD_EN_BLEN 1
+#define PORT_CTL_HEAD_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10
+#define PORT_CTL_IGMP_MLD_EN_BLEN 1
+#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW
+
+#define EG_VLAN_MODE "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8
+#define PORT_CTL_EG_VLAN_MODE_BLEN 2
+#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW
+
+#define LEARN_ONE_LOCK "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW
+
+#define PORT_LOCK_EN "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6
+#define PORT_CTL_PORT_LOCK_EN_BLEN 1
+#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW
+
+#define LOCK_DROP_EN "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5
+#define PORT_CTL_LOCK_DROP_EN_BLEN 1
+#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW
+
+#define PORT_STATE "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET 0
+#define PORT_CTL_PORT_STATE_BLEN 3
+#define PORT_CTL_PORT_STATE_FLAG HSL_RW
+
+
+ /* Port Based Vlan Register */
+#define PORT_BASE_VLAN "pbvlan"
+#define PORT_BASE_VLAN_ID 31
+#define PORT_BASE_VLAN_OFFSET 0x0108
+#define PORT_BASE_VLAN_E_LENGTH 4
+#define PORT_BASE_VLAN_E_OFFSET 0x0100
+#define PORT_BASE_VLAN_NR_E 6
+
+#define DOT1Q_MODE "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW
+
+#define ING_PRI "pbvlan_ingpri"
+#define PORT_BASE_VLAN_ING_PRI_BOFFSET 27
+#define PORT_BASE_VLAN_ING_PRI_BLEN 3
+#define PORT_BASE_VLAN_ING_PRI_FLAG HSL_RW
+
+#define FORCE_PVLAN "pbvlan_fpvlan"
+#define PORT_BASE_VLAN_FORCE_PVLAN_BOFFSET 26
+#define PORT_BASE_VLAN_FORCE_PVLAN_BLEN 1
+#define PORT_BASE_VLAN_FORCE_PVLAN_FLAG HSL_RW
+
+#define PORT_VID_MEM "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW
+
+#define ARP_LEAKY_EN "pbvlan_alen"
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_BOFFSET 15
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_ARP_LEAKY_EN_FLAG HSL_RW
+
+#define UNI_LEAKY_EN "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW
+
+#define MUL_LEAKY_EN "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW
+
+#define FORCE_DEF_VID "pbvlan_fdvid"
+#define PORT_BASE_VLAN_FORCE_DEF_VID_BOFFSET 12
+#define PORT_BASE_VLAN_FORCE_DEF_VID_BLEN 1
+#define PORT_BASE_VLAN_FORCE_DEF_VID_FLAG HSL_RW
+
+#define PORT_VID "pbvlan_ptvid"
+#define PORT_BASE_VLAN_PORT_VID_BOFFSET 0
+#define PORT_BASE_VLAN_PORT_VID_BLEN 12
+#define PORT_BASE_VLAN_PORT_VID_FLAG HSL_RW
+
+
+ /* Port Rate Limit0 Register */
+#define RATE_LIMIT0 "rlmt0"
+#define RATE_LIMIT0_ID 32
+#define RATE_LIMIT0_OFFSET 0x010C
+#define RATE_LIMIT0_E_LENGTH 4
+#define RATE_LIMIT0_E_OFFSET 0x0100
+#define RATE_LIMIT0_NR_E 6
+
+#define ADD_RATE_BYTE "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define EG_RATE_EN "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW
+
+#define EG_MNG_RATE_EN "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MNG_RATE_EN "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MUL_RATE_EN "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET 0
+#define RATE_LIMIT0_ING_RATE_BLEN 15
+#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW
+
+
+ /* Priority Control Register */
+#define PRI_CTL "prctl"
+#define PRI_CTL_ID 33
+#define PRI_CTL_OFFSET 0x0110
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x0100
+#define PRI_CTL_NR_E 6
+
+#define PORT_PRI_EN "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET 19
+#define PRI_CTL_PORT_PRI_EN_BLEN 1
+#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_EN "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+#define PORT_PRI_SEL "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0
+#define PRI_CTL_PORT_PRI_SEL_BLEN 2
+#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW
+
+
+ /* Storm Control Register */
+#define STORM_CTL "sctrl"
+#define STORM_CTL_ID 33
+#define STORM_CTL_OFFSET 0x0114
+#define STORM_CTL_E_LENGTH 4
+#define STORM_CTL_E_OFFSET 0x0100
+#define STORM_CTL_NR_E 6
+
+#define UNIT "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET 24
+#define STORM_CTL_UNIT_BLEN 2
+#define STORM_CTL_UNIT_FLAG HSL_RW
+
+#define MUL_EN "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET 10
+#define STORM_CTL_MUL_EN_BLEN 1
+#define STORM_CTL_MUL_EN_FLAG HSL_RW
+
+#define UNI_EN "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET 9
+#define STORM_CTL_UNI_EN_BLEN 1
+#define STORM_CTL_UNI_EN_FLAG HSL_RW
+
+#define BRO_EN "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET 8
+#define STORM_CTL_BRO_EN_BLEN 1
+#define STORM_CTL_BRO_EN_FLAG HSL_RW
+
+#define RATE "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET 0
+#define STORM_CTL_RATE_BLEN 4
+#define STORM_CTL_RATE_FLAG HSL_RW
+
+
+ /* Queue Control Register */
+#define QUEUE_CTL "qctl"
+#define QUEUE_CTL_ID 34
+#define QUEUE_CTL_OFFSET 0x0118
+#define QUEUE_CTL_E_LENGTH 4
+#define QUEUE_CTL_E_OFFSET 0x0100
+#define QUEUE_CTL_NR_E 6
+
+#define PORT_DESC_EN "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN 1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW
+
+#define QUEUE_DESC_EN "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW
+
+#define PORT_DESC_NR "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN 6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW
+
+#define QUEUE3_DESC_NR "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW
+
+#define QUEUE2_DESC_NR "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW
+
+#define QUEUE1_DESC_NR "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW
+
+#define QUEUE0_DESC_NR "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW
+
+
+ /* Port Rate Limit1 Register */
+#define RATE_LIMIT1 "rlmt1"
+#define RATE_LIMIT1_ID 32
+#define RATE_LIMIT1_OFFSET 0x011C
+#define RATE_LIMIT1_E_LENGTH 4
+#define RATE_LIMIT1_E_OFFSET 0x0100
+#define RATE_LIMIT1_NR_E 6
+
+#define EG_Q1_RATE "rlmt_egq1rate"
+#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET 16
+#define RATE_LIMIT1_EG_Q1_RATE_BLEN 15
+#define RATE_LIMIT1_EG_Q1_RATE_FLAG HSL_RW
+
+#define EG_Q0_RATE "rlmt_egq0rate"
+#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET 0
+#define RATE_LIMIT1_EG_Q0_RATE_BLEN 15
+#define RATE_LIMIT1_EG_Q0_RATE_FLAG HSL_RW
+
+
+ /* Port Rate Limit2 Register */
+#define RATE_LIMIT2 "rlmt2"
+#define RATE_LIMIT2_ID 32
+#define RATE_LIMIT2_OFFSET 0x0120
+#define RATE_LIMIT2_E_LENGTH 4
+#define RATE_LIMIT2_E_OFFSET 0x0100
+#define RATE_LIMIT2_NR_E 6
+
+#define EG_Q3_RATE "rlmt_egq3rate"
+#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET 16
+#define RATE_LIMIT2_EG_Q3_RATE_BLEN 15
+#define RATE_LIMIT2_EG_Q3_RATE_FLAG HSL_RW
+
+#define EG_Q2_RATE "rlmt_egq2rate"
+#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET 0
+#define RATE_LIMIT2_EG_Q2_RATE_BLEN 15
+#define RATE_LIMIT2_EG_Q2_RATE_FLAG HSL_RW
+
+
+ /* mib memory info */
+#define MIB_RXBROAD "RxBroad"
+#define MIB_RXBROAD_ID 34
+#define MIB_RXBROAD_OFFSET 0x20000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0x100
+#define MIB_RXBROAD_NR_E 6
+
+#define MIB_RXPAUSE "RxPause"
+#define MIB_RXPAUSE_ID 35
+#define MIB_RXPAUSE_OFFSET 0x20004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0x100
+#define MIB_RXPAUSE_NR_E 6
+
+#define MIB_RXMULTI "RxMulti"
+#define MIB_RXMULTI_ID 36
+#define MIB_RXMULTI_OFFSET 0x20008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0x100
+#define MIB_RXMULTI_NR_E 6
+
+#define MIB_RXFCSERR "RxFcsErr"
+#define MIB_RXFCSERR_ID 37
+#define MIB_RXFCSERR_OFFSET 0x2000c
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0x100
+#define MIB_RXFCSERR_NR_E 6
+
+#define MIB_RXALLIGNERR "RxAllignErr"
+#define MIB_RXALLIGNERR_ID 38
+#define MIB_RXALLIGNERR_OFFSET 0x20010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0x100
+#define MIB_RXALLIGNERR_NR_E 6
+
+#define MIB_RXRUNT "RxRunt"
+#define MIB_RXRUNT_ID 39
+#define MIB_RXRUNT_OFFSET 0x20014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0x100
+#define MIB_RXRUNT_NR_E 6
+
+#define MIB_RXFRAGMENT "RxFragment"
+#define MIB_RXFRAGMENT_ID 40
+#define MIB_RXFRAGMENT_OFFSET 0x20018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0x100
+#define MIB_RXFRAGMENT_NR_E 6
+
+#define MIB_RX64BYTE "Rx64Byte"
+#define MIB_RX64BYTE_ID 41
+#define MIB_RX64BYTE_OFFSET 0x2001c
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0x100
+#define MIB_RX64BYTE_NR_E 6
+
+#define MIB_RX128BYTE "Rx128Byte"
+#define MIB_RX128BYTE_ID 42
+#define MIB_RX128BYTE_OFFSET 0x20020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0x100
+#define MIB_RX128BYTE_NR_E 6
+
+#define MIB_RX256BYTE "Rx256Byte"
+#define MIB_RX256BYTE_ID 43
+#define MIB_RX256BYTE_OFFSET 0x20024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0x100
+#define MIB_RX256BYTE_NR_E 6
+
+#define MIB_RX512BYTE "Rx512Byte"
+#define MIB_RX512BYTE_ID 44
+#define MIB_RX512BYTE_OFFSET 0x20028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0x100
+#define MIB_RX512BYTE_NR_E 6
+
+#define MIB_RX1024BYTE "Rx1024Byte"
+#define MIB_RX1024BYTE_ID 45
+#define MIB_RX1024BYTE_OFFSET 0x2002c
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0x100
+#define MIB_RX1024BYTE_NR_E 6
+
+#define MIB_RX1518BYTE "Rx1518Byte"
+#define MIB_RX1518BYTE_ID 45
+#define MIB_RX1518BYTE_OFFSET 0x20030
+#define MIB_RX1518BYTE_E_LENGTH 4
+#define MIB_RX1518BYTE_E_OFFSET 0x100
+#define MIB_RX1518BYTE_NR_E 6
+
+#define MIB_RXMAXBYTE "RxMaxByte"
+#define MIB_RXMAXBYTE_ID 46
+#define MIB_RXMAXBYTE_OFFSET 0x20034
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0x100
+#define MIB_RXMAXBYTE_NR_E 6
+
+#define MIB_RXTOOLONG "RxTooLong"
+#define MIB_RXTOOLONG_ID 47
+#define MIB_RXTOOLONG_OFFSET 0x20038
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0x100
+#define MIB_RXTOOLONG_NR_E 6
+
+#define MIB_RXGOODBYTE_LO "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID 48
+#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_LO_NR_E 6
+
+#define MIB_RXGOODBYTE_HI "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID 49
+#define MIB_RXGOODBYTE_HI_OFFSET 0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_HI_NR_E 6
+
+#define MIB_RXBADBYTE_LO "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID 50
+#define MIB_RXBADBYTE_LO_OFFSET 0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0x100
+#define MIB_RXBADBYTE_LO_NR_E 6
+
+#define MIB_RXBADBYTE_HI "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID 51
+#define MIB_RXBADBYTE_HI_OFFSET 0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0x100
+#define MIB_RXBADBYTE_HI_NR_E 6
+
+#define MIB_RXOVERFLOW "RxOverFlow"
+#define MIB_RXOVERFLOW_ID 52
+#define MIB_RXOVERFLOW_OFFSET 0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0x100
+#define MIB_RXOVERFLOW_NR_E 6
+
+#define MIB_FILTERED "Filtered"
+#define MIB_FILTERED_ID 53
+#define MIB_FILTERED_OFFSET 0x20050
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0x100
+#define MIB_FILTERED_NR_E 6
+
+#define MIB_TXBROAD "TxBroad"
+#define MIB_TXBROAD_ID 54
+#define MIB_TXBROAD_OFFSET 0x20054
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0x100
+#define MIB_TXBROAD_NR_E 6
+
+#define MIB_TXPAUSE "TxPause"
+#define MIB_TXPAUSE_ID 55
+#define MIB_TXPAUSE_OFFSET 0x20058
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0x100
+#define MIB_TXPAUSE_NR_E 6
+
+#define MIB_TXMULTI "TxMulti"
+#define MIB_TXMULTI_ID 56
+#define MIB_TXMULTI_OFFSET 0x2005c
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0x100
+#define MIB_TXMULTI_NR_E 6
+
+#define MIB_TXUNDERRUN "TxUnderRun"
+#define MIB_TXUNDERRUN_ID 57
+#define MIB_TXUNDERRUN_OFFSET 0x20060
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0x100
+#define MIB_TXUNDERRUN_NR_E 6
+
+#define MIB_TX64BYTE "Tx64Byte"
+#define MIB_TX64BYTE_ID 58
+#define MIB_TX64BYTE_OFFSET 0x20064
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0x100
+#define MIB_TX64BYTE_NR_E 6
+
+#define MIB_TX128BYTE "Tx128Byte"
+#define MIB_TX128BYTE_ID 59
+#define MIB_TX128BYTE_OFFSET 0x20068
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0x100
+#define MIB_TX128BYTE_NR_E 6
+
+#define MIB_TX256BYTE "Tx256Byte"
+#define MIB_TX256BYTE_ID 60
+#define MIB_TX256BYTE_OFFSET 0x2006c
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0x100
+#define MIB_TX256BYTE_NR_E 6
+
+#define MIB_TX512BYTE "Tx512Byte"
+#define MIB_TX512BYTE_ID 61
+#define MIB_TX512BYTE_OFFSET 0x20070
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0x100
+#define MIB_TX512BYTE_NR_E 6
+
+#define MIB_TX1024BYTE "Tx1024Byte"
+#define MIB_TX1024BYTE_ID 62
+#define MIB_TX1024BYTE_OFFSET 0x20074
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0x100
+#define MIB_TX1024BYTE_NR_E 6
+
+#define MIB_TX1518BYTE "Tx1518Byte"
+#define MIB_TX1518BYTE_ID 62
+#define MIB_TX1518BYTE_OFFSET 0x20078
+#define MIB_TX1518BYTE_E_LENGTH 4
+#define MIB_TX1518BYTE_E_OFFSET 0x100
+#define MIB_TX1518BYTE_NR_E 6
+
+#define MIB_TXMAXBYTE "TxMaxByte"
+#define MIB_TXMAXBYTE_ID 63
+#define MIB_TXMAXBYTE_OFFSET 0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0x100
+#define MIB_TXMAXBYTE_NR_E 6
+
+#define MIB_TXOVERSIZE "TxOverSize"
+#define MIB_TXOVERSIZE_ID 64
+#define MIB_TXOVERSIZE_OFFSET 0x20080
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0x100
+#define MIB_TXOVERSIZE_NR_E 6
+
+#define MIB_TXBYTE_LO "TxByteLo"
+#define MIB_TXBYTE_LO_ID 65
+#define MIB_TXBYTE_LO_OFFSET 0x20084
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0x100
+#define MIB_TXBYTE_LO_NR_E 6
+
+#define MIB_TXBYTE_HI "TxByteHi"
+#define MIB_TXBYTE_HI_ID 66
+#define MIB_TXBYTE_HI_OFFSET 0x20088
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0x100
+#define MIB_TXBYTE_HI_NR_E 6
+
+#define MIB_TXCOLLISION "TxCollision"
+#define MIB_TXCOLLISION_ID 67
+#define MIB_TXCOLLISION_OFFSET 0x2008c
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0x100
+#define MIB_TXCOLLISION_NR_E 6
+
+#define MIB_TXABORTCOL "TxAbortCol"
+#define MIB_TXABORTCOL_ID 68
+#define MIB_TXABORTCOL_OFFSET 0x20090
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0x100
+#define MIB_TXABORTCOL_NR_E 6
+
+#define MIB_TXMULTICOL "TxMultiCol"
+#define MIB_TXMULTICOL_ID 69
+#define MIB_TXMULTICOL_OFFSET 0x20094
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0x100
+#define MIB_TXMULTICOL_NR_E 6
+
+#define MIB_TXSINGALCOL "TxSingalCol"
+#define MIB_TXSINGALCOL_ID 70
+#define MIB_TXSINGALCOL_OFFSET 0x20098
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0x100
+#define MIB_TXSINGALCOL_NR_E 6
+
+#define MIB_TXEXCDEFER "TxExcDefer"
+#define MIB_TXEXCDEFER_ID 71
+#define MIB_TXEXCDEFER_OFFSET 0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0x100
+#define MIB_TXEXCDEFER_NR_E 6
+
+#define MIB_TXDEFER "TxDefer"
+#define MIB_TXDEFER_ID 72
+#define MIB_TXDEFER_OFFSET 0x200a0
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0x100
+#define MIB_TXDEFER_NR_E 6
+
+#define MIB_TXLATECOL "TxLateCol"
+#define MIB_TXLATECOL_ID 73
+#define MIB_TXLATECOL_OFFSET 0x200a4
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0x100
+#define MIB_TXLATECOL_NR_E 6
+
+#if 0
+ /* mib info second mem block */
+#define MIB_RXBROAD_2 "RxBroad_2"
+#define MIB_RXBROAD_2_ID 34
+#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH 4
+#define MIB_RXBROAD_2_E_OFFSET 0xa8
+#define MIB_RXBROAD_2_NR_E 6
+
+#define MIB_RXPAUSE_2 "RxPause_2"
+#define MIB_RXPAUSE_2_ID 35
+#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH 4
+#define MIB_RXPAUSE_2_E_OFFSET 0xa8
+#define MIB_RXPAUSE_2_NR_E 6
+
+#define MIB_RXMULTI_2 "RxMulti_2"
+#define MIB_RXMULTI_2_ID 36
+#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH 4
+#define MIB_RXMULTI_2_E_OFFSET 0xa8
+#define MIB_RXMULTI_2_NR_E 6
+
+#define MIB_RXFCSERR_2 "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID 37
+#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH 4
+#define MIB_RXFCSERR_2_E_OFFSET 0xa8
+#define MIB_RXFCSERR_2_NR_E 6
+
+#define MIB_RXALLIGNERR_2 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID 38
+#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH 4
+#define MIB_RXALLIGNERR_2_E_OFFSET 0xa8
+#define MIB_RXALLIGNERR_2_NR_E 6
+
+#define MIB_RXRUNT_2 "RxRunt_2"
+#define MIB_RXRUNT_2_ID 39
+#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH 4
+#define MIB_RXRUNT_2_E_OFFSET 0xa8
+#define MIB_RXRUNT_2_NR_E 6
+
+#define MIB_RXFRAGMENT_2 "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID 40
+#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH 4
+#define MIB_RXFRAGMENT_2_E_OFFSET 0xa8
+#define MIB_RXFRAGMENT_2_NR_E 6
+
+#define MIB_RX64BYTE_2 "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID 41
+#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH 4
+#define MIB_RX64BYTE_2_E_OFFSET 0xa8
+#define MIB_RX64BYTE_2_NR_E 6
+
+#define MIB_RX128BYTE_2 "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID 42
+#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH 4
+#define MIB_RX128BYTE_2_E_OFFSET 0xa8
+#define MIB_RX128BYTE_2_NR_E 6
+
+#define MIB_RX256BYTE_2 "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID 43
+#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH 4
+#define MIB_RX256BYTE_2_E_OFFSET 0xa8
+#define MIB_RX256BYTE_2_NR_E 6
+
+#define MIB_RX512BYTE_2 "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID 44
+#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH 4
+#define MIB_RX512BYTE_2_E_OFFSET 0xa8
+#define MIB_RX512BYTE_2_NR_E 6
+
+#define MIB_RX1024BYTE_2 "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID 45
+#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH 4
+#define MIB_RX1024BYTE_2_E_OFFSET 0xa8
+#define MIB_RX1024BYTE_2_NR_E 6
+
+#define MIB_RX1518BYTE_2 "Rx1518Byte_2"
+#define MIB_RX1518BYTE_2_ID 45
+#define MIB_RX1518BYTE_2_OFFSET (MIB_RX1518BYTE_OFFSET + 0x400)
+#define MIB_RX1518BYTE_2_E_LENGTH 4
+#define MIB_RX1518BYTE_2_E_OFFSET 0xa8
+#define MIB_RX1518BYTE_2_NR_E 6
+
+#define MIB_RXMAXBYTE_2 "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID 46
+#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH 4
+#define MIB_RXMAXBYTE_2_E_OFFSET 0xa8
+#define MIB_RXMAXBYTE_2_NR_E 6
+
+#define MIB_RXTOOLONG_2 "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID 47
+#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH 4
+#define MIB_RXTOOLONG_2_E_OFFSET 0xa8
+#define MIB_RXTOOLONG_2_NR_E 6
+
+#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID 48
+#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_RXGOODBYTE_LO_2_NR_E 6
+
+#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID 49
+#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_RXGOODBYTE_HI_2_NR_E 6
+
+#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID 50
+#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_RXBADBYTE_LO_2_NR_E 6
+
+#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID 51
+#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_RXBADBYTE_HI_2_NR_E 6
+
+#define MIB_RXOVERFLOW_2 "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID 52
+#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH 4
+#define MIB_RXOVERFLOW_2_E_OFFSET 0xa8
+#define MIB_RXOVERFLOW_2_NR_E 6
+
+#define MIB_FILTERED_2 "Filtered_2"
+#define MIB_FILTERED_2_ID 53
+#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH 4
+#define MIB_FILTERED_2_E_OFFSET 0xa8
+#define MIB_FILTERED_2_NR_E 6
+
+#define MIB_TXBROAD_2 "TxBroad_2"
+#define MIB_TXBROAD_2_ID 54
+#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH 4
+#define MIB_TXBROAD_2_E_OFFSET 0xa8
+#define MIB_TXBROAD_2_NR_E 6
+
+#define MIB_TXPAUSE_2 "TxPause_2"
+#define MIB_TXPAUSE_2_ID 55
+#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH 4
+#define MIB_TXPAUSE_2_E_OFFSET 0xa8
+#define MIB_TXPAUSE_2_NR_E 6
+
+#define MIB_TXMULTI_2 "TxMulti_2"
+#define MIB_TXMULTI_2_ID 56
+#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH 4
+#define MIB_TXMULTI_2_E_OFFSET 0xa8
+#define MIB_TXMULTI_2_NR_E 6
+
+#define MIB_TXUNDERRUN_2 "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID 57
+#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH 4
+#define MIB_TXUNDERRUN_2_E_OFFSET 0xa8
+#define MIB_TXUNDERRUN_2_NR_E 6
+
+#define MIB_TX64BYTE_2 "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID 58
+#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH 4
+#define MIB_TX64BYTE_2_E_OFFSET 0xa8
+#define MIB_TX64BYTE_2_NR_E 6
+
+#define MIB_TX128BYTE_2 "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID 59
+#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH 4
+#define MIB_TX128BYTE_2_E_OFFSET 0xa8
+#define MIB_TX128BYTE_2_NR_E 6
+
+#define MIB_TX256BYTE_2 "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID 60
+#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH 4
+#define MIB_TX256BYTE_2_E_OFFSET 0xa8
+#define MIB_TX256BYTE_2_NR_E 6
+
+#define MIB_TX512BYTE_2 "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID 61
+#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH 4
+#define MIB_TX512BYTE_2_E_OFFSET 0xa8
+#define MIB_TX512BYTE_2_NR_E 6
+
+#define MIB_TX1024BYTE_2 "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID 62
+#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH 4
+#define MIB_TX1024BYTE_2_E_OFFSET 0xa8
+#define MIB_TX1024BYTE_2_NR_E 6
+
+#define MIB_TX1518BYTE_2 "Tx1518Byte_2"
+#define MIB_TX1518BYTE_2_ID 62
+#define MIB_TX1518BYTE_2_OFFSET (MIB_TX1518BYTE_OFFSET + 0x400)
+#define MIB_TX1518BYTE_2_E_LENGTH 4
+#define MIB_TX1518BYTE_2_E_OFFSET 0xa8
+#define MIB_TX1518BYTE_2_NR_E 6
+
+#define MIB_TXMAXBYTE_2 "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID 63
+#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH 4
+#define MIB_TXMAXBYTE_2_E_OFFSET 0xa8
+#define MIB_TXMAXBYTE_2_NR_E 6
+
+#define MIB_TXOVERSIZE_2 "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID 64
+#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH 4
+#define MIB_TXOVERSIZE_2_E_OFFSET 0xa8
+#define MIB_TXOVERSIZE_2_NR_E 6
+
+#define MIB_TXBYTE_LO_2 "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID 65
+#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH 4
+#define MIB_TXBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_TXBYTE_LO_2_NR_E 6
+
+#define MIB_TXBYTE_HI_2 "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID 66
+#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH 4
+#define MIB_TXBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_TXBYTE_HI_2_NR_E 6
+
+#define MIB_TXCOLLISION_2 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID 67
+#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH 4
+#define MIB_TXCOLLISION_2_E_OFFSET 0xa8
+#define MIB_TXCOLLISION_2_NR_E 6
+
+#define MIB_TXABORTCOL_2 "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID 68
+#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH 4
+#define MIB_TXABORTCOL_2_E_OFFSET 0xa8
+#define MIB_TXABORTCOL_2_NR_E 6
+
+#define MIB_TXMULTICOL_2 "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID 69
+#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH 4
+#define MIB_TXMULTICOL_2_E_OFFSET 0xa8
+#define MIB_TXMULTICOL_2_NR_E 6
+
+#define MIB_TXSINGALCOL_2 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID 70
+#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH 4
+#define MIB_TXSINGALCOL_2_E_OFFSET 0xa8
+#define MIB_TXSINGALCOL_2_NR_E 6
+
+#define MIB_TXEXCDEFER_2 "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID 71
+#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH 4
+#define MIB_TXEXCDEFER_2_E_OFFSET 0xa8
+#define MIB_TXEXCDEFER_2_NR_E 6
+
+#define MIB_TXDEFER_2 "TxDefer_2"
+#define MIB_TXDEFER_2_ID 72
+#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH 4
+#define MIB_TXDEFER_2_E_OFFSET 0xa8
+#define MIB_TXDEFER_2_NR_E 6
+
+#define MIB_TXLATECOL_2 "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID 73
+#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH 4
+#define MIB_TXLATECOL_2_E_OFFSET 0xa8
+#define MIB_TXLATECOL_2_NR_E 6
+#endif
+
+#define ACL_RSLT "aclact"
+#define ACL_RSLT_ID 13
+#define ACL_RSLT_OFFSET 0x58000
+#define ACL_RSLT_E_LENGTH 4
+#define ACL_RSLT_E_OFFSET 0x20
+#define ACL_RSLT_NR_E 32
+
+#define RDTCPU "aclact_rdtpu"
+#define ACL_RSLT_RDTCPU_BOFFSET 31
+#define ACL_RSLT_RDTCPU_BLEN 1
+#define ACL_RSLT_RDTCPU_FLAG HSL_RW
+
+#define CPYCPU "aclact_cpcpu"
+#define ACL_RSLT_CPYCPU_BOFFSET 30
+#define ACL_RSLT_CPYCPU_BLEN 1
+#define ACL_RSLT_CPYCPU_FLAG HSL_RW
+
+#define MIRR_EN "aclact_mirr"
+#define ACL_RSLT_MIRR_EN_BOFFSET 29
+#define ACL_RSLT_MIRR_EN_BLEN 1
+#define ACL_RSLT_MIRR_EN_FLAG HSL_RW
+
+#define STAG_CHG_EN "aclact_rdcpu"
+#define ACL_RSLT_STAG_CHG_EN_BOFFSET 28
+#define ACL_RSLT_STAG_CHG_EN_BLEN 1
+#define ACL_RSLT_STAG_CHG_EN_FLAG HSL_RW
+
+#define VID_MEM_EN "aclact_rdcpu"
+#define ACL_RSLT_VID_MEM_EN_BOFFSET 27
+#define ACL_RSLT_VID_MEM_EN_BLEN 1
+#define ACL_RSLT_VID_MEM_EN_FLAG HSL_RW
+
+#define DES_PORT_EN "aclact_rdcpu"
+#define ACL_RSLT_DES_PORT_EN_BOFFSET 26
+#define ACL_RSLT_DES_PORT_EN_BLEN 1
+#define ACL_RSLT_DES_PORT_EN_FLAG HSL_RW
+
+#define PORT_MEM "aclact_rdcpu"
+#define ACL_RSLT_PORT_MEM_BOFFSET 20
+#define ACL_RSLT_PORT_MEM_BLEN 6
+#define ACL_RSLT_PORT_MEM_FLAG HSL_RW
+
+#define REMARK_PRI_QU "aclact_rdcpu"
+#define ACL_RSLT_REMARK_PRI_QU_BOFFSET 19
+#define ACL_RSLT_REMARK_PRI_QU_BLEN 1
+#define ACL_RSLT_REMARK_PRI_QU_FLAG HSL_RW
+
+#define DOT1P "aclact_rdcpu"
+#define ACL_RSLT_DOT1P_BOFFSET 16
+#define ACL_RSLT_DOT1P_BLEN 3
+#define ACL_RSLT_DOT1P_FLAG HSL_RW
+
+#define PRI_QU "aclact_rdcpu"
+#define ACL_RSLT_PRI_QU_BOFFSET 14
+#define ACL_RSLT_PRI_QU_BLEN 2
+#define ACL_RSLT_PRI_QU_FLAG HSL_RW
+
+#define REMARK_DOT1P "aclact_rdcpu"
+#define ACL_RSLT_REMARK_DOT1P_BOFFSET 13
+#define ACL_RSLT_REMARK_DOT1P_BLEN 1
+#define ACL_RSLT_REMARK_DOT1P_FLAG HSL_RW
+
+#define CHG_VID_EN "aclact_rdcpu"
+#define ACL_RSLT_CHG_VID_EN_BOFFSET 12
+#define ACL_RSLT_CHG_VID_EN_BLEN 1
+#define ACL_RSLT_CHG_VID_EN_FLAG HSL_RW
+
+#define VID "aclact_rdcpu"
+#define ACL_RSLT_VID_BOFFSET 0
+#define ACL_RSLT_VID_BLEN 12
+#define ACL_RSLT_VID_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT0 "rulslct0"
+#define RUL_SLCT0_ID 13
+#define RUL_SLCT0_OFFSET 0x58800
+#define RUL_SLCT0_E_LENGTH 4
+#define RUL_SLCT0_E_OFFSET 0x20
+#define RUL_SLCT0_NR_E 32
+
+#define ADDR3_EN "rulslct_addr3en"
+#define RUL_SLCT0_ADDR3_EN_BOFFSET 3
+#define RUL_SLCT0_ADDR3_EN_BLEN 1
+#define RUL_SLCT0_ADDR3_EN_FLAG HSL_RW
+
+#define ADDR2_EN "rulslct_addr2en"
+#define RUL_SLCT0_ADDR2_EN_BOFFSET 2
+#define RUL_SLCT0_ADDR2_EN_BLEN 1
+#define RUL_SLCT0_ADDR2_EN_FLAG HSL_RW
+
+#define ADDR1_EN "rulslct_addr1en"
+#define RUL_SLCT0_ADDR1_EN_BOFFSET 1
+#define RUL_SLCT0_ADDR1_EN_BLEN 1
+#define RUL_SLCT0_ADDR1_EN_FLAG HSL_RW
+
+#define ADDR0_EN "rulslct_addr0en"
+#define RUL_SLCT0_ADDR0_EN_BOFFSET 0
+#define RUL_SLCT0_ADDR0_EN_BLEN 1
+#define RUL_SLCT0_ADDR0_EN_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT1 "rulslct1"
+#define RUL_SLCT1_ID 13
+#define RUL_SLCT1_OFFSET 0x58804
+#define RUL_SLCT1_E_LENGTH 4
+#define RUL_SLCT1_E_OFFSET 0x20
+#define RUL_SLCT1_NR_E 32
+
+#define ADDR0 "rulslct1_addr0"
+#define RUL_SLCT1_ADDR0_BOFFSET 0
+#define RUL_SLCT1_ADDR0_BLEN 5
+#define RUL_SLCT1_ADDR0_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT2 "rulslct2"
+#define RUL_SLCT2_ID 13
+#define RUL_SLCT2_OFFSET 0x58808
+#define RUL_SLCT2_E_LENGTH 4
+#define RUL_SLCT2_E_OFFSET 0x20
+#define RUL_SLCT2_NR_E 32
+
+#define ADDR1 "rulslct2_addr1"
+#define RUL_SLCT2_ADDR1_BOFFSET 0
+#define RUL_SLCT2_ADDR1_BLEN 5
+#define RUL_SLCT2_ADDR1_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT3 "rulslct3"
+#define RUL_SLCT3_ID 13
+#define RUL_SLCT3_OFFSET 0x5880c
+#define RUL_SLCT3_E_LENGTH 4
+#define RUL_SLCT3_E_OFFSET 0x20
+#define RUL_SLCT3_NR_E 32
+
+#define ADDR2 "rulslct3_addr2"
+#define RUL_SLCT3_ADDR2_BOFFSET 0
+#define RUL_SLCT3_ADDR2_BLEN 5
+#define RUL_SLCT3_ADDR2_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT4 "rulslct4"
+#define RUL_SLCT4_ID 13
+#define RUL_SLCT4_OFFSET 0x58810
+#define RUL_SLCT4_E_LENGTH 4
+#define RUL_SLCT4_E_OFFSET 0x20
+#define RUL_SLCT4_NR_E 32
+
+#define ADDR3 "rulslct4_addr3"
+#define RUL_SLCT4_ADDR3_BOFFSET 0
+#define RUL_SLCT4_ADDR3_BLEN 5
+#define RUL_SLCT4_ADDR3_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT6 "rulslct6"
+#define RUL_SLCT6_ID 13
+#define RUL_SLCT6_OFFSET 0x58818
+#define RUL_SLCT6_E_LENGTH 4
+#define RUL_SLCT6_E_OFFSET 0x20
+#define RUL_SLCT6_NR_E 32
+
+#define RULE_LEN "rulslct6_rulelen"
+#define RUL_SLCT6_RULE_LEN_BOFFSET 0
+#define RUL_SLCT6_RULE_LEN_BLEN 6
+#define RUL_SLCT6_RULE_LEN_FLAG HSL_RW
+
+
+
+
+#define RUL_TYPE "ruletype"
+#define RUL_TYPE_ID 13
+#define RUL_TYPE_OFFSET 0x5881c
+#define RUL_TYPE_E_LENGTH 4
+#define RUL_TYPE_E_OFFSET 0x20
+#define RUL_TYPE_NR_E 32
+
+#define TYP "ruletype_typ"
+#define RUL_TYPE_TYP_BOFFSET 0
+#define RUL_TYPE_TYP_BLEN 3
+#define RUL_TYPE_TYP_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V0 "macrv0"
+#define MAC_RUL_V0_ID 13
+#define MAC_RUL_V0_OFFSET 0x58400
+#define MAC_RUL_V0_E_LENGTH 4
+#define MAC_RUL_V0_E_OFFSET 0x20
+#define MAC_RUL_V0_NR_E 32
+
+#define DAV_BYTE2 "macrv0_dav2"
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3 "macrv0_dav3"
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4 "macrv0_dav4"
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5 "macrv0_dav5"
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V1 "macrv1"
+#define MAC_RUL_V1_ID 13
+#define MAC_RUL_V1_OFFSET 0x58404
+#define MAC_RUL_V1_E_LENGTH 4
+#define MAC_RUL_V1_E_OFFSET 0x20
+#define MAC_RUL_V1_NR_E 32
+
+#define SAV_BYTE4 "macrv1_sav4"
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5 "macrv1_sav5"
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0 "macrv1_dav0"
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1 "macrv1_dav1"
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V2 "macrv2"
+#define MAC_RUL_V2_ID 13
+#define MAC_RUL_V2_OFFSET 0x58408
+#define MAC_RUL_V2_E_LENGTH 4
+#define MAC_RUL_V2_E_OFFSET 0x20
+#define MAC_RUL_V2_NR_E 32
+
+#define SAV_BYTE0 "macrv2_sav0"
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW
+
+#define SAV_BYTE1 "macrv2_sav1"
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW
+
+#define SAV_BYTE2 "macrv2_sav2"
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW
+
+#define SAV_BYTE3 "macrv2_sav3"
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V3 "macrv3"
+#define MAC_RUL_V3_ID 13
+#define MAC_RUL_V3_OFFSET 0x5840c
+#define MAC_RUL_V3_E_LENGTH 4
+#define MAC_RUL_V3_E_OFFSET 0x20
+#define MAC_RUL_V3_NR_E 32
+
+#define ETHTYPV "macrv3_ethtypv"
+#define MAC_RUL_V3_ETHTYPV_BOFFSET 16
+#define MAC_RUL_V3_ETHTYPV_BLEN 16
+#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define VLANPRIV "macrv3_vlanpriv"
+#define MAC_RUL_V3_VLANPRIV_BOFFSET 13
+#define MAC_RUL_V3_VLANPRIV_BLEN 3
+#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW
+
+#define VLANIDV "macrv3_vlanidv"
+#define MAC_RUL_V3_VLANIDV_BOFFSET 0
+#define MAC_RUL_V3_VLANIDV_BLEN 12
+#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V4 "macrv4"
+#define MAC_RUL_V4_ID 13
+#define MAC_RUL_V4_OFFSET 0x58410
+#define MAC_RUL_V4_E_LENGTH 4
+#define MAC_RUL_V4_E_OFFSET 0x20
+#define MAC_RUL_V4_NR_E 32
+
+#define TAGGEDM "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDM_BOFFSET 7
+#define MAC_RUL_V4_TAGGEDM_BLEN 1
+#define MAC_RUL_V4_TAGGEDM_FLAG HSL_RW
+
+#define TAGGEDV "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDV_BOFFSET 6
+#define MAC_RUL_V4_TAGGEDV_BLEN 1
+#define MAC_RUL_V4_TAGGEDV_FLAG HSL_RW
+
+#define MAC_INPT "macrv4_vlanid"
+#define MAC_RUL_V4_MAC_INPT_BOFFSET 0
+#define MAC_RUL_V4_MAC_INPT_BLEN 6
+#define MAC_RUL_V4_MAC_INPT_FLAG HSL_RW
+
+
+
+
+
+#define MAC_RUL_M0 "macrv0"
+#define MAC_RUL_M0_ID 13
+#define MAC_RUL_M0_OFFSET 0x58c00
+#define MAC_RUL_M0_E_LENGTH 4
+#define MAC_RUL_M0_E_OFFSET 0x20
+#define MAC_RUL_M0_NR_E 32
+
+#define DAM_BYTE2 "macrv0_dam2"
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3 "macrv0_dam3"
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4 "macrv0_dam4"
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5 "macrv0_dam5"
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M1 "macrm1"
+#define MAC_RUL_M1_ID 13
+#define MAC_RUL_M1_OFFSET 0x58c04
+#define MAC_RUL_M1_E_LENGTH 4
+#define MAC_RUL_M1_E_OFFSET 0x20
+#define MAC_RUL_M1_NR_E 32
+
+#define SAM_BYTE4 "macrm1_sam4"
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5 "macrm1_sam5"
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0 "macrm1_dam0"
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1 "macrm1_dam1"
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M2 "macrm2"
+#define MAC_RUL_M2_ID 13
+#define MAC_RUL_M2_OFFSET 0x58c08
+#define MAC_RUL_M2_E_LENGTH 4
+#define MAC_RUL_M2_E_OFFSET 0x20
+#define MAC_RUL_M2_NR_E 32
+
+#define SAM_BYTE0 "macrm2_sam0"
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW
+
+#define SAM_BYTE1 "macrm2_samv1"
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW
+
+#define SAM_BYTE2 "macrm2_sam2"
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW
+
+#define SAM_BYTE3 "macrm2_sam3"
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M3 "macrv3"
+#define MAC_RUL_M3_ID 13
+#define MAC_RUL_M3_OFFSET 0x58c0c
+#define MAC_RUL_M3_E_LENGTH 4
+#define MAC_RUL_M3_E_OFFSET 0x20
+#define MAC_RUL_M3_NR_E 32
+
+#define ETHTYPM "macrm3_ethtypm"
+#define MAC_RUL_M3_ETHTYPM_BOFFSET 16
+#define MAC_RUL_M3_ETHTYPM_BLEN 16
+#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define VLANPRIM "macrm3_vlanprim"
+#define MAC_RUL_M3_VLANPRIM_BOFFSET 13
+#define MAC_RUL_M3_VLANPRIM_BLEN 3
+#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW
+
+#define VIDMSK "macrm3_vidmsk"
+#define MAC_RUL_M3_VIDMSK_BOFFSET 12
+#define MAC_RUL_M3_VIDMSK_BLEN 1
+#define MAC_RUL_M3_VIDMSK_FLAG HSL_RW
+
+#define VLANIDM "macrm3_vlanidm"
+#define MAC_RUL_M3_VLANIDM_BOFFSET 0
+#define MAC_RUL_M3_VLANIDM_BLEN 12
+#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V0 "ip4v0"
+#define IP4_RUL_V0_ID 13
+#define IP4_RUL_V0_OFFSET 0x58400
+#define IP4_RUL_V0_E_LENGTH 4
+#define IP4_RUL_V0_E_OFFSET 0x20
+#define IP4_RUL_V0_NR_E 32
+
+#define DIPV "ip4v0_dipv"
+#define IP4_RUL_V0_DIPV_BOFFSET 0
+#define IP4_RUL_V0_DIPV_BLEN 32
+#define IP4_RUL_V0_DIPV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V1 "ip4v1"
+#define IP4_RUL_V1_ID 13
+#define IP4_RUL_V1_OFFSET 0x58404
+#define IP4_RUL_V1_E_LENGTH 4
+#define IP4_RUL_V1_E_OFFSET 0x20
+#define IP4_RUL_V1_NR_E 32
+
+#define SIPV "ip4v1_sipv"
+#define IP4_RUL_V1_SIPV_BOFFSET 0
+#define IP4_RUL_V1_SIPV_BLEN 32
+#define IP4_RUL_V1_SIPV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V2 "ip4v2"
+#define IP4_RUL_V2_ID 13
+#define IP4_RUL_V2_OFFSET 0x58408
+#define IP4_RUL_V2_E_LENGTH 4
+#define IP4_RUL_V2_E_OFFSET 0x20
+#define IP4_RUL_V2_NR_E 32
+
+#define IP4PROTV "ip4v2_protv"
+#define IP4_RUL_V2_IP4PROTV_BOFFSET 0
+#define IP4_RUL_V2_IP4PROTV_BLEN 8
+#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW
+
+#define IP4DSCPV "ip4v2_dscpv"
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8
+#define IP4_RUL_V2_IP4DSCPV_BLEN 8
+#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW
+
+#define IP4DPORTV "ip4v2_dportv"
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16
+#define IP4_RUL_V2_IP4DPORTV_BLEN 16
+#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V3 "ip4v3"
+#define IP4_RUL_V3_ID 13
+#define IP4_RUL_V3_OFFSET 0x5840c
+#define IP4_RUL_V3_E_LENGTH 4
+#define IP4_RUL_V3_E_OFFSET 0x20
+#define IP4_RUL_V3_NR_E 32
+
+#define IP4SPORTV "ip4v3_sportv"
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0
+#define IP4_RUL_V3_IP4SPORTV_BLEN 16
+#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW
+
+
+#define IP4_RUL_V4 "ip4v2"
+#define IP4_RUL_V4_ID 13
+#define IP4_RUL_V4_OFFSET 0x58410
+#define IP4_RUL_V4_E_LENGTH 4
+#define IP4_RUL_V4_E_OFFSET 0x20
+#define IP4_RUL_V4_NR_E 32
+
+#define IP4_INPT "ip4rv4_inpt"
+#define IP4_RUL_V4_IP4_INPT_BOFFSET 0
+#define IP4_RUL_V4_IP4_INPT_BLEN 6
+#define IP4_RUL_V4_IP4_INPT_FLAG HSL_RW
+
+
+
+
+
+
+#define IP4_RUL_M0 "ip4m0"
+#define IP4_RUL_M0_ID 13
+#define IP4_RUL_M0_OFFSET 0x58c00
+#define IP4_RUL_M0_E_LENGTH 4
+#define IP4_RUL_M0_E_OFFSET 0x20
+#define IP4_RUL_M0_NR_E 32
+
+#define DIPM "ip4m0_dipm"
+#define IP4_RUL_M0_DIPM_BOFFSET 0
+#define IP4_RUL_M0_DIPM_BLEN 32
+#define IP4_RUL_M0_DIPM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M1 "ip4m1"
+#define IP4_RUL_M1_ID 13
+#define IP4_RUL_M1_OFFSET 0x58c04
+#define IP4_RUL_M1_E_LENGTH 4
+#define IP4_RUL_M1_E_OFFSET 0x20
+#define IP4_RUL_M1_NR_E 32
+
+#define SIPM "ip4m1_sipm"
+#define IP4_RUL_M1_SIPM_BOFFSET 0
+#define IP4_RUL_M1_SIPM_BLEN 32
+#define IP4_RUL_M1_SIPM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M2 "ip4m2"
+#define IP4_RUL_M2_ID 13
+#define IP4_RUL_M2_OFFSET 0x58c08
+#define IP4_RUL_M2_E_LENGTH 4
+#define IP4_RUL_M2_E_OFFSET 0x20
+#define IP4_RUL_M2_NR_E 32
+
+#define IP4PROTM "ip4m2_protm"
+#define IP4_RUL_M2_IP4PROTM_BOFFSET 0
+#define IP4_RUL_M2_IP4PROTM_BLEN 8
+#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW
+
+#define IP4DSCPM "ip4m2_dscpm"
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8
+#define IP4_RUL_M2_IP4DSCPM_BLEN 8
+#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW
+
+#define IP4DPORTM "ip4m2_dportm"
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16
+#define IP4_RUL_M2_IP4DPORTM_BLEN 16
+#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M3 "ip4m3"
+#define IP4_RUL_M3_ID 13
+#define IP4_RUL_M3_OFFSET 0x58c0c
+#define IP4_RUL_M3_E_LENGTH 4
+#define IP4_RUL_M3_E_OFFSET 0x20
+#define IP4_RUL_M3_NR_E 32
+
+#define IP4SPORTM "ip4m3_sportm"
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0
+#define IP4_RUL_M3_IP4SPORTM_BLEN 16
+#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW
+
+#define IP4SPORTM_EN "ip4m3_sportmen"
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW
+
+#define IP4DPORTM_EN "ip4m3_dportmen"
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V0 "ip6r1v0"
+#define IP6_RUL1_V0_ID 13
+#define IP6_RUL1_V0_OFFSET 0x58400
+#define IP6_RUL1_V0_E_LENGTH 4
+#define IP6_RUL1_V0_E_OFFSET 0x20
+#define IP6_RUL1_V0_NR_E 32
+
+#define IP6_DIPV0 "ip6r1v0_dipv0"
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V1 "ip6r1v1"
+#define IP6_RUL1_V1_ID 13
+#define IP6_RUL1_V1_OFFSET 0x58404
+#define IP6_RUL1_V1_E_LENGTH 4
+#define IP6_RUL1_V1_E_OFFSET 0x20
+#define IP6_RUL1_V1_NR_E 32
+
+#define IP6_DIPV1 "ip6r1v1_dipv1"
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW
+
+
+
+#define IP6_RUL1_V2 "ip6r1v2"
+#define IP6_RUL1_V2_ID 13
+#define IP6_RUL1_V2_OFFSET 0x58408
+#define IP6_RUL1_V2_E_LENGTH 4
+#define IP6_RUL1_V2_E_OFFSET 0x20
+#define IP6_RUL1_V2_NR_E 32
+
+#define IP6_DIPV2 "ip6r1v2_dipv2"
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V3 "ip6r1v3"
+#define IP6_RUL1_V3_ID 13
+#define IP6_RUL1_V3_OFFSET 0x5840c
+#define IP6_RUL1_V3_E_LENGTH 4
+#define IP6_RUL1_V3_E_OFFSET 0x20
+#define IP6_RUL1_V3_NR_E 32
+
+#define IP6_DIPV3 "ip6r1v3_dipv3"
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V4 "ip6r1v4"
+#define IP6_RUL1_V4_ID 13
+#define IP6_RUL1_V4_OFFSET 0x58410
+#define IP6_RUL1_V4_E_LENGTH 4
+#define IP6_RUL1_V4_E_OFFSET 0x20
+#define IP6_RUL1_V4_NR_E 32
+
+#define IP6_RUL1_INPT "ip6r1v4_inpt"
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET 0
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN 6
+#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL1_M0 "ip6r1m0"
+#define IP6_RUL1_M0_ID 13
+#define IP6_RUL1_M0_OFFSET 0x58c00
+#define IP6_RUL1_M0_E_LENGTH 4
+#define IP6_RUL1_M0_E_OFFSET 0x20
+#define IP6_RUL1_M0_NR_E 32
+
+#define IP6_DIPM0 "ip6r1m0_dipm0"
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_M1 "ip6r1m1"
+#define IP6_RUL1_M1_ID 13
+#define IP6_RUL1_M1_OFFSET 0x58c04
+#define IP6_RUL1_M1_E_LENGTH 4
+#define IP6_RUL1_M1_E_OFFSET 0x20
+#define IP6_RUL1_M1_NR_E 32
+
+#define IP6_DIPM1 "ip6r1m1_dipm1"
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+
+#define IP6_RUL1_M2 "ip6r1m2"
+#define IP6_RUL1_M2_ID 13
+#define IP6_RUL1_M2_OFFSET 0x58c08
+#define IP6_RUL1_M2_E_LENGTH 4
+#define IP6_RUL1_M2_E_OFFSET 0x20
+#define IP6_RUL1_M2_NR_E 32
+
+#define IP6_DIPM2 "ip6r1m2_dipm2"
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_M3 "ip6r1m3"
+#define IP6_RUL1_M3_ID 13
+#define IP6_RUL1_M3_OFFSET 0x58c0c
+#define IP6_RUL1_M3_E_LENGTH 4
+#define IP6_RUL1_M3_E_OFFSET 0x20
+#define IP6_RUL1_M3_NR_E 32
+
+#define IP6_DIPM3 "ip6r1m3_dipm3"
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL2_V0 "ip6r2v0"
+#define IP6_RUL2_V0_ID 13
+#define IP6_RUL2_V0_OFFSET 0x58400
+#define IP6_RUL2_V0_E_LENGTH 4
+#define IP6_RUL2_V0_E_OFFSET 0x20
+#define IP6_RUL2_V0_NR_E 32
+
+#define IP6_SIPV0 "ip6r2v0_sipv0"
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V1 "ip6r2v1"
+#define IP6_RUL2_V1_ID 13
+#define IP6_RUL2_V1_OFFSET 0x58404
+#define IP6_RUL2_V1_E_LENGTH 4
+#define IP6_RUL2_V1_E_OFFSET 0x20
+#define IP6_RUL2_V1_NR_E 32
+
+#define IP6_SIPV1 "ip6r2v1_sipv1"
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW
+
+
+
+#define IP6_RUL2_V2 "ip6r2v2"
+#define IP6_RUL2_V2_ID 13
+#define IP6_RUL2_V2_OFFSET 0x58408
+#define IP6_RUL2_V2_E_LENGTH 4
+#define IP6_RUL2_V2_E_OFFSET 0x20
+#define IP6_RUL2_V2_NR_E 32
+
+#define IP6_SIPV2 "ip6r2v2_sipv2"
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V3 "ip6r2v3"
+#define IP6_RUL2_V3_ID 13
+#define IP6_RUL2_V3_OFFSET 0x5840c
+#define IP6_RUL2_V3_E_LENGTH 4
+#define IP6_RUL2_V3_E_OFFSET 0x20
+#define IP6_RUL2_V3_NR_E 32
+
+#define IP6_SIPV3 "ip6r2v3_sipv3"
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V4 "ip6r2v4"
+#define IP6_RUL2_V4_ID 13
+#define IP6_RUL2_V4_OFFSET 0x58410
+#define IP6_RUL2_V4_E_LENGTH 4
+#define IP6_RUL2_V4_E_OFFSET 0x20
+#define IP6_RUL2_V4_NR_E 32
+
+#define IP6_RUL2_INPT "ip6r2v4_inptm"
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET 0
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN 6
+#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M0 "ip6r2m0"
+#define IP6_RUL2_M0_ID 13
+#define IP6_RUL2_M0_OFFSET 0x58c00
+#define IP6_RUL2_M0_E_LENGTH 4
+#define IP6_RUL2_M0_E_OFFSET 0x20
+#define IP6_RUL2_M0_NR_E 32
+
+#define IP6_SIPM0 "ip6r2m0_sipm0"
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M1 "ip6r2m1"
+#define IP6_RUL2_M1_ID 13
+#define IP6_RUL2_M1_OFFSET 0x58c04
+#define IP6_RUL2_M1_E_LENGTH 4
+#define IP6_RUL2_M1_E_OFFSET 0x20
+#define IP6_RUL2_M1_NR_E 32
+
+#define IP6_SIPM1 "ip6r2m1_sipm1"
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+
+#define IP6_RUL2_M2 "ip6r2m2"
+#define IP6_RUL2_M2_ID 13
+#define IP6_RUL2_M2_OFFSET 0x58c08
+#define IP6_RUL2_M2_E_LENGTH 4
+#define IP6_RUL2_M2_E_OFFSET 0x20
+#define IP6_RUL2_M2_NR_E 32
+
+#define IP6_SIPM2 "ip6r2m2_sipm2"
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M3 "ip6r2m3"
+#define IP6_RUL2_M3_ID 13
+#define IP6_RUL2_M3_OFFSET 0x58c0c
+#define IP6_RUL2_M3_E_LENGTH 4
+#define IP6_RUL2_M3_E_OFFSET 0x20
+#define IP6_RUL2_M3_NR_E 32
+
+#define IP6_SIPM3 "ip6r2m3_sipm3"
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL3_V0 "ip6r3v0"
+#define IP6_RUL3_V0_ID 13
+#define IP6_RUL3_V0_OFFSET 0x58400
+#define IP6_RUL3_V0_E_LENGTH 4
+#define IP6_RUL3_V0_E_OFFSET 0x20
+#define IP6_RUL3_V0_NR_E 32
+
+#define IP6PROTV "ip6r3v0_protv"
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0
+#define IP6_RUL3_V0_IP6PROTV_BLEN 8
+#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW
+
+#define IP6DSCPV "ip6r3v0_dscpv"
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN 8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW
+
+#define IP6DPORTV "ip6r3v0_dportv"
+#define IP6_RUL3_V0_IP6DPORTV_BOFFSET 16
+#define IP6_RUL3_V0_IP6DPORTV_BLEN 16
+#define IP6_RUL3_V0_IP6DPORTV_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V1 "ip6r3v1"
+#define IP6_RUL3_V1_ID 13
+#define IP6_RUL3_V1_OFFSET 0x58404
+#define IP6_RUL3_V1_E_LENGTH 4
+#define IP6_RUL3_V1_E_OFFSET 0x20
+#define IP6_RUL3_V1_NR_E 32
+
+#define IP6SPORTV "ip6r3v1_sportv"
+#define IP6_RUL3_V1_IP6SPORTV_BOFFSET 0
+#define IP6_RUL3_V1_IP6SPORTV_BLEN 16
+#define IP6_RUL3_V1_IP6SPORTV_FLAG HSL_RW
+
+#define IP6LABEL1V "ip6r3v1_label1v"
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V2 "ip6r3v2"
+#define IP6_RUL3_V2_ID 13
+#define IP6_RUL3_V2_OFFSET 0x58408
+#define IP6_RUL3_V2_E_LENGTH 4
+#define IP6_RUL3_V2_E_OFFSET 0x20
+#define IP6_RUL3_V2_NR_E 32
+
+#define IP6LABEL2V "ip6r3v2_label2v"
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V4 "ip6r3v4"
+#define IP6_RUL3_V4_ID 13
+#define IP6_RUL3_V4_OFFSET 0x58410
+#define IP6_RUL3_V4_E_LENGTH 4
+#define IP6_RUL3_V4_E_OFFSET 0x20
+#define IP6_RUL3_V4_NR_E 32
+
+#define IP6_RUL3_INPT "ip6r3v4_inpt"
+#define IP6_RUL3_V4_IP6_RUL3_INPT_BOFFSET 0
+#define IP6_RUL3_V4_IP6_RUL3_INPT_BLEN 6
+#define IP6_RUL3_V4_IP6_RUL3_INPT_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M0 "ip6r3m0"
+#define IP6_RUL3_M0_ID 13
+#define IP6_RUL3_M0_OFFSET 0x58c00
+#define IP6_RUL3_M0_E_LENGTH 4
+#define IP6_RUL3_M0_E_OFFSET 0x20
+#define IP6_RUL3_M0_NR_E 32
+
+#define IP6PROTM "ip6r3m0_protm"
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0
+#define IP6_RUL3_M0_IP6PROTM_BLEN 8
+#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW
+
+#define IP6DSCPM "ip6r3m0_dscpm"
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN 8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW
+
+#define IP6DPORTM "ip6r3m0_dportm"
+#define IP6_RUL3_M0_IP6DPORTM_BOFFSET 16
+#define IP6_RUL3_M0_IP6DPORTM_BLEN 16
+#define IP6_RUL3_M0_IP6DPORTM_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M1 "ip6r3m1"
+#define IP6_RUL3_M1_ID 13
+#define IP6_RUL3_M1_OFFSET 0x58c04
+#define IP6_RUL3_M1_E_LENGTH 4
+#define IP6_RUL3_M1_E_OFFSET 0x20
+#define IP6_RUL3_M1_NR_E 32
+
+#define IP6SPORTM "ip6r3m1_sportm"
+#define IP6_RUL3_M1_IP6SPORTM_BOFFSET 0
+#define IP6_RUL3_M1_IP6SPORTM_BLEN 16
+#define IP6_RUL3_M1_IP6SPORTM_FLAG HSL_RW
+
+#define IP6LABEL1M "ip6r3m1_label1m"
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M2 "ip6r3m2"
+#define IP6_RUL3_M2_ID 13
+#define IP6_RUL3_M2_OFFSET 0x58c08
+#define IP6_RUL3_M2_E_LENGTH 4
+#define IP6_RUL3_M2_E_OFFSET 0x20
+#define IP6_RUL3_M2_NR_E 32
+
+#define IP6LABEL2M "ip6r3m2_label2m"
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M3 "ip6r3m3"
+#define IP6_RUL3_M3_ID 13
+#define IP6_RUL3_M3_OFFSET 0x58c0c
+#define IP6_RUL3_M3_E_LENGTH 4
+#define IP6_RUL3_M3_E_OFFSET 0x20
+#define IP6_RUL3_M3_NR_E 32
+
+
+#define IP6DPORTM_EN "ip6r3m3_dportmen"
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 25
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM_EN "ip6r3m3_sportmen"
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 24
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_REG_H_ */
+
diff --git a/include/hsl/garuda/garuda_reg_access.h b/include/hsl/garuda/garuda_reg_access.h
new file mode 100644
index 0000000..5e733a0
--- /dev/null
+++ b/include/hsl/garuda/garuda_reg_access.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _GARUDA_REG_ACCESS_H_
+#define _GARUDA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_REG_ACCESS_H_ */
+
diff --git a/include/hsl/garuda/garuda_stp.h b/include/hsl/garuda/garuda_stp.h
new file mode 100644
index 0000000..9c249cd
--- /dev/null
+++ b/include/hsl/garuda/garuda_stp.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_stp GARUDA_STP
+ * @{
+ */
+#ifndef _GARUDA_STP_H_
+#define _GARUDA_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+ sw_error_t garuda_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define GARUDA_STP_INIT(rv, dev_id) \
+ { \
+ rv = garuda_stp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _GARUDA_STP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/garuda/garuda_vlan.h b/include/hsl/garuda/garuda_vlan.h
new file mode 100644
index 0000000..002ad02
--- /dev/null
+++ b/include/hsl/garuda/garuda_vlan.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_vlan GARUDA_VLAN
+ * @{
+ */
+#ifndef _GARUDA_VLAN_H_
+#define _GARUDA_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ garuda_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define GARUDA_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = garuda_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define GARUDA_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+
+ HSL_LOCAL sw_error_t
+ garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _GARUDA_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_api.h b/include/hsl/horus/horus_api.h
new file mode 100644
index 0000000..0aebcea
--- /dev/null
+++ b/include/hsl/horus/horus_api.h
@@ -0,0 +1,550 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HORUS_API_H_
+#define _HORUS_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, horus_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, horus_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, horus_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, horus_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, horus_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, horus_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, horus_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, horus_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, horus_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_HDR_SET, horus_port_hdr_status_set), \
+ SW_API_DEF(SW_API_PT_HDR_GET, horus_port_hdr_status_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, horus_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, horus_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, horus_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, horus_port_flowctrl_forcemode_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, horus_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, horus_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, horus_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, horus_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, horus_port_cdt),
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_HDR_SET) \
+ SW_API_DESC(SW_API_PT_HDR_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, horus_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, horus_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_MEM_UPDATE, horus_vlan_member_update), \
+ SW_API_DEF(SW_API_VLAN_FIND, horus_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, horus_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, horus_vlan_entry_append),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, horus_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, horus_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, horus_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, horus_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, horus_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, horus_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, horus_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, horus_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_DEF_VID_SET, horus_port_default_vid_set), \
+ SW_API_DEF(SW_API_PT_DEF_VID_GET, horus_port_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, horus_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, horus_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, horus_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, horus_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, horus_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, horus_nestvlan_tpid_get), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, horus_port_invlan_mode_set), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, horus_port_invlan_mode_get), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, horus_port_pri_propagation_set), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, horus_port_pri_propagation_get), \
+ SW_API_DEF(SW_API_QINQ_MODE_SET, horus_qinq_mode_set), \
+ SW_API_DEF(SW_API_QINQ_MODE_GET, horus_qinq_mode_get), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, horus_port_qinq_role_set), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, horus_port_qinq_role_get),
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_QINQ_MODE_SET) \
+ SW_API_DESC(SW_API_QINQ_MODE_GET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, horus_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, horus_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,horus_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, horus_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIRST, horus_fdb_first), \
+ SW_API_DEF(SW_API_FDB_NEXT, horus_fdb_next), \
+ SW_API_DEF(SW_API_FDB_FIND, horus_fdb_find), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, horus_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, horus_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, horus_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, horus_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, horus_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, horus_fdb_age_time_get),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIRST) \
+ SW_API_DESC(SW_API_FDB_NEXT) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, horus_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, horus_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, horus_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, horus_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, horus_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, horus_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, horus_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, horus_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, horus_qos_port_rx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, horus_qos_port_rx_buf_nr_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_SET, horus_cosmap_up_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_GET, horus_cosmap_up_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, horus_cosmap_dscp_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, horus_cosmap_dscp_queue_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, horus_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, horus_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, horus_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, horus_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, horus_qos_port_default_up_set), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, horus_qos_port_default_up_get), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, horus_qos_port_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, horus_qos_port_sch_mode_get),
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, horus_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, horus_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, horus_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, horus_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, horus_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, horus_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, horus_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, horus_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, horus_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, horus_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, horus_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, horus_igmp_mld_entry_creat_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, horus_igmp_mld_entry_static_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, horus_igmp_mld_entry_static_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, horus_igmp_mld_entry_leaky_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, horus_igmp_mld_entry_leaky_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, horus_igmp_mld_entry_v3_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, horus_igmp_mld_entry_v3_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, horus_igmp_mld_entry_queue_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, horus_igmp_mld_entry_queue_get), \
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, horus_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, horus_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, horus_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, horus_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, horus_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, horus_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, horus_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, horus_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, horus_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, horus_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, horus_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, horus_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, horus_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, horus_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, horus_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, horus_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_SET, horus_rate_port_egrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_GET, horus_rate_port_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_SET, horus_rate_port_inrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_GET, horus_rate_port_inrl_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, horus_storm_ctrl_frame_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, horus_storm_ctrl_frame_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, horus_storm_ctrl_rate_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, horus_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, horus_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, horus_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, horus_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, horus_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, horus_mib_status_get),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_ARP_STATUS_SET, horus_arp_status_set), \
+ SW_API_DEF(SW_API_ARP_STATUS_GET, horus_arp_status_get), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, horus_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, horus_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, horus_port_unk_sa_cmd_set), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, horus_port_unk_sa_cmd_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, horus_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, horus_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, horus_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, horus_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_SET, horus_port_bc_filter_set), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_GET, horus_port_bc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, horus_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, horus_cpu_port_status_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, horus_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, horus_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, horus_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, horus_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, horus_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, horus_port_dhcp_get), \
+ SW_API_DEF(SW_API_ARP_CMD_SET, horus_arp_cmd_set), \
+ SW_API_DEF(SW_API_ARP_CMD_GET, horus_arp_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_CMD_SET, horus_eapol_cmd_set), \
+ SW_API_DEF(SW_API_EAPOL_CMD_GET, horus_eapol_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_SET, horus_eapol_status_set), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_GET, horus_eapol_status_get), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_SET, horus_ripv1_status_set), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_GET, horus_ripv1_status_get),
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_ARP_STATUS_SET) \
+ SW_API_DESC(SW_API_ARP_STATUS_GET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET) \
+ SW_API_DESC(SW_API_ARP_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, horus_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, horus_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, horus_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, horus_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, horus_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, horus_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, horus_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, horus_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, horus_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ LED_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_API_H_ */
diff --git a/include/hsl/horus/horus_fdb.h b/include/hsl/horus/horus_fdb.h
new file mode 100644
index 0000000..02be25b
--- /dev/null
+++ b/include/hsl/horus/horus_fdb.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_fdb HORUS_FDB
+ * @{
+ */
+#ifndef _HORUS_FDB_H_
+#define _HORUS_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t
+ horus_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define HORUS_FDB_INIT(rv, dev_id) \
+ { \
+ rv = horus_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_del_by_mac(a_uint32_t dev_id,
+ const fal_fdb_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+ HSL_LOCAL sw_error_t
+ horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_igmp.h b/include/hsl/horus/horus_igmp.h
new file mode 100644
index 0000000..7277300
--- /dev/null
+++ b/include/hsl/horus/horus_igmp.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_igmp HORUS_IGMP
+ * @{
+ */
+#ifndef _HORUS_IGMP_H_
+#define _HORUS_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+ sw_error_t
+ horus_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define HORUS_IGMP_INIT(rv, dev_id) \
+ { \
+ rv = horus_igmp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_init.h b/include/hsl/horus/horus_init.h
new file mode 100644
index 0000000..b28a897
--- /dev/null
+++ b/include/hsl/horus/horus_init.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_init HORUS_INIT
+ * @{
+ */
+#ifndef _HORUS_INIT_H_
+#define _HORUS_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+ sw_error_t
+ horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+ sw_error_t
+ horus_reset(a_uint32_t dev_id);
+
+
+ sw_error_t
+ horus_cleanup(a_uint32_t dev_id);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_leaky.h b/include/hsl/horus/horus_leaky.h
new file mode 100644
index 0000000..e081ee3
--- /dev/null
+++ b/include/hsl/horus/horus_leaky.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_leaky HORUS_LEAKY
+ * @{
+ */
+#ifndef _HORUS_LEAKY_H_
+#define _HORUS_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+ sw_error_t horus_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define HORUS_LEAKY_INIT(rv, dev_id) \
+ { \
+ rv = horus_leaky_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_led.h b/include/hsl/horus/horus_led.h
new file mode 100644
index 0000000..c335321
--- /dev/null
+++ b/include/hsl/horus/horus_led.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _HORUS_LED_H_
+#define _HORUS_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+ sw_error_t
+ horus_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define HORUS_LED_INIT(rv, dev_id) \
+ { \
+ rv = horus_led_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+ HSL_LOCAL sw_error_t
+ horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_LED_H_ */
diff --git a/include/hsl/horus/horus_mib.h b/include/hsl/horus/horus_mib.h
new file mode 100644
index 0000000..d307a75
--- /dev/null
+++ b/include/hsl/horus/horus_mib.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_mib HORUS_MIB
+ * @{
+ */
+#ifndef _HORUS_MIB_H_
+#define _HORUS_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ horus_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define HORUS_MIB_INIT(rv, dev_id) \
+ { \
+ rv = horus_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+ HSL_LOCAL sw_error_t
+ horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_mirror.h b/include/hsl/horus/horus_mirror.h
new file mode 100644
index 0000000..5fff8c2
--- /dev/null
+++ b/include/hsl/horus/horus_mirror.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_mirror HORUS_MIRROR
+ * @{
+ */
+#ifndef _HORUS_MIRROR_H_
+#define _HORUS_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+ sw_error_t horus_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define HORUS_MIRR_INIT(rv, dev_id) \
+ { \
+ rv = horus_mirr_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_misc.h b/include/hsl/horus/horus_misc.h
new file mode 100644
index 0000000..3e4ece8
--- /dev/null
+++ b/include/hsl/horus/horus_misc.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_misc HORUS_MISC
+ * @{
+ */
+#ifndef _HORUS_MISC_H_
+#define _HORUS_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+ sw_error_t horus_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define HORUS_MISC_INIT(rv, dev_id) \
+ { \
+ rv = horus_misc_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+ HSL_LOCAL sw_error_t
+ horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_GEN_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_port_ctrl.h b/include/hsl/horus/horus_port_ctrl.h
new file mode 100644
index 0000000..9731ced
--- /dev/null
+++ b/include/hsl/horus/horus_port_ctrl.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_port_ctrl HORUS_PORT_CONTROL
+ * @{
+ */
+#ifndef _HORUS_PORT_CTRL_H_
+#define _HORUS_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t horus_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define HORUS_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = horus_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_portvlan.h b/include/hsl/horus/horus_portvlan.h
new file mode 100644
index 0000000..4c816ba
--- /dev/null
+++ b/include/hsl/horus/horus_portvlan.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup horus_port_vlan HORUS_PORT_VLAN
+ * @{
+ */
+#ifndef _HORUS_PORTVLAN_H_
+#define _HORUS_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t horus_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define HORUS_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = horus_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+ HSL_LOCAL sw_error_t
+ horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid);
+
+ HSL_LOCAL sw_error_t
+ horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid);
+
+ HSL_LOCAL sw_error_t
+ horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+ HSL_LOCAL sw_error_t
+ horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+ HSL_LOCAL sw_error_t
+ horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ATHENA_PORTVLAN_H */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_qos.h b/include/hsl/horus/horus_qos.h
new file mode 100644
index 0000000..132f9e1
--- /dev/null
+++ b/include/hsl/horus/horus_qos.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_qos HORUS_QOS
+ * @{
+ */
+#ifndef _HORUS_QOS_H_
+#define _HORUS_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+ sw_error_t horus_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define HORUS_QOS_INIT(rv, dev_id) \
+ { \
+ rv = horus_qos_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+ HSL_LOCAL sw_error_t
+ horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_rate.h b/include/hsl/horus/horus_rate.h
new file mode 100644
index 0000000..cabfc5e
--- /dev/null
+++ b/include/hsl/horus/horus_rate.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_rate HORUS_RATE
+ * @{
+ */
+#ifndef _HORUS_RATE_H_
+#define _HORUS_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+ sw_error_t horus_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define HORUS_RATE_INIT(rv, dev_id) \
+ { \
+ rv = horus_rate_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+
+
+ HSL_LOCAL sw_error_t
+ horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_reg.h b/include/hsl/horus/horus_reg.h
new file mode 100644
index 0000000..1ce9c72
--- /dev/null
+++ b/include/hsl/horus/horus_reg.h
@@ -0,0 +1,2422 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HORUS_REG_H_
+#define _HORUS_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+ /* Garuda Mask Control Register */
+#define MASK_CTL "mask"
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 1
+
+#define SOFT_RST "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define MII_CLK5_SEL "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21
+#define MASK_CTL_MII_CLK5_SEL_BLEN 1
+#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW
+
+#define MII_CLK0_SEL "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20
+#define MASK_CTL_MII_CLK0_SEL_BLEN 1
+#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW
+
+#define LOAD_EEPROM "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+
+ /* Garuda Mask Control Register */
+#define POSTRIP "postrip"
+#define POSTRIP_ID 0
+#define POSTRIP_OFFSET 0x0008
+#define POSTRIP_E_LENGTH 4
+#define POSTRIP_E_OFFSET 0
+#define POSTRIP_NR_E 1
+
+#define POWER_ON_SEL "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET 31
+#define POSTRIP_POWER_ON_SEL_BLEN 1
+#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW
+
+#define RXDELAY_S1 "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET 26
+#define POSTRIP_RXDELAY_S1_BLEN 1
+#define POSTRIP_RXDELAY_S1_FLAG HSL_RW
+
+#define SPI_EN "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET 25
+#define POSTRIP_SPI_EN_BLEN 1
+#define POSTRIP_SPI_EN_FLAG HSL_RW
+
+#define LED_OPEN_EN "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET 24
+#define POSTRIP_LED_OPEN_EN_BLEN 1
+#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW
+
+#define RXDELAY_S0 "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET 23
+#define POSTRIP_RXDELAY_S0_BLEN 1
+#define POSTRIP_RXDELAY_S0_FLAG HSL_RW
+
+#define TXDELAY_S1 "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET 22
+#define POSTRIP_TXDELAY_S1_BLEN 1
+#define POSTRIP_TXDELAY_S1_FLAG HSL_RW
+
+#define TXDELAY_S0 "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET 21
+#define POSTRIP_TXDELAY_S0_BLEN 1
+#define POSTRIP_TXDELAY_S0_FLAG HSL_RW
+
+#define LPW_EXIT "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET 20
+#define POSTRIP_LPW_EXIT_BLEN 1
+#define POSTRIP_LPW_EXIT_FLAG HSL_RW
+
+#define PHY_PLL_ON "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET 19
+#define POSTRIP_PHY_PLL_ON_BLEN 1
+#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW
+
+#define MAN_ENABLE "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET 18
+#define POSTRIP_MAN_ENABLE_BLEN 1
+#define POSTRIP_MAN_ENABLE_FLAG HSL_RW
+
+#define LPW_STATE_EN "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET 17
+#define POSTRIP_LPW_STATE_EN_BLEN 1
+#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW
+
+#define POWER_DOWN_HW "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET 16
+#define POSTRIP_POWER_DOWN_HW_BLEN 1
+#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW
+
+#define MAC5_PHY_MODE "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15
+#define POSTRIP_MAC5_PHY_MODE_BLEN 1
+#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW
+
+#define MAC5_MAC_MODE "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14
+#define POSTRIP_MAC5_MAC_MODE_BLEN 1
+#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW
+
+#define DBG_MODE_I "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET 13
+#define POSTRIP_DBG_MODE_I_BLEN 1
+#define POSTRIP_DBG_MODE_I_FLAG HSL_RW
+
+#define HIB_PULSE_HW "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET 12
+#define POSTRIP_HIB_PULSE_HW_BLEN 1
+#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW
+
+#define SEL_CLK25M "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET 11
+#define POSTRIP_SEL_CLK25M_BLEN 1
+#define POSTRIP_SEL_CLK25M_FLAG HSL_RW
+
+#define GATE_25M_EN "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET 10
+#define POSTRIP_GATE_25M_EN_BLEN 1
+#define POSTRIP_GATE_25M_EN_FLAG HSL_RW
+
+#define SEL_ANA_RST "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET 9
+#define POSTRIP_SEL_ANA_RST_BLEN 1
+#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW
+
+#define SERDES_EN "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET 8
+#define POSTRIP_SERDES_EN_BLEN 1
+#define POSTRIP_SERDES_EN_FLAG HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RTL_MODE "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET 5
+#define POSTRIP_RTL_MODE_BLEN 1
+#define POSTRIP_RTL_MODE_FLAG HSL_RW
+
+#define MAC0_MAC_MODE "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4
+#define POSTRIP_MAC0_MAC_MODE_BLEN 1
+#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW
+
+#define PHY4_RGMII_EN "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3
+#define POSTRIP_PHY4_RGMII_EN_BLEN 1
+#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW
+
+#define PHY4_GMII_EN "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET 2
+#define POSTRIP_PHY4_GMII_EN_BLEN 1
+#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_EN "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1
+#define POSTRIP_MAC0_RGMII_EN_BLEN 1
+#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW
+
+#define MAC0_GMII_EN "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET 0
+#define POSTRIP_MAC0_GMII_EN_BLEN 1
+#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW
+
+
+
+ /* Global Interrupt Register */
+#define GLOBAL_INT "gint"
+#define GLOBAL_INT_ID 1
+#define GLOBAL_INT_OFFSET 0x0014
+#define GLOBAL_INT_E_LENGTH 4
+#define GLOBAL_INT_E_OFFSET 0
+#define GLOBAL_INT_NR_E 1
+
+#define GLB_QM_ERR_CNT "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO
+
+#define GLB_LOOKUP_ERR "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLB_QM_ERR "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW
+
+#define GLB_HW_INI_DONE "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW
+
+#define GLB_MIB_INI "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN 1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW
+
+#define GLB_MIB_DONE "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW
+
+#define GLB_BIST_DONE "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW
+
+#define GLB_VT_MISS_VIO "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLB_VT_MEM_VIO "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLB_VT_DONE "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN 1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW
+
+#define GLB_QM_INI "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7
+#define GLOBAL_INT_GLB_QM_INI_BLEN 1
+#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW
+
+#define GLB_AT_INI "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6
+#define GLOBAL_INT_GLB_AT_INI_BLEN 1
+#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW
+
+#define GLB_ARL_FULL "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW
+
+#define GLB_ARL_DONE "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW
+
+#define GLB_MDIO_DONE "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW
+
+#define GLB_PHY_INT "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN 1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW
+
+#define GLB_EEPROM_ERR "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW
+
+#define GLB_EEPROM_INT "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK "gintm"
+#define GLOBAL_INT_MASK_ID 2
+#define GLOBAL_INT_MASK_OFFSET 0x0018
+#define GLOBAL_INT_MASK_E_LENGTH 4
+#define GLOBAL_INT_MASK_E_OFFSET 0
+#define GLOBAL_INT_MASK_NR_E 1
+
+#define GLBM_LOOKUP_ERR "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLBM_QM_ERR "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW
+
+#define GLBM_HW_INI_DONE "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW
+
+#define GLBM_MIB_INI "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW
+
+#define GLBM_MIB_DONE "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW
+
+#define GLBM_BIST_DONE "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW
+
+#define GLBM_VT_MISS_VIO "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLBM_VT_MEM_VIO "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLBM_VT_DONE "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW
+
+#define GLBM_QM_INI "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW
+
+#define GLBM_AT_INI "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW
+
+#define GLBM_ARL_FULL "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW
+
+#define GLBM_ARL_DONE "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW
+
+#define GLBM_MDIO_DONE "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW
+
+#define GLBM_PHY_INT "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW
+
+#define GLBM_EEPROM_ERR "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW
+
+#define GLBM_EEPROM_INT "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0 "gmac0"
+#define GLOBAL_MAC_ADDR0_ID 3
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 1
+
+#define GLB_BYTE4 "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5 "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+#define GLOBAL_MAC_ADDR1 "gmac1"
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 1
+
+#define GLB_BYTE0 "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1 "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2 "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3 "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+
+ /* Flood Mask Register */
+#define FLOOD_MASK "fmask"
+#define FLOOD_MASK_ID 5
+#define FLOOD_MASK_OFFSET 0x002c
+#define FLOOD_MASK_E_LENGTH 4
+#define FLOOD_MASK_E_OFFSET 0
+#define FLOOD_MASK_NR_E 1
+
+#define BC_FLOOD_DP "fmask_bfdp"
+#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET 25
+#define FLOOD_MASK_BC_FLOOD_DP_BLEN 6
+#define FLOOD_MASK_BC_FLOOD_DP_FLAG HSL_RW
+
+#define ARL_UNI_LEAKY "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW
+
+#define ARL_MUL_LEAKY "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 23
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW
+
+#define MUL_FLOOD_DP "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 6
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW
+
+#define IGMP_DP "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET 8
+#define FLOOD_MASK_IGMP_DP_BLEN 6
+#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW
+
+#define UNI_FLOOD_DP "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 6
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW
+
+
+ /* Global Control Register */
+#define GLOBAL_CTL "gctl"
+#define GLOBAL_CTL_ID 5
+#define GLOBAL_CTL_OFFSET 0x0030
+#define GLOBAL_CTL_E_LENGTH 4
+#define GLOBAL_CTL_E_OFFSET 0
+#define GLOBAL_CTL_NR_E 1
+
+#define RATE_DROP_EN "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 29
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW
+
+#define QM_PRI_MODE "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 28
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW
+
+#define RATE_CRE_LIMIT "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW
+
+#define RATE_TIME_SLOT "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW
+
+#define RELOAD_TIMER "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW
+
+#define QM_CNT_LOCK "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO
+
+#define BROAD_DROP_EN "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW
+
+#define MAX_FRAME_SIZE "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW
+
+
+ /* Flow Control Register */
+#define FLOW_CTL0 "fctl"
+#define FLOW_CTL0_ID 6
+#define FLOW_CTL0_OFFSET 0x0034
+#define FLOW_CTL0_E_LENGTH 4
+#define FLOW_CTL0_E_OFFSET 0
+#define FLOW_CTL0_NR_E 1
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL0_TEST_PAUSE_BLEN 1
+#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Flow Control1 Register */
+#define FLOW_CTL1 "fctl1"
+#define FLOW_CTL1_ID 6
+#define FLOW_CTL1_OFFSET 0x0038
+#define FLOW_CTL1_E_LENGTH 4
+#define FLOW_CTL1_E_OFFSET 0
+#define FLOW_CTL1_NR_E 1
+
+#define PORT_PAUSE_ON_THRES "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* QM Control Register */
+#define QM_CTL "qmct"
+#define QM_CTL_ID 7
+#define QM_CTL_OFFSET 0x003c
+#define QM_CTL_E_LENGTH 4
+#define QM_CTL_E_OFFSET 0
+#define QM_CTL_NR_E 1
+
+#define QM_ERR_RST_EN "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31
+#define QM_CTL_QM_ERR_RST_EN_BLEN 1
+#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW
+
+#define LOOKUP_ERR_RST_EN "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_STATIC "qmct_igmpjs"
+#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET 24
+#define QM_CTL_IGMP_JOIN_STATIC_BLEN 4
+#define QM_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW
+
+#define IGMP_JOIN_LEAKY "qmct_igmpjl"
+#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET 23
+#define QM_CTL_IGMP_JOIN_LEAKY_BLEN 1
+#define QM_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW
+
+#define IGMP_CREAT_EN "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22
+#define QM_CTL_IGMP_CREAT_EN_BLEN 1
+#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW
+
+#define PPPOE_RDT_EN "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20
+#define QM_CTL_PPPOE_RDT_EN_BLEN 1
+#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW
+
+#define IGMP_V3_EN "qmct_igmpv3e"
+#define QM_CTL_IGMP_V3_EN_BOFFSET 19
+#define QM_CTL_IGMP_V3_EN_BLEN 1
+#define QM_CTL_IGMP_V3_EN_FLAG HSL_RW
+
+#define IGMP_PRI_EN "qmct_igmpprie"
+#define QM_CTL_IGMP_PRI_EN_BOFFSET 18
+#define QM_CTL_IGMP_PRI_EN_BLEN 1
+#define QM_CTL_IGMP_PRI_EN_FLAG HSL_RW
+
+#define IGMP_PRI "qmct_igmppri"
+#define QM_CTL_IGMP_PRI_BOFFSET 16
+#define QM_CTL_IGMP_PRI_BLEN 2
+#define QM_CTL_IGMP_PRI_FLAG HSL_RW
+
+#define ARP_EN "qmct_arpe"
+#define QM_CTL_ARP_EN_BOFFSET 15
+#define QM_CTL_ARP_EN_BLEN 1
+#define QM_CTL_ARP_EN_FLAG HSL_RW
+
+#define ARP_CMD "qmct_arpc"
+#define QM_CTL_ARP_CMD_BOFFSET 14
+#define QM_CTL_ARP_CMD_BLEN 1
+#define QM_CTL_ARP_CMD_FLAG HSL_RW
+
+#define RIP_CPY_EN "qmct_ripcpyen"
+#define QM_CTL_RIP_CPY_EN_BOFFSET 13
+#define QM_CTL_RIP_CPY_EN_BLEN 1
+#define QM_CTL_RIP_CPY_EN_FLAG HSL_RW
+
+#define EAPOL_CMD "qmct_eapolc"
+#define QM_CTL_EAPOL_CMD_BOFFSET 12
+#define QM_CTL_EAPOL_CMD_BLEN 1
+#define QM_CTL_EAPOL_CMD_FLAG HSL_RW
+
+#define IGMP_COPY_EN "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET 11
+#define QM_CTL_IGMP_COPY_EN_BLEN 1
+#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW
+
+#define PPPOE_EN "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET 10
+#define QM_CTL_PPPOE_EN_BLEN 1
+#define QM_CTL_PPPOE_EN_FLAG HSL_RW
+
+#define QM_FUNC_TEST "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET 9
+#define QM_CTL_QM_FUNC_TEST_BLEN 1
+#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW
+
+#define MS_FC_EN "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET 8
+#define QM_CTL_MS_FC_EN_BLEN 1
+#define QM_CTL_MS_FC_EN_FLAG HSL_RW
+
+#define FLOW_DROP_EN "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET 7
+#define QM_CTL_FLOW_DROP_EN_BLEN 1
+#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_CNT "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTL_FLOW_DROP_CNT_BLEN 6
+#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW
+
+
+ /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0 "vtbf0"
+#define VLAN_TABLE_FUNC0_ID 9
+#define VLAN_TABLE_FUNC0_OFFSET 0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 1
+
+#define VT_PRI_EN "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+#define VLAN_ID "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_BUSY "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW
+
+#define VT_FUNC "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW
+
+#define VLAN_TABLE_FUNC1 "vtbf1"
+#define VLAN_TABLE_FUNC1_ID 10
+#define VLAN_TABLE_FUNC1_OFFSET 0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 1
+
+#define VT_VALID "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW
+
+#define LEARN_DIS "vtbf_ldis"
+#define VLAN_TABLE_FUNC1_LEARN_DIS_BOFFSET 10
+#define VLAN_TABLE_FUNC1_LEARN_DIS_BLEN 1
+#define VLAN_TABLE_FUNC1_LEARN_DIS_FLAG HSL_RW
+
+#define VID_MEM "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 6
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW
+
+
+ /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0 "atbf0"
+#define ADDR_TABLE_FUNC0_ID 11
+#define ADDR_TABLE_FUNC0_OFFSET 0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 1
+
+#define AT_ADDR_BYTE4 "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5 "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+#define AT_FULL_VIO "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW
+
+#define FLUSH_ST_EN "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW
+
+#define AT_BUSY "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW
+
+#define AT_FUNC "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC1 "atbf1"
+#define ADDR_TABLE_FUNC1_ID 12
+#define ADDR_TABLE_FUNC1_OFFSET 0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 0
+
+#define AT_ADDR_BYTE0 "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1 "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+#define AT_ADDR_BYTE2 "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3 "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC2 "atbf2"
+#define ADDR_TABLE_FUNC2_ID 13
+#define ADDR_TABLE_FUNC2_OFFSET 0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 0
+
+#define COPY_TO_CPU "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define LEAKY_EN "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW
+
+#define AT_STATUS "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+#define CLONE_EN "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW
+
+#define SA_DROP_EN "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW
+
+#define MIRROR_EN "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_PRI "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW
+
+#define CROSS_PT "atbf_cpt"
+#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET 8
+#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN 1
+#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG HSL_RW
+
+#define DES_PORT "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 6
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW
+
+
+ /* Address Table Control Register */
+#define ADDR_TABLE_CTL "atbc"
+#define ADDR_TABLE_CTL_ID 14
+#define ADDR_TABLE_CTL_OFFSET 0x005C
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 1
+
+#define LOOP_CH_TIME "atbc_lct"
+#define ADDR_TABLE_CTL_LOOP_CH_TIME_BOFFSET 24
+#define ADDR_TABLE_CTL_LOOP_CH_TIMEP_BLEN 3
+#define ADDR_TABLE_CTL_LOOP_CH_TIME_FLAG HSL_RW
+
+#define RESVID_DROP "atbc_rviddrop"
+#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET 22
+#define ADDR_TABLE_CTL_RESVID_DROP_BLEN 1
+#define ADDR_TABLE_CTL_RESVID_DROP_FLAG HSL_RW
+
+#define STAG_MODE "atbc_stag"
+#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET 21
+#define ADDR_TABLE_CTL_STAG_MODE_BLEN 1
+#define ADDR_TABLE_CTL_STAG_MODE_FLAG HSL_RW
+
+#define ARL_INI_EN "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define LEARN_CHANGE_EN "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW
+
+#define AGE_EN "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define AGE_TIME "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING "imap"
+#define IP_PRI_MAPPING_ID 15
+#define IP_PRI_MAPPING_OFFSET 0x0060
+#define IP_PRI_MAPPING_E_LENGTH 4
+#define IP_PRI_MAPPING_E_OFFSET 0
+#define IP_PRI_MAPPING_NR_E 1
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0 "imap0"
+#define IP_PRI_MAPPING0_ID 15
+#define IP_PRI_MAPPING0_OFFSET 0x0060
+#define IP_PRI_MAPPING0_E_LENGTH 4
+#define IP_PRI_MAPPING0_E_OFFSET 0
+#define IP_PRI_MAPPING0_NR_E 0
+
+#define IP_0X3C "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW
+
+#define IP_0X38 "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW
+
+#define IP_0X34 "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW
+
+#define IP_0X30 "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW
+
+#define IP_0X2C "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW
+
+#define IP_0X28 "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW
+
+#define IP_0X24 "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW
+
+#define IP_0X20 "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW
+
+#define IP_0X1C "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW
+
+#define IP_0X18 "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW
+
+#define IP_0X14 "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW
+
+#define IP_0X10 "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW
+
+#define IP_0X0C "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW
+
+#define IP_0X08 "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW
+
+#define IP_0X04 "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW
+
+#define IP_0X00 "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW
+
+#define IP_PRI_MAPPING1 "imap1"
+#define IP_PRI_MAPPING1_ID 16
+#define IP_PRI_MAPPING1_OFFSET 0x0064
+#define IP_PRI_MAPPING1_E_LENGTH 4
+#define IP_PRI_MAPPING1_E_OFFSET 0
+#define IP_PRI_MAPPING1_NR_E 0
+
+#define IP_0X7C "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW
+
+#define IP_0X78 "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW
+
+#define IP_0X74 "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW
+
+#define IP_0X70 "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW
+
+#define IP_0X6C "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW
+
+#define IP_0X68 "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW
+
+#define IP_0X64 "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW
+
+#define IP_0X60 "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW
+
+#define IP_0X5C "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW
+
+#define IP_0X58 "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW
+
+#define IP_0X54 "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW
+
+#define IP_0X50 "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW
+
+#define IP_0X4C "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW
+
+#define IP_0X48 "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW
+
+#define IP_0X44 "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW
+
+#define IP_0X40 "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW
+
+
+#define IP_PRI_MAPPING2 "imap2"
+#define IP_PRI_MAPPING2_ID 17
+#define IP_PRI_MAPPING2_OFFSET 0x0068
+#define IP_PRI_MAPPING2_E_LENGTH 4
+#define IP_PRI_MAPPING2_E_OFFSET 0
+#define IP_PRI_MAPPING2_NR_E 0
+
+#define IP_0XBC "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW
+
+#define IP_0XB8 "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW
+
+#define IP_0XB4 "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW
+
+#define IP_0XB0 "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW
+
+#define IP_0XAC "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW
+
+#define IP_0XA8 "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW
+
+#define IP_0XA4 "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW
+
+#define IP_0XA0 "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW
+
+#define IP_0X9C "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW
+
+#define IP_0X98 "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW
+
+#define IP_0X94 "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW
+
+#define IP_0X90 "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW
+
+#define IP_0X8C "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW
+
+#define IP_0X88 "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW
+
+#define IP_0X84 "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW
+
+#define IP_0X80 "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW
+
+#define IP_PRI_MAPPING3 "imap3"
+#define IP_PRI_MAPPING3_ID 18
+#define IP_PRI_MAPPING3_OFFSET 0x006C
+#define IP_PRI_MAPPING3_E_LENGTH 4
+#define IP_PRI_MAPPING3_E_OFFSET 0
+#define IP_PRI_MAPPING3_NR_E 0
+
+#define IP_0XFC "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW
+
+#define IP_0XF8 "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW
+
+#define IP_0XF4 "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW
+
+#define IP_0XF0 "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW
+
+#define IP_0XEC "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW
+
+#define IP_0XE8 "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW
+
+#define IP_0XE4 "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW
+
+#define IP_0XE0 "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW
+
+#define IP_0XDC "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW
+
+#define IP_0XD8 "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW
+
+#define IP_0XD4 "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW
+
+#define IP_0XD0 "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW
+
+#define IP_0XCC "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW
+
+#define IP_0XC8 "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW
+
+#define IP_0XC4 "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW
+
+#define IP_0XC0 "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW
+
+
+ /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING "tpmap"
+#define TAG_PRI_MAPPING_ID 19
+#define TAG_PRI_MAPPING_OFFSET 0x0070
+#define TAG_PRI_MAPPING_E_LENGTH 4
+#define TAG_PRI_MAPPING_E_OFFSET 0
+#define TAG_PRI_MAPPING_NR_E 1
+
+#define TAG_0X07 "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW
+
+#define TAG_0X06 "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW
+
+#define TAG_0X05 "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW
+
+#define TAG_0X04 "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW
+
+#define TAG_0X03 "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW
+
+#define TAG_0X02 "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW
+
+#define TAG_0X01 "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW
+
+#define TAG_0X00 "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW
+
+
+ /* Service tag Register */
+#define SERVICE_TAG "servicetag"
+#define SERVICE_TAG_ID 20
+#define SERVICE_TAG_OFFSET 0x0074
+#define SERVICE_TAG_E_LENGTH 4
+#define SERVICE_TAG_E_OFFSET 0
+#define SERVICE_TAG_NR_E 1
+
+#define TAG_VALUE "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET 0
+#define SERVICE_TAG_TAG_VALUE_BLEN 16
+#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW
+
+
+ /* Cpu Port Register */
+#define CPU_PORT "cpup"
+#define CPU_PORT_ID 20
+#define CPU_PORT_OFFSET 0x0078
+#define CPU_PORT_E_LENGTH 4
+#define CPU_PORT_E_OFFSET 0
+#define CPU_PORT_NR_E 0
+
+#define CPU_PORT_EN "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET 8
+#define CPU_PORT_CPU_PORT_EN_BLEN 1
+#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW
+
+
+ /* MIB Function Register */
+#define MIB_FUNC "mibfunc"
+#define MIB_FUNC_ID 21
+#define MIB_FUNC_OFFSET 0x0080
+#define MIB_FUNC_E_LENGTH 4
+#define MIB_FUNC_E_OFFSET 0
+#define MIB_FUNC_NR_E 1
+
+#define MAC_CRC_EN "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31
+#define MIB_FUNC_MAC_CRC_EN_BLEN 1
+#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW
+
+#define MIB_EN "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET 30
+#define MIB_FUNC_MIB_EN_BLEN 1
+#define MIB_FUNC_MIB_EN_FLAG HSL_RW
+
+#define MIB_FUN "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET 24
+#define MIB_FUNC_MIB_FUN_BLEN 3
+#define MIB_FUNC_MIB_FUN_FLAG HSL_RW
+
+#define MIB_BUSY "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET 17
+#define MIB_FUNC_MIB_BUSY_BLEN 1
+#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET 0
+#define MIB_FUNC_MIB_TIMER_BLEN 16
+#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW
+
+
+ /* Mdio control Register */
+#define MDIO_CTRL "mctrl"
+#define MDIO_CTRL_ID 24
+#define MDIO_CTRL_OFFSET 0x0098
+#define MDIO_CTRL_E_LENGTH 4
+#define MDIO_CTRL_E_OFFSET 0
+#define MDIO_CTRL_NR_E 1
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define CMD "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET 27
+#define MDIO_CTRL_CMD_BLEN 1
+#define MDIO_CTRL_CMD_FLAG HSL_RW
+
+#define SUP_PRE "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET 26
+#define MDIO_CTRL_SUP_PRE_BLEN 1
+#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW
+
+#define PHY_ADDR "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET 21
+#define MDIO_CTRL_PHY_ADDR_BLEN 5
+#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW
+
+#define REG_ADDR "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET 16
+#define MDIO_CTRL_REG_ADDR_BLEN 5
+#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW
+
+#define DATA "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET 0
+#define MDIO_CTRL_DATA_BLEN 16
+#define MDIO_CTRL_DATA_FLAG HSL_RW
+
+
+
+
+ /* BIST control Register */
+#define BIST_CTRL "bctrl"
+#define BIST_CTRL_ID 24
+#define BIST_CTRL_OFFSET 0x00a0
+#define BIST_CTRL_E_LENGTH 4
+#define BIST_CTRL_E_OFFSET 0
+#define BIST_CTRL_NR_E 1
+
+#define BIST_BUSY "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET 31
+#define BIST_CTRL_BIST_BUSY_BLEN 1
+#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW
+
+#define ONE_ERR "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET 30
+#define BIST_CTRL_ONE_ERR_BLEN 1
+#define BIST_CTRL_ONE_ERR_FLAG HSL_RO
+
+#define ERR_MEM "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET 24
+#define BIST_CTRL_ERR_MEM_BLEN 4
+#define BIST_CTRL_ERR_MEM_FLAG HSL_RO
+
+#define PTN_EN2 "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET 22
+#define BIST_CTRL_PTN_EN2_BLEN 1
+#define BIST_CTRL_PTN_EN2_FLAG HSL_RW
+
+#define PTN_EN1 "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET 21
+#define BIST_CTRL_PTN_EN1_BLEN 1
+#define BIST_CTRL_PTN_EN1_FLAG HSL_RW
+
+#define PTN_EN0 "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET 20
+#define BIST_CTRL_PTN_EN0_BLEN 1
+#define BIST_CTRL_PTN_EN0_FLAG HSL_RW
+
+#define ERR_PTN "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET 16
+#define BIST_CTRL_ERR_PTN_BLEN 2
+#define BIST_CTRL_ERR_PTN_FLAG HSL_RO
+
+#define ERR_CNT "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET 13
+#define BIST_CTRL_ERR_CNT_BLEN 2
+#define BIST_CTRL_ERR_CNT_FLAG HSL_RO
+
+#define ERR_ADDR "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET 0
+#define BIST_CTRL_ERR_ADDR_BLEN 12
+#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO
+
+
+
+
+ /* BIST recover Register */
+#define BIST_RCV "brcv"
+#define BIST_RCV_ID 24
+#define BIST_RCV_OFFSET 0x00a4
+#define BIST_RCV_E_LENGTH 4
+#define BIST_RCV_E_OFFSET 0
+#define BIST_RCV_NR_E 1
+
+#define RCV_EN "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET 31
+#define BIST_RCV_RCV_EN_BLEN 1
+#define BIST_RCV_RCV_EN_FLAG HSL_RW
+
+#define RCV_ADDR "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET 0
+#define BIST_RCV_RCV_ADDR_BLEN 12
+#define BIST_RCV_RCV_ADDR_FLAG HSL_RW
+
+
+
+
+ /* LED control Register */
+#define LED_CTRL "ledctrl"
+#define LED_CTRL_ID 25
+#define LED_CTRL_OFFSET 0x00b0
+#define LED_CTRL_E_LENGTH 4
+#define LED_CTRL_E_OFFSET 0
+#define LED_CTRL_NR_E 1
+
+#define PATTERN_EN "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET 14
+#define LED_CTRL_PATTERN_EN_BLEN 2
+#define LED_CTRL_PATTERN_EN_FLAG HSL_RW
+
+#define FULL_LIGHT_EN "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN 1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW
+
+#define HALF_LIGHT_EN "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN 1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW
+
+#define POWERON_LIGHT_EN "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW
+
+#define GE_LIGHT_EN "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10
+#define LED_CTRL_GE_LIGHT_EN_BLEN 1
+#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW
+
+#define FE_LIGHT_EN "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9
+#define LED_CTRL_FE_LIGHT_EN_BLEN 1
+#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW
+
+#define ETH_LIGHT_EN "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN 1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW
+
+#define COL_BLINK_EN "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET 7
+#define LED_CTRL_COL_BLINK_EN_BLEN 1
+#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW
+
+#define RX_BLINK_EN "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET 5
+#define LED_CTRL_RX_BLINK_EN_BLEN 1
+#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW
+
+#define TX_BLINK_EN "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET 4
+#define LED_CTRL_TX_BLINK_EN_BLEN 1
+#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW
+
+#define LINKUP_OVER_EN "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN 1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW
+
+#define BLINK_FREQ "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET 0
+#define LED_CTRL_BLINK_FREQ_BLEN 2
+#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW
+
+ /* LED control Register */
+#define LED_PATTERN "ledpatten"
+#define LED_PATTERN_ID 25
+#define LED_PATTERN_OFFSET 0x00bc
+#define LED_PATTERN_E_LENGTH 4
+#define LED_PATTERN_E_OFFSET 0
+#define LED_PATTERN_NR_E 1
+
+#define P3L1_MODE "p3l1_mode"
+#define LED_PATTERN_P3L1_MODE_BOFFSET 24
+#define LED_PATTERN_P3L1_MODE_BLEN 2
+#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW
+
+#define P3L0_MODE "p3l0_mode"
+#define LED_PATTERN_P3L0_MODE_BOFFSET 22
+#define LED_PATTERN_P3L0_MODE_BLEN 2
+#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW
+
+#define P2L1_MODE "p2l1_mode"
+#define LED_PATTERN_P2L1_MODE_BOFFSET 20
+#define LED_PATTERN_P2L1_MODE_BLEN 2
+#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW
+
+#define P2L0_MODE "p2l0_mode"
+#define LED_PATTERN_P2L0_MODE_BOFFSET 18
+#define LED_PATTERN_P2L0_MODE_BLEN 2
+#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW
+
+#define P1L1_MODE "p1l1_mode"
+#define LED_PATTERN_P1L1_MODE_BOFFSET 16
+#define LED_PATTERN_P1L1_MODE_BLEN 2
+#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW
+
+#define P1L0_MODE "p1l0_mode"
+#define LED_PATTERN_P1L0_MODE_BOFFSET 14
+#define LED_PATTERN_P1L0_MODE_BLEN 2
+#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW
+
+#define M5_MODE "m5_mode"
+#define LED_PATTERN_M5_MODE_BOFFSET 10
+#define LED_PATTERN_M5_MODE_BLEN 2
+#define LED_PATTERN_M5_MODE_FLAG HSL_RW
+
+
+ /* Port Status Register */
+#define PORT_STATUS "ptsts"
+#define PORT_STATUS_ID 29
+#define PORT_STATUS_OFFSET 0x0100
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0100
+#define PORT_STATUS_NR_E 6
+
+#define FLOW_LINK_EN "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN 1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW
+
+
+#define LINK_ASYN_PAUSE "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO
+
+#define LINK_PAUSE "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET 10
+#define PORT_STATUS_LINK_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO
+
+#define LINK_EN "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW
+
+#define DUPLEX_MODE "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+
+ /* Port Control Register */
+#define PORT_CTL "pctl"
+#define PORT_CTL_ID 30
+#define PORT_CTL_OFFSET 0x0104
+#define PORT_CTL_E_LENGTH 4
+#define PORT_CTL_E_OFFSET 0x0100
+#define PORT_CTL_NR_E 6
+
+#define EAPOL_EN "pctl_eapolen"
+#define PORT_CTL_EAPOL_EN_BOFFSET 23
+#define PORT_CTL_EAPOL_EN_BLEN 1
+#define PORT_CTL_EAPOL_EN_FLAG HSL_RW
+
+#define ARP_LEAKY_EN "pbvlan_alen"
+#define PORT_CTL_ARP_LEAKY_EN_BOFFSET 22
+#define PORT_CTL_ARP_LEAKY_EN_BLEN 1
+#define PORT_CTL_ARP_LEAKY_EN_FLAG HSL_RW
+
+#define LEAVE_EN "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET 21
+#define PORT_CTL_LEAVE_EN_BLEN 1
+#define PORT_CTL_LEAVE_EN_FLAG HSL_RW
+
+#define JOIN_EN "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET 20
+#define PORT_CTL_JOIN_EN_BLEN 1
+#define PORT_CTL_JOIN_EN_FLAG HSL_RW
+
+#define DHCP_EN "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET 19
+#define PORT_CTL_DHCP_EN_BLEN 1
+#define PORT_CTL_DHCP_EN_FLAG HSL_RW
+
+#define ING_MIRROR_EN "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17
+#define PORT_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define EG_MIRROR_EN "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16
+#define PORT_CTL_EG_MIRROR_EN_BLEN 1
+#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW
+
+#define LEARN_EN "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET 14
+#define PORT_CTL_LEARN_EN_BLEN 1
+#define PORT_CTL_LEARN_EN_FLAG HSL_RW
+
+#define MAC_LOOP_BACK "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN 1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW
+
+#define HEAD_EN "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET 11
+#define PORT_CTL_HEAD_EN_BLEN 1
+#define PORT_CTL_HEAD_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10
+#define PORT_CTL_IGMP_MLD_EN_BLEN 1
+#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW
+
+#define EG_VLAN_MODE "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8
+#define PORT_CTL_EG_VLAN_MODE_BLEN 2
+#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW
+
+#define LEARN_ONE_LOCK "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW
+
+#define PORT_LOCK_EN "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6
+#define PORT_CTL_PORT_LOCK_EN_BLEN 1
+#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW
+
+#define LOCK_DROP_EN "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5
+#define PORT_CTL_LOCK_DROP_EN_BLEN 1
+#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW
+
+#define PORT_STATE "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET 0
+#define PORT_CTL_PORT_STATE_BLEN 3
+#define PORT_CTL_PORT_STATE_FLAG HSL_RW
+
+
+ /* Port dot1q Register */
+#define PORT_DOT1Q "pdot1Q"
+#define PORT_DOT1Q_ID 31
+#define PORT_DOT1Q_OFFSET 0x0108
+#define PORT_DOT1Q_E_LENGTH 4
+#define PORT_DOT1Q_E_OFFSET 0x0100
+#define PORT_DOT1Q_NR_E 6
+
+#define ING_PRI "pdot1q_ingpri"
+#define PORT_DOT1Q_ING_PRI_BOFFSET 29
+#define PORT_DOT1Q_ING_PRI_BLEN 3
+#define PORT_DOT1Q_ING_PRI_FLAG HSL_RW
+
+#define FORCE_PVLAN "pdot1q_fpvlan"
+#define PORT_DOT1Q_FORCE_PVLAN_BOFFSET 28
+#define PORT_DOT1Q_FORCE_PVLAN_BLEN 1
+#define PORT_DOT1Q_FORCE_PVLAN_FLAG HSL_RW
+
+#define DEF_VID "pdot1q_dcvid"
+#define PORT_DOT1Q_DEF_VID_BOFFSET 16
+#define PORT_DOT1Q_DEF_VID_BLEN 12
+#define PORT_DOT1Q_DEF_VID_FLAG HSL_RW
+
+#define FORCE_DEF_VID "pbot1q_fdvid"
+#define PORT_DOT1Q_FORCE_DEF_VID_BOFFSET 12
+#define PORT_DOT1Q_FORCE_DEF_VID_BLEN 1
+#define PORT_DOT1Q_FORCE_DEF_VID_FLAG HSL_RW
+
+
+ /* Port Based Vlan Register */
+#define PORT_BASE_VLAN "pbvlan"
+#define PORT_BASE_VLAN_ID 31
+#define PORT_BASE_VLAN_OFFSET 0x010c
+#define PORT_BASE_VLAN_E_LENGTH 4
+#define PORT_BASE_VLAN_E_OFFSET 0x0100
+#define PORT_BASE_VLAN_NR_E 6
+
+#define DOT1Q_MODE "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW
+
+#define COREP_EN "pbvlan_corepen"
+#define PORT_BASE_VLAN_COREP_EN_BOFFSET 29
+#define PORT_BASE_VLAN_COREP_EN_BLEN 1
+#define PORT_BASE_VLAN_COREP_EN_FLAG HSL_RW
+
+#define IN_VLAN_MODE "pbvlan_imode"
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET 27
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN 2
+#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG HSL_RW
+
+#define PRI_PROPAGATION "pbvlan_prip"
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET 23
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN 1
+#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define PORT_VID_MEM "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 6
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW
+
+#define UNI_LEAKY_EN "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW
+
+#define MUL_LEAKY_EN "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW
+
+
+ /* Port Rate Limit0 Register */
+#define RATE_LIMIT0 "rlmt0"
+#define RATE_LIMIT0_ID 32
+#define RATE_LIMIT0_OFFSET 0x0110
+#define RATE_LIMIT0_E_LENGTH 4
+#define RATE_LIMIT0_E_OFFSET 0x0100
+#define RATE_LIMIT0_NR_E 6
+
+#define ADD_RATE_BYTE "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define EG_MNG_RATE_EN "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MNG_RATE_EN "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MUL_RATE_EN "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET 0
+#define RATE_LIMIT0_ING_RATE_BLEN 13
+#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW
+
+
+ /* Priority Control Register */
+#define PRI_CTL "prctl"
+#define PRI_CTL_ID 33
+#define PRI_CTL_OFFSET 0x0114
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x0100
+#define PRI_CTL_NR_E 6
+
+#define PORT_PRI_EN "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET 19
+#define PRI_CTL_PORT_PRI_EN_BLEN 1
+#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_EN "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+#define PORT_PRI_SEL "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0
+#define PRI_CTL_PORT_PRI_SEL_BLEN 2
+#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW
+
+
+ /* Storm Control Register */
+#define STORM_CTL "sctrl"
+#define STORM_CTL_ID 33
+#define STORM_CTL_OFFSET 0x0118
+#define STORM_CTL_E_LENGTH 4
+#define STORM_CTL_E_OFFSET 0x0100
+#define STORM_CTL_NR_E 6
+
+#define UNIT "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET 24
+#define STORM_CTL_UNIT_BLEN 2
+#define STORM_CTL_UNIT_FLAG HSL_RW
+
+#define MUL_EN "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET 10
+#define STORM_CTL_MUL_EN_BLEN 1
+#define STORM_CTL_MUL_EN_FLAG HSL_RW
+
+#define UNI_EN "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET 9
+#define STORM_CTL_UNI_EN_BLEN 1
+#define STORM_CTL_UNI_EN_FLAG HSL_RW
+
+#define BRO_EN "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET 8
+#define STORM_CTL_BRO_EN_BLEN 1
+#define STORM_CTL_BRO_EN_FLAG HSL_RW
+
+#define RATE "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET 0
+#define STORM_CTL_RATE_BLEN 4
+#define STORM_CTL_RATE_FLAG HSL_RW
+
+
+ /* Queue Control Register */
+#define QUEUE_CTL "qctl"
+#define QUEUE_CTL_ID 34
+#define QUEUE_CTL_OFFSET 0x011c
+#define QUEUE_CTL_E_LENGTH 4
+#define QUEUE_CTL_E_OFFSET 0x0100
+#define QUEUE_CTL_NR_E 6
+
+#define PORT_IN_DESC_EN "qctl_pdescen"
+#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET 28
+#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN 4
+#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG HSL_RW
+
+#define PORT_DESC_EN "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN 1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW
+
+#define QUEUE_DESC_EN "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW
+
+#define PORT_DESC_NR "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN 6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW
+
+#define QUEUE3_DESC_NR "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW
+
+#define QUEUE2_DESC_NR "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW
+
+#define QUEUE1_DESC_NR "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW
+
+#define QUEUE0_DESC_NR "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW
+
+
+ /* Port Rate Limit1 Register */
+#define RATE_LIMIT1 "rlmt1"
+#define RATE_LIMIT1_ID 32
+#define RATE_LIMIT1_OFFSET 0x0120
+#define RATE_LIMIT1_E_LENGTH 4
+#define RATE_LIMIT1_E_OFFSET 0x0100
+#define RATE_LIMIT1_NR_E 6
+
+#define EG_RATE "rlmt_egrate"
+#define RATE_LIMIT1_EG_RATE_BOFFSET 0
+#define RATE_LIMIT1_EG_RATE_BLEN 13
+#define RATE_LIMIT1_EG_RATE_FLAG HSL_RW
+
+
+ /* Port Rate Limit3 Register */
+#define RATE_LIMIT3 "rlmt3"
+#define RATE_LIMIT3_ID 32
+#define RATE_LIMIT3_OFFSET 0x0128
+#define RATE_LIMIT3_E_LENGTH 4
+#define RATE_LIMIT3_E_OFFSET 0x0100
+#define RATE_LIMIT3_NR_E 6
+
+#define EG_CBS "rlmt_egcbs"
+#define RATE_LIMIT3_EG_CBS_BOFFSET 16
+#define RATE_LIMIT3_EG_CBS_BLEN 2
+#define RATE_LIMIT3_EG_CBS_FLAG HSL_RW
+
+#define EG_TS "rlmt_egts"
+#define RATE_LIMIT3_EG_TS_BOFFSET 0
+#define RATE_LIMIT3_EG_TS_BLEN 3
+#define RATE_LIMIT3_EG_TS_FLAG HSL_RW
+
+
+ /* Weight Round Robin Register */
+#define WRR_CTRL "wrrc"
+#define WRR_CTRL_ID 32
+#define WRR_CTRL_OFFSET 0x012c
+#define WRR_CTRL_E_LENGTH 4
+#define WRR_CTRL_E_OFFSET 0x0100
+#define WRR_CTRL_NR_E 6
+
+#define SCH_MODE "wrrc_mode"
+#define WRR_CTRL_SCH_MODE_BOFFSET 29
+#define WRR_CTRL_SCH_MODE_BLEN 2
+#define WRR_CTRL_SCH_MODE_FLAG HSL_RW
+
+
+ /* mib memory info */
+#define MIB_RXBROAD "RxBroad"
+#define MIB_RXBROAD_ID 34
+#define MIB_RXBROAD_OFFSET 0x20000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0x100
+#define MIB_RXBROAD_NR_E 6
+
+#define MIB_RXPAUSE "RxPause"
+#define MIB_RXPAUSE_ID 35
+#define MIB_RXPAUSE_OFFSET 0x20004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0x100
+#define MIB_RXPAUSE_NR_E 6
+
+#define MIB_RXMULTI "RxMulti"
+#define MIB_RXMULTI_ID 36
+#define MIB_RXMULTI_OFFSET 0x20008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0x100
+#define MIB_RXMULTI_NR_E 6
+
+#define MIB_RXFCSERR "RxFcsErr"
+#define MIB_RXFCSERR_ID 37
+#define MIB_RXFCSERR_OFFSET 0x2000c
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0x100
+#define MIB_RXFCSERR_NR_E 6
+
+#define MIB_RXALLIGNERR "RxAllignErr"
+#define MIB_RXALLIGNERR_ID 38
+#define MIB_RXALLIGNERR_OFFSET 0x20010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0x100
+#define MIB_RXALLIGNERR_NR_E 6
+
+#define MIB_RXRUNT "RxRunt"
+#define MIB_RXRUNT_ID 39
+#define MIB_RXRUNT_OFFSET 0x20014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0x100
+#define MIB_RXRUNT_NR_E 6
+
+#define MIB_RXFRAGMENT "RxFragment"
+#define MIB_RXFRAGMENT_ID 40
+#define MIB_RXFRAGMENT_OFFSET 0x20018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0x100
+#define MIB_RXFRAGMENT_NR_E 6
+
+#define MIB_RX64BYTE "Rx64Byte"
+#define MIB_RX64BYTE_ID 41
+#define MIB_RX64BYTE_OFFSET 0x2001c
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0x100
+#define MIB_RX64BYTE_NR_E 6
+
+#define MIB_RX128BYTE "Rx128Byte"
+#define MIB_RX128BYTE_ID 42
+#define MIB_RX128BYTE_OFFSET 0x20020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0x100
+#define MIB_RX128BYTE_NR_E 6
+
+#define MIB_RX256BYTE "Rx256Byte"
+#define MIB_RX256BYTE_ID 43
+#define MIB_RX256BYTE_OFFSET 0x20024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0x100
+#define MIB_RX256BYTE_NR_E 6
+
+#define MIB_RX512BYTE "Rx512Byte"
+#define MIB_RX512BYTE_ID 44
+#define MIB_RX512BYTE_OFFSET 0x20028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0x100
+#define MIB_RX512BYTE_NR_E 6
+
+#define MIB_RX1024BYTE "Rx1024Byte"
+#define MIB_RX1024BYTE_ID 45
+#define MIB_RX1024BYTE_OFFSET 0x2002c
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0x100
+#define MIB_RX1024BYTE_NR_E 6
+
+#define MIB_RX1518BYTE "Rx1518Byte"
+#define MIB_RX1518BYTE_ID 45
+#define MIB_RX1518BYTE_OFFSET 0x20030
+#define MIB_RX1518BYTE_E_LENGTH 4
+#define MIB_RX1518BYTE_E_OFFSET 0x100
+#define MIB_RX1518BYTE_NR_E 6
+
+#define MIB_RXMAXBYTE "RxMaxByte"
+#define MIB_RXMAXBYTE_ID 46
+#define MIB_RXMAXBYTE_OFFSET 0x20034
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0x100
+#define MIB_RXMAXBYTE_NR_E 6
+
+#define MIB_RXTOOLONG "RxTooLong"
+#define MIB_RXTOOLONG_ID 47
+#define MIB_RXTOOLONG_OFFSET 0x20038
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0x100
+#define MIB_RXTOOLONG_NR_E 6
+
+#define MIB_RXGOODBYTE_LO "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID 48
+#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_LO_NR_E 6
+
+#define MIB_RXGOODBYTE_HI "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID 49
+#define MIB_RXGOODBYTE_HI_OFFSET 0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_HI_NR_E 6
+
+#define MIB_RXBADBYTE_LO "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID 50
+#define MIB_RXBADBYTE_LO_OFFSET 0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0x100
+#define MIB_RXBADBYTE_LO_NR_E 6
+
+#define MIB_RXBADBYTE_HI "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID 51
+#define MIB_RXBADBYTE_HI_OFFSET 0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0x100
+#define MIB_RXBADBYTE_HI_NR_E 6
+
+#define MIB_RXOVERFLOW "RxOverFlow"
+#define MIB_RXOVERFLOW_ID 52
+#define MIB_RXOVERFLOW_OFFSET 0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0x100
+#define MIB_RXOVERFLOW_NR_E 6
+
+#define MIB_FILTERED "Filtered"
+#define MIB_FILTERED_ID 53
+#define MIB_FILTERED_OFFSET 0x20050
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0x100
+#define MIB_FILTERED_NR_E 6
+
+#define MIB_TXBROAD "TxBroad"
+#define MIB_TXBROAD_ID 54
+#define MIB_TXBROAD_OFFSET 0x20054
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0x100
+#define MIB_TXBROAD_NR_E 6
+
+#define MIB_TXPAUSE "TxPause"
+#define MIB_TXPAUSE_ID 55
+#define MIB_TXPAUSE_OFFSET 0x20058
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0x100
+#define MIB_TXPAUSE_NR_E 6
+
+#define MIB_TXMULTI "TxMulti"
+#define MIB_TXMULTI_ID 56
+#define MIB_TXMULTI_OFFSET 0x2005c
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0x100
+#define MIB_TXMULTI_NR_E 6
+
+#define MIB_TXUNDERRUN "TxUnderRun"
+#define MIB_TXUNDERRUN_ID 57
+#define MIB_TXUNDERRUN_OFFSET 0x20060
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0x100
+#define MIB_TXUNDERRUN_NR_E 6
+
+#define MIB_TX64BYTE "Tx64Byte"
+#define MIB_TX64BYTE_ID 58
+#define MIB_TX64BYTE_OFFSET 0x20064
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0x100
+#define MIB_TX64BYTE_NR_E 6
+
+#define MIB_TX128BYTE "Tx128Byte"
+#define MIB_TX128BYTE_ID 59
+#define MIB_TX128BYTE_OFFSET 0x20068
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0x100
+#define MIB_TX128BYTE_NR_E 6
+
+#define MIB_TX256BYTE "Tx256Byte"
+#define MIB_TX256BYTE_ID 60
+#define MIB_TX256BYTE_OFFSET 0x2006c
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0x100
+#define MIB_TX256BYTE_NR_E 6
+
+#define MIB_TX512BYTE "Tx512Byte"
+#define MIB_TX512BYTE_ID 61
+#define MIB_TX512BYTE_OFFSET 0x20070
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0x100
+#define MIB_TX512BYTE_NR_E 6
+
+#define MIB_TX1024BYTE "Tx1024Byte"
+#define MIB_TX1024BYTE_ID 62
+#define MIB_TX1024BYTE_OFFSET 0x20074
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0x100
+#define MIB_TX1024BYTE_NR_E 6
+
+#define MIB_TX1518BYTE "Tx1518Byte"
+#define MIB_TX1518BYTE_ID 62
+#define MIB_TX1518BYTE_OFFSET 0x20078
+#define MIB_TX1518BYTE_E_LENGTH 4
+#define MIB_TX1518BYTE_E_OFFSET 0x100
+#define MIB_TX1518BYTE_NR_E 6
+
+#define MIB_TXMAXBYTE "TxMaxByte"
+#define MIB_TXMAXBYTE_ID 63
+#define MIB_TXMAXBYTE_OFFSET 0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0x100
+#define MIB_TXMAXBYTE_NR_E 6
+
+#define MIB_TXOVERSIZE "TxOverSize"
+#define MIB_TXOVERSIZE_ID 64
+#define MIB_TXOVERSIZE_OFFSET 0x20080
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0x100
+#define MIB_TXOVERSIZE_NR_E 6
+
+#define MIB_TXBYTE_LO "TxByteLo"
+#define MIB_TXBYTE_LO_ID 65
+#define MIB_TXBYTE_LO_OFFSET 0x20084
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0x100
+#define MIB_TXBYTE_LO_NR_E 6
+
+#define MIB_TXBYTE_HI "TxByteHi"
+#define MIB_TXBYTE_HI_ID 66
+#define MIB_TXBYTE_HI_OFFSET 0x20088
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0x100
+#define MIB_TXBYTE_HI_NR_E 6
+
+#define MIB_TXCOLLISION "TxCollision"
+#define MIB_TXCOLLISION_ID 67
+#define MIB_TXCOLLISION_OFFSET 0x2008c
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0x100
+#define MIB_TXCOLLISION_NR_E 6
+
+#define MIB_TXABORTCOL "TxAbortCol"
+#define MIB_TXABORTCOL_ID 68
+#define MIB_TXABORTCOL_OFFSET 0x20090
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0x100
+#define MIB_TXABORTCOL_NR_E 6
+
+#define MIB_TXMULTICOL "TxMultiCol"
+#define MIB_TXMULTICOL_ID 69
+#define MIB_TXMULTICOL_OFFSET 0x20094
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0x100
+#define MIB_TXMULTICOL_NR_E 6
+
+#define MIB_TXSINGALCOL "TxSingalCol"
+#define MIB_TXSINGALCOL_ID 70
+#define MIB_TXSINGALCOL_OFFSET 0x20098
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0x100
+#define MIB_TXSINGALCOL_NR_E 6
+
+#define MIB_TXEXCDEFER "TxExcDefer"
+#define MIB_TXEXCDEFER_ID 71
+#define MIB_TXEXCDEFER_OFFSET 0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0x100
+#define MIB_TXEXCDEFER_NR_E 6
+
+#define MIB_TXDEFER "TxDefer"
+#define MIB_TXDEFER_ID 72
+#define MIB_TXDEFER_OFFSET 0x200a0
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0x100
+#define MIB_TXDEFER_NR_E 6
+
+#define MIB_TXLATECOL "TxLateCol"
+#define MIB_TXLATECOL_ID 73
+#define MIB_TXLATECOL_OFFSET 0x200a4
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0x100
+#define MIB_TXLATECOL_NR_E 6
+
+
+#define PPPOE_SESSION "pppoes"
+#define PPPOE_SESSION_ID 13
+#define PPPOE_SESSION_OFFSET 0x59100
+#define PPPOE_SESSION_E_LENGTH 4
+#define PPPOE_SESSION_E_OFFSET 0x4
+#define PPPOE_SESSION_NR_E 16
+
+#define ENTRY_VALID "pppoes_v"
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 19
+#define PPPOE_SESSION_ENTRY_VALID_BLEN 1
+#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW
+
+#define STRIP_EN "pppoes_s"
+#define PPPOE_SESSION_STRIP_EN_BOFFSET 16
+#define PPPOE_SESSION_STRIP_EN_BLEN 1
+#define PPPOE_SESSION_STRIP_EN_FLAG HSL_RW
+
+#define SEESION_ID "pppoes_id"
+#define PPPOE_SESSION_SEESION_ID_BOFFSET 0
+#define PPPOE_SESSION_SEESION_ID_BLEN 16
+#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_REG_H_ */
+
diff --git a/include/hsl/horus/horus_reg_access.h b/include/hsl/horus/horus_reg_access.h
new file mode 100644
index 0000000..de72b93
--- /dev/null
+++ b/include/hsl/horus/horus_reg_access.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HORUS_REG_ACCESS_H_
+#define _HORUS_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_REG_ACCESS_H_ */
+
diff --git a/include/hsl/horus/horus_stp.h b/include/hsl/horus/horus_stp.h
new file mode 100644
index 0000000..c3ecb6f
--- /dev/null
+++ b/include/hsl/horus/horus_stp.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_stp HORUS_STP
+ * @{
+ */
+#ifndef _HORUS_STP_H_
+#define _HORUS_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+ sw_error_t horus_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define HORUS_STP_INIT(rv, dev_id) \
+ { \
+ rv = horus_stp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+ HSL_LOCAL sw_error_t
+ horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HORUS_STP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/horus/horus_vlan.h b/include/hsl/horus/horus_vlan.h
new file mode 100644
index 0000000..84d9445
--- /dev/null
+++ b/include/hsl/horus/horus_vlan.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_vlan HORUS_VLAN
+ * @{
+ */
+#ifndef _HORUS_VLAN_H_
+#define _HORUS_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ horus_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define HORUS_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = horus_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define HORUS_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+ HSL_LOCAL sw_error_t
+ horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _HORUS_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/hsl.h b/include/hsl/hsl.h
new file mode 100644
index 0000000..7983e0d
--- /dev/null
+++ b/include/hsl/hsl.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_H
+#define _HSL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+ typedef sw_error_t
+ (*hsl_acl_rule_copy) (a_uint32_t dev_id, a_uint32_t src_addr,
+ a_uint32_t dest_addr, a_uint32_t size);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_invalid) (a_uint32_t dev_id, a_uint32_t addr,
+ a_uint32_t size);
+
+ typedef sw_error_t
+ (*hsl_acl_addr_update) (a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t info);
+
+ typedef struct
+ {
+ hsl_acl_rule_copy acl_rule_copy;
+ hsl_acl_rule_invalid acl_rule_invalid;
+ hsl_acl_addr_update acl_addr_update;
+ } hsl_acl_func_t;
+
+#define HSL_REG_ENTRY_GET(rv, dev, reg, index, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+ (a_uint8_t*)value, (a_uint8_t)val_len); \
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_ENTRY_SET(rv, dev, reg, index, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_set (dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+ (a_uint8_t*)value, (a_uint8_t)val_len); \
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_FIELD_GET(rv, dev, reg, index, field, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_field_get(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+ reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_FIELD_SET(rv, dev, reg, index, field, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api){ \
+ rv = p_api->reg_field_set(dev, reg##_OFFSET + ((a_uint32_t)index) * reg##_E_OFFSET,\
+ reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN, (a_uint8_t*)value, val_len);\
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_ENTRY_GEN_GET(rv, dev, addr, reg_len, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_get(dev, addr, (a_uint8_t*)value, val_len);\
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_ENTRY_GEN_SET(rv, dev, addr, reg_len, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_set(dev, addr, (a_uint8_t*)value, val_len); \
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_FIELD_GEN_GET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->reg_field_get(dev, regaddr, bitoffset, bitlength, \
+ (a_uint8_t *) value, val_len);\
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_REG_FIELD_GEN_SET(rv, dev, regaddr, bitlength, bitoffset, value, val_len) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) {\
+ rv = p_api->reg_field_set(dev, regaddr, bitoffset, bitlength, \
+ (a_uint8_t *) value, val_len);\
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_PHY_GET(rv, dev, phy_addr, reg, value) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->phy_get(dev, phy_addr, reg, value); \
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#define HSL_PHY_SET(rv, dev, phy_addr, reg, value) \
+do { \
+ hsl_api_t *p_api = hsl_api_ptr_get(dev); \
+ if (p_api) { \
+ rv = p_api->phy_set(dev, phy_addr, reg, value); \
+ } else { \
+ rv = SW_NOT_INITIALIZED; \
+ } \
+} while (0);
+
+#if (defined(API_LOCK) \
+&& (defined(HSL_STANDALONG) || (defined(KERNEL_MODULE) && defined(USER_MODE))))
+ extern aos_lock_t sw_hsl_api_lock;
+#define HSL_API_LOCK aos_lock(&sw_hsl_api_lock)
+#define HSL_API_UNLOCK aos_unlock(&sw_hsl_api_lock)
+#else
+#define HSL_API_LOCK
+#define HSL_API_UNLOCK
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HSL_H */
diff --git a/include/hsl/hsl_acl.h b/include/hsl/hsl_acl.h
new file mode 100644
index 0000000..1eb4168
--- /dev/null
+++ b/include/hsl/hsl_acl.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_ACL_H_
+#define _HSL_ACL_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+ sw_error_t
+ hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr);
+
+ sw_error_t
+ hsl_acl_pool_destroy(a_uint32_t dev_id);
+
+ sw_error_t
+ hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size,
+ a_uint32_t info, a_uint32_t * addr);
+
+ sw_error_t
+ hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr);
+
+ sw_error_t
+ hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size);
+
+ sw_error_t
+ hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /*_HSL_ACL_H_ */
diff --git a/include/hsl/hsl_api.h b/include/hsl/hsl_api.h
new file mode 100644
index 0000000..2825c73
--- /dev/null
+++ b/include/hsl/hsl_api.h
@@ -0,0 +1,2060 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_API_H
+#define _HSL_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal.h"
+
+ /* Misc */
+#define MISC_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_arp_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_arp_status_get) (a_uint32_t dev_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_frame_max_size_set) (a_uint32_t dev_id, a_uint32_t size);
+
+ typedef sw_error_t
+ (*hsl_frame_max_size_get) (a_uint32_t dev_id, a_uint32_t *size);
+
+ typedef sw_error_t
+ (*hsl_port_unk_sa_cmd_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_port_unk_sa_cmd_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_port_unk_uc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_unk_uc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_port_unk_mc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_unk_mc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_port_bc_filter_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_bc_filter_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_cpu_port_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_cpu_port_status_get) (a_uint32_t dev_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_bc_to_cpu_port_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_bc_to_cpu_port_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_dhcp_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_pppoe_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_pppoe_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_pppoe_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_pppoe_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_dhcp_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_arp_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_arp_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_eapol_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_eapol_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_add) (a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_del) (a_uint32_t dev_id, a_uint32_t session_id);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_get) (a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
+
+ typedef sw_error_t
+ (*hsl_eapol_status_set) (a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_eapol_status_get) (a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_ripv1_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_ripv1_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_arp_req_status_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_arp_req_status_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_arp_ack_status_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_arp_ack_status_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_table_add)(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_table_del)(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_table_get)(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_id_set)(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id);
+
+ typedef sw_error_t
+ (*hsl_pppoe_session_id_get)(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id);
+
+ typedef sw_error_t
+ (*hsl_intr_mask_set)(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+ typedef sw_error_t
+ (*hsl_intr_mask_get)(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+ typedef sw_error_t
+ (*hsl_intr_status_get)(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+ typedef sw_error_t
+ (*hsl_intr_status_clear)(a_uint32_t dev_id, a_uint32_t intr_status);
+
+ typedef sw_error_t
+ (*hsl_intr_port_link_mask_set)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t intr_mask);
+
+ typedef sw_error_t
+ (*hsl_intr_port_link_mask_get)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask);
+
+ typedef sw_error_t
+ (*hsl_intr_port_link_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask);
+
+ typedef sw_error_t
+ (*hsl_intr_mask_mac_linkchg_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_intr_mask_mac_linkchg_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_intr_status_mac_linkchg_get)(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+ typedef sw_error_t
+ (*hsl_intr_status_mac_linkchg_clear)(a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_cpu_vid_en_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_cpu_vid_en_get) (a_uint32_t dev_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_rtd_pppoe_en_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_rtd_pppoe_en_get) (a_uint32_t dev_id, a_bool_t *enable);
+
+ /* Port Control */
+#define PORT_CONTROL_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_port_duplex_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+ typedef sw_error_t
+ (*hsl_port_duplex_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+ typedef sw_error_t
+ (*hsl_port_speed_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+ typedef sw_error_t
+ (*hsl_port_autoneg_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+ typedef sw_error_t
+ (*hsl_port_speed_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+ typedef sw_error_t
+ (*hsl_port_autoneg_enable) (a_uint32_t dev_id, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_port_autoneg_restart) (a_uint32_t dev_id, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_port_autoneg_adv_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+ typedef sw_error_t
+ (*hsl_port_autoneg_adv_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+ typedef sw_error_t
+ (*hsl_port_hdr_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_hdr_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_port_flowctrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_flowctrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_flowctrl_forcemode_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_flowctrl_forcemode_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_powersave_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ typedef sw_error_t
+ (*hsl_port_powersave_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ typedef sw_error_t
+ (*hsl_port_hibernate_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ typedef sw_error_t
+ (*hsl_port_hibernate_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ typedef sw_error_t
+ (*hsl_port_cdt) (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+ typedef sw_error_t
+ (*hsl_port_rxhdr_mode_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_port_rxhdr_mode_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_port_txhdr_mode_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_port_txhdr_mode_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_header_type_set)(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+ typedef sw_error_t
+ (*hsl_header_type_get)(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+ typedef sw_error_t
+ (*hsl_port_txmac_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_txmac_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_rxmac_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_rxmac_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_txfc_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_txfc_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_rxfc_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_rxfc_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_bp_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_bp_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_link_forcemode_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_link_forcemode_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_link_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+ typedef sw_error_t
+ (*hsl_port_mac_loopback_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_mac_loopback_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ /* VLAN */
+#define VLAN_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_vlan_entry_append) (a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+ typedef sw_error_t
+ (*hsl_vlan_create) (a_uint32_t dev_id, a_uint32_t vlan_id);
+
+ typedef sw_error_t
+ (*hsl_vlan_next) (a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_vlan_t * p_vlan);
+
+ typedef sw_error_t
+ (*hsl_vlan_find) (a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_vlan_t * p_vlan);
+
+ typedef sw_error_t
+ (*hsl_vlan_member_update) (a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+ typedef sw_error_t
+ (*hsl_vlan_delete) (a_uint32_t dev_id, a_uint32_t vlan_id);
+
+ typedef sw_error_t
+ (*hsl_vlan_flush) (a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_vlan_fid_set)(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+ typedef sw_error_t
+ (*hsl_vlan_fid_get)(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+ typedef sw_error_t
+ (*hsl_vlan_member_add)(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+ typedef sw_error_t
+ (*hsl_vlan_member_del)(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_vlan_learning_state_set)(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_vlan_learning_state_get)(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable);
+
+ /* Port Vlan */
+#define PORT_VLAN_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_port_1qmode_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+ typedef sw_error_t
+ (*hsl_port_1qmode_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+ typedef sw_error_t
+ (*hsl_port_egvlanmode_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+ typedef sw_error_t
+ (*hsl_port_egvlanmode_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+ typedef sw_error_t
+ (*hsl_portvlan_member_add) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+ typedef sw_error_t
+ (*hsl_portvlan_member_del) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+ typedef sw_error_t
+ (*hsl_portvlan_member_update) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+ typedef sw_error_t
+ (*hsl_portvlan_member_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+ typedef sw_error_t
+ (*hsl_port_nestvlan_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_nestvlan_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_nestvlan_tpid_set) (a_uint32_t dev_id, a_uint32_t tpid);
+
+ typedef sw_error_t
+ (*hsl_nestvlan_tpid_get) (a_uint32_t dev_id, a_uint32_t *tpid);
+
+ typedef sw_error_t
+ (*hsl_port_default_vid_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+ typedef sw_error_t
+ (*hsl_port_default_vid_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ typedef sw_error_t
+ (*hsl_port_force_default_vid_set) (a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_force_default_vid_get) (a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_force_portvlan_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_force_portvlan_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_invlan_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_port_invlan_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_port_tls_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_tls_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_pri_propagation_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_pri_propagation_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_default_svid_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+ typedef sw_error_t
+ (*hsl_port_default_svid_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ typedef sw_error_t
+ (*hsl_port_default_cvid_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+ typedef sw_error_t
+ (*hsl_port_default_cvid_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_propagation_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_propagation_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_trans_add) (a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_trans_del) (a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_trans_get) (a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+ typedef sw_error_t
+ (*hsl_qinq_mode_set) (a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_qinq_mode_get) (a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_port_qinq_role_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t role);
+
+ typedef sw_error_t
+ (*hsl_port_qinq_role_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t * role);
+
+ typedef sw_error_t
+ (*hsl_port_vlan_trans_iterate) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_port_mac_vlan_xlt_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_mac_vlan_xlt_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_netisolate_set) (a_uint32_t dev_id, a_uint32_t enable);
+
+ typedef sw_error_t
+ (*hsl_netisolate_get) (a_uint32_t dev_id, a_uint32_t *enable);
+
+ typedef sw_error_t
+ (*hsl_eg_trans_filter_bypass_en_set) (a_uint32_t dev_id, a_uint32_t enable);
+
+ typedef sw_error_t
+ (*hsl_eg_trans_filter_bypass_en_get) (a_uint32_t dev_id, a_uint32_t *enable);
+
+
+ /* FDB */
+#define FDB_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_fdb_add) (a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_del_all) (a_uint32_t dev_id, a_uint32_t flag);
+
+ typedef sw_error_t
+ (*hsl_fdb_del_by_port) (a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+ typedef sw_error_t
+ (*hsl_fdb_del_by_mac) (a_uint32_t dev_id, const fal_fdb_entry_t * addr);
+
+ typedef sw_error_t
+ (*hsl_fdb_first) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_next) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_find) (a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_learn_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_learn_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_age_ctrl_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_age_ctrl_get) (a_uint32_t dev_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_vlan_ivl_svl_set)(a_uint32_t dev_id, fal_fdb_smode smode);
+
+ typedef sw_error_t
+ (*hsl_fdb_vlan_ivl_svl_get)(a_uint32_t dev_id, fal_fdb_smode* smode);
+
+ typedef sw_error_t
+ (*hsl_fdb_age_time_set) (a_uint32_t dev_id, a_uint32_t * time);
+
+ typedef sw_error_t
+ (*hsl_fdb_age_time_get) (a_uint32_t dev_id, a_uint32_t *time);
+
+ typedef sw_error_t
+ (*hsl_fdb_iterate)(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_extend_next)(a_uint32_t dev_id, fal_fdb_op_t * op,
+ fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_extend_first)(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_transfer)(a_uint32_t dev_id, fal_port_t old_port,
+ fal_port_t new_port, a_uint32_t fid,
+ fal_fdb_op_t * option);
+
+ typedef sw_error_t
+ (*hsl_port_fdb_learn_limit_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+ typedef sw_error_t
+ (*hsl_port_fdb_learn_limit_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+ typedef sw_error_t
+ (*hsl_port_fdb_learn_exceed_cmd_set)(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_port_fdb_learn_exceed_cmd_get)(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_fdb_learn_limit_set)(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t cnt);
+
+ typedef sw_error_t
+ (*hsl_fdb_learn_limit_get)(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * cnt);
+
+ typedef sw_error_t
+ (*hsl_fdb_learn_exceed_cmd_set)(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_fdb_learn_exceed_cmd_get)(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_fdb_resv_add)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_resv_del)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_resv_find)(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_resv_iterate)(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_learn_static_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_learn_static_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_add)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_fdb_port_del)(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+ /* QOS */
+#define QOS_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_cosmap_up_queue_set) (a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_up_queue_get) (a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_queue_set) (a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_queue_get) (a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue);
+
+ typedef sw_error_t
+ (*hsl_qos_port_mode_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_mode_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_mode_pri_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode,
+ a_uint32_t pri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_mode_pri_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode,
+ a_uint32_t * pri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_up_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_up_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up);
+
+ typedef sw_error_t
+ (*hsl_qos_sch_mode_set) (a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+ typedef sw_error_t
+ (*hsl_qos_sch_mode_get) (a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t queue_id, a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t queue_id, a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_port_tx_buf_status_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_tx_buf_status_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_red_en_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_red_en_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_tx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_port_tx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_port_rx_buf_nr_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_port_rx_buf_nr_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ typedef sw_error_t
+ (*hsl_qos_port_sch_mode_set) (a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+ typedef sw_error_t
+ (*hsl_qos_port_sch_mode_get) (a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_spri_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_spri_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_cpri_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_default_cpri_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri);
+
+ typedef sw_error_t
+ (*hsl_qos_port_force_spri_status_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_force_spri_status_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_force_cpri_status_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_port_force_cpri_status_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_remark_table_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_qos_queue_remark_table_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+ /* Rate */
+#define RATE_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_rate_queue_egrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t queue_id, a_uint32_t * speed,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_rate_queue_egrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_rate_port_egrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_rate_port_egrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_rate_port_inrl_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_rate_port_inrl_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_storm_ctrl_frame_set) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_storm_ctrl_frame_get) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_storm_ctrl_rate_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate);
+
+ typedef sw_error_t
+ (*hsl_storm_ctrl_rate_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate);
+
+ typedef sw_error_t
+ (*hsl_rate_port_policer_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ typedef sw_error_t
+ (*hsl_rate_port_policer_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ typedef sw_error_t
+ (*hsl_rate_port_shaper_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper);
+
+ typedef sw_error_t
+ (*hsl_rate_port_shaper_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper);
+
+ typedef sw_error_t
+ (*hsl_rate_queue_shaper_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+ typedef sw_error_t
+ (*hsl_rate_queue_shaper_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+ typedef sw_error_t
+ (*hsl_rate_acl_policer_set)(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ typedef sw_error_t
+ (*hsl_rate_acl_policer_get)(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ typedef sw_error_t
+ (*hsl_rate_port_add_rate_byte_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number);
+
+ typedef sw_error_t
+ (*hsl_rate_port_add_rate_byte_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+ typedef sw_error_t
+ (*hsl_rate_port_gol_flow_en_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_rate_port_gol_flow_en_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ /* Mirror */
+#define MIRROR_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_mirr_analysis_port_set) (a_uint32_t dev_id, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_mirr_analysis_port_get) (a_uint32_t dev_id, fal_port_t * port_id);
+
+ typedef sw_error_t
+ (*hsl_mirr_port_in_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_mirr_port_in_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_mirr_port_eg_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_mirr_port_eg_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ /* STP */
+#define STP_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_stp_port_state_set) (a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+ typedef sw_error_t
+ (*hsl_stp_port_state_get) (a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+ /* IGMP */
+#define IGMP_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_port_igmps_status_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_igmps_status_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_mld_cmd_set) (a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_igmp_mld_cmd_get) (a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_join_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_join_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_leave_set) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_leave_get) (a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_rp_set) (a_uint32_t dev_id, fal_pbmp_t pts);
+
+ typedef sw_error_t
+ (*hsl_igmp_rp_get) (a_uint32_t dev_id, fal_pbmp_t * pts);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_creat_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_creat_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_static_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_static_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_leaky_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_leaky_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_v3_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_v3_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_queue_set) (a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+ typedef sw_error_t
+ (*hsl_igmp_entry_queue_get) (a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_mld_learn_limit_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_mld_learn_limit_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_mld_learn_exceed_cmd_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_port_igmp_mld_learn_exceed_cmd_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+ typedef sw_error_t
+ (*hsl_igmp_sg_entry_set)(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_igmp_sg_entry_clear)(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_igmp_sg_entry_show)(a_uint32_t dev_id);
+
+ /* Leaky */
+#define LEAKY_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_uc_leaky_mode_set) (a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+ typedef sw_error_t
+ (*hsl_uc_leaky_mode_get) (a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+ typedef sw_error_t
+ (*hsl_mc_leaky_mode_set) (a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+ typedef sw_error_t
+ (*hsl_mc_leaky_mode_get) (a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode);
+
+ typedef sw_error_t
+ (*hsl_port_arp_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_arp_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_port_uc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_uc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ typedef sw_error_t
+ (*hsl_port_mc_leaky_set) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_mc_leaky_get) (a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+ /* Mib */
+#define MIB_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_get_mib_info) (a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info);
+
+ typedef sw_error_t
+ (*hsl_mib_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_mib_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_mib_port_flush_counters) (a_uint32_t dev_id, fal_port_t port_id);
+
+ typedef sw_error_t
+ (*hsl_mib_cpukeep_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_mib_cpukeep_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ /* Acl */
+#define ACL_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_acl_list_creat) (a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri);
+
+ typedef sw_error_t
+ (*hsl_acl_list_destroy) (a_uint32_t dev_id, a_uint32_t list_id);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_add) (a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr, fal_acl_rule_t * rule);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_delete) (a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_query) (a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ fal_acl_rule_t * rule);
+
+ typedef sw_error_t
+ (*hsl_acl_list_bind) (a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ typedef sw_error_t
+ (*hsl_acl_list_unbind) (a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ typedef sw_error_t
+ (*hsl_acl_status_set) (a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_acl_status_get) (a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_acl_list_dump) (a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_dump) (a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_acl_port_udf_profile_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length);
+
+ typedef sw_error_t
+ (*hsl_acl_port_udf_profile_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_active) (a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_deactive) (a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_src_filter_sts_set) (a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_src_filter_sts_get) (a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t * enable);
+
+ typedef a_uint32_t
+ (*hsl_acl_rule_get_offset)(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+ typedef sw_error_t
+ (*hsl_acl_rule_sync_multi_portmap)(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+ typedef sw_error_t
+ (*hsl_dev_reset) (a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_dev_clean) (a_uint32_t dev_id);
+
+ typedef sw_error_t
+ (*hsl_dev_access_set) (a_uint32_t dev_id, hsl_access_mode mode);
+
+ /* LED */
+#define LED_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_led_ctrl_pattern_set) (a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+ typedef sw_error_t
+ (*hsl_led_ctrl_pattern_get) (a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+ /* CoSMAP */
+#define COSMAP_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_to_pri_set)(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri);
+
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_to_pri_get)(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri);
+
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_to_dp_set)(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t dp);
+
+ typedef sw_error_t
+ (*hsl_cosmap_dscp_to_dp_get)(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * dp);
+
+ typedef sw_error_t
+ (*hsl_cosmap_up_to_pri_set)(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t pri);
+
+ typedef sw_error_t
+ (*hsl_cosmap_up_to_pri_get)(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * pri);
+
+ typedef sw_error_t
+ (*hsl_cosmap_up_to_dp_set)(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t dp);
+
+ typedef sw_error_t
+ (*hsl_cosmap_up_to_dp_get)(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * dp);
+
+ typedef sw_error_t
+ (*hsl_cosmap_pri_to_queue_set)(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_pri_to_queue_get)(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_pri_to_ehqueue_set)(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_pri_to_ehqueue_get)(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ typedef sw_error_t
+ (*hsl_cosmap_egress_remark_set)(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+ typedef sw_error_t
+ (*hsl_cosmap_egress_remark_get)(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+
+ /* IP */
+#define IP_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_ip_host_add)(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+ typedef sw_error_t
+ (*hsl_ip_host_del)(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry);
+
+ typedef sw_error_t
+ (*hsl_ip_host_get)(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry);
+
+ typedef sw_error_t
+ (*hsl_ip_host_next)(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry);
+
+ typedef sw_error_t
+ (*hsl_ip_host_counter_bind)(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_ip_host_pppoe_bind)(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_ip_pt_arp_learn_set)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags);
+
+ typedef sw_error_t
+ (*hsl_ip_pt_arp_learn_get)(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags);
+
+ typedef sw_error_t
+ (*hsl_ip_arp_learn_set)(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_ip_arp_learn_get)(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_ip_source_guard_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_ip_source_guard_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_ip_unk_source_cmd_set)(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_ip_unk_source_cmd_get)(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_ip_arp_guard_set)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_ip_arp_guard_get)(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_arp_unk_source_cmd_set)(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_arp_unk_source_cmd_get)(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ typedef sw_error_t
+ (*hsl_ip_route_status_set)(a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_ip_route_status_get)(a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_ip_intf_entry_add)(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_ip_intf_entry_del)(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_ip_intf_entry_next)(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry);
+
+ typedef sw_error_t
+ (*hsl_ip_age_time_set)(a_uint32_t dev_id, a_uint32_t * time);
+
+ typedef sw_error_t
+ (*hsl_ip_age_time_get)(a_uint32_t dev_id, a_uint32_t * time);
+
+ typedef sw_error_t
+ (*hsl_ip_wcmp_hash_mode_set)(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ typedef sw_error_t
+ (*hsl_ip_wcmp_hash_mode_get)(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+ /* NAT */
+#define NAT_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_nat_add)(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+ typedef sw_error_t
+ (*hsl_nat_del)(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry);
+
+ typedef sw_error_t
+ (*hsl_nat_get)(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry);
+
+ typedef sw_error_t
+ (*hsl_nat_next)(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry);
+
+ typedef sw_error_t
+ (*hsl_nat_counter_bind)(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_napt_add)(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+ typedef sw_error_t
+ (*hsl_napt_del)(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry);
+
+ typedef sw_error_t
+ (*hsl_napt_get)(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry);
+
+ typedef sw_error_t
+ (*hsl_napt_next)(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry);
+
+ typedef sw_error_t
+ (*hsl_napt_counter_bind)(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_nat_status_set)(a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_nat_status_get)(a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_nat_hash_mode_set)(a_uint32_t dev_id, a_uint32_t mode);
+
+ typedef sw_error_t
+ (*hsl_nat_hash_mode_get)(a_uint32_t dev_id, a_uint32_t * mode);
+
+ typedef sw_error_t
+ (*hsl_napt_status_set)(a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_napt_status_get)(a_uint32_t dev_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_napt_mode_set)(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+ typedef sw_error_t
+ (*hsl_napt_mode_get)(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_base_addr_set)(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_base_addr_get)(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_base_mask_set)(a_uint32_t dev_id, fal_ip4_addr_t mask);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_base_mask_get)(a_uint32_t dev_id, fal_ip4_addr_t * mask);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_addr_mode_set)(a_uint32_t dev_id, a_bool_t map_en);
+
+ typedef sw_error_t
+ (*hsl_nat_prv_addr_mode_get)(a_uint32_t dev_id, a_bool_t * map_en);
+
+ typedef sw_error_t
+ (*hsl_nat_pub_addr_add)(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+ typedef sw_error_t
+ (*hsl_nat_pub_addr_del)(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry);
+
+ typedef sw_error_t
+ (*hsl_nat_pub_addr_next)(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry);
+
+ typedef sw_error_t
+ (*hsl_nat_unk_session_cmd_set)(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ typedef sw_error_t
+ (*hsl_nat_unk_session_cmd_get)(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ /* SEC */
+#define SEC_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_sec_norm_item_set)(a_uint32_t dev_id, fal_norm_item_t item, void * value);
+
+ typedef sw_error_t
+ (*hsl_sec_norm_item_get)(a_uint32_t dev_id, fal_norm_item_t item, void * value);
+
+
+ /* Trunk */
+#define TRUNK_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_trunk_group_set)(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member);
+
+ typedef sw_error_t
+ (*hsl_trunk_group_get)(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member);
+
+ typedef sw_error_t
+ (*hsl_trunk_hash_mode_set)(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ typedef sw_error_t
+ (*hsl_trunk_hash_mode_get)(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+ typedef sw_error_t
+ (*hsl_trunk_manipulate_sa_set)(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ typedef sw_error_t
+ (*hsl_trunk_manipulate_sa_get)(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ /* Interface Control */
+#define INTERFACE_CONTROL_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_interface_mac_mode_set)(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_interface_mac_mode_get)(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_port_3az_status_set)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_port_3az_status_get)(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ typedef sw_error_t
+ (*hsl_interface_phy_mode_set)(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_interface_phy_mode_get)(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_interface_fx100_ctrl_set)(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_interface_fx100_ctrl_get)(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config);
+
+ typedef sw_error_t
+ (*hsl_interface_fx100_status_get)(a_uint32_t dev_id, a_uint32_t* status);
+
+ typedef sw_error_t
+ (*hsl_interface_mac06_exch_set)(a_uint32_t dev_id, a_bool_t enable);
+
+ typedef sw_error_t
+ (*hsl_interface_mac06_exch_get)(a_uint32_t dev_id, a_bool_t* enable);
+
+ /* REG */
+#define REG_FUNC_PROTOTYPE_DEF
+ typedef sw_error_t
+ (*hsl_phy_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+ a_uint16_t * value);
+
+ typedef sw_error_t
+ (*hsl_phy_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+ a_uint16_t value);
+
+ typedef sw_error_t
+ (*hsl_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ typedef sw_error_t
+ (*hsl_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ typedef sw_error_t
+ (*hsl_reg_field_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ typedef sw_error_t
+ (*hsl_reg_field_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ typedef sw_error_t
+ (*hsl_reg_entries_get) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t entry_len, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ typedef sw_error_t
+ (*hsl_reg_entries_set) (a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t entry_len, const a_uint8_t value[],
+ a_uint32_t value_len);
+
+ typedef struct
+ {
+#if (!(defined(USER_MODE) && defined(KERNEL_MODULE)))
+#ifndef HSL_STANDALONG
+ /* Misc */
+ hsl_arp_status_set arp_status_set;
+ hsl_arp_status_get arp_status_get;
+ hsl_frame_max_size_set frame_max_size_set;
+ hsl_frame_max_size_get frame_max_size_get;
+ hsl_port_unk_sa_cmd_set port_unk_sa_cmd_set;
+ hsl_port_unk_sa_cmd_get port_unk_sa_cmd_get;
+ hsl_port_unk_uc_filter_set port_unk_uc_filter_set;
+ hsl_port_unk_uc_filter_get port_unk_uc_filter_get;
+ hsl_port_unk_mc_filter_set port_unk_mc_filter_set;
+ hsl_port_unk_mc_filter_get port_unk_mc_filter_get;
+ hsl_port_bc_filter_set port_bc_filter_set;
+ hsl_port_bc_filter_get port_bc_filter_get;
+ hsl_nestvlan_tpid_set nestvlan_tpid_set;
+ hsl_nestvlan_tpid_get nestvlan_tpid_get;
+ hsl_cpu_port_status_set cpu_port_status_set;
+ hsl_cpu_port_status_get cpu_port_status_get;
+ hsl_bc_to_cpu_port_set bc_to_cpu_port_set;
+ hsl_bc_to_cpu_port_get bc_to_cpu_port_get;
+ hsl_pppoe_cmd_set pppoe_cmd_set;
+ hsl_pppoe_cmd_get pppoe_cmd_get;
+ hsl_pppoe_status_set pppoe_status_set;
+ hsl_pppoe_status_get pppoe_status_get;
+ hsl_port_dhcp_set port_dhcp_set;
+ hsl_port_dhcp_get port_dhcp_get;
+ hsl_arp_cmd_set arp_cmd_set;
+ hsl_arp_cmd_get arp_cmd_get;
+ hsl_eapol_cmd_set eapol_cmd_set;
+ hsl_eapol_cmd_get eapol_cmd_get;
+ hsl_pppoe_session_add pppoe_session_add;
+ hsl_pppoe_session_del pppoe_session_del;
+ hsl_pppoe_session_get pppoe_session_get;
+ hsl_eapol_status_set eapol_status_set;
+ hsl_eapol_status_get eapol_status_get;
+ hsl_ripv1_status_set ripv1_status_set;
+ hsl_ripv1_status_get ripv1_status_get;
+ hsl_port_arp_req_status_set port_arp_req_status_set;
+ hsl_port_arp_req_status_get port_arp_req_status_get;
+ hsl_port_arp_ack_status_set port_arp_ack_status_set;
+ hsl_port_arp_ack_status_get port_arp_ack_status_get;
+ hsl_pppoe_session_table_add pppoe_session_table_add;
+ hsl_pppoe_session_table_del pppoe_session_table_del;
+ hsl_pppoe_session_table_get pppoe_session_table_get;
+ hsl_pppoe_session_id_set pppoe_session_id_set;
+ hsl_pppoe_session_id_get pppoe_session_id_get;
+ hsl_intr_mask_set intr_mask_set;
+ hsl_intr_mask_get intr_mask_get;
+ hsl_intr_status_get intr_status_get;
+ hsl_intr_status_clear intr_status_clear;
+ hsl_intr_port_link_mask_set intr_port_link_mask_set;
+ hsl_intr_port_link_mask_get intr_port_link_mask_get;
+ hsl_intr_port_link_status_get intr_port_link_status_get;
+ hsl_intr_mask_mac_linkchg_set intr_mask_mac_linkchg_set;
+ hsl_intr_mask_mac_linkchg_get intr_mask_mac_linkchg_get;
+ hsl_intr_status_mac_linkchg_get intr_status_mac_linkchg_get;
+ hsl_cpu_vid_en_set cpu_vid_en_set;
+ hsl_cpu_vid_en_get cpu_vid_en_get;
+ hsl_rtd_pppoe_en_set rtd_pppoe_en_set;
+ hsl_rtd_pppoe_en_get rtd_pppoe_en_get;
+ hsl_intr_status_mac_linkchg_clear intr_status_mac_linkchg_clear;
+
+
+ /* Port control */
+ hsl_port_duplex_set port_duplex_set;
+ hsl_port_duplex_get port_duplex_get;
+ hsl_port_speed_set port_speed_set;
+ hsl_port_speed_get port_speed_get;
+ hsl_port_autoneg_status_get port_autoneg_status_get;
+ hsl_port_autoneg_enable port_autoneg_enable;
+ hsl_port_autoneg_restart port_autoneg_restart;
+ hsl_port_autoneg_adv_get port_autoneg_adv_get;
+ hsl_port_autoneg_adv_set port_autoneg_adv_set;
+ hsl_port_hdr_status_set port_hdr_status_set;
+ hsl_port_hdr_status_get port_hdr_status_get;
+ hsl_port_flowctrl_set port_flowctrl_set;
+ hsl_port_flowctrl_get port_flowctrl_get;
+ hsl_port_flowctrl_forcemode_set port_flowctrl_forcemode_set;
+ hsl_port_flowctrl_forcemode_get port_flowctrl_forcemode_get;
+
+ hsl_port_powersave_set port_powersave_set;
+ hsl_port_powersave_get port_powersave_get;
+ hsl_port_hibernate_set port_hibernate_set;
+ hsl_port_hibernate_get port_hibernate_get;
+ hsl_port_cdt port_cdt;
+ hsl_port_rxhdr_mode_set port_rxhdr_mode_set;
+ hsl_port_rxhdr_mode_get port_rxhdr_mode_get;
+ hsl_port_txhdr_mode_set port_txhdr_mode_set;
+ hsl_port_txhdr_mode_get port_txhdr_mode_get;
+ hsl_header_type_set header_type_set;
+ hsl_header_type_get header_type_get;
+ hsl_port_txmac_status_set port_txmac_status_set;
+ hsl_port_txmac_status_get port_txmac_status_get;
+ hsl_port_rxmac_status_set port_rxmac_status_set;
+ hsl_port_rxmac_status_get port_rxmac_status_get;
+ hsl_port_txfc_status_set port_txfc_status_set;
+ hsl_port_txfc_status_get port_txfc_status_get;
+ hsl_port_rxfc_status_set port_rxfc_status_set;
+ hsl_port_rxfc_status_get port_rxfc_status_get;
+ hsl_port_bp_status_set port_bp_status_set;
+ hsl_port_bp_status_get port_bp_status_get;
+ hsl_port_link_forcemode_set port_link_forcemode_set;
+ hsl_port_link_forcemode_get port_link_forcemode_get;
+ hsl_port_link_status_get port_link_status_get;
+ hsl_port_mac_loopback_set port_mac_loopback_set;
+ hsl_port_mac_loopback_get port_mac_loopback_get;
+
+ /* VLAN */
+ hsl_vlan_entry_append vlan_entry_append;
+ hsl_vlan_create vlan_creat;
+ hsl_vlan_member_update vlan_member_update;
+ hsl_vlan_delete vlan_delete;
+ hsl_vlan_find vlan_find;
+ hsl_vlan_next vlan_next;
+ hsl_vlan_flush vlan_flush;
+ hsl_vlan_fid_set vlan_fid_set;
+ hsl_vlan_fid_get vlan_fid_get;
+ hsl_vlan_member_add vlan_member_add;
+ hsl_vlan_member_del vlan_member_del;
+ hsl_vlan_learning_state_set vlan_learning_state_set;
+ hsl_vlan_learning_state_get vlan_learning_state_get;
+
+ /* Port VLAN */
+ hsl_port_1qmode_set port_1qmode_set;
+ hsl_port_1qmode_get port_1qmode_get;
+ hsl_port_egvlanmode_get port_egvlanmode_get;
+ hsl_port_egvlanmode_set port_egvlanmode_set;
+ hsl_portvlan_member_add portvlan_member_add;
+ hsl_portvlan_member_del portvlan_member_del;
+ hsl_portvlan_member_update portvlan_member_update;
+ hsl_portvlan_member_get portvlan_member_get;
+ hsl_port_default_vid_set port_default_vid_set;
+ hsl_port_default_vid_get port_default_vid_get;
+ hsl_port_force_default_vid_set port_force_default_vid_set;
+ hsl_port_force_default_vid_get port_force_default_vid_get;
+ hsl_port_force_portvlan_set port_force_portvlan_set;
+ hsl_port_force_portvlan_get port_force_portvlan_get;
+ hsl_port_nestvlan_set port_nestvlan_set;
+ hsl_port_nestvlan_get port_nestvlan_get;
+ hsl_port_invlan_mode_set port_invlan_mode_set;
+ hsl_port_invlan_mode_get port_invlan_mode_get;
+ hsl_port_tls_set port_tls_set;
+ hsl_port_tls_get port_tls_get;
+ hsl_port_pri_propagation_set port_pri_propagation_set;
+ hsl_port_pri_propagation_get port_pri_propagation_get;
+ hsl_port_default_svid_set port_default_svid_set;
+ hsl_port_default_svid_get port_default_svid_get;
+ hsl_port_default_cvid_set port_default_cvid_set;
+ hsl_port_default_cvid_get port_default_cvid_get;
+ hsl_port_vlan_propagation_set port_vlan_propagation_set;
+ hsl_port_vlan_propagation_get port_vlan_propagation_get;
+ hsl_port_vlan_trans_add port_vlan_trans_add;
+ hsl_port_vlan_trans_del port_vlan_trans_del;
+ hsl_port_vlan_trans_get port_vlan_trans_get;
+ hsl_qinq_mode_set qinq_mode_set;
+ hsl_qinq_mode_get qinq_mode_get;
+ hsl_port_qinq_role_set port_qinq_role_set;
+ hsl_port_qinq_role_get port_qinq_role_get;
+ hsl_port_vlan_trans_iterate port_vlan_trans_iterate;
+ hsl_port_mac_vlan_xlt_set port_mac_vlan_xlt_set;
+ hsl_port_mac_vlan_xlt_get port_mac_vlan_xlt_get;
+ hsl_netisolate_set netisolate_set;
+ hsl_netisolate_get netisolate_get;
+ hsl_eg_trans_filter_bypass_en_set eg_trans_filter_bypass_en_set;
+ hsl_eg_trans_filter_bypass_en_get eg_trans_filter_bypass_en_get;
+
+ /* FDB */
+ hsl_fdb_add fdb_add;
+ hsl_fdb_del_all fdb_del_all;
+ hsl_fdb_del_by_port fdb_del_by_port;
+ hsl_fdb_del_by_mac fdb_del_by_mac;
+ hsl_fdb_first fdb_first;
+ hsl_fdb_next fdb_next;
+ hsl_fdb_find fdb_find;
+ hsl_fdb_port_learn_set port_learn_set;
+ hsl_fdb_port_learn_get port_learn_get;
+ hsl_fdb_age_ctrl_set age_ctrl_set;
+ hsl_fdb_age_ctrl_get age_ctrl_get;
+ hsl_fdb_vlan_ivl_svl_set vlan_ivl_svl_set;
+ hsl_fdb_vlan_ivl_svl_get vlan_ivl_svl_get;
+ hsl_fdb_age_time_set age_time_set;
+ hsl_fdb_age_time_get age_time_get;
+ hsl_fdb_iterate fdb_iterate;
+ hsl_fdb_extend_next fdb_extend_next;
+ hsl_fdb_extend_first fdb_extend_first;
+ hsl_fdb_transfer fdb_transfer;
+ hsl_port_fdb_learn_limit_set port_fdb_learn_limit_set;
+ hsl_port_fdb_learn_limit_get port_fdb_learn_limit_get;
+ hsl_port_fdb_learn_exceed_cmd_set port_fdb_learn_exceed_cmd_set;
+ hsl_port_fdb_learn_exceed_cmd_get port_fdb_learn_exceed_cmd_get;
+ hsl_fdb_learn_limit_set fdb_learn_limit_set;
+ hsl_fdb_learn_limit_get fdb_learn_limit_get;
+ hsl_fdb_learn_exceed_cmd_set fdb_learn_exceed_cmd_set;
+ hsl_fdb_learn_exceed_cmd_get fdb_learn_exceed_cmd_get;
+ hsl_fdb_resv_add fdb_resv_add;
+ hsl_fdb_resv_del fdb_resv_del;
+ hsl_fdb_resv_find fdb_resv_find;
+ hsl_fdb_resv_iterate fdb_resv_iterate;
+ hsl_fdb_port_learn_static_set fdb_port_learn_static_set;
+ hsl_fdb_port_learn_static_get fdb_port_learn_static_get;
+ hsl_fdb_port_add fdb_port_add;
+ hsl_fdb_port_del fdb_port_del;
+
+ /* QOS */
+ hsl_qos_sch_mode_set qos_sch_mode_set;
+ hsl_qos_sch_mode_get qos_sch_mode_get;
+ hsl_qos_queue_tx_buf_status_set qos_queue_tx_buf_status_set;
+ hsl_qos_queue_tx_buf_status_get qos_queue_tx_buf_status_get;
+ hsl_qos_port_tx_buf_status_set qos_port_tx_buf_status_set;
+ hsl_qos_port_tx_buf_status_get qos_port_tx_buf_status_get;
+ hsl_qos_port_red_en_set qos_port_red_en_set;
+ hsl_qos_port_red_en_get qos_port_red_en_get;
+ hsl_qos_queue_tx_buf_nr_set qos_queue_tx_buf_nr_set;
+ hsl_qos_queue_tx_buf_nr_get qos_queue_tx_buf_nr_get;
+ hsl_qos_port_tx_buf_nr_set qos_port_tx_buf_nr_set;
+ hsl_qos_port_tx_buf_nr_get qos_port_tx_buf_nr_get;
+ hsl_qos_port_rx_buf_nr_set qos_port_rx_buf_nr_set;
+ hsl_qos_port_rx_buf_nr_get qos_port_rx_buf_nr_get;
+ hsl_cosmap_up_queue_set cosmap_up_queue_set;
+ hsl_cosmap_up_queue_get cosmap_up_queue_get;
+ hsl_cosmap_dscp_queue_set cosmap_dscp_queue_set;
+ hsl_cosmap_dscp_queue_get cosmap_dscp_queue_get;
+ hsl_qos_port_mode_set qos_port_mode_set;
+ hsl_qos_port_mode_get qos_port_mode_get;
+ hsl_qos_port_mode_pri_set qos_port_mode_pri_set;
+ hsl_qos_port_mode_pri_get qos_port_mode_pri_get;
+ hsl_qos_port_default_up_set qos_port_default_up_set;
+ hsl_qos_port_default_up_get qos_port_default_up_get;
+ hsl_qos_port_sch_mode_set qos_port_sch_mode_set;
+ hsl_qos_port_sch_mode_get qos_port_sch_mode_get;
+ hsl_qos_port_default_spri_set qos_port_default_spri_set;
+ hsl_qos_port_default_spri_get qos_port_default_spri_get;
+ hsl_qos_port_default_cpri_set qos_port_default_cpri_set;
+ hsl_qos_port_default_cpri_get qos_port_default_cpri_get;
+ hsl_qos_port_force_spri_status_set qos_port_force_spri_status_set;
+ hsl_qos_port_force_spri_status_get qos_port_force_spri_status_get;
+ hsl_qos_port_force_cpri_status_set qos_port_force_cpri_status_set;
+ hsl_qos_port_force_cpri_status_get qos_port_force_cpri_status_get;
+
+ hsl_qos_queue_remark_table_set qos_queue_remark_table_set;
+ hsl_qos_queue_remark_table_get qos_queue_remark_table_get;
+
+ /* Rate */
+ hsl_storm_ctrl_frame_set storm_ctrl_frame_set;
+ hsl_storm_ctrl_frame_get storm_ctrl_frame_get;
+ hsl_storm_ctrl_rate_set storm_ctrl_rate_set;
+ hsl_storm_ctrl_rate_get storm_ctrl_rate_get;
+ hsl_rate_queue_egrl_set rate_queue_egrl_set;
+ hsl_rate_queue_egrl_get rate_queue_egrl_get;
+ hsl_rate_port_egrl_set rate_port_egrl_set;
+ hsl_rate_port_egrl_get rate_port_egrl_get;
+ hsl_rate_port_inrl_set rate_port_inrl_set;
+ hsl_rate_port_inrl_get rate_port_inrl_get;
+ hsl_rate_port_policer_set rate_port_policer_set;
+ hsl_rate_port_policer_get rate_port_policer_get;
+ hsl_rate_port_shaper_set rate_port_shaper_set;
+ hsl_rate_port_shaper_get rate_port_shaper_get;
+ hsl_rate_queue_shaper_set rate_queue_shaper_set;
+ hsl_rate_queue_shaper_get rate_queue_shaper_get;
+ hsl_rate_acl_policer_set rate_acl_policer_set;
+ hsl_rate_acl_policer_get rate_acl_policer_get;
+ hsl_rate_port_add_rate_byte_set rate_port_add_rate_byte_set;
+ hsl_rate_port_add_rate_byte_get rate_port_add_rate_byte_get;
+ hsl_rate_port_gol_flow_en_set rate_port_gol_flow_en_set;
+ hsl_rate_port_gol_flow_en_get rate_port_gol_flow_en_get;
+
+ /* Mirror */
+ hsl_mirr_analysis_port_set mirr_analysis_port_set;
+ hsl_mirr_analysis_port_get mirr_analysis_port_get;
+ hsl_mirr_port_in_set mirr_port_in_set;
+ hsl_mirr_port_in_get mirr_port_in_get;
+ hsl_mirr_port_eg_set mirr_port_eg_set;
+ hsl_mirr_port_eg_get mirr_port_eg_get;
+
+ /* Stp */
+ hsl_stp_port_state_set stp_port_state_set;
+ hsl_stp_port_state_get stp_port_state_get;
+
+ /* IGMP */
+ hsl_port_igmps_status_set port_igmps_status_set;
+ hsl_port_igmps_status_get port_igmps_status_get;
+ hsl_igmp_mld_cmd_set igmp_mld_cmd_set;
+ hsl_igmp_mld_cmd_get igmp_mld_cmd_get;
+ hsl_port_igmp_join_set port_igmp_join_set;
+ hsl_port_igmp_join_get port_igmp_join_get;
+ hsl_port_igmp_leave_set port_igmp_leave_set;
+ hsl_port_igmp_leave_get port_igmp_leave_get;
+ hsl_igmp_rp_set igmp_rp_set;
+ hsl_igmp_rp_get igmp_rp_get;
+ hsl_igmp_entry_creat_set igmp_entry_creat_set;
+ hsl_igmp_entry_creat_get igmp_entry_creat_get;
+ hsl_igmp_entry_static_set igmp_entry_static_set;
+ hsl_igmp_entry_static_get igmp_entry_static_get;
+ hsl_igmp_entry_leaky_set igmp_entry_leaky_set;
+ hsl_igmp_entry_leaky_get igmp_entry_leaky_get;
+ hsl_igmp_entry_v3_set igmp_entry_v3_set;
+ hsl_igmp_entry_v3_get igmp_entry_v3_get;
+ hsl_igmp_entry_queue_set igmp_entry_queue_set;
+ hsl_igmp_entry_queue_get igmp_entry_queue_get;
+ hsl_port_igmp_mld_learn_limit_set port_igmp_mld_learn_limit_set;
+ hsl_port_igmp_mld_learn_limit_get port_igmp_mld_learn_limit_get;
+ hsl_port_igmp_mld_learn_exceed_cmd_set port_igmp_mld_learn_exceed_cmd_set;
+ hsl_port_igmp_mld_learn_exceed_cmd_get port_igmp_mld_learn_exceed_cmd_get;
+ hsl_igmp_sg_entry_set igmp_sg_entry_set;
+ hsl_igmp_sg_entry_clear igmp_sg_entry_clear;
+ hsl_igmp_sg_entry_show igmp_sg_entry_show;
+
+ /* Leaky */
+ hsl_uc_leaky_mode_set uc_leaky_mode_set;
+ hsl_uc_leaky_mode_get uc_leaky_mode_get;
+ hsl_mc_leaky_mode_set mc_leaky_mode_set;
+ hsl_mc_leaky_mode_get mc_leaky_mode_get;
+ hsl_port_arp_leaky_set port_arp_leaky_set;
+ hsl_port_arp_leaky_get port_arp_leaky_get;
+ hsl_port_uc_leaky_set port_uc_leaky_set;
+ hsl_port_uc_leaky_get port_uc_leaky_get;
+ hsl_port_mc_leaky_set port_mc_leaky_set;
+ hsl_port_mc_leaky_get port_mc_leaky_get;
+
+ /* MIB API */
+ hsl_get_mib_info get_mib_info;
+ hsl_mib_status_set mib_status_set;
+ hsl_mib_status_get mib_status_get;
+ hsl_mib_port_flush_counters mib_port_flush_counters;
+ hsl_mib_cpukeep_set mib_cpukeep_set;
+ hsl_mib_cpukeep_get mib_cpukeep_get;
+
+
+ /* Acl */
+ hsl_acl_list_creat acl_list_creat;
+ hsl_acl_list_destroy acl_list_destroy;
+ hsl_acl_rule_add acl_rule_add;
+ hsl_acl_rule_delete acl_rule_delete;
+ hsl_acl_rule_query acl_rule_query;
+ hsl_acl_list_bind acl_list_bind;
+ hsl_acl_list_unbind acl_list_unbind;
+ hsl_acl_status_set acl_status_set;
+ hsl_acl_status_get acl_status_get;
+ hsl_acl_list_dump acl_list_dump;
+ hsl_acl_rule_dump acl_rule_dump;
+ hsl_acl_port_udf_profile_set acl_port_udf_profile_set;
+ hsl_acl_port_udf_profile_get acl_port_udf_profile_get;
+ hsl_acl_rule_active acl_rule_active;
+ hsl_acl_rule_deactive acl_rule_deactive;
+ hsl_acl_rule_src_filter_sts_set acl_rule_src_filter_sts_set;
+ hsl_acl_rule_src_filter_sts_get acl_rule_src_filter_sts_get;
+ hsl_acl_rule_get_offset acl_rule_get_offset;
+ hsl_acl_rule_sync_multi_portmap acl_rule_sync_multi_portmap;
+
+ /* LED */
+ hsl_led_ctrl_pattern_set led_ctrl_pattern_set;
+ hsl_led_ctrl_pattern_get led_ctrl_pattern_get;
+
+ /* CoSMap */
+ hsl_cosmap_dscp_to_pri_set cosmap_dscp_to_pri_set;
+ hsl_cosmap_dscp_to_pri_get cosmap_dscp_to_pri_get;
+ hsl_cosmap_dscp_to_dp_set cosmap_dscp_to_dp_set;
+ hsl_cosmap_dscp_to_dp_get cosmap_dscp_to_dp_get;
+ hsl_cosmap_up_to_pri_set cosmap_up_to_pri_set;
+ hsl_cosmap_up_to_pri_get cosmap_up_to_pri_get;
+ hsl_cosmap_up_to_dp_set cosmap_up_to_dp_set;
+ hsl_cosmap_up_to_dp_get cosmap_up_to_dp_get;
+ hsl_cosmap_pri_to_queue_set cosmap_pri_to_queue_set;
+ hsl_cosmap_pri_to_queue_get cosmap_pri_to_queue_get;
+ hsl_cosmap_pri_to_ehqueue_set cosmap_pri_to_ehqueue_set;
+ hsl_cosmap_pri_to_ehqueue_get cosmap_pri_to_ehqueue_get;
+ hsl_cosmap_egress_remark_set cosmap_egress_remark_set;
+ hsl_cosmap_egress_remark_get cosmap_egress_remark_get;
+
+ /* IP */
+ hsl_ip_host_add ip_host_add;
+ hsl_ip_host_del ip_host_del;
+ hsl_ip_host_get ip_host_get;
+ hsl_ip_host_next ip_host_next;
+ hsl_ip_host_counter_bind ip_host_counter_bind;
+ hsl_ip_host_pppoe_bind ip_host_pppoe_bind;
+ hsl_ip_pt_arp_learn_set ip_pt_arp_learn_set;
+ hsl_ip_pt_arp_learn_get ip_pt_arp_learn_get;
+ hsl_ip_arp_learn_set ip_arp_learn_set;
+ hsl_ip_arp_learn_get ip_arp_learn_get;
+ hsl_ip_source_guard_set ip_source_guard_set;
+ hsl_ip_source_guard_get ip_source_guard_get;
+ hsl_ip_unk_source_cmd_set ip_unk_source_cmd_set;
+ hsl_ip_unk_source_cmd_get ip_unk_source_cmd_get;
+ hsl_ip_arp_guard_set ip_arp_guard_set;
+ hsl_ip_arp_guard_get ip_arp_guard_get;
+ hsl_arp_unk_source_cmd_set arp_unk_source_cmd_set;
+ hsl_arp_unk_source_cmd_get arp_unk_source_cmd_get;
+ hsl_ip_route_status_set ip_route_status_set;
+ hsl_ip_route_status_get ip_route_status_get;
+ hsl_ip_intf_entry_add ip_intf_entry_add;
+ hsl_ip_intf_entry_del ip_intf_entry_del;
+ hsl_ip_intf_entry_next ip_intf_entry_next;
+ hsl_ip_age_time_set ip_age_time_set;
+ hsl_ip_age_time_get ip_age_time_get;
+ hsl_ip_wcmp_hash_mode_set ip_wcmp_hash_mode_set;
+ hsl_ip_wcmp_hash_mode_get ip_wcmp_hash_mode_get;
+
+ /* NAT */
+ hsl_nat_add nat_add;
+ hsl_nat_del nat_del;
+ hsl_nat_get nat_get;
+ hsl_nat_next nat_next;
+ hsl_nat_counter_bind nat_counter_bind;
+ hsl_napt_add napt_add;
+ hsl_napt_del napt_del;
+ hsl_napt_get napt_get;
+ hsl_napt_next napt_next;
+ hsl_napt_counter_bind napt_counter_bind;
+ hsl_nat_status_set nat_status_set;
+ hsl_nat_status_get nat_status_get;
+ hsl_nat_hash_mode_set nat_hash_mode_set;
+ hsl_nat_hash_mode_get nat_hash_mode_get;
+ hsl_napt_status_set napt_status_set;
+ hsl_napt_status_get napt_status_get;
+ hsl_napt_mode_set napt_mode_set;
+ hsl_napt_mode_get napt_mode_get;
+ hsl_nat_prv_base_addr_set nat_prv_base_addr_set;
+ hsl_nat_prv_base_addr_get nat_prv_base_addr_get;
+ hsl_nat_prv_base_mask_set nat_prv_base_mask_set;
+ hsl_nat_prv_base_mask_get nat_prv_base_mask_get;
+ hsl_nat_prv_addr_mode_set nat_prv_addr_mode_set;
+ hsl_nat_prv_addr_mode_get nat_prv_addr_mode_get;
+ hsl_nat_pub_addr_add nat_pub_addr_add;
+ hsl_nat_pub_addr_del nat_pub_addr_del;
+ hsl_nat_pub_addr_next nat_pub_addr_next;
+ hsl_nat_unk_session_cmd_set nat_unk_session_cmd_set;
+ hsl_nat_unk_session_cmd_get nat_unk_session_cmd_get;
+
+ /* SEC */
+ hsl_sec_norm_item_set sec_norm_item_set;
+ hsl_sec_norm_item_get sec_norm_item_get;
+
+ /* Trunk */
+ hsl_trunk_group_set trunk_group_set;
+ hsl_trunk_group_get trunk_group_get;
+ hsl_trunk_hash_mode_set trunk_hash_mode_set;
+ hsl_trunk_hash_mode_get trunk_hash_mode_get;
+ hsl_trunk_manipulate_sa_set trunk_manipulate_sa_set;
+ hsl_trunk_manipulate_sa_get trunk_manipulate_sa_get;
+
+ /* Interface Control */
+ hsl_interface_mac_mode_set interface_mac_mode_set;
+ hsl_interface_mac_mode_get interface_mac_mode_get;
+ hsl_port_3az_status_set port_3az_status_set;
+ hsl_port_3az_status_get port_3az_status_get;
+ hsl_interface_phy_mode_set interface_phy_mode_set;
+ hsl_interface_phy_mode_get interface_phy_mode_get;
+ hsl_interface_fx100_ctrl_set interface_fx100_ctrl_set;
+ hsl_interface_fx100_ctrl_get interface_fx100_ctrl_get;
+ hsl_interface_fx100_status_get interface_fx100_status_get;
+ hsl_interface_mac06_exch_set interface_mac06_exch_set;
+ hsl_interface_mac06_exch_get interface_mac06_exch_get;
+#endif
+#endif
+
+ /* REG Access */
+ hsl_phy_get phy_get;
+ hsl_phy_set phy_set;
+ hsl_reg_get reg_get;
+ hsl_reg_set reg_set;
+ hsl_reg_field_get reg_field_get;
+ hsl_reg_field_set reg_field_set;
+ hsl_reg_entries_get reg_entries_get;
+ hsl_reg_entries_set reg_entries_set;
+
+ /*INIT*/
+ hsl_dev_reset dev_reset;
+ hsl_dev_clean dev_clean;
+ hsl_dev_access_set dev_access_set;
+ } hsl_api_t;
+
+ hsl_api_t *
+ hsl_api_ptr_get(a_uint32_t dev_id);
+
+ sw_error_t
+ hsl_api_init(a_uint32_t dev_id);
+
+#if defined(SW_API_LOCK) && (!defined(HSL_STANDALONG))
+ extern aos_lock_t sw_hsl_api_lock;
+#define FAL_API_LOCK aos_lock(&sw_hsl_api_lock)
+#define FAL_API_UNLOCK aos_unlock(&sw_hsl_api_lock)
+#else
+#define FAL_API_LOCK
+#define FAL_API_UNLOCK
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SW_API_H */
diff --git a/include/hsl/hsl_dev.h b/include/hsl/hsl_dev.h
new file mode 100644
index 0000000..317f15b
--- /dev/null
+++ b/include/hsl/hsl_dev.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_DEV_H
+#define _HSL_DEV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "hsl_api.h"
+#include "ssdk_init.h"
+
+#define HSL_DEV_ID_CHECK(dev_id) \
+do { \
+ if (dev_id >= SW_MAX_NR_DEV) \
+ return SW_OUT_OF_RANGE; \
+} while (0)
+
+ typedef struct
+ {
+ a_uint32_t dev_id;
+ a_uint8_t cpu_port_nr;
+ a_uint8_t nr_ports;
+ a_uint8_t nr_phy;
+ a_uint8_t nr_queue;
+ a_uint16_t nr_vlans;
+ a_bool_t hw_vlan_query;
+ hsl_acl_func_t acl_func;
+ hsl_init_mode cpu_mode;
+ } hsl_dev_t;
+
+ hsl_dev_t *hsl_dev_ptr_get(a_uint32_t dev_id);
+ hsl_acl_func_t *hsl_acl_ptr_get(a_uint32_t dev_id);
+
+ sw_error_t
+ hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+ sw_error_t
+ hsl_dev_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode,
+ hsl_access_mode reg_mode);
+
+ sw_error_t
+ hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg);
+
+ sw_error_t
+ hsl_dev_cleanup(void);
+
+ sw_error_t
+ hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _HSL_DEV_H */
diff --git a/include/hsl/hsl_lock.h b/include/hsl/hsl_lock.h
new file mode 100644
index 0000000..bbf04ff
--- /dev/null
+++ b/include/hsl/hsl_lock.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_LOCK_H_
+#define _HSL_LOCK_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+ sw_error_t hsl_api_lock_init(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /*_HSL_LOCK_H_ */
diff --git a/include/hsl/hsl_port_prop.h b/include/hsl/hsl_port_prop.h
new file mode 100644
index 0000000..88633c3
--- /dev/null
+++ b/include/hsl/hsl_port_prop.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _HSL_PORT_PROPERTY_H_
+#define _HSL_PORT_PROPERTY_H_
+
+#ifdef __cplusplus
+extern "c" {
+#endif
+
+ typedef enum {
+ HSL_PP_PHY = 0, /* setting concerning phy */
+ HSL_PP_INCL_CPU, /* setting may include cpu port */
+ HSL_PP_EXCL_CPU, /* setting exclude cpu port */
+ HSL_PP_BUTT
+ }
+ hsl_port_prop_t;
+
+ a_bool_t
+ hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id,
+ hsl_port_prop_t p_type);
+
+ a_bool_t
+ hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap,
+ hsl_port_prop_t p_type);
+ a_bool_t
+ hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id);
+
+ a_bool_t
+ hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap);
+
+ sw_error_t
+ hsl_port_prop_portmap_get(a_uint32_t dev_id, fal_pbmp_t port_bitmap);
+
+ sw_error_t
+ hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id,
+ hsl_port_prop_t p_type);
+
+ sw_error_t
+ hsl_port_prop_portmap_set(a_uint32_t dev_id, fal_port_t port_id);
+
+ sw_error_t
+ hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id,
+ hsl_port_prop_t p_type);
+
+ sw_error_t
+ hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *phy_id);
+
+ sw_error_t
+ hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t phy_id);
+
+ sw_error_t
+ hsl_port_prop_init_by_dev(a_uint32_t dev_id);
+
+ sw_error_t
+ hsl_port_prop_init(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /*_HSL_PORT_PROPERTY_H_ */
diff --git a/include/hsl/hsl_shared_api.h b/include/hsl/hsl_shared_api.h
new file mode 100644
index 0000000..c817d53
--- /dev/null
+++ b/include/hsl/hsl_shared_api.h
@@ -0,0 +1,255 @@
+#ifndef _HSL_SHARED_API_H
+#define _HSL_SHARED_API_H
+
+#include "hsl.h"
+#include "hsl_api.h"
+#include "ssdk_init.h"
+
+extern ssdk_chip_type SSDK_CURRENT_CHIP_TYPE; /*running chip type*/
+
+#if !defined (HSL_STANDALONG)
+/*NAT API*/
+#define NAPT_ADD hsl_api_ptr_get(0)->napt_add
+#define NAT_PUB_ADDR_ADD hsl_api_ptr_get(0)->nat_pub_addr_add
+#define NAPT_NEXT hsl_api_ptr_get(0)->napt_next
+#define NAT_PRV_BASE_ADDR_SET hsl_api_ptr_get(0)->nat_prv_base_addr_set
+#define NAT_PRV_BASE_MASK_SET hsl_api_ptr_get(0)->nat_prv_base_mask_set
+#define NAPT_DEL hsl_api_ptr_get(0)->napt_del
+#define NAT_DEL hsl_api_ptr_get(0)->nat_del
+#define NAT_PUB_ADDR_DEL hsl_api_ptr_get(0)->nat_pub_addr_del
+#define NAT_ADD hsl_api_ptr_get(0)->nat_add
+#define NAT_PRV_ADDR_MODE_GET hsl_api_ptr_get(0)->nat_prv_addr_mode_get
+
+/*IP API*/
+#define IP_INTF_ENTRY_ADD hsl_api_ptr_get(0)->ip_intf_entry_add
+#define IP_HOST_ADD hsl_api_ptr_get(0)->ip_host_add
+#define IP_HOST_DEL hsl_api_ptr_get(0)->ip_host_del
+#define IP_HOST_GET hsl_api_ptr_get(0)->ip_host_get
+#define IP_HOST_NEXT hsl_api_ptr_get(0)->ip_host_next
+#define IP_INTF_ENTRY_DEL hsl_api_ptr_get(0)->ip_intf_entry_del
+#define IP_HOST_PPPOE_BIND hsl_api_ptr_get(0)->ip_host_pppoe_bind
+#define IP_ROUTE_STATUS_SET hsl_api_ptr_get(0)->ip_route_status_set
+
+/*MISC API*/
+#define PPPOE_STATUS_GET hsl_api_ptr_get(0)->pppoe_status_get
+#define PPPOE_STATUS_SET hsl_api_ptr_get(0)->pppoe_status_set
+#define PPPOE_SESSION_ID_SET hsl_api_ptr_get(0)->pppoe_session_id_set
+#define PPPOE_SESSION_TABLE_ADD hsl_api_ptr_get(0)->pppoe_session_table_add
+#define PPPOE_SESSION_TABLE_DEL hsl_api_ptr_get(0)->pppoe_session_table_del
+#define PORT_BC_FILTER_SET hsl_api_ptr_get(0)->port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET hsl_api_ptr_get(0)->port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET hsl_api_ptr_get(0)->port_unk_uc_filter_set
+#define PORT_RXMAC_STATUS_SET hsl_api_ptr_get(0)->port_rxmac_status_set
+#define MISC_ARP_CMD_SET hsl_api_ptr_get(0)->arp_cmd_set
+#define CPU_VID_EN_SET hsl_api_ptr_get(0)->cpu_vid_en_set
+#define RTD_PPPOE_EN_SET hsl_api_ptr_get(0)->rtd_pppoe_en_set
+#define PORT_ARP_ACK_STATUS_SET hsl_api_ptr_get(0)->port_arp_ack_status_set
+#define CPU_PORT_STATUS_SET hsl_api_ptr_get(0)->cpu_port_status_set
+
+/*ACL API*/
+#define ACL_RULE_ADD hsl_api_ptr_get(0)->acl_rule_add
+#define ACL_RULE_DEL hsl_api_ptr_get(0)->acl_rule_delete
+#define ACL_LIST_CREATE hsl_api_ptr_get(0)->acl_list_creat
+#define ACL_LIST_DESTROY hsl_api_ptr_get(0)->acl_list_destroy
+#define ACL_LIST_BIND hsl_api_ptr_get(0)->acl_list_bind
+#define ACL_LIST_UNBIND hsl_api_ptr_get(0)->acl_list_unbind
+#define ACL_RULE_GET_OFFSET hsl_api_ptr_get(0)->acl_rule_get_offset
+#define ACL_RULE_QUERY hsl_api_ptr_get(0)->acl_rule_query
+#define ACL_RULE_SYNC_MULTI_PORTMAP hsl_api_ptr_get(0)->acl_rule_sync_multi_portmap
+#define ACL_STATUS_GET hsl_api_ptr_get(0)->acl_status_get
+#define ACL_STATUS_SET hsl_api_ptr_get(0)->acl_status_set
+#define ACL_PORT_UDF_PROFILE_SET hsl_api_ptr_get(0)->acl_port_udf_profile_set
+
+/*VLAN API */
+#define VLAN_CREATE hsl_api_ptr_get(0)->vlan_creat
+#define VLAN_DEL hsl_api_ptr_get(0)->vlan_delete
+#define VLAN_FIND hsl_api_ptr_get(0)->vlan_find
+#define VLAN_MEMBER_ADD hsl_api_ptr_get(0)->vlan_member_add
+
+/*RATE API*/
+#define RATE_ACL_POLICER_SET hsl_api_ptr_get(0)->rate_acl_policer_set
+
+/*MIB API*/
+#define MIB_STATUS_SET hsl_api_ptr_get(0)->mib_status_set
+#define GET_MIB_INFO hsl_api_ptr_get(0)->get_mib_info
+
+/* PORTVLAN API */
+#define PORTVLAN_ROUTE_DEFV_SET hsl_api_ptr_get(0)->port_route_defv_set
+#define NETISOLATE_SET hsl_api_ptr_get(0)->netisolate_set
+
+/* PORT_CTRL API */
+#define HEADER_TYPE_SET hsl_api_ptr_get(0)->header_type_set
+#define PORT_TXHDR_MODE_SET hsl_api_ptr_get(0)->port_txhdr_mode_set
+#define PORT_TXMAC_STATUS_SET hsl_api_ptr_get(0)->port_txmac_status_set
+
+#elif defined(ISISC)
+/* NAT API*/
+#include "isisc_nat.h"
+#define NAPT_ADD isisc_napt_add
+#define NAT_PUB_ADDR_ADD isisc_nat_pub_addr_add
+#define NAPT_NEXT isisc_napt_next
+#define NAT_PRV_BASE_ADDR_SET isisc_nat_prv_base_addr_set
+#define NAT_PRV_BASE_MASK_SET isisc_nat_prv_base_mask_set
+#define NAPT_DEL isisc_napt_del
+#define NAT_DEL isisc_nat_del
+#define NAT_PUB_ADDR_DEL isisc_nat_pub_addr_del
+#define NAT_ADD isisc_nat_add
+#define NAT_PRV_ADDR_MODE_GET isisc_nat_prv_addr_mode_get
+
+/*IP API*/
+#include "isisc_ip.h"
+#define IP_INTF_ENTRY_ADD isisc_ip_intf_entry_add
+#define IP_HOST_ADD isisc_ip_host_add
+#define IP_HOST_DEL isisc_ip_host_del
+#define IP_HOST_GET isisc_ip_host_get
+#define IP_HOST_NEXT isisc_ip_host_next
+#define IP_INTF_ENTRY_DEL isisc_ip_intf_entry_del
+#define IP_HOST_PPPOE_BIND isisc_ip_host_pppoe_bind
+#define IP_ROUTE_STATUS_SET isisc_ip_route_status_set
+
+/*MISC API*/
+#include "isisc_misc.h"
+#define PPPOE_STATUS_GET isisc_pppoe_status_get
+#define PPPOE_STATUS_SET isisc_pppoe_status_set
+#define PPPOE_SESSION_ID_SET isisc_pppoe_session_id_set
+#define PPPOE_SESSION_TABLE_ADD isisc_pppoe_session_table_add
+#define PPPOE_SESSION_TABLE_DEL isisc_pppoe_session_table_del
+#define PORT_BC_FILTER_SET isisc_port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET isisc_port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET isisc_port_unk_uc_filter_set
+#define PORT_RXMAC_STATUS_SET isisc_port_rxmac_status_set
+#define MISC_ARP_CMD_SET isisc_arp_cmd_set
+#define MISC_ARP_SP_NOT_FOUND_SET isisc_arp_unk_source_cmd_set
+#define MISC_ARP_GUARD_SET isisc_ip_arp_guard_set
+#define CPU_VID_EN_SET isisc_cpu_vid_en_set
+#define RTD_PPPOE_EN_SET isisc_rtd_pppoe_en_set
+#define PORT_ARP_ACK_STATUS_SET isisc_port_arp_ack_status_set
+#define CPU_PORT_STATUS_SET isisc_cpu_port_status_set
+
+/*ACL API*/
+#include "isisc_acl.h"
+#define ACL_RULE_ADD isisc_acl_rule_add
+#define ACL_RULE_DEL isisc_acl_rule_delete
+#define ACL_LIST_CREATE isisc_acl_list_creat
+#define ACL_LIST_DESTROY isisc_acl_list_destroy
+#define ACL_LIST_BIND isisc_acl_list_bind
+#define ACL_LIST_UNBIND isisc_acl_list_unbind
+#define ACL_RULE_GET_OFFSET isisc_acl_rule_get_offset
+#define ACL_RULE_QUERY isisc_acl_rule_query
+#define ACL_RULE_SYNC_MULTI_PORTMAP isisc_acl_rule_sync_multi_portmap
+#define ACL_STATUS_GET isisc_acl_status_get
+#define ACL_STATUS_SET isisc_acl_status_set
+#define ACL_PORT_UDF_PROFILE_SET isisc_acl_port_udf_profile_set
+
+/*VLAN API */
+#include "isisc_vlan.h"
+#define VLAN_CREATE isisc_vlan_create
+#define VLAN_DEL isisc_vlan_delete
+#define VLAN_FIND isisc_vlan_find
+#define VLAN_MEMBER_ADD isisc_vlan_member_add
+
+/*RATE API*/
+#include "isisc_rate.h"
+#define RATE_ACL_POLICER_SET isisc_rate_acl_policer_set
+
+/*MIB API*/
+#include "isisc_mib.h"
+#define MIB_STATUS_SET isisc_mib_status_set
+#define GET_MIB_INFO isisc_get_mib_info
+
+/* PORTVLAN API */
+#include "isisc_portvlan.h"
+#define PORTVLAN_ROUTE_DEFV_SET isisc_port_route_defv_set
+#define NETISOLATE_SET isisc_netisolate_set
+
+/* PORT_CTRL API */
+#include "isisc_port_ctrl.h"
+#define HEADER_TYPE_SET isisc_header_type_set
+#define PORT_TXHDR_MODE_SET isisc_port_txhdr_mode_set
+#define PORT_TXMAC_STATUS_SET isisc_port_txmac_status_set
+
+#elif defined(ISIS)
+/* NAT API*/
+#include "isis_nat.h"
+#define NAPT_ADD isis_napt_add
+#define NAT_PUB_ADDR_ADD isis_nat_pub_addr_add
+#define NAPT_NEXT isis_napt_next
+#define NAT_PRV_BASE_ADDR_SET isis_nat_prv_base_addr_set
+#define NAT_PRV_BASE_MASK_SET isis_nat_prv_base_mask_set
+#define NAPT_DEL isis_napt_del
+#define NAT_DEL isis_nat_del
+#define NAT_PUB_ADDR_DEL isis_nat_pub_addr_del
+#define NAT_ADD isis_nat_add
+#define NAT_PRV_ADDR_MODE_GET isis_nat_prv_addr_mode_get
+
+/*IP API*/
+#include "isis_ip.h"
+#define IP_INTF_ENTRY_ADD isis_ip_intf_entry_add
+#define IP_HOST_ADD isis_ip_host_add
+#define IP_HOST_DEL isis_ip_host_del
+#define IP_HOST_GET isis_ip_host_get
+#define IP_HOST_NEXT isis_ip_host_next
+#define IP_INTF_ENTRY_DEL isis_ip_intf_entry_del
+#define IP_HOST_PPPOE_BIND isis_ip_host_pppoe_bind
+#define IP_ROUTE_STATUS_SET isis_ip_route_status_set
+
+/*MISC API*/
+#include "isis_misc.h"
+#define PPPOE_STATUS_GET isis_pppoe_status_get
+#define PPPOE_STATUS_SET isis_pppoe_status_set
+#define PPPOE_SESSION_ID_SET isis_pppoe_session_id_set
+#define PPPOE_SESSION_TABLE_ADD isis_pppoe_session_table_add
+#define PPPOE_SESSION_TABLE_DEL isis_pppoe_session_table_del
+#define PORT_BC_FILTER_SET isis_port_bc_filter_set
+#define PORT_UNK_MC_FILTER_SET isis_port_unk_mc_filter_set
+#define PORT_UNK_UC_FILTER_SET isis_port_unk_uc_filter_set
+#define PORT_RXMAC_STATUS_SET isis_port_rxmac_status_set
+#define MISC_ARP_CMD_SET isis_arp_cmd_set
+#define CPU_VID_EN_SET isis_cpu_vid_en_set
+#define RTD_PPPOE_EN_SET isis_rtd_pppoe_en_set
+#define PORT_ARP_ACK_STATUS_SET isis_port_arp_ack_status_set
+#define CPU_PORT_STATUS_SET isis_cpu_port_status_set
+
+/*ACL API*/
+#include "isis_acl.h"
+#define ACL_RULE_ADD isis_acl_rule_add
+#define ACL_RULE_DEL isis_acl_rule_delete
+#define ACL_LIST_CREATE isis_acl_list_creat
+#define ACL_LIST_DESTROY isis_acl_list_destroy
+#define ACL_LIST_BIND isis_acl_list_bind
+#define ACL_LIST_UNBIND isis_acl_list_unbind
+#define ACL_RULE_GET_OFFSET isis_acl_rule_get_offset
+#define ACL_RULE_QUERY isis_acl_rule_query
+#define ACL_RULE_SYNC_MULTI_PORTMAP isis_acl_rule_sync_multi_portmap
+#define ACL_STATUS_GET isis_acl_status_get
+#define ACL_STATUS_SET isis_acl_status_set
+#define ACL_PORT_UDF_PROFILE_SET isis_acl_port_udf_profile_set
+
+/*VLAN API */
+#include "isis_vlan.h"
+#define VLAN_CREATE isis_vlan_create
+#define VLAN_DEL isis_vlan_delete
+#define VLAN_FIND isis_vlan_find
+#define VLAN_MEMBER_ADD isis_vlan_member_add
+
+/*RATE API*/
+#include "isis_rate.h"
+#define RATE_ACL_POLICER_SET isis_rate_acl_policer_set
+
+/*MIB API*/
+#include "isis_mib.h"
+#define MIB_STATUS_SET isis_mib_status_set
+#define GET_MIB_INFO isis_get_mib_info
+
+/* PORTVLAN API */
+#include "isis_portvlan.h"
+#define PORTVLAN_ROUTE_DEFV_SET isis_port_route_defv_set
+
+/* PORT_CTRL API */
+#include "isis_port_ctrl.h"
+#define HEADER_TYPE_SET isis_header_type_set
+#define PORT_TXHDR_MODE_SET isis_port_txhdr_mode_set
+#define PORT_TXMAC_STATUS_SET isis_port_txmac_status_set
+#endif
+
+#endif
diff --git a/include/hsl/isis/isis_acl.h b/include/hsl/isis/isis_acl.h
new file mode 100644
index 0000000..5f92672
--- /dev/null
+++ b/include/hsl/isis/isis_acl.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_acl ISIS_ACL
+ * @{
+ */
+#ifndef _ISIS_ACL_H_
+#define _ISIS_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+ sw_error_t isis_acl_init(a_uint32_t dev_id);
+
+ sw_error_t isis_acl_reset(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define ISIS_ACL_INIT(rv, dev_id) \
+ { \
+ rv = isis_acl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISIS_ACL_RESET(rv, dev_id) \
+ { \
+ rv = isis_acl_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_ACL_INIT(rv, dev_id)
+#define ISIS_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+ HSL_LOCAL a_uint32_t
+ isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_list_dump(a_uint32_t dev_id);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_dump(a_uint32_t dev_id);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t offset, a_uint32_t length);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t * offset, a_uint32_t * length);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ HSL_LOCAL sw_error_t
+ isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isis/isis_api.h b/include/hsl/isis/isis_api.h
new file mode 100644
index 0000000..cc75216
--- /dev/null
+++ b/include/hsl/isis/isis_api.h
@@ -0,0 +1,972 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISIS_API_H_
+#define _ISIS_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, isis_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, isis_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, isis_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, isis_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, isis_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, isis_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, isis_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, isis_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, isis_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isis_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isis_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isis_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isis_port_flowctrl_forcemode_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, isis_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, isis_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, isis_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, isis_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, isis_port_cdt), \
+ SW_API_DEF(SW_API_PT_TXHDR_SET, isis_port_txhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_TXHDR_GET, isis_port_txhdr_mode_get), \
+ SW_API_DEF(SW_API_PT_RXHDR_SET, isis_port_rxhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_RXHDR_GET, isis_port_rxhdr_mode_get), \
+ SW_API_DEF(SW_API_HEADER_TYPE_SET, isis_header_type_set), \
+ SW_API_DEF(SW_API_HEADER_TYPE_GET, isis_header_type_get), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_SET, isis_port_txmac_status_set), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_GET, isis_port_txmac_status_get), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_SET, isis_port_rxmac_status_set), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_GET, isis_port_rxmac_status_get), \
+ SW_API_DEF(SW_API_TXFC_STATUS_SET, isis_port_txfc_status_set), \
+ SW_API_DEF(SW_API_TXFC_STATUS_GET, isis_port_txfc_status_get), \
+ SW_API_DEF(SW_API_RXFC_STATUS_SET, isis_port_rxfc_status_set), \
+ SW_API_DEF(SW_API_RXFC_STATUS_GET, isis_port_rxfc_status_get), \
+ SW_API_DEF(SW_API_BP_STATUS_SET, isis_port_bp_status_set), \
+ SW_API_DEF(SW_API_BP_STATUS_GET, isis_port_bp_status_get), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_SET, isis_port_link_forcemode_set), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_GET, isis_port_link_forcemode_get), \
+ SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isis_port_link_status_get), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isis_port_mac_loopback_set), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isis_port_mac_loopback_get),
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT) \
+ SW_API_DESC(SW_API_PT_TXHDR_SET) \
+ SW_API_DESC(SW_API_PT_TXHDR_GET) \
+ SW_API_DESC(SW_API_PT_RXHDR_SET) \
+ SW_API_DESC(SW_API_PT_RXHDR_GET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_BP_STATUS_SET) \
+ SW_API_DESC(SW_API_BP_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+ SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, isis_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, isis_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_FIND, isis_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, isis_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, isis_vlan_entry_append), \
+ SW_API_DEF(SW_API_VLAN_FLUSH, isis_vlan_flush), \
+ SW_API_DEF(SW_API_VLAN_FID_SET, isis_vlan_fid_set), \
+ SW_API_DEF(SW_API_VLAN_FID_GET, isis_vlan_fid_get), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isis_vlan_member_add), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isis_vlan_member_del), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isis_vlan_learning_state_set), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isis_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND) \
+ SW_API_DESC(SW_API_VLAN_FLUSH) \
+ SW_API_DESC(SW_API_VLAN_FID_SET) \
+ SW_API_DESC(SW_API_VLAN_FID_GET) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, isis_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, isis_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, isis_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, isis_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isis_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isis_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isis_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isis_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isis_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isis_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isis_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isis_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isis_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isis_nestvlan_tpid_get), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isis_port_invlan_mode_set), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isis_port_invlan_mode_get), \
+ SW_API_DEF(SW_API_PT_TLS_SET, isis_port_tls_set), \
+ SW_API_DEF(SW_API_PT_TLS_GET, isis_port_tls_get), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isis_port_pri_propagation_set), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isis_port_pri_propagation_get), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_SET, isis_port_default_svid_set), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_GET, isis_port_default_svid_get), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_SET, isis_port_default_cvid_set), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_GET, isis_port_default_cvid_get), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isis_port_vlan_propagation_set), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isis_port_vlan_propagation_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isis_port_vlan_trans_add), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isis_port_vlan_trans_del), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isis_port_vlan_trans_get), \
+ SW_API_DEF(SW_API_QINQ_MODE_SET, isis_qinq_mode_set), \
+ SW_API_DEF(SW_API_QINQ_MODE_GET, isis_qinq_mode_get), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isis_port_qinq_role_set), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isis_port_qinq_role_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isis_port_vlan_trans_iterate), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isis_port_mac_vlan_xlt_set), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isis_port_mac_vlan_xlt_get),
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \
+ SW_API_DESC(SW_API_PT_TLS_SET) \
+ SW_API_DESC(SW_API_PT_TLS_GET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_GET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \
+ SW_API_DESC(SW_API_QINQ_MODE_SET) \
+ SW_API_DESC(SW_API_QINQ_MODE_GET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, isis_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, isis_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,isis_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, isis_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIND, isis_fdb_find), \
+ SW_API_DEF(SW_API_FDB_EXTEND_NEXT, isis_fdb_extend_next), \
+ SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isis_fdb_extend_first), \
+ SW_API_DEF(SW_API_FDB_TRANSFER, isis_fdb_transfer), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, isis_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, isis_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, isis_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, isis_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, isis_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, isis_fdb_age_time_get), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, isis_port_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, isis_port_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, isis_port_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, isis_port_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, isis_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, isis_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, isis_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, isis_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_RESV_ADD, isis_fdb_resv_add), \
+ SW_API_DEF(SW_API_FDB_RESV_DEL, isis_fdb_resv_del), \
+ SW_API_DEF(SW_API_FDB_RESV_FIND, isis_fdb_resv_find), \
+ SW_API_DEF(SW_API_FDB_RESV_ITERATE, isis_fdb_resv_iterate), \
+ SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isis_fdb_extend_first), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, isis_fdb_port_learn_static_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, isis_fdb_port_learn_static_get), \
+ SW_API_DEF(SW_API_FDB_PORT_ADD, isis_fdb_port_add), \
+ SW_API_DEF(SW_API_FDB_PORT_DEL, isis_fdb_port_del),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \
+ SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+ SW_API_DESC(SW_API_FDB_TRANSFER) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_RESV_ADD) \
+ SW_API_DESC(SW_API_FDB_RESV_DEL) \
+ SW_API_DESC(SW_API_FDB_RESV_FIND) \
+ SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+ SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+ SW_API_DESC(SW_API_FDB_PORT_ADD) \
+ SW_API_DESC(SW_API_FDB_PORT_DEL)
+
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_ACL
+#define ACL_API \
+ SW_API_DEF(SW_API_ACL_LIST_CREAT, isis_acl_list_creat), \
+ SW_API_DEF(SW_API_ACL_LIST_DESTROY, isis_acl_list_destroy), \
+ SW_API_DEF(SW_API_ACL_RULE_ADD, isis_acl_rule_add), \
+ SW_API_DEF(SW_API_ACL_RULE_DELETE, isis_acl_rule_delete), \
+ SW_API_DEF(SW_API_ACL_RULE_QUERY, isis_acl_rule_query), \
+ SW_API_DEF(SW_API_ACL_LIST_BIND, isis_acl_list_bind), \
+ SW_API_DEF(SW_API_ACL_LIST_UNBIND, isis_acl_list_unbind), \
+ SW_API_DEF(SW_API_ACL_STATUS_SET, isis_acl_status_set), \
+ SW_API_DEF(SW_API_ACL_STATUS_GET, isis_acl_status_get), \
+ SW_API_DEF(SW_API_ACL_LIST_DUMP, isis_acl_list_dump), \
+ SW_API_DEF(SW_API_ACL_RULE_DUMP, isis_acl_rule_dump), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isis_acl_port_udf_profile_set), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isis_acl_port_udf_profile_get), \
+ SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isis_acl_rule_active), \
+ SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isis_acl_rule_deactive),\
+ SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isis_acl_rule_get_offset),
+
+#define ACL_API_PARAM \
+ SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+ SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+ SW_API_DESC(SW_API_ACL_RULE_ADD) \
+ SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+ SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+ SW_API_DESC(SW_API_ACL_LIST_BIND) \
+ SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+ SW_API_DESC(SW_API_ACL_STATUS_SET) \
+ SW_API_DESC(SW_API_ACL_STATUS_GET) \
+ SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+ SW_API_DESC(SW_API_ACL_RULE_DUMP) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \
+ SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \
+ SW_API_DESC(SW_API_ACL_RULE_DEACTIVE)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isis_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isis_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isis_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isis_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isis_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isis_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isis_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isis_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isis_qos_port_rx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isis_qos_port_rx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, isis_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, isis_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isis_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isis_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isis_qos_port_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isis_qos_port_sch_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isis_qos_port_default_spri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isis_qos_port_default_spri_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isis_qos_port_default_cpri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isis_qos_port_default_cpri_get), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isis_qos_queue_remark_table_set), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isis_qos_queue_remark_table_get),
+
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isis_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isis_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isis_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isis_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isis_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isis_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isis_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isis_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, isis_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, isis_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isis_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isis_igmp_mld_entry_creat_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isis_igmp_mld_entry_static_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isis_igmp_mld_entry_static_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isis_igmp_mld_entry_leaky_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isis_igmp_mld_entry_leaky_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isis_igmp_mld_entry_v3_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isis_igmp_mld_entry_v3_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isis_igmp_mld_entry_queue_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isis_igmp_mld_entry_queue_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, isis_port_igmp_mld_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, isis_port_igmp_mld_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, isis_port_igmp_mld_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, isis_port_igmp_mld_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, isis_igmp_sg_entry_set), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, isis_igmp_sg_entry_clear), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, isis_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isis_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isis_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isis_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isis_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isis_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isis_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isis_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isis_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isis_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isis_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isis_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isis_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isis_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isis_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isis_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isis_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isis_rate_port_policer_set), \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isis_rate_port_policer_get), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isis_rate_port_shaper_set), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isis_rate_port_shaper_get), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isis_rate_queue_shaper_set), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isis_rate_queue_shaper_get), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isis_rate_acl_policer_set), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isis_rate_acl_policer_get), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isis_rate_port_add_rate_byte_set), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isis_rate_port_add_rate_byte_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, isis_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, isis_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, isis_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, isis_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, isis_mib_status_get),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isis_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isis_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isis_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isis_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isis_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isis_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_SET, isis_port_bc_filter_set), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_GET, isis_port_bc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isis_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isis_cpu_port_status_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, isis_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, isis_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, isis_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, isis_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, isis_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, isis_port_dhcp_get), \
+ SW_API_DEF(SW_API_ARP_CMD_SET, isis_arp_cmd_set), \
+ SW_API_DEF(SW_API_ARP_CMD_GET, isis_arp_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_CMD_SET, isis_eapol_cmd_set), \
+ SW_API_DEF(SW_API_EAPOL_CMD_GET, isis_eapol_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_SET, isis_eapol_status_set), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_GET, isis_eapol_status_get), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_SET, isis_ripv1_status_set), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_GET, isis_ripv1_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isis_port_arp_req_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isis_port_arp_req_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isis_port_arp_ack_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isis_port_arp_ack_status_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isis_pppoe_session_table_add), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isis_pppoe_session_table_del), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isis_pppoe_session_table_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isis_pppoe_session_id_set), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isis_pppoe_session_id_get), \
+ SW_API_DEF(SW_API_INTR_MASK_SET, isis_intr_mask_set), \
+ SW_API_DEF(SW_API_INTR_MASK_GET, isis_intr_mask_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_GET, isis_intr_status_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isis_intr_status_clear), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isis_intr_port_link_mask_set), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isis_intr_port_link_mask_get), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isis_intr_port_link_status_get),
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET) \
+ SW_API_DESC(SW_API_ARP_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_GET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+ SW_API_DESC(SW_API_INTR_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, isis_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, isis_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isis_cosmap_dscp_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isis_cosmap_dscp_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isis_cosmap_dscp_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isis_cosmap_dscp_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isis_cosmap_up_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isis_cosmap_up_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isis_cosmap_up_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isis_cosmap_up_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isis_cosmap_pri_to_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isis_cosmap_pri_to_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isis_cosmap_pri_to_ehqueue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isis_cosmap_pri_to_ehqueue_get),
+
+#define COSMAP_API_PARAM \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+ SW_API_DEF(SW_API_SEC_NORM_SET, isis_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_NORM_GET, isis_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+ SW_API_DESC(SW_API_SEC_NORM_SET) \
+ SW_API_DESC(SW_API_SEC_NORM_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+ SW_API_DEF(SW_API_IP_HOST_ADD, isis_ip_host_add), \
+ SW_API_DEF(SW_API_IP_HOST_DEL, isis_ip_host_del), \
+ SW_API_DEF(SW_API_IP_HOST_GET, isis_ip_host_get), \
+ SW_API_DEF(SW_API_IP_HOST_NEXT, isis_ip_host_next), \
+ SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isis_ip_host_counter_bind), \
+ SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isis_ip_host_pppoe_bind), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isis_ip_pt_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isis_ip_pt_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isis_ip_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isis_ip_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isis_ip_source_guard_set), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isis_ip_source_guard_get), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isis_ip_arp_guard_set), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isis_ip_arp_guard_get), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isis_ip_route_status_set), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isis_ip_route_status_get), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isis_ip_intf_entry_add), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isis_ip_intf_entry_del), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isis_ip_intf_entry_next), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isis_ip_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isis_ip_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isis_arp_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isis_arp_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_SET, isis_ip_age_time_set), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_GET, isis_ip_age_time_get), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isis_ip_wcmp_hash_mode_set), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isis_ip_wcmp_hash_mode_get),
+
+#define IP_API_PARAM \
+ SW_API_DESC(SW_API_IP_HOST_ADD) \
+ SW_API_DESC(SW_API_IP_HOST_DEL) \
+ SW_API_DESC(SW_API_IP_HOST_GET) \
+ SW_API_DESC(SW_API_IP_HOST_NEXT) \
+ SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+ SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_GET)
+
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+ SW_API_DEF(SW_API_NAT_ADD, isis_nat_add), \
+ SW_API_DEF(SW_API_NAT_DEL, isis_nat_del), \
+ SW_API_DEF(SW_API_NAT_GET, isis_nat_get), \
+ SW_API_DEF(SW_API_NAT_NEXT, isis_nat_next), \
+ SW_API_DEF(SW_API_NAT_COUNTER_BIND, isis_nat_counter_bind), \
+ SW_API_DEF(SW_API_NAPT_ADD, isis_napt_add), \
+ SW_API_DEF(SW_API_NAPT_DEL, isis_napt_del), \
+ SW_API_DEF(SW_API_NAPT_GET, isis_napt_get), \
+ SW_API_DEF(SW_API_NAPT_NEXT, isis_napt_next), \
+ SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isis_napt_counter_bind), \
+ SW_API_DEF(SW_API_NAT_STATUS_SET, isis_nat_status_set), \
+ SW_API_DEF(SW_API_NAT_STATUS_GET, isis_nat_status_get), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isis_nat_hash_mode_set), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isis_nat_hash_mode_get), \
+ SW_API_DEF(SW_API_NAPT_STATUS_SET, isis_napt_status_set), \
+ SW_API_DEF(SW_API_NAPT_STATUS_GET, isis_napt_status_get), \
+ SW_API_DEF(SW_API_NAPT_MODE_SET, isis_napt_mode_set), \
+ SW_API_DEF(SW_API_NAPT_MODE_GET, isis_napt_mode_get), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isis_nat_prv_base_addr_set), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isis_nat_prv_base_addr_get), \
+ SW_API_DEF(SW_API_PRV_ADDR_MODE_SET, isis_nat_prv_addr_mode_set), \
+ SW_API_DEF(SW_API_PRV_ADDR_MODE_GET, isis_nat_prv_addr_mode_get), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isis_nat_pub_addr_add), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isis_nat_pub_addr_del), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isis_nat_pub_addr_next), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isis_nat_unk_session_cmd_set), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isis_nat_unk_session_cmd_get),
+
+#define NAT_API_PARAM \
+ SW_API_DESC(SW_API_NAT_ADD) \
+ SW_API_DESC(SW_API_NAT_DEL) \
+ SW_API_DESC(SW_API_NAT_GET) \
+ SW_API_DESC(SW_API_NAT_NEXT) \
+ SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAPT_ADD) \
+ SW_API_DESC(SW_API_NAPT_DEL) \
+ SW_API_DESC(SW_API_NAPT_GET) \
+ SW_API_DESC(SW_API_NAPT_NEXT) \
+ SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAPT_MODE_SET) \
+ SW_API_DESC(SW_API_NAPT_MODE_GET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+ SW_API_DESC(SW_API_PRV_ADDR_MODE_SET) \
+ SW_API_DESC(SW_API_PRV_ADDR_MODE_GET) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+ SW_API_DEF(SW_API_TRUNK_GROUP_SET, isis_trunk_group_set), \
+ SW_API_DEF(SW_API_TRUNK_GROUP_GET, isis_trunk_group_get), \
+ SW_API_DEF(SW_API_TRUNK_HASH_SET, isis_trunk_hash_mode_set), \
+ SW_API_DEF(SW_API_TRUNK_HASH_GET, isis_trunk_hash_mode_get), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isis_trunk_manipulate_sa_set), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isis_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+ SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+ SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_SET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_GET) \
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+ SW_API_DEF(SW_API_MAC_MODE_SET, isis_interface_mac_mode_set), \
+ SW_API_DEF(SW_API_MAC_MODE_GET, isis_interface_mac_mode_get), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isis_port_3az_status_set), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isis_port_3az_status_get), \
+ SW_API_DEF(SW_API_PHY_MODE_SET, isis_interface_phy_mode_set), \
+ SW_API_DEF(SW_API_PHY_MODE_GET, isis_interface_phy_mode_get),
+
+#define INTERFACECTRL_API_PARAM \
+ SW_API_DESC(SW_API_MAC_MODE_SET) \
+ SW_API_DESC(SW_API_MAC_MODE_GET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \
+ SW_API_DESC(SW_API_PHY_MODE_SET) \
+ SW_API_DESC(SW_API_PHY_MODE_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, isis_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, isis_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, isis_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, isis_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, isis_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, isis_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, isis_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ ACL_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ COSMAP_API \
+ SEC_API \
+ IP_API \
+ NAT_API \
+ TRUNK_API \
+ INTERFACECTRL_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ ACL_API_PARAM \
+ LED_API_PARAM \
+ COSMAP_API_PARAM \
+ SEC_API_PARAM \
+ IP_API_PARAM \
+ NAT_API_PARAM \
+ TRUNK_API_PARAM \
+ INTERFACECTRL_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_API_H_ */
diff --git a/include/hsl/isis/isis_cosmap.h b/include/hsl/isis/isis_cosmap.h
new file mode 100644
index 0000000..ec7aa6c
--- /dev/null
+++ b/include/hsl/isis/isis_cosmap.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_cosmap ISIS_COSMAP
+ * @{
+ */
+#ifndef _ISIS_COSMAP_H_
+#define _ISIS_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_cosmap.h"
+
+ sw_error_t isis_cosmap_init(a_uint32_t dev_id);
+
+#ifdef IN_COSMAP
+#define ISIS_COSMAP_INIT(rv, dev_id) \
+ { \
+ rv = isis_cosmap_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_COSMAP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t pri);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t dp);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * dp);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t pri);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * pri);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t dp);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * dp);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+ HSL_LOCAL sw_error_t
+ isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/hsl/isis/isis_fdb.h b/include/hsl/isis/isis_fdb.h
new file mode 100644
index 0000000..5eeafc4
--- /dev/null
+++ b/include/hsl/isis/isis_fdb.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_fdb ISIS_FDB
+ * @{
+ */
+#ifndef _ISIS_FDB_H_
+#define _ISIS_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t isis_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ISIS_FDB_INIT(rv, dev_id) \
+ { \
+ rv = isis_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flag);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port,
+ fal_port_t new_port, a_uint32_t fid,
+ fal_fdb_op_t * option);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+ HSL_LOCAL sw_error_t
+ isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+ HSL_LOCAL sw_error_t
+ isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t cnt);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * cnt);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+ HSL_LOCAL sw_error_t
+ isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_FDB_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/hsl/isis/isis_igmp.h b/include/hsl/isis/isis_igmp.h
new file mode 100644
index 0000000..98fa832
--- /dev/null
+++ b/include/hsl/isis/isis_igmp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_igmp ISIS_IGMP
+ * @{
+ */
+#ifndef _ISIS_IGMP_H_
+#define _ISIS_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+#include "fal/fal_multi.h"
+
+ sw_error_t
+ isis_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define ISIS_IGMP_INIT(rv, dev_id) \
+ { \
+ rv = isis_igmp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_igmp_sg_entry_show(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isis/isis_init.h b/include/hsl/isis/isis_init.h
new file mode 100644
index 0000000..d9ba6c7
--- /dev/null
+++ b/include/hsl/isis/isis_init.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_init ISIS_INIT
+ * @{
+ */
+#ifndef _ISIS_INIT_H_
+#define _ISIS_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+ sw_error_t
+ isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+ sw_error_t
+ isis_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isis/isis_interface_ctrl.h b/include/hsl/isis/isis_interface_ctrl.h
new file mode 100644
index 0000000..9fbaf1f
--- /dev/null
+++ b/include/hsl/isis/isis_interface_ctrl.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_INTERFACE_CTRL_H_
+#define _ISIS_INTERFACE_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_interface_ctrl.h"
+
+ sw_error_t isis_interface_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_INTERFACECONTROL
+#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = isis_interface_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_INTERFACE_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+
+ HSL_LOCAL sw_error_t
+ isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ HSL_LOCAL sw_error_t
+ isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ HSL_LOCAL sw_error_t
+ isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_INTERFACE_CTRL_H_ */
+
diff --git a/include/hsl/isis/isis_ip.h b/include/hsl/isis/isis_ip.h
new file mode 100644
index 0000000..4030021
--- /dev/null
+++ b/include/hsl/isis/isis_ip.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_IP_H_
+#define _ISIS_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_ip.h"
+
+ sw_error_t isis_ip_init(a_uint32_t dev_id);
+
+ sw_error_t isis_ip_reset(a_uint32_t dev_id);
+
+#ifdef IN_IP
+#define ISIS_IP_INIT(rv, dev_id) \
+ { \
+ rv = isis_ip_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISIS_IP_RESET(rv, dev_id) \
+ { \
+ rv = isis_ip_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_IP_INIT(rv, dev_id)
+#define ISIS_IP_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_IP_H_ */
diff --git a/include/hsl/isis/isis_leaky.h b/include/hsl/isis/isis_leaky.h
new file mode 100644
index 0000000..54b8329
--- /dev/null
+++ b/include/hsl/isis/isis_leaky.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_LEAKY_H_
+#define _ISIS_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+ sw_error_t isis_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define ISIS_LEAKY_INIT(rv, dev_id) \
+ { \
+ rv = isis_leaky_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_LEAKY_H_ */
+
diff --git a/include/hsl/isis/isis_led.h b/include/hsl/isis/isis_led.h
new file mode 100644
index 0000000..6698138
--- /dev/null
+++ b/include/hsl/isis/isis_led.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_LED_H_
+#define _ISIS_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+ sw_error_t
+ isis_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define ISIS_LED_INIT(rv, dev_id) \
+ { \
+ rv = isis_led_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+ HSL_LOCAL sw_error_t
+ isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_LED_H_ */
+
diff --git a/include/hsl/isis/isis_mib.h b/include/hsl/isis/isis_mib.h
new file mode 100644
index 0000000..ac443b8
--- /dev/null
+++ b/include/hsl/isis/isis_mib.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_MIB_H_
+#define _ISIS_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ isis_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ISIS_MIB_INIT(rv, dev_id) \
+ { \
+ rv = isis_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+ HSL_LOCAL sw_error_t
+ isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_MIB_H_ */
+
diff --git a/include/hsl/isis/isis_mirror.h b/include/hsl/isis/isis_mirror.h
new file mode 100644
index 0000000..b83eecb
--- /dev/null
+++ b/include/hsl/isis/isis_mirror.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_MIRROR_H_
+#define _ISIS_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+ sw_error_t isis_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define ISIS_MIRR_INIT(rv, dev_id) \
+ { \
+ rv = isis_mirr_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_MIRROR_H_ */
+
diff --git a/include/hsl/isis/isis_misc.h b/include/hsl/isis/isis_misc.h
new file mode 100644
index 0000000..228f037
--- /dev/null
+++ b/include/hsl/isis/isis_misc.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_MISC_H_
+#define _ISIS_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+ sw_error_t isis_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define ISIS_MISC_INIT(rv, dev_id) \
+ { \
+ rv = isis_misc_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+ HSL_LOCAL sw_error_t
+ isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+ HSL_LOCAL sw_error_t
+ isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
+
diff --git a/include/hsl/isis/isis_nat.h b/include/hsl/isis/isis_nat.h
new file mode 100644
index 0000000..f514144
--- /dev/null
+++ b/include/hsl/isis/isis_nat.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_NAT_H_
+#define _ISIS_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+ sw_error_t isis_nat_init(a_uint32_t dev_id);
+
+ sw_error_t isis_nat_reset(a_uint32_t dev_id);
+
+#ifdef IN_NAT
+#define ISIS_NAT_INIT(rv, dev_id) \
+ { \
+ rv = isis_nat_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISIS_NAT_RESET(rv, dev_id) \
+ { \
+ rv = isis_nat_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_NAT_INIT(rv, dev_id)
+#define ISIS_NAT_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ HSL_LOCAL sw_error_t
+ isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_NAT_H_ */
diff --git a/include/hsl/isis/isis_nat_helper.h b/include/hsl/isis/isis_nat_helper.h
new file mode 100644
index 0000000..0ed6817
--- /dev/null
+++ b/include/hsl/isis/isis_nat_helper.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_NAT_HELPER_H_
+#define _ISIS_NAT_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+ sw_error_t nat_helper_init(a_uint32_t dev_id);
+
+ sw_error_t nat_helper_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_NAT_HELPER
+#define ISIS_NAT_HELPER_INIT(rv, dev_id) \
+ { \
+ rv = nat_helper_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id) \
+ { \
+ rv = nat_helper_cleanup(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_NAT_HELPER_INIT(rv, dev_id)
+#define ISIS_NAT_HELPER_CLEANUP(rv, dev_id)
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_NAT_HELPER_H_ */
diff --git a/include/hsl/isis/isis_port_ctrl.h b/include/hsl/isis/isis_port_ctrl.h
new file mode 100644
index 0000000..95b802e
--- /dev/null
+++ b/include/hsl/isis/isis_port_ctrl.h
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_PORT_CTRL_H_
+#define _ISIS_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t isis_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ISIS_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = isis_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+
+ HSL_LOCAL sw_error_t
+ isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+ HSL_LOCAL sw_error_t
+ isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_PORT_CTRL_H_ */
+
diff --git a/include/hsl/isis/isis_portvlan.h b/include/hsl/isis/isis_portvlan.h
new file mode 100644
index 0000000..a388ffb
--- /dev/null
+++ b/include/hsl/isis/isis_portvlan.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_PORTVLAN_H_
+#define _ISIS_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t isis_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ISIS_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = isis_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ HSL_LOCAL sw_error_t
+ isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_PORTVLAN_H */
+
diff --git a/include/hsl/isis/isis_qos.h b/include/hsl/isis/isis_qos.h
new file mode 100644
index 0000000..992b717
--- /dev/null
+++ b/include/hsl/isis/isis_qos.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_QOS_H_
+#define _ISIS_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+ sw_error_t isis_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define ISIS_QOS_INIT(rv, dev_id) \
+ { \
+ rv = isis_qos_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_QOS_H_ */
+
diff --git a/include/hsl/isis/isis_rate.h b/include/hsl/isis/isis_rate.h
new file mode 100644
index 0000000..b08ffc1
--- /dev/null
+++ b/include/hsl/isis/isis_rate.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_RATE_H_
+#define _ISIS_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+ sw_error_t isis_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define ISIS_RATE_INIT(rv, dev_id) \
+ { \
+ rv = isis_rate_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number);
+
+ HSL_LOCAL sw_error_t
+ isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_RATE_H_ */
+
diff --git a/include/hsl/isis/isis_reg.h b/include/hsl/isis/isis_reg.h
new file mode 100644
index 0000000..e5f9755
--- /dev/null
+++ b/include/hsl/isis/isis_reg.h
@@ -0,0 +1,5206 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISIS_REG_H_
+#define _ISIS_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define S16E_DEVICE_ID 0x11
+#define S17_DEVICE_ID 0x12
+#define S17_REVISION_A 0x01
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+ /* ISIS Mask Control Register */
+#define MASK_CTL
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 1
+
+#define SOFT_RST
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define LOAD_EEPROM
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+
+
+
+ /* Port0 Pad Control Register */
+#define PORT0_PAD_CTRL
+#define PORT0_PAD_CTRL_ID 0
+#define PORT0_PAD_CTRL_OFFSET 0x0004
+#define PORT0_PAD_CTRL_E_LENGTH 4
+#define PORT0_PAD_CTRL_E_OFFSET 0
+#define PORT0_PAD_CTRL_NR_E 1
+
+#define MAC0_RGMII_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET 26
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define SGMII_CLK125M_RX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET 19
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG HSL_RW
+
+#define SGMII_CLK125M_TX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET 18
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET 14
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET 13
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET 12
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET 10
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC0_PHY_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_SGMII_EN
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET 7
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET 6
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET 5
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET 4
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_MII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET 2
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* Port5 Pad Control Register */
+#define PORT5_PAD_CTRL
+#define PORT5_PAD_CTRL_ID 0
+#define PORT5_PAD_CTRL_OFFSET 0x0008
+#define PORT5_PAD_CTRL_E_LENGTH 4
+#define PORT5_PAD_CTRL_E_OFFSET 0
+#define PORT5_PAD_CTRL_NR_E 1
+
+#define MAC5_RGMII_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET 26
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_PIPE_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_EN
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET 10
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC5_PHY_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_MAC_MII_EN
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET 2
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC5_MAC_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_MAC_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* Port6 Pad Control Register */
+#define PORT6_PAD_CTRL
+#define PORT6_PAD_CTRL_ID 0
+#define PORT6_PAD_CTRL_OFFSET 0x000c
+#define PORT6_PAD_CTRL_E_LENGTH 4
+#define PORT6_PAD_CTRL_E_OFFSET 0
+#define PORT6_PAD_CTRL_NR_E 1
+
+#define MAC6_RGMII_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET 26
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define PHY4_MII_EN
+#define PORT6_PAD_CTRL_PHY4_MII_EN_BOFFSET 18
+#define PORT6_PAD_CTRL_PHY4_MII_EN_BLEN 1
+#define PORT6_PAD_CTRL_PHY4_MII_EN_FLAG HSL_RW
+
+#define PHY4_RGMII_EN
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET 17
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG HSL_RW
+
+#define PHY4_GMII_EN
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_BOFFSET 16
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_PHY4_GMII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET 14
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET 13
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET 12
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_PIPE_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET 10
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_SGMII_EN
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET 7
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET 6
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET 5
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET 4
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_MII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET 2
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* SGMII Control Register */
+#define SGMII_CTRL
+#define SGMII_CTRL_ID 0
+#define SGMII_CTRL_OFFSET 0x00e0
+#define SGMII_CTRL_E_LENGTH 4
+#define SGMII_CTRL_E_OFFSET 0
+#define SGMII_CTRL_NR_E 1
+
+#define FULL_25M
+#define SGMII_CTRL_FULL_25M_BOFFSET 31
+#define SGMII_CTRL_FULL_25M_BLEN 1
+#define SGMII_CTRL_FULL_25M_FLAG HSL_RW
+
+#define HALF_25M
+#define SGMII_CTRL_HALF_25M_BOFFSET 30
+#define SGMII_CTRL_HALF_25M_BLEN 1
+#define SGMII_CTRL_HALF_25M_FLAG HSL_RW
+
+#define REMOTE_25M
+#define SGMII_CTRL_REMOTE_25M_BOFFSET 28
+#define SGMII_CTRL_REMOTE_25M_BLEN 2
+#define SGMII_CTRL_REMOTE_25M_FLAG HSL_RW
+
+#define NEXT_PAGE_25M
+#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET 27
+#define SGMII_CTRL_NEXT_PAGE_25M_BLEN 1
+#define SGMII_CTRL_NEXT_PAGE_25M_FLAG HSL_RW
+
+#define PAUSE_25M
+#define SGMII_CTRL_PAUSE_25M_BOFFSET 26
+#define SGMII_CTRL_PAUSE_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_25M_FLAG HSL_RW
+
+#define ASYM_PAUSE_25M
+#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET 25
+#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN 1
+#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW
+
+#define MODE_CTRL_25M
+#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET 22
+#define SGMII_CTRL_MODE_CTRL_25M_BLEN 2
+#define SGMII_CTRL_MODE_CTRL_25M_FLAG HSL_RW
+
+#define MR_LOOPBACK
+#define SGMII_CTRL_MR_LOOPBACK_BOFFSET 21
+#define SGMII_CTRL_MR_LOOPBACK_BLEN 1
+#define SGMII_CTRL_MR_LOOPBACK_FLAG HSL_RW
+
+#define MR_REG4_25M
+#define SGMII_CTRL_MR_REG4_25M_BOFFSET 20
+#define SGMII_CTRL_MR_REG4_25M_BLEN 1
+#define SGMII_CTRL_MR_REG4_25M_FLAG HSL_RW
+
+#define AUTO_LPI_25M
+#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET 19
+#define SGMII_CTRL_AUTO_LPI_25M_BLEN 1
+#define SGMII_CTRL_AUTO_LPI_25M_FLAG HSL_RW
+
+#define PRBS_EN
+#define SGMII_CTRL_PRBS_EN_BOFFSET 18
+#define SGMII_CTRL_PRBS_EN_BLEN 1
+#define SGMII_CTRL_PRBS_EN_FLAG HSL_RW
+
+#define SGMII_TH_LOS1
+#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET 17
+#define SGMII_CTRL_SGMII_TH_LOS1_BLEN 1
+#define SGMII_CTRL_SGMII_TH_LOS1_FLAG HSL_RW
+
+#define DIS_AUTO_LPI_25M
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET 16
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN 1
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG HSL_RW
+
+#define SGMII_TH_LOS0
+#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET 15
+#define SGMII_CTRL_SGMII_TH_LOS0_BLEN 1
+#define SGMII_CTRL_SGMII_TH_LOS0_FLAG HSL_RW
+
+#define SGMII_CDR_BW
+#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET 13
+#define SGMII_CTRL_SGMII_CDR_BW_BLEN 2
+#define SGMII_CTRL_SGMII_CDR_BW_FLAG HSL_RW
+
+#define SGMII_TXDR_CTRL
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET 10
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN 3
+#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG HSL_RW
+
+#define SGMII_FIBER_MODE
+#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET 8
+#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN 2
+#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG HSL_RW
+
+#define SGMII_SEL_125M
+#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET 7
+#define SGMII_CTRL_SGMII_SEL_125M_BLEN 1
+#define SGMII_CTRL_SGMII_SEL_125M_FLAG HSL_RW
+
+#define SGMII_PLL_BW
+#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET 6
+#define SGMII_CTRL_SGMII_PLL_BW_BLEN 1
+#define SGMII_CTRL_SGMII_PLL_BW_FLAG HSL_RW
+
+#define SGMII_HALFTX
+#define SGMII_CTRL_SGMII_HALFTX_BOFFSET 5
+#define SGMII_CTRL_SGMII_HALFTX_BLEN 1
+#define SGMII_CTRL_SGMII_HALFTX_FLAG HSL_RW
+
+#define SGMII_EN_SD
+#define SGMII_CTRL_SGMII_EN_SD_BOFFSET 4
+#define SGMII_CTRL_SGMII_EN_SD_BLEN 1
+#define SGMII_CTRL_SGMII_EN_SD_FLAG HSL_RW
+
+#define SGMII_EN_TX
+#define SGMII_CTRL_SGMII_EN_TX_BOFFSET 3
+#define SGMII_CTRL_SGMII_EN_TX_BLEN 1
+#define SGMII_CTRL_SGMII_EN_TX_FLAG HSL_RW
+
+#define SGMII_EN_RX
+#define SGMII_CTRL_SGMII_EN_RX_BOFFSET 2
+#define SGMII_CTRL_SGMII_EN_RX_BLEN 1
+#define SGMII_CTRL_SGMII_EN_RX_FLAG HSL_RW
+
+#define SGMII_EN_PLL
+#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET 1
+#define SGMII_CTRL_SGMII_EN_PLL_BLEN 1
+#define SGMII_CTRL_SGMII_EN_PLL_FLAG HSL_RW
+
+#define SGMII_EN_LCKDT
+#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET 0
+#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN 1
+#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG HSL_RW
+
+
+
+
+ /* Power On Strip Register */
+#define POWER_STRIP
+#define POWER_STRIP_ID 0
+#define POWER_STRIP_OFFSET 0x0010
+#define POWER_STRIP_E_LENGTH 4
+#define POWER_STRIP_E_OFFSET 0
+#define POWER_STRIP_NR_E 1
+
+#define POWER_ON_SEL
+#define POWER_STRIP_POWER_ON_SEL_BOFFSET 31
+#define POWER_STRIP_POWER_ON_SEL_BLEN 1
+#define POWER_STRIP_POWER_ON_SEL_FLAG HSL_RW
+
+#define PKG128_EN
+#define POWER_STRIP_PKG128_EN_BOFFSET 30
+#define POWER_STRIP_PKG128_EN_BLEN 1
+#define POWER_STRIP_PKG128_EN_FLAG HSL_RW
+
+#define PKG128_EN_LED
+#define POWER_STRIP_PKG128_EN_LED_BOFFSET 29
+#define POWER_STRIP_PKG128_EN_LED_BLEN 1
+#define POWER_STRIP_PKG128_EN_LED_FLAG HSL_RW
+
+#define S16_MODE
+#define POWER_STRIP_S16_MODE_BOFFSET 28
+#define POWER_STRIP_S16_MODE_BLEN 1
+#define POWER_STRIP_S16_MODE_FLAG HSL_RW
+
+#define INPUT_MODE
+#define POWER_STRIP_INPUT_MODE_BOFFSET 27
+#define POWER_STRIP_INPUT_MODE_BLEN 1
+#define POWER_STRIP_INPUT_MODE_FLAG HSL_RW
+
+#define SGMII_POWER_ON_SEL
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET 26
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN 1
+#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG HSL_RW
+
+#define SPI_EN
+#define POWER_STRIP_SPI_EN_BOFFSET 25
+#define POWER_STRIP_SPI_EN_BLEN 1
+#define POWER_STRIP_SPI_EN_FLAG HSL_RW
+
+#define LED_OPEN_EN
+#define POWER_STRIP_LED_OPEN_EN_BOFFSET 24
+#define POWER_STRIP_LED_OPEN_EN_BLEN 1
+#define POWER_STRIP_LED_OPEN_EN_FLAG HSL_RW
+
+#define SGMII_RXIMP_50_70
+#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET 23
+#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN 1
+#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG HSL_RW
+
+#define SGMII_TXIMP_50_70
+#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET 22
+#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN 1
+#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG HSL_RW
+
+#define SGMII_SIGNAL_DETECT
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET 21
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN 1
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG HSL_RW
+
+#define LPW_EXIT
+#define POWER_STRIP_LPW_EXIT_BOFFSET 20
+#define POWER_STRIP_LPW_EXIT_BLEN 1
+#define POWER_STRIP_LPW_EXIT_FLAG HSL_RW
+
+#define MAN_EN
+#define POWER_STRIP_MAN_EN_BOFFSET 18
+#define POWER_STRIP_MAN_EN_BLEN 1
+#define POWER_STRIP_MAN_EN_FLAG HSL_RW
+
+#define HIB_EN
+#define POWER_STRIP_HIB_EN_BOFFSET 17
+#define POWER_STRIP_HIB_EN_BLEN 1
+#define POWER_STRIP_HIB_EN_FLAG HSL_RW
+
+#define POWER_DOWN_HW
+#define POWER_STRIP_POWER_DOWN_HW_BOFFSET 16
+#define POWER_STRIP_POWER_DOWN_HW_BLEN 1
+#define POWER_STRIP_POWER_DOWN_HW_FLAG HSL_RW
+
+#define BIST_BYPASS_CEL
+#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET 15
+#define POWER_STRIP_BIST_BYPASS_CEL_BLEN 1
+#define POWER_STRIP_BIST_BYPASS_CEL_FLAG HSL_RW
+
+#define BIST_BYPASS_CSR
+#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET 14
+#define POWER_STRIP_BIST_BYPASS_CSR_BLEN 1
+#define POWER_STRIP_BIST_BYPASS_CSR_FLAG HSL_RW
+
+#define HIB_PULSE_HW
+#define POWER_STRIP_HIB_PULSE_HW_BOFFSET 12
+#define POWER_STRIP_HIB_PULSE_HW_BLEN 1
+#define POWER_STRIP_HIB_PULSE_HW_FLAG HSL_RW
+
+#define GATE_25M_EN
+#define POWER_STRIP_GATE_25M_EN_BOFFSET 10
+#define POWER_STRIP_GATE_25M_EN_BLEN 1
+#define POWER_STRIP_GATE_25M_EN_FLAG HSL_RW
+
+#define SEL_ANA_RST
+#define POWER_STRIP_SEL_ANA_RST_BOFFSET 9
+#define POWER_STRIP_SEL_ANA_RST_BLEN 1
+#define POWER_STRIP_SEL_ANA_RST_FLAG HSL_RW
+
+#define SERDES_EN
+#define POWER_STRIP_SERDES_EN_BOFFSET 8
+#define POWER_STRIP_SERDES_EN_BLEN 1
+#define POWER_STRIP_SERDES_EN_FLAG HSL_RW
+
+#define SERDES_AN_EN
+#define POWER_STRIP_SERDES_AN_EN_BOFFSET 7
+#define POWER_STRIP_SERDES_AN_EN_BLEN 1
+#define POWER_STRIP_SERDES_AN_EN_FLAG HSL_RW
+
+#define RTL_MODE
+#define POWER_STRIP_RTL_MODE_BOFFSET 5
+#define POWER_STRIP_RTL_MODE_BLEN 1
+#define POWER_STRIP_RTL_MODE_FLAG HSL_RW
+
+#define PAD_CTRL_FOR25M
+#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET 3
+#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN 2
+#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG HSL_RW
+
+#define PAD_CTRL
+#define POWER_STRIP_PAD_CTRL_BOFFSET 0
+#define POWER_STRIP_PAD_CTRL_BLEN 2
+#define POWER_STRIP_PAD_CTRL_FLAG HSL_RW
+
+
+
+
+ /* Global Interrupt Status Register1 */
+#define GBL_INT_STATUS1
+#define GBL_INT_STATUS1_ID 1
+#define GBL_INT_STATUS1_OFFSET 0x0024
+#define GBL_INT_STATUS1_E_LENGTH 4
+#define GBL_INT_STATUS1_E_OFFSET 0
+#define GBL_INT_STATUS1_NR_E 1
+
+#define PHY_INT_S
+#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15
+#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1
+#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO
+
+
+
+
+ /* Global Interrupt Mask Register1 */
+#define GBL_INT_MASK1
+#define GBL_INT_MASK1_ID 1
+#define GBL_INT_MASK1_OFFSET 0x002c
+#define GBL_INT_MASK1_E_LENGTH 4
+#define GBL_INT_MASK1_E_OFFSET 0
+#define GBL_INT_MASK1_NR_E 1
+
+#define PHY_INT_M
+#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15
+#define GBL_INT_MASK1_PHY_INT_M_BLEN 1
+#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO
+
+
+
+
+ /* Module Enable Register */
+#define MOD_ENABLE
+#define MOD_ENABLE_OFFSET 0x0030
+#define MOD_ENABLE_E_LENGTH 4
+#define MOD_ENABLE_E_OFFSET 0
+#define MOD_ENABLE_NR_E 1
+
+#define L3_EN
+#define MOD_ENABLE_L3_EN_BOFFSET 2
+#define MOD_ENABLE_L3_EN_BLEN 1
+#define MOD_ENABLE_L3_EN_FLAG HSL_RW
+
+#define ACL_EN
+#define MOD_ENABLE_ACL_EN_BOFFSET 1
+#define MOD_ENABLE_ACL_EN_BLEN 1
+#define MOD_ENABLE_ACL_EN_FLAG HSL_RW
+
+#define MIB_EN
+#define MOD_ENABLE_MIB_EN_BOFFSET 0
+#define MOD_ENABLE_MIB_EN_BLEN 1
+#define MOD_ENABLE_MIB_EN_FLAG HSL_RW
+
+
+
+
+ /* MIB Function Register */
+#define MIB_FUNC
+#define MIB_FUNC_OFFSET 0x0034
+#define MIB_FUNC_E_LENGTH 4
+#define MIB_FUNC_E_OFFSET 0
+#define MIB_FUNC_NR_E 1
+
+#define MIB_FUN
+#define MIB_FUNC_MIB_FUN_BOFFSET 24
+#define MIB_FUNC_MIB_FUN_BLEN 3
+#define MIB_FUNC_MIB_FUN_FLAG HSL_RW
+
+#define MIB_BUSY
+#define MIB_FUNC_MIB_BUSY_BOFFSET 17
+#define MIB_FUNC_MIB_BUSY_BLEN 1
+#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER
+#define MIB_FUNC_MIB_TIMER_BOFFSET 0
+#define MIB_FUNC_MIB_TIMER_BLEN 16
+#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW
+
+
+
+
+ /* Service tag Register */
+#define SERVICE_TAG
+#define SERVICE_TAG_OFFSET 0x0048
+#define SERVICE_TAG_E_LENGTH 4
+#define SERVICE_TAG_E_OFFSET 0
+#define SERVICE_TAG_NR_E 1
+
+#define STAG_MODE
+#define SERVICE_TAG_STAG_MODE_BOFFSET 17
+#define SERVICE_TAG_STAG_MODE_BLEN 1
+#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW
+
+#define TAG_VALUE
+#define SERVICE_TAG_TAG_VALUE_BOFFSET 0
+#define SERVICE_TAG_TAG_VALUE_BLEN 16
+#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW
+
+
+
+
+ /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0060
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 1
+
+#define GLB_BYTE4
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+#define GLOBAL_MAC_ADDR1
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0064
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 1
+
+#define GLB_BYTE0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+
+
+
+ /* Max Size Register */
+#define MAX_SIZE
+#define MAX_SIZE_OFFSET 0x0078
+#define MAX_SIZE_E_LENGTH 4
+#define MAX_SIZE_E_OFFSET 0
+#define MAX_SIZE_NR_E 1
+
+#define MAX_FRAME_SIZE
+#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0
+#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14
+#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW
+
+
+
+
+ /* Flow Control Register */
+#define FLOW_CTL0 "fctl"
+#define FLOW_CTL0_ID 6
+#define FLOW_CTL0_OFFSET 0x0034
+#define FLOW_CTL0_E_LENGTH 4
+#define FLOW_CTL0_E_OFFSET 0
+#define FLOW_CTL0_NR_E 1
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL0_TEST_PAUSE_BLEN 1
+#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Flow Control1 Register */
+#define FLOW_CTL1 "fctl1"
+#define FLOW_CTL1_ID 6
+#define FLOW_CTL1_OFFSET 0x0038
+#define FLOW_CTL1_E_LENGTH 4
+#define FLOW_CTL1_E_OFFSET 0
+#define FLOW_CTL1_NR_E 1
+
+#define PORT_PAUSE_ON_THRES "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Port Status Register */
+#define PORT_STATUS
+#define PORT_STATUS_OFFSET 0x007c
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0004
+#define PORT_STATUS_NR_E 7
+
+#define FLOW_LINK_EN
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN 1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW
+
+#define AUTO_RX_FLOW
+#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11
+#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1
+#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO
+
+#define AUTO_TX_FLOW
+#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10
+#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1
+#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO
+
+#define LINK_EN
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW
+
+#define DUPLEX_MODE
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+
+
+
+ /* Header Ctl Register */
+#define HEADER_CTL
+#define HEADER_CTL_OFFSET 0x0098
+#define HEADER_CTL_E_LENGTH 4
+#define HEADER_CTL_E_OFFSET 0x0004
+#define HEADER_CTL_NR_E 1
+
+#define TYPE_LEN
+#define HEADER_CTL_TYPE_LEN_BOFFSET 16
+#define HEADER_CTL_TYPE_LEN_BLEN 1
+#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW
+
+#define TYPE_VAL
+#define HEADER_CTL_TYPE_VAL_BOFFSET 0
+#define HEADER_CTL_TYPE_VAL_BLEN 16
+#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW
+
+
+
+
+ /* Port Header Ctl Register */
+#define PORT_HDR_CTL
+#define PORT_HDR_CTL_OFFSET 0x009c
+#define PORT_HDR_CTL_E_LENGTH 4
+#define PORT_HDR_CTL_E_OFFSET 0x0004
+#define PORT_HDR_CTL_NR_E 7
+
+#define IPG_DEC_EN
+#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5
+#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1
+#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW
+
+#define LOOPBACK_EN
+#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4
+#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1
+#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW
+
+#define RXHDR_MODE
+#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2
+#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2
+#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW
+
+#define TXHDR_MODE
+#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0
+#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2
+#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW
+
+
+
+
+ /* EEE control Register */
+#define EEE_CTL
+#define EEE_CTL_OFFSET 0x0100
+#define EEE_CTL_E_LENGTH 4
+#define EEE_CTL_E_OFFSET 0
+#define EEE_CTL_NR_E 1
+
+#define LPI_STATE_REMAP_EN_5
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW
+
+#define LPI_EN_5
+#define EEE_CTL_LPI_EN_5_BOFFSET 12
+#define EEE_CTL_LPI_EN_5_BLEN 1
+#define EEE_CTL_LPI_EN_5_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_4
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW
+
+#define LPI_EN_4
+#define EEE_CTL_LPI_EN_4_BOFFSET 10
+#define EEE_CTL_LPI_EN_4_BLEN 1
+#define EEE_CTL_LPI_EN_4_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_3
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW
+
+#define LPI_EN_3
+#define EEE_CTL_LPI_EN_3_BOFFSET 8
+#define EEE_CTL_LPI_EN_3_BLEN 1
+#define EEE_CTL_LPI_EN_3_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_2
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW
+
+#define LPI_EN_2
+#define EEE_CTL_LPI_EN_2_BOFFSET 6
+#define EEE_CTL_LPI_EN_2_BLEN 1
+#define EEE_CTL_LPI_EN_2_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW
+
+#define LPI_EN_1
+#define EEE_CTL_LPI_EN_1_BOFFSET 4
+#define EEE_CTL_LPI_EN_1_BLEN 1
+#define EEE_CTL_LPI_EN_1_FLAG HSL_RW
+
+
+
+
+ /* Frame Ack Ctl0 Register */
+#define FRAME_ACK_CTL0
+#define FRAME_ACK_CTL0_OFFSET 0x0210
+#define FRAME_ACK_CTL0_E_LENGTH 4
+#define FRAME_ACK_CTL0_E_OFFSET 0
+#define FRAME_ACK_CTL0_NR_E 1
+
+#define ARP_REQ_EN
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1
+#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW
+
+#define ARP_REP_EN
+#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5
+#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1
+#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW
+
+#define DHCP_EN
+#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4
+#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1
+#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW
+
+#define EAPOL_EN
+#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3
+#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1
+#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW
+
+#define LEAVE_EN
+#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2
+#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1
+#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW
+
+#define JOIN_EN
+#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1
+#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1
+#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW
+
+
+
+
+ /* Frame Ack Ctl1 Register */
+#define FRAME_ACK_CTL1
+#define FRAME_ACK_CTL1_OFFSET 0x0214
+#define FRAME_ACK_CTL1_E_LENGTH 4
+#define FRAME_ACK_CTL1_E_OFFSET 0
+#define FRAME_ACK_CTL1_NR_E 1
+
+#define PPPOE_EN
+#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25
+#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1
+#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW
+
+#define IGMP_V3_EN
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1
+#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW
+
+
+
+
+ /* Window Rule Ctl0 Register */
+#define WIN_RULE_CTL0
+#define WIN_RULE_CTL0_OFFSET 0x0218
+#define WIN_RULE_CTL0_E_LENGTH 4
+#define WIN_RULE_CTL0_E_OFFSET 0x4
+#define WIN_RULE_CTL0_NR_E 7
+
+#define L4_LENGTH
+#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24
+#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW
+
+#define L3_LENGTH
+#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20
+#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW
+
+#define L2_LENGTH
+#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16
+#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW
+
+#define L4_OFFSET
+#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10
+#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW
+
+#define L3_OFFSET
+#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5
+#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW
+
+#define L2_OFFSET
+#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0
+#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW
+
+
+
+
+ /* Window Rule Ctl1 Register */
+#define WIN_RULE_CTL1
+#define WIN_RULE_CTL1_OFFSET 0x0234
+#define WIN_RULE_CTL1_E_LENGTH 4
+#define WIN_RULE_CTL1_E_OFFSET 0x4
+#define WIN_RULE_CTL1_NR_E 7
+
+#define L3P_LENGTH
+#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20
+#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4
+#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW
+
+#define L2S_LENGTH
+#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16
+#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4
+#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW
+
+#define L3P_OFFSET
+#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5
+#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5
+#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW
+
+#define L2S_OFFSET
+#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0
+#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5
+#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW
+
+
+
+
+ /* Trunk Hash Mode Register */
+#define TRUNK_HASH_MODE
+#define TRUNK_HASH_MODE_OFFSET 0x0270
+#define TRUNK_HASH_MODE_E_LENGTH 4
+#define TRUNK_HASH_MODE_E_OFFSET 0x4
+#define TRUNK_HASH_MODE_NR_E 1
+
+#define DIP_EN
+#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 3
+#define TRUNK_HASH_MODE_DIP_EN_BLEN 1
+#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW
+
+#define SIP_EN
+#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 2
+#define TRUNK_HASH_MODE_SIP_EN_BLEN 1
+#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW
+
+#define SA_EN
+#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1
+#define TRUNK_HASH_MODE_SA_EN_BLEN 1
+#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW
+
+#define DA_EN
+#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0
+#define TRUNK_HASH_MODE_DA_EN_BLEN 1
+#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW
+
+
+
+
+ /* Vlan Table Function0 Register */
+#define VLAN_TABLE_FUNC0
+#define VLAN_TABLE_FUNC0_OFFSET 0x0610
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 1
+
+#define VT_VALID
+#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20
+#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW
+
+#define IVL_EN
+#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19
+#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW
+
+#define LEARN_DIS
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1
+#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW
+
+#define VID_MEM
+#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14
+#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW
+
+#define VT_PRI_EN
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+ /* Vlan Table Function1 Register */
+#define VLAN_TABLE_FUNC1
+#define VLAN_TABLE_FUNC1_OFFSET 0x0614
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 1
+
+#define VT_BUSY
+#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31
+#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW
+
+#define VLAN_ID
+#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_FUNC
+#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW
+
+
+
+
+ /* Address Table Function0 Register */
+#define ADDR_TABLE_FUNC0
+#define ADDR_TABLE_FUNC0_OFFSET 0x0600
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 1
+
+
+#define AT_ADDR_BYTE2
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW
+
+#define AT_ADDR_BYTE4
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+ /* Address Table Function1 Register */
+#define ADDR_TABLE_FUNC1
+#define ADDR_TABLE_FUNC1_OFFSET 0x0604
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 1
+
+#define SA_DROP_EN
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW
+
+#define MIRROR_EN
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_SVL_EN
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW
+
+#define AT_PRI
+#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3
+#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW
+
+#define CROSS_PT
+#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23
+#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1
+#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW
+
+#define DES_PORT
+#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16
+#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7
+#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW
+
+#define AT_ADDR_BYTE0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+ /* Address Table Function2 Register */
+#define ADDR_TABLE_FUNC2
+#define ADDR_TABLE_FUNC2_OFFSET 0x0608
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 1
+
+#define WL_EN
+#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20
+#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW
+
+#define AT_VID
+#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8
+#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12
+#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW
+
+#define SHORT_LOOP
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW
+
+#define COPY_TO_CPU
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define LEAKY_EN
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW
+
+#define AT_STATUS
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+ /* Address Table Function3 Register */
+#define ADDR_TABLE_FUNC3
+#define ADDR_TABLE_FUNC3_OFFSET 0x060c
+#define ADDR_TABLE_FUNC3_E_LENGTH 4
+#define ADDR_TABLE_FUNC3_E_OFFSET 0
+#define ADDR_TABLE_FUNC3_NR_E 1
+
+#define AT_BUSY
+#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31
+#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW
+
+#define NEW_PORT_NUM
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW
+
+#define AT_INDEX
+#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16
+#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5
+#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW
+
+#define AT_VID_EN
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW
+
+#define AT_PORT_EN
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW
+
+#define AT_MULTI_EN
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW
+
+#define AT_FULL_VIO
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW
+
+#define FLUSH_ST_EN
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW
+
+#define AT_FUNC
+#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4
+#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW
+
+
+
+
+ /* Reserve Address Table0 Register */
+#define RESV_ADDR_TBL0
+#define RESV_ADDR_TBL0_OFFSET 0x3c000
+#define RESV_ADDR_TBL0_E_LENGTH 4
+#define RESV_ADDR_TBL0_E_OFFSET 0
+#define RESV_ADDR_TBL0_NR_E 1
+
+#define RESV_ADDR_BYTE2
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE3
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE4
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE5
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW
+
+ /* Reserve Address Table1 Register */
+#define RESV_ADDR_TBL1
+#define RESV_ADDR_TBL1_OFFSET 0x3c004
+#define RESV_ADDR_TBL1_E_LENGTH 4
+#define RESV_ADDR_TBL1_E_OFFSET 0
+#define RESV_ADDR_TBL1_NR_E 1
+
+#define RESV_COPY_TO_CPU
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW
+
+#define RESV_REDRCT_TO_CPU
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define RESV_LEAKY_EN
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW
+
+#define RESV_MIRROR_EN
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW
+
+#define RESV_PRI_EN
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW
+
+#define RESV_PRI
+#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24
+#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3
+#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW
+
+#define RESV_CROSS_PT
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW
+
+#define RESV_DES_PORT
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7
+#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE1
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW
+
+ /* Reserve Address Table2 Register */
+#define RESV_ADDR_TBL2
+#define RESV_ADDR_TBL2_OFFSET 0x3c008
+#define RESV_ADDR_TBL2_E_LENGTH 4
+#define RESV_ADDR_TBL2_E_OFFSET 0
+#define RESV_ADDR_TBL2_NR_E 1
+
+#define RESV_STATUS
+#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0
+#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1
+#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW
+
+
+
+
+ /* Address Table Control Register */
+#define ADDR_TABLE_CTL
+#define ADDR_TABLE_CTL_OFFSET 0x0618
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 1
+
+#define ARL_INI_EN
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define LEARN_CHANGE_EN
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_LEAKY
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW
+
+#define IGMP_CREAT_EN
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW
+
+#define IGMP_PRI_EN
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW
+
+#define IGMP_PRI
+#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24
+#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3
+#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW
+
+#define IGMP_JOIN_STATIC
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW
+
+#define AGE_EN
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define LOOP_CHECK_TIMER
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW
+
+#define AGE_TIME
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+
+
+
+ /* Global Forward Control0 Register */
+#define FORWARD_CTL0
+#define FORWARD_CTL0_OFFSET 0x0620
+#define FORWARD_CTL0_E_LENGTH 4
+#define FORWARD_CTL0_E_OFFSET 0
+#define FORWARD_CTL0_NR_E 1
+
+#define ARP_CMD
+#define FORWARD_CTL0_ARP_CMD_BOFFSET 26
+#define FORWARD_CTL0_ARP_CMD_BLEN 2
+#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW
+
+#define IP_NOT_FOUND
+#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24
+#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2
+#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW
+
+#define ARP_NOT_FOUND
+#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22
+#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2
+#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW
+
+#define HASH_MODE
+#define FORWARD_CTL0_HASH_MODE_BOFFSET 20
+#define FORWARD_CTL0_HASH_MODE_BLEN 2
+#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW
+
+#define NAT_NOT_FOUND_DROP
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW
+
+#define SP_NOT_FOUND_DROP
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW
+
+#define IGMP_LEAVE_DROP
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW
+
+#define ARL_UNI_LEAKY
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1
+#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW
+
+#define ARL_MUL_LEAKY
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1
+#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW
+
+#define CPU_PORT_EN
+#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10
+#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1
+#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW
+
+#define PPPOE_RDT_EN
+#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8
+#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1
+#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW
+
+#define IGMP_COPY_EN
+#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3
+#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1
+#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW
+
+#define RIP_CPY_EN
+#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2
+#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1
+#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW
+
+#define EAPOL_CMD
+#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0
+#define FORWARD_CTL0_EAPOL_CMD_BLEN 1
+#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW
+
+ /* Global Forward Control1 Register */
+#define FORWARD_CTL1
+#define FORWARD_CTL1_OFFSET 0x0624
+#define FORWARD_CTL1_E_LENGTH 4
+#define FORWARD_CTL1_E_OFFSET 0
+#define FORWARD_CTL1_NR_E 1
+
+#define IGMP_DP
+#define FORWARD_CTL1_IGMP_DP_BOFFSET 24
+#define FORWARD_CTL1_IGMP_DP_BLEN 7
+#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW
+
+#define BC_FLOOD_DP
+#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16
+#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW
+
+#define MUL_FLOOD_DP
+#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8
+#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW
+
+#define UNI_FLOOD_DP
+#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0
+#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW
+
+
+
+
+ /* Global Learn Limit Ctl Register */
+#define GLOBAL_LEARN_LIMIT_CTL
+#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628
+#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4
+#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0
+#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1
+
+#define GOL_SA_LEARN_LIMIT_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW
+
+#define GOL_SA_LEARN_LIMIT_DROP_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 11
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define GOL_SA_LEARN_CNT
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 11
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW
+
+
+
+
+ /* DSCP To Priority Register */
+#define DSCP_TO_PRI
+#define DSCP_TO_PRI_OFFSET 0x0630
+#define DSCP_TO_PRI_E_LENGTH 4
+#define DSCP_TO_PRI_E_OFFSET 0x0004
+#define DSCP_TO_PRI_NR_E 8
+
+
+
+
+ /* UP To Priority Register */
+#define UP_TO_PRI
+#define UP_TO_PRI_OFFSET 0x0650
+#define UP_TO_PRI_E_LENGTH 4
+#define UP_TO_PRI_E_OFFSET 0x0004
+#define UP_TO_PRI_NR_E 1
+
+
+
+
+ /* Port Lookup control Register */
+#define PORT_LOOKUP_CTL
+#define PORT_LOOKUP_CTL_OFFSET 0x0660
+#define PORT_LOOKUP_CTL_E_LENGTH 4
+#define PORT_LOOKUP_CTL_E_OFFSET 0x000c
+#define PORT_LOOKUP_CTL_NR_E 7
+
+#define MULTI_DROP_EN
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW
+
+#define UNI_LEAKY_EN
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW
+
+#define MUL_LEAKY_EN
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW
+
+#define ARP_LEAKY_EN
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW
+
+#define ING_MIRROR_EN
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define PORT_LOOP_BACK
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW
+
+#define LEARN_EN
+#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20
+#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1
+#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW
+
+#define PORT_STATE
+#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16
+#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3
+#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW
+
+#define FORCE_PVLAN
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW
+
+#define DOT1Q_MODE
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW
+
+#define PORT_VID_MEM
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW
+
+
+
+
+ /* Priority Control Register */
+#define PRI_CTL
+#define PRI_CTL_OFFSET 0x0664
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x000c
+#define PRI_CTL_NR_E 7
+
+#define EG_MAC_BASE_VLAN_EN
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW
+
+#define DA_PRI_EN
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+
+
+ /* Port Learn Limit Ctl Register */
+#define PORT_LEARN_LIMIT_CTL
+#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668
+#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4
+#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c
+#define PORT_LEARN_LIMIT_CTL_NR_E 7
+
+#define IGMP_JOIN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 26
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_CNT
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 10
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW
+
+#define SA_LEARN_STATUS
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW
+
+#define SA_LEARN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW
+
+#define SA_LEARN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 10
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define SA_LEARN_CNT
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 10
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW
+
+
+
+ /* Global Trunk Ctl0 Register */
+#define GOL_TRUNK_CTL0
+#define GOL_TRUNK_CTL0_OFFSET 0x0700
+#define GOL_TRUNK_CTL0_E_LENGTH 4
+#define GOL_TRUNK_CTL0_E_OFFSET 0x4
+#define GOL_TRUNK_CTL0_NR_E 1
+
+
+ /* Global Trunk Ctl1 Register */
+#define GOL_TRUNK_CTL1
+#define GOL_TRUNK_CTL1_OFFSET 0x0704
+#define GOL_TRUNK_CTL1_E_LENGTH 4
+#define GOL_TRUNK_CTL1_E_OFFSET 0x4
+#define GOL_TRUNK_CTL1_NR_E 2
+
+
+
+
+ /* Port vlan0 Register */
+#define PORT_VLAN0
+#define PORT_VLAN0_OFFSET 0x0420
+#define PORT_VLAN0_E_LENGTH 4
+#define PORT_VLAN0_E_OFFSET 0x0008
+#define PORT_VLAN0_NR_E 7
+
+#define ING_CPRI
+#define PORT_VLAN0_ING_CPRI_BOFFSET 29
+#define PORT_VLAN0_ING_CPRI_BLEN 3
+#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW
+
+#define DEF_CVID
+#define PORT_VLAN0_DEF_CVID_BOFFSET 16
+#define PORT_VLAN0_DEF_CVID_BLEN 12
+#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW
+
+#define ING_SPRI
+#define PORT_VLAN0_ING_SPRI_BOFFSET 13
+#define PORT_VLAN0_ING_SPRI_BLEN 3
+#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW
+
+#define DEF_SVID
+#define PORT_VLAN0_DEF_SVID_BOFFSET 0
+#define PORT_VLAN0_DEF_SVID_BLEN 12
+#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW
+
+ /* Port vlan1 Register */
+#define PORT_VLAN1
+#define PORT_VLAN1_OFFSET 0x0424
+#define PORT_VLAN1_E_LENGTH 4
+#define PORT_VLAN1_E_OFFSET 0x0008
+#define PORT_VLAN1_NR_E 7
+
+#define EG_VLAN_MODE
+#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12
+#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2
+#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW
+
+#define VLAN_DIS
+#define PORT_VLAN1_VLAN_DIS_BOFFSET 11
+#define PORT_VLAN1_VLAN_DIS_BLEN 1
+#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW
+
+#define SP_CHECK_EN
+#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10
+#define PORT_VLAN1_SP_CHECK_EN_BLEN 1
+#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW
+
+#define COREP_EN
+#define PORT_VLAN1_COREP_EN_BOFFSET 9
+#define PORT_VLAN1_COREP_EN_BLEN 1
+#define PORT_VLAN1_COREP_EN_FLAG HSL_RW
+
+#define FORCE_DEF_VID
+#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8
+#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1
+#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW
+
+#define TLS_EN
+#define PORT_VLAN1_TLS_EN_BOFFSET 7
+#define PORT_VLAN1_TLS_EN_BLEN 1
+#define PORT_VLAN1_TLS_EN_FLAG HSL_RW
+
+#define PROPAGATION_EN
+#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6
+#define PORT_VLAN1_PROPAGATION_EN_BLEN 1
+#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW
+
+#define CLONE
+#define PORT_VLAN1_CLONE_BOFFSET 5
+#define PORT_VLAN1_CLONE_BLEN 1
+#define PORT_VLAN1_CLONE_FLAG HSL_RW
+
+#define PRI_PROPAGATION
+#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4
+#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1
+#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define IN_VLAN_MODE
+#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2
+#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2
+#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW
+
+
+ /* Route Default VID Register */
+#define ROUTER_DEFV
+#define ROUTER_DEFV_OFFSET 0x0c70
+#define ROUTER_DEFV_E_LENGTH 4
+#define ROUTER_DEFV_E_OFFSET 0x0004
+#define ROUTER_DEFV_NR_E 4
+
+
+ /* Route Egress VLAN Mode Register */
+#define ROUTER_EG
+#define ROUTER_EG_OFFSET 0x0c80
+#define ROUTER_EG_E_LENGTH 4
+#define ROUTER_EG_E_OFFSET 0x0004
+#define ROUTER_EG_NR_E 1
+
+
+
+
+ /* Mdio control Register */
+#define MDIO_CTRL "mctrl"
+#define MDIO_CTRL_ID 24
+#define MDIO_CTRL_OFFSET 0x0098
+#define MDIO_CTRL_E_LENGTH 4
+#define MDIO_CTRL_E_OFFSET 0
+#define MDIO_CTRL_NR_E 1
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define CMD "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET 27
+#define MDIO_CTRL_CMD_BLEN 1
+#define MDIO_CTRL_CMD_FLAG HSL_RW
+
+#define SUP_PRE "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET 26
+#define MDIO_CTRL_SUP_PRE_BLEN 1
+#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW
+
+#define PHY_ADDR "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET 21
+#define MDIO_CTRL_PHY_ADDR_BLEN 5
+#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW
+
+#define REG_ADDR "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET 16
+#define MDIO_CTRL_REG_ADDR_BLEN 5
+#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW
+
+#define DATA "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET 0
+#define MDIO_CTRL_DATA_BLEN 16
+#define MDIO_CTRL_DATA_FLAG HSL_RW
+
+
+
+
+ /* BIST control Register */
+#define BIST_CTRL "bctrl"
+#define BIST_CTRL_ID 24
+#define BIST_CTRL_OFFSET 0x00a0
+#define BIST_CTRL_E_LENGTH 4
+#define BIST_CTRL_E_OFFSET 0
+#define BIST_CTRL_NR_E 1
+
+#define BIST_BUSY "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET 31
+#define BIST_CTRL_BIST_BUSY_BLEN 1
+#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW
+
+#define ONE_ERR "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET 30
+#define BIST_CTRL_ONE_ERR_BLEN 1
+#define BIST_CTRL_ONE_ERR_FLAG HSL_RO
+
+#define ERR_MEM "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET 24
+#define BIST_CTRL_ERR_MEM_BLEN 4
+#define BIST_CTRL_ERR_MEM_FLAG HSL_RO
+
+#define PTN_EN2 "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET 22
+#define BIST_CTRL_PTN_EN2_BLEN 1
+#define BIST_CTRL_PTN_EN2_FLAG HSL_RW
+
+#define PTN_EN1 "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET 21
+#define BIST_CTRL_PTN_EN1_BLEN 1
+#define BIST_CTRL_PTN_EN1_FLAG HSL_RW
+
+#define PTN_EN0 "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET 20
+#define BIST_CTRL_PTN_EN0_BLEN 1
+#define BIST_CTRL_PTN_EN0_FLAG HSL_RW
+
+#define ERR_PTN "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET 16
+#define BIST_CTRL_ERR_PTN_BLEN 2
+#define BIST_CTRL_ERR_PTN_FLAG HSL_RO
+
+#define ERR_CNT "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET 13
+#define BIST_CTRL_ERR_CNT_BLEN 2
+#define BIST_CTRL_ERR_CNT_FLAG HSL_RO
+
+#define ERR_ADDR "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET 0
+#define BIST_CTRL_ERR_ADDR_BLEN 12
+#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO
+
+
+
+
+ /* BIST recover Register */
+#define BIST_RCV "brcv"
+#define BIST_RCV_ID 24
+#define BIST_RCV_OFFSET 0x00a4
+#define BIST_RCV_E_LENGTH 4
+#define BIST_RCV_E_OFFSET 0
+#define BIST_RCV_NR_E 1
+
+#define RCV_EN "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET 31
+#define BIST_RCV_RCV_EN_BLEN 1
+#define BIST_RCV_RCV_EN_FLAG HSL_RW
+
+#define RCV_ADDR "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET 0
+#define BIST_RCV_RCV_ADDR_BLEN 12
+#define BIST_RCV_RCV_ADDR_FLAG HSL_RW
+
+
+
+
+ /* LED control Register */
+#define LED_CTRL "ledctrl"
+#define LED_CTRL_ID 25
+#define LED_CTRL_OFFSET 0x0050
+#define LED_CTRL_E_LENGTH 4
+#define LED_CTRL_E_OFFSET 0
+#define LED_CTRL_NR_E 3
+
+#define PATTERN_EN "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET 14
+#define LED_CTRL_PATTERN_EN_BLEN 2
+#define LED_CTRL_PATTERN_EN_FLAG HSL_RW
+
+#define FULL_LIGHT_EN "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN 1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW
+
+#define HALF_LIGHT_EN "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN 1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW
+
+#define POWERON_LIGHT_EN "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW
+
+#define GE_LIGHT_EN "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10
+#define LED_CTRL_GE_LIGHT_EN_BLEN 1
+#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW
+
+#define FE_LIGHT_EN "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9
+#define LED_CTRL_FE_LIGHT_EN_BLEN 1
+#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW
+
+#define ETH_LIGHT_EN "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN 1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW
+
+#define COL_BLINK_EN "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET 7
+#define LED_CTRL_COL_BLINK_EN_BLEN 1
+#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW
+
+#define RX_BLINK_EN "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET 5
+#define LED_CTRL_RX_BLINK_EN_BLEN 1
+#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW
+
+#define TX_BLINK_EN "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET 4
+#define LED_CTRL_TX_BLINK_EN_BLEN 1
+#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW
+
+#define LINKUP_OVER_EN "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN 1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW
+
+#define BLINK_FREQ "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET 0
+#define LED_CTRL_BLINK_FREQ_BLEN 2
+#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW
+
+ /* LED control Register */
+#define LED_PATTERN "ledpatten"
+#define LED_PATTERN_ID 25
+#define LED_PATTERN_OFFSET 0x005c
+#define LED_PATTERN_E_LENGTH 4
+#define LED_PATTERN_E_OFFSET 0
+#define LED_PATTERN_NR_E 1
+
+
+#define P3L2_MODE
+#define LED_PATTERN_P3L2_MODE_BOFFSET 24
+#define LED_PATTERN_P3L2_MODE_BLEN 2
+#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW
+
+#define P3L1_MODE
+#define LED_PATTERN_P3L1_MODE_BOFFSET 22
+#define LED_PATTERN_P3L1_MODE_BLEN 2
+#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW
+
+#define P3L0_MODE
+#define LED_PATTERN_P3L0_MODE_BOFFSET 20
+#define LED_PATTERN_P3L0_MODE_BLEN 2
+#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW
+
+#define P2L2_MODE
+#define LED_PATTERN_P2L2_MODE_BOFFSET 18
+#define LED_PATTERN_P2L2_MODE_BLEN 2
+#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW
+
+#define P2L1_MODE
+#define LED_PATTERN_P2L1_MODE_BOFFSET 16
+#define LED_PATTERN_P2L1_MODE_BLEN 2
+#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW
+
+#define P2L0_MODE
+#define LED_PATTERN_P2L0_MODE_BOFFSET 14
+#define LED_PATTERN_P2L0_MODE_BLEN 2
+#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW
+
+#define P1L2_MODE
+#define LED_PATTERN_P1L2_MODE_BOFFSET 12
+#define LED_PATTERN_P1L2_MODE_BLEN 2
+#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW
+
+#define P1L1_MODE
+#define LED_PATTERN_P1L1_MODE_BOFFSET 10
+#define LED_PATTERN_P1L1_MODE_BLEN 2
+#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW
+
+#define P1L0_MODE
+#define LED_PATTERN_P1L0_MODE_BOFFSET 8
+#define LED_PATTERN_P1L0_MODE_BLEN 2
+#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW
+
+
+
+
+ /* Pri To Queue Register */
+#define PRI_TO_QUEUE
+#define PRI_TO_QUEUE_OFFSET 0x0814
+#define PRI_TO_QUEUE_E_LENGTH 4
+#define PRI_TO_QUEUE_E_OFFSET 0x0004
+#define PRI_TO_QUEUE_NR_E 1
+
+
+
+
+ /* Pri To EhQueue Register */
+#define PRI_TO_EHQUEUE
+#define PRI_TO_EHQUEUE_OFFSET 0x0810
+#define PRI_TO_EHQUEUE_E_LENGTH 4
+#define PRI_TO_EHQUEUE_E_OFFSET 0x0004
+#define PRI_TO_EHQUEUE_NR_E 1
+
+
+
+
+ /* Port HOL CTL0 Register */
+#define PORT_HOL_CTL0
+#define PORT_HOL_CTL0_OFFSET 0x0970
+#define PORT_HOL_CTL0_E_LENGTH 4
+#define PORT_HOL_CTL0_E_OFFSET 0x0008
+#define PORT_HOL_CTL0_NR_E 7
+
+#define PORT_DESC_NR
+#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24
+#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6
+#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW
+
+#define QUEUE5_DESC_NR
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW
+
+#define QUEUE4_DESC_NR
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW
+
+#define QUEUE3_DESC_NR
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW
+
+#define QUEUE2_DESC_NR
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW
+
+#define QUEUE1_DESC_NR
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW
+
+#define QUEUE0_DESC_NR
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW
+
+ /* Port HOL CTL1 Register */
+#define PORT_HOL_CTL1
+#define PORT_HOL_CTL1_OFFSET 0x0974
+#define PORT_HOL_CTL1_E_LENGTH 4
+#define PORT_HOL_CTL1_E_OFFSET 0x0008
+#define PORT_HOL_CTL1_NR_E 7
+
+#define EG_MIRROR_EN
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1
+#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW
+
+#define PORT_DESC_EN
+#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7
+#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1
+#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW
+
+#define QUEUE_DESC_EN
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW
+
+#define PORT_IN_DESC_EN
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW
+
+
+
+
+ /* Port Rate Limit0 Register */
+#define RATE_LIMIT0 "rlmt0"
+#define RATE_LIMIT0_ID 32
+#define RATE_LIMIT0_OFFSET 0x0110
+#define RATE_LIMIT0_E_LENGTH 4
+#define RATE_LIMIT0_E_OFFSET 0x0100
+#define RATE_LIMIT0_NR_E 7
+
+
+#define EG_RATE_EN "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW
+
+#define EG_MNG_RATE_EN "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MNG_RATE_EN "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MUL_RATE_EN "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET 0
+#define RATE_LIMIT0_ING_RATE_BLEN 15
+#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW
+
+
+
+
+
+
+
+
+
+
+ /* mib memory info */
+#define MIB_RXBROAD
+#define MIB_RXBROAD_OFFSET 0x01000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0x100
+#define MIB_RXBROAD_NR_E 7
+
+#define MIB_RXPAUSE
+#define MIB_RXPAUSE_OFFSET 0x01004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0x100
+#define MIB_RXPAUSE_NR_E 7
+
+#define MIB_RXMULTI
+#define MIB_RXMULTI_OFFSET 0x01008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0x100
+#define MIB_RXMULTI_NR_E 7
+
+#define MIB_RXFCSERR
+#define MIB_RXFCSERR_OFFSET 0x0100c
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0x100
+#define MIB_RXFCSERR_NR_E 7
+
+#define MIB_RXALLIGNERR
+#define MIB_RXALLIGNERR_OFFSET 0x01010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0x100
+#define MIB_RXALLIGNERR_NR_E 7
+
+#define MIB_RXRUNT
+#define MIB_RXRUNT_OFFSET 0x01014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0x100
+#define MIB_RXRUNT_NR_E 7
+
+#define MIB_RXFRAGMENT
+#define MIB_RXFRAGMENT_OFFSET 0x01018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0x100
+#define MIB_RXFRAGMENT_NR_E 7
+
+#define MIB_RX64BYTE
+#define MIB_RX64BYTE_OFFSET 0x0101c
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0x100
+#define MIB_RX64BYTE_NR_E 7
+
+#define MIB_RX128BYTE
+#define MIB_RX128BYTE_OFFSET 0x01020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0x100
+#define MIB_RX128BYTE_NR_E 7
+
+#define MIB_RX256BYTE
+#define MIB_RX256BYTE_OFFSET 0x01024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0x100
+#define MIB_RX256BYTE_NR_E 7
+
+#define MIB_RX512BYTE
+#define MIB_RX512BYTE_OFFSET 0x01028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0x100
+#define MIB_RX512BYTE_NR_E 7
+
+#define MIB_RX1024BYTE
+#define MIB_RX1024BYTE_OFFSET 0x0102c
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0x100
+#define MIB_RX1024BYTE_NR_E 7
+
+#define MIB_RX1518BYTE
+#define MIB_RX1518BYTE_OFFSET 0x01030
+#define MIB_RX1518BYTE_E_LENGTH 4
+#define MIB_RX1518BYTE_E_OFFSET 0x100
+#define MIB_RX1518BYTE_NR_E 7
+
+#define MIB_RXMAXBYTE
+#define MIB_RXMAXBYTE_OFFSET 0x01034
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0x100
+#define MIB_RXMAXBYTE_NR_E 7
+
+#define MIB_RXTOOLONG
+#define MIB_RXTOOLONG_OFFSET 0x01038
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0x100
+#define MIB_RXTOOLONG_NR_E 7
+
+#define MIB_RXGOODBYTE_LO
+#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_LO_NR_E 7
+
+#define MIB_RXGOODBYTE_HI
+#define MIB_RXGOODBYTE_HI_OFFSET 0x01040
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_HI_NR_E 7
+
+#define MIB_RXBADBYTE_LO
+#define MIB_RXBADBYTE_LO_OFFSET 0x01044
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0x100
+#define MIB_RXBADBYTE_LO_NR_E 7
+
+#define MIB_RXBADBYTE_HI
+#define MIB_RXBADBYTE_HI_OFFSET 0x01048
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0x100
+#define MIB_RXBADBYTE_HI_NR_E 7
+
+#define MIB_RXOVERFLOW
+#define MIB_RXOVERFLOW_OFFSET 0x0104c
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0x100
+#define MIB_RXOVERFLOW_NR_E 7
+
+#define MIB_FILTERED
+#define MIB_FILTERED_OFFSET 0x01050
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0x100
+#define MIB_FILTERED_NR_E 7
+
+#define MIB_TXBROAD
+#define MIB_TXBROAD_OFFSET 0x01054
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0x100
+#define MIB_TXBROAD_NR_E 7
+
+#define MIB_TXPAUSE
+#define MIB_TXPAUSE_OFFSET 0x01058
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0x100
+#define MIB_TXPAUSE_NR_E 7
+
+#define MIB_TXMULTI
+#define MIB_TXMULTI_OFFSET 0x0105c
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0x100
+#define MIB_TXMULTI_NR_E 7
+
+#define MIB_TXUNDERRUN
+#define MIB_TXUNDERRUN_OFFSET 0x01060
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0x100
+#define MIB_TXUNDERRUN_NR_E 7
+
+#define MIB_TX64BYTE
+#define MIB_TX64BYTE_OFFSET 0x01064
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0x100
+#define MIB_TX64BYTE_NR_E 7
+
+#define MIB_TX128BYTE
+#define MIB_TX128BYTE_OFFSET 0x01068
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0x100
+#define MIB_TX128BYTE_NR_E 7
+
+#define MIB_TX256BYTE
+#define MIB_TX256BYTE_OFFSET 0x0106c
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0x100
+#define MIB_TX256BYTE_NR_E 7
+
+#define MIB_TX512BYTE
+#define MIB_TX512BYTE_OFFSET 0x01070
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0x100
+#define MIB_TX512BYTE_NR_E 7
+
+#define MIB_TX1024BYTE
+#define MIB_TX1024BYTE_OFFSET 0x01074
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0x100
+#define MIB_TX1024BYTE_NR_E 7
+
+#define MIB_TX1518BYTE
+#define MIB_TX1518BYTE_OFFSET 0x01078
+#define MIB_TX1518BYTE_E_LENGTH 4
+#define MIB_TX1518BYTE_E_OFFSET 0x100
+#define MIB_TX1518BYTE_NR_E 7
+
+#define MIB_TXMAXBYTE
+#define MIB_TXMAXBYTE_OFFSET 0x0107c
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0x100
+#define MIB_TXMAXBYTE_NR_E 7
+
+#define MIB_TXOVERSIZE
+#define MIB_TXOVERSIZE_OFFSET 0x01080
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0x100
+#define MIB_TXOVERSIZE_NR_E 7
+
+#define MIB_TXBYTE_LO
+#define MIB_TXBYTE_LO_OFFSET 0x01084
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0x100
+#define MIB_TXBYTE_LO_NR_E 7
+
+#define MIB_TXBYTE_HI
+#define MIB_TXBYTE_HI_OFFSET 0x01088
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0x100
+#define MIB_TXBYTE_HI_NR_E 7
+
+#define MIB_TXCOLLISION
+#define MIB_TXCOLLISION_OFFSET 0x0108c
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0x100
+#define MIB_TXCOLLISION_NR_E 7
+
+#define MIB_TXABORTCOL
+#define MIB_TXABORTCOL_OFFSET 0x01090
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0x100
+#define MIB_TXABORTCOL_NR_E 7
+
+#define MIB_TXMULTICOL
+#define MIB_TXMULTICOL_OFFSET 0x01094
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0x100
+#define MIB_TXMULTICOL_NR_E 7
+
+#define MIB_TXSINGALCOL
+#define MIB_TXSINGALCOL_OFFSET 0x01098
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0x100
+#define MIB_TXSINGALCOL_NR_E 7
+
+#define MIB_TXEXCDEFER
+#define MIB_TXEXCDEFER_OFFSET 0x0109c
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0x100
+#define MIB_TXEXCDEFER_NR_E 7
+
+#define MIB_TXDEFER
+#define MIB_TXDEFER_OFFSET 0x010a0
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0x100
+#define MIB_TXDEFER_NR_E 7
+
+#define MIB_TXLATECOL
+#define MIB_TXLATECOL_OFFSET 0x010a4
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0x100
+#define MIB_TXLATECOL_NR_E 7
+
+
+
+ /* ACL Action Register */
+#define ACL_RSLT0 10
+#define ACL_RSLT0_OFFSET 0x5a000
+#define ACL_RSLT0_E_LENGTH 4
+#define ACL_RSLT0_E_OFFSET 0x10
+#define ACL_RSLT0_NR_E 96
+
+#define CTAGPRI
+#define ACL_RSLT0_CTAGPRI_BOFFSET 29
+#define ACL_RSLT0_CTAGPRI_BLEN 3
+#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW
+
+#define CTAGCFI
+#define ACL_RSLT0_CTAGCFI_BOFFSET 28
+#define ACL_RSLT0_CTAGCFI_BLEN 1
+#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW
+
+#define CTAGVID
+#define ACL_RSLT0_CTAGVID_BOFFSET 16
+#define ACL_RSLT0_CTAGVID_BLEN 12
+#define ACL_RSLT0_CTAGVID_FLAG HSL_RW
+
+#define STAGPRI
+#define ACL_RSLT0_STAGPRI_BOFFSET 13
+#define ACL_RSLT0_STAGPRI_BLEN 3
+#define ACL_RSLT0_STAGPRI_FLAG HSL_RW
+
+#define STAGDEI
+#define ACL_RSLT0_STAGDEI_BOFFSET 12
+#define ACL_RSLT0_STAGDEI_BLEN 1
+#define ACL_RSLT0_STAGDEI_FLAG HSL_RW
+
+#define STAGVID
+#define ACL_RSLT0_STAGVID_BOFFSET 0
+#define ACL_RSLT0_STAGVID_BLEN 12
+#define ACL_RSLT0_STAGVID_FLAG HSL_RW
+
+
+#define ACL_RSLT1 11
+#define ACL_RSLT1_OFFSET 0x5a004
+#define ACL_RSLT1_E_LENGTH 4
+#define ACL_RSLT1_E_OFFSET 0x10
+#define ACL_RSLT1_NR_E 96
+
+#define DES_PORT0
+#define ACL_RSLT1_DES_PORT0_BOFFSET 29
+#define ACL_RSLT1_DES_PORT0_BLEN 3
+#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW
+
+#define PRI_QU_EN
+#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28
+#define ACL_RSLT1_PRI_QU_EN_BLEN 1
+#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW
+
+#define PRI_QU
+#define ACL_RSLT1_PRI_QU_BOFFSET 25
+#define ACL_RSLT1_PRI_QU_BLEN 3
+#define ACL_RSLT1_PRI_QU_FLAG HSL_RW
+
+#define WCMP_EN
+#define ACL_RSLT1_WCMP_EN_BOFFSET 24
+#define ACL_RSLT1_WCMP_EN_BLEN 1
+#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW
+
+#define ARP_PTR
+#define ACL_RSLT1_ARP_PTR_BOFFSET 17
+#define ACL_RSLT1_ARP_PTR_BLEN 7
+#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW
+
+#define ARP_PTR_EN
+#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16
+#define ACL_RSLT1_ARP_PTR_EN_BLEN 1
+#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW
+
+#define FORCE_L3_MODE
+#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14
+#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2
+#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW
+
+#define LOOK_VID_CHG
+#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13
+#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1
+#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW
+
+#define TRANS_CVID_CHG
+#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12
+#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1
+#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW
+
+#define TRANS_SVID_CHG
+#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11
+#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1
+#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW
+
+#define CTAG_CFI_CHG
+#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10
+#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1
+#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW
+
+#define CTAG_PRI_REMAP
+#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9
+#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1
+#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW
+
+#define STAG_DEI_CHG
+#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8
+#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1
+#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW
+
+#define STAG_PRI_REMAP
+#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7
+#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1
+#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW
+
+#define DSCP_REMAP
+#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6
+#define ACL_RSLT1_DSCP_REMAP_BLEN 1
+#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW
+
+#define DSCPV
+#define ACL_RSLT1_DSCPV_BOFFSET 0
+#define ACL_RSLT1_DSCPV_BLEN 6
+#define ACL_RSLT1_DSCPV_FLAG HSL_RW
+
+#define ACL_RSLT2 12
+#define ACL_RSLT2_OFFSET 0x5a008
+#define ACL_RSLT2_E_LENGTH 4
+#define ACL_RSLT2_E_OFFSET 0x10
+#define ACL_RSLT2_NR_E 96
+
+#define TRIGGER_INTR
+#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16
+#define ACL_RSLT2_TRIGGER_INTR_BLEN 1
+#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW
+
+#define EG_BYPASS
+#define ACL_RSLT2_EG_BYPASS_BOFFSET 15
+#define ACL_RSLT2_EG_BYPASS_BLEN 1
+#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW
+
+#define POLICER_EN
+#define ACL_RSLT2_POLICER_EN_BOFFSET 14
+#define ACL_RSLT2_POLICER_EN_BLEN 1
+#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW
+
+#define POLICER_PTR
+#define ACL_RSLT2_POLICER_PTR_BOFFSET 9
+#define ACL_RSLT2_POLICER_PTR_BLEN 5
+#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW
+
+#define FWD_CMD
+#define ACL_RSLT2_FWD_CMD_BOFFSET 6
+#define ACL_RSLT2_FWD_CMD_BLEN 3
+#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW
+
+#define MIRR_EN
+#define ACL_RSLT2_MIRR_EN_BOFFSET 5
+#define ACL_RSLT2_MIRR_EN_BLEN 1
+#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW
+
+#define DES_PORT_EN
+#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4
+#define ACL_RSLT2_DES_PORT_EN_BLEN 1
+#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW
+
+#define DES_PORT1
+#define ACL_RSLT2_DES_PORT1_BOFFSET 0
+#define ACL_RSLT2_DES_PORT1_BLEN 4
+#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW
+
+
+
+
+ /* MAC Type Rule Field Define */
+#define MAC_RUL_V0 0
+#define MAC_RUL_V0_OFFSET 0x58000
+#define MAC_RUL_V0_E_LENGTH 4
+#define MAC_RUL_V0_E_OFFSET 0x20
+#define MAC_RUL_V0_NR_E 96
+
+#define DAV_BYTE2
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+#define MAC_RUL_V1 1
+#define MAC_RUL_V1_OFFSET 0x58004
+#define MAC_RUL_V1_E_LENGTH 4
+#define MAC_RUL_V1_E_OFFSET 0x20
+#define MAC_RUL_V1_NR_E 96
+
+#define SAV_BYTE4
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+#define MAC_RUL_V2 2
+#define MAC_RUL_V2_OFFSET 0x58008
+#define MAC_RUL_V2_E_LENGTH 4
+#define MAC_RUL_V2_E_OFFSET 0x20
+#define MAC_RUL_V2_NR_E 96
+
+#define SAV_BYTE0
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW
+
+#define SAV_BYTE1
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW
+
+#define SAV_BYTE2
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW
+
+#define SAV_BYTE3
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+#define MAC_RUL_V3 3
+#define MAC_RUL_V3_ID 13
+#define MAC_RUL_V3_OFFSET 0x5800c
+#define MAC_RUL_V3_E_LENGTH 4
+#define MAC_RUL_V3_E_OFFSET 0x20
+#define MAC_RUL_V3_NR_E 96
+
+#define ETHTYPV
+#define MAC_RUL_V3_ETHTYPV_BOFFSET 16
+#define MAC_RUL_V3_ETHTYPV_BLEN 16
+#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define VLANPRIV
+#define MAC_RUL_V3_VLANPRIV_BOFFSET 13
+#define MAC_RUL_V3_VLANPRIV_BLEN 3
+#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW
+
+#define VLANCFIV
+#define MAC_RUL_V3_VLANCFIV_BOFFSET 12
+#define MAC_RUL_V3_VLANCFIV_BLEN 1
+#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW
+
+#define VLANIDV
+#define MAC_RUL_V3_VLANIDV_BOFFSET 0
+#define MAC_RUL_V3_VLANIDV_BLEN 12
+#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW
+
+
+#define MAC_RUL_V4 4
+#define MAC_RUL_V4_OFFSET 0x58010
+#define MAC_RUL_V4_E_LENGTH 4
+#define MAC_RUL_V4_E_OFFSET 0x20
+#define MAC_RUL_V4_NR_E 96
+
+#define RULE_INV
+#define MAC_RUL_V4_RULE_INV_BOFFSET 7
+#define MAC_RUL_V4_RULE_INV_BLEN 1
+#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW
+
+#define SRC_PT
+#define MAC_RUL_V4_SRC_PT_BOFFSET 0
+#define MAC_RUL_V4_SRC_PT_BLEN 7
+#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW
+
+
+#define MAC_RUL_M0 5
+#define MAC_RUL_M0_OFFSET 0x59000
+#define MAC_RUL_M0_E_LENGTH 4
+#define MAC_RUL_M0_E_OFFSET 0x20
+#define MAC_RUL_M0_NR_E 96
+
+#define DAM_BYTE2
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+#define MAC_RUL_M1 6
+#define MAC_RUL_M1_OFFSET 0x59004
+#define MAC_RUL_M1_E_LENGTH 4
+#define MAC_RUL_M1_E_OFFSET 0x20
+#define MAC_RUL_M1_NR_E 96
+
+#define SAM_BYTE4
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+#define MAC_RUL_M2 7
+#define MAC_RUL_M2_OFFSET 0x59008
+#define MAC_RUL_M2_E_LENGTH 4
+#define MAC_RUL_M2_E_OFFSET 0x20
+#define MAC_RUL_M2_NR_E 96
+
+#define SAM_BYTE0
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW
+
+#define SAM_BYTE1
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW
+
+#define SAM_BYTE2
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW
+
+#define SAM_BYTE3
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+#define MAC_RUL_M3 8
+#define MAC_RUL_M3_OFFSET 0x5900c
+#define MAC_RUL_M3_E_LENGTH 4
+#define MAC_RUL_M3_E_OFFSET 0x20
+#define MAC_RUL_M3_NR_E 96
+
+#define ETHTYPM
+#define MAC_RUL_M3_ETHTYPM_BOFFSET 16
+#define MAC_RUL_M3_ETHTYPM_BLEN 16
+#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define VLANPRIM
+#define MAC_RUL_M3_VLANPRIM_BOFFSET 13
+#define MAC_RUL_M3_VLANPRIM_BLEN 3
+#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW
+
+#define VLANCFIM
+#define MAC_RUL_M3_VLANCFIM_BOFFSET 12
+#define MAC_RUL_M3_VLANCFIM_BLEN 1
+#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW
+
+#define VLANIDM
+#define MAC_RUL_M3_VLANIDM_BOFFSET 0
+#define MAC_RUL_M3_VLANIDM_BLEN 12
+#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW
+
+
+#define MAC_RUL_M4 9
+#define MAC_RUL_M4_OFFSET 0x59010
+#define MAC_RUL_M4_E_LENGTH 4
+#define MAC_RUL_M4_E_OFFSET 0x20
+#define MAC_RUL_M4_NR_E 96
+
+#define RULE_VALID
+#define MAC_RUL_M4_RULE_VALID_BOFFSET 6
+#define MAC_RUL_M4_RULE_VALID_BLEN 2
+#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW
+
+#define TAGGEDM
+#define MAC_RUL_M4_TAGGEDM_BOFFSET 5
+#define MAC_RUL_M4_TAGGEDM_BLEN 1
+#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW
+
+#define TAGGEDV
+#define MAC_RUL_M4_TAGGEDV_BOFFSET 4
+#define MAC_RUL_M4_TAGGEDV_BLEN 1
+#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW
+
+#define VIDMSK
+#define MAC_RUL_M4_VIDMSK_BOFFSET 3
+#define MAC_RUL_M4_VIDMSK_BLEN 1
+#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW
+
+#define RULE_TYP
+#define MAC_RUL_M4_RULE_TYP_BOFFSET 0
+#define MAC_RUL_M4_RULE_TYP_BLEN 3
+#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW
+
+
+
+
+ /* IP4 Type Rule Field Define */
+#define IP4_RUL_V0 0
+#define IP4_RUL_V0_OFFSET 0x58000
+#define IP4_RUL_V0_E_LENGTH 4
+#define IP4_RUL_V0_E_OFFSET 0x20
+#define IP4_RUL_V0_NR_E 96
+
+#define DIPV
+#define IP4_RUL_V0_DIPV_BOFFSET 0
+#define IP4_RUL_V0_DIPV_BLEN 32
+#define IP4_RUL_V0_DIPV_FLAG HSL_RW
+
+
+#define IP4_RUL_V1 1
+#define IP4_RUL_V1_OFFSET 0x58004
+#define IP4_RUL_V1_E_LENGTH 4
+#define IP4_RUL_V1_E_OFFSET 0x20
+#define IP4_RUL_V1_NR_E 96
+
+#define SIPV
+#define IP4_RUL_V1_SIPV_BOFFSET 0
+#define IP4_RUL_V1_SIPV_BLEN 32
+#define IP4_RUL_V1_SIPV_FLAG HSL_RW
+
+
+#define IP4_RUL_V2 2
+#define IP4_RUL_V2_OFFSET 0x58008
+#define IP4_RUL_V2_E_LENGTH 4
+#define IP4_RUL_V2_E_OFFSET 0x20
+#define IP4_RUL_V2_NR_E 96
+
+#define IP4PROTV
+#define IP4_RUL_V2_IP4PROTV_BOFFSET 0
+#define IP4_RUL_V2_IP4PROTV_BLEN 8
+#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW
+
+#define IP4DSCPV
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8
+#define IP4_RUL_V2_IP4DSCPV_BLEN 8
+#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW
+
+#define IP4DPORTV
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16
+#define IP4_RUL_V2_IP4DPORTV_BLEN 16
+#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW
+
+
+#define IP4_RUL_V3 3
+#define IP4_RUL_V3_OFFSET 0x5800c
+#define IP4_RUL_V3_E_LENGTH 4
+#define IP4_RUL_V3_E_OFFSET 0x20
+#define IP4_RUL_V3_NR_E 96
+
+#define IP4TCPFLAGV
+#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24
+#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6
+#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW
+
+#define IP4DHCPV
+#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22
+#define IP4_RUL_V3_IP4DHCPV_BLEN 1
+#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW
+
+#define IP4RIPV
+#define IP4_RUL_V3_IP4RIPV_BOFFSET 21
+#define IP4_RUL_V3_IP4RIPV_BLEN 1
+#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW
+
+#define ICMP_EN
+#define IP4_RUL_V3_ICMP_EN_BOFFSET 20
+#define IP4_RUL_V3_ICMP_EN_BLEN 1
+#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW
+
+#define IP4SPORTV
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0
+#define IP4_RUL_V3_IP4SPORTV_BLEN 16
+#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW
+
+#define IP4ICMPTYPV
+#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8
+#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8
+#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW
+
+#define IP4ICMPCODEV
+#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0
+#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8
+#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW
+
+
+#define IP4_RUL_V4 4
+#define IP4_RUL_V4_OFFSET 0x58010
+#define IP4_RUL_V4_E_LENGTH 4
+#define IP4_RUL_V4_E_OFFSET 0x20
+#define IP4_RUL_V4_NR_E 96
+
+
+#define IP4_RUL_M0 5
+#define IP4_RUL_M0_OFFSET 0x59000
+#define IP4_RUL_M0_E_LENGTH 4
+#define IP4_RUL_M0_E_OFFSET 0x20
+#define IP4_RUL_M0_NR_E 96
+
+#define DIPM
+#define IP4_RUL_M0_DIPM_BOFFSET 0
+#define IP4_RUL_M0_DIPM_BLEN 32
+#define IP4_RUL_M0_DIPM_FLAG HSL_RW
+
+
+#define IP4_RUL_M1 6
+#define IP4_RUL_M1_OFFSET 0x59004
+#define IP4_RUL_M1_E_LENGTH 4
+#define IP4_RUL_M1_E_OFFSET 0x20
+#define IP4_RUL_M1_NR_E 96
+
+#define SIPM
+#define IP4_RUL_M1_SIPM_BOFFSET 0
+#define IP4_RUL_M1_SIPM_BLEN 32
+#define IP4_RUL_M1_SIPM_FLAG HSL_RW
+
+
+#define IP4_RUL_M2 7
+#define IP4_RUL_M2_OFFSET 0x59008
+#define IP4_RUL_M2_E_LENGTH 4
+#define IP4_RUL_M2_E_OFFSET 0x20
+#define IP4_RUL_M2_NR_E 96
+
+#define IP4PROTM
+#define IP4_RUL_M2_IP4PROTM_BOFFSET 0
+#define IP4_RUL_M2_IP4PROTM_BLEN 8
+#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW
+
+#define IP4DSCPM
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8
+#define IP4_RUL_M2_IP4DSCPM_BLEN 8
+#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW
+
+#define IP4DPORTM
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16
+#define IP4_RUL_M2_IP4DPORTM_BLEN 16
+#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW
+
+
+#define IP4_RUL_M3 8
+#define IP4_RUL_M3_OFFSET 0x5900c
+#define IP4_RUL_M3_E_LENGTH 4
+#define IP4_RUL_M3_E_OFFSET 0x20
+#define IP4_RUL_M3_NR_E 96
+
+#define IP4TCPFLAGM
+#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24
+#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6
+#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW
+
+#define IP4DHCPM
+#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22
+#define IP4_RUL_M3_IP4DHCPM_BLEN 1
+#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW
+
+#define IP4RIPM
+#define IP4_RUL_M3_IP4RIPM_BOFFSET 21
+#define IP4_RUL_M3_IP4RIPM_BLEN 1
+#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW
+
+#define IP4DPORTM_EN
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW
+
+#define IP4SPORTM_EN
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW
+
+#define IP4SPORTM
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0
+#define IP4_RUL_M3_IP4SPORTM_BLEN 16
+#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW
+
+#define IP4ICMPTYPM
+#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8
+#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8
+#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW
+
+#define IP4ICMPCODEM
+#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0
+#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8
+#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW
+
+
+#define IP4_RUL_M4 9
+#define IP4_RUL_M4_OFFSET 0x59010
+#define IP4_RUL_M4_E_LENGTH 4
+#define IP4_RUL_M4_E_OFFSET 0x20
+#define IP4_RUL_M4_NR_E 32
+
+
+
+
+ /* IP6 Type1 Rule Field Define */
+#define IP6_RUL1_V0 0
+#define IP6_RUL1_V0_OFFSET 0x58000
+#define IP6_RUL1_V0_E_LENGTH 4
+#define IP6_RUL1_V0_E_OFFSET 0x20
+#define IP6_RUL1_V0_NR_E 96
+
+#define IP6_DIPV0
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW
+
+
+#define IP6_RUL1_V1 1
+#define IP6_RUL1_V1_OFFSET 0x58004
+#define IP6_RUL1_V1_E_LENGTH 4
+#define IP6_RUL1_V1_E_OFFSET 0x20
+#define IP6_RUL1_V1_NR_E 96
+
+#define IP6_DIPV1
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW
+
+
+#define IP6_RUL1_V2 2
+#define IP6_RUL1_V2_OFFSET 0x58008
+#define IP6_RUL1_V2_E_LENGTH 4
+#define IP6_RUL1_V2_E_OFFSET 0x20
+#define IP6_RUL1_V2_NR_E 96
+
+#define IP6_DIPV2
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW
+
+
+#define IP6_RUL1_V3 3
+#define IP6_RUL1_V3_OFFSET 0x5800c
+#define IP6_RUL1_V3_E_LENGTH 4
+#define IP6_RUL1_V3_E_OFFSET 0x20
+#define IP6_RUL1_V3_NR_E 96
+
+#define IP6_DIPV3
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW
+
+
+#define IP6_RUL1_V4 4
+#define IP6_RUL1_V4_OFFSET 0x58010
+#define IP6_RUL1_V4_E_LENGTH 4
+#define IP6_RUL1_V4_E_OFFSET 0x20
+#define IP6_RUL1_V4_NR_E 96
+
+
+#define IP6_RUL1_M0 5
+#define IP6_RUL1_M0_OFFSET 0x59000
+#define IP6_RUL1_M0_E_LENGTH 4
+#define IP6_RUL1_M0_E_OFFSET 0x20
+#define IP6_RUL1_M0_NR_E 96
+
+#define IP6_DIPM0
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW
+
+
+#define IP6_RUL1_M1 6
+#define IP6_RUL1_M1_OFFSET 0x59004
+#define IP6_RUL1_M1_E_LENGTH 4
+#define IP6_RUL1_M1_E_OFFSET 0x20
+#define IP6_RUL1_M1_NR_E 96
+
+#define IP6_DIPM1
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+#define IP6_RUL1_M2 7
+#define IP6_RUL1_M2_OFFSET 0x59008
+#define IP6_RUL1_M2_E_LENGTH 4
+#define IP6_RUL1_M2_E_OFFSET 0x20
+#define IP6_RUL1_M2_NR_E 96
+
+#define IP6_DIPM2
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+#define IP6_RUL1_M3 8
+#define IP6_RUL1_M3_OFFSET 0x5900c
+#define IP6_RUL1_M3_E_LENGTH 4
+#define IP6_RUL1_M3_E_OFFSET 0x20
+#define IP6_RUL1_M3_NR_E 96
+
+#define IP6_DIPM3
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW
+
+
+#define IP6_RUL1_M4 9
+#define IP6_RUL1_M4_OFFSET 0x59010
+#define IP6_RUL1_M4_E_LENGTH 4
+#define IP6_RUL1_M4_E_OFFSET 0x20
+#define IP6_RUL1_M4_NR_E 96
+
+
+
+
+ /* IP6 Type2 Rule Field Define */
+#define IP6_RUL2_V0 0
+#define IP6_RUL2_V0_OFFSET 0x58000
+#define IP6_RUL2_V0_E_LENGTH 4
+#define IP6_RUL2_V0_E_OFFSET 0x20
+#define IP6_RUL2_V0_NR_E 96
+
+#define IP6_SIPV0
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW
+
+
+#define IP6_RUL2_V1 1
+#define IP6_RUL2_V1_OFFSET 0x58004
+#define IP6_RUL2_V1_E_LENGTH 4
+#define IP6_RUL2_V1_E_OFFSET 0x20
+#define IP6_RUL2_V1_NR_E 96
+
+#define IP6_SIPV1
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW
+
+
+#define IP6_RUL2_V2 2
+#define IP6_RUL2_V2_OFFSET 0x58008
+#define IP6_RUL2_V2_E_LENGTH 4
+#define IP6_RUL2_V2_E_OFFSET 0x20
+#define IP6_RUL2_V2_NR_E 96
+
+#define IP6_SIPV2
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW
+
+
+#define IP6_RUL2_V3 3
+#define IP6_RUL2_V3_OFFSET 0x5800c
+#define IP6_RUL2_V3_E_LENGTH 4
+#define IP6_RUL2_V3_E_OFFSET 0x20
+#define IP6_RUL2_V3_NR_E 96
+
+#define IP6_SIPV3
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW
+
+
+#define IP6_RUL2_V4 4
+#define IP6_RUL2_V4_OFFSET 0x58010
+#define IP6_RUL2_V4_E_LENGTH 4
+#define IP6_RUL2_V4_E_OFFSET 0x20
+#define IP6_RUL2_V4_NR_E 96
+
+
+#define IP6_RUL2_M0 5
+#define IP6_RUL2_M0_OFFSET 0x59000
+#define IP6_RUL2_M0_E_LENGTH 4
+#define IP6_RUL2_M0_E_OFFSET 0x20
+#define IP6_RUL2_M0_NR_E 96
+
+#define IP6_SIPM0
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW
+
+
+#define IP6_RUL2_M1 6
+#define IP6_RUL2_M1_OFFSET 0x59004
+#define IP6_RUL2_M1_E_LENGTH 4
+#define IP6_RUL2_M1_E_OFFSET 0x20
+#define IP6_RUL2_M1_NR_E 96
+
+#define IP6_SIPM1
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+#define IP6_RUL2_M2 7
+#define IP6_RUL2_M2_OFFSET 0x59008
+#define IP6_RUL2_M2_E_LENGTH 4
+#define IP6_RUL2_M2_E_OFFSET 0x20
+#define IP6_RUL2_M2_NR_E 96
+
+#define IP6_SIPM2
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+#define IP6_RUL2_M3 8
+#define IP6_RUL2_M3_OFFSET 0x5900c
+#define IP6_RUL2_M3_E_LENGTH 4
+#define IP6_RUL2_M3_E_OFFSET 0x20
+#define IP6_RUL2_M3_NR_E 96
+
+#define IP6_SIPM3
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW
+
+
+#define IP6_RUL2_M4 9
+#define IP6_RUL2_M4_OFFSET 0x59010
+#define IP6_RUL2_M4_E_LENGTH 4
+#define IP6_RUL2_M4_E_OFFSET 0x20
+#define IP6_RUL2_M4_NR_E 96
+
+
+
+
+ /* IP6 Type3 Rule Field Define */
+#define IP6_RUL3_V0 0
+#define IP6_RUL3_V0_OFFSET 0x58000
+#define IP6_RUL3_V0_E_LENGTH 4
+#define IP6_RUL3_V0_E_OFFSET 0x20
+#define IP6_RUL3_V0_NR_E 96
+
+#define IP6PROTV
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0
+#define IP6_RUL3_V0_IP6PROTV_BLEN 8
+#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW
+
+#define IP6DSCPV
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN 8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V1 1
+#define IP6_RUL3_V1_OFFSET 0x58004
+#define IP6_RUL3_V1_E_LENGTH 4
+#define IP6_RUL3_V1_E_OFFSET 0x20
+#define IP6_RUL3_V1_NR_E 96
+
+#define IP6LABEL1V
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW
+
+
+#define IP6_RUL3_V2 2
+#define IP6_RUL3_V2_OFFSET 0x58008
+#define IP6_RUL3_V2_E_LENGTH 4
+#define IP6_RUL3_V2_E_OFFSET 0x20
+#define IP6_RUL3_V2_NR_E 96
+
+#define IP6LABEL2V
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW
+
+#define IP6DPORTV
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN 16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V3 3
+#define IP6_RUL3_V3_OFFSET 0x5800c
+#define IP6_RUL3_V3_E_LENGTH 4
+#define IP6_RUL3_V3_E_OFFSET 0x20
+#define IP6_RUL3_V3_NR_E 96
+
+#define IP6TCPFLAGV
+#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24
+#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6
+#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW
+
+#define IP6FWDTYPV
+#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23
+#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1
+#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW
+
+#define IP6DHCPV
+#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22
+#define IP6_RUL3_V3_IP6DHCPV_BLEN 1
+#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW
+
+#define ICMP6_EN
+#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20
+#define IP6_RUL3_V3_ICMP6_EN_BLEN 1
+#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW
+
+#define IP6SPORTV
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN 16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW
+
+#define IP6ICMPTYPV
+#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8
+#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8
+#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW
+
+#define IP6ICMPCODEV
+#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0
+#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8
+#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V4 4
+#define IP6_RUL3_V4_OFFSET 0x58010
+#define IP6_RUL3_V4_E_LENGTH 4
+#define IP6_RUL3_V4_E_OFFSET 0x20
+#define IP6_RUL3_V4_NR_E 96
+
+
+#define IP6_RUL3_M0 5
+#define IP6_RUL3_M0_OFFSET 0x59000
+#define IP6_RUL3_M0_E_LENGTH 4
+#define IP6_RUL3_M0_E_OFFSET 0x20
+#define IP6_RUL3_M0_NR_E 96
+
+#define IP6PROTM
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0
+#define IP6_RUL3_M0_IP6PROTM_BLEN 8
+#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW
+
+#define IP6DSCPM
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN 8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M1 6
+#define IP6_RUL3_M1_OFFSET 0x59004
+#define IP6_RUL3_M1_E_LENGTH 4
+#define IP6_RUL3_M1_E_OFFSET 0x20
+#define IP6_RUL3_M1_NR_E 96
+
+#define IP6LABEL1M
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW
+
+
+#define IP6_RUL3_M2 7
+#define IP6_RUL3_M2_OFFSET 0x59008
+#define IP6_RUL3_M2_E_LENGTH 4
+#define IP6_RUL3_M2_E_OFFSET 0x20
+#define IP6_RUL3_M2_NR_E 96
+
+#define IP6LABEL2M
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW
+
+#define IP6DPORTM
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN 16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M3 8
+#define IP6_RUL3_M3_OFFSET 0x5900c
+#define IP6_RUL3_M3_E_LENGTH 4
+#define IP6_RUL3_M3_E_OFFSET 0x20
+#define IP6_RUL3_M3_NR_E 96
+
+#define IP6TCPFLAGM
+#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24
+#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6
+#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW
+
+#define IP6RWDTYPM
+#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23
+#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1
+#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW
+
+#define IP6DHCPM
+#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22
+#define IP6_RUL3_M3_IP6DHCPM_BLEN 1
+#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW
+
+#define IP6DPORTM_EN
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM_EN
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN 16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW
+
+#define IP6ICMPTYPM
+#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8
+#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8
+#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW
+
+#define IP6ICMPCODEM
+#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0
+#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8
+#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M4 9
+#define IP6_RUL3_M4_OFFSET 0x59010
+#define IP6_RUL3_M4_E_LENGTH 4
+#define IP6_RUL3_M4_E_OFFSET 0x20
+#define IP6_RUL3_M4_NR_E 96
+
+
+
+
+ /* Enhanced MAC Type Rule Field Define */
+#define EHMAC_RUL_V0 0
+#define EHMAC_RUL_V0_OFFSET 0x58000
+#define EHMAC_RUL_V0_E_LENGTH 4
+#define EHMAC_RUL_V0_E_OFFSET 0x20
+#define EHMAC_RUL_V0_NR_E 96
+
+#define DAV_BYTE2
+#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3
+#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4
+#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5
+#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V1 1
+#define EHMAC_RUL_V1_OFFSET 0x58004
+#define EHMAC_RUL_V1_E_LENGTH 4
+#define EHMAC_RUL_V1_E_OFFSET 0x20
+#define EHMAC_RUL_V1_NR_E 96
+
+#define SAV_BYTE4
+#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5
+#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0
+#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1
+#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V2 2
+#define EHMAC_RUL_V2_OFFSET 0x58008
+#define EHMAC_RUL_V2_E_LENGTH 4
+#define EHMAC_RUL_V2_E_OFFSET 0x20
+#define EHMAC_RUL_V2_NR_E 96
+
+#define CTAG_VIDLV
+#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24
+#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8
+#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW
+
+#define STAG_PRIV
+#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21
+#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3
+#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW
+
+#define STAG_DEIV
+#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20
+#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1
+#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW
+
+#define STAG_VIDV
+#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8
+#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12
+#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW
+
+#define SAV_BYTE3
+#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V3 3
+#define EHMAC_RUL_V3_ID 13
+#define EHMAC_RUL_V3_OFFSET 0x5800c
+#define EHMAC_RUL_V3_E_LENGTH 4
+#define EHMAC_RUL_V3_E_OFFSET 0x20
+#define EHMAC_RUL_V3_NR_E 96
+
+#define STAGGEDM
+#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31
+#define EHMAC_RUL_V3_STAGGEDM_BLEN 1
+#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW
+
+#define STAGGEDV
+#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30
+#define EHMAC_RUL_V3_STAGGEDV_BLEN 1
+#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW
+
+#define DA_EN
+#define EHMAC_RUL_V3_DA_EN_BOFFSET 25
+#define EHMAC_RUL_V3_DA_EN_BLEN 1
+#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW
+
+#define SVIDMSK
+#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24
+#define EHMAC_RUL_V3_SVIDMSK_BLEN 1
+#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW
+
+#define ETHTYPV
+#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8
+#define EHMAC_RUL_V3_ETHTYPV_BLEN 16
+#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define CTAG_PRIV
+#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5
+#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3
+#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW
+
+#define CTAG_CFIV
+#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4
+#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1
+#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW
+
+#define CTAG_VIDHV
+#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0
+#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4
+#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V4 4
+#define EHMAC_RUL_V4_OFFSET 0x58010
+#define EHMAC_RUL_V4_E_LENGTH 4
+#define EHMAC_RUL_V4_E_OFFSET 0x20
+#define EHMAC_RUL_V4_NR_E 96
+
+
+#define EHMAC_RUL_M0 5
+#define EHMAC_RUL_M0_OFFSET 0x59000
+#define EHMAC_RUL_M0_E_LENGTH 4
+#define EHMAC_RUL_M0_E_OFFSET 0x20
+#define EHMAC_RUL_M0_NR_E 96
+
+#define DAM_BYTE2
+#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3
+#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4
+#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5
+#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M1 6
+#define EHMAC_RUL_M1_OFFSET 0x59004
+#define EHMAC_RUL_M1_E_LENGTH 4
+#define EHMAC_RUL_M1_E_OFFSET 0x20
+#define EHMAC_RUL_M1_NR_E 96
+
+#define SAM_BYTE4
+#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5
+#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0
+#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1
+#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M2 7
+#define EHMAC_RUL_M2_OFFSET 0x59008
+#define EHMAC_RUL_M2_E_LENGTH 4
+#define EHMAC_RUL_M2_E_OFFSET 0x20
+#define EHMAC_RUL_M2_NR_E 96
+
+#define CTAG_VIDLM
+#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24
+#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8
+#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW
+
+#define STAG_PRIM
+#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21
+#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3
+#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW
+
+#define STAG_DEIM
+#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20
+#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1
+#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW
+
+#define STAG_VIDM
+#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8
+#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12
+#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW
+
+#define SAM_BYTE3
+#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M3 8
+#define EHMAC_RUL_M3_OFFSET 0x5900c
+#define EHMAC_RUL_M3_E_LENGTH 4
+#define EHMAC_RUL_M3_E_OFFSET 0x20
+#define EHMAC_RUL_M3_NR_E 96
+
+#define ETHTYPM
+#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8
+#define EHMAC_RUL_M3_ETHTYPM_BLEN 16
+#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define CTAG_PRIM
+#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5
+#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3
+#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW
+
+#define CTAG_CFIM
+#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4
+#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1
+#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW
+
+#define CTAG_VIDHM
+#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0
+#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4
+#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M4 9
+#define EHMAC_RUL_M4_OFFSET 0x59010
+#define EHMAC_RUL_M4_E_LENGTH 4
+#define EHMAC_RUL_M4_E_OFFSET 0x20
+#define EHMAC_RUL_M4_NR_E 96
+
+#define CTAGGEDM
+#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5
+#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1
+#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW
+
+#define CTAGGEDV
+#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4
+#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1
+#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW
+
+#define CVIDMSK
+#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3
+#define EHMAC_RUL_M4_CVIDMSK_BLEN 1
+#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW
+
+
+
+
+ /* PPPoE Session Table Define */
+#define PPPOE_SESSION
+#define PPPOE_SESSION_OFFSET 0x5f000
+#define PPPOE_SESSION_E_LENGTH 4
+#define PPPOE_SESSION_E_OFFSET 0x4
+#define PPPOE_SESSION_NR_E 16
+
+#define ENTRY_VALID
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16
+#define PPPOE_SESSION_ENTRY_VALID_BLEN 2
+#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW
+
+#define SEESION_ID
+#define PPPOE_SESSION_SEESION_ID_BOFFSET 0
+#define PPPOE_SESSION_SEESION_ID_BLEN 16
+#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW
+
+
+#define PPPOE_EDIT
+#define PPPOE_EDIT_OFFSET 0x02200
+#define PPPOE_EDIT_E_LENGTH 4
+#define PPPOE_EDIT_E_OFFSET 0x10
+#define PPPOE_EDIT_NR_E 16
+
+#define EDIT_ID
+#define PPPOE_EDIT_EDIT_ID_BOFFSET 0
+#define PPPOE_EDIT_EDIT_ID_BLEN 16
+#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW
+
+
+
+
+ /* L3 Host Entry Defile */
+#define HOST_ENTRY0
+#define HOST_ENTRY0_OFFSET 0x0e48
+#define HOST_ENTRY0_E_LENGTH 4
+#define HOST_ENTRY0_E_OFFSET 0x0
+#define HOST_ENTRY0_NR_E 1
+
+#define IP_ADDR
+#define HOST_ENTRY0_IP_ADDR_BOFFSET 0
+#define HOST_ENTRY0_IP_ADDR_BLEN 32
+#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW
+
+#define HOST_ENTRY1
+#define HOST_ENTRY1_OFFSET 0x0e4c
+#define HOST_ENTRY1_E_LENGTH 4
+#define HOST_ENTRY1_E_OFFSET 0x0
+#define HOST_ENTRY1_NR_E 1
+
+#define MAC_ADDR2
+#define HOST_ENTRY1_MAC_ADDR2_BOFFSET 24
+#define HOST_ENTRY1_MAC_ADDR2_BLEN 8
+#define HOST_ENTRY1_MAC_ADDR2_FLAG HSL_RW
+
+#define MAC_ADDR3
+#define HOST_ENTRY1_MAC_ADDR3_BOFFSET 16
+#define HOST_ENTRY1_MAC_ADDR3_BLEN 8
+#define HOST_ENTRY1_MAC_ADDR3_FLAG HSL_RW
+
+#define MAC_ADDR4
+#define HOST_ENTRY1_MAC_ADDR4_BOFFSET 8
+#define HOST_ENTRY1_MAC_ADDR4_BLEN 8
+#define HOST_ENTRY1_MAC_ADDR4_FLAG HSL_RW
+
+#define MAC_ADDR5
+#define HOST_ENTRY1_MAC_ADDR5_BOFFSET 0
+#define HOST_ENTRY1_MAC_ADDR5_BLEN 8
+#define HOST_ENTRY1_MAC_ADDR5_FLAG HSL_RW
+
+#define HOST_ENTRY2
+#define HOST_ENTRY2_OFFSET 0x0e50
+#define HOST_ENTRY2_E_LENGTH 4
+#define HOST_ENTRY2_E_OFFSET 0x0
+#define HOST_ENTRY2_NR_E 1
+
+#define CPU_ADDR
+#define HOST_ENTRY2_CPU_ADDR_BOFFSET 31
+#define HOST_ENTRY2_CPU_ADDR_BLEN 1
+#define HOST_ENTRY2_CPU_ADDR_FLAG HSL_RW
+
+#define SRC_PORT
+#define HOST_ENTRY2_SRC_PORT_BOFFSET 28
+#define HOST_ENTRY2_SRC_PORT_BLEN 3
+#define HOST_ENTRY2_SRC_PORT_FLAG HSL_RW
+
+#define INTF_ID
+#define HOST_ENTRY2_INTF_ID_BOFFSET 16
+#define HOST_ENTRY2_INTF_ID_BLEN 12
+#define HOST_ENTRY2_INTF_ID_FLAG HSL_RW
+
+#define MAC_ADDR0
+#define HOST_ENTRY2_MAC_ADDR0_BOFFSET 8
+#define HOST_ENTRY2_MAC_ADDR0_BLEN 8
+#define HOST_ENTRY2_MAC_ADDR0_FLAG HSL_RW
+
+#define MAC_ADDR1
+#define HOST_ENTRY2_MAC_ADDR1_BOFFSET 0
+#define HOST_ENTRY2_MAC_ADDR1_BLEN 8
+#define HOST_ENTRY2_MAC_ADDR1_FLAG HSL_RW
+
+
+#define HOST_ENTRY3
+#define HOST_ENTRY3_OFFSET 0x0e54
+#define HOST_ENTRY3_E_LENGTH 4
+#define HOST_ENTRY3_E_OFFSET 0x0
+#define HOST_ENTRY3_NR_E 1
+
+#define IP_VER
+#define HOST_ENTRY3_IP_VER_BOFFSET 15
+#define HOST_ENTRY3_IP_VER_BLEN 1
+#define HOST_ENTRY3_IP_VER_FLAG HSL_RW
+
+#define AGE_FLAG
+#define HOST_ENTRY3_AGE_FLAG_BOFFSET 12
+#define HOST_ENTRY3_AGE_FLAG_BLEN 3
+#define HOST_ENTRY3_AGE_FLAG_FLAG HSL_RW
+
+#define PPPOE_EN
+#define HOST_ENTRY3_PPPOE_EN_BOFFSET 11
+#define HOST_ENTRY3_PPPOE_EN_BLEN 1
+#define HOST_ENTRY3_PPPOE_EN_FLAG HSL_RW
+
+#define PPPOE_IDX
+#define HOST_ENTRY3_PPPOE_IDX_BOFFSET 7
+#define HOST_ENTRY3_PPPOE_IDX_BLEN 4
+#define HOST_ENTRY3_PPPOE_IDX_FLAG HSL_RW
+
+#define CNT_EN
+#define HOST_ENTRY3_CNT_EN_BOFFSET 6
+#define HOST_ENTRY3_CNT_EN_BLEN 1
+#define HOST_ENTRY3_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define HOST_ENTRY3_CNT_IDX_BOFFSET 2
+#define HOST_ENTRY3_CNT_IDX_BLEN 4
+#define HOST_ENTRY3_CNT_IDX_FLAG HSL_RW
+
+#define ACTION
+#define HOST_ENTRY3_ACTION_BOFFSET 0
+#define HOST_ENTRY3_ACTION_BLEN 2
+#define HOST_ENTRY3_ACTION_FLAG HSL_RW
+
+
+#define HOST_ENTRY4
+#define HOST_ENTRY4_OFFSET 0x0e58
+#define HOST_ENTRY4_E_LENGTH 4
+#define HOST_ENTRY4_E_OFFSET 0x0
+#define HOST_ENTRY4_NR_E 1
+
+#define TBL_BUSY
+#define HOST_ENTRY4_TBL_BUSY_BOFFSET 31
+#define HOST_ENTRY4_TBL_BUSY_BLEN 1
+#define HOST_ENTRY4_TBL_BUSY_FLAG HSL_RW
+
+#define SPEC_SP
+#define HOST_ENTRY4_SPEC_SP_BOFFSET 22
+#define HOST_ENTRY4_SPEC_SP_BLEN 1
+#define HOST_ENTRY4_SPEC_SP_FLAG HSL_RW
+
+#define SPEC_VID
+#define HOST_ENTRY4_SPEC_VID_BOFFSET 21
+#define HOST_ENTRY4_SPEC_VID_BLEN 1
+#define HOST_ENTRY4_SPEC_VID_FLAG HSL_RW
+
+#define SPEC_PIP
+#define HOST_ENTRY4_SPEC_PIP_BOFFSET 20
+#define HOST_ENTRY4_SPEC_PIP_BLEN 1
+#define HOST_ENTRY4_SPEC_PIP_FLAG HSL_RW
+
+#define SPEC_SIP
+#define HOST_ENTRY4_SPEC_SIP_BOFFSET 19
+#define HOST_ENTRY4_SPEC_SIP_BLEN 1
+#define HOST_ENTRY4_SPEC_SIP_FLAG HSL_RW
+
+#define SPEC_STATUS
+#define HOST_ENTRY4_SPEC_STATUS_BOFFSET 18
+#define HOST_ENTRY4_SPEC_STATUS_BLEN 1
+#define HOST_ENTRY4_SPEC_STATUS_FLAG HSL_RW
+
+#define TBL_IDX
+#define HOST_ENTRY4_TBL_IDX_BOFFSET 8
+#define HOST_ENTRY4_TBL_IDX_BLEN 10
+#define HOST_ENTRY4_TBL_IDX_FLAG HSL_RW
+
+#define TBL_STAUS
+#define HOST_ENTRY4_TBL_STAUS_BOFFSET 7
+#define HOST_ENTRY4_TBL_STAUS_BLEN 1
+#define HOST_ENTRY4_TBL_STAUS_FLAG HSL_RW
+
+#define TBL_SEL
+#define HOST_ENTRY4_TBL_SEL_BOFFSET 4
+#define HOST_ENTRY4_TBL_SEL_BLEN 2
+#define HOST_ENTRY4_TBL_SEL_FLAG HSL_RW
+
+#define ENTRY_FUNC
+#define HOST_ENTRY4_ENTRY_FUNC_BOFFSET 0
+#define HOST_ENTRY4_ENTRY_FUNC_BLEN 3
+#define HOST_ENTRY4_ENTRY_FUNC_FLAG HSL_RW
+
+
+
+
+#define NAT_ENTRY0
+#define NAT_ENTRY0_OFFSET 0x0e48
+#define NAT_ENTRY0_E_LENGTH 4
+#define NAT_ENTRY0_E_OFFSET 0x0
+#define NAT_ENTRY0_NR_E 1
+
+#define IP_ADDR
+#define NAT_ENTRY0_IP_ADDR_BOFFSET 0
+#define NAT_ENTRY0_IP_ADDR_BLEN 32
+#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW
+
+
+#define NAT_ENTRY1
+#define NAT_ENTRY1_OFFSET 0x0e4c
+#define NAT_ENTRY1_E_LENGTH 4
+#define NAT_ENTRY1_E_OFFSET 0x0
+#define NAT_ENTRY1_NR_E 1
+
+#define PRV_IPADDR0
+#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24
+#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8
+#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW
+
+#define PORT_RANGE
+#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16
+#define NAT_ENTRY1_PORT_RANGE_BLEN 8
+#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW
+
+#define PORT_NUM
+#define NAT_ENTRY1_PORT_NUM_BOFFSET 0
+#define NAT_ENTRY1_PORT_NUM_BLEN 16
+#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW
+
+
+#define NAT_ENTRY2
+#define NAT_ENTRY2_OFFSET 0x0e50
+#define NAT_ENTRY2_E_LENGTH 4
+#define NAT_ENTRY2_E_OFFSET 0x0
+#define NAT_ENTRY2_NR_E 1
+
+#define ENTRY_VALID
+#define NAT_ENTRY2_ENTRY_VALID_BOFFSET 15
+#define NAT_ENTRY2_ENTRY_VALID_BLEN 1
+#define NAT_ENTRY2_ENTRY_VALID_FLAG HSL_RW
+
+#define PORT_EN
+#define NAT_ENTRY2_PORT_EN_BOFFSET 14
+#define NAT_ENTRY2_PORT_EN_BLEN 1
+#define NAT_ENTRY2_PORT_EN_FLAG HSL_RW
+
+#define PRO_TYP
+#define NAT_ENTRY2_PRO_TYP_BOFFSET 12
+#define NAT_ENTRY2_PRO_TYP_BLEN 2
+#define NAT_ENTRY2_PRO_TYP_FLAG HSL_RW
+
+#define HASH_KEY
+#define NAT_ENTRY2_HASH_KEY_BOFFSET 10
+#define NAT_ENTRY2_HASH_KEY_BLEN 2
+#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW
+
+#define ACTION
+#define NAT_ENTRY2_ACTION_BOFFSET 8
+#define NAT_ENTRY2_ACTION_BLEN 2
+#define NAT_ENTRY2_ACTION_FLAG HSL_RW
+
+#define CNT_EN
+#define NAT_ENTRY2_CNT_EN_BOFFSET 7
+#define NAT_ENTRY2_CNT_EN_BLEN 1
+#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define NAT_ENTRY2_CNT_IDX_BOFFSET 4
+#define NAT_ENTRY2_CNT_IDX_BLEN 3
+#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW
+
+#define PRV_IPADDR1
+#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0
+#define NAT_ENTRY2_PRV_IPADDR1_BLEN 4
+#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW
+
+
+
+
+#define NAPT_ENTRY0
+#define NAPT_ENTRY0_OFFSET 0x0e48
+#define NAPT_ENTRY0_E_LENGTH 4
+#define NAPT_ENTRY0_E_OFFSET 0x0
+#define NAPT_ENTRY0_NR_E 1
+
+#define DST_IPADDR
+#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0
+#define NAPT_ENTRY0_DST_IPADDR_BLEN 32
+#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW
+
+
+#define NAPT_ENTRY1
+#define NAPT_ENTRY1_OFFSET 0x0e4c
+#define NAPT_ENTRY1_E_LENGTH 4
+#define NAPT_ENTRY1_E_OFFSET 0x0
+#define NAPT_ENTRY1_NR_E 1
+
+#define SRC_PORT
+#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16
+#define NAPT_ENTRY1_SRC_PORT_BLEN 16
+#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW
+
+#define DST_PORT
+#define NAPT_ENTRY1_DST_PORT_BOFFSET 0
+#define NAPT_ENTRY1_DST_PORT_BLEN 16
+#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW
+
+
+#define NAPT_ENTRY2
+#define NAPT_ENTRY2_OFFSET 0x0e50
+#define NAPT_ENTRY2_E_LENGTH 4
+#define NAPT_ENTRY2_E_OFFSET 0x0
+#define NAPT_ENTRY2_NR_E 1
+
+#define SRC_IPADDR
+#define NAPT_ENTRY2_SRC_IPADDR_BOFFSET 20
+#define NAPT_ENTRY2_SRC_IPADDR_BLEN 12
+#define NAPT_ENTRY2_SRC_IPADDR_FLAG HSL_RW
+
+#define TRANS_IPADDR
+#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16
+#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4
+#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW
+
+#define TRANS_PORT
+#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0
+#define NAPT_ENTRY2_TRANS_PORT_BLEN 16
+#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW
+
+
+#define NAPT_ENTRY3
+#define NAPT_ENTRY3_OFFSET 0x0e54
+#define NAPT_ENTRY3_E_LENGTH 4
+#define NAPT_ENTRY3_E_OFFSET 0x0
+#define NAPT_ENTRY3_NR_E 1
+
+#define AGE_FLAG
+#define NAPT_ENTRY3_AGE_FLAG_BOFFSET 12
+#define NAPT_ENTRY3_AGE_FLAG_BLEN 4
+#define NAPT_ENTRY3_AGE_FLAG_FLAG HSL_RW
+
+#define CNT_EN
+#define NAPT_ENTRY3_CNT_EN_BOFFSET 7
+#define NAPT_ENTRY3_CNT_EN_BLEN 1
+#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define NAPT_ENTRY3_CNT_IDX_BOFFSET 4
+#define NAPT_ENTRY3_CNT_IDX_BLEN 3
+#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW
+
+#define PROT_TYP
+#define NAPT_ENTRY3_PROT_TYP_BOFFSET 2
+#define NAPT_ENTRY3_PROT_TYP_BLEN 2
+#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW
+
+#define ACTION
+#define NAPT_ENTRY3_ACTION_BOFFSET 0
+#define NAPT_ENTRY3_ACTION_BLEN 2
+#define NAPT_ENTRY3_ACTION_FLAG HSL_RW
+
+
+
+
+#define ROUTER_CTRL
+#define ROUTER_CTRL_OFFSET 0x0e00
+#define ROUTER_CTRL_E_LENGTH 4
+#define ROUTER_CTRL_E_OFFSET 0x0
+#define ROUTER_CTRL_NR_E 1
+
+#define ARP_LEARN_MODE
+#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19
+#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1
+#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW
+
+#define GLB_LOCKTIME
+#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16
+#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2
+#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW
+
+#define ARP_AGE_TIME
+#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8
+#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8
+#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW
+
+#define WCMP_HAHS_DP
+#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7
+#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW
+
+#define WCMP_HAHS_DIP
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW
+
+#define WCMP_HAHS_SP
+#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5
+#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW
+
+#define WCMP_HAHS_SIP
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW
+
+#define ARP_AGE_MODE
+#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1
+#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1
+#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW
+
+#define ROUTER_EN
+#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0
+#define ROUTER_CTRL_ROUTER_EN_BLEN 1
+#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW
+
+
+
+
+#define ROUTER_PTCTRL0
+#define ROUTER_PTCTRL0_OFFSET 0x0e04
+#define ROUTER_PTCTRL0_E_LENGTH 4
+#define ROUTER_PTCTRL0_E_OFFSET 0x0
+#define ROUTER_PTCTRL0_NR_E 1
+
+
+
+
+#define ROUTER_PTCTRL1
+#define ROUTER_PTCTRL1_OFFSET 0x0e08
+#define ROUTER_PTCTRL1_E_LENGTH 4
+#define ROUTER_PTCTRL1_E_OFFSET 0x0
+#define ROUTER_PTCTRL1_NR_E 1
+
+
+
+#define ROUTER_PTCTRL2
+#define ROUTER_PTCTRL2_OFFSET 0x0e0c
+#define ROUTER_PTCTRL2_E_LENGTH 4
+#define ROUTER_PTCTRL2_E_OFFSET 0x0
+#define ROUTER_PTCTRL2_NR_E 1
+
+#define ARP_PT_UP
+#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16
+#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7
+#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW
+
+#define ARP_LEARN_ACK
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW
+
+#define ARP_LEARN_REQ
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW
+
+
+
+
+#define NAT_CTRL
+#define NAT_CTRL_OFFSET 0x0e38
+#define NAT_CTRL_E_LENGTH 4
+#define NAT_CTRL_E_OFFSET 0x0
+#define NAT_CTRL_NR_E 1
+
+#define NAT_HASH_MODE
+#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5
+#define NAT_CTRL_NAT_HASH_MODE_BLEN 2
+#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW
+
+#define NAPT_OVERRIDE
+#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4
+#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1
+#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW
+
+#define NAPT_MODE
+#define NAT_CTRL_NAPT_MODE_BOFFSET 2
+#define NAT_CTRL_NAPT_MODE_BLEN 2
+#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW
+
+#define NAT_EN
+#define NAT_CTRL_NAT_EN_BOFFSET 1
+#define NAT_CTRL_NAT_EN_BLEN 1
+#define NAT_CTRL_NAT_EN_FLAG HSL_RW
+
+#define NAPT_EN
+#define NAT_CTRL_NAPT_EN_BOFFSET 0
+#define NAT_CTRL_NAPT_EN_BLEN 1
+#define NAT_CTRL_NAPT_EN_FLAG HSL_RW
+
+
+
+
+#define PRV_BASEADDR
+#define PRV_BASEADDR_OFFSET 0x0e5c
+#define PRV_BASEADDR_E_LENGTH 4
+#define PRV_BASEADDR_E_OFFSET 0x0
+#define PRV_BASEADDR_NR_E 1
+
+#define IP4_ADDR
+#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0
+#define PRV_BASEADDR_IP4_ADDR_BLEN 20
+#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW
+
+
+
+
+#define PRVIP_CTL
+#define PRVIP_CTL_OFFSET 0x0418
+#define PRVIP_CTL_E_LENGTH 4
+#define PRVIP_CTL_E_OFFSET 0x0
+#define PRVIP_CTL_NR_E 1
+
+#define BASEADDR_SEL
+#define PRVIP_CTL_BASEADDR_SEL_BOFFSET 28
+#define PRVIP_CTL_BASEADDR_SEL_BLEN 1
+#define PRVIP_CTL_BASEADDR_SEL_FLAG HSL_RW
+
+#define IP4_BASEADDR
+#define PRVIP_CTL_IP4_BASEADDR_BOFFSET 0
+#define PRVIP_CTL_IP4_BASEADDR_BLEN 20
+#define PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW
+
+
+#define OFFLOAD_PRVIP_CTL
+#define OFFLOAD_PRVIP_CTL_OFFSET 0x0e5c
+#define OFFLOAD_PRVIP_CTL_E_LENGTH 4
+#define OFFLOAD_PRVIP_CTL_E_OFFSET 0x0
+#define OFFLOAD_PRVIP_CTL_NR_E 1
+
+#define IP4_BASEADDR
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BOFFSET 0
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_BLEN 20
+#define OFFLOAD_PRVIP_CTL_IP4_BASEADDR_FLAG HSL_RW
+
+
+
+
+#define PUB_ADDR0
+#define PUB_ADDR0_OFFSET 0x5aa00
+#define PUB_ADDR0_E_LENGTH 4
+#define PUB_ADDR0_E_OFFSET 0x0
+#define PUB_ADDR0_NR_E 1
+
+#define IP4_ADDR
+#define PUB_ADDR0_IP4_ADDR_BOFFSET 0
+#define PUB_ADDR0_IP4_ADDR_BLEN 32
+#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW
+
+
+#define PUB_ADDR1
+#define PUB_ADDR1_OFFSET 0x5aa04
+#define PUB_ADDR1_E_LENGTH 4
+#define PUB_ADDR1_E_OFFSET 0x0
+#define PUB_ADDR1_NR_E 1
+
+#define ADDR_VALID
+#define PUB_ADDR1_ADDR_VALID_BOFFSET 0
+#define PUB_ADDR1_ADDR_VALID_BLEN 1
+#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW
+
+
+
+
+#define INTF_ADDR_ENTRY0
+#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00
+#define INTF_ADDR_ENTRY0_E_LENGTH 4
+#define INTF_ADDR_ENTRY0_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY0_NR_E 8
+
+#define MAC_ADDR2
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW
+
+#define MAC_ADDR3
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW
+
+#define MAC_ADDR4
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW
+
+#define MAC_ADDR5
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW
+
+
+#define INTF_ADDR_ENTRY1
+#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04
+#define INTF_ADDR_ENTRY1_E_LENGTH 4
+#define INTF_ADDR_ENTRY1_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY1_NR_E 8
+
+#define VID_HIGH0
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4
+#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW
+
+#define VID_LOW
+#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16
+#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12
+#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW
+
+#define MAC_ADDR0
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW
+
+#define MAC_ADDR1
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW
+
+
+#define INTF_ADDR_ENTRY2
+#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08
+#define INTF_ADDR_ENTRY2_E_LENGTH 4
+#define INTF_ADDR_ENTRY2_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY2_NR_E 8
+
+#define IP6_ROUTE
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW
+
+#define IP4_ROUTE
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW
+
+#define VID_HIGH1
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8
+#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW
+
+
+
+
+ /* Port Shaper Register0 */
+#define EG_SHAPER0
+#define EG_SHAPER0_OFFSET 0x0890
+#define EG_SHAPER0_E_LENGTH 4
+#define EG_SHAPER0_E_OFFSET 0x0020
+#define EG_SHAPER0_NR_E 7
+
+#define EG_Q1_CIR
+#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16
+#define EG_SHAPER0_EG_Q1_CIR_BLEN 15
+#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW
+
+#define EG_Q0_CIR
+#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0
+#define EG_SHAPER0_EG_Q0_CIR_BLEN 15
+#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register1 */
+#define EG_SHAPER1
+#define EG_SHAPER1_OFFSET 0x0894
+#define EG_SHAPER1_E_LENGTH 4
+#define EG_SHAPER1_E_OFFSET 0x0020
+#define EG_SHAPER1_NR_E 7
+
+#define EG_Q3_CIR
+#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16
+#define EG_SHAPER1_EG_Q3_CIR_BLEN 15
+#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW
+
+#define EG_Q2_CIR
+#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0
+#define EG_SHAPER1_EG_Q2_CIR_BLEN 15
+#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register2 */
+#define EG_SHAPER2
+#define EG_SHAPER2_OFFSET 0x0898
+#define EG_SHAPER2_E_LENGTH 4
+#define EG_SHAPER2_E_OFFSET 0x0020
+#define EG_SHAPER2_NR_E 7
+
+#define EG_Q5_CIR
+#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16
+#define EG_SHAPER2_EG_Q5_CIR_BLEN 15
+#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW
+
+#define EG_Q4_CIR
+#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0
+#define EG_SHAPER2_EG_Q4_CIR_BLEN 15
+#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register3 */
+#define EG_SHAPER3
+#define EG_SHAPER3_OFFSET 0x089c
+#define EG_SHAPER3_E_LENGTH 4
+#define EG_SHAPER3_E_OFFSET 0x0020
+#define EG_SHAPER3_NR_E 7
+
+#define EG_Q1_EIR
+#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16
+#define EG_SHAPER3_EG_Q1_EIR_BLEN 15
+#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW
+
+#define EG_Q0_EIR
+#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0
+#define EG_SHAPER3_EG_Q0_EIR_BLEN 15
+#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register4 */
+#define EG_SHAPER4
+#define EG_SHAPER4_OFFSET 0x08a0
+#define EG_SHAPER4_E_LENGTH 4
+#define EG_SHAPER4_E_OFFSET 0x0020
+#define EG_SHAPER4_NR_E 7
+
+#define EG_Q3_EIR
+#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16
+#define EG_SHAPER4_EG_Q3_EIR_BLEN 15
+#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW
+
+#define EG_Q2_EIR
+#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0
+#define EG_SHAPER4_EG_Q2_EIR_BLEN 15
+#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register5 */
+#define EG_SHAPER5
+#define EG_SHAPER5_OFFSET 0x08a4
+#define EG_SHAPER5_E_LENGTH 4
+#define EG_SHAPER5_E_OFFSET 0x0020
+#define EG_SHAPER5_NR_E 7
+
+#define EG_Q5_EIR
+#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16
+#define EG_SHAPER5_EG_Q5_EIR_BLEN 15
+#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW
+
+#define EG_Q4_EIR
+#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0
+#define EG_SHAPER5_EG_Q4_EIR_BLEN 15
+#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register6 */
+#define EG_SHAPER6
+#define EG_SHAPER6_OFFSET 0x08a8
+#define EG_SHAPER6_E_LENGTH 4
+#define EG_SHAPER6_E_OFFSET 0x0020
+#define EG_SHAPER6_NR_E 7
+
+#define EG_Q3_CBS
+#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28
+#define EG_SHAPER6_EG_Q3_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW
+
+#define EG_Q3_EBS
+#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24
+#define EG_SHAPER6_EG_Q3_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW
+
+#define EG_Q2_CBS
+#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20
+#define EG_SHAPER6_EG_Q2_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW
+
+#define EG_Q2_EBS
+#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16
+#define EG_SHAPER6_EG_Q2_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW
+
+#define EG_Q1_CBS
+#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12
+#define EG_SHAPER6_EG_Q1_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW
+
+#define EG_Q1_EBS
+#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8
+#define EG_SHAPER6_EG_Q1_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW
+
+#define EG_Q0_CBS
+#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4
+#define EG_SHAPER6_EG_Q0_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW
+
+#define EG_Q0_EBS
+#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0
+#define EG_SHAPER6_EG_Q0_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW
+
+
+ /* Port Shaper Register7 */
+#define EG_SHAPER7
+#define EG_SHAPER7_OFFSET 0x08ac
+#define EG_SHAPER7_E_LENGTH 4
+#define EG_SHAPER7_E_OFFSET 0x0020
+#define EG_SHAPER7_NR_E 7
+
+#define EG_Q5_CBS
+#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28
+#define EG_SHAPER7_EG_Q5_CBS_BLEN 3
+#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW
+
+#define EG_Q5_EBS
+#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24
+#define EG_SHAPER7_EG_Q5_EBS_BLEN 3
+#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW
+
+#define EG_Q4_CBS
+#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20
+#define EG_SHAPER7_EG_Q4_CBS_BLEN 3
+#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW
+
+#define EG_Q4_EBS
+#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16
+#define EG_SHAPER7_EG_Q4_EBS_BLEN 3
+#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW
+
+#define EG_Q5_UNIT
+#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13
+#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW
+
+#define EG_Q4_UNIT
+#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12
+#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW
+
+#define EG_Q3_UNIT
+#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11
+#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW
+
+#define EG_Q2_UNIT
+#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10
+#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW
+
+#define EG_Q1_UNIT
+#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9
+#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW
+
+#define EG_Q0_UNIT
+#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8
+#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW
+
+#define EG_PT
+#define EG_SHAPER7_EG_PT_BOFFSET 3
+#define EG_SHAPER7_EG_PT_BLEN 1
+#define EG_SHAPER7_EG_PT_FLAG HSL_RW
+
+#define EG_TS
+#define EG_SHAPER7_EG_TS_BOFFSET 0
+#define EG_SHAPER7_EG_TS_BLEN 3
+#define EG_SHAPER7_EG_TS_FLAG HSL_RW
+
+
+
+ /* ACL Policer Register0 */
+#define ACL_POLICER0
+#define ACL_POLICER0_OFFSET 0x0a00
+#define ACL_POLICER0_E_LENGTH 4
+#define ACL_POLICER0_E_OFFSET 0x0008
+#define ACL_POLICER0_NR_E 32
+
+#define ACL_CBS
+#define ACL_POLICER0_ACL_CBS_BOFFSET 15
+#define ACL_POLICER0_ACL_CBS_BLEN 3
+#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW
+
+#define ACL_CIR
+#define ACL_POLICER0_ACL_CIR_BOFFSET 0
+#define ACL_POLICER0_ACL_CIR_BLEN 15
+#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW
+
+
+ /* ACL Policer Register1 */
+#define ACL_POLICER1
+#define ACL_POLICER1_OFFSET 0x0a04
+#define ACL_POLICER1_E_LENGTH 4
+#define ACL_POLICER1_E_OFFSET 0x0008
+#define ACL_POLICER1_NR_E 32
+
+#define ACL_BORROW
+#define ACL_POLICER1_ACL_BORROW_BOFFSET 23
+#define ACL_POLICER1_ACL_BORROW_BLEN 1
+#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW
+
+#define ACL_UNIT
+#define ACL_POLICER1_ACL_UNIT_BOFFSET 22
+#define ACL_POLICER1_ACL_UNIT_BLEN 1
+#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW
+
+#define ACL_CF
+#define ACL_POLICER1_ACL_CF_BOFFSET 21
+#define ACL_POLICER1_ACL_CF_BLEN 1
+#define ACL_POLICER1_ACL_CF_FLAG HSL_RW
+
+#define ACL_CM
+#define ACL_POLICER1_ACL_CM_BOFFSET 20
+#define ACL_POLICER1_ACL_CM_BLEN 1
+#define ACL_POLICER1_ACL_CM_FLAG HSL_RW
+
+#define ACL_TS
+#define ACL_POLICER1_ACL_TS_BOFFSET 18
+#define ACL_POLICER1_ACL_TS_BLEN 2
+#define ACL_POLICER1_ACL_TS_FLAG HSL_RW
+
+#define ACL_EBS
+#define ACL_POLICER1_ACL_EBS_BOFFSET 15
+#define ACL_POLICER1_ACL_EBS_BLEN 3
+#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW
+
+#define ACL_EIR
+#define ACL_POLICER1_ACL_EIR_BOFFSET 0
+#define ACL_POLICER1_ACL_EIR_BLEN 15
+#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW
+
+
+ /* ACL Counter Register0 */
+#define ACL_COUNTER0
+#define ACL_COUNTER0_OFFSET 0x1c000
+#define ACL_COUNTER0_E_LENGTH 4
+#define ACL_COUNTER0_E_OFFSET 0x0008
+#define ACL_COUNTER0_NR_E 32
+
+ /* ACL Counter Register1 */
+#define ACL_COUNTER1
+#define ACL_COUNTER1_OFFSET 0x1c004
+#define ACL_COUNTER1_E_LENGTH 4
+#define ACL_COUNTER1_E_OFFSET 0x0008
+#define ACL_COUNTER1_NR_E 32
+
+
+
+
+ /* INGRESS Policer Register0 */
+#define INGRESS_POLICER0
+#define INGRESS_POLICER0_OFFSET 0x0b00
+#define INGRESS_POLICER0_E_LENGTH 4
+#define INGRESS_POLICER0_E_OFFSET 0x0010
+#define INGRESS_POLICER0_NR_E 7
+
+#define ADD_RATE_BYTE
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8
+#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define C_ING_TS
+#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22
+#define INGRESS_POLICER0_C_ING_TS_BLEN 2
+#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW
+
+#define RATE_MODE
+#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20
+#define INGRESS_POLICER0_RATE_MODE_BLEN 1
+#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW
+
+#define INGRESS_CBS
+#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15
+#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3
+#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW
+
+#define INGRESS_CIR
+#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0
+#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15
+#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW
+
+
+ /* INGRESS Policer Register1 */
+#define INGRESS_POLICER1
+#define INGRESS_POLICER1_OFFSET 0x0b04
+#define INGRESS_POLICER1_E_LENGTH 4
+#define INGRESS_POLICER1_E_OFFSET 0x0010
+#define INGRESS_POLICER1_NR_E 7
+
+#define INGRESS_BORROW
+#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23
+#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1
+#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW
+
+#define INGRESS_UNIT
+#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22
+#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1
+#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW
+
+#define INGRESS_CF
+#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21
+#define INGRESS_POLICER1_INGRESS_CF_BLEN 1
+#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW
+
+#define INGRESS_CM
+#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20
+#define INGRESS_POLICER1_INGRESS_CM_BLEN 1
+#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW
+
+#define E_ING_TS
+#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18
+#define INGRESS_POLICER1_E_ING_TS_BLEN 2
+#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW
+
+#define INGRESS_EBS
+#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15
+#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3
+#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW
+
+#define INGRESS_EIR
+#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0
+#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15
+#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW
+
+
+ /* INGRESS Policer Register2 */
+#define INGRESS_POLICER2
+#define INGRESS_POLICER2_OFFSET 0x0b08
+#define INGRESS_POLICER2_E_LENGTH 4
+#define INGRESS_POLICER2_E_OFFSET 0x0010
+#define INGRESS_POLICER2_NR_E 7
+
+#define C_MUL
+#define INGRESS_POLICER2_C_MUL_BOFFSET 15
+#define INGRESS_POLICER2_C_MUL_BLEN 1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW
+
+#define C_UNI
+#define INGRESS_POLICER2_C_UNI_BOFFSET 14
+#define INGRESS_POLICER2_C_UNI_BLEN 1
+#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW
+
+#define C_UNK_MUL
+#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13
+#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW
+
+#define C_UNK_UNI
+#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12
+#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1
+#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW
+
+#define C_BROAD
+#define INGRESS_POLICER2_C_BROAD_BOFFSET 11
+#define INGRESS_POLICER2_C_BROAD_BLEN 1
+#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW
+
+#define C_MANAGE
+#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10
+#define INGRESS_POLICER2_C_MANAGC_BLEN 1
+#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW
+
+#define C_TCP
+#define INGRESS_POLICER2_C_TCP_BOFFSET 9
+#define INGRESS_POLICER2_C_TCP_BLEN 1
+#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW
+
+#define C_MIRR
+#define INGRESS_POLICER2_C_MIRR_BOFFSET 8
+#define INGRESS_POLICER2_C_MIRR_BLEN 1
+#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW
+
+#define E_MUL
+#define INGRESS_POLICER2_E_MUL_BOFFSET 7
+#define INGRESS_POLICER2_E_MUL_BLEN 1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW
+
+#define E_UNI
+#define INGRESS_POLICER2_E_UNI_BOFFSET 6
+#define INGRESS_POLICER2_E_UNI_BLEN 1
+#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW
+
+#define E_UNK_MUL
+#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5
+#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW
+
+#define E_UNK_UNI
+#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4
+#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1
+#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW
+
+#define E_BROAD
+#define INGRESS_POLICER2_E_BROAD_BOFFSET 3
+#define INGRESS_POLICER2_E_BROAD_BLEN 1
+#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW
+
+#define E_MANAGE
+#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2
+#define INGRESS_POLICER2_E_MANAGE_BLEN 1
+#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW
+
+#define E_TCP
+#define INGRESS_POLICER2_E_TCP_BOFFSET 1
+#define INGRESS_POLICER2_E_TCP_BLEN 1
+#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW
+
+#define E_MIRR
+#define INGRESS_POLICER2_E_MIRR_BOFFSET 0
+#define INGRESS_POLICER2_E_MIRR_BLEN 1
+#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW
+
+
+
+
+ /* Port Rate Limit2 Register */
+#define WRR_CTRL
+#define WRR_CTRL_OFFSET 0x0830
+#define WRR_CTRL_E_LENGTH 4
+#define WRR_CTRL_E_OFFSET 0x0004
+#define WRR_CTRL_NR_E 7
+
+#define SCH_MODE
+#define WRR_CTRL_SCH_MODE_BOFFSET 30
+#define WRR_CTRL_SCH_MODE_BLEN 2
+#define WRR_CTRL_SCH_MODE_FLAG HSL_RW
+
+#define Q5_W
+#define WRR_CTRL_Q5_W_BOFFSET 25
+#define WRR_CTRL_Q5_W_BLEN 5
+#define WRR_CTRL_Q5_W_FLAG HSL_RW
+
+#define Q4_W
+#define WRR_CTRL_Q4_W_BOFFSET 20
+#define WRR_CTRL_Q4_W_BLEN 5
+#define WRR_CTRL_Q4_W_FLAG HSL_RW
+
+#define Q3_W
+#define WRR_CTRL_Q3_W_BOFFSET 15
+#define WRR_CTRL_Q3_W_BLEN 5
+#define WRR_CTRL_Q3_W_FLAG HSL_RW
+
+#define Q2_W
+#define WRR_CTRL_Q2_W_BOFFSET 10
+#define WRR_CTRL_Q2_W_BLEN 5
+#define WRR_CTRL_Q2_W_FLAG HSL_RW
+
+#define Q1_W
+#define WRR_CTRL_Q1_W_BOFFSET 5
+#define WRR_CTRL_Q1_W_BLEN 5
+#define WRR_CTRL_Q1_W_FLAG HSL_RW
+
+#define Q0_W
+#define WRR_CTRL_Q0_W_BOFFSET 0
+#define WRR_CTRL_Q0_W_BLEN 5
+#define WRR_CTRL_Q0_W_FLAG HSL_RW
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_REG_H_ */
+
diff --git a/include/hsl/isis/isis_reg_access.h b/include/hsl/isis/isis_reg_access.h
new file mode 100644
index 0000000..459e3a1
--- /dev/null
+++ b/include/hsl/isis/isis_reg_access.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISIS_REG_ACCESS_H_
+#define _ISIS_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+#define ISIS_HEADER_CMD_LEN 8
+#define ISIS_HEADER_DATA_LEN 4
+#define ISIS_HEADER_LEN 4
+#define ISIS_HEADER_MAX_DATA_LEN 16
+#define VID_LEN 2
+#define ATHRS_HEADER_4BYTE_VAL 0xaaaa
+
+ typedef enum {
+ NORMAL_PACKET,
+ RESERVED0,
+ MIB_1ST,
+ RESERVED1,
+ RESERVED2,
+ READ_WRITE_REG,
+ READ_WRITE_REG_ACK,
+ RESERVED3
+ }
+ ATHRS_HEADER_TYPE;
+
+ typedef struct
+ {
+ a_uint8_t version;
+ a_uint8_t priority;
+ a_uint8_t type ;
+ a_uint8_t broadcast;
+ a_uint8_t from_cpu;
+ a_uint8_t port_num;
+ } athrs_header_t;
+
+ typedef struct
+ {
+ a_uint32_t reg_addr;
+ a_uint8_t cmd_len;
+ a_uint8_t cmd;
+ a_uint16_t check_code;
+ a_uint32_t seq_num;
+ } athrs_header_regcmd_t;
+
+ typedef struct
+ {
+ a_uint8_t data[ISIS_HEADER_MAX_DATA_LEN];
+ a_uint8_t len;
+ a_uint16_t athrs_4byte_value;
+ volatile a_uint32_t seq;
+ } athrs_cmd_resp_t;
+
+ sw_error_t
+ isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+ int
+ isis_reg_config_header (a_uint8_t *header, a_uint8_t wr_flag,
+ a_uint32_t reg_addr, a_uint8_t cmd_len,
+ a_uint8_t *val, a_uint32_t seq_num);
+
+ sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_REG_ACCESS_H_ */
+
diff --git a/include/hsl/isis/isis_sec.h b/include/hsl/isis/isis_sec.h
new file mode 100644
index 0000000..b959ea6
--- /dev/null
+++ b/include/hsl/isis/isis_sec.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_SEC_H_
+#define _ISIS_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_sec.h"
+
+ sw_error_t isis_sec_init(a_uint32_t dev_id);
+
+#ifdef IN_SEC
+#define ISIS_SEC_INIT(rv, dev_id) \
+ { \
+ rv = isis_sec_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_SEC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item,
+ void *value);
+
+ HSL_LOCAL sw_error_t
+ isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item,
+ void *value);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_SEC_H_ */
+
diff --git a/include/hsl/isis/isis_stp.h b/include/hsl/isis/isis_stp.h
new file mode 100644
index 0000000..cb6f347
--- /dev/null
+++ b/include/hsl/isis/isis_stp.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_STP_H_
+#define _ISIS_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+ sw_error_t isis_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define ISIS_STP_INIT(rv, dev_id) \
+ { \
+ rv = isis_stp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+ HSL_LOCAL sw_error_t
+ isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_STP_H_ */
+
diff --git a/include/hsl/isis/isis_trunk.h b/include/hsl/isis/isis_trunk.h
new file mode 100644
index 0000000..b76ee29
--- /dev/null
+++ b/include/hsl/isis/isis_trunk.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_TRUNK_H_
+#define _ISIS_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_trunk.h"
+
+ sw_error_t isis_trunk_init(a_uint32_t dev_id);
+
+#ifdef IN_TRUNK
+#define ISIS_TRUNK_INIT(rv, dev_id) \
+ { \
+ rv = isis_trunk_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_TRUNK_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISIS_TRUNK_H_ */
+
diff --git a/include/hsl/isis/isis_vlan.h b/include/hsl/isis/isis_vlan.h
new file mode 100644
index 0000000..87b830e
--- /dev/null
+++ b/include/hsl/isis/isis_vlan.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISIS_VLAN_H_
+#define _ISIS_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ isis_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ISIS_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = isis_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISIS_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_flush(a_uint32_t dev_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISIS_VLAN_H_ */
+
diff --git a/include/hsl/isisc/isisc_acl.h b/include/hsl/isisc/isisc_acl.h
new file mode 100644
index 0000000..7e0ded3
--- /dev/null
+++ b/include/hsl/isisc/isisc_acl.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_acl ISISC_ACL
+ * @{
+ */
+#ifndef _ISISC_ACL_H_
+#define _ISISC_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+ sw_error_t isisc_acl_init(a_uint32_t dev_id);
+
+ sw_error_t isisc_acl_reset(a_uint32_t dev_id);
+
+
+
+#ifdef IN_ACL
+#define ISISC_ACL_INIT(rv, dev_id) \
+ { \
+ rv = isisc_acl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISISC_ACL_RESET(rv, dev_id) \
+ { \
+ rv = isisc_acl_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_ACL_INIT(rv, dev_id)
+#define ISISC_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+ HSL_LOCAL a_uint32_t
+ isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_list_dump(a_uint32_t dev_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_dump(a_uint32_t dev_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t offset, a_uint32_t length);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type,
+ a_uint32_t * offset, a_uint32_t * length);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isisc/isisc_api.h b/include/hsl/isisc/isisc_api.h
new file mode 100644
index 0000000..f8923d3
--- /dev/null
+++ b/include/hsl/isisc/isisc_api.h
@@ -0,0 +1,1044 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISISC_API_H_
+#define _ISISC_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, isisc_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, isisc_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, isisc_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, isisc_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, isisc_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, isisc_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, isisc_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, isisc_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, isisc_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, isisc_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, isisc_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, isisc_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, isisc_port_flowctrl_forcemode_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, isisc_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, isisc_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, isisc_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, isisc_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, isisc_port_cdt), \
+ SW_API_DEF(SW_API_PT_TXHDR_SET, isisc_port_txhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_TXHDR_GET, isisc_port_txhdr_mode_get), \
+ SW_API_DEF(SW_API_PT_RXHDR_SET, isisc_port_rxhdr_mode_set), \
+ SW_API_DEF(SW_API_PT_RXHDR_GET, isisc_port_rxhdr_mode_get), \
+ SW_API_DEF(SW_API_HEADER_TYPE_SET, isisc_header_type_set), \
+ SW_API_DEF(SW_API_HEADER_TYPE_GET, isisc_header_type_get), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_SET, isisc_port_txmac_status_set), \
+ SW_API_DEF(SW_API_TXMAC_STATUS_GET, isisc_port_txmac_status_get), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_SET, isisc_port_rxmac_status_set), \
+ SW_API_DEF(SW_API_RXMAC_STATUS_GET, isisc_port_rxmac_status_get), \
+ SW_API_DEF(SW_API_TXFC_STATUS_SET, isisc_port_txfc_status_set), \
+ SW_API_DEF(SW_API_TXFC_STATUS_GET, isisc_port_txfc_status_get), \
+ SW_API_DEF(SW_API_RXFC_STATUS_SET, isisc_port_rxfc_status_set), \
+ SW_API_DEF(SW_API_RXFC_STATUS_GET, isisc_port_rxfc_status_get), \
+ SW_API_DEF(SW_API_BP_STATUS_SET, isisc_port_bp_status_set), \
+ SW_API_DEF(SW_API_BP_STATUS_GET, isisc_port_bp_status_get), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_SET, isisc_port_link_forcemode_set), \
+ SW_API_DEF(SW_API_PT_LINK_MODE_GET, isisc_port_link_forcemode_get), \
+ SW_API_DEF(SW_API_PT_LINK_STATUS_GET, isisc_port_link_status_get), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_SET, isisc_port_mac_loopback_set), \
+ SW_API_DEF(SW_API_PT_MAC_LOOPBACK_GET, isisc_port_mac_loopback_get),
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT) \
+ SW_API_DESC(SW_API_PT_TXHDR_SET) \
+ SW_API_DESC(SW_API_PT_TXHDR_GET) \
+ SW_API_DESC(SW_API_PT_RXHDR_SET) \
+ SW_API_DESC(SW_API_PT_RXHDR_GET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_SET) \
+ SW_API_DESC(SW_API_HEADER_TYPE_GET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXMAC_STATUS_GET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_TXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_SET) \
+ SW_API_DESC(SW_API_RXFC_STATUS_GET) \
+ SW_API_DESC(SW_API_BP_STATUS_SET) \
+ SW_API_DESC(SW_API_BP_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_SET) \
+ SW_API_DESC(SW_API_PT_LINK_MODE_GET) \
+ SW_API_DESC(SW_API_PT_LINK_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_SET) \
+ SW_API_DESC(SW_API_PT_MAC_LOOPBACK_GET)
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, isisc_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, isisc_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_FIND, isisc_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, isisc_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, isisc_vlan_entry_append), \
+ SW_API_DEF(SW_API_VLAN_FLUSH, isisc_vlan_flush), \
+ SW_API_DEF(SW_API_VLAN_FID_SET, isisc_vlan_fid_set), \
+ SW_API_DEF(SW_API_VLAN_FID_GET, isisc_vlan_fid_get), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_ADD, isisc_vlan_member_add), \
+ SW_API_DEF(SW_API_VLAN_MEMBER_DEL, isisc_vlan_member_del), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_SET, isisc_vlan_learning_state_set), \
+ SW_API_DEF(SW_API_VLAN_LEARN_STATE_GET, isisc_vlan_learning_state_get),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND) \
+ SW_API_DESC(SW_API_VLAN_FLUSH) \
+ SW_API_DESC(SW_API_VLAN_FID_SET) \
+ SW_API_DESC(SW_API_VLAN_FID_GET) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_ADD) \
+ SW_API_DESC(SW_API_VLAN_MEMBER_DEL) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_SET) \
+ SW_API_DESC(SW_API_VLAN_LEARN_STATE_GET)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, isisc_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, isisc_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, isisc_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, isisc_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, isisc_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, isisc_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, isisc_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, isisc_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, isisc_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, isisc_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, isisc_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, isisc_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, isisc_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, isisc_nestvlan_tpid_get), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, isisc_port_invlan_mode_set), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, isisc_port_invlan_mode_get), \
+ SW_API_DEF(SW_API_PT_TLS_SET, isisc_port_tls_set), \
+ SW_API_DEF(SW_API_PT_TLS_GET, isisc_port_tls_get), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, isisc_port_pri_propagation_set), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, isisc_port_pri_propagation_get), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_SET, isisc_port_default_svid_set), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_GET, isisc_port_default_svid_get), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_SET, isisc_port_default_cvid_set), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_GET, isisc_port_default_cvid_get), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, isisc_port_vlan_propagation_set), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, isisc_port_vlan_propagation_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, isisc_port_vlan_trans_add), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, isisc_port_vlan_trans_del), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, isisc_port_vlan_trans_get), \
+ SW_API_DEF(SW_API_QINQ_MODE_SET, isisc_qinq_mode_set), \
+ SW_API_DEF(SW_API_QINQ_MODE_GET, isisc_qinq_mode_get), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, isisc_port_qinq_role_set), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, isisc_port_qinq_role_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, isisc_port_vlan_trans_iterate), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_SET, isisc_port_mac_vlan_xlt_set), \
+ SW_API_DEF(SW_API_PT_MAC_VLAN_XLT_GET, isisc_port_mac_vlan_xlt_get), \
+ SW_API_DEF(SW_API_NETISOLATE_SET, isisc_netisolate_set), \
+ SW_API_DEF(SW_API_NETISOLATE_GET, isisc_netisolate_get),\
+ SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_SET, isisc_eg_trans_filter_bypass_en_set), \
+ SW_API_DEF(SW_API_EG_FLTR_BYPASS_EN_GET, isisc_eg_trans_filter_bypass_en_get),
+
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \
+ SW_API_DESC(SW_API_PT_TLS_SET) \
+ SW_API_DESC(SW_API_PT_TLS_GET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_GET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \
+ SW_API_DESC(SW_API_QINQ_MODE_SET) \
+ SW_API_DESC(SW_API_QINQ_MODE_GET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_SET) \
+ SW_API_DESC(SW_API_PT_MAC_VLAN_XLT_GET) \
+ SW_API_DESC(SW_API_NETISOLATE_SET) \
+ SW_API_DESC(SW_API_NETISOLATE_GET) \
+ SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_SET) \
+ SW_API_DESC(SW_API_EG_FLTR_BYPASS_EN_GET)
+
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, isisc_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, isisc_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,isisc_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, isisc_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIND, isisc_fdb_find), \
+ SW_API_DEF(SW_API_FDB_EXTEND_NEXT, isisc_fdb_extend_next), \
+ SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isisc_fdb_extend_first), \
+ SW_API_DEF(SW_API_FDB_TRANSFER, isisc_fdb_transfer), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, isisc_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, isisc_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, isisc_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, isisc_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_SET, isisc_fdb_vlan_ivl_svl_set),\
+ SW_API_DEF(SW_API_FDB_VLAN_IVL_SVL_GET, isisc_fdb_vlan_ivl_svl_get),\
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, isisc_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, isisc_fdb_age_time_get), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_SET, isisc_port_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_LIMIT_GET, isisc_port_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, isisc_port_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, isisc_port_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_SET, isisc_fdb_learn_limit_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_LIMIT_GET, isisc_fdb_learn_limit_get), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_SET, isisc_fdb_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_FDB_LEARN_EXCEED_CMD_GET, isisc_fdb_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_FDB_RESV_ADD, isisc_fdb_resv_add), \
+ SW_API_DEF(SW_API_FDB_RESV_DEL, isisc_fdb_resv_del), \
+ SW_API_DEF(SW_API_FDB_RESV_FIND, isisc_fdb_resv_find), \
+ SW_API_DEF(SW_API_FDB_RESV_ITERATE, isisc_fdb_resv_iterate), \
+ SW_API_DEF(SW_API_FDB_EXTEND_FIRST, isisc_fdb_extend_first), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_SET, isisc_fdb_port_learn_static_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_STATIC_GET, isisc_fdb_port_learn_static_get), \
+ SW_API_DEF(SW_API_FDB_PORT_ADD, isisc_fdb_port_add), \
+ SW_API_DEF(SW_API_FDB_PORT_DEL, isisc_fdb_port_del),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_EXTEND_NEXT) \
+ SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+ SW_API_DESC(SW_API_FDB_TRANSFER) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_SET) \
+ SW_API_DESC(SW_API_FDB_VLAN_IVL_SVL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_FDB_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_FDB_RESV_ADD) \
+ SW_API_DESC(SW_API_FDB_RESV_DEL) \
+ SW_API_DESC(SW_API_FDB_RESV_FIND) \
+ SW_API_DESC(SW_API_FDB_RESV_ITERATE) \
+ SW_API_DESC(SW_API_FDB_EXTEND_FIRST) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_STATIC_GET) \
+ SW_API_DESC(SW_API_FDB_PORT_ADD) \
+ SW_API_DESC(SW_API_FDB_PORT_DEL)
+
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+
+#ifdef IN_ACL
+#define ACL_API \
+ SW_API_DEF(SW_API_ACL_LIST_CREAT, isisc_acl_list_creat), \
+ SW_API_DEF(SW_API_ACL_LIST_DESTROY, isisc_acl_list_destroy), \
+ SW_API_DEF(SW_API_ACL_RULE_ADD, isisc_acl_rule_add), \
+ SW_API_DEF(SW_API_ACL_RULE_DELETE, isisc_acl_rule_delete), \
+ SW_API_DEF(SW_API_ACL_RULE_QUERY, isisc_acl_rule_query), \
+ SW_API_DEF(SW_API_ACL_LIST_BIND, isisc_acl_list_bind), \
+ SW_API_DEF(SW_API_ACL_LIST_UNBIND, isisc_acl_list_unbind), \
+ SW_API_DEF(SW_API_ACL_STATUS_SET, isisc_acl_status_set), \
+ SW_API_DEF(SW_API_ACL_STATUS_GET, isisc_acl_status_get), \
+ SW_API_DEF(SW_API_ACL_LIST_DUMP, isisc_acl_list_dump), \
+ SW_API_DEF(SW_API_ACL_RULE_DUMP, isisc_acl_rule_dump), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_SET, isisc_acl_port_udf_profile_set), \
+ SW_API_DEF(SW_API_ACL_PT_UDF_PROFILE_GET, isisc_acl_port_udf_profile_get), \
+ SW_API_DEF(SW_API_ACL_RULE_ACTIVE, isisc_acl_rule_active), \
+ SW_API_DEF(SW_API_ACL_RULE_DEACTIVE, isisc_acl_rule_deactive),\
+ SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_SET, isisc_acl_rule_src_filter_sts_set),\
+ SW_API_DEF(SW_API_ACL_RULE_SRC_FILTER_STS_GET, isisc_acl_rule_src_filter_sts_get), \
+ SW_API_DEF(SW_API_ACL_RULE_GET_OFFSET, isisc_acl_rule_get_offset),
+
+#define ACL_API_PARAM \
+ SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+ SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+ SW_API_DESC(SW_API_ACL_RULE_ADD) \
+ SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+ SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+ SW_API_DESC(SW_API_ACL_LIST_BIND) \
+ SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+ SW_API_DESC(SW_API_ACL_STATUS_SET) \
+ SW_API_DESC(SW_API_ACL_STATUS_GET) \
+ SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+ SW_API_DESC(SW_API_ACL_RULE_DUMP) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_SET) \
+ SW_API_DESC(SW_API_ACL_PT_UDF_PROFILE_GET) \
+ SW_API_DESC(SW_API_ACL_RULE_ACTIVE) \
+ SW_API_DESC(SW_API_ACL_RULE_DEACTIVE) \
+ SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_SET) \
+ SW_API_DESC(SW_API_ACL_RULE_SRC_FILTER_STS_GET)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, isisc_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, isisc_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, isisc_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, isisc_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, isisc_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, isisc_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_RED_EN_SET, isisc_qos_port_red_en_set),\
+ SW_API_DEF(SW_API_QOS_PT_RED_EN_GET, isisc_qos_port_red_en_get),\
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, isisc_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, isisc_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, isisc_qos_port_rx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, isisc_qos_port_rx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, isisc_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, isisc_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, isisc_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, isisc_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, isisc_qos_port_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, isisc_qos_port_sch_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_SET, isisc_qos_port_default_spri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_SPRI_GET, isisc_qos_port_default_spri_get), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_SET, isisc_qos_port_default_cpri_set), \
+ SW_API_DEF(SW_API_QOS_PT_DEF_CPRI_GET, isisc_qos_port_default_cpri_get), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_SET, isisc_qos_port_force_spri_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_SPRI_ST_GET, isisc_qos_port_force_spri_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_SET, isisc_qos_port_force_cpri_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_FORCE_CPRI_ST_GET, isisc_qos_port_force_cpri_status_get), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_SET, isisc_qos_queue_remark_table_set), \
+ SW_API_DEF(SW_API_QOS_QUEUE_REMARK_GET, isisc_qos_queue_remark_table_get),
+
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RED_EN_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RED_EN_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_SPRI_GET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_DEF_CPRI_GET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_SPRI_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_FORCE_CPRI_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_SET) \
+ SW_API_DESC(SW_API_QOS_QUEUE_REMARK_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, isisc_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, isisc_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, isisc_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, isisc_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, isisc_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, isisc_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, isisc_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, isisc_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, isisc_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, isisc_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, isisc_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, isisc_igmp_mld_entry_creat_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, isisc_igmp_mld_entry_static_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, isisc_igmp_mld_entry_static_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, isisc_igmp_mld_entry_leaky_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, isisc_igmp_mld_entry_leaky_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, isisc_igmp_mld_entry_v3_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, isisc_igmp_mld_entry_v3_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, isisc_igmp_mld_entry_queue_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, isisc_igmp_mld_entry_queue_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_SET, isisc_port_igmp_mld_learn_limit_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_LIMIT_GET, isisc_port_igmp_mld_learn_limit_get), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, isisc_port_igmp_mld_learn_exceed_cmd_set), \
+ SW_API_DEF(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, isisc_port_igmp_mld_learn_exceed_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SET, isisc_igmp_sg_entry_set), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_CLEAR, isisc_igmp_sg_entry_clear), \
+ SW_API_DEF(SW_API_IGMP_SG_ENTRY_SHOW, isisc_igmp_sg_entry_show),
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_LIMIT_GET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET) \
+ SW_API_DESC(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SET) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_CLEAR) \
+ SW_API_DESC(SW_API_IGMP_SG_ENTRY_SHOW)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, isisc_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, isisc_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, isisc_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, isisc_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, isisc_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, isisc_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, isisc_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, isisc_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, isisc_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, isisc_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, isisc_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, isisc_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, isisc_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, isisc_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, isisc_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, isisc_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_SET, isisc_rate_port_policer_set), \
+ SW_API_DEF(SW_API_RATE_PORT_POLICER_GET, isisc_rate_port_policer_get), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_SET, isisc_rate_port_shaper_set), \
+ SW_API_DEF(SW_API_RATE_PORT_SHAPER_GET, isisc_rate_port_shaper_get), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_SET, isisc_rate_queue_shaper_set), \
+ SW_API_DEF(SW_API_RATE_QUEUE_SHAPER_GET, isisc_rate_queue_shaper_get), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_SET, isisc_rate_acl_policer_set), \
+ SW_API_DEF(SW_API_RATE_ACL_POLICER_GET, isisc_rate_acl_policer_get), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_SET, isisc_rate_port_add_rate_byte_set), \
+ SW_API_DEF(SW_API_RATE_PT_ADDRATEBYTE_GET, isisc_rate_port_add_rate_byte_get), \
+ SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_SET, isisc_rate_port_gol_flow_en_set), \
+ SW_API_DEF(SW_API_RATE_PT_GOL_FLOW_EN_GET, isisc_rate_port_gol_flow_en_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_PORT_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_SET) \
+ SW_API_DESC(SW_API_RATE_QUEUE_SHAPER_GET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_SET) \
+ SW_API_DESC(SW_API_RATE_ACL_POLICER_GET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_SET) \
+ SW_API_DESC(SW_API_RATE_PT_ADDRATEBYTE_GET) \
+ SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_SET) \
+ SW_API_DESC(SW_API_RATE_PT_GOL_FLOW_EN_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, isisc_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, isisc_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, isisc_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, isisc_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, isisc_mib_status_get), \
+ SW_API_DEF(SW_API_PT_MIB_FLUSH_COUNTERS, isisc_mib_port_flush_counters), \
+ SW_API_DEF(SW_API_MIB_CPU_KEEP_SET, isisc_mib_cpukeep_set), \
+ SW_API_DEF(SW_API_MIB_CPU_KEEP_GET, isisc_mib_cpukeep_get),
+
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET)\
+ SW_API_DESC(SW_API_PT_MIB_FLUSH_COUNTERS) \
+ SW_API_DESC(SW_API_MIB_CPU_KEEP_SET) \
+ SW_API_DESC(SW_API_MIB_CPU_KEEP_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, isisc_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, isisc_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, isisc_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, isisc_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, isisc_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, isisc_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_SET, isisc_port_bc_filter_set), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_GET, isisc_port_bc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, isisc_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, isisc_cpu_port_status_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, isisc_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, isisc_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, isisc_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, isisc_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, isisc_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, isisc_port_dhcp_get), \
+ SW_API_DEF(SW_API_ARP_CMD_SET, isisc_arp_cmd_set), \
+ SW_API_DEF(SW_API_ARP_CMD_GET, isisc_arp_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_CMD_SET, isisc_eapol_cmd_set), \
+ SW_API_DEF(SW_API_EAPOL_CMD_GET, isisc_eapol_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_SET, isisc_eapol_status_set), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_GET, isisc_eapol_status_get), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_SET, isisc_ripv1_status_set), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_GET, isisc_ripv1_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_SET, isisc_port_arp_req_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_REQ_STATUS_GET, isisc_port_arp_req_status_get), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_SET, isisc_port_arp_ack_status_set), \
+ SW_API_DEF(SW_API_PT_ARP_ACK_STATUS_GET, isisc_port_arp_ack_status_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_ADD, isisc_pppoe_session_table_add), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_DEL, isisc_pppoe_session_table_del), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_TABLE_GET, isisc_pppoe_session_table_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_SET, isisc_pppoe_session_id_set), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ID_GET, isisc_pppoe_session_id_get), \
+ SW_API_DEF(SW_API_INTR_MASK_SET, isisc_intr_mask_set), \
+ SW_API_DEF(SW_API_INTR_MASK_GET, isisc_intr_mask_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_GET, isisc_intr_status_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_CLEAR, isisc_intr_status_clear), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_SET, isisc_intr_port_link_mask_set), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_MASK_GET, isisc_intr_port_link_mask_get), \
+ SW_API_DEF(SW_API_INTR_PORT_LINK_STATUS_GET, isisc_intr_port_link_status_get),\
+ SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_SET, isisc_intr_mask_mac_linkchg_set), \
+ SW_API_DEF(SW_API_INTR_MASK_MAC_LINKCHG_GET, isisc_intr_mask_mac_linkchg_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_GET, isisc_intr_status_mac_linkchg_get), \
+ SW_API_DEF(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, isisc_intr_status_mac_linkchg_clear), \
+ SW_API_DEF(SW_API_CPU_VID_EN_SET, isisc_cpu_vid_en_set), \
+ SW_API_DEF(SW_API_CPU_VID_EN_GET, isisc_cpu_vid_en_get), \
+ SW_API_DEF(SW_API_RTD_PPPOE_EN_SET, isisc_rtd_pppoe_en_set), \
+ SW_API_DEF(SW_API_RTD_PPPOE_EN_GET, isisc_rtd_pppoe_en_get),
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET) \
+ SW_API_DESC(SW_API_ARP_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_GET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_REQ_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_SET) \
+ SW_API_DESC(SW_API_PT_ARP_ACK_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_TABLE_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_SET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ID_GET) \
+ SW_API_DESC(SW_API_INTR_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_CLEAR) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_SET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_MASK_GET) \
+ SW_API_DESC(SW_API_INTR_PORT_LINK_STATUS_GET) \
+ SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_SET) \
+ SW_API_DESC(SW_API_INTR_MASK_MAC_LINKCHG_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_GET) \
+ SW_API_DESC(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR) \
+ SW_API_DESC(SW_API_CPU_VID_EN_SET) \
+ SW_API_DESC(SW_API_CPU_VID_EN_GET) \
+ SW_API_DESC(SW_API_RTD_PPPOE_EN_SET) \
+ SW_API_DESC(SW_API_RTD_PPPOE_EN_GET)
+
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, isisc_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, isisc_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#ifdef IN_COSMAP
+#define COSMAP_API \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_SET, isisc_cosmap_dscp_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_PRI_GET, isisc_cosmap_dscp_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_SET, isisc_cosmap_dscp_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_TO_DP_GET, isisc_cosmap_dscp_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_SET, isisc_cosmap_up_to_pri_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_PRI_GET, isisc_cosmap_up_to_pri_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_SET, isisc_cosmap_up_to_dp_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_TO_DP_GET, isisc_cosmap_up_to_dp_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_SET, isisc_cosmap_pri_to_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_QU_GET, isisc_cosmap_pri_to_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_SET, isisc_cosmap_pri_to_ehqueue_set), \
+ SW_API_DEF(SW_API_COSMAP_PRI_TO_EHQU_GET, isisc_cosmap_pri_to_ehqueue_get), \
+ SW_API_DEF(SW_API_COSMAP_EG_REMARK_SET, isisc_cosmap_egress_remark_set), \
+ SW_API_DEF(SW_API_COSMAP_EG_REMARK_GET, isisc_cosmap_egress_remark_get),
+
+#define COSMAP_API_PARAM \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_PRI_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_TO_DP_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_SET) \
+ SW_API_DESC(SW_API_COSMAP_PRI_TO_EHQU_GET) \
+ SW_API_DESC(SW_API_COSMAP_EG_REMARK_SET) \
+ SW_API_DESC(SW_API_COSMAP_EG_REMARK_GET)
+#else
+#define COSMAP_API
+#define COSMAP_API_PARAM
+#endif
+
+#ifdef IN_SEC
+#define SEC_API \
+ SW_API_DEF(SW_API_SEC_NORM_SET, isisc_sec_norm_item_set), \
+ SW_API_DEF(SW_API_SEC_NORM_GET, isisc_sec_norm_item_get),
+
+#define SEC_API_PARAM \
+ SW_API_DESC(SW_API_SEC_NORM_SET) \
+ SW_API_DESC(SW_API_SEC_NORM_GET)
+#else
+#define SEC_API
+#define SEC_API_PARAM
+#endif
+
+#ifdef IN_IP
+#define IP_API \
+ SW_API_DEF(SW_API_IP_HOST_ADD, isisc_ip_host_add), \
+ SW_API_DEF(SW_API_IP_HOST_DEL, isisc_ip_host_del), \
+ SW_API_DEF(SW_API_IP_HOST_GET, isisc_ip_host_get), \
+ SW_API_DEF(SW_API_IP_HOST_NEXT, isisc_ip_host_next), \
+ SW_API_DEF(SW_API_IP_HOST_COUNTER_BIND, isisc_ip_host_counter_bind), \
+ SW_API_DEF(SW_API_IP_HOST_PPPOE_BIND, isisc_ip_host_pppoe_bind), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_SET, isisc_ip_pt_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_PT_ARP_LEARN_GET, isisc_ip_pt_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_SET, isisc_ip_arp_learn_set), \
+ SW_API_DEF(SW_API_IP_ARP_LEARN_GET, isisc_ip_arp_learn_get), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_SET, isisc_ip_source_guard_set), \
+ SW_API_DEF(SW_API_IP_SOURCE_GUARD_GET, isisc_ip_source_guard_get), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_SET, isisc_ip_arp_guard_set), \
+ SW_API_DEF(SW_API_IP_ARP_GUARD_GET, isisc_ip_arp_guard_get), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_SET, isisc_ip_route_status_set), \
+ SW_API_DEF(SW_API_IP_ROUTE_STATUS_GET, isisc_ip_route_status_get), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_ADD, isisc_ip_intf_entry_add), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_DEL, isisc_ip_intf_entry_del), \
+ SW_API_DEF(SW_API_IP_INTF_ENTRY_NEXT, isisc_ip_intf_entry_next), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_SET, isisc_ip_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_IP_UNK_SOURCE_CMD_GET, isisc_ip_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_SET, isisc_arp_unk_source_cmd_set), \
+ SW_API_DEF(SW_API_ARP_UNK_SOURCE_CMD_GET, isisc_arp_unk_source_cmd_get), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_SET, isisc_ip_age_time_set), \
+ SW_API_DEF(SW_API_IP_AGE_TIME_GET, isisc_ip_age_time_get), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_SET, isisc_ip_wcmp_hash_mode_set), \
+ SW_API_DEF(SW_API_WCMP_HASH_MODE_GET, isisc_ip_wcmp_hash_mode_get),
+
+#define IP_API_PARAM \
+ SW_API_DESC(SW_API_IP_HOST_ADD) \
+ SW_API_DESC(SW_API_IP_HOST_DEL) \
+ SW_API_DESC(SW_API_IP_HOST_GET) \
+ SW_API_DESC(SW_API_IP_HOST_NEXT) \
+ SW_API_DESC(SW_API_IP_HOST_COUNTER_BIND) \
+ SW_API_DESC(SW_API_IP_HOST_PPPOE_BIND) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_PT_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_SET) \
+ SW_API_DESC(SW_API_IP_ARP_LEARN_GET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_SOURCE_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_SET) \
+ SW_API_DESC(SW_API_IP_ARP_GUARD_GET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_SET) \
+ SW_API_DESC(SW_API_IP_ROUTE_STATUS_GET) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_ADD) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_DEL) \
+ SW_API_DESC(SW_API_IP_INTF_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_IP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_UNK_SOURCE_CMD_GET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_IP_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_WCMP_HASH_MODE_GET)
+
+#else
+#define IP_API
+#define IP_API_PARAM
+#endif
+
+#ifdef IN_NAT
+#define NAT_API \
+ SW_API_DEF(SW_API_NAT_ADD, isisc_nat_add), \
+ SW_API_DEF(SW_API_NAT_DEL, isisc_nat_del), \
+ SW_API_DEF(SW_API_NAT_GET, isisc_nat_get), \
+ SW_API_DEF(SW_API_NAT_NEXT, isisc_nat_next), \
+ SW_API_DEF(SW_API_NAT_COUNTER_BIND, isisc_nat_counter_bind), \
+ SW_API_DEF(SW_API_NAPT_ADD, isisc_napt_add), \
+ SW_API_DEF(SW_API_NAPT_DEL, isisc_napt_del), \
+ SW_API_DEF(SW_API_NAPT_GET, isisc_napt_get), \
+ SW_API_DEF(SW_API_NAPT_NEXT, isisc_napt_next), \
+ SW_API_DEF(SW_API_NAPT_COUNTER_BIND, isisc_napt_counter_bind), \
+ SW_API_DEF(SW_API_NAT_STATUS_SET, isisc_nat_status_set), \
+ SW_API_DEF(SW_API_NAT_STATUS_GET, isisc_nat_status_get), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_SET, isisc_nat_hash_mode_set), \
+ SW_API_DEF(SW_API_NAT_HASH_MODE_GET, isisc_nat_hash_mode_get), \
+ SW_API_DEF(SW_API_NAPT_STATUS_SET, isisc_napt_status_set), \
+ SW_API_DEF(SW_API_NAPT_STATUS_GET, isisc_napt_status_get), \
+ SW_API_DEF(SW_API_NAPT_MODE_SET, isisc_napt_mode_set), \
+ SW_API_DEF(SW_API_NAPT_MODE_GET, isisc_napt_mode_get), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_SET, isisc_nat_prv_base_addr_set), \
+ SW_API_DEF(SW_API_PRV_BASE_ADDR_GET, isisc_nat_prv_base_addr_get), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_ADD, isisc_nat_pub_addr_add), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_DEL, isisc_nat_pub_addr_del), \
+ SW_API_DEF(SW_API_PUB_ADDR_ENTRY_NEXT, isisc_nat_pub_addr_next), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_SET, isisc_nat_unk_session_cmd_set), \
+ SW_API_DEF(SW_API_NAT_UNK_SESSION_CMD_GET, isisc_nat_unk_session_cmd_get), \
+ SW_API_DEF(SW_API_PRV_BASE_MASK_SET, isisc_nat_prv_base_mask_set), \
+ SW_API_DEF(SW_API_PRV_BASE_MASK_GET, isisc_nat_prv_base_mask_get),
+
+#define NAT_API_PARAM \
+ SW_API_DESC(SW_API_NAT_ADD) \
+ SW_API_DESC(SW_API_NAT_DEL) \
+ SW_API_DESC(SW_API_NAT_GET) \
+ SW_API_DESC(SW_API_NAT_NEXT) \
+ SW_API_DESC(SW_API_NAT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAPT_ADD) \
+ SW_API_DESC(SW_API_NAPT_DEL) \
+ SW_API_DESC(SW_API_NAPT_GET) \
+ SW_API_DESC(SW_API_NAPT_NEXT) \
+ SW_API_DESC(SW_API_NAPT_COUNTER_BIND) \
+ SW_API_DESC(SW_API_NAT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_SET) \
+ SW_API_DESC(SW_API_NAT_HASH_MODE_GET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_SET) \
+ SW_API_DESC(SW_API_NAPT_STATUS_GET) \
+ SW_API_DESC(SW_API_NAPT_MODE_SET) \
+ SW_API_DESC(SW_API_NAPT_MODE_GET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_SET) \
+ SW_API_DESC(SW_API_PRV_BASE_ADDR_GET) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_ADD) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_DEL) \
+ SW_API_DESC(SW_API_PUB_ADDR_ENTRY_NEXT) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_SET) \
+ SW_API_DESC(SW_API_NAT_UNK_SESSION_CMD_GET) \
+ SW_API_DESC(SW_API_PRV_BASE_MASK_SET) \
+ SW_API_DESC(SW_API_PRV_BASE_MASK_GET)
+#else
+#define NAT_API
+#define NAT_API_PARAM
+#endif
+
+#ifdef IN_TRUNK
+#define TRUNK_API \
+ SW_API_DEF(SW_API_TRUNK_GROUP_SET, isisc_trunk_group_set), \
+ SW_API_DEF(SW_API_TRUNK_GROUP_GET, isisc_trunk_group_get), \
+ SW_API_DEF(SW_API_TRUNK_HASH_SET, isisc_trunk_hash_mode_set), \
+ SW_API_DEF(SW_API_TRUNK_HASH_GET, isisc_trunk_hash_mode_get), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_SET, isisc_trunk_manipulate_sa_set), \
+ SW_API_DEF(SW_API_TRUNK_MAN_SA_GET, isisc_trunk_manipulate_sa_get),
+
+#define TRUNK_API_PARAM \
+ SW_API_DESC(SW_API_TRUNK_GROUP_SET) \
+ SW_API_DESC(SW_API_TRUNK_GROUP_GET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_SET) \
+ SW_API_DESC(SW_API_TRUNK_HASH_GET) \
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_SET)\
+ SW_API_DESC(SW_API_TRUNK_MAN_SA_GET)
+#else
+#define TRUNK_API
+#define TRUNK_API_PARAM
+#endif
+
+#ifdef IN_INTERFACECONTROL
+#define INTERFACECTRL_API \
+ SW_API_DEF(SW_API_MAC_MODE_SET, isisc_interface_mac_mode_set), \
+ SW_API_DEF(SW_API_MAC_MODE_GET, isisc_interface_mac_mode_get), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_SET, isisc_port_3az_status_set), \
+ SW_API_DEF(SW_API_PORT_3AZ_STATUS_GET, isisc_port_3az_status_get), \
+ SW_API_DEF(SW_API_PHY_MODE_SET, isisc_interface_phy_mode_set), \
+ SW_API_DEF(SW_API_PHY_MODE_GET, isisc_interface_phy_mode_get), \
+ SW_API_DEF(SW_API_FX100_CTRL_SET, isisc_interface_fx100_ctrl_set), \
+ SW_API_DEF(SW_API_FX100_CTRL_GET, isisc_interface_fx100_ctrl_get), \
+ SW_API_DEF(SW_API_FX100_STATUS_GET, isisc_interface_fx100_status_get), \
+ SW_API_DEF(SW_API_MAC06_EXCH_SET, isisc_interface_mac06_exch_set), \
+ SW_API_DEF(SW_API_MAC06_EXCH_GET, isisc_interface_mac06_exch_get),
+
+#define INTERFACECTRL_API_PARAM \
+ SW_API_DESC(SW_API_MAC_MODE_SET) \
+ SW_API_DESC(SW_API_MAC_MODE_GET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_SET) \
+ SW_API_DESC(SW_API_PORT_3AZ_STATUS_GET) \
+ SW_API_DESC(SW_API_PHY_MODE_SET) \
+ SW_API_DESC(SW_API_PHY_MODE_GET) \
+ SW_API_DESC(SW_API_FX100_CTRL_SET) \
+ SW_API_DESC(SW_API_FX100_CTRL_GET) \
+ SW_API_DESC(SW_API_FX100_STATUS_GET) \
+ SW_API_DESC(SW_API_MAC06_EXCH_SET) \
+ SW_API_DESC(SW_API_MAC06_EXCH_GET)
+
+#else
+#define INTERFACECTRL_API
+#define INTERFACECTRL_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, isisc_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, isisc_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, isisc_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, isisc_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, isisc_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, isisc_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, isisc_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ ACL_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ COSMAP_API \
+ SEC_API \
+ IP_API \
+ NAT_API \
+ TRUNK_API \
+ INTERFACECTRL_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ ACL_API_PARAM \
+ LED_API_PARAM \
+ COSMAP_API_PARAM \
+ SEC_API_PARAM \
+ IP_API_PARAM \
+ NAT_API_PARAM \
+ TRUNK_API_PARAM \
+ INTERFACECTRL_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_API_H_ */
diff --git a/include/hsl/isisc/isisc_cosmap.h b/include/hsl/isisc/isisc_cosmap.h
new file mode 100644
index 0000000..3126b20
--- /dev/null
+++ b/include/hsl/isisc/isisc_cosmap.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_cosmap ISISC_COSMAP
+ * @{
+ */
+#ifndef _ISISC_COSMAP_H_
+#define _ISISC_COSMAP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_cosmap.h"
+
+ sw_error_t isisc_cosmap_init(a_uint32_t dev_id);
+
+#ifdef IN_COSMAP
+#define ISISC_COSMAP_INIT(rv, dev_id) \
+ { \
+ rv = isisc_cosmap_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_COSMAP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t pri);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t dp);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * dp);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t pri);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * pri);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t dp);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up,
+ a_uint32_t * dp);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+ HSL_LOCAL sw_error_t
+ isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_COSMAP_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/hsl/isisc/isisc_fdb.h b/include/hsl/isisc/isisc_fdb.h
new file mode 100644
index 0000000..bc656ef
--- /dev/null
+++ b/include/hsl/isisc/isisc_fdb.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_fdb ISISC_FDB
+ * @{
+ */
+#ifndef _ISISC_FDB_H_
+#define _ISISC_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t isisc_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define ISISC_FDB_INIT(rv, dev_id) \
+ { \
+ rv = isisc_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flag);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * op,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port,
+ fal_port_t new_port, a_uint32_t fid,
+ fal_fdb_op_t * option);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode * smode);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t cnt);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * cnt);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_FDB_H_ */
+
+/**
+ * @}
+ */
+
diff --git a/include/hsl/isisc/isisc_fdb_prv.h b/include/hsl/isisc/isisc_fdb_prv.h
new file mode 100644
index 0000000..fcd50d9
--- /dev/null
+++ b/include/hsl/isisc/isisc_fdb_prv.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_FDB_PRV_H_
+#define _ISISC_FDB_PRV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+#define ARL_FIND_ENTRY 7
+#define ARL_TRANSFER_ENTRY 8
+
+#define ARL_FIRST_ENTRY 1001
+#define ARL_FLUSH_PORT_NO_STATIC 1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+#define ISISC_MAX_FID 4095
+#define ISISC_MAX_LEARN_LIMIT_CNT 2048
+#define ISISC_MAX_PORT_LEARN_LIMIT_CNT 1024
+
+ sw_error_t
+ inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_FDB_PRV_H_ */
+
diff --git a/include/hsl/isisc/isisc_igmp.h b/include/hsl/isisc/isisc_igmp.h
new file mode 100644
index 0000000..bd295d2
--- /dev/null
+++ b/include/hsl/isisc/isisc_igmp.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_igmp ISISC_IGMP
+ * @{
+ */
+#ifndef _ISISC_IGMP_H_
+#define _ISISC_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+#include "fal/fal_multi.h"
+
+ sw_error_t
+ isisc_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define ISISC_IGMP_INIT(rv, dev_id) \
+ { \
+ rv = isisc_igmp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_igmp_sg_entry_show(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isisc/isisc_init.h b/include/hsl/isisc/isisc_init.h
new file mode 100644
index 0000000..e72ff74
--- /dev/null
+++ b/include/hsl/isisc/isisc_init.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_init ISISC_INIT
+ * @{
+ */
+#ifndef _ISISC_INIT_H_
+#define _ISISC_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+ sw_error_t
+ isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+ sw_error_t
+ isisc_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/isisc/isisc_interface_ctrl.h b/include/hsl/isisc/isisc_interface_ctrl.h
new file mode 100644
index 0000000..c0b5032
--- /dev/null
+++ b/include/hsl/isisc/isisc_interface_ctrl.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_INTERFACE_CTRL_H_
+#define _ISISC_INTERFACE_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_interface_ctrl.h"
+
+ sw_error_t isisc_interface_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_INTERFACECONTROL
+#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = isisc_interface_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_INTERFACE_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_INTERFACE_CTRL_H_ */
+
diff --git a/include/hsl/isisc/isisc_ip.h b/include/hsl/isisc/isisc_ip.h
new file mode 100644
index 0000000..54f4ea0
--- /dev/null
+++ b/include/hsl/isisc/isisc_ip.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_IP_H_
+#define _ISISC_IP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_ip.h"
+
+ sw_error_t isisc_ip_init(a_uint32_t dev_id);
+
+ sw_error_t isisc_ip_reset(a_uint32_t dev_id);
+
+#ifdef IN_IP
+#define ISISC_IP_INIT(rv, dev_id) \
+ { \
+ rv = isisc_ip_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISISC_IP_RESET(rv, dev_id) \
+ { \
+ rv = isisc_ip_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_IP_INIT(rv, dev_id)
+#define ISISC_IP_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_IP_H_ */
diff --git a/include/hsl/isisc/isisc_leaky.h b/include/hsl/isisc/isisc_leaky.h
new file mode 100644
index 0000000..1191fa2
--- /dev/null
+++ b/include/hsl/isisc/isisc_leaky.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_LEAKY_H_
+#define _ISISC_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+ sw_error_t isisc_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define ISISC_LEAKY_INIT(rv, dev_id) \
+ { \
+ rv = isisc_leaky_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_LEAKY_H_ */
+
diff --git a/include/hsl/isisc/isisc_led.h b/include/hsl/isisc/isisc_led.h
new file mode 100644
index 0000000..85f7314
--- /dev/null
+++ b/include/hsl/isisc/isisc_led.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_LED_H_
+#define _ISISC_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+ sw_error_t
+ isisc_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define ISISC_LED_INIT(rv, dev_id) \
+ { \
+ rv = isisc_led_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_LED_H_ */
+
diff --git a/include/hsl/isisc/isisc_mib.h b/include/hsl/isisc/isisc_mib.h
new file mode 100644
index 0000000..43ca997
--- /dev/null
+++ b/include/hsl/isisc/isisc_mib.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_MIB_H_
+#define _ISISC_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ isisc_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define ISISC_MIB_INIT(rv, dev_id) \
+ { \
+ rv = isisc_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id);
+
+ HSL_LOCAL sw_error_t
+ isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_MIB_H_ */
+
diff --git a/include/hsl/isisc/isisc_mirror.h b/include/hsl/isisc/isisc_mirror.h
new file mode 100644
index 0000000..f225183
--- /dev/null
+++ b/include/hsl/isisc/isisc_mirror.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_MIRROR_H_
+#define _ISISC_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+ sw_error_t isisc_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define ISISC_MIRR_INIT(rv, dev_id) \
+ { \
+ rv = isisc_mirr_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_MIRROR_H_ */
+
diff --git a/include/hsl/isisc/isisc_misc.h b/include/hsl/isisc/isisc_misc.h
new file mode 100644
index 0000000..5655c47
--- /dev/null
+++ b/include/hsl/isisc/isisc_misc.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_MISC_H_
+#define _ISISC_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+ sw_error_t isisc_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define ISISC_MISC_INIT(rv, dev_id) \
+ { \
+ rv = isisc_misc_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag);
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap);
+
+ HSL_LOCAL sw_error_t
+ isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
+
diff --git a/include/hsl/isisc/isisc_nat.h b/include/hsl/isisc/isisc_nat.h
new file mode 100644
index 0000000..70263d1
--- /dev/null
+++ b/include/hsl/isisc/isisc_nat.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_NAT_H_
+#define _ISISC_NAT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+ sw_error_t isisc_nat_init(a_uint32_t dev_id);
+
+ sw_error_t isisc_nat_reset(a_uint32_t dev_id);
+
+#ifdef IN_NAT
+#define ISISC_NAT_INIT(rv, dev_id) \
+ { \
+ rv = isisc_nat_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISISC_NAT_RESET(rv, dev_id) \
+ { \
+ rv = isisc_nat_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_NAT_INIT(rv, dev_id)
+#define ISISC_NAT_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_NAT_H_ */
diff --git a/include/hsl/isisc/isisc_nat_helper.h b/include/hsl/isisc/isisc_nat_helper.h
new file mode 100644
index 0000000..4dfd052
--- /dev/null
+++ b/include/hsl/isisc/isisc_nat_helper.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_NAT_HELPER_H_
+#define _ISISC_NAT_HELPER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_nat.h"
+
+ sw_error_t nat_helper_init(a_uint32_t dev_id);
+
+ sw_error_t nat_helper_cleanup(a_uint32_t dev_id);
+
+#ifdef IN_NAT_HELPER
+#define ISISC_NAT_HELPER_INIT(rv, dev_id) \
+ { \
+ rv = nat_helper_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id) \
+ { \
+ rv = nat_helper_cleanup(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_NAT_HELPER_INIT(rv, dev_id)
+#define ISISC_NAT_HELPER_CLEANUP(rv, dev_id)
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_NAT_HELPER_H_ */
diff --git a/include/hsl/isisc/isisc_port_ctrl.h b/include/hsl/isisc/isisc_port_ctrl.h
new file mode 100644
index 0000000..f55852d
--- /dev/null
+++ b/include/hsl/isisc/isisc_port_ctrl.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_PORT_CTRL_H_
+#define _ISISC_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t isisc_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define ISISC_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = isisc_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_PORT_CTRL_H_ */
+
diff --git a/include/hsl/isisc/isisc_portvlan.h b/include/hsl/isisc/isisc_portvlan.h
new file mode 100644
index 0000000..a68dc79
--- /dev/null
+++ b/include/hsl/isisc/isisc_portvlan.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_PORTVLAN_H_
+#define _ISISC_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t isisc_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define ISISC_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = isisc_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_netisolate_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_PORTVLAN_H */
+
diff --git a/include/hsl/isisc/isisc_qos.h b/include/hsl/isisc/isisc_qos.h
new file mode 100644
index 0000000..cb92c7d
--- /dev/null
+++ b/include/hsl/isisc/isisc_qos.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_QOS_H_
+#define _ISISC_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+ sw_error_t isisc_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define ISISC_QOS_INIT(rv, dev_id) \
+ { \
+ rv = isisc_qos_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri);
+
+ sw_error_t
+ isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ sw_error_t
+ isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ sw_error_t
+ isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ sw_error_t
+ isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_QOS_H_ */
+
diff --git a/include/hsl/isisc/isisc_rate.h b/include/hsl/isisc/isisc_rate.h
new file mode 100644
index 0000000..e5bf403
--- /dev/null
+++ b/include/hsl/isisc/isisc_rate.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_RATE_H_
+#define _ISISC_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+ sw_error_t isisc_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define ISISC_RATE_INIT(rv, dev_id) \
+ { \
+ rv = isisc_rate_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_RATE_H_ */
+
diff --git a/include/hsl/isisc/isisc_reg.h b/include/hsl/isisc/isisc_reg.h
new file mode 100644
index 0000000..69a6fd4
--- /dev/null
+++ b/include/hsl/isisc/isisc_reg.h
@@ -0,0 +1,5452 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISISC_REG_H_
+#define _ISISC_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define S16E_DEVICE_ID 0x11
+#define S17C_DEVICE_ID 0x13 /* TBD */
+#define S17_REVISION_A 0x01
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+ /* ISIS Mask Control Register */
+#define MASK_CTL
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 1
+
+#define SOFT_RST
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define LOAD_EEPROM
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+
+
+
+ /* Port0 Pad Control Register */
+#define PORT0_PAD_CTRL
+#define PORT0_PAD_CTRL_ID 0
+#define PORT0_PAD_CTRL_OFFSET 0x0004
+#define PORT0_PAD_CTRL_E_LENGTH 4
+#define PORT0_PAD_CTRL_E_OFFSET 0
+#define PORT0_PAD_CTRL_NR_E 1
+
+#define RMII_MAC06_EXCH_EN
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BOFFSET 31
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_BLEN 1
+#define PORT0_PAD_CTRL_RMII_MAC06_EXCH_EN_FLAG HSL_RW
+
+#define RMII_MASTER_EN
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_BOFFSET 30
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_BLEN 1
+#define PORT0_PAD_CTRL_RMII_MASTER_EN_FLAG HSL_RW
+
+#define RMII_SLAVE_EN
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BOFFSET 29
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_BLEN 1
+#define PORT0_PAD_CTRL_RMII_SLAVE_EN_FLAG HSL_RW
+
+#define RMII_SEL
+#define PORT0_PAD_CTRL_RMII_SEL_BOFFSET 28
+#define PORT0_PAD_CTRL_RMII_SEL_BLEN 1
+#define PORT0_PAD_CTRL_RMII_SEL_FLAG HSL_RW
+
+#define RMII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BOFFSET 27
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_RMII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_RGMII_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BOFFSET 26
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_EN
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_TXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT0_PAD_CTRL_MAC0_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC0_RGMII_RXCLK_DELAY_SEL
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT0_PAD_CTRL_MAC0_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define SGMII_CLK125M_RX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BOFFSET 19
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_RX_SEL_FLAG HSL_RW
+
+#define SGMII_CLK125M_TX_SEL
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BOFFSET 18
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_CLK125M_TX_SEL_FLAG HSL_RW
+
+#define SGMII_FX100_EN
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_BOFFSET 17
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_FX100_EN_FLAG HSL_RW
+
+#define SGMII_PRBS_BERT_EN
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BOFFSET 16
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_PRBS_BERT_EN_FLAG HSL_RW
+
+#define SGMII_REM_PHY_LPBK_EN
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BOFFSET 15
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_BLEN 1
+#define PORT0_PAD_CTRL_SGMII_REM_PHY_LPBK_EN_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BOFFSET 14
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_EN_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BOFFSET 13
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BOFFSET 12
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_PIPE_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_EN
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BOFFSET 10
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC0_PHY_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_PHY_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_SGMII_EN
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BOFFSET 7
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_SGMII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BOFFSET 6
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BOFFSET 5
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_GMII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BOFFSET 4
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_SGMII_FORCE_SPEED
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BOFFSET 3
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_SGMII_FORCE_SPEED_FLAG HSL_RW
+
+#define MAC0_MAC_MII_EN
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BOFFSET 2
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC0_MAC_MII_TXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC0_MAC_MII_RXCLK_SEL
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT0_PAD_CTRL_MAC0_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* Port5 Pad Control Register */
+#define PORT5_PAD_CTRL
+#define PORT5_PAD_CTRL_ID 0
+#define PORT5_PAD_CTRL_OFFSET 0x0008
+#define PORT5_PAD_CTRL_E_LENGTH 4
+#define PORT5_PAD_CTRL_E_OFFSET 0
+#define PORT5_PAD_CTRL_NR_E 1
+
+#define MAC5_RGMII_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BOFFSET 26
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_EN
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC5_RGMII_TXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT5_PAD_CTRL_MAC5_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC5_RGMII_RXCLK_DELAY_SEL
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT5_PAD_CTRL_MAC5_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_PIPE_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_EN
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BOFFSET 10
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC5_PHY_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_PHY_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_MAC_MII_EN
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BOFFSET 2
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC5_MAC_MII_TXCLK_SEL
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC0_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC5_MAC_MII_RXCLK_SEL
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT5_PAD_CTRL_MAC5_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* Port6 Pad Control Register */
+#define PORT6_PAD_CTRL
+#define PORT6_PAD_CTRL_ID 0
+#define PORT6_PAD_CTRL_OFFSET 0x000c
+#define PORT6_PAD_CTRL_E_LENGTH 4
+#define PORT6_PAD_CTRL_E_OFFSET 0
+#define PORT6_PAD_CTRL_NR_E 1
+
+#define MAC6_RGMII_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BOFFSET 26
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BOFFSET 25
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_EN
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BOFFSET 24
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define MAC6_RGMII_TXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BOFFSET 22
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_BLEN 2
+#define PORT6_PAD_CTRL_MAC6_RGMII_TXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define MAC6_RGMII_RXCLK_DELAY_SEL
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BOFFSET 20
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_BLEN 2
+#define PORT6_PAD_CTRL_MAC6_RGMII_RXCLK_DELAY_SEL_FLAG HSL_RW
+
+#define PHY4_RGMII_EN
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BOFFSET 17
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_PHY4_RGMII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BOFFSET 14
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BOFFSET 13
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BOFFSET 12
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_PIPE_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BOFFSET 11
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_PIPE_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_EN
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BOFFSET 10
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_EN_FLAG HSL_RW
+
+#define MAC6_PHY_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BOFFSET 9
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_PHY_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BOFFSET 8
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_PHY_MII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_SGMII_EN
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BOFFSET 7
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_SGMII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BOFFSET 6
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BOFFSET 5
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_GMII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BOFFSET 4
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_GMII_RXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_MII_EN
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BOFFSET 2
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_EN_FLAG HSL_RW
+
+#define MAC6_MAC_MII_TXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BOFFSET 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_TXCLK_SEL_FLAG HSL_RW
+
+#define MAC6_MAC_MII_RXCLK_SEL
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BOFFSET 0
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_BLEN 1
+#define PORT6_PAD_CTRL_MAC6_MAC_MII_RXCLK_SEL_FLAG HSL_RW
+
+
+
+
+ /* SGMII Control Register */
+#define SGMII_CTRL
+#define SGMII_CTRL_ID 0
+#define SGMII_CTRL_OFFSET 0x00e0
+#define SGMII_CTRL_E_LENGTH 4
+#define SGMII_CTRL_E_OFFSET 0
+#define SGMII_CTRL_NR_E 1
+
+#define FULL_25M
+#define SGMII_CTRL_FULL_25M_BOFFSET 31
+#define SGMII_CTRL_FULL_25M_BLEN 1
+#define SGMII_CTRL_FULL_25M_FLAG HSL_RW
+
+#define HALF_25M
+#define SGMII_CTRL_HALF_25M_BOFFSET 30
+#define SGMII_CTRL_HALF_25M_BLEN 1
+#define SGMII_CTRL_HALF_25M_FLAG HSL_RW
+
+#define REMOTE_25M
+#define SGMII_CTRL_REMOTE_25M_BOFFSET 28
+#define SGMII_CTRL_REMOTE_25M_BLEN 2
+#define SGMII_CTRL_REMOTE_25M_FLAG HSL_RW
+
+#define NEXT_PAGE_25M
+#define SGMII_CTRL_NEXT_PAGE_25M_BOFFSET 27
+#define SGMII_CTRL_NEXT_PAGE_25M_BLEN 1
+#define SGMII_CTRL_NEXT_PAGE_25M_FLAG HSL_RW
+
+#define PAUSE_25M
+#define SGMII_CTRL_PAUSE_25M_BOFFSET 26
+#define SGMII_CTRL_PAUSE_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_25M_FLAG HSL_RW
+
+#define ASYM_PAUSE_25M
+#define SGMII_CTRL_ASYM_PAUSE_25M_BOFFSET 25
+#define SGMII_CTRL_ASYM_PAUSE_25M_BLEN 1
+#define SGMII_CTRL_ASYM_PAUSE_25M_FLAG HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW
+
+#define PAUSE_SG_25M
+#define SGMII_CTRL_PAUSE_SG_25M_BOFFSET 24
+#define SGMII_CTRL_PAUSE_SG_25M_BLEN 1
+#define SGMII_CTRL_PAUSE_SG_25M_FLAG HSL_RW
+
+#define MODE_CTRL_25M
+#define SGMII_CTRL_MODE_CTRL_25M_BOFFSET 22
+#define SGMII_CTRL_MODE_CTRL_25M_BLEN 2
+#define SGMII_CTRL_MODE_CTRL_25M_FLAG HSL_RW
+
+#define MR_LOOPBACK
+#define SGMII_CTRL_MR_LOOPBACK_BOFFSET 21
+#define SGMII_CTRL_MR_LOOPBACK_BLEN 1
+#define SGMII_CTRL_MR_LOOPBACK_FLAG HSL_RW
+
+#define MR_REG4_25M
+#define SGMII_CTRL_MR_REG4_25M_BOFFSET 20
+#define SGMII_CTRL_MR_REG4_25M_BLEN 1
+#define SGMII_CTRL_MR_REG4_25M_FLAG HSL_RW
+
+#define AUTO_LPI_25M
+#define SGMII_CTRL_AUTO_LPI_25M_BOFFSET 19
+#define SGMII_CTRL_AUTO_LPI_25M_BLEN 1
+#define SGMII_CTRL_AUTO_LPI_25M_FLAG HSL_RW
+
+#define PRBS_EN
+#define SGMII_CTRL_PRBS_EN_BOFFSET 18
+#define SGMII_CTRL_PRBS_EN_BLEN 1
+#define SGMII_CTRL_PRBS_EN_FLAG HSL_RW
+
+#define SGMII_TH_LOS1
+#define SGMII_CTRL_SGMII_TH_LOS1_BOFFSET 17
+#define SGMII_CTRL_SGMII_TH_LOS1_BLEN 1
+#define SGMII_CTRL_SGMII_TH_LOS1_FLAG HSL_RW
+
+#define DIS_AUTO_LPI_25M
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BOFFSET 16
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_BLEN 1
+#define SGMII_CTRL_DIS_AUTO_LPI_25M_FLAG HSL_RW
+
+#define SGMII_TH_LOS0
+#define SGMII_CTRL_SGMII_TH_LOS0_BOFFSET 15
+#define SGMII_CTRL_SGMII_TH_LOS0_BLEN 1
+#define SGMII_CTRL_SGMII_TH_LOS0_FLAG HSL_RW
+
+#define SGMII_CDR_BW
+#define SGMII_CTRL_SGMII_CDR_BW_BOFFSET 13
+#define SGMII_CTRL_SGMII_CDR_BW_BLEN 2
+#define SGMII_CTRL_SGMII_CDR_BW_FLAG HSL_RW
+
+#define SGMII_TXDR_CTRL
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BOFFSET 10
+#define SGMII_CTRL_SGMII_TXDR_CTRL_BLEN 3
+#define SGMII_CTRL_SGMII_TXDR_CTRL_FLAG HSL_RW
+
+#define SGMII_FIBER_MODE
+#define SGMII_CTRL_SGMII_FIBER_MODE_BOFFSET 8
+#define SGMII_CTRL_SGMII_FIBER_MODE_BLEN 2
+#define SGMII_CTRL_SGMII_FIBER_MODE_FLAG HSL_RW
+
+#define SGMII_SEL_125M
+#define SGMII_CTRL_SGMII_SEL_125M_BOFFSET 7
+#define SGMII_CTRL_SGMII_SEL_125M_BLEN 1
+#define SGMII_CTRL_SGMII_SEL_125M_FLAG HSL_RW
+
+#define SGMII_PLL_BW
+#define SGMII_CTRL_SGMII_PLL_BW_BOFFSET 6
+#define SGMII_CTRL_SGMII_PLL_BW_BLEN 1
+#define SGMII_CTRL_SGMII_PLL_BW_FLAG HSL_RW
+
+#define SGMII_HALFTX
+#define SGMII_CTRL_SGMII_HALFTX_BOFFSET 5
+#define SGMII_CTRL_SGMII_HALFTX_BLEN 1
+#define SGMII_CTRL_SGMII_HALFTX_FLAG HSL_RW
+
+#define SGMII_EN_SD
+#define SGMII_CTRL_SGMII_EN_SD_BOFFSET 4
+#define SGMII_CTRL_SGMII_EN_SD_BLEN 1
+#define SGMII_CTRL_SGMII_EN_SD_FLAG HSL_RW
+
+#define SGMII_EN_TX
+#define SGMII_CTRL_SGMII_EN_TX_BOFFSET 3
+#define SGMII_CTRL_SGMII_EN_TX_BLEN 1
+#define SGMII_CTRL_SGMII_EN_TX_FLAG HSL_RW
+
+#define SGMII_EN_RX
+#define SGMII_CTRL_SGMII_EN_RX_BOFFSET 2
+#define SGMII_CTRL_SGMII_EN_RX_BLEN 1
+#define SGMII_CTRL_SGMII_EN_RX_FLAG HSL_RW
+
+#define SGMII_EN_PLL
+#define SGMII_CTRL_SGMII_EN_PLL_BOFFSET 1
+#define SGMII_CTRL_SGMII_EN_PLL_BLEN 1
+#define SGMII_CTRL_SGMII_EN_PLL_FLAG HSL_RW
+
+#define SGMII_EN_LCKDT
+#define SGMII_CTRL_SGMII_EN_LCKDT_BOFFSET 0
+#define SGMII_CTRL_SGMII_EN_LCKDT_BLEN 1
+#define SGMII_CTRL_SGMII_EN_LCKDT_FLAG HSL_RW
+
+
+
+
+ /* Power On Strip Register */
+#define POWER_STRIP
+#define POWER_STRIP_ID 0
+#define POWER_STRIP_OFFSET 0x0010
+#define POWER_STRIP_E_LENGTH 4
+#define POWER_STRIP_E_OFFSET 0
+#define POWER_STRIP_NR_E 1
+
+#define POWER_ON_SEL
+#define POWER_STRIP_POWER_ON_SEL_BOFFSET 31
+#define POWER_STRIP_POWER_ON_SEL_BLEN 1
+#define POWER_STRIP_POWER_ON_SEL_FLAG HSL_RW
+
+#define PKG128_EN
+#define POWER_STRIP_PKG128_EN_BOFFSET 30
+#define POWER_STRIP_PKG128_EN_BLEN 1
+#define POWER_STRIP_PKG128_EN_FLAG HSL_RW
+
+#define PKG128_EN_LED
+#define POWER_STRIP_PKG128_EN_LED_BOFFSET 29
+#define POWER_STRIP_PKG128_EN_LED_BLEN 1
+#define POWER_STRIP_PKG128_EN_LED_FLAG HSL_RW
+
+#define S16_MODE
+#define POWER_STRIP_S16_MODE_BOFFSET 28
+#define POWER_STRIP_S16_MODE_BLEN 1
+#define POWER_STRIP_S16_MODE_FLAG HSL_RW
+
+#define INPUT_MODE
+#define POWER_STRIP_INPUT_MODE_BOFFSET 27
+#define POWER_STRIP_INPUT_MODE_BLEN 1
+#define POWER_STRIP_INPUT_MODE_FLAG HSL_RW
+
+#define SGMII_POWER_ON_SEL
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BOFFSET 26
+#define POWER_STRIP_SGMII_POWER_ON_SEL_BLEN 1
+#define POWER_STRIP_SGMII_POWER_ON_SEL_FLAG HSL_RW
+
+#define SPI_EN
+#define POWER_STRIP_SPI_EN_BOFFSET 25
+#define POWER_STRIP_SPI_EN_BLEN 1
+#define POWER_STRIP_SPI_EN_FLAG HSL_RW
+
+#define LED_OPEN_EN
+#define POWER_STRIP_LED_OPEN_EN_BOFFSET 24
+#define POWER_STRIP_LED_OPEN_EN_BLEN 1
+#define POWER_STRIP_LED_OPEN_EN_FLAG HSL_RW
+
+#define SGMII_RXIMP_50_70
+#define POWER_STRIP_SGMII_RXIMP_50_70_BOFFSET 23
+#define POWER_STRIP_SGMII_RXIMP_50_70_BLEN 1
+#define POWER_STRIP_SGMII_RXIMP_50_70_FLAG HSL_RW
+
+#define SGMII_TXIMP_50_70
+#define POWER_STRIP_SGMII_TXIMP_50_70_BOFFSET 22
+#define POWER_STRIP_SGMII_TXIMP_50_70_BLEN 1
+#define POWER_STRIP_SGMII_TXIMP_50_70_FLAG HSL_RW
+
+#define SGMII_SIGNAL_DETECT
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BOFFSET 21
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_BLEN 1
+#define POWER_STRIP_SGMII_SIGNAL_DETECT_FLAG HSL_RW
+
+#define LPW_EXIT
+#define POWER_STRIP_LPW_EXIT_BOFFSET 20
+#define POWER_STRIP_LPW_EXIT_BLEN 1
+#define POWER_STRIP_LPW_EXIT_FLAG HSL_RW
+
+#define MAN_EN
+#define POWER_STRIP_MAN_EN_BOFFSET 18
+#define POWER_STRIP_MAN_EN_BLEN 1
+#define POWER_STRIP_MAN_EN_FLAG HSL_RW
+
+#define HIB_EN
+#define POWER_STRIP_HIB_EN_BOFFSET 17
+#define POWER_STRIP_HIB_EN_BLEN 1
+#define POWER_STRIP_HIB_EN_FLAG HSL_RW
+
+#define POWER_DOWN_HW
+#define POWER_STRIP_POWER_DOWN_HW_BOFFSET 16
+#define POWER_STRIP_POWER_DOWN_HW_BLEN 1
+#define POWER_STRIP_POWER_DOWN_HW_FLAG HSL_RW
+
+#define BIST_BYPASS_CEL
+#define POWER_STRIP_BIST_BYPASS_CEL_BOFFSET 15
+#define POWER_STRIP_BIST_BYPASS_CEL_BLEN 1
+#define POWER_STRIP_BIST_BYPASS_CEL_FLAG HSL_RW
+
+#define BIST_BYPASS_CSR
+#define POWER_STRIP_BIST_BYPASS_CSR_BOFFSET 14
+#define POWER_STRIP_BIST_BYPASS_CSR_BLEN 1
+#define POWER_STRIP_BIST_BYPASS_CSR_FLAG HSL_RW
+
+#define HIB_PULSE_HW
+#define POWER_STRIP_HIB_PULSE_HW_BOFFSET 12
+#define POWER_STRIP_HIB_PULSE_HW_BLEN 1
+#define POWER_STRIP_HIB_PULSE_HW_FLAG HSL_RW
+
+#define GATE_25M_EN
+#define POWER_STRIP_GATE_25M_EN_BOFFSET 10
+#define POWER_STRIP_GATE_25M_EN_BLEN 1
+#define POWER_STRIP_GATE_25M_EN_FLAG HSL_RW
+
+#define SEL_ANA_RST
+#define POWER_STRIP_SEL_ANA_RST_BOFFSET 9
+#define POWER_STRIP_SEL_ANA_RST_BLEN 1
+#define POWER_STRIP_SEL_ANA_RST_FLAG HSL_RW
+
+#define SERDES_EN
+#define POWER_STRIP_SERDES_EN_BOFFSET 8
+#define POWER_STRIP_SERDES_EN_BLEN 1
+#define POWER_STRIP_SERDES_EN_FLAG HSL_RW
+
+#define SERDES_AN_EN
+#define POWER_STRIP_SERDES_AN_EN_BOFFSET 7
+#define POWER_STRIP_SERDES_AN_EN_BLEN 1
+#define POWER_STRIP_SERDES_AN_EN_FLAG HSL_RW
+
+#define RTL_MODE
+#define POWER_STRIP_RTL_MODE_BOFFSET 5
+#define POWER_STRIP_RTL_MODE_BLEN 1
+#define POWER_STRIP_RTL_MODE_FLAG HSL_RW
+
+#define PAD_CTRL_FOR25M
+#define POWER_STRIP_PAD_CTRL_FOR25M_BOFFSET 3
+#define POWER_STRIP_PAD_CTRL_FOR25M_BLEN 2
+#define POWER_STRIP_PAD_CTRL_FOR25M_FLAG HSL_RW
+
+#define PAD_CTRL
+#define POWER_STRIP_PAD_CTRL_BOFFSET 0
+#define POWER_STRIP_PAD_CTRL_BLEN 2
+#define POWER_STRIP_PAD_CTRL_FLAG HSL_RW
+
+
+
+
+ /* Global Interrupt Status Register1 */
+#define GBL_INT_STATUS1
+#define GBL_INT_STATUS1_ID 1
+#define GBL_INT_STATUS1_OFFSET 0x0024
+#define GBL_INT_STATUS1_E_LENGTH 4
+#define GBL_INT_STATUS1_E_OFFSET 0
+#define GBL_INT_STATUS1_NR_E 1
+
+#define LINK_CHG_INT_S
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BOFFSET 1
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_BLEN 7
+#define GBL_INT_STATUS1_LINK_CHG_INT_S_FLAG HSL_RW
+
+#define PHY_INT_S
+#define GBL_INT_STATUS1_PHY_INT_S_BOFFSET 15
+#define GBL_INT_STATUS1_PHY_INT_S_BLEN 1
+#define GBL_INT_STATUS1_PHY_INT_S_FLAG HSL_RO
+
+
+
+
+ /* Global Interrupt Mask Register1 */
+#define GBL_INT_MASK1
+#define GBL_INT_MASK1_ID 1
+#define GBL_INT_MASK1_OFFSET 0x002c
+#define GBL_INT_MASK1_E_LENGTH 4
+#define GBL_INT_MASK1_E_OFFSET 0
+#define GBL_INT_MASK1_NR_E 1
+
+#define LINK_CHG_INT_M
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BOFFSET 1
+#define GBL_INT_MASK1_LINK_CHG_INT_M_BLEN 7
+#define GBL_INT_MASK1_LINK_CHG_INT_M_FLAG HSL_RW
+
+#define PHY_INT_M
+#define GBL_INT_MASK1_PHY_INT_M_BOFFSET 15
+#define GBL_INT_MASK1_PHY_INT_M_BLEN 1
+#define GBL_INT_MASK1_PHY_INT_M_FLAG HSL_RO
+
+
+
+
+ /* Module Enable Register */
+#define MOD_ENABLE
+#define MOD_ENABLE_OFFSET 0x0030
+#define MOD_ENABLE_E_LENGTH 4
+#define MOD_ENABLE_E_OFFSET 0
+#define MOD_ENABLE_NR_E 1
+
+#define L3_EN
+#define MOD_ENABLE_L3_EN_BOFFSET 2
+#define MOD_ENABLE_L3_EN_BLEN 1
+#define MOD_ENABLE_L3_EN_FLAG HSL_RW
+
+#define ACL_EN
+#define MOD_ENABLE_ACL_EN_BOFFSET 1
+#define MOD_ENABLE_ACL_EN_BLEN 1
+#define MOD_ENABLE_ACL_EN_FLAG HSL_RW
+
+#define MIB_EN
+#define MOD_ENABLE_MIB_EN_BOFFSET 0
+#define MOD_ENABLE_MIB_EN_BLEN 1
+#define MOD_ENABLE_MIB_EN_FLAG HSL_RW
+
+
+
+
+ /* MIB Function Register */
+#define MIB_FUNC
+#define MIB_FUNC_OFFSET 0x0034
+#define MIB_FUNC_E_LENGTH 4
+#define MIB_FUNC_E_OFFSET 0
+#define MIB_FUNC_NR_E 1
+
+#define MIB_FUN
+#define MIB_FUNC_MIB_FUN_BOFFSET 24
+#define MIB_FUNC_MIB_FUN_BLEN 3
+#define MIB_FUNC_MIB_FUN_FLAG HSL_RW
+
+#define MIB_FLUSH_PORT
+#define MIB_FUNC_MIB_FLUSH_PORT_BOFFSET 21
+#define MIB_FUNC_MIB_FLUSH_PORT_BLEN 3
+#define MIB_FUNC_MIB_FLUSH_PORT_FLAG HSL_RW
+
+#define MIB_CPU_KEEP
+#define MIB_FUNC_MIB_CPU_KEEP_BOFFSET 20
+#define MIB_FUNC_MIB_CPU_KEEP_BLEN 1
+#define MIB_FUNC_MIB_CPU_KEEP_FLAG HSL_RW
+
+#define MIB_BUSY
+#define MIB_FUNC_MIB_BUSY_BOFFSET 17
+#define MIB_FUNC_MIB_BUSY_BLEN 1
+#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER
+#define MIB_FUNC_MIB_TIMER_BOFFSET 0
+#define MIB_FUNC_MIB_TIMER_BLEN 16
+#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW
+
+
+
+
+ /* Service tag Register */
+#define SERVICE_TAG
+#define SERVICE_TAG_OFFSET 0x0048
+#define SERVICE_TAG_E_LENGTH 4
+#define SERVICE_TAG_E_OFFSET 0
+#define SERVICE_TAG_NR_E 1
+
+#define STAG_MODE
+#define SERVICE_TAG_STAG_MODE_BOFFSET 17
+#define SERVICE_TAG_STAG_MODE_BLEN 1
+#define SERVICE_TAG_STAG_MODE_FLAG HSL_RW
+
+#define TAG_VALUE
+#define SERVICE_TAG_TAG_VALUE_BOFFSET 0
+#define SERVICE_TAG_TAG_VALUE_BLEN 16
+#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW
+
+
+
+
+ /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0060
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 1
+
+#define GLB_BYTE4
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+#define GLOBAL_MAC_ADDR1
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0064
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 1
+
+#define GLB_BYTE0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+
+
+
+ /* Max Size Register */
+#define MAX_SIZE
+#define MAX_SIZE_OFFSET 0x0078
+#define MAX_SIZE_E_LENGTH 4
+#define MAX_SIZE_E_OFFSET 0
+#define MAX_SIZE_NR_E 1
+
+#define MAX_FRAME_SIZE
+#define MAX_SIZE_MAX_FRAME_SIZE_BOFFSET 0
+#define MAX_SIZE_MAX_FRAME_SIZE_BLEN 14
+#define MAX_SIZE_MAX_FRAME_SIZE_FLAG HSL_RW
+
+
+
+
+ /* Flow Control Register */
+#define FLOW_CTL0 "fctl"
+#define FLOW_CTL0_ID 6
+#define FLOW_CTL0_OFFSET 0x0034
+#define FLOW_CTL0_E_LENGTH 4
+#define FLOW_CTL0_E_OFFSET 0
+#define FLOW_CTL0_NR_E 1
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL0_TEST_PAUSE_BLEN 1
+#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Flow Control1 Register */
+#define FLOW_CTL1 "fctl1"
+#define FLOW_CTL1_ID 6
+#define FLOW_CTL1_OFFSET 0x0038
+#define FLOW_CTL1_E_LENGTH 4
+#define FLOW_CTL1_E_OFFSET 0
+#define FLOW_CTL1_NR_E 1
+
+#define PORT_PAUSE_ON_THRES "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Port Status Register */
+#define PORT_STATUS
+#define PORT_STATUS_OFFSET 0x007c
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0004
+#define PORT_STATUS_NR_E 7
+
+#define FLOW_LINK_EN
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN 1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW
+
+#define AUTO_RX_FLOW
+#define PORT_STATUS_AUTO_RX_FLOW_BOFFSET 11
+#define PORT_STATUS_AUTO_RX_FLOW_BLEN 1
+#define PORT_STATUS_AUTO_RX_FLOW_FLAG HSL_RO
+
+#define AUTO_TX_FLOW
+#define PORT_STATUS_AUTO_TX_FLOW_BOFFSET 10
+#define PORT_STATUS_AUTO_TX_FLOW_BLEN 1
+#define PORT_STATUS_AUTO_TX_FLOW_FLAG HSL_RO
+
+#define LINK_EN
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW
+
+#define DUPLEX_MODE
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+
+
+
+ /* Header Ctl Register */
+#define HEADER_CTL
+#define HEADER_CTL_OFFSET 0x0098
+#define HEADER_CTL_E_LENGTH 4
+#define HEADER_CTL_E_OFFSET 0x0004
+#define HEADER_CTL_NR_E 1
+
+#define TYPE_LEN
+#define HEADER_CTL_TYPE_LEN_BOFFSET 16
+#define HEADER_CTL_TYPE_LEN_BLEN 1
+#define HEADER_CTL_TYPE_LEN_FLAG HSL_RW
+
+#define TYPE_VAL
+#define HEADER_CTL_TYPE_VAL_BOFFSET 0
+#define HEADER_CTL_TYPE_VAL_BLEN 16
+#define HEADER_CTL_TYPE_VAL_FLAG HSL_RW
+
+
+
+
+ /* Port Header Ctl Register */
+#define PORT_HDR_CTL
+#define PORT_HDR_CTL_OFFSET 0x009c
+#define PORT_HDR_CTL_E_LENGTH 4
+#define PORT_HDR_CTL_E_OFFSET 0x0004
+#define PORT_HDR_CTL_NR_E 7
+
+#define IPG_DEC_EN
+#define PORT_HDR_CTL_IPG_DEC_EN_BOFFSET 5
+#define PORT_HDR_CTL_IPG_DEC_EN_BLEN 1
+#define PORT_HDR_CTL_IPG_DEC_EN_FLAG HSL_RW
+
+#define LOOPBACK_EN
+#define PORT_HDR_CTL_LOOPBACK_EN_BOFFSET 4
+#define PORT_HDR_CTL_LOOPBACK_EN_BLEN 1
+#define PORT_HDR_CTL_LOOPBACK_EN_FLAG HSL_RW
+
+#define RXHDR_MODE
+#define PORT_HDR_CTL_RXHDR_MODE_BOFFSET 2
+#define PORT_HDR_CTL_RXHDR_MODE_BLEN 2
+#define PORT_HDR_CTL_RXHDR_MODE_FLAG HSL_RW
+
+#define TXHDR_MODE
+#define PORT_HDR_CTL_TXHDR_MODE_BOFFSET 0
+#define PORT_HDR_CTL_TXHDR_MODE_BLEN 2
+#define PORT_HDR_CTL_TXHDR_MODE_FLAG HSL_RW
+
+
+
+
+ /* EEE control Register */
+#define EEE_CTL
+#define EEE_CTL_OFFSET 0x0100
+#define EEE_CTL_E_LENGTH 4
+#define EEE_CTL_E_OFFSET 0
+#define EEE_CTL_NR_E 1
+
+#define LPI_STATE_REMAP_EN_5
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BOFFSET 13
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_5_FLAG HSL_RW
+
+#define LPI_EN_5
+#define EEE_CTL_LPI_EN_5_BOFFSET 12
+#define EEE_CTL_LPI_EN_5_BLEN 1
+#define EEE_CTL_LPI_EN_5_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_4
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BOFFSET 11
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_4_FLAG HSL_RW
+
+#define LPI_EN_4
+#define EEE_CTL_LPI_EN_4_BOFFSET 10
+#define EEE_CTL_LPI_EN_4_BLEN 1
+#define EEE_CTL_LPI_EN_4_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_3
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BOFFSET 9
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_3_FLAG HSL_RW
+
+#define LPI_EN_3
+#define EEE_CTL_LPI_EN_3_BOFFSET 8
+#define EEE_CTL_LPI_EN_3_BLEN 1
+#define EEE_CTL_LPI_EN_3_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_2
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BOFFSET 7
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_2_FLAG HSL_RW
+
+#define LPI_EN_2
+#define EEE_CTL_LPI_EN_2_BOFFSET 6
+#define EEE_CTL_LPI_EN_2_BLEN 1
+#define EEE_CTL_LPI_EN_2_FLAG HSL_RW
+
+#define LPI_STATE_REMAP_EN_1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BOFFSET 5
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_BLEN 1
+#define EEE_CTL_LPI_STATE_REMAP_EN_1_FLAG HSL_RW
+
+#define LPI_EN_1
+#define EEE_CTL_LPI_EN_1_BOFFSET 4
+#define EEE_CTL_LPI_EN_1_BLEN 1
+#define EEE_CTL_LPI_EN_1_FLAG HSL_RW
+
+
+
+
+ /* Frame Ack Ctl0 Register */
+#define FRAME_ACK_CTL0
+#define FRAME_ACK_CTL0_OFFSET 0x0210
+#define FRAME_ACK_CTL0_E_LENGTH 4
+#define FRAME_ACK_CTL0_E_OFFSET 0
+#define FRAME_ACK_CTL0_NR_E 1
+
+#define ARP_REQ_EN
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BOFFSET 6
+#define FRAME_ACK_CTL0_ARP_REQ_EN_BLEN 1
+#define FRAME_ACK_CTL0_ARP_REQ_EN_FLAG HSL_RW
+
+#define ARP_REP_EN
+#define FRAME_ACK_CTL0_ARP_REP_EN_BOFFSET 5
+#define FRAME_ACK_CTL0_ARP_REP_EN_BLEN 1
+#define FRAME_ACK_CTL0_ARP_REP_EN_FLAG HSL_RW
+
+#define DHCP_EN
+#define FRAME_ACK_CTL0_DHCP_EN_BOFFSET 4
+#define FRAME_ACK_CTL0_DHCP_EN_BLEN 1
+#define FRAME_ACK_CTL0_DHCP_EN_FLAG HSL_RW
+
+#define EAPOL_EN
+#define FRAME_ACK_CTL0_EAPOL_EN_BOFFSET 3
+#define FRAME_ACK_CTL0_EAPOL_EN_BLEN 1
+#define FRAME_ACK_CTL0_EAPOL_EN_FLAG HSL_RW
+
+#define LEAVE_EN
+#define FRAME_ACK_CTL0_LEAVE_EN_BOFFSET 2
+#define FRAME_ACK_CTL0_LEAVE_EN_BLEN 1
+#define FRAME_ACK_CTL0_LEAVE_EN_FLAG HSL_RW
+
+#define JOIN_EN
+#define FRAME_ACK_CTL0_JOIN_EN_BOFFSET 1
+#define FRAME_ACK_CTL0_JOIN_EN_BLEN 1
+#define FRAME_ACK_CTL0_JOIN_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BOFFSET 0
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_BLEN 1
+#define FRAME_ACK_CTL0_IGMP_MLD_EN_FLAG HSL_RW
+
+
+
+
+ /* Frame Ack Ctl1 Register */
+#define FRAME_ACK_CTL1
+#define FRAME_ACK_CTL1_OFFSET 0x0214
+#define FRAME_ACK_CTL1_E_LENGTH 4
+#define FRAME_ACK_CTL1_E_OFFSET 0
+#define FRAME_ACK_CTL1_NR_E 1
+
+#define PPPOE_EN
+#define FRAME_ACK_CTL1_PPPOE_EN_BOFFSET 25
+#define FRAME_ACK_CTL1_PPPOE_EN_BLEN 1
+#define FRAME_ACK_CTL1_PPPOE_EN_FLAG HSL_RW
+
+#define IGMP_V3_EN
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BOFFSET 24
+#define FRAME_ACK_CTL1_IGMP_V3_EN_BLEN 1
+#define FRAME_ACK_CTL1_IGMP_V3_EN_FLAG HSL_RW
+
+
+
+
+ /* Window Rule Ctl0 Register */
+#define WIN_RULE_CTL0
+#define WIN_RULE_CTL0_OFFSET 0x0218
+#define WIN_RULE_CTL0_E_LENGTH 4
+#define WIN_RULE_CTL0_E_OFFSET 0x4
+#define WIN_RULE_CTL0_NR_E 7
+
+#define L4_LENGTH
+#define WIN_RULE_CTL0_L4_LENGTH_BOFFSET 24
+#define WIN_RULE_CTL0_L4_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L4_LENGTH_FLAG HSL_RW
+
+#define L3_LENGTH
+#define WIN_RULE_CTL0_L3_LENGTH_BOFFSET 20
+#define WIN_RULE_CTL0_L3_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L3_LENGTH_FLAG HSL_RW
+
+#define L2_LENGTH
+#define WIN_RULE_CTL0_L2_LENGTH_BOFFSET 16
+#define WIN_RULE_CTL0_L2_LENGTH_BLEN 4
+#define WIN_RULE_CTL0_L2_LENGTH_FLAG HSL_RW
+
+#define L4_OFFSET
+#define WIN_RULE_CTL0_L4_OFFSET_BOFFSET 10
+#define WIN_RULE_CTL0_L4_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L4_OFFSET_FLAG HSL_RW
+
+#define L3_OFFSET
+#define WIN_RULE_CTL0_L3_OFFSET_BOFFSET 5
+#define WIN_RULE_CTL0_L3_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L3_OFFSET_FLAG HSL_RW
+
+#define L2_OFFSET
+#define WIN_RULE_CTL0_L2_OFFSET_BOFFSET 0
+#define WIN_RULE_CTL0_L2_OFFSET_BLEN 5
+#define WIN_RULE_CTL0_L2_OFFSET_FLAG HSL_RW
+
+
+
+
+ /* Window Rule Ctl1 Register */
+#define WIN_RULE_CTL1
+#define WIN_RULE_CTL1_OFFSET 0x0234
+#define WIN_RULE_CTL1_E_LENGTH 4
+#define WIN_RULE_CTL1_E_OFFSET 0x4
+#define WIN_RULE_CTL1_NR_E 7
+
+#define L3P_LENGTH
+#define WIN_RULE_CTL1_L3P_LENGTH_BOFFSET 20
+#define WIN_RULE_CTL1_L3P_LENGTH_BLEN 4
+#define WIN_RULE_CTL1_L3P_LENGTH_FLAG HSL_RW
+
+#define L2S_LENGTH
+#define WIN_RULE_CTL1_L2S_LENGTH_BOFFSET 16
+#define WIN_RULE_CTL1_L2S_LENGTH_BLEN 4
+#define WIN_RULE_CTL1_L2S_LENGTH_FLAG HSL_RW
+
+#define L3P_OFFSET
+#define WIN_RULE_CTL1_L3P_OFFSET_BOFFSET 5
+#define WIN_RULE_CTL1_L3P_OFFSET_BLEN 5
+#define WIN_RULE_CTL1_L3P_OFFSET_FLAG HSL_RW
+
+#define L2S_OFFSET
+#define WIN_RULE_CTL1_L2S_OFFSET_BOFFSET 0
+#define WIN_RULE_CTL1_L2S_OFFSET_BLEN 5
+#define WIN_RULE_CTL1_L2S_OFFSET_FLAG HSL_RW
+
+
+
+
+ /* Trunk Hash Mode Register */
+#define TRUNK_HASH_MODE
+#define TRUNK_HASH_MODE_OFFSET 0x0270
+#define TRUNK_HASH_MODE_E_LENGTH 4
+#define TRUNK_HASH_MODE_E_OFFSET 0x4
+#define TRUNK_HASH_MODE_NR_E 1
+
+#define DIP_EN
+#define TRUNK_HASH_MODE_DIP_EN_BOFFSET 3
+#define TRUNK_HASH_MODE_DIP_EN_BLEN 1
+#define TRUNK_HASH_MODE_DIP_EN_FLAG HSL_RW
+
+#define SIP_EN
+#define TRUNK_HASH_MODE_SIP_EN_BOFFSET 2
+#define TRUNK_HASH_MODE_SIP_EN_BLEN 1
+#define TRUNK_HASH_MODE_SIP_EN_FLAG HSL_RW
+
+#define SA_EN
+#define TRUNK_HASH_MODE_SA_EN_BOFFSET 1
+#define TRUNK_HASH_MODE_SA_EN_BLEN 1
+#define TRUNK_HASH_MODE_SA_EN_FLAG HSL_RW
+
+#define DA_EN
+#define TRUNK_HASH_MODE_DA_EN_BOFFSET 0
+#define TRUNK_HASH_MODE_DA_EN_BLEN 1
+#define TRUNK_HASH_MODE_DA_EN_FLAG HSL_RW
+
+
+
+
+ /* Vlan Table Function0 Register */
+#define VLAN_TABLE_FUNC0
+#define VLAN_TABLE_FUNC0_OFFSET 0x0610
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 1
+
+#define VT_VALID
+#define VLAN_TABLE_FUNC0_VT_VALID_BOFFSET 20
+#define VLAN_TABLE_FUNC0_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_VALID_FLAG HSL_RW
+
+#define IVL_EN
+#define VLAN_TABLE_FUNC0_IVL_EN_BOFFSET 19
+#define VLAN_TABLE_FUNC0_IVL_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_IVL_EN_FLAG HSL_RW
+
+#define LEARN_DIS
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BOFFSET 18
+#define VLAN_TABLE_FUNC0_LEARN_DIS_BLEN 1
+#define VLAN_TABLE_FUNC0_LEARN_DIS_FLAG HSL_RW
+
+#define VID_MEM
+#define VLAN_TABLE_FUNC0_VID_MEM_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VID_MEM_BLEN 14
+#define VLAN_TABLE_FUNC0_VID_MEM_FLAG HSL_RW
+
+#define VT_PRI_EN
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+ /* Vlan Table Function1 Register */
+#define VLAN_TABLE_FUNC1
+#define VLAN_TABLE_FUNC1_OFFSET 0x0614
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 1
+
+#define VT_BUSY
+#define VLAN_TABLE_FUNC1_VT_BUSY_BOFFSET 31
+#define VLAN_TABLE_FUNC1_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_BUSY_FLAG HSL_RW
+
+#define VLAN_ID
+#define VLAN_TABLE_FUNC1_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC1_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC1_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC1_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_FUNC
+#define VLAN_TABLE_FUNC1_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC1_VT_FUNC_FLAG HSL_RW
+
+
+
+
+ /* Address Table Function0 Register */
+#define ADDR_TABLE_FUNC0
+#define ADDR_TABLE_FUNC0_OFFSET 0x0600
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 1
+
+
+#define AT_ADDR_BYTE2
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE3_FLAG HSL_RW
+
+#define AT_ADDR_BYTE4
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+ /* Address Table Function1 Register */
+#define ADDR_TABLE_FUNC1
+#define ADDR_TABLE_FUNC1_OFFSET 0x0604
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 1
+
+#define SA_DROP_EN
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BOFFSET 30
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_SA_DROP_EN_FLAG HSL_RW
+
+#define MIRROR_EN
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BOFFSET 29
+#define ADDR_TABLE_FUNC1_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BOFFSET 28
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_SVL_EN
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BOFFSET 27
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_BLEN 1
+#define ADDR_TABLE_FUNC1_AT_SVL_EN_FLAG HSL_RW
+
+#define AT_PRI
+#define ADDR_TABLE_FUNC1_AT_PRI_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_PRI_BLEN 3
+#define ADDR_TABLE_FUNC1_AT_PRI_FLAG HSL_RW
+
+#define CROSS_PT
+#define ADDR_TABLE_FUNC1_CROSS_PT_BOFFSET 23
+#define ADDR_TABLE_FUNC1_CROSS_PT_BLEN 1
+#define ADDR_TABLE_FUNC1_CROSS_PT_FLAG HSL_RW
+
+#define DES_PORT
+#define ADDR_TABLE_FUNC1_DES_PORT_BOFFSET 16
+#define ADDR_TABLE_FUNC1_DES_PORT_BLEN 7
+#define ADDR_TABLE_FUNC1_DES_PORT_FLAG HSL_RW
+
+#define AT_ADDR_BYTE0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+ /* Address Table Function2 Register */
+#define ADDR_TABLE_FUNC2
+#define ADDR_TABLE_FUNC2_OFFSET 0x0608
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 1
+
+#define WL_EN
+#define ADDR_TABLE_FUNC2_WL_EN_BOFFSET 20
+#define ADDR_TABLE_FUNC2_WL_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_WL_EN_FLAG HSL_RW
+
+#define AT_VID
+#define ADDR_TABLE_FUNC2_AT_VID_BOFFSET 8
+#define ADDR_TABLE_FUNC2_AT_VID_BLEN 12
+#define ADDR_TABLE_FUNC2_AT_VID_FLAG HSL_RW
+
+#define SHORT_LOOP
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BOFFSET 7
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_BLEN 1
+#define ADDR_TABLE_FUNC2_SHORT_LOOP_FLAG HSL_RW
+
+#define COPY_TO_CPU
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 6
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 5
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define LEAKY_EN
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW
+
+#define AT_STATUS
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 0
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+ /* Address Table Function3 Register */
+#define ADDR_TABLE_FUNC3
+#define ADDR_TABLE_FUNC3_OFFSET 0x060c
+#define ADDR_TABLE_FUNC3_E_LENGTH 4
+#define ADDR_TABLE_FUNC3_E_OFFSET 0
+#define ADDR_TABLE_FUNC3_NR_E 1
+
+#define AT_BUSY
+#define ADDR_TABLE_FUNC3_AT_BUSY_BOFFSET 31
+#define ADDR_TABLE_FUNC3_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_BUSY_FLAG HSL_RW
+
+#define NEW_PORT_NUM
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BOFFSET 22
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_BLEN 3
+#define ADDR_TABLE_FUNC3_NEW_PORT_NUM_FLAG HSL_RW
+
+#define AT_INDEX
+#define ADDR_TABLE_FUNC3_AT_INDEX_BOFFSET 16
+#define ADDR_TABLE_FUNC3_AT_INDEX_BLEN 5
+#define ADDR_TABLE_FUNC3_AT_INDEX_FLAG HSL_RW
+
+#define AT_VID_EN
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BOFFSET 15
+#define ADDR_TABLE_FUNC3_AT_VID_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_VID_EN_FLAG HSL_RW
+
+#define AT_PORT_EN
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BOFFSET 14
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_PORT_EN_FLAG HSL_RW
+
+#define AT_MULTI_EN
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_MULTI_EN_FLAG HSL_RW
+
+#define AT_FULL_VIO
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC3_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC3_AT_PORT_NUM_FLAG HSL_RW
+
+#define FLUSH_ST_EN
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_BLEN 1
+#define ADDR_TABLE_FUNC3_FLUSH_ST_EN_FLAG HSL_RW
+
+#define AT_FUNC
+#define ADDR_TABLE_FUNC3_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC3_AT_FUNC_BLEN 4
+#define ADDR_TABLE_FUNC3_AT_FUNC_FLAG HSL_RW
+
+
+
+
+ /* Reserve Address Table0 Register */
+#define RESV_ADDR_TBL0
+#define RESV_ADDR_TBL0_OFFSET 0x3c000
+#define RESV_ADDR_TBL0_E_LENGTH 4
+#define RESV_ADDR_TBL0_E_OFFSET 0
+#define RESV_ADDR_TBL0_NR_E 1
+
+#define RESV_ADDR_BYTE2
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BOFFSET 24
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE2_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE3
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BOFFSET 16
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE3_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE4
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BOFFSET 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE4_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE5
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BOFFSET 0
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_BLEN 8
+#define RESV_ADDR_TBL0_RESV_ADDR_BYTE5_FLAG HSL_RW
+
+ /* Reserve Address Table1 Register */
+#define RESV_ADDR_TBL1
+#define RESV_ADDR_TBL1_OFFSET 0x3c004
+#define RESV_ADDR_TBL1_E_LENGTH 4
+#define RESV_ADDR_TBL1_E_OFFSET 0
+#define RESV_ADDR_TBL1_NR_E 1
+
+#define RESV_COPY_TO_CPU
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BOFFSET 31
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_BLEN 1
+#define RESV_ADDR_TBL1_RESV_COPY_TO_CPU_FLAG HSL_RW
+
+#define RESV_REDRCT_TO_CPU
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BOFFSET 30
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_BLEN 1
+#define RESV_ADDR_TBL1_RESV_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define RESV_LEAKY_EN
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BOFFSET 29
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_LEAKY_EN_FLAG HSL_RW
+
+#define RESV_MIRROR_EN
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BOFFSET 28
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_MIRROR_EN_FLAG HSL_RW
+
+#define RESV_PRI_EN
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BOFFSET 27
+#define RESV_ADDR_TBL1_RESV_PRI_EN_BLEN 1
+#define RESV_ADDR_TBL1_RESV_PRI_EN_FLAG HSL_RW
+
+#define RESV_PRI
+#define RESV_ADDR_TBL1_RESV_PRI_BOFFSET 24
+#define RESV_ADDR_TBL1_RESV_PRI_BLEN 3
+#define RESV_ADDR_TBL1_RESV_PRI_FLAG HSL_RW
+
+#define RESV_CROSS_PT
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BOFFSET 23
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_BLEN 1
+#define RESV_ADDR_TBL1_RESV_CROSS_PT_FLAG HSL_RW
+
+#define RESV_DES_PORT
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BOFFSET 16
+#define RESV_ADDR_TBL1_RESV_DES_PORT_BLEN 7
+#define RESV_ADDR_TBL1_RESV_DES_PORT_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BOFFSET 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_BLEN 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE0_FLAG HSL_RW
+
+#define RESV_ADDR_BYTE1
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BOFFSET 0
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_BLEN 8
+#define RESV_ADDR_TBL1_RESV_ADDR_BYTE1_FLAG HSL_RW
+
+ /* Reserve Address Table2 Register */
+#define RESV_ADDR_TBL2
+#define RESV_ADDR_TBL2_OFFSET 0x3c008
+#define RESV_ADDR_TBL2_E_LENGTH 4
+#define RESV_ADDR_TBL2_E_OFFSET 0
+#define RESV_ADDR_TBL2_NR_E 1
+
+#define RESV_STATUS
+#define RESV_ADDR_TBL2_RESV_STATUS_BOFFSET 0
+#define RESV_ADDR_TBL2_RESV_STATUS_BLEN 1
+#define RESV_ADDR_TBL2_RESV_STATUS_FLAG HSL_RW
+
+
+
+
+ /* Address Table Control Register */
+#define ADDR_TABLE_CTL
+#define ADDR_TABLE_CTL_OFFSET 0x0618
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 1
+
+#define ARL_INI_EN
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 31
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define LEARN_CHANGE_EN
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 30
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_LEAKY
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BOFFSET 29
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW
+
+#define IGMP_CREAT_EN
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BOFFSET 28
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_CREAT_EN_FLAG HSL_RW
+
+#define IGMP_PRI_EN
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BOFFSET 27
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_BLEN 1
+#define ADDR_TABLE_CTL_IGMP_PRI_EN_FLAG HSL_RW
+
+#define IGMP_PRI
+#define ADDR_TABLE_CTL_IGMP_PRI_BOFFSET 24
+#define ADDR_TABLE_CTL_IGMP_PRI_BLEN 3
+#define ADDR_TABLE_CTL_IGMP_PRI_FLAG HSL_RW
+
+#define IGMP_JOIN_STATIC
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BOFFSET 20
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_BLEN 4
+#define ADDR_TABLE_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW
+
+#define AGE_EN
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define LOOP_CHECK_TIMER
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BOFFSET 16
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_BLEN 3
+#define ADDR_TABLE_CTL_LOOP_CHECK_TIMER_FLAG HSL_RW
+
+#define AGE_TIME
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+
+
+
+ /* Global Forward Control0 Register */
+#define FORWARD_CTL0
+#define FORWARD_CTL0_OFFSET 0x0620
+#define FORWARD_CTL0_E_LENGTH 4
+#define FORWARD_CTL0_E_OFFSET 0
+#define FORWARD_CTL0_NR_E 1
+
+#define ARP_CMD
+#define FORWARD_CTL0_ARP_CMD_BOFFSET 26
+#define FORWARD_CTL0_ARP_CMD_BLEN 2
+#define FORWARD_CTL0_ARP_CMD_FLAG HSL_RW
+
+#define IP_NOT_FOUND
+#define FORWARD_CTL0_IP_NOT_FOUND_BOFFSET 24
+#define FORWARD_CTL0_IP_NOT_FOUND_BLEN 2
+#define FORWARD_CTL0_IP_NOT_FOUND_FLAG HSL_RW
+
+#define ARP_NOT_FOUND
+#define FORWARD_CTL0_ARP_NOT_FOUND_BOFFSET 22
+#define FORWARD_CTL0_ARP_NOT_FOUND_BLEN 2
+#define FORWARD_CTL0_ARP_NOT_FOUND_FLAG HSL_RW
+
+#define HASH_MODE
+#define FORWARD_CTL0_HASH_MODE_BOFFSET 20
+#define FORWARD_CTL0_HASH_MODE_BLEN 2
+#define FORWARD_CTL0_HASH_MODE_FLAG HSL_RW
+
+#define NAT_NOT_FOUND_DROP
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BOFFSET 17
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_BLEN 1
+#define FORWARD_CTL0_NAT_NOT_FOUND_DROP_FLAG HSL_RW
+
+#define SP_NOT_FOUND_DROP
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BOFFSET 16
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_BLEN 1
+#define FORWARD_CTL0_SP_NOT_FOUND_DROP_FLAG HSL_RW
+
+#define IGMP_LEAVE_DROP
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BOFFSET 14
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_BLEN 1
+#define FORWARD_CTL0_IGMP_LEAVE_DROP_FLAG HSL_RW
+
+#define ARL_UNI_LEAKY
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BOFFSET 13
+#define FORWARD_CTL0_ARL_UNI_LEAKY_BLEN 1
+#define FORWARD_CTL0_ARL_UNI_LEAKY_FLAG HSL_RW
+
+#define ARL_MUL_LEAKY
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BOFFSET 12
+#define FORWARD_CTL0_ARL_MUL_LEAKY_BLEN 1
+#define FORWARD_CTL0_ARL_MUL_LEAKY_FLAG HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BOFFSET 11
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_BLEN 1
+#define FORWARD_CTL0_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW
+
+#define CPU_PORT_EN
+#define FORWARD_CTL0_CPU_PORT_EN_BOFFSET 10
+#define FORWARD_CTL0_CPU_PORT_EN_BLEN 1
+#define FORWARD_CTL0_CPU_PORT_EN_FLAG HSL_RW
+
+#define PPPOE_RDT_EN
+#define FORWARD_CTL0_PPPOE_RDT_EN_BOFFSET 8
+#define FORWARD_CTL0_PPPOE_RDT_EN_BLEN 1
+#define FORWARD_CTL0_PPPOE_RDT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BOFFSET 4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_BLEN 4
+#define FORWARD_CTL0_MIRROR_PORT_NUM_FLAG HSL_RW
+
+#define IGMP_COPY_EN
+#define FORWARD_CTL0_IGMP_COPY_EN_BOFFSET 3
+#define FORWARD_CTL0_IGMP_COPY_EN_BLEN 1
+#define FORWARD_CTL0_IGMP_COPY_EN_FLAG HSL_RW
+
+#define RIP_CPY_EN
+#define FORWARD_CTL0_RIP_CPY_EN_BOFFSET 2
+#define FORWARD_CTL0_RIP_CPY_EN_BLEN 1
+#define FORWARD_CTL0_RIP_CPY_EN_FLAG HSL_RW
+
+#define EAPOL_CMD
+#define FORWARD_CTL0_EAPOL_CMD_BOFFSET 0
+#define FORWARD_CTL0_EAPOL_CMD_BLEN 1
+#define FORWARD_CTL0_EAPOL_CMD_FLAG HSL_RW
+
+ /* Global Forward Control1 Register */
+#define FORWARD_CTL1
+#define FORWARD_CTL1_OFFSET 0x0624
+#define FORWARD_CTL1_E_LENGTH 4
+#define FORWARD_CTL1_E_OFFSET 0
+#define FORWARD_CTL1_NR_E 1
+
+#define IGMP_DP
+#define FORWARD_CTL1_IGMP_DP_BOFFSET 24
+#define FORWARD_CTL1_IGMP_DP_BLEN 7
+#define FORWARD_CTL1_IGMP_DP_FLAG HSL_RW
+
+#define BC_FLOOD_DP
+#define FORWARD_CTL1_BC_FLOOD_DP_BOFFSET 16
+#define FORWARD_CTL1_BC_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_BC_FLOOD_DP_FLAG HSL_RW
+
+#define MUL_FLOOD_DP
+#define FORWARD_CTL1_MUL_FLOOD_DP_BOFFSET 8
+#define FORWARD_CTL1_MUL_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_MUL_FLOOD_DP_FLAG HSL_RW
+
+#define UNI_FLOOD_DP
+#define FORWARD_CTL1_UNI_FLOOD_DP_BOFFSET 0
+#define FORWARD_CTL1_UNI_FLOOD_DP_BLEN 7
+#define FORWARD_CTL1_UNI_FLOOD_DP_FLAG HSL_RW
+
+
+
+
+ /* Global Learn Limit Ctl Register */
+#define GLOBAL_LEARN_LIMIT_CTL
+#define GLOBAL_LEARN_LIMIT_CTL_OFFSET 0x0628
+#define GLOBAL_LEARN_LIMIT_CTL_E_LENGTH 4
+#define GLOBAL_LEARN_LIMIT_CTL_E_OFFSET 0
+#define GLOBAL_LEARN_LIMIT_CTL_NR_E 1
+
+#define GOL_SA_LEARN_LIMIT_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BOFFSET 12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_BLEN 1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_EN_FLAG HSL_RW
+
+#define GOL_SA_LEARN_LIMIT_DROP_EN
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 13
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_BLEN 1
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define GOL_SA_LEARN_CNT
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BOFFSET 0
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_BLEN 12
+#define GLOBAL_LEARN_LIMIT_CTL_GOL_SA_LEARN_CNT_FLAG HSL_RW
+
+
+
+
+ /* DSCP To Priority Register */
+#define DSCP_TO_PRI
+#define DSCP_TO_PRI_OFFSET 0x0630
+#define DSCP_TO_PRI_E_LENGTH 4
+#define DSCP_TO_PRI_E_OFFSET 0x0004
+#define DSCP_TO_PRI_NR_E 8
+
+
+
+
+ /* UP To Priority Register */
+#define UP_TO_PRI
+#define UP_TO_PRI_OFFSET 0x0650
+#define UP_TO_PRI_E_LENGTH 4
+#define UP_TO_PRI_E_OFFSET 0x0004
+#define UP_TO_PRI_NR_E 1
+
+
+
+
+ /* Port Lookup control Register */
+#define PORT_LOOKUP_CTL
+#define PORT_LOOKUP_CTL_OFFSET 0x0660
+#define PORT_LOOKUP_CTL_E_LENGTH 4
+#define PORT_LOOKUP_CTL_E_OFFSET 0x000c
+#define PORT_LOOKUP_CTL_NR_E 7
+
+#define MULTI_DROP_EN
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BOFFSET 31
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_BLEN 1
+#define PORT_LOOKUP_CTL_MULTI_DROP_EN_FLAG HSL_RW
+
+#define UNI_LEAKY_EN
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BOFFSET 28
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_UNI_LEAKY_EN_FLAG HSL_RW
+
+#define MUL_LEAKY_EN
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BOFFSET 27
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_MUL_LEAKY_EN_FLAG HSL_RW
+
+#define ARP_LEAKY_EN
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BOFFSET 26
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_BLEN 1
+#define PORT_LOOKUP_CTL_ARP_LEAKY_EN_FLAG HSL_RW
+
+#define ING_MIRROR_EN
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BOFFSET 25
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_LOOKUP_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define PORT_LOOP_BACK
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BOFFSET 21
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_BLEN 1
+#define PORT_LOOKUP_CTL_PORT_LOOP_BACK_FLAG HSL_RW
+
+#define LEARN_EN
+#define PORT_LOOKUP_CTL_LEARN_EN_BOFFSET 20
+#define PORT_LOOKUP_CTL_LEARN_EN_BLEN 1
+#define PORT_LOOKUP_CTL_LEARN_EN_FLAG HSL_RW
+
+#define PORT_STATE
+#define PORT_LOOKUP_CTL_PORT_STATE_BOFFSET 16
+#define PORT_LOOKUP_CTL_PORT_STATE_BLEN 3
+#define PORT_LOOKUP_CTL_PORT_STATE_FLAG HSL_RW
+
+#define FORCE_PVLAN
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BOFFSET 10
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_BLEN 1
+#define PORT_LOOKUP_CTL_FORCE_PVLAN_FLAG HSL_RW
+
+#define DOT1Q_MODE
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BOFFSET 8
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_BLEN 2
+#define PORT_LOOKUP_CTL_DOT1Q_MODE_FLAG HSL_RW
+
+#define PORT_VID_MEM
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BOFFSET 0
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_BLEN 7
+#define PORT_LOOKUP_CTL_PORT_VID_MEM_FLAG HSL_RW
+
+
+
+
+ /* Priority Control Register */
+#define PRI_CTL
+#define PRI_CTL_OFFSET 0x0664
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x000c
+#define PRI_CTL_NR_E 7
+
+#define EG_MAC_BASE_VLAN_EN
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BOFFSET 20
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_BLEN 1
+#define PRI_CTL_EG_MAC_BASE_VLAN_EN_FLAG HSL_RW
+
+#define DA_PRI_EN
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+
+
+ /* Port Learn Limit Ctl Register */
+#define PORT_LEARN_LIMIT_CTL
+#define PORT_LEARN_LIMIT_CTL_OFFSET 0x0668
+#define PORT_LEARN_LIMIT_CTL_E_LENGTH 4
+#define PORT_LEARN_LIMIT_CTL_E_OFFSET 0x000c
+#define PORT_LEARN_LIMIT_CTL_NR_E 7
+
+#define IGMP_JOIN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BOFFSET 29
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define SA_LEARN_LIMIT_DROP_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BOFFSET 28
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_DROP_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BOFFSET 27
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_LIMIT_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_CNT
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BOFFSET 16
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_BLEN 11
+#define PORT_LEARN_LIMIT_CTL_IGMP_JOIN_CNT_FLAG HSL_RW
+
+#define SA_LEARN_STATUS
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BOFFSET 12
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_BLEN 4
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_STATUS_FLAG HSL_RW
+
+#define SA_LEARN_LIMIT_EN
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BOFFSET 11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_BLEN 1
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_LIMIT_EN_FLAG HSL_RW
+
+#define SA_LEARN_CNT
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BOFFSET 0
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_BLEN 11
+#define PORT_LEARN_LIMIT_CTL_SA_LEARN_CNT_FLAG HSL_RW
+
+
+
+ /* Global Trunk Ctl0 Register */
+#define GOL_TRUNK_CTL0
+#define GOL_TRUNK_CTL0_OFFSET 0x0700
+#define GOL_TRUNK_CTL0_E_LENGTH 4
+#define GOL_TRUNK_CTL0_E_OFFSET 0x4
+#define GOL_TRUNK_CTL0_NR_E 1
+
+
+ /* Global Trunk Ctl1 Register */
+#define GOL_TRUNK_CTL1
+#define GOL_TRUNK_CTL1_OFFSET 0x0704
+#define GOL_TRUNK_CTL1_E_LENGTH 4
+#define GOL_TRUNK_CTL1_E_OFFSET 0x4
+#define GOL_TRUNK_CTL1_NR_E 2
+
+
+ /* ACL Forward source filter Register */
+#define ACL_FWD_SRC_FILTER_CTL0
+#define ACL_FWD_SRC_FILTER_CTL0_OFFSET 0x0710
+#define ACL_FWD_SRC_FILTER_CTL0_E_LENGTH 4
+#define ACL_FWD_SRC_FILTER_CTL0_E_OFFSET 0x4
+#define ACL_FWD_SRC_FILTER_CTL0_NR_E 3
+
+
+ /* VLAN translation register */
+#define VLAN_TRANS
+#define VLAN_TRANS_OFFSET 0x0418
+#define VLAN_TRANS_E_LENGTH 4
+#define VLAN_TRANS_E_OFFSET 0
+#define VLAN_TRANS_NR_E 7
+
+#define EG_FLTR_BYPASS_EN
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BOFFSET 1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_BLEN 1
+#define VLAN_TRANS_EG_FLTR_BYPASS_EN_FLAG HSL_RW
+
+#define NET_ISO
+#define VLAN_TRANS_NET_ISO_BOFFSET 0
+#define VLAN_TRANS_NET_ISO_BLEN 1
+#define VLAN_TRANS_NET_ISO_FLAG HSL_RW
+
+
+ /* Port vlan0 Register */
+#define PORT_VLAN0
+#define PORT_VLAN0_OFFSET 0x0420
+#define PORT_VLAN0_E_LENGTH 4
+#define PORT_VLAN0_E_OFFSET 0x0008
+#define PORT_VLAN0_NR_E 7
+
+#define ING_CPRI
+#define PORT_VLAN0_ING_CPRI_BOFFSET 29
+#define PORT_VLAN0_ING_CPRI_BLEN 3
+#define PORT_VLAN0_ING_CPRI_FLAG HSL_RW
+
+#define ING_FORCE_CPRI
+#define PORT_VLAN0_ING_FORCE_CPRI_BOFFSET 28
+#define PORT_VLAN0_ING_FORCE_CPRI_BLEN 1
+#define PORT_VLAN0_ING_FORCE_CPRI_FLAG HSL_RW
+
+#define DEF_CVID
+#define PORT_VLAN0_DEF_CVID_BOFFSET 16
+#define PORT_VLAN0_DEF_CVID_BLEN 12
+#define PORT_VLAN0_DEF_CVID_FLAG HSL_RW
+
+#define ING_SPRI
+#define PORT_VLAN0_ING_SPRI_BOFFSET 13
+#define PORT_VLAN0_ING_SPRI_BLEN 3
+#define PORT_VLAN0_ING_SPRI_FLAG HSL_RW
+
+#define ING_FORCE_SPRI
+#define PORT_VLAN0_ING_FORCE_SPRI_BOFFSET 12
+#define PORT_VLAN0_ING_FORCE_SPRI_BLEN 1
+#define PORT_VLAN0_ING_FORCE_SPRI_FLAG HSL_RW
+
+#define DEF_SVID
+#define PORT_VLAN0_DEF_SVID_BOFFSET 0
+#define PORT_VLAN0_DEF_SVID_BLEN 12
+#define PORT_VLAN0_DEF_SVID_FLAG HSL_RW
+
+ /* Port vlan1 Register */
+#define PORT_VLAN1
+#define PORT_VLAN1_OFFSET 0x0424
+#define PORT_VLAN1_E_LENGTH 4
+#define PORT_VLAN1_E_OFFSET 0x0008
+#define PORT_VLAN1_NR_E 7
+
+#define EG_VLAN_MODE
+#define PORT_VLAN1_EG_VLAN_MODE_BOFFSET 12
+#define PORT_VLAN1_EG_VLAN_MODE_BLEN 2
+#define PORT_VLAN1_EG_VLAN_MODE_FLAG HSL_RW
+
+#define VLAN_DIS
+#define PORT_VLAN1_VLAN_DIS_BOFFSET 11
+#define PORT_VLAN1_VLAN_DIS_BLEN 1
+#define PORT_VLAN1_VLAN_DIS_FLAG HSL_RW
+
+#define SP_CHECK_EN
+#define PORT_VLAN1_SP_CHECK_EN_BOFFSET 10
+#define PORT_VLAN1_SP_CHECK_EN_BLEN 1
+#define PORT_VLAN1_SP_CHECK_EN_FLAG HSL_RW
+
+#define COREP_EN
+#define PORT_VLAN1_COREP_EN_BOFFSET 9
+#define PORT_VLAN1_COREP_EN_BLEN 1
+#define PORT_VLAN1_COREP_EN_FLAG HSL_RW
+
+#define FORCE_DEF_VID
+#define PORT_VLAN1_FORCE_DEF_VID_BOFFSET 8
+#define PORT_VLAN1_FORCE_DEF_VID_BLEN 1
+#define PORT_VLAN1_FORCE_DEF_VID_FLAG HSL_RW
+
+#define TLS_EN
+#define PORT_VLAN1_TLS_EN_BOFFSET 7
+#define PORT_VLAN1_TLS_EN_BLEN 1
+#define PORT_VLAN1_TLS_EN_FLAG HSL_RW
+
+#define PROPAGATION_EN
+#define PORT_VLAN1_PROPAGATION_EN_BOFFSET 6
+#define PORT_VLAN1_PROPAGATION_EN_BLEN 1
+#define PORT_VLAN1_PROPAGATION_EN_FLAG HSL_RW
+
+#define CLONE
+#define PORT_VLAN1_CLONE_BOFFSET 5
+#define PORT_VLAN1_CLONE_BLEN 1
+#define PORT_VLAN1_CLONE_FLAG HSL_RW
+
+#define PRI_PROPAGATION
+#define PORT_VLAN1_PRI_PROPAGATION_BOFFSET 4
+#define PORT_VLAN1_PRI_PROPAGATION_BLEN 1
+#define PORT_VLAN1_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define IN_VLAN_MODE
+#define PORT_VLAN1_IN_VLAN_MODE_BOFFSET 2
+#define PORT_VLAN1_IN_VLAN_MODE_BLEN 2
+#define PORT_VLAN1_IN_VLAN_MODE_FLAG HSL_RW
+
+
+ /* Route Default VID Register */
+#define ROUTER_DEFV
+#define ROUTER_DEFV_OFFSET 0x0c70
+#define ROUTER_DEFV_E_LENGTH 4
+#define ROUTER_DEFV_E_OFFSET 0x0004
+#define ROUTER_DEFV_NR_E 4
+
+
+ /* Route Egress VLAN Mode Register */
+#define ROUTER_EG
+#define ROUTER_EG_OFFSET 0x0c80
+#define ROUTER_EG_E_LENGTH 4
+#define ROUTER_EG_E_OFFSET 0x0004
+#define ROUTER_EG_NR_E 1
+
+
+
+
+ /* Mdio control Register */
+#define MDIO_CTRL "mctrl"
+#define MDIO_CTRL_ID 24
+#define MDIO_CTRL_OFFSET 0x0098
+#define MDIO_CTRL_E_LENGTH 4
+#define MDIO_CTRL_E_OFFSET 0
+#define MDIO_CTRL_NR_E 1
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define CMD "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET 27
+#define MDIO_CTRL_CMD_BLEN 1
+#define MDIO_CTRL_CMD_FLAG HSL_RW
+
+#define SUP_PRE "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET 26
+#define MDIO_CTRL_SUP_PRE_BLEN 1
+#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW
+
+#define PHY_ADDR "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET 21
+#define MDIO_CTRL_PHY_ADDR_BLEN 5
+#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW
+
+#define REG_ADDR "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET 16
+#define MDIO_CTRL_REG_ADDR_BLEN 5
+#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW
+
+#define DATA "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET 0
+#define MDIO_CTRL_DATA_BLEN 16
+#define MDIO_CTRL_DATA_FLAG HSL_RW
+
+
+
+
+ /* BIST control Register */
+#define BIST_CTRL "bctrl"
+#define BIST_CTRL_ID 24
+#define BIST_CTRL_OFFSET 0x00a0
+#define BIST_CTRL_E_LENGTH 4
+#define BIST_CTRL_E_OFFSET 0
+#define BIST_CTRL_NR_E 1
+
+#define BIST_BUSY "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET 31
+#define BIST_CTRL_BIST_BUSY_BLEN 1
+#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW
+
+#define ONE_ERR "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET 30
+#define BIST_CTRL_ONE_ERR_BLEN 1
+#define BIST_CTRL_ONE_ERR_FLAG HSL_RO
+
+#define ERR_MEM "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET 24
+#define BIST_CTRL_ERR_MEM_BLEN 4
+#define BIST_CTRL_ERR_MEM_FLAG HSL_RO
+
+#define PTN_EN2 "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET 22
+#define BIST_CTRL_PTN_EN2_BLEN 1
+#define BIST_CTRL_PTN_EN2_FLAG HSL_RW
+
+#define PTN_EN1 "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET 21
+#define BIST_CTRL_PTN_EN1_BLEN 1
+#define BIST_CTRL_PTN_EN1_FLAG HSL_RW
+
+#define PTN_EN0 "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET 20
+#define BIST_CTRL_PTN_EN0_BLEN 1
+#define BIST_CTRL_PTN_EN0_FLAG HSL_RW
+
+#define ERR_PTN "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET 16
+#define BIST_CTRL_ERR_PTN_BLEN 2
+#define BIST_CTRL_ERR_PTN_FLAG HSL_RO
+
+#define ERR_CNT "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET 13
+#define BIST_CTRL_ERR_CNT_BLEN 2
+#define BIST_CTRL_ERR_CNT_FLAG HSL_RO
+
+#define ERR_ADDR "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET 0
+#define BIST_CTRL_ERR_ADDR_BLEN 12
+#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO
+
+
+
+
+ /* BIST recover Register */
+#define BIST_RCV "brcv"
+#define BIST_RCV_ID 24
+#define BIST_RCV_OFFSET 0x00a4
+#define BIST_RCV_E_LENGTH 4
+#define BIST_RCV_E_OFFSET 0
+#define BIST_RCV_NR_E 1
+
+#define RCV_EN "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET 31
+#define BIST_RCV_RCV_EN_BLEN 1
+#define BIST_RCV_RCV_EN_FLAG HSL_RW
+
+#define RCV_ADDR "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET 0
+#define BIST_RCV_RCV_ADDR_BLEN 12
+#define BIST_RCV_RCV_ADDR_FLAG HSL_RW
+
+
+
+
+ /* LED control Register */
+#define LED_CTRL "ledctrl"
+#define LED_CTRL_ID 25
+#define LED_CTRL_OFFSET 0x0050
+#define LED_CTRL_E_LENGTH 4
+#define LED_CTRL_E_OFFSET 0
+#define LED_CTRL_NR_E 3
+
+#define PATTERN_EN "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET 14
+#define LED_CTRL_PATTERN_EN_BLEN 2
+#define LED_CTRL_PATTERN_EN_FLAG HSL_RW
+
+#define FULL_LIGHT_EN "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN 1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW
+
+#define HALF_LIGHT_EN "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN 1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW
+
+#define POWERON_LIGHT_EN "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW
+
+#define GE_LIGHT_EN "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10
+#define LED_CTRL_GE_LIGHT_EN_BLEN 1
+#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW
+
+#define FE_LIGHT_EN "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9
+#define LED_CTRL_FE_LIGHT_EN_BLEN 1
+#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW
+
+#define ETH_LIGHT_EN "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN 1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW
+
+#define COL_BLINK_EN "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET 7
+#define LED_CTRL_COL_BLINK_EN_BLEN 1
+#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW
+
+#define RX_BLINK_EN "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET 5
+#define LED_CTRL_RX_BLINK_EN_BLEN 1
+#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW
+
+#define TX_BLINK_EN "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET 4
+#define LED_CTRL_TX_BLINK_EN_BLEN 1
+#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW
+
+#define LINKUP_OVER_EN "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN 1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW
+
+#define BLINK_FREQ "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET 0
+#define LED_CTRL_BLINK_FREQ_BLEN 2
+#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW
+
+ /* LED control Register */
+#define LED_PATTERN "ledpatten"
+#define LED_PATTERN_ID 25
+#define LED_PATTERN_OFFSET 0x005c
+#define LED_PATTERN_E_LENGTH 4
+#define LED_PATTERN_E_OFFSET 0
+#define LED_PATTERN_NR_E 1
+
+
+#define P3L2_MODE
+#define LED_PATTERN_P3L2_MODE_BOFFSET 24
+#define LED_PATTERN_P3L2_MODE_BLEN 2
+#define LED_PATTERN_P3L2_MODE_FLAG HSL_RW
+
+#define P3L1_MODE
+#define LED_PATTERN_P3L1_MODE_BOFFSET 22
+#define LED_PATTERN_P3L1_MODE_BLEN 2
+#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW
+
+#define P3L0_MODE
+#define LED_PATTERN_P3L0_MODE_BOFFSET 20
+#define LED_PATTERN_P3L0_MODE_BLEN 2
+#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW
+
+#define P2L2_MODE
+#define LED_PATTERN_P2L2_MODE_BOFFSET 18
+#define LED_PATTERN_P2L2_MODE_BLEN 2
+#define LED_PATTERN_P2L2_MODE_FLAG HSL_RW
+
+#define P2L1_MODE
+#define LED_PATTERN_P2L1_MODE_BOFFSET 16
+#define LED_PATTERN_P2L1_MODE_BLEN 2
+#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW
+
+#define P2L0_MODE
+#define LED_PATTERN_P2L0_MODE_BOFFSET 14
+#define LED_PATTERN_P2L0_MODE_BLEN 2
+#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW
+
+#define P1L2_MODE
+#define LED_PATTERN_P1L2_MODE_BOFFSET 12
+#define LED_PATTERN_P1L2_MODE_BLEN 2
+#define LED_PATTERN_P1L2_MODE_FLAG HSL_RW
+
+#define P1L1_MODE
+#define LED_PATTERN_P1L1_MODE_BOFFSET 10
+#define LED_PATTERN_P1L1_MODE_BLEN 2
+#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW
+
+#define P1L0_MODE
+#define LED_PATTERN_P1L0_MODE_BOFFSET 8
+#define LED_PATTERN_P1L0_MODE_BLEN 2
+#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW
+
+
+
+
+ /* Pri To Queue Register */
+#define PRI_TO_QUEUE
+#define PRI_TO_QUEUE_OFFSET 0x0814
+#define PRI_TO_QUEUE_E_LENGTH 4
+#define PRI_TO_QUEUE_E_OFFSET 0x0004
+#define PRI_TO_QUEUE_NR_E 1
+
+
+
+
+ /* Pri To EhQueue Register */
+#define PRI_TO_EHQUEUE
+#define PRI_TO_EHQUEUE_OFFSET 0x0810
+#define PRI_TO_EHQUEUE_E_LENGTH 4
+#define PRI_TO_EHQUEUE_E_OFFSET 0x0004
+#define PRI_TO_EHQUEUE_NR_E 1
+
+
+
+
+ /*Global Flow Control Register*/
+#define QM_CTRL_REG
+#define QM_CTRL_REG_OFFSET 0X0808
+#define QM_CTRL_REG_E_LENGTH 4
+#define QM_CTRL_REG_E_OFFSET 0x0004
+#define QM_CTRL_REG_NR_E 1
+
+#define GOL_FLOW_EN
+#define QM_CTRL_REG_GOL_FLOW_EN_BOFFSET 16
+#define QM_CTRL_REG_GOL_FLOW_EN_BLEN 7
+#define QM_CTRL_REG_GOL_FLOW_EN_FLAG HSL_RW
+
+#define QM_FUNC_TEST
+#define QM_CTRL_REG_QM_FUNC_TEST_BOFFSET 10
+#define QM_CTRL_REG_QM_FUNC_TEST_BLEN 1
+#define QM_CTRL_REG_QM_FUNC_TEST_FLAG HSL_RW
+
+#define RATE_DROP_EN
+#define QM_CTRL_REG_RATE_DROP_EN_BOFFSET 7
+#define QM_CTRL_REG_RATE_DROP_EN_BLEN 1
+#define QM_CTRL_REG_RATE_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_EN
+#define QM_CTRL_REG_FLOW_DROP_EN_BOFFSET 6
+#define QM_CTRL_REG_FLOW_DROP_EN_BLEN 1
+#define QM_CTRL_REG_FLOW_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_CNT
+#define QM_CTRL_REG_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTRL_REG_FLOW_DROP_CNT_BLEN 6
+#define QM_CTRL_REG_FLOW_DROP_CNT_FLAG HSL_RW
+
+
+
+
+ /* Port HOL CTL0 Register */
+#define PORT_HOL_CTL0
+#define PORT_HOL_CTL0_OFFSET 0x0970
+#define PORT_HOL_CTL0_E_LENGTH 4
+#define PORT_HOL_CTL0_E_OFFSET 0x0008
+#define PORT_HOL_CTL0_NR_E 7
+
+#define PORT_DESC_NR
+#define PORT_HOL_CTL0_PORT_DESC_NR_BOFFSET 24
+#define PORT_HOL_CTL0_PORT_DESC_NR_BLEN 6
+#define PORT_HOL_CTL0_PORT_DESC_NR_FLAG HSL_RW
+
+#define QUEUE5_DESC_NR
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BOFFSET 20
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE5_DESC_NR_FLAG HSL_RW
+
+#define QUEUE4_DESC_NR
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BOFFSET 16
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE4_DESC_NR_FLAG HSL_RW
+
+#define QUEUE3_DESC_NR
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BOFFSET 12
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE3_DESC_NR_FLAG HSL_RW
+
+#define QUEUE2_DESC_NR
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BOFFSET 8
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE2_DESC_NR_FLAG HSL_RW
+
+#define QUEUE1_DESC_NR
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BOFFSET 4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE1_DESC_NR_FLAG HSL_RW
+
+#define QUEUE0_DESC_NR
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BOFFSET 0
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_BLEN 4
+#define PORT_HOL_CTL0_QUEUE0_DESC_NR_FLAG HSL_RW
+
+ /* Port HOL CTL1 Register */
+#define PORT_HOL_CTL1
+#define PORT_HOL_CTL1_OFFSET 0x0974
+#define PORT_HOL_CTL1_E_LENGTH 4
+#define PORT_HOL_CTL1_E_OFFSET 0x0008
+#define PORT_HOL_CTL1_NR_E 7
+
+#define EG_MIRROR_EN
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BOFFSET 16
+#define PORT_HOL_CTL1_EG_MIRROR_EN_BLEN 1
+#define PORT_HOL_CTL1_EG_MIRROR_EN_FLAG HSL_RW
+
+#define PORT_RED_EN
+#define PORT_HOL_CTL1_PORT_RED_EN_BOFFSET 8
+#define PORT_HOL_CTL1_PORT_RED_EN_BLEN 1
+#define PORT_HOL_CTL1_PORT_RED_EN_FLAG HSL_RW
+
+#define PORT_DESC_EN
+#define PORT_HOL_CTL1_PORT_DESC_EN_BOFFSET 7
+#define PORT_HOL_CTL1_PORT_DESC_EN_BLEN 1
+#define PORT_HOL_CTL1_PORT_DESC_EN_FLAG HSL_RW
+
+#define QUEUE_DESC_EN
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BOFFSET 6
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_BLEN 1
+#define PORT_HOL_CTL1_QUEUE_DESC_EN_FLAG HSL_RW
+
+#define PORT_IN_DESC_EN
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BOFFSET 0
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_BLEN 4
+#define PORT_HOL_CTL1_PORT_IN_DESC_EN_FLAG HSL_RW
+
+ /* FX100 CTRL Register */
+#define FX100_CTRL
+#define FX100_CTRL_OFFSET 0x00fc
+#define FX100_CTRL_E_LENGTH 4
+#define FX100_CTRL_E_OFFSET 0X0004
+#define FX100_CTRL_NR_E 1
+
+#define FX100_STATUS
+#define FX100_CTRL_FX100_STATUS_BOFFSET 24
+#define FX100_CTRL_FX100_STATUS_BLEN 8
+#define FX100_CTRL_FX100_STATUS_FLAG HSL_RO
+
+#define FX100_LOOP_EN
+#define FX100_CTRL_FX100_LOOP_EN_BOFFSET 23
+#define FX100_CTRL_FX100_LOOP_EN_BLEN 1
+#define FX100_CTRL_FX100_LOOP_EN_FLAG HSL_Rw
+
+#define SGMII_FIBER
+#define FX100_CTRL_SGMII_FIBER_BOFFSET 15
+#define FX100_CTRL_SGMII_FIBER_BLEN 2
+#define FX100_CTRL_SGMII_FIBER_FLAG HSL_Rw
+
+#define CRS_COL_100_CTRL
+#define FX100_CTRL_CRS_COL_100_CTRL_BOFFSET 14
+#define FX100_CTRL_CRS_COL_100_CTRL_BLEN 1
+#define FX100_CTRL_CRS_COL_100_CTRL_FLAG HSL_Rw
+
+#define LOOPBACK_TEST
+#define FX100_CTRL_LOOPBACK_TEST_BOFFSET 13
+#define FX100_CTRL_LOOPBACK_TEST_BLEN 1
+#define FX100_CTRL_LOOPBACK_TEST_FLAG HSL_Rw
+
+#define CRS_CTRL
+#define FX100_CTRL_CRS_CTRL_BOFFSET 12
+#define FX100_CTRL_CRS_CTRL_BLEN 1
+#define FX100_CTRL_CRS_CTRL_FLAG HSL_Rw
+
+#define COL_TEST
+#define FX100_CTRL_COL_TEST_BOFFSET 11
+#define FX100_CTRL_COL_TEST_BLEN 1
+#define FX100_CTRL_COL_TEST_FLAG HSL_Rw
+
+#define FD_MODE
+#define FX100_CTRL_FD_MODE_BOFFSET 10
+#define FX100_CTRL_FD_MODE_BLEN 1
+#define FX100_CTRL_FD_MODE_FLAG HSL_Rw
+
+#define LINK_CTRL
+#define FX100_CTRL_LINK_CTRL_BOFFSET 8
+#define FX100_CTRL_LINK_CTRL_BLEN 2
+#define FX100_CTRL_LINK_CTRL_FLAG HSL_Rw
+
+#define OVERSHOOT_MODE
+#define FX100_CTRL_OVERSHOOT_MODE_BOFFSET 6
+#define FX100_CTRL_OVERSHOOT_MODE_BLEN 1
+#define FX100_CTRL_OVERSHOOT_MODE_FLAG HSL_Rw
+
+#define LOOPBACK_MODE
+#define FX100_CTRL_LOOPBACK_MODE_BOFFSET 3
+#define FX100_CTRL_LOOPBACK_MODE_BLEN 1
+#define FX100_CTRL_LOOPBACK_MODE_FLAG HSL_Rw
+
+
+
+ /* Port Rate Limit0 Register */
+#define RATE_LIMIT0 "rlmt0"
+#define RATE_LIMIT0_ID 32
+#define RATE_LIMIT0_OFFSET 0x0110
+#define RATE_LIMIT0_E_LENGTH 4
+#define RATE_LIMIT0_E_OFFSET 0x0100
+#define RATE_LIMIT0_NR_E 7
+
+
+#define EG_RATE_EN "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW
+
+#define EG_MNG_RATE_EN "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MNG_RATE_EN "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MUL_RATE_EN "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET 0
+#define RATE_LIMIT0_ING_RATE_BLEN 15
+#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW
+
+
+
+ /* PKT edit control register */
+#define PKT_CTRL
+#define PKT_CTRL_OFFSET 0x0c00
+#define PKT_CTRL_E_LENGTH 4
+#define PKT_CTRL_E_OFFSET 0
+#define PKT_CTRL_NR_E 7
+
+#define CPU_VID_EN
+#define PKT_CTRL_CPU_VID_EN_BOFFSET 1
+#define PKT_CTRL_CPU_VID_EN_BLEN 1
+#define PKT_CTRL_CPU_VID_EN_FLAG HSL_RW
+
+
+#define RTD_PPPOE_EN
+#define PKT_CTRL_RTD_PPPOE_EN_BOFFSET 0
+#define PKT_CTRL_RTD_PPPOE_EN_BLEN 1
+#define PKT_CTRL_RTD_PPPOE_EN_FLAG HSL_RW
+
+
+
+
+ /* mib memory info */
+#define MIB_RXBROAD
+#define MIB_RXBROAD_OFFSET 0x01000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0x100
+#define MIB_RXBROAD_NR_E 7
+
+#define MIB_RXPAUSE
+#define MIB_RXPAUSE_OFFSET 0x01004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0x100
+#define MIB_RXPAUSE_NR_E 7
+
+#define MIB_RXMULTI
+#define MIB_RXMULTI_OFFSET 0x01008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0x100
+#define MIB_RXMULTI_NR_E 7
+
+#define MIB_RXFCSERR
+#define MIB_RXFCSERR_OFFSET 0x0100c
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0x100
+#define MIB_RXFCSERR_NR_E 7
+
+#define MIB_RXALLIGNERR
+#define MIB_RXALLIGNERR_OFFSET 0x01010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0x100
+#define MIB_RXALLIGNERR_NR_E 7
+
+#define MIB_RXRUNT
+#define MIB_RXRUNT_OFFSET 0x01014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0x100
+#define MIB_RXRUNT_NR_E 7
+
+#define MIB_RXFRAGMENT
+#define MIB_RXFRAGMENT_OFFSET 0x01018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0x100
+#define MIB_RXFRAGMENT_NR_E 7
+
+#define MIB_RX64BYTE
+#define MIB_RX64BYTE_OFFSET 0x0101c
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0x100
+#define MIB_RX64BYTE_NR_E 7
+
+#define MIB_RX128BYTE
+#define MIB_RX128BYTE_OFFSET 0x01020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0x100
+#define MIB_RX128BYTE_NR_E 7
+
+#define MIB_RX256BYTE
+#define MIB_RX256BYTE_OFFSET 0x01024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0x100
+#define MIB_RX256BYTE_NR_E 7
+
+#define MIB_RX512BYTE
+#define MIB_RX512BYTE_OFFSET 0x01028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0x100
+#define MIB_RX512BYTE_NR_E 7
+
+#define MIB_RX1024BYTE
+#define MIB_RX1024BYTE_OFFSET 0x0102c
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0x100
+#define MIB_RX1024BYTE_NR_E 7
+
+#define MIB_RX1518BYTE
+#define MIB_RX1518BYTE_OFFSET 0x01030
+#define MIB_RX1518BYTE_E_LENGTH 4
+#define MIB_RX1518BYTE_E_OFFSET 0x100
+#define MIB_RX1518BYTE_NR_E 7
+
+#define MIB_RXMAXBYTE
+#define MIB_RXMAXBYTE_OFFSET 0x01034
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0x100
+#define MIB_RXMAXBYTE_NR_E 7
+
+#define MIB_RXTOOLONG
+#define MIB_RXTOOLONG_OFFSET 0x01038
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0x100
+#define MIB_RXTOOLONG_NR_E 7
+
+#define MIB_RXGOODBYTE_LO
+#define MIB_RXGOODBYTE_LO_OFFSET 0x0103c
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_LO_NR_E 7
+
+#define MIB_RXGOODBYTE_HI
+#define MIB_RXGOODBYTE_HI_OFFSET 0x01040
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_HI_NR_E 7
+
+#define MIB_RXBADBYTE_LO
+#define MIB_RXBADBYTE_LO_OFFSET 0x01044
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0x100
+#define MIB_RXBADBYTE_LO_NR_E 7
+
+#define MIB_RXBADBYTE_HI
+#define MIB_RXBADBYTE_HI_OFFSET 0x01048
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0x100
+#define MIB_RXBADBYTE_HI_NR_E 7
+
+#define MIB_RXOVERFLOW
+#define MIB_RXOVERFLOW_OFFSET 0x0104c
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0x100
+#define MIB_RXOVERFLOW_NR_E 7
+
+#define MIB_FILTERED
+#define MIB_FILTERED_OFFSET 0x01050
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0x100
+#define MIB_FILTERED_NR_E 7
+
+#define MIB_TXBROAD
+#define MIB_TXBROAD_OFFSET 0x01054
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0x100
+#define MIB_TXBROAD_NR_E 7
+
+#define MIB_TXPAUSE
+#define MIB_TXPAUSE_OFFSET 0x01058
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0x100
+#define MIB_TXPAUSE_NR_E 7
+
+#define MIB_TXMULTI
+#define MIB_TXMULTI_OFFSET 0x0105c
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0x100
+#define MIB_TXMULTI_NR_E 7
+
+#define MIB_TXUNDERRUN
+#define MIB_TXUNDERRUN_OFFSET 0x01060
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0x100
+#define MIB_TXUNDERRUN_NR_E 7
+
+#define MIB_TX64BYTE
+#define MIB_TX64BYTE_OFFSET 0x01064
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0x100
+#define MIB_TX64BYTE_NR_E 7
+
+#define MIB_TX128BYTE
+#define MIB_TX128BYTE_OFFSET 0x01068
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0x100
+#define MIB_TX128BYTE_NR_E 7
+
+#define MIB_TX256BYTE
+#define MIB_TX256BYTE_OFFSET 0x0106c
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0x100
+#define MIB_TX256BYTE_NR_E 7
+
+#define MIB_TX512BYTE
+#define MIB_TX512BYTE_OFFSET 0x01070
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0x100
+#define MIB_TX512BYTE_NR_E 7
+
+#define MIB_TX1024BYTE
+#define MIB_TX1024BYTE_OFFSET 0x01074
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0x100
+#define MIB_TX1024BYTE_NR_E 7
+
+#define MIB_TX1518BYTE
+#define MIB_TX1518BYTE_OFFSET 0x01078
+#define MIB_TX1518BYTE_E_LENGTH 4
+#define MIB_TX1518BYTE_E_OFFSET 0x100
+#define MIB_TX1518BYTE_NR_E 7
+
+#define MIB_TXMAXBYTE
+#define MIB_TXMAXBYTE_OFFSET 0x0107c
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0x100
+#define MIB_TXMAXBYTE_NR_E 7
+
+#define MIB_TXOVERSIZE
+#define MIB_TXOVERSIZE_OFFSET 0x01080
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0x100
+#define MIB_TXOVERSIZE_NR_E 7
+
+#define MIB_TXBYTE_LO
+#define MIB_TXBYTE_LO_OFFSET 0x01084
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0x100
+#define MIB_TXBYTE_LO_NR_E 7
+
+#define MIB_TXBYTE_HI
+#define MIB_TXBYTE_HI_OFFSET 0x01088
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0x100
+#define MIB_TXBYTE_HI_NR_E 7
+
+#define MIB_TXCOLLISION
+#define MIB_TXCOLLISION_OFFSET 0x0108c
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0x100
+#define MIB_TXCOLLISION_NR_E 7
+
+#define MIB_TXABORTCOL
+#define MIB_TXABORTCOL_OFFSET 0x01090
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0x100
+#define MIB_TXABORTCOL_NR_E 7
+
+#define MIB_TXMULTICOL
+#define MIB_TXMULTICOL_OFFSET 0x01094
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0x100
+#define MIB_TXMULTICOL_NR_E 7
+
+#define MIB_TXSINGALCOL
+#define MIB_TXSINGALCOL_OFFSET 0x01098
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0x100
+#define MIB_TXSINGALCOL_NR_E 7
+
+#define MIB_TXEXCDEFER
+#define MIB_TXEXCDEFER_OFFSET 0x0109c
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0x100
+#define MIB_TXEXCDEFER_NR_E 7
+
+#define MIB_TXDEFER
+#define MIB_TXDEFER_OFFSET 0x010a0
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0x100
+#define MIB_TXDEFER_NR_E 7
+
+#define MIB_TXLATECOL
+#define MIB_TXLATECOL_OFFSET 0x010a4
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0x100
+#define MIB_TXLATECOL_NR_E 7
+
+#define MIB_RXUNICAST
+#define MIB_RXUNICAST_OFFSET 0x010a8
+#define MIB_RXUNICAST_E_LENGTH 4
+#define MIB_RXUNICAST_E_OFFSET 0x100
+#define MIB_RXUNICAST_NR_E 7
+
+#define MIB_TXUNICAST
+#define MIB_TXUNICAST_OFFSET 0x010ac
+#define MIB_TXUNICAST_E_LENGTH 4
+#define MIB_TXUNICAST_E_OFFSET 0x100
+#define MIB_TXUNICAST_NR_E 7
+
+ /* ACL Action Register */
+#define ACL_RSLT0 10
+#define ACL_RSLT0_OFFSET 0x5a000
+#define ACL_RSLT0_E_LENGTH 4
+#define ACL_RSLT0_E_OFFSET 0x10
+#define ACL_RSLT0_NR_E 96
+
+#define CTAGPRI
+#define ACL_RSLT0_CTAGPRI_BOFFSET 29
+#define ACL_RSLT0_CTAGPRI_BLEN 3
+#define ACL_RSLT0_CTAGPRI_FLAG HSL_RW
+
+#define CTAGCFI
+#define ACL_RSLT0_CTAGCFI_BOFFSET 28
+#define ACL_RSLT0_CTAGCFI_BLEN 1
+#define ACL_RSLT0_CTAGCFI_FLAG HSL_RW
+
+#define CTAGVID
+#define ACL_RSLT0_CTAGVID_BOFFSET 16
+#define ACL_RSLT0_CTAGVID_BLEN 12
+#define ACL_RSLT0_CTAGVID_FLAG HSL_RW
+
+#define STAGPRI
+#define ACL_RSLT0_STAGPRI_BOFFSET 13
+#define ACL_RSLT0_STAGPRI_BLEN 3
+#define ACL_RSLT0_STAGPRI_FLAG HSL_RW
+
+#define STAGDEI
+#define ACL_RSLT0_STAGDEI_BOFFSET 12
+#define ACL_RSLT0_STAGDEI_BLEN 1
+#define ACL_RSLT0_STAGDEI_FLAG HSL_RW
+
+#define STAGVID
+#define ACL_RSLT0_STAGVID_BOFFSET 0
+#define ACL_RSLT0_STAGVID_BLEN 12
+#define ACL_RSLT0_STAGVID_FLAG HSL_RW
+
+
+#define ACL_RSLT1 11
+#define ACL_RSLT1_OFFSET 0x5a004
+#define ACL_RSLT1_E_LENGTH 4
+#define ACL_RSLT1_E_OFFSET 0x10
+#define ACL_RSLT1_NR_E 96
+
+#define DES_PORT0
+#define ACL_RSLT1_DES_PORT0_BOFFSET 29
+#define ACL_RSLT1_DES_PORT0_BLEN 3
+#define ACL_RSLT1_DES_PORT0_FLAG HSL_RW
+
+#define PRI_QU_EN
+#define ACL_RSLT1_PRI_QU_EN_BOFFSET 28
+#define ACL_RSLT1_PRI_QU_EN_BLEN 1
+#define ACL_RSLT1_PRI_QU_EN_FLAG HSL_RW
+
+#define PRI_QU
+#define ACL_RSLT1_PRI_QU_BOFFSET 25
+#define ACL_RSLT1_PRI_QU_BLEN 3
+#define ACL_RSLT1_PRI_QU_FLAG HSL_RW
+
+#define WCMP_EN
+#define ACL_RSLT1_WCMP_EN_BOFFSET 24
+#define ACL_RSLT1_WCMP_EN_BLEN 1
+#define ACL_RSLT1_WCMP_EN_FLAG HSL_RW
+
+#define ARP_PTR
+#define ACL_RSLT1_ARP_PTR_BOFFSET 17
+#define ACL_RSLT1_ARP_PTR_BLEN 7
+#define ACL_RSLT1_ARP_PTR_FLAG HSL_RW
+
+#define ARP_PTR_EN
+#define ACL_RSLT1_ARP_PTR_EN_BOFFSET 16
+#define ACL_RSLT1_ARP_PTR_EN_BLEN 1
+#define ACL_RSLT1_ARP_PTR_EN_FLAG HSL_RW
+
+#define FORCE_L3_MODE
+#define ACL_RSLT1_FORCE_L3_MODE_BOFFSET 14
+#define ACL_RSLT1_FORCE_L3_MODE_BLEN 2
+#define ACL_RSLT1_FORCE_L3_MODE_FLAG HSL_RW
+
+#define LOOK_VID_CHG
+#define ACL_RSLT1_LOOK_VID_CHG_BOFFSET 13
+#define ACL_RSLT1_LOOK_VID_CHG_BLEN 1
+#define ACL_RSLT1_LOOK_VID_CHG_FLAG HSL_RW
+
+#define TRANS_CVID_CHG
+#define ACL_RSLT1_TRANS_CVID_CHG_BOFFSET 12
+#define ACL_RSLT1_TRANS_CVID_CHG_BLEN 1
+#define ACL_RSLT1_TRANS_CVID_CHG_FLAG HSL_RW
+
+#define TRANS_SVID_CHG
+#define ACL_RSLT1_TRANS_SVID_CHG_BOFFSET 11
+#define ACL_RSLT1_TRANS_SVID_CHG_BLEN 1
+#define ACL_RSLT1_TRANS_SVID_CHG_FLAG HSL_RW
+
+#define CTAG_CFI_CHG
+#define ACL_RSLT1_CTAG_CFI_CHG_BOFFSET 10
+#define ACL_RSLT1_CTAG_CFI_CHG_BLEN 1
+#define ACL_RSLT1_CTAG_CFI_CHG_FLAG HSL_RW
+
+#define CTAG_PRI_REMAP
+#define ACL_RSLT1_CTAG_PRI_REMAP_BOFFSET 9
+#define ACL_RSLT1_CTAG_PRI_REMAP_BLEN 1
+#define ACL_RSLT1_CTAG_PRI_REMAP_FLAG HSL_RW
+
+#define STAG_DEI_CHG
+#define ACL_RSLT1_STAG_DEI_CHG_BOFFSET 8
+#define ACL_RSLT1_STAG_DEI_CHG_BLEN 1
+#define ACL_RSLT1_STAG_DEI_CHG_FLAG HSL_RW
+
+#define STAG_PRI_REMAP
+#define ACL_RSLT1_STAG_PRI_REMAP_BOFFSET 7
+#define ACL_RSLT1_STAG_PRI_REMAP_BLEN 1
+#define ACL_RSLT1_STAG_PRI_REMAP_FLAG HSL_RW
+
+#define DSCP_REMAP
+#define ACL_RSLT1_DSCP_REMAP_BOFFSET 6
+#define ACL_RSLT1_DSCP_REMAP_BLEN 1
+#define ACL_RSLT1_DSCP_REMAP_FLAG HSL_RW
+
+#define DSCPV
+#define ACL_RSLT1_DSCPV_BOFFSET 0
+#define ACL_RSLT1_DSCPV_BLEN 6
+#define ACL_RSLT1_DSCPV_FLAG HSL_RW
+
+#define ACL_RSLT2 12
+#define ACL_RSLT2_OFFSET 0x5a008
+#define ACL_RSLT2_E_LENGTH 4
+#define ACL_RSLT2_E_OFFSET 0x10
+#define ACL_RSLT2_NR_E 96
+
+#define TRIGGER_INTR
+#define ACL_RSLT2_TRIGGER_INTR_BOFFSET 16
+#define ACL_RSLT2_TRIGGER_INTR_BLEN 1
+#define ACL_RSLT2_TRIGGER_INTR_FLAG HSL_RW
+
+#define EG_BYPASS
+#define ACL_RSLT2_EG_BYPASS_BOFFSET 15
+#define ACL_RSLT2_EG_BYPASS_BLEN 1
+#define ACL_RSLT2_EG_BYPASS_FLAG HSL_RW
+
+#define POLICER_EN
+#define ACL_RSLT2_POLICER_EN_BOFFSET 14
+#define ACL_RSLT2_POLICER_EN_BLEN 1
+#define ACL_RSLT2_POLICER_EN_FLAG HSL_RW
+
+#define POLICER_PTR
+#define ACL_RSLT2_POLICER_PTR_BOFFSET 9
+#define ACL_RSLT2_POLICER_PTR_BLEN 5
+#define ACL_RSLT2_POLICER_PTR_FLAG HSL_RW
+
+#define FWD_CMD
+#define ACL_RSLT2_FWD_CMD_BOFFSET 6
+#define ACL_RSLT2_FWD_CMD_BLEN 3
+#define ACL_RSLT2_FWD_CMD_FLAG HSL_RW
+
+#define MIRR_EN
+#define ACL_RSLT2_MIRR_EN_BOFFSET 5
+#define ACL_RSLT2_MIRR_EN_BLEN 1
+#define ACL_RSLT2_MIRR_EN_FLAG HSL_RW
+
+#define DES_PORT_EN
+#define ACL_RSLT2_DES_PORT_EN_BOFFSET 4
+#define ACL_RSLT2_DES_PORT_EN_BLEN 1
+#define ACL_RSLT2_DES_PORT_EN_FLAG HSL_RW
+
+#define DES_PORT1
+#define ACL_RSLT2_DES_PORT1_BOFFSET 0
+#define ACL_RSLT2_DES_PORT1_BLEN 4
+#define ACL_RSLT2_DES_PORT1_FLAG HSL_RW
+
+
+
+
+ /* MAC Type Rule Field Define */
+#define MAC_RUL_V0 0
+#define MAC_RUL_V0_OFFSET 0x58000
+#define MAC_RUL_V0_E_LENGTH 4
+#define MAC_RUL_V0_E_OFFSET 0x20
+#define MAC_RUL_V0_NR_E 96
+
+#define DAV_BYTE2
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+#define MAC_RUL_V1 1
+#define MAC_RUL_V1_OFFSET 0x58004
+#define MAC_RUL_V1_E_LENGTH 4
+#define MAC_RUL_V1_E_OFFSET 0x20
+#define MAC_RUL_V1_NR_E 96
+
+#define SAV_BYTE4
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+#define MAC_RUL_V2 2
+#define MAC_RUL_V2_OFFSET 0x58008
+#define MAC_RUL_V2_E_LENGTH 4
+#define MAC_RUL_V2_E_OFFSET 0x20
+#define MAC_RUL_V2_NR_E 96
+
+#define SAV_BYTE0
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW
+
+#define SAV_BYTE1
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW
+
+#define SAV_BYTE2
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW
+
+#define SAV_BYTE3
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+#define MAC_RUL_V3 3
+#define MAC_RUL_V3_ID 13
+#define MAC_RUL_V3_OFFSET 0x5800c
+#define MAC_RUL_V3_E_LENGTH 4
+#define MAC_RUL_V3_E_OFFSET 0x20
+#define MAC_RUL_V3_NR_E 96
+
+#define ETHTYPV
+#define MAC_RUL_V3_ETHTYPV_BOFFSET 16
+#define MAC_RUL_V3_ETHTYPV_BLEN 16
+#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define VLANPRIV
+#define MAC_RUL_V3_VLANPRIV_BOFFSET 13
+#define MAC_RUL_V3_VLANPRIV_BLEN 3
+#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW
+
+#define VLANCFIV
+#define MAC_RUL_V3_VLANCFIV_BOFFSET 12
+#define MAC_RUL_V3_VLANCFIV_BLEN 1
+#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW
+
+#define VLANIDV
+#define MAC_RUL_V3_VLANIDV_BOFFSET 0
+#define MAC_RUL_V3_VLANIDV_BLEN 12
+#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW
+
+
+#define MAC_RUL_V4 4
+#define MAC_RUL_V4_OFFSET 0x58010
+#define MAC_RUL_V4_E_LENGTH 4
+#define MAC_RUL_V4_E_OFFSET 0x20
+#define MAC_RUL_V4_NR_E 96
+
+#define RULE_INV
+#define MAC_RUL_V4_RULE_INV_BOFFSET 7
+#define MAC_RUL_V4_RULE_INV_BLEN 1
+#define MAC_RUL_V4_RULE_INV_FLAG HSL_RW
+
+#define SRC_PT
+#define MAC_RUL_V4_SRC_PT_BOFFSET 0
+#define MAC_RUL_V4_SRC_PT_BLEN 7
+#define MAC_RUL_V4_SRC_PT_FLAG HSL_RW
+
+
+#define MAC_RUL_M0 5
+#define MAC_RUL_M0_OFFSET 0x59000
+#define MAC_RUL_M0_E_LENGTH 4
+#define MAC_RUL_M0_E_OFFSET 0x20
+#define MAC_RUL_M0_NR_E 96
+
+#define DAM_BYTE2
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+#define MAC_RUL_M1 6
+#define MAC_RUL_M1_OFFSET 0x59004
+#define MAC_RUL_M1_E_LENGTH 4
+#define MAC_RUL_M1_E_OFFSET 0x20
+#define MAC_RUL_M1_NR_E 96
+
+#define SAM_BYTE4
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+#define MAC_RUL_M2 7
+#define MAC_RUL_M2_OFFSET 0x59008
+#define MAC_RUL_M2_E_LENGTH 4
+#define MAC_RUL_M2_E_OFFSET 0x20
+#define MAC_RUL_M2_NR_E 96
+
+#define SAM_BYTE0
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW
+
+#define SAM_BYTE1
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW
+
+#define SAM_BYTE2
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW
+
+#define SAM_BYTE3
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+#define MAC_RUL_M3 8
+#define MAC_RUL_M3_OFFSET 0x5900c
+#define MAC_RUL_M3_E_LENGTH 4
+#define MAC_RUL_M3_E_OFFSET 0x20
+#define MAC_RUL_M3_NR_E 96
+
+#define ETHTYPM
+#define MAC_RUL_M3_ETHTYPM_BOFFSET 16
+#define MAC_RUL_M3_ETHTYPM_BLEN 16
+#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define VLANPRIM
+#define MAC_RUL_M3_VLANPRIM_BOFFSET 13
+#define MAC_RUL_M3_VLANPRIM_BLEN 3
+#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW
+
+#define VLANCFIM
+#define MAC_RUL_M3_VLANCFIM_BOFFSET 12
+#define MAC_RUL_M3_VLANCFIM_BLEN 1
+#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW
+
+#define VLANIDM
+#define MAC_RUL_M3_VLANIDM_BOFFSET 0
+#define MAC_RUL_M3_VLANIDM_BLEN 12
+#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW
+
+
+#define MAC_RUL_M4 9
+#define MAC_RUL_M4_OFFSET 0x59010
+#define MAC_RUL_M4_E_LENGTH 4
+#define MAC_RUL_M4_E_OFFSET 0x20
+#define MAC_RUL_M4_NR_E 96
+
+#define RULE_VALID
+#define MAC_RUL_M4_RULE_VALID_BOFFSET 6
+#define MAC_RUL_M4_RULE_VALID_BLEN 2
+#define MAC_RUL_M4_RULE_VALID_FLAG HSL_RW
+
+#define TAGGEDM
+#define MAC_RUL_M4_TAGGEDM_BOFFSET 5
+#define MAC_RUL_M4_TAGGEDM_BLEN 1
+#define MAC_RUL_M4_TAGGEDM_FLAG HSL_RW
+
+#define TAGGEDV
+#define MAC_RUL_M4_TAGGEDV_BOFFSET 4
+#define MAC_RUL_M4_TAGGEDV_BLEN 1
+#define MAC_RUL_M4_TAGGEDV_FLAG HSL_RW
+
+#define VIDMSK
+#define MAC_RUL_M4_VIDMSK_BOFFSET 3
+#define MAC_RUL_M4_VIDMSK_BLEN 1
+#define MAC_RUL_M4_VIDMSK_FLAG HSL_RW
+
+#define RULE_TYP
+#define MAC_RUL_M4_RULE_TYP_BOFFSET 0
+#define MAC_RUL_M4_RULE_TYP_BLEN 3
+#define MAC_RUL_M4_RULE_TYP_FLAG HSL_RW
+
+
+
+
+ /* IP4 Type Rule Field Define */
+#define IP4_RUL_V0 0
+#define IP4_RUL_V0_OFFSET 0x58000
+#define IP4_RUL_V0_E_LENGTH 4
+#define IP4_RUL_V0_E_OFFSET 0x20
+#define IP4_RUL_V0_NR_E 96
+
+#define DIPV
+#define IP4_RUL_V0_DIPV_BOFFSET 0
+#define IP4_RUL_V0_DIPV_BLEN 32
+#define IP4_RUL_V0_DIPV_FLAG HSL_RW
+
+
+#define IP4_RUL_V1 1
+#define IP4_RUL_V1_OFFSET 0x58004
+#define IP4_RUL_V1_E_LENGTH 4
+#define IP4_RUL_V1_E_OFFSET 0x20
+#define IP4_RUL_V1_NR_E 96
+
+#define SIPV
+#define IP4_RUL_V1_SIPV_BOFFSET 0
+#define IP4_RUL_V1_SIPV_BLEN 32
+#define IP4_RUL_V1_SIPV_FLAG HSL_RW
+
+
+#define IP4_RUL_V2 2
+#define IP4_RUL_V2_OFFSET 0x58008
+#define IP4_RUL_V2_E_LENGTH 4
+#define IP4_RUL_V2_E_OFFSET 0x20
+#define IP4_RUL_V2_NR_E 96
+
+#define IP4PROTV
+#define IP4_RUL_V2_IP4PROTV_BOFFSET 0
+#define IP4_RUL_V2_IP4PROTV_BLEN 8
+#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW
+
+#define IP4DSCPV
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8
+#define IP4_RUL_V2_IP4DSCPV_BLEN 8
+#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW
+
+#define IP4DPORTV
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16
+#define IP4_RUL_V2_IP4DPORTV_BLEN 16
+#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW
+
+
+#define IP4_RUL_V3 3
+#define IP4_RUL_V3_OFFSET 0x5800c
+#define IP4_RUL_V3_E_LENGTH 4
+#define IP4_RUL_V3_E_OFFSET 0x20
+#define IP4_RUL_V3_NR_E 96
+
+#define IP4TCPFLAGV
+#define IP4_RUL_V3_IP4TCPFLAGV_BOFFSET 24
+#define IP4_RUL_V3_IP4TCPFLAGV_BLEN 6
+#define IP4_RUL_V3_IP4TCPFLAGV_FLAG HSL_RW
+
+#define IP4DHCPV
+#define IP4_RUL_V3_IP4DHCPV_BOFFSET 22
+#define IP4_RUL_V3_IP4DHCPV_BLEN 1
+#define IP4_RUL_V3_IP4DHCPV_FLAG HSL_RW
+
+#define IP4RIPV
+#define IP4_RUL_V3_IP4RIPV_BOFFSET 21
+#define IP4_RUL_V3_IP4RIPV_BLEN 1
+#define IP4_RUL_V3_IP4RIPV_FLAG HSL_RW
+
+#define ICMP_EN
+#define IP4_RUL_V3_ICMP_EN_BOFFSET 20
+#define IP4_RUL_V3_ICMP_EN_BLEN 1
+#define IP4_RUL_V3_ICMP_EN_FLAG HSL_RW
+
+#define IP4SPORTV
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0
+#define IP4_RUL_V3_IP4SPORTV_BLEN 16
+#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW
+
+#define IP4ICMPTYPV
+#define IP4_RUL_V3_IP4ICMPTYPV_BOFFSET 8
+#define IP4_RUL_V3_IP4ICMPTYPV_BLEN 8
+#define IP4_RUL_V3_IP4ICMPTYPV_FLAG HSL_RW
+
+#define IP4ICMPCODEV
+#define IP4_RUL_V3_IP4ICMPCODEV_BOFFSET 0
+#define IP4_RUL_V3_IP4ICMPCODEV_BLEN 8
+#define IP4_RUL_V3_IP4ICMPCODEV_FLAG HSL_RW
+
+
+#define IP4_RUL_V4 4
+#define IP4_RUL_V4_OFFSET 0x58010
+#define IP4_RUL_V4_E_LENGTH 4
+#define IP4_RUL_V4_E_OFFSET 0x20
+#define IP4_RUL_V4_NR_E 96
+
+
+#define IP4_RUL_M0 5
+#define IP4_RUL_M0_OFFSET 0x59000
+#define IP4_RUL_M0_E_LENGTH 4
+#define IP4_RUL_M0_E_OFFSET 0x20
+#define IP4_RUL_M0_NR_E 96
+
+#define DIPM
+#define IP4_RUL_M0_DIPM_BOFFSET 0
+#define IP4_RUL_M0_DIPM_BLEN 32
+#define IP4_RUL_M0_DIPM_FLAG HSL_RW
+
+
+#define IP4_RUL_M1 6
+#define IP4_RUL_M1_OFFSET 0x59004
+#define IP4_RUL_M1_E_LENGTH 4
+#define IP4_RUL_M1_E_OFFSET 0x20
+#define IP4_RUL_M1_NR_E 96
+
+#define SIPM
+#define IP4_RUL_M1_SIPM_BOFFSET 0
+#define IP4_RUL_M1_SIPM_BLEN 32
+#define IP4_RUL_M1_SIPM_FLAG HSL_RW
+
+
+#define IP4_RUL_M2 7
+#define IP4_RUL_M2_OFFSET 0x59008
+#define IP4_RUL_M2_E_LENGTH 4
+#define IP4_RUL_M2_E_OFFSET 0x20
+#define IP4_RUL_M2_NR_E 96
+
+#define IP4PROTM
+#define IP4_RUL_M2_IP4PROTM_BOFFSET 0
+#define IP4_RUL_M2_IP4PROTM_BLEN 8
+#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW
+
+#define IP4DSCPM
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8
+#define IP4_RUL_M2_IP4DSCPM_BLEN 8
+#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW
+
+#define IP4DPORTM
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16
+#define IP4_RUL_M2_IP4DPORTM_BLEN 16
+#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW
+
+
+#define IP4_RUL_M3 8
+#define IP4_RUL_M3_OFFSET 0x5900c
+#define IP4_RUL_M3_E_LENGTH 4
+#define IP4_RUL_M3_E_OFFSET 0x20
+#define IP4_RUL_M3_NR_E 96
+
+#define IP4TCPFLAGM
+#define IP4_RUL_M3_IP4TCPFLAGM_BOFFSET 24
+#define IP4_RUL_M3_IP4TCPFLAGM_BLEN 6
+#define IP4_RUL_M3_IP4TCPFLAGM_FLAG HSL_RW
+
+#define IP4DHCPM
+#define IP4_RUL_M3_IP4DHCPM_BOFFSET 22
+#define IP4_RUL_M3_IP4DHCPM_BLEN 1
+#define IP4_RUL_M3_IP4DHCPM_FLAG HSL_RW
+
+#define IP4RIPM
+#define IP4_RUL_M3_IP4RIPM_BOFFSET 21
+#define IP4_RUL_M3_IP4RIPM_BLEN 1
+#define IP4_RUL_M3_IP4RIPM_FLAG HSL_RW
+
+#define IP4DPORTM_EN
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW
+
+#define IP4SPORTM_EN
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW
+
+#define IP4SPORTM
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0
+#define IP4_RUL_M3_IP4SPORTM_BLEN 16
+#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW
+
+#define IP4ICMPTYPM
+#define IP4_RUL_M3_IP4ICMPTYPM_BOFFSET 8
+#define IP4_RUL_M3_IP4ICMPTYPM_BLEN 8
+#define IP4_RUL_M3_IP4ICMPTYPM_FLAG HSL_RW
+
+#define IP4ICMPCODEM
+#define IP4_RUL_M3_IP4ICMPCODEM_BOFFSET 0
+#define IP4_RUL_M3_IP4ICMPCODEM_BLEN 8
+#define IP4_RUL_M3_IP4ICMPCODEM_FLAG HSL_RW
+
+
+#define IP4_RUL_M4 9
+#define IP4_RUL_M4_OFFSET 0x59010
+#define IP4_RUL_M4_E_LENGTH 4
+#define IP4_RUL_M4_E_OFFSET 0x20
+#define IP4_RUL_M4_NR_E 32
+
+
+
+
+ /* IP6 Type1 Rule Field Define */
+#define IP6_RUL1_V0 0
+#define IP6_RUL1_V0_OFFSET 0x58000
+#define IP6_RUL1_V0_E_LENGTH 4
+#define IP6_RUL1_V0_E_OFFSET 0x20
+#define IP6_RUL1_V0_NR_E 96
+
+#define IP6_DIPV0
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW
+
+
+#define IP6_RUL1_V1 1
+#define IP6_RUL1_V1_OFFSET 0x58004
+#define IP6_RUL1_V1_E_LENGTH 4
+#define IP6_RUL1_V1_E_OFFSET 0x20
+#define IP6_RUL1_V1_NR_E 96
+
+#define IP6_DIPV1
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW
+
+
+#define IP6_RUL1_V2 2
+#define IP6_RUL1_V2_OFFSET 0x58008
+#define IP6_RUL1_V2_E_LENGTH 4
+#define IP6_RUL1_V2_E_OFFSET 0x20
+#define IP6_RUL1_V2_NR_E 96
+
+#define IP6_DIPV2
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW
+
+
+#define IP6_RUL1_V3 3
+#define IP6_RUL1_V3_OFFSET 0x5800c
+#define IP6_RUL1_V3_E_LENGTH 4
+#define IP6_RUL1_V3_E_OFFSET 0x20
+#define IP6_RUL1_V3_NR_E 96
+
+#define IP6_DIPV3
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW
+
+
+#define IP6_RUL1_V4 4
+#define IP6_RUL1_V4_OFFSET 0x58010
+#define IP6_RUL1_V4_E_LENGTH 4
+#define IP6_RUL1_V4_E_OFFSET 0x20
+#define IP6_RUL1_V4_NR_E 96
+
+
+#define IP6_RUL1_M0 5
+#define IP6_RUL1_M0_OFFSET 0x59000
+#define IP6_RUL1_M0_E_LENGTH 4
+#define IP6_RUL1_M0_E_OFFSET 0x20
+#define IP6_RUL1_M0_NR_E 96
+
+#define IP6_DIPM0
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW
+
+
+#define IP6_RUL1_M1 6
+#define IP6_RUL1_M1_OFFSET 0x59004
+#define IP6_RUL1_M1_E_LENGTH 4
+#define IP6_RUL1_M1_E_OFFSET 0x20
+#define IP6_RUL1_M1_NR_E 96
+
+#define IP6_DIPM1
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+#define IP6_RUL1_M2 7
+#define IP6_RUL1_M2_OFFSET 0x59008
+#define IP6_RUL1_M2_E_LENGTH 4
+#define IP6_RUL1_M2_E_OFFSET 0x20
+#define IP6_RUL1_M2_NR_E 96
+
+#define IP6_DIPM2
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+#define IP6_RUL1_M3 8
+#define IP6_RUL1_M3_OFFSET 0x5900c
+#define IP6_RUL1_M3_E_LENGTH 4
+#define IP6_RUL1_M3_E_OFFSET 0x20
+#define IP6_RUL1_M3_NR_E 96
+
+#define IP6_DIPM3
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW
+
+
+#define IP6_RUL1_M4 9
+#define IP6_RUL1_M4_OFFSET 0x59010
+#define IP6_RUL1_M4_E_LENGTH 4
+#define IP6_RUL1_M4_E_OFFSET 0x20
+#define IP6_RUL1_M4_NR_E 96
+
+
+
+
+ /* IP6 Type2 Rule Field Define */
+#define IP6_RUL2_V0 0
+#define IP6_RUL2_V0_OFFSET 0x58000
+#define IP6_RUL2_V0_E_LENGTH 4
+#define IP6_RUL2_V0_E_OFFSET 0x20
+#define IP6_RUL2_V0_NR_E 96
+
+#define IP6_SIPV0
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW
+
+
+#define IP6_RUL2_V1 1
+#define IP6_RUL2_V1_OFFSET 0x58004
+#define IP6_RUL2_V1_E_LENGTH 4
+#define IP6_RUL2_V1_E_OFFSET 0x20
+#define IP6_RUL2_V1_NR_E 96
+
+#define IP6_SIPV1
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW
+
+
+#define IP6_RUL2_V2 2
+#define IP6_RUL2_V2_OFFSET 0x58008
+#define IP6_RUL2_V2_E_LENGTH 4
+#define IP6_RUL2_V2_E_OFFSET 0x20
+#define IP6_RUL2_V2_NR_E 96
+
+#define IP6_SIPV2
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW
+
+
+#define IP6_RUL2_V3 3
+#define IP6_RUL2_V3_OFFSET 0x5800c
+#define IP6_RUL2_V3_E_LENGTH 4
+#define IP6_RUL2_V3_E_OFFSET 0x20
+#define IP6_RUL2_V3_NR_E 96
+
+#define IP6_SIPV3
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW
+
+
+#define IP6_RUL2_V4 4
+#define IP6_RUL2_V4_OFFSET 0x58010
+#define IP6_RUL2_V4_E_LENGTH 4
+#define IP6_RUL2_V4_E_OFFSET 0x20
+#define IP6_RUL2_V4_NR_E 96
+
+
+#define IP6_RUL2_M0 5
+#define IP6_RUL2_M0_OFFSET 0x59000
+#define IP6_RUL2_M0_E_LENGTH 4
+#define IP6_RUL2_M0_E_OFFSET 0x20
+#define IP6_RUL2_M0_NR_E 96
+
+#define IP6_SIPM0
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW
+
+
+#define IP6_RUL2_M1 6
+#define IP6_RUL2_M1_OFFSET 0x59004
+#define IP6_RUL2_M1_E_LENGTH 4
+#define IP6_RUL2_M1_E_OFFSET 0x20
+#define IP6_RUL2_M1_NR_E 96
+
+#define IP6_SIPM1
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+#define IP6_RUL2_M2 7
+#define IP6_RUL2_M2_OFFSET 0x59008
+#define IP6_RUL2_M2_E_LENGTH 4
+#define IP6_RUL2_M2_E_OFFSET 0x20
+#define IP6_RUL2_M2_NR_E 96
+
+#define IP6_SIPM2
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+#define IP6_RUL2_M3 8
+#define IP6_RUL2_M3_OFFSET 0x5900c
+#define IP6_RUL2_M3_E_LENGTH 4
+#define IP6_RUL2_M3_E_OFFSET 0x20
+#define IP6_RUL2_M3_NR_E 96
+
+#define IP6_SIPM3
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW
+
+
+#define IP6_RUL2_M4 9
+#define IP6_RUL2_M4_OFFSET 0x59010
+#define IP6_RUL2_M4_E_LENGTH 4
+#define IP6_RUL2_M4_E_OFFSET 0x20
+#define IP6_RUL2_M4_NR_E 96
+
+
+
+
+ /* IP6 Type3 Rule Field Define */
+#define IP6_RUL3_V0 0
+#define IP6_RUL3_V0_OFFSET 0x58000
+#define IP6_RUL3_V0_E_LENGTH 4
+#define IP6_RUL3_V0_E_OFFSET 0x20
+#define IP6_RUL3_V0_NR_E 96
+
+#define IP6PROTV
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0
+#define IP6_RUL3_V0_IP6PROTV_BLEN 8
+#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW
+
+#define IP6DSCPV
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN 8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V1 1
+#define IP6_RUL3_V1_OFFSET 0x58004
+#define IP6_RUL3_V1_E_LENGTH 4
+#define IP6_RUL3_V1_E_OFFSET 0x20
+#define IP6_RUL3_V1_NR_E 96
+
+#define IP6LABEL1V
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW
+
+
+#define IP6_RUL3_V2 2
+#define IP6_RUL3_V2_OFFSET 0x58008
+#define IP6_RUL3_V2_E_LENGTH 4
+#define IP6_RUL3_V2_E_OFFSET 0x20
+#define IP6_RUL3_V2_NR_E 96
+
+#define IP6LABEL2V
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW
+
+#define IP6DPORTV
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN 16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V3 3
+#define IP6_RUL3_V3_OFFSET 0x5800c
+#define IP6_RUL3_V3_E_LENGTH 4
+#define IP6_RUL3_V3_E_OFFSET 0x20
+#define IP6_RUL3_V3_NR_E 96
+
+#define IP6TCPFLAGV
+#define IP6_RUL3_V3_IP6TCPFLAGV_BOFFSET 24
+#define IP6_RUL3_V3_IP6TCPFLAGV_BLEN 6
+#define IP6_RUL3_V3_IP6TCPFLAGV_FLAG HSL_RW
+
+#define IP6FWDTYPV
+#define IP6_RUL3_V3_IP6FWDTYPV_BOFFSET 23
+#define IP6_RUL3_V3_IP6FWDTYPV_BLEN 1
+#define IP6_RUL3_V3_IP6FWDTYPV_FLAG HSL_RW
+
+#define IP6DHCPV
+#define IP6_RUL3_V3_IP6DHCPV_BOFFSET 22
+#define IP6_RUL3_V3_IP6DHCPV_BLEN 1
+#define IP6_RUL3_V3_IP6DHCPV_FLAG HSL_RW
+
+#define ICMP6_EN
+#define IP6_RUL3_V3_ICMP6_EN_BOFFSET 20
+#define IP6_RUL3_V3_ICMP6_EN_BLEN 1
+#define IP6_RUL3_V3_ICMP6_EN_FLAG HSL_RW
+
+#define IP6SPORTV
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN 16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW
+
+#define IP6ICMPTYPV
+#define IP6_RUL3_V3_IP6ICMPTYPV_BOFFSET 8
+#define IP6_RUL3_V3_IP6ICMPTYPV_BLEN 8
+#define IP6_RUL3_V3_IP6ICMPTYPV_FLAG HSL_RW
+
+#define IP6ICMPCODEV
+#define IP6_RUL3_V3_IP6ICMPCODEV_BOFFSET 0
+#define IP6_RUL3_V3_IP6ICMPCODEV_BLEN 8
+#define IP6_RUL3_V3_IP6ICMPCODEV_FLAG HSL_RW
+
+
+#define IP6_RUL3_V4 4
+#define IP6_RUL3_V4_OFFSET 0x58010
+#define IP6_RUL3_V4_E_LENGTH 4
+#define IP6_RUL3_V4_E_OFFSET 0x20
+#define IP6_RUL3_V4_NR_E 96
+
+
+#define IP6_RUL3_M0 5
+#define IP6_RUL3_M0_OFFSET 0x59000
+#define IP6_RUL3_M0_E_LENGTH 4
+#define IP6_RUL3_M0_E_OFFSET 0x20
+#define IP6_RUL3_M0_NR_E 96
+
+#define IP6PROTM
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0
+#define IP6_RUL3_M0_IP6PROTM_BLEN 8
+#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW
+
+#define IP6DSCPM
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN 8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M1 6
+#define IP6_RUL3_M1_OFFSET 0x59004
+#define IP6_RUL3_M1_E_LENGTH 4
+#define IP6_RUL3_M1_E_OFFSET 0x20
+#define IP6_RUL3_M1_NR_E 96
+
+#define IP6LABEL1M
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW
+
+
+#define IP6_RUL3_M2 7
+#define IP6_RUL3_M2_OFFSET 0x59008
+#define IP6_RUL3_M2_E_LENGTH 4
+#define IP6_RUL3_M2_E_OFFSET 0x20
+#define IP6_RUL3_M2_NR_E 96
+
+#define IP6LABEL2M
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW
+
+#define IP6DPORTM
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN 16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M3 8
+#define IP6_RUL3_M3_OFFSET 0x5900c
+#define IP6_RUL3_M3_E_LENGTH 4
+#define IP6_RUL3_M3_E_OFFSET 0x20
+#define IP6_RUL3_M3_NR_E 96
+
+#define IP6TCPFLAGM
+#define IP6_RUL3_M3_IP6TCPFLAGM_BOFFSET 24
+#define IP6_RUL3_M3_IP6TCPFLAGM_BLEN 6
+#define IP6_RUL3_M3_IP6TCPFLAGM_FLAG HSL_RW
+
+#define IP6RWDTYPM
+#define IP6_RUL3_M3_IP6RWDTYPV_BOFFSET 23
+#define IP6_RUL3_M3_IP6RWDTYPV_BLEN 1
+#define IP6_RUL3_M3_IP6RWDTYPV_FLAG HSL_RW
+
+#define IP6DHCPM
+#define IP6_RUL3_M3_IP6DHCPM_BOFFSET 22
+#define IP6_RUL3_M3_IP6DHCPM_BLEN 1
+#define IP6_RUL3_M3_IP6DHCPM_FLAG HSL_RW
+
+#define IP6DPORTM_EN
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM_EN
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN 16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW
+
+#define IP6ICMPTYPM
+#define IP6_RUL3_M3_IP6ICMPTYPM_BOFFSET 8
+#define IP6_RUL3_M3_IP6ICMPTYPM_BLEN 8
+#define IP6_RUL3_M3_IP6ICMPTYPM_FLAG HSL_RW
+
+#define IP6ICMPCODEM
+#define IP6_RUL3_M3_IP6ICMPCODEM_BOFFSET 0
+#define IP6_RUL3_M3_IP6ICMPCODEM_BLEN 8
+#define IP6_RUL3_M3_IP6ICMPCODEM_FLAG HSL_RW
+
+
+#define IP6_RUL3_M4 9
+#define IP6_RUL3_M4_OFFSET 0x59010
+#define IP6_RUL3_M4_E_LENGTH 4
+#define IP6_RUL3_M4_E_OFFSET 0x20
+#define IP6_RUL3_M4_NR_E 96
+
+
+
+
+ /* Enhanced MAC Type Rule Field Define */
+#define EHMAC_RUL_V0 0
+#define EHMAC_RUL_V0_OFFSET 0x58000
+#define EHMAC_RUL_V0_E_LENGTH 4
+#define EHMAC_RUL_V0_E_OFFSET 0x20
+#define EHMAC_RUL_V0_NR_E 96
+
+#define DAV_BYTE2
+#define EHMAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define EHMAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3
+#define EHMAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define EHMAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4
+#define EHMAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define EHMAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5
+#define EHMAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define EHMAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define EHMAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V1 1
+#define EHMAC_RUL_V1_OFFSET 0x58004
+#define EHMAC_RUL_V1_E_LENGTH 4
+#define EHMAC_RUL_V1_E_OFFSET 0x20
+#define EHMAC_RUL_V1_NR_E 96
+
+#define SAV_BYTE4
+#define EHMAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define EHMAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define EHMAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5
+#define EHMAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define EHMAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define EHMAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0
+#define EHMAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define EHMAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define EHMAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1
+#define EHMAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define EHMAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define EHMAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V2 2
+#define EHMAC_RUL_V2_OFFSET 0x58008
+#define EHMAC_RUL_V2_E_LENGTH 4
+#define EHMAC_RUL_V2_E_OFFSET 0x20
+#define EHMAC_RUL_V2_NR_E 96
+
+#define CTAG_VIDLV
+#define EHMAC_RUL_V2_CTAG_VIDLV_BOFFSET 24
+#define EHMAC_RUL_V2_CTAG_VIDLV_BLEN 8
+#define EHMAC_RUL_V2_CTAG_VIDLV_FLAG HSL_RW
+
+#define STAG_PRIV
+#define EHMAC_RUL_V2_STAG_PRIV_BOFFSET 21
+#define EHMAC_RUL_V2_STAG_PRIV_BLEN 3
+#define EHMAC_RUL_V2_STAG_PRIV_FLAG HSL_RW
+
+#define STAG_DEIV
+#define EHMAC_RUL_V2_STAG_DEIV_BOFFSET 20
+#define EHMAC_RUL_V2_STAG_DEIV_BLEN 1
+#define EHMAC_RUL_V2_STAG_DEIV_FLAG HSL_RW
+
+#define STAG_VIDV
+#define EHMAC_RUL_V2_STAG_VIDV_BOFFSET 8
+#define EHMAC_RUL_V2_STAG_VIDV_BLEN 12
+#define EHMAC_RUL_V2_STAG_VIDV_FLAG HSL_RW
+
+#define SAV_BYTE3
+#define EHMAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define EHMAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define EHMAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V3 3
+#define EHMAC_RUL_V3_ID 13
+#define EHMAC_RUL_V3_OFFSET 0x5800c
+#define EHMAC_RUL_V3_E_LENGTH 4
+#define EHMAC_RUL_V3_E_OFFSET 0x20
+#define EHMAC_RUL_V3_NR_E 96
+
+#define STAGGEDM
+#define EHMAC_RUL_V3_STAGGEDM_BOFFSET 31
+#define EHMAC_RUL_V3_STAGGEDM_BLEN 1
+#define EHMAC_RUL_V3_STAGGEDM_FLAG HSL_RW
+
+#define STAGGEDV
+#define EHMAC_RUL_V3_STAGGEDV_BOFFSET 30
+#define EHMAC_RUL_V3_STAGGEDV_BLEN 1
+#define EHMAC_RUL_V3_STAGGEDV_FLAG HSL_RW
+
+#define DA_EN
+#define EHMAC_RUL_V3_DA_EN_BOFFSET 25
+#define EHMAC_RUL_V3_DA_EN_BLEN 1
+#define EHMAC_RUL_V3_DA_EN_FLAG HSL_RW
+
+#define SVIDMSK
+#define EHMAC_RUL_V3_SVIDMSK_BOFFSET 24
+#define EHMAC_RUL_V3_SVIDMSK_BLEN 1
+#define EHMAC_RUL_V3_SVIDMSK_FLAG HSL_RW
+
+#define ETHTYPV
+#define EHMAC_RUL_V3_ETHTYPV_BOFFSET 8
+#define EHMAC_RUL_V3_ETHTYPV_BLEN 16
+#define EHMAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define CTAG_PRIV
+#define EHMAC_RUL_V3_CTAG_PRIV_BOFFSET 5
+#define EHMAC_RUL_V3_CTAG_PRIV_BLEN 3
+#define EHMAC_RUL_V3_CTAG_PRIV_FLAG HSL_RW
+
+#define CTAG_CFIV
+#define EHMAC_RUL_V3_CTAG_CFIV_BOFFSET 4
+#define EHMAC_RUL_V3_CTAG_CFIV_BLEN 1
+#define EHMAC_RUL_V3_CTAG_CFIV_FLAG HSL_RW
+
+#define CTAG_VIDHV
+#define EHMAC_RUL_V3_CTAG_VIDHV_BOFFSET 0
+#define EHMAC_RUL_V3_CTAG_VIDHV_BLEN 4
+#define EHMAC_RUL_V3_CTAG_VIDHV_FLAG HSL_RW
+
+
+#define EHMAC_RUL_V4 4
+#define EHMAC_RUL_V4_OFFSET 0x58010
+#define EHMAC_RUL_V4_E_LENGTH 4
+#define EHMAC_RUL_V4_E_OFFSET 0x20
+#define EHMAC_RUL_V4_NR_E 96
+
+
+#define EHMAC_RUL_M0 5
+#define EHMAC_RUL_M0_OFFSET 0x59000
+#define EHMAC_RUL_M0_E_LENGTH 4
+#define EHMAC_RUL_M0_E_OFFSET 0x20
+#define EHMAC_RUL_M0_NR_E 96
+
+#define DAM_BYTE2
+#define EHMAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define EHMAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3
+#define EHMAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define EHMAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4
+#define EHMAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define EHMAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5
+#define EHMAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define EHMAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define EHMAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M1 6
+#define EHMAC_RUL_M1_OFFSET 0x59004
+#define EHMAC_RUL_M1_E_LENGTH 4
+#define EHMAC_RUL_M1_E_OFFSET 0x20
+#define EHMAC_RUL_M1_NR_E 96
+
+#define SAM_BYTE4
+#define EHMAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define EHMAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define EHMAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5
+#define EHMAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define EHMAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define EHMAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0
+#define EHMAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define EHMAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define EHMAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1
+#define EHMAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define EHMAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define EHMAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M2 7
+#define EHMAC_RUL_M2_OFFSET 0x59008
+#define EHMAC_RUL_M2_E_LENGTH 4
+#define EHMAC_RUL_M2_E_OFFSET 0x20
+#define EHMAC_RUL_M2_NR_E 96
+
+#define CTAG_VIDLM
+#define EHMAC_RUL_M2_CTAG_VIDLM_BOFFSET 24
+#define EHMAC_RUL_M2_CTAG_VIDLM_BLEN 8
+#define EHMAC_RUL_M2_CTAG_VIDLM_FLAG HSL_RW
+
+#define STAG_PRIM
+#define EHMAC_RUL_M2_STAG_PRIM_BOFFSET 21
+#define EHMAC_RUL_M2_STAG_PRIM_BLEN 3
+#define EHMAC_RUL_M2_STAG_PRIM_FLAG HSL_RW
+
+#define STAG_DEIM
+#define EHMAC_RUL_M2_STAG_DEIM_BOFFSET 20
+#define EHMAC_RUL_M2_STAG_DEIM_BLEN 1
+#define EHMAC_RUL_M2_STAG_DEIM_FLAG HSL_RW
+
+#define STAG_VIDM
+#define EHMAC_RUL_M2_STAG_VIDM_BOFFSET 8
+#define EHMAC_RUL_M2_STAG_VIDM_BLEN 12
+#define EHMAC_RUL_M2_STAG_VIDM_FLAG HSL_RW
+
+#define SAM_BYTE3
+#define EHMAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define EHMAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define EHMAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M3 8
+#define EHMAC_RUL_M3_OFFSET 0x5900c
+#define EHMAC_RUL_M3_E_LENGTH 4
+#define EHMAC_RUL_M3_E_OFFSET 0x20
+#define EHMAC_RUL_M3_NR_E 96
+
+#define ETHTYPM
+#define EHMAC_RUL_M3_ETHTYPM_BOFFSET 8
+#define EHMAC_RUL_M3_ETHTYPM_BLEN 16
+#define EHMAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define CTAG_PRIM
+#define EHMAC_RUL_M3_CTAG_PRIM_BOFFSET 5
+#define EHMAC_RUL_M3_CTAG_PRIM_BLEN 3
+#define EHMAC_RUL_M3_CTAG_PRIM_FLAG HSL_RW
+
+#define CTAG_CFIM
+#define EHMAC_RUL_M3_CTAG_CFIM_BOFFSET 4
+#define EHMAC_RUL_M3_CTAG_CFIM_BLEN 1
+#define EHMAC_RUL_M3_CTAG_CFIM_FLAG HSL_RW
+
+#define CTAG_VIDHM
+#define EHMAC_RUL_M3_CTAG_VIDHM_BOFFSET 0
+#define EHMAC_RUL_M3_CTAG_VIDHM_BLEN 4
+#define EHMAC_RUL_M3_CTAG_VIDHM_FLAG HSL_RW
+
+
+#define EHMAC_RUL_M4 9
+#define EHMAC_RUL_M4_OFFSET 0x59010
+#define EHMAC_RUL_M4_E_LENGTH 4
+#define EHMAC_RUL_M4_E_OFFSET 0x20
+#define EHMAC_RUL_M4_NR_E 96
+
+#define CTAGGEDM
+#define EHMAC_RUL_M4_CTAGGEDM_BOFFSET 5
+#define EHMAC_RUL_M4_CTAGGEDM_BLEN 1
+#define EHMAC_RUL_M4_CTAGGEDM_FLAG HSL_RW
+
+#define CTAGGEDV
+#define EHMAC_RUL_M4_CTAGGEDV_BOFFSET 4
+#define EHMAC_RUL_M4_CTAGGEDV_BLEN 1
+#define EHMAC_RUL_M4_CTAGGEDV_FLAG HSL_RW
+
+#define CVIDMSK
+#define EHMAC_RUL_M4_CVIDMSK_BOFFSET 3
+#define EHMAC_RUL_M4_CVIDMSK_BLEN 1
+#define EHMAC_RUL_M4_CVIDMSK_FLAG HSL_RW
+
+
+
+
+ /* PPPoE Session Table Define */
+#define PPPOE_SESSION
+#define PPPOE_SESSION_OFFSET 0x5f000
+#define PPPOE_SESSION_E_LENGTH 4
+#define PPPOE_SESSION_E_OFFSET 0x4
+#define PPPOE_SESSION_NR_E 16
+
+#define ENTRY_VALID
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 16
+#define PPPOE_SESSION_ENTRY_VALID_BLEN 2
+#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW
+
+#define SEESION_ID
+#define PPPOE_SESSION_SEESION_ID_BOFFSET 0
+#define PPPOE_SESSION_SEESION_ID_BLEN 16
+#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW
+
+
+#define PPPOE_EDIT
+#define PPPOE_EDIT_OFFSET 0x02200
+#define PPPOE_EDIT_E_LENGTH 4
+#define PPPOE_EDIT_E_OFFSET 0x10
+#define PPPOE_EDIT_NR_E 16
+
+#define EDIT_ID
+#define PPPOE_EDIT_EDIT_ID_BOFFSET 0
+#define PPPOE_EDIT_EDIT_ID_BLEN 16
+#define PPPOE_EDIT_EDIT_ID_FLAG HSL_RW
+
+
+
+
+ /* L3 Host Entry Define */
+#define HOST_ENTRY0
+#define HOST_ENTRY0_OFFSET 0x0e80
+#define HOST_ENTRY0_E_LENGTH 4
+#define HOST_ENTRY0_E_OFFSET 0x0
+#define HOST_ENTRY0_NR_E 1
+
+#define IP_ADDR
+#define HOST_ENTRY0_IP_ADDR_BOFFSET 0
+#define HOST_ENTRY0_IP_ADDR_BLEN 32
+#define HOST_ENTRY0_IP_ADDR_FLAG HSL_RW
+
+
+#define HOST_ENTRY1
+#define HOST_ENTRY1_OFFSET 0x0e84
+#define HOST_ENTRY1_E_LENGTH 4
+#define HOST_ENTRY1_E_OFFSET 0x0
+#define HOST_ENTRY1_NR_E 1
+
+
+#define HOST_ENTRY2
+#define HOST_ENTRY2_OFFSET 0x0e88
+#define HOST_ENTRY2_E_LENGTH 4
+#define HOST_ENTRY2_E_OFFSET 0x0
+#define HOST_ENTRY2_NR_E 1
+
+
+#define HOST_ENTRY3
+#define HOST_ENTRY3_OFFSET 0x0e8c
+#define HOST_ENTRY3_E_LENGTH 4
+#define HOST_ENTRY3_E_OFFSET 0x0
+#define HOST_ENTRY3_NR_E 1
+
+
+#define HOST_ENTRY4
+#define HOST_ENTRY4_OFFSET 0x0e90
+#define HOST_ENTRY4_E_LENGTH 4
+#define HOST_ENTRY4_E_OFFSET 0x0
+#define HOST_ENTRY4_NR_E 1
+
+#define MAC_ADDR2
+#define HOST_ENTRY4_MAC_ADDR2_BOFFSET 24
+#define HOST_ENTRY4_MAC_ADDR2_BLEN 8
+#define HOST_ENTRY4_MAC_ADDR2_FLAG HSL_RW
+
+#define MAC_ADDR3
+#define HOST_ENTRY4_MAC_ADDR3_BOFFSET 16
+#define HOST_ENTRY4_MAC_ADDR3_BLEN 8
+#define HOST_ENTRY4_MAC_ADDR3_FLAG HSL_RW
+
+#define MAC_ADDR4
+#define HOST_ENTRY4_MAC_ADDR4_BOFFSET 8
+#define HOST_ENTRY4_MAC_ADDR4_BLEN 8
+#define HOST_ENTRY4_MAC_ADDR4_FLAG HSL_RW
+
+#define MAC_ADDR5
+#define HOST_ENTRY4_MAC_ADDR5_BOFFSET 0
+#define HOST_ENTRY4_MAC_ADDR5_BLEN 8
+#define HOST_ENTRY4_MAC_ADDR5_FLAG HSL_RW
+
+#define HOST_ENTRY5
+#define HOST_ENTRY5_OFFSET 0x0e94
+#define HOST_ENTRY5_E_LENGTH 4
+#define HOST_ENTRY5_E_OFFSET 0x0
+#define HOST_ENTRY5_NR_E 1
+
+#define CPU_ADDR
+#define HOST_ENTRY5_CPU_ADDR_BOFFSET 31
+#define HOST_ENTRY5_CPU_ADDR_BLEN 1
+#define HOST_ENTRY5_CPU_ADDR_FLAG HSL_RW
+
+#define SRC_PORT
+#define HOST_ENTRY5_SRC_PORT_BOFFSET 28
+#define HOST_ENTRY5_SRC_PORT_BLEN 3
+#define HOST_ENTRY5_SRC_PORT_FLAG HSL_RW
+
+#define INTF_ID
+#define HOST_ENTRY5_INTF_ID_BOFFSET 16
+#define HOST_ENTRY5_INTF_ID_BLEN 12
+#define HOST_ENTRY5_INTF_ID_FLAG HSL_RW
+
+#define MAC_ADDR0
+#define HOST_ENTRY5_MAC_ADDR0_BOFFSET 8
+#define HOST_ENTRY5_MAC_ADDR0_BLEN 8
+#define HOST_ENTRY5_MAC_ADDR0_FLAG HSL_RW
+
+#define MAC_ADDR1
+#define HOST_ENTRY5_MAC_ADDR1_BOFFSET 0
+#define HOST_ENTRY5_MAC_ADDR1_BLEN 8
+#define HOST_ENTRY5_MAC_ADDR1_FLAG HSL_RW
+
+
+#define HOST_ENTRY6
+#define HOST_ENTRY6_OFFSET 0x0e98
+#define HOST_ENTRY6_E_LENGTH 4
+#define HOST_ENTRY6_E_OFFSET 0x0
+#define HOST_ENTRY6_NR_E 1
+
+#define IP_VER
+#define HOST_ENTRY6_IP_VER_BOFFSET 15
+#define HOST_ENTRY6_IP_VER_BLEN 1
+#define HOST_ENTRY6_IP_VER_FLAG HSL_RW
+
+#define AGE_FLAG
+#define HOST_ENTRY6_AGE_FLAG_BOFFSET 12
+#define HOST_ENTRY6_AGE_FLAG_BLEN 3
+#define HOST_ENTRY6_AGE_FLAG_FLAG HSL_RW
+
+#define PPPOE_EN
+#define HOST_ENTRY6_PPPOE_EN_BOFFSET 11
+#define HOST_ENTRY6_PPPOE_EN_BLEN 1
+#define HOST_ENTRY6_PPPOE_EN_FLAG HSL_RW
+
+#define PPPOE_IDX
+#define HOST_ENTRY6_PPPOE_IDX_BOFFSET 7
+#define HOST_ENTRY6_PPPOE_IDX_BLEN 4
+#define HOST_ENTRY6_PPPOE_IDX_FLAG HSL_RW
+
+#define CNT_EN
+#define HOST_ENTRY6_CNT_EN_BOFFSET 6
+#define HOST_ENTRY6_CNT_EN_BLEN 1
+#define HOST_ENTRY6_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define HOST_ENTRY6_CNT_IDX_BOFFSET 2
+#define HOST_ENTRY6_CNT_IDX_BLEN 4
+#define HOST_ENTRY6_CNT_IDX_FLAG HSL_RW
+
+#define ACTION
+#define HOST_ENTRY6_ACTION_BOFFSET 0
+#define HOST_ENTRY6_ACTION_BLEN 2
+#define HOST_ENTRY6_ACTION_FLAG HSL_RW
+
+
+#define HOST_ENTRY7
+#define HOST_ENTRY7_OFFSET 0x0e58
+#define HOST_ENTRY7_E_LENGTH 4
+#define HOST_ENTRY7_E_OFFSET 0x0
+#define HOST_ENTRY7_NR_E 1
+
+#define TBL_BUSY
+#define HOST_ENTRY7_TBL_BUSY_BOFFSET 31
+#define HOST_ENTRY7_TBL_BUSY_BLEN 1
+#define HOST_ENTRY7_TBL_BUSY_FLAG HSL_RW
+
+#define SPEC_SP
+#define HOST_ENTRY7_SPEC_SP_BOFFSET 22
+#define HOST_ENTRY7_SPEC_SP_BLEN 1
+#define HOST_ENTRY7_SPEC_SP_FLAG HSL_RW
+
+#define SPEC_VID
+#define HOST_ENTRY7_SPEC_VID_BOFFSET 21
+#define HOST_ENTRY7_SPEC_VID_BLEN 1
+#define HOST_ENTRY7_SPEC_VID_FLAG HSL_RW
+
+#define SPEC_PIP
+#define HOST_ENTRY7_SPEC_PIP_BOFFSET 20
+#define HOST_ENTRY7_SPEC_PIP_BLEN 1
+#define HOST_ENTRY7_SPEC_PIP_FLAG HSL_RW
+
+#define SPEC_SIP
+#define HOST_ENTRY7_SPEC_SIP_BOFFSET 19
+#define HOST_ENTRY7_SPEC_SIP_BLEN 1
+#define HOST_ENTRY7_SPEC_SIP_FLAG HSL_RW
+
+#define SPEC_STATUS
+#define HOST_ENTRY7_SPEC_STATUS_BOFFSET 18
+#define HOST_ENTRY7_SPEC_STATUS_BLEN 1
+#define HOST_ENTRY7_SPEC_STATUS_FLAG HSL_RW
+
+#define TBL_IDX
+#define HOST_ENTRY7_TBL_IDX_BOFFSET 8
+#define HOST_ENTRY7_TBL_IDX_BLEN 10
+#define HOST_ENTRY7_TBL_IDX_FLAG HSL_RW
+
+#define TBL_STAUS
+#define HOST_ENTRY7_TBL_STAUS_BOFFSET 7
+#define HOST_ENTRY7_TBL_STAUS_BLEN 1
+#define HOST_ENTRY7_TBL_STAUS_FLAG HSL_RW
+
+#define TBL_SEL
+#define HOST_ENTRY7_TBL_SEL_BOFFSET 4
+#define HOST_ENTRY7_TBL_SEL_BLEN 2
+#define HOST_ENTRY7_TBL_SEL_FLAG HSL_RW
+
+#define ENTRY_FUNC
+#define HOST_ENTRY7_ENTRY_FUNC_BOFFSET 0
+#define HOST_ENTRY7_ENTRY_FUNC_BLEN 3
+#define HOST_ENTRY7_ENTRY_FUNC_FLAG HSL_RW
+
+
+
+
+#define NAT_ENTRY0
+#define NAT_ENTRY0_OFFSET 0x0e80
+#define NAT_ENTRY0_E_LENGTH 4
+#define NAT_ENTRY0_E_OFFSET 0x0
+#define NAT_ENTRY0_NR_E 1
+
+#define IP_ADDR
+#define NAT_ENTRY0_IP_ADDR_BOFFSET 0
+#define NAT_ENTRY0_IP_ADDR_BLEN 32
+#define NAT_ENTRY0_IP_ADDR_FLAG HSL_RW
+
+
+#define NAT_ENTRY1
+#define NAT_ENTRY1_OFFSET 0x0e84
+#define NAT_ENTRY1_E_LENGTH 4
+#define NAT_ENTRY1_E_OFFSET 0x0
+#define NAT_ENTRY1_NR_E 1
+
+#define PRV_IPADDR0
+#define NAT_ENTRY1_PRV_IPADDR0_BOFFSET 24
+#define NAT_ENTRY1_PRV_IPADDR0_BLEN 8
+#define NAT_ENTRY1_PRV_IPADDR0_FLAG HSL_RW
+
+#define PORT_RANGE
+#define NAT_ENTRY1_PORT_RANGE_BOFFSET 16
+#define NAT_ENTRY1_PORT_RANGE_BLEN 8
+#define NAT_ENTRY1_PORT_RANGE_FLAG HSL_RW
+
+#define PORT_NUM
+#define NAT_ENTRY1_PORT_NUM_BOFFSET 0
+#define NAT_ENTRY1_PORT_NUM_BLEN 16
+#define NAT_ENTRY1_PORT_NUM_FLAG HSL_RW
+
+
+#define NAT_ENTRY2
+#define NAT_ENTRY2_OFFSET 0x0e88
+#define NAT_ENTRY2_E_LENGTH 4
+#define NAT_ENTRY2_E_OFFSET 0x0
+#define NAT_ENTRY2_NR_E 1
+
+#define HASH_KEY
+#define NAT_ENTRY2_HASH_KEY_BOFFSET 30
+#define NAT_ENTRY2_HASH_KEY_BLEN 2
+#define NAT_ENTRY2_HASH_KEY_FLAG HSL_RW
+
+#define ACTION
+#define NAT_ENTRY2_ACTION_BOFFSET 28
+#define NAT_ENTRY2_ACTION_BLEN 2
+#define NAT_ENTRY2_ACTION_FLAG HSL_RW
+
+#define CNT_EN
+#define NAT_ENTRY2_CNT_EN_BOFFSET 27
+#define NAT_ENTRY2_CNT_EN_BLEN 1
+#define NAT_ENTRY2_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define NAT_ENTRY2_CNT_IDX_BOFFSET 24
+#define NAT_ENTRY2_CNT_IDX_BLEN 3
+#define NAT_ENTRY2_CNT_IDX_FLAG HSL_RW
+
+#define PRV_IPADDR1
+#define NAT_ENTRY2_PRV_IPADDR1_BOFFSET 0
+#define NAT_ENTRY2_PRV_IPADDR1_BLEN 24
+#define NAT_ENTRY2_PRV_IPADDR1_FLAG HSL_RW
+
+
+#define NAT_ENTRY3
+#define NAT_ENTRY3_OFFSET 0x0e8c
+#define NAT_ENTRY3_E_LENGTH 4
+#define NAT_ENTRY3_E_OFFSET 0x0
+#define NAT_ENTRY3_NR_E 1
+
+#define ENTRY_VALID
+#define NAT_ENTRY3_ENTRY_VALID_BOFFSET 3
+#define NAT_ENTRY3_ENTRY_VALID_BLEN 1
+#define NAT_ENTRY3_ENTRY_VALID_FLAG HSL_RW
+
+#define PORT_EN
+#define NAT_ENTRY3_PORT_EN_BOFFSET 2
+#define NAT_ENTRY3_PORT_EN_BLEN 1
+#define NAT_ENTRY3_PORT_EN_FLAG HSL_RW
+
+#define PRO_TYP
+#define NAT_ENTRY3_PRO_TYP_BOFFSET 0
+#define NAT_ENTRY3_PRO_TYP_BLEN 2
+#define NAT_ENTRY3_PRO_TYP_FLAG HSL_RW
+
+
+#define NAPT_ENTRY0
+#define NAPT_ENTRY0_OFFSET 0x0e80
+#define NAPT_ENTRY0_E_LENGTH 4
+#define NAPT_ENTRY0_E_OFFSET 0x0
+#define NAPT_ENTRY0_NR_E 1
+
+#define DST_IPADDR
+#define NAPT_ENTRY0_DST_IPADDR_BOFFSET 0
+#define NAPT_ENTRY0_DST_IPADDR_BLEN 32
+#define NAPT_ENTRY0_DST_IPADDR_FLAG HSL_RW
+
+
+#define NAPT_ENTRY1
+#define NAPT_ENTRY1_OFFSET 0x0e84
+#define NAPT_ENTRY1_E_LENGTH 4
+#define NAPT_ENTRY1_E_OFFSET 0x0
+#define NAPT_ENTRY1_NR_E 1
+
+#define SRC_PORT
+#define NAPT_ENTRY1_SRC_PORT_BOFFSET 16
+#define NAPT_ENTRY1_SRC_PORT_BLEN 16
+#define NAPT_ENTRY1_SRC_PORT_FLAG HSL_RW
+
+#define DST_PORT
+#define NAPT_ENTRY1_DST_PORT_BOFFSET 0
+#define NAPT_ENTRY1_DST_PORT_BLEN 16
+#define NAPT_ENTRY1_DST_PORT_FLAG HSL_RW
+
+
+#define NAPT_ENTRY2
+#define NAPT_ENTRY2_OFFSET 0x0e88
+#define NAPT_ENTRY2_E_LENGTH 4
+#define NAPT_ENTRY2_E_OFFSET 0x0
+#define NAPT_ENTRY2_NR_E 1
+
+#define SRC_IPADDR0
+#define NAPT_ENTRY2_SRC_IPADDR0_BOFFSET 20
+#define NAPT_ENTRY2_SRC_IPADDR0_BLEN 12
+#define NAPT_ENTRY2_SRC_IPADDR0_FLAG HSL_RW
+
+#define TRANS_IPADDR
+#define NAPT_ENTRY2_TRANS_IPADDR_BOFFSET 16
+#define NAPT_ENTRY2_TRANS_IPADDR_BLEN 4
+#define NAPT_ENTRY2_TRANS_IPADDR_FLAG HSL_RW
+
+#define TRANS_PORT
+#define NAPT_ENTRY2_TRANS_PORT_BOFFSET 0
+#define NAPT_ENTRY2_TRANS_PORT_BLEN 16
+#define NAPT_ENTRY2_TRANS_PORT_FLAG HSL_RW
+
+
+#define NAPT_ENTRY3
+#define NAPT_ENTRY3_OFFSET 0x0e8c
+#define NAPT_ENTRY3_E_LENGTH 4
+#define NAPT_ENTRY3_E_OFFSET 0x0
+#define NAPT_ENTRY3_NR_E 1
+
+#define CNT_EN
+#define NAPT_ENTRY3_CNT_EN_BOFFSET 27
+#define NAPT_ENTRY3_CNT_EN_BLEN 1
+#define NAPT_ENTRY3_CNT_EN_FLAG HSL_RW
+
+#define CNT_IDX
+#define NAPT_ENTRY3_CNT_IDX_BOFFSET 24
+#define NAPT_ENTRY3_CNT_IDX_BLEN 3
+#define NAPT_ENTRY3_CNT_IDX_FLAG HSL_RW
+
+#define PROT_TYP
+#define NAPT_ENTRY3_PROT_TYP_BOFFSET 22
+#define NAPT_ENTRY3_PROT_TYP_BLEN 2
+#define NAPT_ENTRY3_PROT_TYP_FLAG HSL_RW
+
+#define ACTION
+#define NAPT_ENTRY3_ACTION_BOFFSET 20
+#define NAPT_ENTRY3_ACTION_BLEN 2
+#define NAPT_ENTRY3_ACTION_FLAG HSL_RW
+
+#define SRC_IPADDR1
+#define NAPT_ENTRY3_SRC_IPADDR1_BOFFSET 0
+#define NAPT_ENTRY3_SRC_IPADDR1_BLEN 20
+#define NAPT_ENTRY3_SRC_IPADDR1_FLAG HSL_RW
+
+
+#define NAPT_ENTRY4
+#define NAPT_ENTRY4_OFFSET 0x0e90
+#define NAPT_ENTRY4_E_LENGTH 4
+#define NAPT_ENTRY4_E_OFFSET 0x0
+#define NAPT_ENTRY4_NR_E 1
+
+#define AGE_FLAG
+#define NAPT_ENTRY4_AGE_FLAG_BOFFSET 0
+#define NAPT_ENTRY4_AGE_FLAG_BLEN 4
+#define NAPT_ENTRY4_AGE_FLAG_FLAG HSL_RW
+
+
+#define ROUTER_CTRL
+#define ROUTER_CTRL_OFFSET 0x0e00
+#define ROUTER_CTRL_E_LENGTH 4
+#define ROUTER_CTRL_E_OFFSET 0x0
+#define ROUTER_CTRL_NR_E 1
+
+#define ARP_LEARN_MODE
+#define ROUTER_CTRL_ARP_LEARN_MODE_BOFFSET 19
+#define ROUTER_CTRL_ARP_LEARN_MODE_BLEN 1
+#define ROUTER_CTRL_ARP_LEARN_MODE_FLAG HSL_RW
+
+#define GLB_LOCKTIME
+#define ROUTER_CTRL_GLB_LOCKTIME_BOFFSET 16
+#define ROUTER_CTRL_GLB_LOCKTIME_BLEN 2
+#define ROUTER_CTRL_GLB_LOCKTIME_FLAG HSL_RW
+
+#define ARP_AGE_TIME
+#define ROUTER_CTRL_ARP_AGE_TIME_BOFFSET 8
+#define ROUTER_CTRL_ARP_AGE_TIME_BLEN 8
+#define ROUTER_CTRL_ARP_AGE_TIME_FLAG HSL_RW
+
+#define WCMP_HAHS_DP
+#define ROUTER_CTRL_WCMP_HAHS_DP_BOFFSET 7
+#define ROUTER_CTRL_WCMP_HAHS_DP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_DP_FLAG HSL_RW
+
+#define WCMP_HAHS_DIP
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BOFFSET 6
+#define ROUTER_CTRL_WCMP_HAHS_DIP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_DIP_FLAG HSL_RW
+
+#define WCMP_HAHS_SP
+#define ROUTER_CTRL_WCMP_HAHS_SP_BOFFSET 5
+#define ROUTER_CTRL_WCMP_HAHS_SP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_SP_FLAG HSL_RW
+
+#define WCMP_HAHS_SIP
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BOFFSET 4
+#define ROUTER_CTRL_WCMP_HAHS_SIP_BLEN 1
+#define ROUTER_CTRL_WCMP_HAHS_SIP_FLAG HSL_RW
+
+#define ARP_AGE_MODE
+#define ROUTER_CTRL_ARP_AGE_MODE_BOFFSET 1
+#define ROUTER_CTRL_ARP_AGE_MODE_BLEN 1
+#define ROUTER_CTRL_ARP_AGE_MODE_FLAG HSL_RW
+
+#define ROUTER_EN
+#define ROUTER_CTRL_ROUTER_EN_BOFFSET 0
+#define ROUTER_CTRL_ROUTER_EN_BLEN 1
+#define ROUTER_CTRL_ROUTER_EN_FLAG HSL_RW
+
+
+
+
+#define ROUTER_PTCTRL0
+#define ROUTER_PTCTRL0_OFFSET 0x0e04
+#define ROUTER_PTCTRL0_E_LENGTH 4
+#define ROUTER_PTCTRL0_E_OFFSET 0x0
+#define ROUTER_PTCTRL0_NR_E 1
+
+
+
+
+#define ROUTER_PTCTRL1
+#define ROUTER_PTCTRL1_OFFSET 0x0e08
+#define ROUTER_PTCTRL1_E_LENGTH 4
+#define ROUTER_PTCTRL1_E_OFFSET 0x0
+#define ROUTER_PTCTRL1_NR_E 1
+
+
+
+#define ROUTER_PTCTRL2
+#define ROUTER_PTCTRL2_OFFSET 0x0e0c
+#define ROUTER_PTCTRL2_E_LENGTH 4
+#define ROUTER_PTCTRL2_E_OFFSET 0x0
+#define ROUTER_PTCTRL2_NR_E 1
+
+#define ARP_PT_UP
+#define ROUTER_PTCTRL2_ARP_PT_UP_BOFFSET 16
+#define ROUTER_PTCTRL2_ARP_PT_UP_BLEN 7
+#define ROUTER_PTCTRL2_ARP_PT_UP_FLAG HSL_RW
+
+#define ARP_LEARN_ACK
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BOFFSET 8
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_BLEN 7
+#define ROUTER_PTCTRL2_ARP_LEARN_ACK_FLAG HSL_RW
+
+#define ARP_LEARN_REQ
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BOFFSET 0
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_BLEN 7
+#define ROUTER_PTCTRL2_ARP_LEARN_REQ_FLAG HSL_RW
+
+
+
+
+#define NAT_CTRL
+#define NAT_CTRL_OFFSET 0x0e38
+#define NAT_CTRL_E_LENGTH 4
+#define NAT_CTRL_E_OFFSET 0x0
+#define NAT_CTRL_NR_E 1
+
+#define NAT_HASH_MODE
+#define NAT_CTRL_NAT_HASH_MODE_BOFFSET 5
+#define NAT_CTRL_NAT_HASH_MODE_BLEN 2
+#define NAT_CTRL_NAT_HASH_MODE_FLAG HSL_RW
+
+#define NAPT_OVERRIDE
+#define NAT_CTRL_NAPT_OVERRIDE_BOFFSET 4
+#define NAT_CTRL_NAPT_OVERRIDE_BLEN 1
+#define NAT_CTRL_NAPT_OVERRIDE_FLAG HSL_RW
+
+#define NAPT_MODE
+#define NAT_CTRL_NAPT_MODE_BOFFSET 2
+#define NAT_CTRL_NAPT_MODE_BLEN 2
+#define NAT_CTRL_NAPT_MODE_FLAG HSL_RW
+
+#define NAT_EN
+#define NAT_CTRL_NAT_EN_BOFFSET 1
+#define NAT_CTRL_NAT_EN_BLEN 1
+#define NAT_CTRL_NAT_EN_FLAG HSL_RW
+
+#define NAPT_EN
+#define NAT_CTRL_NAPT_EN_BOFFSET 0
+#define NAT_CTRL_NAPT_EN_BLEN 1
+#define NAT_CTRL_NAPT_EN_FLAG HSL_RW
+
+
+
+
+#define PRV_BASEADDR
+#define PRV_BASEADDR_OFFSET 0x0e5c
+#define PRV_BASEADDR_E_LENGTH 4
+#define PRV_BASEADDR_E_OFFSET 0x0
+#define PRV_BASEADDR_NR_E 1
+
+#define IP4_ADDR
+#define PRV_BASEADDR_IP4_ADDR_BOFFSET 0
+#define PRV_BASEADDR_IP4_ADDR_BLEN 20
+#define PRV_BASEADDR_IP4_ADDR_FLAG HSL_RW
+
+
+
+
+#define PRVIP_ADDR
+#define PRVIP_ADDR_OFFSET 0x0470
+#define PRVIP_ADDR_E_LENGTH 4
+#define PRVIP_ADDR_E_OFFSET 0x0
+#define PRVIP_ADDR_NR_E 1
+
+#define IP4_BASEADDR
+#define PRVIP_ADDR_IP4_BASEADDR_BOFFSET 0
+#define PRVIP_ADDR_IP4_BASEADDR_BLEN 32
+#define PRVIP_ADDR_IP4_BASEADDR_FLAG HSL_RW
+
+
+#define PRVIP_MASK
+#define PRVIP_MASK_OFFSET 0x0474
+#define PRVIP_MASK_E_LENGTH 4
+#define PRVIP_MASK_E_OFFSET 0x0
+#define PRVIP_MASK_NR_E 1
+
+#define IP4_BASEMASK
+#define PRVIP_MASK_IP4_BASEMASK_BOFFSET 0
+#define PRVIP_MASK_IP4_BASEMASK_BLEN 32
+#define PRVIP_MASK_IP4_BASEMASK_FLAG HSL_RW
+
+
+
+
+#define PUB_ADDR0
+#define PUB_ADDR0_OFFSET 0x5aa00
+#define PUB_ADDR0_E_LENGTH 4
+#define PUB_ADDR0_E_OFFSET 0x0
+#define PUB_ADDR0_NR_E 1
+
+#define IP4_ADDR
+#define PUB_ADDR0_IP4_ADDR_BOFFSET 0
+#define PUB_ADDR0_IP4_ADDR_BLEN 32
+#define PUB_ADDR0_IP4_ADDR_FLAG HSL_RW
+
+
+#define PUB_ADDR1
+#define PUB_ADDR1_OFFSET 0x5aa04
+#define PUB_ADDR1_E_LENGTH 4
+#define PUB_ADDR1_E_OFFSET 0x0
+#define PUB_ADDR1_NR_E 1
+
+#define ADDR_VALID
+#define PUB_ADDR1_ADDR_VALID_BOFFSET 0
+#define PUB_ADDR1_ADDR_VALID_BLEN 1
+#define PUB_ADDR1_ADDR_VALID_FLAG HSL_RW
+
+
+
+
+#define INTF_ADDR_ENTRY0
+#define INTF_ADDR_ENTRY0_OFFSET 0x5aa00
+#define INTF_ADDR_ENTRY0_E_LENGTH 4
+#define INTF_ADDR_ENTRY0_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY0_NR_E 8
+
+#define MAC_ADDR2
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BOFFSET 24
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR2_FLAG HSL_RW
+
+#define MAC_ADDR3
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BOFFSET 16
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR3_FLAG HSL_RW
+
+#define MAC_ADDR4
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BOFFSET 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR4_FLAG HSL_RW
+
+#define MAC_ADDR5
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BOFFSET 0
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_BLEN 8
+#define INTF_ADDR_ENTRY0_MAC_ADDR5_FLAG HSL_RW
+
+
+#define INTF_ADDR_ENTRY1
+#define INTF_ADDR_ENTRY1_OFFSET 0x5aa04
+#define INTF_ADDR_ENTRY1_E_LENGTH 4
+#define INTF_ADDR_ENTRY1_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY1_NR_E 8
+
+#define VID_HIGH0
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BOFFSET 28
+#define INTF_ADDR_ENTRY1_VID_HIGH0_BLEN 4
+#define INTF_ADDR_ENTRY1_VID_HIGH0_FLAG HSL_RW
+
+#define VID_LOW
+#define INTF_ADDR_ENTRY1_VID_LOW_BOFFSET 16
+#define INTF_ADDR_ENTRY1_VID_LOW_BLEN 12
+#define INTF_ADDR_ENTRY1_VID_LOW_FLAG HSL_RW
+
+#define MAC_ADDR0
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BOFFSET 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_BLEN 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR0_FLAG HSL_RW
+
+#define MAC_ADDR1
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BOFFSET 0
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_BLEN 8
+#define INTF_ADDR_ENTRY1_MAC_ADDR1_FLAG HSL_RW
+
+
+#define INTF_ADDR_ENTRY2
+#define INTF_ADDR_ENTRY2_OFFSET 0x5aa08
+#define INTF_ADDR_ENTRY2_E_LENGTH 4
+#define INTF_ADDR_ENTRY2_E_OFFSET 0x0
+#define INTF_ADDR_ENTRY2_NR_E 8
+
+#define IP6_ROUTE
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BOFFSET 9
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_BLEN 1
+#define INTF_ADDR_ENTRY2_IP6_ROUTE_FLAG HSL_RW
+
+#define IP4_ROUTE
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BOFFSET 8
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_BLEN 1
+#define INTF_ADDR_ENTRY2_IP4_ROUTE_FLAG HSL_RW
+
+#define VID_HIGH1
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BOFFSET 0
+#define INTF_ADDR_ENTRY2_VID_HIGH1_BLEN 8
+#define INTF_ADDR_ENTRY2_VID_HIGH1_FLAG HSL_RW
+
+
+
+
+ /* Port Shaper Register0 */
+#define EG_SHAPER0
+#define EG_SHAPER0_OFFSET 0x0890
+#define EG_SHAPER0_E_LENGTH 4
+#define EG_SHAPER0_E_OFFSET 0x0020
+#define EG_SHAPER0_NR_E 7
+
+#define EG_Q1_CIR
+#define EG_SHAPER0_EG_Q1_CIR_BOFFSET 16
+#define EG_SHAPER0_EG_Q1_CIR_BLEN 15
+#define EG_SHAPER0_EG_Q1_CIR_FLAG HSL_RW
+
+#define EG_Q0_CIR
+#define EG_SHAPER0_EG_Q0_CIR_BOFFSET 0
+#define EG_SHAPER0_EG_Q0_CIR_BLEN 15
+#define EG_SHAPER0_EG_Q0_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register1 */
+#define EG_SHAPER1
+#define EG_SHAPER1_OFFSET 0x0894
+#define EG_SHAPER1_E_LENGTH 4
+#define EG_SHAPER1_E_OFFSET 0x0020
+#define EG_SHAPER1_NR_E 7
+
+#define EG_Q3_CIR
+#define EG_SHAPER1_EG_Q3_CIR_BOFFSET 16
+#define EG_SHAPER1_EG_Q3_CIR_BLEN 15
+#define EG_SHAPER1_EG_Q3_CIR_FLAG HSL_RW
+
+#define EG_Q2_CIR
+#define EG_SHAPER1_EG_Q2_CIR_BOFFSET 0
+#define EG_SHAPER1_EG_Q2_CIR_BLEN 15
+#define EG_SHAPER1_EG_Q2_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register2 */
+#define EG_SHAPER2
+#define EG_SHAPER2_OFFSET 0x0898
+#define EG_SHAPER2_E_LENGTH 4
+#define EG_SHAPER2_E_OFFSET 0x0020
+#define EG_SHAPER2_NR_E 7
+
+#define EG_Q5_CIR
+#define EG_SHAPER2_EG_Q5_CIR_BOFFSET 16
+#define EG_SHAPER2_EG_Q5_CIR_BLEN 15
+#define EG_SHAPER2_EG_Q5_CIR_FLAG HSL_RW
+
+#define EG_Q4_CIR
+#define EG_SHAPER2_EG_Q4_CIR_BOFFSET 0
+#define EG_SHAPER2_EG_Q4_CIR_BLEN 15
+#define EG_SHAPER2_EG_Q4_CIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register3 */
+#define EG_SHAPER3
+#define EG_SHAPER3_OFFSET 0x089c
+#define EG_SHAPER3_E_LENGTH 4
+#define EG_SHAPER3_E_OFFSET 0x0020
+#define EG_SHAPER3_NR_E 7
+
+#define EG_Q1_EIR
+#define EG_SHAPER3_EG_Q1_EIR_BOFFSET 16
+#define EG_SHAPER3_EG_Q1_EIR_BLEN 15
+#define EG_SHAPER3_EG_Q1_EIR_FLAG HSL_RW
+
+#define EG_Q0_EIR
+#define EG_SHAPER3_EG_Q0_EIR_BOFFSET 0
+#define EG_SHAPER3_EG_Q0_EIR_BLEN 15
+#define EG_SHAPER3_EG_Q0_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register4 */
+#define EG_SHAPER4
+#define EG_SHAPER4_OFFSET 0x08a0
+#define EG_SHAPER4_E_LENGTH 4
+#define EG_SHAPER4_E_OFFSET 0x0020
+#define EG_SHAPER4_NR_E 7
+
+#define EG_Q3_EIR
+#define EG_SHAPER4_EG_Q3_EIR_BOFFSET 16
+#define EG_SHAPER4_EG_Q3_EIR_BLEN 15
+#define EG_SHAPER4_EG_Q3_EIR_FLAG HSL_RW
+
+#define EG_Q2_EIR
+#define EG_SHAPER4_EG_Q2_EIR_BOFFSET 0
+#define EG_SHAPER4_EG_Q2_EIR_BLEN 15
+#define EG_SHAPER4_EG_Q2_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register5 */
+#define EG_SHAPER5
+#define EG_SHAPER5_OFFSET 0x08a4
+#define EG_SHAPER5_E_LENGTH 4
+#define EG_SHAPER5_E_OFFSET 0x0020
+#define EG_SHAPER5_NR_E 7
+
+#define EG_Q5_EIR
+#define EG_SHAPER5_EG_Q5_EIR_BOFFSET 16
+#define EG_SHAPER5_EG_Q5_EIR_BLEN 15
+#define EG_SHAPER5_EG_Q5_EIR_FLAG HSL_RW
+
+#define EG_Q4_EIR
+#define EG_SHAPER5_EG_Q4_EIR_BOFFSET 0
+#define EG_SHAPER5_EG_Q4_EIR_BLEN 15
+#define EG_SHAPER5_EG_Q4_EIR_FLAG HSL_RW
+
+
+ /* Port Shaper Register6 */
+#define EG_SHAPER6
+#define EG_SHAPER6_OFFSET 0x08a8
+#define EG_SHAPER6_E_LENGTH 4
+#define EG_SHAPER6_E_OFFSET 0x0020
+#define EG_SHAPER6_NR_E 7
+
+#define EG_Q3_CBS
+#define EG_SHAPER6_EG_Q3_CBS_BOFFSET 28
+#define EG_SHAPER6_EG_Q3_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q3_CBS_FLAG HSL_RW
+
+#define EG_Q3_EBS
+#define EG_SHAPER6_EG_Q3_EBS_BOFFSET 24
+#define EG_SHAPER6_EG_Q3_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q3_EBS_FLAG HSL_RW
+
+#define EG_Q2_CBS
+#define EG_SHAPER6_EG_Q2_CBS_BOFFSET 20
+#define EG_SHAPER6_EG_Q2_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q2_CBS_FLAG HSL_RW
+
+#define EG_Q2_EBS
+#define EG_SHAPER6_EG_Q2_EBS_BOFFSET 16
+#define EG_SHAPER6_EG_Q2_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q2_EBS_FLAG HSL_RW
+
+#define EG_Q1_CBS
+#define EG_SHAPER6_EG_Q1_CBS_BOFFSET 12
+#define EG_SHAPER6_EG_Q1_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q1_CBS_FLAG HSL_RW
+
+#define EG_Q1_EBS
+#define EG_SHAPER6_EG_Q1_EBS_BOFFSET 8
+#define EG_SHAPER6_EG_Q1_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q1_EBS_FLAG HSL_RW
+
+#define EG_Q0_CBS
+#define EG_SHAPER6_EG_Q0_CBS_BOFFSET 4
+#define EG_SHAPER6_EG_Q0_CBS_BLEN 3
+#define EG_SHAPER6_EG_Q0_CBS_FLAG HSL_RW
+
+#define EG_Q0_EBS
+#define EG_SHAPER6_EG_Q0_EBS_BOFFSET 0
+#define EG_SHAPER6_EG_Q0_EBS_BLEN 3
+#define EG_SHAPER6_EG_Q0_EBS_FLAG HSL_RW
+
+
+ /* Port Shaper Register7 */
+#define EG_SHAPER7
+#define EG_SHAPER7_OFFSET 0x08ac
+#define EG_SHAPER7_E_LENGTH 4
+#define EG_SHAPER7_E_OFFSET 0x0020
+#define EG_SHAPER7_NR_E 7
+
+#define EG_Q5_CBS
+#define EG_SHAPER7_EG_Q5_CBS_BOFFSET 28
+#define EG_SHAPER7_EG_Q5_CBS_BLEN 3
+#define EG_SHAPER7_EG_Q5_CBS_FLAG HSL_RW
+
+#define EG_Q5_EBS
+#define EG_SHAPER7_EG_Q5_EBS_BOFFSET 24
+#define EG_SHAPER7_EG_Q5_EBS_BLEN 3
+#define EG_SHAPER7_EG_Q5_EBS_FLAG HSL_RW
+
+#define EG_Q4_CBS
+#define EG_SHAPER7_EG_Q4_CBS_BOFFSET 20
+#define EG_SHAPER7_EG_Q4_CBS_BLEN 3
+#define EG_SHAPER7_EG_Q4_CBS_FLAG HSL_RW
+
+#define EG_Q4_EBS
+#define EG_SHAPER7_EG_Q4_EBS_BOFFSET 16
+#define EG_SHAPER7_EG_Q4_EBS_BLEN 3
+#define EG_SHAPER7_EG_Q4_EBS_FLAG HSL_RW
+
+#define EG_Q5_UNIT
+#define EG_SHAPER7_EG_Q5_UNIT_BOFFSET 13
+#define EG_SHAPER7_EG_Q5_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q5_UNIT_FLAG HSL_RW
+
+#define EG_Q4_UNIT
+#define EG_SHAPER7_EG_Q4_UNIT_BOFFSET 12
+#define EG_SHAPER7_EG_Q4_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q4_UNIT_FLAG HSL_RW
+
+#define EG_Q3_UNIT
+#define EG_SHAPER7_EG_Q3_UNIT_BOFFSET 11
+#define EG_SHAPER7_EG_Q3_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q3_UNIT_FLAG HSL_RW
+
+#define EG_Q2_UNIT
+#define EG_SHAPER7_EG_Q2_UNIT_BOFFSET 10
+#define EG_SHAPER7_EG_Q2_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q2_UNIT_FLAG HSL_RW
+
+#define EG_Q1_UNIT
+#define EG_SHAPER7_EG_Q1_UNIT_BOFFSET 9
+#define EG_SHAPER7_EG_Q1_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q1_UNIT_FLAG HSL_RW
+
+#define EG_Q0_UNIT
+#define EG_SHAPER7_EG_Q0_UNIT_BOFFSET 8
+#define EG_SHAPER7_EG_Q0_UNIT_BLEN 1
+#define EG_SHAPER7_EG_Q0_UNIT_FLAG HSL_RW
+
+#define EG_PT
+#define EG_SHAPER7_EG_PT_BOFFSET 3
+#define EG_SHAPER7_EG_PT_BLEN 1
+#define EG_SHAPER7_EG_PT_FLAG HSL_RW
+
+#define EG_TS
+#define EG_SHAPER7_EG_TS_BOFFSET 0
+#define EG_SHAPER7_EG_TS_BLEN 3
+#define EG_SHAPER7_EG_TS_FLAG HSL_RW
+
+
+
+ /* ACL Policer Register0 */
+#define ACL_POLICER0
+#define ACL_POLICER0_OFFSET 0x0a00
+#define ACL_POLICER0_E_LENGTH 4
+#define ACL_POLICER0_E_OFFSET 0x0008
+#define ACL_POLICER0_NR_E 32
+
+#define ACL_CBS
+#define ACL_POLICER0_ACL_CBS_BOFFSET 15
+#define ACL_POLICER0_ACL_CBS_BLEN 3
+#define ACL_POLICER0_ACL_CBS_FLAG HSL_RW
+
+#define ACL_CIR
+#define ACL_POLICER0_ACL_CIR_BOFFSET 0
+#define ACL_POLICER0_ACL_CIR_BLEN 15
+#define ACL_POLICER0_ACL_CIR_FLAG HSL_RW
+
+
+ /* ACL Policer Register1 */
+#define ACL_POLICER1
+#define ACL_POLICER1_OFFSET 0x0a04
+#define ACL_POLICER1_E_LENGTH 4
+#define ACL_POLICER1_E_OFFSET 0x0008
+#define ACL_POLICER1_NR_E 32
+
+#define ACL_BORROW
+#define ACL_POLICER1_ACL_BORROW_BOFFSET 23
+#define ACL_POLICER1_ACL_BORROW_BLEN 1
+#define ACL_POLICER1_ACL_BORROW_FLAG HSL_RW
+
+#define ACL_UNIT
+#define ACL_POLICER1_ACL_UNIT_BOFFSET 22
+#define ACL_POLICER1_ACL_UNIT_BLEN 1
+#define ACL_POLICER1_ACL_UNIT_FLAG HSL_RW
+
+#define ACL_CF
+#define ACL_POLICER1_ACL_CF_BOFFSET 21
+#define ACL_POLICER1_ACL_CF_BLEN 1
+#define ACL_POLICER1_ACL_CF_FLAG HSL_RW
+
+#define ACL_CM
+#define ACL_POLICER1_ACL_CM_BOFFSET 20
+#define ACL_POLICER1_ACL_CM_BLEN 1
+#define ACL_POLICER1_ACL_CM_FLAG HSL_RW
+
+#define ACL_TS
+#define ACL_POLICER1_ACL_TS_BOFFSET 18
+#define ACL_POLICER1_ACL_TS_BLEN 2
+#define ACL_POLICER1_ACL_TS_FLAG HSL_RW
+
+#define ACL_EBS
+#define ACL_POLICER1_ACL_EBS_BOFFSET 15
+#define ACL_POLICER1_ACL_EBS_BLEN 3
+#define ACL_POLICER1_ACL_EBS_FLAG HSL_RW
+
+#define ACL_EIR
+#define ACL_POLICER1_ACL_EIR_BOFFSET 0
+#define ACL_POLICER1_ACL_EIR_BLEN 15
+#define ACL_POLICER1_ACL_EIR_FLAG HSL_RW
+
+
+ /* ACL Counter Register0 */
+#define ACL_COUNTER0
+#define ACL_COUNTER0_OFFSET 0x1c000
+#define ACL_COUNTER0_E_LENGTH 4
+#define ACL_COUNTER0_E_OFFSET 0x0008
+#define ACL_COUNTER0_NR_E 32
+
+ /* ACL Counter Register1 */
+#define ACL_COUNTER1
+#define ACL_COUNTER1_OFFSET 0x1c004
+#define ACL_COUNTER1_E_LENGTH 4
+#define ACL_COUNTER1_E_OFFSET 0x0008
+#define ACL_COUNTER1_NR_E 32
+
+
+
+
+ /* INGRESS Policer Register0 */
+#define INGRESS_POLICER0
+#define INGRESS_POLICER0_OFFSET 0x0b00
+#define INGRESS_POLICER0_E_LENGTH 4
+#define INGRESS_POLICER0_E_OFFSET 0x0010
+#define INGRESS_POLICER0_NR_E 7
+
+#define ADD_RATE_BYTE
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BOFFSET 24
+#define INGRESS_POLICER0_ADD_RATE_BYTE_BLEN 8
+#define INGRESS_POLICER0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define C_ING_TS
+#define INGRESS_POLICER0_C_ING_TS_BOFFSET 22
+#define INGRESS_POLICER0_C_ING_TS_BLEN 2
+#define INGRESS_POLICER0_C_ING_TS_FLAG HSL_RW
+
+#define RATE_MODE
+#define INGRESS_POLICER0_RATE_MODE_BOFFSET 20
+#define INGRESS_POLICER0_RATE_MODE_BLEN 1
+#define INGRESS_POLICER0_RATE_MODE_FLAG HSL_RW
+
+#define INGRESS_CBS
+#define INGRESS_POLICER0_INGRESS_CBS_BOFFSET 15
+#define INGRESS_POLICER0_INGRESS_CBS_BLEN 3
+#define INGRESS_POLICER0_INGRESS_CBS_FLAG HSL_RW
+
+#define INGRESS_CIR
+#define INGRESS_POLICER0_INGRESS_CIR_BOFFSET 0
+#define INGRESS_POLICER0_INGRESS_CIR_BLEN 15
+#define INGRESS_POLICER0_INGRESS_CIR_FLAG HSL_RW
+
+
+ /* INGRESS Policer Register1 */
+#define INGRESS_POLICER1
+#define INGRESS_POLICER1_OFFSET 0x0b04
+#define INGRESS_POLICER1_E_LENGTH 4
+#define INGRESS_POLICER1_E_OFFSET 0x0010
+#define INGRESS_POLICER1_NR_E 7
+
+#define INGRESS_BORROW
+#define INGRESS_POLICER1_INGRESS_BORROW_BOFFSET 23
+#define INGRESS_POLICER1_INGRESS_BORROW_BLEN 1
+#define INGRESS_POLICER1_INGRESS_BORROW_FLAG HSL_RW
+
+#define INGRESS_UNIT
+#define INGRESS_POLICER1_INGRESS_UNIT_BOFFSET 22
+#define INGRESS_POLICER1_INGRESS_UNIT_BLEN 1
+#define INGRESS_POLICER1_INGRESS_UNIT_FLAG HSL_RW
+
+#define INGRESS_CF
+#define INGRESS_POLICER1_INGRESS_CF_BOFFSET 21
+#define INGRESS_POLICER1_INGRESS_CF_BLEN 1
+#define INGRESS_POLICER1_INGRESS_CF_FLAG HSL_RW
+
+#define INGRESS_CM
+#define INGRESS_POLICER1_INGRESS_CM_BOFFSET 20
+#define INGRESS_POLICER1_INGRESS_CM_BLEN 1
+#define INGRESS_POLICER1_INGRESS_CM_FLAG HSL_RW
+
+#define E_ING_TS
+#define INGRESS_POLICER1_E_ING_TS_BOFFSET 18
+#define INGRESS_POLICER1_E_ING_TS_BLEN 2
+#define INGRESS_POLICER1_E_ING_TS_FLAG HSL_RW
+
+#define INGRESS_EBS
+#define INGRESS_POLICER1_INGRESS_EBS_BOFFSET 15
+#define INGRESS_POLICER1_INGRESS_EBS_BLEN 3
+#define INGRESS_POLICER1_INGRESS_EBS_FLAG HSL_RW
+
+#define INGRESS_EIR
+#define INGRESS_POLICER1_INGRESS_EIR_BOFFSET 0
+#define INGRESS_POLICER1_INGRESS_EIR_BLEN 15
+#define INGRESS_POLICER1_INGRESS_EIR_FLAG HSL_RW
+
+
+ /* INGRESS Policer Register2 */
+#define INGRESS_POLICER2
+#define INGRESS_POLICER2_OFFSET 0x0b08
+#define INGRESS_POLICER2_E_LENGTH 4
+#define INGRESS_POLICER2_E_OFFSET 0x0010
+#define INGRESS_POLICER2_NR_E 7
+
+#define C_MUL
+#define INGRESS_POLICER2_C_MUL_BOFFSET 15
+#define INGRESS_POLICER2_C_MUL_BLEN 1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW
+
+#define C_UNI
+#define INGRESS_POLICER2_C_UNI_BOFFSET 14
+#define INGRESS_POLICER2_C_UNI_BLEN 1
+#define INGRESS_POLICER2_C_UNI_FLAG HSL_RW
+
+#define C_UNK_MUL
+#define INGRESS_POLICER2_C_UNK_MUL_BOFFSET 13
+#define INGRESS_POLICER2_C_UNK_MUL_BLEN 1
+#define INGRESS_POLICER2_C_UNK_MUL_FLAG HSL_RW
+
+#define C_UNK_UNI
+#define INGRESS_POLICER2_C_UNK_UNI_BOFFSET 12
+#define INGRESS_POLICER2_C_UNK_UNI_BLEN 1
+#define INGRESS_POLICER2_C_UNK_UNI_FLAG HSL_RW
+
+#define C_BROAD
+#define INGRESS_POLICER2_C_BROAD_BOFFSET 11
+#define INGRESS_POLICER2_C_BROAD_BLEN 1
+#define INGRESS_POLICER2_C_BROAD_FLAG HSL_RW
+
+#define C_MANAGE
+#define INGRESS_POLICER2_C_MANAGC_BOFFSET 10
+#define INGRESS_POLICER2_C_MANAGC_BLEN 1
+#define INGRESS_POLICER2_C_MANAGC_FLAG HSL_RW
+
+#define C_TCP
+#define INGRESS_POLICER2_C_TCP_BOFFSET 9
+#define INGRESS_POLICER2_C_TCP_BLEN 1
+#define INGRESS_POLICER2_C_TCP_FLAG HSL_RW
+
+#define C_MIRR
+#define INGRESS_POLICER2_C_MIRR_BOFFSET 8
+#define INGRESS_POLICER2_C_MIRR_BLEN 1
+#define INGRESS_POLICER2_C_MIRR_FLAG HSL_RW
+
+#define E_MUL
+#define INGRESS_POLICER2_E_MUL_BOFFSET 7
+#define INGRESS_POLICER2_E_MUL_BLEN 1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW
+
+#define E_UNI
+#define INGRESS_POLICER2_E_UNI_BOFFSET 6
+#define INGRESS_POLICER2_E_UNI_BLEN 1
+#define INGRESS_POLICER2_E_UNI_FLAG HSL_RW
+
+#define E_UNK_MUL
+#define INGRESS_POLICER2_E_UNK_MUL_BOFFSET 5
+#define INGRESS_POLICER2_E_UNK_MUL_BLEN 1
+#define INGRESS_POLICER2_E_UNK_MUL_FLAG HSL_RW
+
+#define E_UNK_UNI
+#define INGRESS_POLICER2_E_UNK_UNI_BOFFSET 4
+#define INGRESS_POLICER2_E_UNK_UNI_BLEN 1
+#define INGRESS_POLICER2_E_UNK_UNI_FLAG HSL_RW
+
+#define E_BROAD
+#define INGRESS_POLICER2_E_BROAD_BOFFSET 3
+#define INGRESS_POLICER2_E_BROAD_BLEN 1
+#define INGRESS_POLICER2_E_BROAD_FLAG HSL_RW
+
+#define E_MANAGE
+#define INGRESS_POLICER2_E_MANAGE_BOFFSET 2
+#define INGRESS_POLICER2_E_MANAGE_BLEN 1
+#define INGRESS_POLICER2_E_MANAGE_FLAG HSL_RW
+
+#define E_TCP
+#define INGRESS_POLICER2_E_TCP_BOFFSET 1
+#define INGRESS_POLICER2_E_TCP_BLEN 1
+#define INGRESS_POLICER2_E_TCP_FLAG HSL_RW
+
+#define E_MIRR
+#define INGRESS_POLICER2_E_MIRR_BOFFSET 0
+#define INGRESS_POLICER2_E_MIRR_BLEN 1
+#define INGRESS_POLICER2_E_MIRR_FLAG HSL_RW
+
+
+
+
+ /* Port Rate Limit2 Register */
+#define WRR_CTRL
+#define WRR_CTRL_OFFSET 0x0830
+#define WRR_CTRL_E_LENGTH 4
+#define WRR_CTRL_E_OFFSET 0x0004
+#define WRR_CTRL_NR_E 7
+
+#define SCH_MODE
+#define WRR_CTRL_SCH_MODE_BOFFSET 30
+#define WRR_CTRL_SCH_MODE_BLEN 2
+#define WRR_CTRL_SCH_MODE_FLAG HSL_RW
+
+#define Q5_W
+#define WRR_CTRL_Q5_W_BOFFSET 25
+#define WRR_CTRL_Q5_W_BLEN 5
+#define WRR_CTRL_Q5_W_FLAG HSL_RW
+
+#define Q4_W
+#define WRR_CTRL_Q4_W_BOFFSET 20
+#define WRR_CTRL_Q4_W_BLEN 5
+#define WRR_CTRL_Q4_W_FLAG HSL_RW
+
+#define Q3_W
+#define WRR_CTRL_Q3_W_BOFFSET 15
+#define WRR_CTRL_Q3_W_BLEN 5
+#define WRR_CTRL_Q3_W_FLAG HSL_RW
+
+#define Q2_W
+#define WRR_CTRL_Q2_W_BOFFSET 10
+#define WRR_CTRL_Q2_W_BLEN 5
+#define WRR_CTRL_Q2_W_FLAG HSL_RW
+
+#define Q1_W
+#define WRR_CTRL_Q1_W_BOFFSET 5
+#define WRR_CTRL_Q1_W_BLEN 5
+#define WRR_CTRL_Q1_W_FLAG HSL_RW
+
+#define Q0_W
+#define WRR_CTRL_Q0_W_BOFFSET 0
+#define WRR_CTRL_Q0_W_BLEN 5
+#define WRR_CTRL_Q0_W_FLAG HSL_RW
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_REG_H_ */
+
diff --git a/include/hsl/isisc/isisc_reg_access.h b/include/hsl/isisc/isisc_reg_access.h
new file mode 100644
index 0000000..5f92d6f
--- /dev/null
+++ b/include/hsl/isisc/isisc_reg_access.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _ISISC_REG_ACCESS_H_
+#define _ISISC_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_REG_ACCESS_H_ */
+
diff --git a/include/hsl/isisc/isisc_sec.h b/include/hsl/isisc/isisc_sec.h
new file mode 100644
index 0000000..561a70f
--- /dev/null
+++ b/include/hsl/isisc/isisc_sec.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_SEC_H_
+#define _ISISC_SEC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_sec.h"
+
+ sw_error_t isisc_sec_init(a_uint32_t dev_id);
+
+#ifdef IN_SEC
+#define ISISC_SEC_INIT(rv, dev_id) \
+ { \
+ rv = isisc_sec_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_SEC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item,
+ void *value);
+
+ HSL_LOCAL sw_error_t
+ isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item,
+ void *value);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_SEC_H_ */
+
diff --git a/include/hsl/isisc/isisc_stp.h b/include/hsl/isisc/isisc_stp.h
new file mode 100644
index 0000000..3f03eb2
--- /dev/null
+++ b/include/hsl/isisc/isisc_stp.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_STP_H_
+#define _ISISC_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+ sw_error_t isisc_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define ISISC_STP_INIT(rv, dev_id) \
+ { \
+ rv = isisc_stp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_STP_H_ */
+
diff --git a/include/hsl/isisc/isisc_trunk.h b/include/hsl/isisc/isisc_trunk.h
new file mode 100644
index 0000000..cb63990
--- /dev/null
+++ b/include/hsl/isisc/isisc_trunk.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_TRUNK_H_
+#define _ISISC_TRUNK_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_trunk.h"
+
+ sw_error_t isisc_trunk_init(a_uint32_t dev_id);
+
+#ifdef IN_TRUNK
+#define ISISC_TRUNK_INIT(rv, dev_id) \
+ { \
+ rv = isisc_trunk_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_TRUNK_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr);
+
+ HSL_LOCAL sw_error_t
+ isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _ISISC_TRUNK_H_ */
+
diff --git a/include/hsl/isisc/isisc_vlan.h b/include/hsl/isisc/isisc_vlan.h
new file mode 100644
index 0000000..b111f16
--- /dev/null
+++ b/include/hsl/isisc/isisc_vlan.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _ISISC_VLAN_H_
+#define _ISISC_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ isisc_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define ISISC_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = isisc_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define ISISC_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_flush(a_uint32_t dev_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _ISISC_VLAN_H_ */
+
diff --git a/include/hsl/phy/f1_phy.h b/include/hsl/phy/f1_phy.h
new file mode 100644
index 0000000..9d1b1e0
--- /dev/null
+++ b/include/hsl/phy/f1_phy.h
@@ -0,0 +1,451 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _F1_PHY_H_
+#define _F1_PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ /* PHY Registers */
+#define F1_PHY_CONTROL 0
+#define F1_PHY_STATUS 1
+#define F1_PHY_ID1 2
+#define F1_PHY_ID2 3
+#define F1_AUTONEG_ADVERT 4
+#define F1_LINK_PARTNER_ABILITY 5
+#define F1_AUTONEG_EXPANSION 6
+#define F1_NEXT_PAGE_TRANSMIT 7
+#define F1_LINK_PARTNER_NEXT_PAGE 8
+#define F1_1000BASET_CONTROL 9
+#define F1_1000BASET_STATUS 10
+#define F1_MMD_CTRL_REG 13
+#define F1_MMD_DATA_REG 14
+#define F1_EXTENDED_STATUS 15
+#define F1_PHY_SPEC_CONTROL 16
+#define F1_PHY_SPEC_STATUS 17
+#define F1_PHY_INTR_MASK 18
+#define F1_PHY_INTR_STATUS 19
+#define F1_PHY_CDT_CONTROL 22
+#define F1_PHY_CDT_STATUS 28
+#define F1_DEBUG_PORT_ADDRESS 29
+#define F1_DEBUG_PORT_DATA 30
+
+
+ /*debug port*/
+#define F1_DEBUG_PORT_RGMII_MODE 18
+#define F1_DEBUG_PORT_RGMII_MODE_EN 0x0008
+
+#define F1_DEBUG_PORT_RX_DELAY 0
+#define F1_DEBUG_PORT_RX_DELAY_EN 0x8000
+
+#define F1_DEBUG_PORT_TX_DELAY 5
+#define F1_DEBUG_PORT_TX_DELAY_EN 0x0100
+
+ /* PHY Registers Field*/
+
+ /* Control Register fields offset:0*/
+ /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F1_CTRL_SPEED_MSB 0x0040
+
+ /* Collision test enable */
+#define F1_CTRL_COLL_TEST_ENABLE 0x0080
+
+ /* FDX =1, half duplex =0 */
+#define F1_CTRL_FULL_DUPLEX 0x0100
+
+ /* Restart auto negotiation */
+#define F1_CTRL_RESTART_AUTONEGOTIATION 0x0200
+
+ /* Isolate PHY from MII */
+#define F1_CTRL_ISOLATE 0x0400
+
+ /* Power down */
+#define F1_CTRL_POWER_DOWN 0x0800
+
+ /* Auto Neg Enable */
+#define F1_CTRL_AUTONEGOTIATION_ENABLE 0x1000
+
+ /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F1_CTRL_SPEED_LSB 0x2000
+
+ /* 0 = normal, 1 = loopback */
+#define F1_CTRL_LOOPBACK 0x4000
+#define F1_CTRL_SOFTWARE_RESET 0x8000
+
+#define F1_CTRL_SPEED_MASK 0x2040
+#define F1_CTRL_SPEED_1000 0x0040
+#define F1_CTRL_SPEED_100 0x2000
+#define F1_CTRL_SPEED_10 0x0000
+
+#define F1_RESET_DONE(phy_control) \
+ (((phy_control) & (F1_CTRL_SOFTWARE_RESET)) == 0)
+
+ /* Status Register fields offset:1*/
+ /* Extended register capabilities */
+#define F1_STATUS_EXTENDED_CAPS 0x0001
+
+ /* Jabber Detected */
+#define F1_STATUS_JABBER_DETECT 0x0002
+
+ /* Link Status 1 = link */
+#define F1_STATUS_LINK_STATUS_UP 0x0004
+
+ /* Auto Neg Capable */
+#define F1_STATUS_AUTONEG_CAPS 0x0008
+
+ /* Remote Fault Detect */
+#define F1_STATUS_REMOTE_FAULT 0x0010
+
+ /* Auto Neg Complete */
+#define F1_STATUS_AUTO_NEG_DONE 0x0020
+
+ /* Preamble may be suppressed */
+#define F1_STATUS_PREAMBLE_SUPPRESS 0x0040
+
+ /* Ext. status info in Reg 0x0F */
+#define F1_STATUS_EXTENDED_STATUS 0x0100
+
+ /* 100T2 Half Duplex Capable */
+#define F1_STATUS_100T2_HD_CAPS 0x0200
+
+ /* 100T2 Full Duplex Capable */
+#define F1_STATUS_100T2_FD_CAPS 0x0400
+
+ /* 10T Half Duplex Capable */
+#define F1_STATUS_10T_HD_CAPS 0x0800
+
+ /* 10T Full Duplex Capable */
+#define F1_STATUS_10T_FD_CAPS 0x1000
+
+ /* 100X Half Duplex Capable */
+#define F1_STATUS_100X_HD_CAPS 0x2000
+
+ /* 100X Full Duplex Capable */
+#define F1_STATUS_100X_FD_CAPS 0x4000
+
+ /* 100T4 Capable */
+#define F1_STATUS_100T4_CAPS 0x8000
+
+ /* extended status register capabilities */
+
+#define F1_STATUS_1000T_HD_CAPS 0x1000
+
+#define F1_STATUS_1000T_FD_CAPS 0x2000
+
+#define F1_STATUS_1000X_HD_CAPS 0x4000
+
+#define F1_STATUS_1000X_FD_CAPS 0x8000
+
+#define F1_AUTONEG_DONE(ip_phy_status) \
+ (((ip_phy_status) & (F1_STATUS_AUTO_NEG_DONE)) == \
+ (F1_STATUS_AUTO_NEG_DONE))
+
+ /* PHY identifier1 offset:2*/
+//Organizationally Unique Identifier bits 3:18
+
+ /* PHY identifier2 offset:3*/
+//Organizationally Unique Identifier bits 19:24
+
+ /* Auto-Negotiation Advertisement register. offset:4*/
+ /* indicates IEEE 802.3 CSMA/CD */
+#define F1_ADVERTISE_SELECTOR_FIELD 0x0001
+
+ /* 10T Half Duplex Capable */
+#define F1_ADVERTISE_10HALF 0x0020
+
+ /* 10T Full Duplex Capable */
+#define F1_ADVERTISE_10FULL 0x0040
+
+ /* 100TX Half Duplex Capable */
+#define F1_ADVERTISE_100HALF 0x0080
+
+ /* 100TX Full Duplex Capable */
+#define F1_ADVERTISE_100FULL 0x0100
+
+ /* 100T4 Capable */
+#define F1_ADVERTISE_100T4 0x0200
+
+ /* Pause operation desired */
+#define F1_ADVERTISE_PAUSE 0x0400
+
+ /* Asymmetric Pause Direction bit */
+#define F1_ADVERTISE_ASYM_PAUSE 0x0800
+
+ /* Remote Fault detected */
+#define F1_ADVERTISE_REMOTE_FAULT 0x2000
+
+ /* Next Page ability supported */
+#define F1_ADVERTISE_NEXT_PAGE 0x8000
+
+ /* 100TX Half Duplex Capable */
+#define F1_ADVERTISE_1000HALF 0x0100
+
+ /* 100TX Full Duplex Capable */
+#define F1_ADVERTISE_1000FULL 0x0200
+
+#define F1_ADVERTISE_ALL \
+ (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \
+ F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL | \
+ F1_ADVERTISE_1000FULL)
+
+#define F1_ADVERTISE_MEGA_ALL \
+ (F1_ADVERTISE_10HALF | F1_ADVERTISE_10FULL | \
+ F1_ADVERTISE_100HALF | F1_ADVERTISE_100FULL)
+
+ /* Link Partner ability offset:5*/
+ /* Same as advertise selector */
+#define F1_LINK_SLCT 0x001f
+
+ /* Can do 10mbps half-duplex */
+#define F1_LINK_10BASETX_HALF_DUPLEX 0x0020
+
+ /* Can do 10mbps full-duplex */
+#define F1_LINK_10BASETX_FULL_DUPLEX 0x0040
+
+ /* Can do 100mbps half-duplex */
+#define F1_LINK_100BASETX_HALF_DUPLEX 0x0080
+
+ /* Can do 100mbps full-duplex */
+#define F1_LINK_100BASETX_FULL_DUPLEX 0x0100
+
+ /* Can do 1000mbps full-duplex */
+#define F1_LINK_1000BASETX_FULL_DUPLEX 0x0800
+
+ /* Can do 1000mbps half-duplex */
+#define F1_LINK_1000BASETX_HALF_DUPLEX 0x0400
+
+ /* 100BASE-T4 */
+#define F1_LINK_100BASE4 0x0200
+
+ /* PAUSE */
+#define F1_LINK_PAUSE 0x0400
+
+ /* Asymmetrical PAUSE */
+#define F1_LINK_ASYPAUSE 0x0800
+
+ /* Link partner faulted */
+#define F1_LINK_RFAULT 0x2000
+
+ /* Link partner acked us */
+#define F1_LINK_LPACK 0x4000
+
+ /* Next page bit */
+#define F1_LINK_NPAGE 0x8000
+
+ /* Auto-Negotiation Expansion Register offset:6 */
+
+ /* Next Page Transmit Register offset:7 */
+
+ /* Link partner Next Page Register offset:8*/
+
+ /* 1000BASE-T Control Register offset:9*/
+ /* Advertise 1000T HD capability */
+#define F1_CTL_1000T_HD_CAPS 0x0100
+
+ /* Advertise 1000T FD capability */
+#define F1_CTL_1000T_FD_CAPS 0x0200
+
+ /* 1=Repeater/switch device port 0=DTE device*/
+#define F1_CTL_1000T_REPEATER_DTE 0x0400
+
+ /* 1=Configure PHY as Master 0=Configure PHY as Slave */
+#define F1_CTL_1000T_MS_VALUE 0x0800
+
+ /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
+#define F1_CTL_1000T_MS_ENABLE 0x1000
+
+ /* Normal Operation */
+#define F1_CTL_1000T_TEST_MODE_NORMAL 0x0000
+
+ /* Transmit Waveform test */
+#define F1_CTL_1000T_TEST_MODE_1 0x2000
+
+ /* Master Transmit Jitter test */
+#define F1_CTL_1000T_TEST_MODE_2 0x4000
+
+ /* Slave Transmit Jitter test */
+#define F1_CTL_1000T_TEST_MODE_3 0x6000
+
+ /* Transmitter Distortion test */
+#define F1_CTL_1000T_TEST_MODE_4 0x8000
+#define F1_CTL_1000T_SPEED_MASK 0x0300
+#define F1_CTL_1000T_DEFAULT_CAP_MASK 0x0300
+
+ /* 1000BASE-T Status Register offset:10 */
+ /* LP is 1000T HD capable */
+#define F1_STATUS_1000T_LP_HD_CAPS 0x0400
+
+ /* LP is 1000T FD capable */
+#define F1_STATUS_1000T_LP_FD_CAPS 0x0800
+
+ /* Remote receiver OK */
+#define F1_STATUS_1000T_REMOTE_RX_STATUS 0x1000
+
+ /* Local receiver OK */
+#define F1_STATUS_1000T_LOCAL_RX_STATUS 0x2000
+
+ /* 1=Local TX is Master, 0=Slave */
+#define F1_STATUS_1000T_MS_CONFIG_RES 0x4000
+
+#define F1_STATUS_1000T_MS_CONFIG_FAULT 0x8000
+
+ /* Master/Slave config fault */
+#define F1_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12
+#define F1_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13
+
+ /* Phy Specific Control Register offset:16*/
+ /* 1=Jabber Function disabled */
+#define F1_CTL_JABBER_DISABLE 0x0001
+
+ /* 1=Polarity Reversal enabled */
+#define F1_CTL_POLARITY_REVERSAL 0x0002
+
+ /* 1=SQE Test enabled */
+#define F1_CTL_SQE_TEST 0x0004
+#define F1_CTL_MAC_POWERDOWN 0x0008
+
+ /* 1=CLK125 low, 0=CLK125 toggling
+ #define F1_CTL_CLK125_DISABLE 0x0010
+ */
+ /* MDI Crossover Mode bits 6:5 */
+ /* Manual MDI configuration */
+#define F1_CTL_MDI_MANUAL_MODE 0x0000
+
+ /* Manual MDIX configuration */
+#define F1_CTL_MDIX_MANUAL_MODE 0x0020
+
+ /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define F1_CTL_AUTO_X_1000T 0x0040
+
+ /* Auto crossover enabled all speeds */
+#define F1_CTL_AUTO_X_MODE 0x0060
+
+ /* 1=Enable Extended 10BASE-T distance
+ * (Lower 10BASE-T RX Threshold)
+ * 0=Normal 10BASE-T RX Threshold */
+#define F1_CTL_10BT_EXT_DIST_ENABLE 0x0080
+
+ /* 1=5-Bit interface in 100BASE-TX
+ * 0=MII interface in 100BASE-TX */
+#define F1_CTL_MII_5BIT_ENABLE 0x0100
+
+ /* 1=Scrambler disable */
+#define F1_CTL_SCRAMBLER_DISABLE 0x0200
+
+ /* 1=Force link good */
+#define F1_CTL_FORCE_LINK_GOOD 0x0400
+
+ /* 1=Assert CRS on Transmit */
+#define F1_CTL_ASSERT_CRS_ON_TX 0x0800
+
+#define F1_CTL_POLARITY_REVERSAL_SHIFT 1
+#define F1_CTL_AUTO_X_MODE_SHIFT 5
+#define F1_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7
+
+ /* Phy Specific status fields offset:17*/
+ /* 1=Speed & Duplex resolved */
+#define F1_STATUS_LINK_PASS 0x0400
+#define F1_STATUS_RESOVLED 0x0800
+
+ /* 1=Duplex 0=Half Duplex */
+#define F1_STATUS_FULL_DUPLEX 0x2000
+
+ /* Speed, bits 14:15 */
+#define F1_STATUS_SPEED 0xC000
+#define F1_STATUS_SPEED_MASK 0xC000
+
+ /* 00=10Mbs */
+#define F1_STATUS_SPEED_10MBS 0x0000
+
+ /* 01=100Mbs */
+#define F1_STATUS_SPEED_100MBS 0x4000
+
+ /* 10=1000Mbs */
+#define F1_STATUS_SPEED_1000MBS 0x8000
+#define F1_SPEED_DUPLEX_RESOVLED(phy_status) \
+ (((phy_status) & \
+ (F1_STATUS_RESOVLED)) == \
+ (F1_STATUS_RESOVLED))
+
+ /*phy debug port1 register offset:29*/
+ /*phy debug port2 register offset:30*/
+
+ /*F1 interrupt flag */
+#define F1_INTR_SPEED_CHANGE 0x4000
+#define F1_INTR_DUPLEX_CHANGE 0x2000
+#define F1_INTR_STATUS_UP_CHANGE 0x0400
+#define F1_INTR_STATUS_DOWN_CHANGE 0x0800
+
+ sw_error_t
+ f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+ sw_error_t
+ f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+ sw_error_t
+ f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+ sw_error_t
+ f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+ sw_error_t
+ f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len) ;
+
+ sw_error_t
+ f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t duplex);
+
+ sw_error_t
+ f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t * duplex);
+
+ sw_error_t
+ f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t speed);
+
+ sw_error_t
+ f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t * speed);
+
+ sw_error_t
+ f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ sw_error_t
+ f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ a_bool_t
+ f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ sw_error_t
+ f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t autoneg);
+
+ sw_error_t
+ f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * autoneg);
+
+ a_bool_t f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ sw_error_t
+ f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t intr_mask_flag);
+
+ sw_error_t
+ f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * intr_mask_flag);
+
+ sw_error_t
+ f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * intr_status_flag);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _F1_PHY_H_ */
diff --git a/include/hsl/phy/f2_phy.h b/include/hsl/phy/f2_phy.h
new file mode 100644
index 0000000..83c354d
--- /dev/null
+++ b/include/hsl/phy/f2_phy.h
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _F2_PHY_H_
+#define _F2_PHY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ /* Athena PHY Registers */
+#define F2_PHY_CONTROL 0
+#define F2_PHY_STATUS 1
+#define F2_PHY_ID1 2
+#define F2_PHY_ID2 3
+#define F2_AUTONEG_ADVERT 4
+#define F2_LINK_PARTNER_ABILITY 5
+#define F2_AUTONEG_EXPANSION 6
+#define F2_NEXT_PAGE_TRANSMIT 7
+#define F2_LINK_PARTNER_NEXT_PAGE 8
+#define F2_1000BASET_CONTROL 9
+#define F2_1000BASET_STATUS 10
+#define F2_PHY_SPEC_CONTROL 16
+#define F2_PHY_SPEC_STATUS 17
+#define F2_PHY_CDT_CONTROL 22
+#define F2_PHY_CDT_STATUS 28
+#define F2_DEBUG_PORT_ADDRESS 29
+#define F2_DEBUG_PORT_DATA 30
+
+ /* Athena PHY Registers Field*/
+
+ /* Control Register fields offset:0*/
+ /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F2_CTRL_SPEED_MSB 0x0040
+
+ /* Collision test enable */
+#define F2_CTRL_COLL_TEST_ENABLE 0x0080
+
+ /* FDX =1, half duplex =0 */
+#define F2_CTRL_FULL_DUPLEX 0x0100
+
+ /* Restart auto negotiation */
+#define F2_CTRL_RESTART_AUTONEGOTIATION 0x0200
+
+ /* Isolate PHY from MII */
+#define F2_CTRL_ISOLATE 0x0400
+
+ /* Power down */
+#define F2_CTRL_POWER_DOWN 0x0800
+
+ /* Auto Neg Enable */
+#define F2_CTRL_AUTONEGOTIATION_ENABLE 0x1000
+
+ /* bits 6,13: 10=1000, 01=100, 00=10 */
+#define F2_CTRL_SPEED_LSB 0x2000
+
+ /* 0 = normal, 1 = loopback */
+#define F2_CTRL_LOOPBACK 0x4000
+#define F2_CTRL_SOFTWARE_RESET 0x8000
+
+#define F2_CTRL_SPEED_MASK 0x2040
+#define F2_CTRL_SPEED_1000 0x0040
+#define F2_CTRL_SPEED_100 0x2000
+#define F2_CTRL_SPEED_10 0x0000
+
+#define F2_RESET_DONE(phy_control) \
+ (((phy_control) & (F2_CTRL_SOFTWARE_RESET)) == 0)
+
+ /* Status Register fields offset:1*/
+ /* Extended register capabilities */
+#define F2_STATUS_EXTENDED_CAPS 0x0001
+
+ /* Jabber Detected */
+#define F2_STATUS_JABBER_DETECT 0x0002
+
+ /* Link Status 1 = link */
+#define F2_STATUS_LINK_STATUS_UP 0x0004
+
+ /* Auto Neg Capable */
+#define F2_STATUS_AUTONEG_CAPS 0x0008
+
+ /* Remote Fault Detect */
+#define F2_STATUS_REMOTE_FAULT 0x0010
+
+ /* Auto Neg Complete */
+#define F2_STATUS_AUTO_NEG_DONE 0x0020
+
+ /* Preamble may be suppressed */
+#define F2_STATUS_PREAMBLE_SUPPRESS 0x0040
+
+ /* Ext. status info in Reg 0x0F */
+#define F2_STATUS_EXTENDED_STATUS 0x0100
+
+ /* 100T2 Half Duplex Capable */
+#define F2_STATUS_100T2_HD_CAPS 0x0200
+
+ /* 100T2 Full Duplex Capable */
+#define F2_STATUS_100T2_FD_CAPS 0x0400
+
+ /* 10T Half Duplex Capable */
+#define F2_STATUS_10T_HD_CAPS 0x0800
+
+ /* 10T Full Duplex Capable */
+#define F2_STATUS_10T_FD_CAPS 0x1000
+
+ /* 100X Half Duplex Capable */
+#define F2_STATUS_100X_HD_CAPS 0x2000
+
+ /* 100X Full Duplex Capable */
+#define F2_STATUS_100X_FD_CAPS 0x4000
+
+ /* 100T4 Capable */
+#define F2_STATUS_100T4_CAPS 0x8000
+
+#define F2_AUTONEG_DONE(ip_phy_status) \
+ (((ip_phy_status) & (F2_STATUS_AUTO_NEG_DONE)) == \
+ (F2_STATUS_AUTO_NEG_DONE))
+
+ /* PHY identifier1 offset:2*/
+//Organizationally Unique Identifier bits 3:18
+
+ /* PHY identifier2 offset:3*/
+//Organizationally Unique Identifier bits 19:24
+
+ /* Auto-Negotiation Advertisement register. offset:4*/
+ /* indicates IEEE 802.3 CSMA/CD */
+#define F2_ADVERTISE_SELECTOR_FIELD 0x0001
+
+ /* 10T Half Duplex Capable */
+#define F2_ADVERTISE_10HALF 0x0020
+
+ /* 10T Full Duplex Capable */
+#define F2_ADVERTISE_10FULL 0x0040
+
+ /* 100TX Half Duplex Capable */
+#define F2_ADVERTISE_100HALF 0x0080
+
+ /* 100TX Full Duplex Capable */
+#define F2_ADVERTISE_100FULL 0x0100
+
+ /* 100T4 Capable */
+#define F2_ADVERTISE_100T4 0x0200
+
+ /* Pause operation desired */
+#define F2_ADVERTISE_PAUSE 0x0400
+
+ /* Asymmetric Pause Direction bit */
+#define F2_ADVERTISE_ASYM_PAUSE 0x0800
+
+ /* Remote Fault detected */
+#define F2_ADVERTISE_REMOTE_FAULT 0x2000
+
+ /* Next Page ability supported */
+#define F2_ADVERTISE_NEXT_PAGE 0x8000
+
+#define F2_ADVERTISE_ALL \
+ (F2_ADVERTISE_10HALF | F2_ADVERTISE_10FULL | \
+ F2_ADVERTISE_100HALF | F2_ADVERTISE_100FULL )
+
+ /* Link Partner ability offset:5*/
+ /* Same as advertise selector */
+#define F2_LINK_SLCT 0x001f
+
+ /* Can do 10mbps half-duplex */
+#define F2_LINK_10BASETX_HALF_DUPLEX 0x0020
+
+ /* Can do 10mbps full-duplex */
+#define F2_LINK_10BASETX_FULL_DUPLEX 0x0040
+
+ /* Can do 100mbps half-duplex */
+#define F2_LINK_100BASETX_HALF_DUPLEX 0x0080
+
+ /* Can do 100mbps full-duplex */
+#define F2_LINK_100BASETX_FULL_DUPLEX 0x0100
+
+ /* 100BASE-T4 */
+#define F2_LINK_100BASE4 0x0200
+
+ /* PAUSE */
+#define F2_LINK_PAUSE 0x0400
+
+ /* Asymmetrical PAUSE */
+#define F2_LINK_ASYPAUSE 0x0800
+
+ /* Link partner faulted */
+#define F2_LINK_RFAULT 0x2000
+
+ /* Link partner acked us */
+#define F2_LINK_LPACK 0x4000
+
+ /* Next page bit */
+#define F2_LINK_NPAGE 0x8000
+
+ /* Auto-Negotiation Expansion Register offset:6 */
+
+ /* Next Page Transmit Register offset:7 */
+
+ /* Link partner Next Page Register offset:8*/
+
+ /* 1000BASE-T Control Register offset:9*/
+ /* Advertise 1000T HD capability */
+#define F2_CTL_1000T_HD_CAPS 0x0100
+
+ /* Advertise 1000T FD capability */
+#define F2_CTL_1000T_FD_CAPS 0x0200
+
+ /* 1=Repeater/switch device port 0=DTE device*/
+#define F2_CTL_1000T_REPEATER_DTE 0x0400
+
+ /* 1=Configure PHY as Master 0=Configure PHY as Slave */
+#define F2_CTL_1000T_MS_VALUE 0x0800
+
+ /* 1=Master/Slave manual config value 0=Automatic Master/Slave config */
+#define F2_CTL_1000T_MS_ENABLE 0x1000
+
+ /* Normal Operation */
+#define F2_CTL_1000T_TEST_MODE_NORMAL 0x0000
+
+ /* Transmit Waveform test */
+#define F2_CTL_1000T_TEST_MODE_1 0x2000
+
+ /* Master Transmit Jitter test */
+#define F2_CTL_1000T_TEST_MODE_2 0x4000
+
+ /* Slave Transmit Jitter test */
+#define F2_CTL_1000T_TEST_MODE_3 0x6000
+
+ /* Transmitter Distortion test */
+#define F2_CTL_1000T_TEST_MODE_4 0x8000
+#define F2_CTL_1000T_SPEED_MASK 0x0300
+#define F2_CTL_1000T_DEFAULT_CAP_MASK 0x0300
+
+ /* 1000BASE-T Status Register offset:10 */
+ /* LP is 1000T HD capable */
+#define F2_STATUS_1000T_LP_HD_CAPS 0x0400
+
+ /* LP is 1000T FD capable */
+#define F2_STATUS_1000T_LP_FD_CAPS 0x0800
+
+ /* Remote receiver OK */
+#define F2_STATUS_1000T_REMOTE_RX_STATUS 0x1000
+
+ /* Local receiver OK */
+#define F2_STATUS_1000T_LOCAL_RX_STATUS 0x2000
+
+ /* 1=Local TX is Master, 0=Slave */
+#define F2_STATUS_1000T_MS_CONFIG_RES 0x4000
+
+#define F2_STATUS_1000T_MS_CONFIG_FAULT 0x8000
+
+ /* Master/Slave config fault */
+#define F2_STATUS_1000T_REMOTE_RX_STATUS_SHIFT 12
+#define F2_STATUS_1000T_LOCAL_RX_STATUS_SHIFT 13
+
+ /* Phy Specific Control Register offset:16*/
+ /* 1=Jabber Function disabled */
+#define F2_CTL_JABBER_DISABLE 0x0001
+
+ /* 1=Polarity Reversal enabled */
+#define F2_CTL_POLARITY_REVERSAL 0x0002
+
+ /* 1=SQE Test enabled */
+#define F2_CTL_SQE_TEST 0x0004
+#define F2_CTL_MAC_POWERDOWN 0x0008
+
+ /* 1=CLK125 low, 0=CLK125 toggling
+ #define F2_CTL_CLK125_DISABLE 0x0010
+ */
+ /* MDI Crossover Mode bits 6:5 */
+ /* Manual MDI configuration */
+#define F2_CTL_MDI_MANUAL_MODE 0x0000
+
+ /* Manual MDIX configuration */
+#define F2_CTL_MDIX_MANUAL_MODE 0x0020
+
+ /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
+#define F2_CTL_AUTO_X_1000T 0x0040
+
+ /* Auto crossover enabled all speeds */
+#define F2_CTL_AUTO_X_MODE 0x0060
+
+ /* 1=Enable Extended 10BASE-T distance
+ * (Lower 10BASE-T RX Threshold)
+ * 0=Normal 10BASE-T RX Threshold */
+#define F2_CTL_10BT_EXT_DIST_ENABLE 0x0080
+
+ /* 1=5-Bit interface in 100BASE-TX
+ * 0=MII interface in 100BASE-TX */
+#define F2_CTL_MII_5BIT_ENABLE 0x0100
+
+ /* 1=Scrambler disable */
+#define F2_CTL_SCRAMBLER_DISABLE 0x0200
+
+ /* 1=Force link good */
+#define F2_CTL_FORCE_LINK_GOOD 0x0400
+
+ /* 1=Assert CRS on Transmit */
+#define F2_CTL_ASSERT_CRS_ON_TX 0x0800
+
+#define F2_CTL_POLARITY_REVERSAL_SHIFT 1
+#define F2_CTL_AUTO_X_MODE_SHIFT 5
+#define F2_CTL_10BT_EXT_DIST_ENABLE_SHIFT 7
+
+ /* Phy Specific status fields offset:17*/
+ /* 1=Speed & Duplex resolved */
+#define F2_STATUS_RESOVLED 0x0800
+
+ /* 1=Duplex 0=Half Duplex */
+#define F2_STATUS_FULL_DUPLEX 0x2000
+
+ /* Speed, bits 14:15 */
+#define F2_STATUS_SPEED 0xC000
+#define F2_STATUS_SPEED_MASK 0xC000
+
+ /* 00=10Mbs */
+#define F2_STATUS_SPEED_10MBS 0x0000
+
+ /* 01=100Mbs */
+#define F2_STATUS_SPEED_100MBS 0x4000
+
+ /* 10=1000Mbs */
+#define F2_STATUS_SPEED_1000MBS 0x8000
+#define F2_SPEED_DUPLEX_RESOVLED(phy_status) \
+ (((phy_status) & \
+ (F2_STATUS_RESOVLED)) == \
+ (F2_STATUS_RESOVLED))
+
+ /*phy debug port1 register offset:29*/
+ /*phy debug port2 register offset:30*/
+
+ sw_error_t
+ f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+ sw_error_t
+ f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+ sw_error_t
+ f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable);
+
+ sw_error_t
+ f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable);
+
+ sw_error_t
+ f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len) ;
+
+ sw_error_t
+ f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t duplex);
+
+ sw_error_t
+ f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t * duplex);
+
+ sw_error_t
+ f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t speed);
+
+ sw_error_t
+ f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t * speed);
+
+ sw_error_t
+ f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ sw_error_t
+ f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id);
+
+ sw_error_t
+ f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t autoneg);
+
+ sw_error_t
+ f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * autoneg);
+
+ a_bool_t
+ f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _F2_PHY_H_ */
diff --git a/include/hsl/shiva/shiva_acl.h b/include/hsl/shiva/shiva_acl.h
new file mode 100644
index 0000000..1a1fb46
--- /dev/null
+++ b/include/hsl/shiva/shiva_acl.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_acl SHIVA_ACL
+ * @{
+ */
+#ifndef _SHIVA_ACL_H_
+#define _SHIVA_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_acl.h"
+
+ sw_error_t
+ shiva_acl_init(a_uint32_t dev_id);
+
+ sw_error_t
+ shiva_acl_reset(a_uint32_t dev_id);
+
+#ifdef IN_ACL
+#define SHIVA_ACL_INIT(rv, dev_id) \
+ { \
+ rv = shiva_acl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+
+#define SHIVA_ACL_RESET(rv, dev_id) \
+ { \
+ rv = shiva_acl_reset(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_ACL_INIT(rv, dev_id)
+#define SHIVA_ACL_RESET(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_list_dump(a_uint32_t dev_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_acl_rule_dump(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_ACL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_api.h b/include/hsl/shiva/shiva_api.h
new file mode 100644
index 0000000..b2e4cbb
--- /dev/null
+++ b/include/hsl/shiva/shiva_api.h
@@ -0,0 +1,600 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SHIVA_API_H_
+#define _SHIVA_API_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef IN_PORTCONTROL
+#define PORTCONTROL_API \
+ SW_API_DEF(SW_API_PT_DUPLEX_GET, shiva_port_duplex_get), \
+ SW_API_DEF(SW_API_PT_DUPLEX_SET, shiva_port_duplex_set), \
+ SW_API_DEF(SW_API_PT_SPEED_GET, shiva_port_speed_get), \
+ SW_API_DEF(SW_API_PT_SPEED_SET, shiva_port_speed_set), \
+ SW_API_DEF(SW_API_PT_AN_GET, shiva_port_autoneg_status_get), \
+ SW_API_DEF(SW_API_PT_AN_ENABLE, shiva_port_autoneg_enable), \
+ SW_API_DEF(SW_API_PT_AN_RESTART, shiva_port_autoneg_restart), \
+ SW_API_DEF(SW_API_PT_AN_ADV_GET, shiva_port_autoneg_adv_get), \
+ SW_API_DEF(SW_API_PT_AN_ADV_SET, shiva_port_autoneg_adv_set), \
+ SW_API_DEF(SW_API_PT_HDR_SET, shiva_port_hdr_status_set), \
+ SW_API_DEF(SW_API_PT_HDR_GET, shiva_port_hdr_status_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_SET, shiva_port_flowctrl_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_GET, shiva_port_flowctrl_get), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_SET, shiva_port_flowctrl_forcemode_set), \
+ SW_API_DEF(SW_API_PT_FLOWCTRL_MODE_GET, shiva_port_flowctrl_forcemode_get), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_SET, shiva_port_powersave_set), \
+ SW_API_DEF(SW_API_PT_POWERSAVE_GET, shiva_port_powersave_get), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_SET, shiva_port_hibernate_set), \
+ SW_API_DEF(SW_API_PT_HIBERNATE_GET, shiva_port_hibernate_get), \
+ SW_API_DEF(SW_API_PT_CDT, shiva_port_cdt),
+
+
+#define PORTCONTROL_API_PARAM \
+ SW_API_DESC(SW_API_PT_DUPLEX_GET) \
+ SW_API_DESC(SW_API_PT_DUPLEX_SET) \
+ SW_API_DESC(SW_API_PT_SPEED_GET) \
+ SW_API_DESC(SW_API_PT_SPEED_SET) \
+ SW_API_DESC(SW_API_PT_AN_GET) \
+ SW_API_DESC(SW_API_PT_AN_ENABLE) \
+ SW_API_DESC(SW_API_PT_AN_RESTART) \
+ SW_API_DESC(SW_API_PT_AN_ADV_GET) \
+ SW_API_DESC(SW_API_PT_AN_ADV_SET) \
+ SW_API_DESC(SW_API_PT_HDR_SET) \
+ SW_API_DESC(SW_API_PT_HDR_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_GET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_SET) \
+ SW_API_DESC(SW_API_PT_FLOWCTRL_MODE_GET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_SET) \
+ SW_API_DESC(SW_API_PT_POWERSAVE_GET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_SET) \
+ SW_API_DESC(SW_API_PT_HIBERNATE_GET) \
+ SW_API_DESC(SW_API_PT_CDT)
+
+#else
+#define PORTCONTROL_API
+#define PORTCONTROL_API_PARAM
+#endif
+
+#ifdef IN_VLAN
+#define VLAN_API \
+ SW_API_DEF(SW_API_VLAN_ADD, shiva_vlan_create), \
+ SW_API_DEF(SW_API_VLAN_DEL, shiva_vlan_delete), \
+ SW_API_DEF(SW_API_VLAN_MEM_UPDATE, shiva_vlan_member_update), \
+ SW_API_DEF(SW_API_VLAN_FIND, shiva_vlan_find), \
+ SW_API_DEF(SW_API_VLAN_NEXT, shiva_vlan_next), \
+ SW_API_DEF(SW_API_VLAN_APPEND, shiva_vlan_entry_append), \
+ SW_API_DEF(SW_API_VLAN_FLUSH, shiva_vlan_flush),
+
+#define VLAN_API_PARAM \
+ SW_API_DESC(SW_API_VLAN_ADD) \
+ SW_API_DESC(SW_API_VLAN_DEL) \
+ SW_API_DESC(SW_API_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_VLAN_FIND) \
+ SW_API_DESC(SW_API_VLAN_NEXT) \
+ SW_API_DESC(SW_API_VLAN_APPEND) \
+ SW_API_DESC(SW_API_VLAN_FLUSH)
+#else
+#define VLAN_API
+#define VLAN_API_PARAM
+#endif
+
+#ifdef IN_PORTVLAN
+#define PORTVLAN_API \
+ SW_API_DEF(SW_API_PT_ING_MODE_GET, shiva_port_1qmode_get), \
+ SW_API_DEF(SW_API_PT_ING_MODE_SET, shiva_port_1qmode_set), \
+ SW_API_DEF(SW_API_PT_EG_MODE_GET, shiva_port_egvlanmode_get), \
+ SW_API_DEF(SW_API_PT_EG_MODE_SET, shiva_port_egvlanmode_set), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_ADD, shiva_portvlan_member_add), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_DEL, shiva_portvlan_member_del), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_UPDATE, shiva_portvlan_member_update), \
+ SW_API_DEF(SW_API_PT_VLAN_MEM_GET, shiva_portvlan_member_get), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_SET, shiva_port_force_default_vid_set), \
+ SW_API_DEF(SW_API_PT_FORCE_DEF_VID_GET, shiva_port_force_default_vid_get), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_SET, shiva_port_force_portvlan_set), \
+ SW_API_DEF(SW_API_PT_FORCE_PORTVLAN_GET, shiva_port_force_portvlan_get), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_SET, shiva_nestvlan_tpid_set), \
+ SW_API_DEF(SW_API_NESTVLAN_TPID_GET, shiva_nestvlan_tpid_get), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_SET, shiva_port_invlan_mode_set), \
+ SW_API_DEF(SW_API_PT_IN_VLAN_MODE_GET, shiva_port_invlan_mode_get), \
+ SW_API_DEF(SW_API_PT_TLS_SET, shiva_port_tls_set), \
+ SW_API_DEF(SW_API_PT_TLS_GET, shiva_port_tls_get), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_SET, shiva_port_pri_propagation_set), \
+ SW_API_DEF(SW_API_PT_PRI_PROPAGATION_GET, shiva_port_pri_propagation_get), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_SET, shiva_port_default_svid_set), \
+ SW_API_DEF(SW_API_PT_DEF_SVID_GET, shiva_port_default_svid_get), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_SET, shiva_port_default_cvid_set), \
+ SW_API_DEF(SW_API_PT_DEF_CVID_GET, shiva_port_default_cvid_get), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_SET, shiva_port_vlan_propagation_set), \
+ SW_API_DEF(SW_API_PT_VLAN_PROPAGATION_GET, shiva_port_vlan_propagation_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ADD, shiva_port_vlan_trans_add), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_DEL, shiva_port_vlan_trans_del), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_GET, shiva_port_vlan_trans_get), \
+ SW_API_DEF(SW_API_QINQ_MODE_SET, shiva_qinq_mode_set), \
+ SW_API_DEF(SW_API_QINQ_MODE_GET, shiva_qinq_mode_get), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_SET, shiva_port_qinq_role_set), \
+ SW_API_DEF(SW_API_PT_QINQ_ROLE_GET, shiva_port_qinq_role_get), \
+ SW_API_DEF(SW_API_PT_VLAN_TRANS_ITERATE, shiva_port_vlan_trans_iterate),
+
+#define PORTVLAN_API_PARAM \
+ SW_API_DESC(SW_API_PT_ING_MODE_GET) \
+ SW_API_DESC(SW_API_PT_ING_MODE_SET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_GET) \
+ SW_API_DESC(SW_API_PT_EG_MODE_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_UPDATE) \
+ SW_API_DESC(SW_API_PT_VLAN_MEM_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_DEF_VID_GET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_SET) \
+ SW_API_DESC(SW_API_PT_FORCE_PORTVLAN_GET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_SET) \
+ SW_API_DESC(SW_API_NESTVLAN_TPID_GET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IN_VLAN_MODE_GET) \
+ SW_API_DESC(SW_API_PT_TLS_SET) \
+ SW_API_DESC(SW_API_PT_TLS_GET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_PRI_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_SVID_GET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_SET) \
+ SW_API_DESC(SW_API_PT_DEF_CVID_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_SET) \
+ SW_API_DESC(SW_API_PT_VLAN_PROPAGATION_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ADD) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_DEL) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_GET) \
+ SW_API_DESC(SW_API_QINQ_MODE_SET) \
+ SW_API_DESC(SW_API_QINQ_MODE_GET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_SET) \
+ SW_API_DESC(SW_API_PT_QINQ_ROLE_GET) \
+ SW_API_DESC(SW_API_PT_VLAN_TRANS_ITERATE)
+#else
+#define PORTVLAN_API
+#define PORTVLAN_API_PARAM
+#endif
+
+#ifdef IN_FDB
+#define FDB_API \
+ SW_API_DEF(SW_API_FDB_ADD, shiva_fdb_add), \
+ SW_API_DEF(SW_API_FDB_DELALL, shiva_fdb_del_all), \
+ SW_API_DEF(SW_API_FDB_DELPORT,shiva_fdb_del_by_port), \
+ SW_API_DEF(SW_API_FDB_DELMAC, shiva_fdb_del_by_mac), \
+ SW_API_DEF(SW_API_FDB_FIRST, shiva_fdb_first), \
+ SW_API_DEF(SW_API_FDB_FIND, shiva_fdb_find), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_SET, shiva_fdb_port_learn_set), \
+ SW_API_DEF(SW_API_FDB_PT_LEARN_GET, shiva_fdb_port_learn_get), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_SET, shiva_fdb_age_ctrl_set), \
+ SW_API_DEF(SW_API_FDB_AGE_CTRL_GET, shiva_fdb_age_ctrl_get), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_SET, shiva_fdb_age_time_set), \
+ SW_API_DEF(SW_API_FDB_AGE_TIME_GET, shiva_fdb_age_time_get), \
+ SW_API_DEF(SW_API_FDB_ITERATE, shiva_fdb_iterate),
+
+#define FDB_API_PARAM \
+ SW_API_DESC(SW_API_FDB_ADD) \
+ SW_API_DESC(SW_API_FDB_DELALL) \
+ SW_API_DESC(SW_API_FDB_DELPORT) \
+ SW_API_DESC(SW_API_FDB_DELMAC) \
+ SW_API_DESC(SW_API_FDB_FIRST) \
+ SW_API_DESC(SW_API_FDB_FIND) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_SET) \
+ SW_API_DESC(SW_API_FDB_PT_LEARN_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_CTRL_GET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_SET) \
+ SW_API_DESC(SW_API_FDB_AGE_TIME_GET) \
+ SW_API_DESC(SW_API_FDB_ITERATE)
+#else
+#define FDB_API
+#define FDB_API_PARAM
+#endif
+
+#ifdef IN_ACL
+#define ACL_API \
+ SW_API_DEF(SW_API_ACL_LIST_CREAT, shiva_acl_list_creat), \
+ SW_API_DEF(SW_API_ACL_LIST_DESTROY, shiva_acl_list_destroy), \
+ SW_API_DEF(SW_API_ACL_RULE_ADD, shiva_acl_rule_add), \
+ SW_API_DEF(SW_API_ACL_RULE_DELETE, shiva_acl_rule_delete), \
+ SW_API_DEF(SW_API_ACL_RULE_QUERY, shiva_acl_rule_query), \
+ SW_API_DEF(SW_API_ACL_LIST_BIND, shiva_acl_list_bind), \
+ SW_API_DEF(SW_API_ACL_LIST_UNBIND, shiva_acl_list_unbind), \
+ SW_API_DEF(SW_API_ACL_STATUS_SET, shiva_acl_status_set), \
+ SW_API_DEF(SW_API_ACL_STATUS_GET, shiva_acl_status_get), \
+ SW_API_DEF(SW_API_ACL_LIST_DUMP, shiva_acl_list_dump), \
+ SW_API_DEF(SW_API_ACL_RULE_DUMP, shiva_acl_rule_dump),
+
+#define ACL_API_PARAM \
+ SW_API_DESC(SW_API_ACL_LIST_CREAT) \
+ SW_API_DESC(SW_API_ACL_LIST_DESTROY) \
+ SW_API_DESC(SW_API_ACL_RULE_ADD) \
+ SW_API_DESC(SW_API_ACL_RULE_DELETE) \
+ SW_API_DESC(SW_API_ACL_RULE_QUERY) \
+ SW_API_DESC(SW_API_ACL_LIST_BIND) \
+ SW_API_DESC(SW_API_ACL_LIST_UNBIND) \
+ SW_API_DESC(SW_API_ACL_STATUS_SET) \
+ SW_API_DESC(SW_API_ACL_STATUS_GET) \
+ SW_API_DESC(SW_API_ACL_LIST_DUMP) \
+ SW_API_DESC(SW_API_ACL_RULE_DUMP)
+#else
+#define ACL_API
+#define ACL_API_PARAM
+#endif
+
+#ifdef IN_QOS
+#define QOS_API \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_SET, shiva_qos_queue_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_ST_GET, shiva_qos_queue_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_SET, shiva_qos_queue_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_QU_TX_BUF_NR_GET, shiva_qos_queue_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_SET, shiva_qos_port_tx_buf_status_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_ST_GET, shiva_qos_port_tx_buf_status_get), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_SET, shiva_qos_port_tx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_TX_BUF_NR_GET, shiva_qos_port_tx_buf_nr_get), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_SET, shiva_qos_port_rx_buf_nr_set), \
+ SW_API_DEF(SW_API_QOS_PT_RX_BUF_NR_GET, shiva_qos_port_rx_buf_nr_get), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_SET, shiva_cosmap_up_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_UP_QU_GET, shiva_cosmap_up_queue_get), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_SET, shiva_cosmap_dscp_queue_set), \
+ SW_API_DEF(SW_API_COSMAP_DSCP_QU_GET, shiva_cosmap_dscp_queue_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_SET, shiva_qos_port_mode_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_GET, shiva_qos_port_mode_get), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_SET, shiva_qos_port_mode_pri_set), \
+ SW_API_DEF(SW_API_QOS_PT_MODE_PRI_GET, shiva_qos_port_mode_pri_get), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_SET, shiva_qos_port_default_up_set), \
+ SW_API_DEF(SW_API_QOS_PORT_DEF_UP_GET, shiva_qos_port_default_up_get), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_SET, shiva_qos_port_sch_mode_set), \
+ SW_API_DEF(SW_API_QOS_PORT_SCH_MODE_GET, shiva_qos_port_sch_mode_get),
+
+#define QOS_API_PARAM \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_QU_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_ST_GET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_TX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_SET) \
+ SW_API_DESC(SW_API_QOS_PT_RX_BUF_NR_GET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_UP_QU_GET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_SET) \
+ SW_API_DESC(SW_API_COSMAP_DSCP_QU_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_GET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_SET) \
+ SW_API_DESC(SW_API_QOS_PT_MODE_PRI_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_DEF_UP_GET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_SET) \
+ SW_API_DESC(SW_API_QOS_PORT_SCH_MODE_GET)
+#else
+#define QOS_API
+#define QOS_API_PARAM
+#endif
+
+#ifdef IN_IGMP
+#define IGMP_API \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_SET, shiva_port_igmps_status_set), \
+ SW_API_DEF(SW_API_PT_IGMPS_MODE_GET, shiva_port_igmps_status_get), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_SET, shiva_igmp_mld_cmd_set), \
+ SW_API_DEF(SW_API_IGMP_MLD_CMD_GET, shiva_igmp_mld_cmd_get), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_SET, shiva_port_igmp_mld_join_set), \
+ SW_API_DEF(SW_API_IGMP_PT_JOIN_GET, shiva_port_igmp_mld_join_get), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_SET, shiva_port_igmp_mld_leave_set), \
+ SW_API_DEF(SW_API_IGMP_PT_LEAVE_GET, shiva_port_igmp_mld_leave_get), \
+ SW_API_DEF(SW_API_IGMP_RP_SET, shiva_igmp_mld_rp_set), \
+ SW_API_DEF(SW_API_IGMP_RP_GET, shiva_igmp_mld_rp_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_SET, shiva_igmp_mld_entry_creat_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_CREAT_GET, shiva_igmp_mld_entry_creat_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_SET, shiva_igmp_mld_entry_static_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_STATIC_GET, shiva_igmp_mld_entry_static_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_SET, shiva_igmp_mld_entry_leaky_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_LEAKY_GET, shiva_igmp_mld_entry_leaky_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_SET, shiva_igmp_mld_entry_v3_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_V3_GET, shiva_igmp_mld_entry_v3_get), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_SET, shiva_igmp_mld_entry_queue_set), \
+ SW_API_DEF(SW_API_IGMP_ENTRY_QUEUE_GET, shiva_igmp_mld_entry_queue_get),
+
+#define IGMP_API_PARAM \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_SET) \
+ SW_API_DESC(SW_API_PT_IGMPS_MODE_GET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_SET) \
+ SW_API_DESC(SW_API_IGMP_MLD_CMD_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_JOIN_GET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_SET) \
+ SW_API_DESC(SW_API_IGMP_PT_LEAVE_GET) \
+ SW_API_DESC(SW_API_IGMP_RP_SET) \
+ SW_API_DESC(SW_API_IGMP_RP_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_CREAT_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_STATIC_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_LEAKY_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_V3_GET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_SET) \
+ SW_API_DESC(SW_API_IGMP_ENTRY_QUEUE_GET)
+#else
+#define IGMP_API
+#define IGMP_API_PARAM
+#endif
+
+#ifdef IN_LEAKY
+#define LEAKY_API \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_SET, shiva_uc_leaky_mode_set), \
+ SW_API_DEF(SW_API_UC_LEAKY_MODE_GET, shiva_uc_leaky_mode_get), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_SET, shiva_mc_leaky_mode_set), \
+ SW_API_DEF(SW_API_MC_LEAKY_MODE_GET, shiva_mc_leaky_mode_get), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_SET, shiva_port_arp_leaky_set), \
+ SW_API_DEF(SW_API_ARP_LEAKY_MODE_GET, shiva_port_arp_leaky_get), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_SET, shiva_port_uc_leaky_set), \
+ SW_API_DEF(SW_API_PT_UC_LEAKY_MODE_GET, shiva_port_uc_leaky_get), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_SET, shiva_port_mc_leaky_set), \
+ SW_API_DEF(SW_API_PT_MC_LEAKY_MODE_GET, shiva_port_mc_leaky_get),
+
+#define LEAKY_API_PARAM \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_MC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_ARP_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_UC_LEAKY_MODE_GET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_SET) \
+ SW_API_DESC(SW_API_PT_MC_LEAKY_MODE_GET)
+#else
+#define LEAKY_API
+#define LEAKY_API_PARAM
+#endif
+
+#ifdef IN_MIRROR
+#define MIRROR_API \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_SET, shiva_mirr_analysis_port_set), \
+ SW_API_DEF(SW_API_MIRROR_ANALY_PT_GET, shiva_mirr_analysis_port_get), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_SET, shiva_mirr_port_in_set), \
+ SW_API_DEF(SW_API_MIRROR_IN_PT_GET, shiva_mirr_port_in_get), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_SET, shiva_mirr_port_eg_set), \
+ SW_API_DEF(SW_API_MIRROR_EG_PT_GET, shiva_mirr_port_eg_get),
+
+#define MIRROR_API_PARAM \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_ANALY_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_IN_PT_GET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_SET) \
+ SW_API_DESC(SW_API_MIRROR_EG_PT_GET)
+#else
+#define MIRROR_API
+#define MIRROR_API_PARAM
+#endif
+
+#ifdef IN_RATE
+#define RATE_API \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_SET, shiva_rate_queue_egrl_set), \
+ SW_API_DEF(SW_API_RATE_QU_EGRL_GET, shiva_rate_queue_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_SET, shiva_rate_port_egrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_EGRL_GET, shiva_rate_port_egrl_get), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_SET, shiva_rate_port_inrl_set), \
+ SW_API_DEF(SW_API_RATE_PT_INRL_GET, shiva_rate_port_inrl_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_SET, shiva_storm_ctrl_frame_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_FRAME_GET, shiva_storm_ctrl_frame_get), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_SET, shiva_storm_ctrl_rate_set), \
+ SW_API_DEF(SW_API_STORM_CTRL_RATE_GET, shiva_storm_ctrl_rate_get),
+
+#define RATE_API_PARAM \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_QU_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_EGRL_GET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_SET) \
+ SW_API_DESC(SW_API_RATE_PT_INRL_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_FRAME_GET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_SET) \
+ SW_API_DESC(SW_API_STORM_CTRL_RATE_GET)
+#else
+#define RATE_API
+#define RATE_API_PARAM
+#endif
+
+#ifdef IN_STP
+#define STP_API \
+ SW_API_DEF(SW_API_STP_PT_STATE_SET, shiva_stp_port_state_set), \
+ SW_API_DEF(SW_API_STP_PT_STATE_GET, shiva_stp_port_state_get),
+
+#define STP_API_PARAM \
+ SW_API_DESC(SW_API_STP_PT_STATE_SET) \
+ SW_API_DESC(SW_API_STP_PT_STATE_GET)
+#else
+#define STP_API
+#define STP_API_PARAM
+#endif
+
+#ifdef IN_MIB
+#define MIB_API \
+ SW_API_DEF(SW_API_PT_MIB_GET, shiva_get_mib_info), \
+ SW_API_DEF(SW_API_MIB_STATUS_SET, shiva_mib_status_set), \
+ SW_API_DEF(SW_API_MIB_STATUS_GET, shiva_mib_status_get),
+
+#define MIB_API_PARAM \
+ SW_API_DESC(SW_API_PT_MIB_GET) \
+ SW_API_DESC(SW_API_MIB_STATUS_SET) \
+ SW_API_DESC(SW_API_MIB_STATUS_GET)
+#else
+#define MIB_API
+#define MIB_API_PARAM
+#endif
+
+#ifdef IN_MISC
+#define MISC_API \
+ SW_API_DEF(SW_API_ARP_STATUS_SET, shiva_arp_status_set), \
+ SW_API_DEF(SW_API_ARP_STATUS_GET, shiva_arp_status_get), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_SET, shiva_frame_max_size_set), \
+ SW_API_DEF(SW_API_FRAME_MAX_SIZE_GET, shiva_frame_max_size_get), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_SET, shiva_port_unk_sa_cmd_set), \
+ SW_API_DEF(SW_API_PT_UNK_SA_CMD_GET, shiva_port_unk_sa_cmd_get), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_SET, shiva_port_unk_uc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_UC_FILTER_GET, shiva_port_unk_uc_filter_get), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_SET, shiva_port_unk_mc_filter_set), \
+ SW_API_DEF(SW_API_PT_UNK_MC_FILTER_GET, shiva_port_unk_mc_filter_get), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_SET, shiva_port_bc_filter_set), \
+ SW_API_DEF(SW_API_PT_BC_FILTER_GET, shiva_port_bc_filter_get), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_SET, shiva_cpu_port_status_set), \
+ SW_API_DEF(SW_API_CPU_PORT_STATUS_GET, shiva_cpu_port_status_get), \
+ SW_API_DEF(SW_API_PPPOE_CMD_SET, shiva_pppoe_cmd_set), \
+ SW_API_DEF(SW_API_PPPOE_CMD_GET, shiva_pppoe_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_SET, shiva_pppoe_status_set), \
+ SW_API_DEF(SW_API_PPPOE_STATUS_GET, shiva_pppoe_status_get), \
+ SW_API_DEF(SW_API_PT_DHCP_SET, shiva_port_dhcp_set), \
+ SW_API_DEF(SW_API_PT_DHCP_GET, shiva_port_dhcp_get), \
+ SW_API_DEF(SW_API_ARP_CMD_SET, shiva_arp_cmd_set), \
+ SW_API_DEF(SW_API_ARP_CMD_GET, shiva_arp_cmd_get), \
+ SW_API_DEF(SW_API_EAPOL_CMD_SET, shiva_eapol_cmd_set), \
+ SW_API_DEF(SW_API_EAPOL_CMD_GET, shiva_eapol_cmd_get), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_ADD, shiva_pppoe_session_add), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_DEL, shiva_pppoe_session_del), \
+ SW_API_DEF(SW_API_PPPOE_SESSION_GET, shiva_pppoe_session_get), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_SET, shiva_eapol_status_set), \
+ SW_API_DEF(SW_API_EAPOL_STATUS_GET, shiva_eapol_status_get), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_SET, shiva_ripv1_status_set), \
+ SW_API_DEF(SW_API_RIPV1_STATUS_GET, shiva_ripv1_status_get),
+
+#define MISC_API_PARAM \
+ SW_API_DESC(SW_API_ARP_STATUS_SET) \
+ SW_API_DESC(SW_API_ARP_STATUS_GET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_SET) \
+ SW_API_DESC(SW_API_FRAME_MAX_SIZE_GET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_SET) \
+ SW_API_DESC(SW_API_PT_UNK_SA_CMD_GET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_UC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_UNK_MC_FILTER_GET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_SET) \
+ SW_API_DESC(SW_API_PT_BC_FILTER_GET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_SET) \
+ SW_API_DESC(SW_API_CPU_PORT_STATUS_GET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_SET) \
+ SW_API_DESC(SW_API_PPPOE_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_SET) \
+ SW_API_DESC(SW_API_PPPOE_STATUS_GET) \
+ SW_API_DESC(SW_API_PT_DHCP_SET) \
+ SW_API_DESC(SW_API_PT_DHCP_GET) \
+ SW_API_DESC(SW_API_ARP_CMD_SET) \
+ SW_API_DESC(SW_API_ARP_CMD_GET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_SET) \
+ SW_API_DESC(SW_API_EAPOL_CMD_GET) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_ADD) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_DEL) \
+ SW_API_DESC(SW_API_PPPOE_SESSION_GET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_SET) \
+ SW_API_DESC(SW_API_EAPOL_STATUS_GET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_SET) \
+ SW_API_DESC(SW_API_RIPV1_STATUS_GET)
+#else
+#define MISC_API
+#define MISC_API_PARAM
+#endif
+
+#ifdef IN_LED
+#define LED_API \
+ SW_API_DEF(SW_API_LED_PATTERN_SET, shiva_led_ctrl_pattern_set), \
+ SW_API_DEF(SW_API_LED_PATTERN_GET, shiva_led_ctrl_pattern_get),
+
+#define LED_API_PARAM \
+ SW_API_DESC(SW_API_LED_PATTERN_SET) \
+ SW_API_DESC(SW_API_LED_PATTERN_GET)
+#else
+#define LED_API
+#define LED_API_PARAM
+#endif
+
+#define REG_API \
+ SW_API_DEF(SW_API_PHY_GET, shiva_phy_get), \
+ SW_API_DEF(SW_API_PHY_SET, shiva_phy_set), \
+ SW_API_DEF(SW_API_REG_GET, shiva_reg_get), \
+ SW_API_DEF(SW_API_REG_SET, shiva_reg_set), \
+ SW_API_DEF(SW_API_REG_FIELD_GET, shiva_reg_field_get), \
+ SW_API_DEF(SW_API_REG_FIELD_SET, shiva_reg_field_set),
+
+#define REG_API_PARAM \
+ SW_API_DESC(SW_API_PHY_GET) \
+ SW_API_DESC(SW_API_PHY_SET) \
+ SW_API_DESC(SW_API_REG_GET) \
+ SW_API_DESC(SW_API_REG_SET) \
+ SW_API_DESC(SW_API_REG_FIELD_GET) \
+ SW_API_DESC(SW_API_REG_FIELD_SET)
+
+#define SSDK_API \
+ SW_API_DEF(SW_API_SWITCH_RESET, shiva_reset), \
+ SW_API_DEF(SW_API_SSDK_CFG, hsl_ssdk_cfg), \
+ PORTCONTROL_API \
+ VLAN_API \
+ PORTVLAN_API \
+ FDB_API \
+ ACL_API \
+ QOS_API \
+ IGMP_API \
+ LEAKY_API \
+ MIRROR_API \
+ RATE_API \
+ STP_API \
+ MIB_API \
+ MISC_API \
+ LED_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+
+#define SSDK_PARAM \
+ SW_PARAM_DEF(SW_API_SWITCH_RESET, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"), \
+ SW_PARAM_DEF(SW_API_SSDK_CFG, SW_SSDK_CFG, sizeof(ssdk_cfg_t), SW_PARAM_PTR|SW_PARAM_OUT, "ssdk configuration"), \
+ MIB_API_PARAM \
+ LEAKY_API_PARAM \
+ MISC_API_PARAM \
+ IGMP_API_PARAM \
+ MIRROR_API_PARAM \
+ PORTCONTROL_API_PARAM \
+ PORTVLAN_API_PARAM \
+ VLAN_API_PARAM \
+ FDB_API_PARAM \
+ QOS_API_PARAM \
+ RATE_API_PARAM \
+ STP_API_PARAM \
+ ACL_API_PARAM \
+ LED_API_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+
+#if (defined(USER_MODE) && defined(KERNEL_MODULE))
+#undef SSDK_API
+#undef SSDK_PARAM
+
+#define SSDK_API \
+ REG_API \
+ SW_API_DEF(SW_API_MAX, NULL),
+
+#define SSDK_PARAM \
+ REG_API_PARAM \
+ SW_PARAM_DEF(SW_API_MAX, SW_UINT32, 4, SW_PARAM_IN, "Dev ID"),
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_API_H_ */
diff --git a/include/hsl/shiva/shiva_fdb.h b/include/hsl/shiva/shiva_fdb.h
new file mode 100644
index 0000000..b714f44
--- /dev/null
+++ b/include/hsl/shiva/shiva_fdb.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_fdb SHIVA_FDB
+ * @{
+ */
+#ifndef _SHIVA_FDB_H_
+#define _SHIVA_FDB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_fdb.h"
+
+ sw_error_t
+ shiva_fdb_init(a_uint32_t dev_id);
+
+#ifdef IN_FDB
+#define SHIVA_FDB_INIT(rv, dev_id) \
+ { \
+ rv = shiva_fdb_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_FDB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_del_by_port(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_del_by_mac(a_uint32_t dev_id,
+ const fal_fdb_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_FDB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_igmp.h b/include/hsl/shiva/shiva_igmp.h
new file mode 100644
index 0000000..6508635
--- /dev/null
+++ b/include/hsl/shiva/shiva_igmp.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_igmp SHIVA_IGMP
+ * @{
+ */
+#ifndef _SHIVA_IGMP_H_
+#define _SHIVA_IGMP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_igmp.h"
+
+ sw_error_t
+ shiva_igmp_init(a_uint32_t dev_id);
+
+#ifdef IN_IGMP
+#define SHIVA_IGMP_INIT(rv, dev_id) \
+ { \
+ rv = shiva_igmp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_IGMP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_IGMP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_init.h b/include/hsl/shiva/shiva_init.h
new file mode 100644
index 0000000..02801b3
--- /dev/null
+++ b/include/hsl/shiva/shiva_init.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_init SHIVA_INIT
+ * @{
+ */
+#ifndef _SHIVA_INIT_H_
+#define _SHIVA_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "init/ssdk_init.h"
+
+
+ sw_error_t
+ shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+
+ sw_error_t
+ shiva_cleanup(a_uint32_t dev_id);
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_reset(a_uint32_t dev_id);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_INIT_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_leaky.h b/include/hsl/shiva/shiva_leaky.h
new file mode 100644
index 0000000..49d9d41
--- /dev/null
+++ b/include/hsl/shiva/shiva_leaky.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_leaky SHIVA_LEAKY
+ * @{
+ */
+#ifndef _SHIVA_LEAKY_H_
+#define _SHIVA_LEAKY_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_leaky.h"
+
+ sw_error_t shiva_leaky_init(a_uint32_t dev_id);
+
+#ifdef IN_LEAKY
+#define SHIVA_LEAKY_INIT(rv, dev_id) \
+ { \
+ rv = shiva_leaky_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_LEAKY_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t * ctrl_mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_LEAKY_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_led.h b/include/hsl/shiva/shiva_led.h
new file mode 100644
index 0000000..062ba13
--- /dev/null
+++ b/include/hsl/shiva/shiva_led.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#ifndef _SHIVA_LED_H_
+#define _SHIVA_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_led.h"
+
+ sw_error_t
+ shiva_led_init(a_uint32_t dev_id);
+
+#ifdef IN_LED
+#define SHIVA_LED_INIT(rv, dev_id) \
+ { \
+ rv = shiva_led_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_LED_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_LED_H_ */
diff --git a/include/hsl/shiva/shiva_mib.h b/include/hsl/shiva/shiva_mib.h
new file mode 100644
index 0000000..eb9650e
--- /dev/null
+++ b/include/hsl/shiva/shiva_mib.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_mib SHIVA_MIB
+ * @{
+ */
+#ifndef _SHIVA_MIB_H_
+#define _SHIVA_MIB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mib.h"
+
+ sw_error_t
+ shiva_mib_init(a_uint32_t dev_id);
+
+#ifdef IN_MIB
+#define SHIVA_MIB_INIT(rv, dev_id) \
+ { \
+ rv = shiva_mib_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_MIB_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info );
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_MIB_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_mirror.h b/include/hsl/shiva/shiva_mirror.h
new file mode 100644
index 0000000..47b9204
--- /dev/null
+++ b/include/hsl/shiva/shiva_mirror.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_mirror SHIVA_MIRROR
+ * @{
+ */
+#ifndef _SHIVA_MIRROR_H_
+#define _SHIVA_MIRROR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_mirror.h"
+
+ sw_error_t shiva_mirr_init(a_uint32_t dev_id);
+
+#ifdef IN_MIRROR
+#define SHIVA_MIRR_INIT(rv, dev_id) \
+ { \
+ rv = shiva_mirr_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_MIRR_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_MIRROR_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_misc.h b/include/hsl/shiva/shiva_misc.h
new file mode 100644
index 0000000..39114e7
--- /dev/null
+++ b/include/hsl/shiva/shiva_misc.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_misc SHIVA_MISC
+ * @{
+ */
+#ifndef _SHIVA_MISC_H_
+#define _SHIVA_MISC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_misc.h"
+
+ sw_error_t shiva_misc_init(a_uint32_t dev_id);
+
+#ifdef IN_MISC
+#define SHIVA_MISC_INIT(rv, dev_id) \
+ { \
+ rv = shiva_misc_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_MISC_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+ HSL_LOCAL sw_error_t
+ shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_arp_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr);
+
+ HSL_LOCAL sw_error_t
+ shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_GEN_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_port_ctrl.h b/include/hsl/shiva/shiva_port_ctrl.h
new file mode 100644
index 0000000..b97ef23
--- /dev/null
+++ b/include/hsl/shiva/shiva_port_ctrl.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL
+ * @{
+ */
+#ifndef _SHIVA_PORT_CTRL_H_
+#define _SHIVA_PORT_CTRL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_port_ctrl.h"
+
+ sw_error_t shiva_port_ctrl_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTCONTROL
+#define SHIVA_PORT_CTRL_INIT(rv, dev_id) \
+ { \
+ rv = shiva_port_ctrl_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_PORT_CTRL_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_PORT_CTRL_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_portvlan.h b/include/hsl/shiva/shiva_portvlan.h
new file mode 100644
index 0000000..c2495fc
--- /dev/null
+++ b/include/hsl/shiva/shiva_portvlan.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup shiva_port_vlan SHIVA_PORT_VLAN
+ * @{
+ */
+#ifndef _SHIVA_PORTVLAN_H_
+#define _SHIVA_PORTVLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_portvlan.h"
+
+ sw_error_t shiva_portvlan_init(a_uint32_t dev_id);
+
+#ifdef IN_PORTVLAN
+#define SHIVA_PORTVLAN_INIT(rv, dev_id) \
+ { \
+ rv = shiva_portvlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_PORTVLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+ HSL_LOCAL sw_error_t
+ shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_PORTVLAN_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_qos.h b/include/hsl/shiva/shiva_qos.h
new file mode 100644
index 0000000..096ffa5
--- /dev/null
+++ b/include/hsl/shiva/shiva_qos.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_qos SHIVA_QOS
+ * @{
+ */
+#ifndef _SHIVA_QOS_H_
+#define _SHIVA_QOS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_qos.h"
+
+ sw_error_t shiva_qos_init(a_uint32_t dev_id);
+
+#ifdef IN_QOS
+#define SHIVA_QOS_INIT(rv, dev_id) \
+ { \
+ rv = shiva_qos_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_QOS_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id,
+ fal_port_t port_id, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id,
+ fal_port_t port_id,
+ a_bool_t * enable);
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[]);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[]);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_QOS_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_rate.h b/include/hsl/shiva/shiva_rate.h
new file mode 100644
index 0000000..66a9c7d
--- /dev/null
+++ b/include/hsl/shiva/shiva_rate.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_rate SHIVA_RATE
+ * @{
+ */
+#ifndef _SHIVA_RATE_H_
+#define _SHIVA_RATE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_rate.h"
+
+ sw_error_t shiva_rate_init(a_uint32_t dev_id);
+
+#ifdef IN_RATE
+#define SHIVA_RATE_INIT(rv, dev_id) \
+ { \
+ rv = shiva_rate_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_RATE_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_RATE_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_reduced_acl.h b/include/hsl/shiva/shiva_reduced_acl.h
new file mode 100644
index 0000000..db24130
--- /dev/null
+++ b/include/hsl/shiva/shiva_reduced_acl.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SHIVA_REDUCED_ACL_H_
+#define _SHIVA_REDUCED_ACL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8]);
+
+ sw_error_t
+ shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act[3]);
+
+ sw_error_t
+ shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8]);
+
+ sw_error_t
+ shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8]);
+
+ sw_error_t
+ shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act[3]);
+
+ sw_error_t
+ shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8]);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_REDUCED_ACL_H_ */
+
diff --git a/include/hsl/shiva/shiva_reg.h b/include/hsl/shiva/shiva_reg.h
new file mode 100644
index 0000000..cc10728
--- /dev/null
+++ b/include/hsl/shiva/shiva_reg.h
@@ -0,0 +1,4066 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SHIVA_REG_H_
+#define _SHIVA_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define MAX_ENTRY_LEN 128
+
+#define HSL_RW 1
+#define HSL_RO 0
+
+
+ /* SHIVA Mask Control Register */
+#define MASK_CTL "mask"
+#define MASK_CTL_ID 0
+#define MASK_CTL_OFFSET 0x0000
+#define MASK_CTL_E_LENGTH 4
+#define MASK_CTL_E_OFFSET 0
+#define MASK_CTL_NR_E 1
+
+#define SOFT_RST "mask_rst"
+#define MASK_CTL_SOFT_RST_BOFFSET 31
+#define MASK_CTL_SOFT_RST_BLEN 1
+#define MASK_CTL_SOFT_RST_FLAG HSL_RW
+
+#define MII_CLK5_SEL "mask_clk5s"
+#define MASK_CTL_MII_CLK5_SEL_BOFFSET 21
+#define MASK_CTL_MII_CLK5_SEL_BLEN 1
+#define MASK_CTL_MII_CLK5_SEL_FLAG HSL_RW
+
+#define MII_CLK0_SEL "mask_clk0s"
+#define MASK_CTL_MII_CLK0_SEL_BOFFSET 20
+#define MASK_CTL_MII_CLK0_SEL_BLEN 1
+#define MASK_CTL_MII_CLK0_SEL_FLAG HSL_RW
+
+#define LOAD_EEPROM "mask_ldro"
+#define MASK_CTL_LOAD_EEPROM_BOFFSET 16
+#define MASK_CTL_LOAD_EEPROM_BLEN 1
+#define MASK_CTL_LOAD_EEPROM_FLAG HSL_RW
+
+#define DEVICE_ID "mask_did"
+#define MASK_CTL_DEVICE_ID_BOFFSET 8
+#define MASK_CTL_DEVICE_ID_BLEN 8
+#define MASK_CTL_DEVICE_ID_FLAG HSL_RO
+
+#define REV_ID "mask_rid"
+#define MASK_CTL_REV_ID_BOFFSET 0
+#define MASK_CTL_REV_ID_BLEN 8
+#define MASK_CTL_REV_ID_FLAG HSL_RO
+
+
+ /* SHIVA Mask Control Register */
+#define POSTRIP "postrip"
+#define POSTRIP_ID 0
+#define POSTRIP_OFFSET 0x0008
+#define POSTRIP_E_LENGTH 4
+#define POSTRIP_E_OFFSET 0
+#define POSTRIP_NR_E 1
+
+#define POWER_ON_SEL "postrip_sel"
+#define POSTRIP_POWER_ON_SEL_BOFFSET 31
+#define POSTRIP_POWER_ON_SEL_BLEN 1
+#define POSTRIP_POWER_ON_SEL_FLAG HSL_RW
+
+#define RXDELAY_S1 "postrip_rx_s1"
+#define POSTRIP_RXDELAY_S1_BOFFSET 26
+#define POSTRIP_RXDELAY_S1_BLEN 1
+#define POSTRIP_RXDELAY_S1_FLAG HSL_RW
+
+#define SPI_EN "postrip_spi"
+#define POSTRIP_SPI_EN_BOFFSET 25
+#define POSTRIP_SPI_EN_BLEN 1
+#define POSTRIP_SPI_EN_FLAG HSL_RW
+
+#define LED_OPEN_EN "postrip_led"
+#define POSTRIP_LED_OPEN_EN_BOFFSET 24
+#define POSTRIP_LED_OPEN_EN_BLEN 1
+#define POSTRIP_LED_OPEN_EN_FLAG HSL_RW
+
+#define RXDELAY_S0 "postrip_rx_s0"
+#define POSTRIP_RXDELAY_S0_BOFFSET 23
+#define POSTRIP_RXDELAY_S0_BLEN 1
+#define POSTRIP_RXDELAY_S0_FLAG HSL_RW
+
+#define TXDELAY_S1 "postrip_tx_s1"
+#define POSTRIP_TXDELAY_S1_BOFFSET 22
+#define POSTRIP_TXDELAY_S1_BLEN 1
+#define POSTRIP_TXDELAY_S1_FLAG HSL_RW
+
+#define TXDELAY_S0 "postrip_tx_s0"
+#define POSTRIP_TXDELAY_S0_BOFFSET 21
+#define POSTRIP_TXDELAY_S0_BLEN 1
+#define POSTRIP_TXDELAY_S0_FLAG HSL_RW
+
+#define LPW_EXIT "postrip_lpw_exit"
+#define POSTRIP_LPW_EXIT_BOFFSET 20
+#define POSTRIP_LPW_EXIT_BLEN 1
+#define POSTRIP_LPW_EXIT_FLAG HSL_RW
+
+#define PHY_PLL_ON "postrip_phy_pll"
+#define POSTRIP_PHY_PLL_ON_BOFFSET 19
+#define POSTRIP_PHY_PLL_ON_BLEN 1
+#define POSTRIP_PHY_PLL_ON_FLAG HSL_RW
+
+#define MAN_ENABLE "postrip_man_en"
+#define POSTRIP_MAN_ENABLE_BOFFSET 18
+#define POSTRIP_MAN_ENABLE_BLEN 1
+#define POSTRIP_MAN_ENABLE_FLAG HSL_RW
+
+#define LPW_STATE_EN "postrip_lpw_state"
+#define POSTRIP_LPW_STATE_EN_BOFFSET 17
+#define POSTRIP_LPW_STATE_EN_BLEN 1
+#define POSTRIP_LPW_STATE_EN_FLAG HSL_RW
+
+#define POWER_DOWN_HW "postrip_power_down"
+#define POSTRIP_POWER_DOWN_HW_BOFFSET 16
+#define POSTRIP_POWER_DOWN_HW_BLEN 1
+#define POSTRIP_POWER_DOWN_HW_FLAG HSL_RW
+
+#define MAC5_PHY_MODE "postrip_mac5_phy"
+#define POSTRIP_MAC5_PHY_MODE_BOFFSET 15
+#define POSTRIP_MAC5_PHY_MODE_BLEN 1
+#define POSTRIP_MAC5_PHY_MODE_FLAG HSL_RW
+
+#define MAC5_MAC_MODE "postrip_mac5_mac"
+#define POSTRIP_MAC5_MAC_MODE_BOFFSET 14
+#define POSTRIP_MAC5_MAC_MODE_BLEN 1
+#define POSTRIP_MAC5_MAC_MODE_FLAG HSL_RW
+
+#define DBG_MODE_I "postrip_dbg"
+#define POSTRIP_DBG_MODE_I_BOFFSET 13
+#define POSTRIP_DBG_MODE_I_BLEN 1
+#define POSTRIP_DBG_MODE_I_FLAG HSL_RW
+
+#define HIB_PULSE_HW "postrip_hib"
+#define POSTRIP_HIB_PULSE_HW_BOFFSET 12
+#define POSTRIP_HIB_PULSE_HW_BLEN 1
+#define POSTRIP_HIB_PULSE_HW_FLAG HSL_RW
+
+#define SEL_CLK25M "postrip_clk25"
+#define POSTRIP_SEL_CLK25M_BOFFSET 11
+#define POSTRIP_SEL_CLK25M_BLEN 1
+#define POSTRIP_SEL_CLK25M_FLAG HSL_RW
+
+#define GATE_25M_EN "postrip_gate25"
+#define POSTRIP_GATE_25M_EN_BOFFSET 10
+#define POSTRIP_GATE_25M_EN_BLEN 1
+#define POSTRIP_GATE_25M_EN_FLAG HSL_RW
+
+#define SEL_ANA_RST "postrip_sel_ana"
+#define POSTRIP_SEL_ANA_RST_BOFFSET 9
+#define POSTRIP_SEL_ANA_RST_BLEN 1
+#define POSTRIP_SEL_ANA_RST_FLAG HSL_RW
+
+#define SERDES_EN "postrip_serdes_en"
+#define POSTRIP_SERDES_EN_BOFFSET 8
+#define POSTRIP_SERDES_EN_BLEN 1
+#define POSTRIP_SERDES_EN_FLAG HSL_RW
+
+#define RGMII_TXCLK_DELAY_EN "postrip_tx_delay"
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BOFFSET 7
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_TXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RGMII_RXCLK_DELAY_EN "postrip_rx_delay"
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BOFFSET 6
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_BLEN 1
+#define POSTRIP_RGMII_RXCLK_DELAY_EN_FLAG HSL_RW
+
+#define RTL_MODE "postrip_rtl"
+#define POSTRIP_RTL_MODE_BOFFSET 5
+#define POSTRIP_RTL_MODE_BLEN 1
+#define POSTRIP_RTL_MODE_FLAG HSL_RW
+
+#define MAC0_MAC_MODE "postrip_mac0_mac"
+#define POSTRIP_MAC0_MAC_MODE_BOFFSET 4
+#define POSTRIP_MAC0_MAC_MODE_BLEN 1
+#define POSTRIP_MAC0_MAC_MODE_FLAG HSL_RW
+
+#define PHY4_RGMII_EN "postrip_phy4_rgmii"
+#define POSTRIP_PHY4_RGMII_EN_BOFFSET 3
+#define POSTRIP_PHY4_RGMII_EN_BLEN 1
+#define POSTRIP_PHY4_RGMII_EN_FLAG HSL_RW
+
+#define PHY4_GMII_EN "postrip_phy4_gmii"
+#define POSTRIP_PHY4_GMII_EN_BOFFSET 2
+#define POSTRIP_PHY4_GMII_EN_BLEN 1
+#define POSTRIP_PHY4_GMII_EN_FLAG HSL_RW
+
+#define MAC0_RGMII_EN "postrip_mac0_rgmii"
+#define POSTRIP_MAC0_RGMII_EN_BOFFSET 1
+#define POSTRIP_MAC0_RGMII_EN_BLEN 1
+#define POSTRIP_MAC0_RGMII_EN_FLAG HSL_RW
+
+#define MAC0_GMII_EN "postrip_mac0_gmii"
+#define POSTRIP_MAC0_GMII_EN_BOFFSET 0
+#define POSTRIP_MAC0_GMII_EN_BLEN 1
+#define POSTRIP_MAC0_GMII_EN_FLAG HSL_RW
+
+
+
+ /* Global Interrupt Register */
+#define GLOBAL_INT "gint"
+#define GLOBAL_INT_ID 1
+#define GLOBAL_INT_OFFSET 0x0014
+#define GLOBAL_INT_E_LENGTH 4
+#define GLOBAL_INT_E_OFFSET 0
+#define GLOBAL_INT_NR_E 1
+
+#define GLB_QM_ERR_CNT "gint_qmen"
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BOFFSET 24
+#define GLOBAL_INT_GLB_QM_ERR_CNT_BLEN 8
+#define GLOBAL_INT_GLB_QM_ERR_CNT_FLAG HSL_RO
+
+#define GLB_LOOKUP_ERR "gint_glblper"
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_GLB_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_GLB_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLB_QM_ERR "gint_glbqmer"
+#define GLOBAL_INT_GLB_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_GLB_QM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_QM_ERR_FLAG HSL_RW
+
+#define GLB_HW_INI_DONE "gint_hwid"
+#define GLOBAL_INT_GLB_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_GLB_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_GLB_HW_INI_DONE_FLAG HSL_RW
+
+#define GLB_MIB_INI "gint_mibi"
+#define GLOBAL_INT_GLB_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_GLB_MIB_INI_BLEN 1
+#define GLOBAL_INT_GLB_MIB_INI_FLAG HSL_RW
+
+#define GLB_MIB_DONE "gint_mibd"
+#define GLOBAL_INT_GLB_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_GLB_MIB_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MIB_DONE_FLAG HSL_RW
+
+#define GLB_BIST_DONE "gint_bisd"
+#define GLOBAL_INT_GLB_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_GLB_BIST_DONE_BLEN 1
+#define GLOBAL_INT_GLB_BIST_DONE_FLAG HSL_RW
+
+#define GLB_VT_MISS_VIO "gint_vtms"
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_GLB_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLB_VT_MEM_VIO "gint_vtme"
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_GLB_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_GLB_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLB_VT_DONE "gint_vtd"
+#define GLOBAL_INT_GLB_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_GLB_VT_DONE_BLEN 1
+#define GLOBAL_INT_GLB_VT_DONE_FLAG HSL_RW
+
+#define GLB_QM_INI "gint_qmin"
+#define GLOBAL_INT_GLB_QM_INI_BOFFSET 7
+#define GLOBAL_INT_GLB_QM_INI_BLEN 1
+#define GLOBAL_INT_GLB_QM_INI_FLAG HSL_RW
+
+#define GLB_AT_INI "gint_atin"
+#define GLOBAL_INT_GLB_AT_INI_BOFFSET 6
+#define GLOBAL_INT_GLB_AT_INI_BLEN 1
+#define GLOBAL_INT_GLB_AT_INI_FLAG HSL_RW
+
+#define GLB_ARL_FULL "gint_arlf"
+#define GLOBAL_INT_GLB_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_GLB_ARL_FULL_BLEN 1
+#define GLOBAL_INT_GLB_ARL_FULL_FLAG HSL_RW
+
+#define GLB_ARL_DONE "gint_arld"
+#define GLOBAL_INT_GLB_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_GLB_ARL_DONE_BLEN 1
+#define GLOBAL_INT_GLB_ARL_DONE_FLAG HSL_RW
+
+#define GLB_MDIO_DONE "gint_mdid"
+#define GLOBAL_INT_GLB_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_GLB_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_GLB_MDIO_DONE_FLAG HSL_RW
+
+#define GLB_PHY_INT "gint_phyi"
+#define GLOBAL_INT_GLB_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_GLB_PHY_INT_BLEN 1
+#define GLOBAL_INT_GLB_PHY_INT_FLAG HSL_RW
+
+#define GLB_EEPROM_ERR "gint_epei"
+#define GLOBAL_INT_GLB_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_ERR_FLAG HSL_RW
+
+#define GLB_EEPROM_INT "gint_epi"
+#define GLOBAL_INT_GLB_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_GLB_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_GLB_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global Interrupt Mask Register */
+#define GLOBAL_INT_MASK "gintm"
+#define GLOBAL_INT_MASK_ID 2
+#define GLOBAL_INT_MASK_OFFSET 0x0018
+#define GLOBAL_INT_MASK_E_LENGTH 4
+#define GLOBAL_INT_MASK_E_OFFSET 0
+#define GLOBAL_INT_MASK_NR_E 1
+
+#define GLBM_LOOP_CHECK "gintm_lc"
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BOFFSET 18
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_LOOP_CHECK_FLAG HSL_RW
+
+#define GLBM_LOOKUP_ERR "gintm_lpe"
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BOFFSET 17
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_LOOKUP_ERR_FLAG HSL_RW
+
+#define GLBM_QM_ERR "gintm_qme"
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BOFFSET 16
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_ERR_FLAG HSL_RW
+
+#define GLBM_HW_INI_DONE "gintm_hwid"
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BOFFSET 14
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_HW_INI_DONE_FLAG HSL_RW
+
+#define GLBM_MIB_INI "gintm_mibi"
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BOFFSET 13
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_INI_FLAG HSL_RW
+
+#define GLBM_MIB_DONE "gintm_mibd"
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BOFFSET 12
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MIB_DONE_FLAG HSL_RW
+
+#define GLBM_BIST_DONE "gintm_bisd"
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BOFFSET 11
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_BIST_DONE_FLAG HSL_RW
+
+#define GLBM_VT_MISS_VIO "gintm_vtms"
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BOFFSET 10
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MISS_VIO_FLAG HSL_RW
+
+#define GLBM_VT_MEM_VIO "gintm_vtme"
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BOFFSET 9
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_MEM_VIO_FLAG HSL_RW
+
+#define GLBM_VT_DONE "gintm_vtd"
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BOFFSET 8
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_VT_DONE_FLAG HSL_RW
+
+#define GLBM_QM_INI "gintm_qmin"
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BOFFSET 7
+#define GLOBAL_INT_MASK_GLBM_QM_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_QM_INI_FLAG HSL_RW
+
+#define GLBM_AT_INI "gintm_atin"
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BOFFSET 6
+#define GLOBAL_INT_MASK_GLBM_AT_INI_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_AT_INI_FLAG HSL_RW
+
+#define GLBM_ARL_FULL "gintm_arlf"
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BOFFSET 5
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_FULL_FLAG HSL_RW
+
+#define GLBM_ARL_DONE "gintm_arld"
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BOFFSET 4
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_ARL_DONE_FLAG HSL_RW
+
+#define GLBM_MDIO_DONE "gintm_mdid"
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BOFFSET 3
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_MDIO_DONE_FLAG HSL_RW
+
+#define GLBM_PHY_INT "gintm_phy"
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BOFFSET 2
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_PHY_INT_FLAG HSL_RW
+
+#define GLBM_EEPROM_ERR "gintm_epe"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BOFFSET 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_ERR_FLAG HSL_RW
+
+#define GLBM_EEPROM_INT "gintm_ep"
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BOFFSET 0
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_BLEN 1
+#define GLOBAL_INT_MASK_GLBM_EEPROM_INT_FLAG HSL_RW
+
+
+ /* Global MAC Address Register */
+#define GLOBAL_MAC_ADDR0 "gmac0"
+#define GLOBAL_MAC_ADDR0_ID 3
+#define GLOBAL_MAC_ADDR0_OFFSET 0x0020
+#define GLOBAL_MAC_ADDR0_E_LENGTH 4
+#define GLOBAL_MAC_ADDR0_E_OFFSET 0
+#define GLOBAL_MAC_ADDR0_NR_E 1
+
+#define GLB_BYTE4 "gmac_b4"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BOFFSET 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE4_FLAG HSL_RW
+
+#define GLB_BYTE5 "gmac_b5"
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BOFFSET 0
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_BLEN 8
+#define GLOBAL_MAC_ADDR0_GLB_BYTE5_FLAG HSL_RW
+
+#define GLOBAL_MAC_ADDR1 "gmac1"
+#define GLOBAL_MAC_ADDR1_ID 4
+#define GLOBAL_MAC_ADDR1_OFFSET 0x0024
+#define GLOBAL_MAC_ADDR1_E_LENGTH 4
+#define GLOBAL_MAC_ADDR1_E_OFFSET 0
+#define GLOBAL_MAC_ADDR1_NR_E 1
+
+#define GLB_BYTE0 "gmac_b0"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BOFFSET 24
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE0_FLAG HSL_RW
+
+#define GLB_BYTE1 "gmac_b1"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BOFFSET 16
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE1_FLAG HSL_RW
+
+#define GLB_BYTE2 "gmac_b2"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BOFFSET 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE2_FLAG HSL_RW
+
+#define GLB_BYTE3 "gmac_b3"
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BOFFSET 0
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_BLEN 8
+#define GLOBAL_MAC_ADDR1_GLB_BYTE3_FLAG HSL_RW
+
+
+ /* Flood Mask Register */
+#define LOOP_CHECK "loopc"
+#define LOOP_CHECK_ID 4
+#define LOOP_CHECK_OFFSET 0x0028
+#define LOOP_CHECK_E_LENGTH 4
+#define LOOP_CHECK_E_OFFSET 0
+#define LOOP_CHECK_NR_E 1
+
+#define NEW_PORT
+#define LOOP_CHECK_NEW_PORT_BOFFSET 4
+#define LOOP_CHECK_NEW_PORT_BLEN 4
+#define LOOP_CHECK_NEW_PORT_FLAG HSL_RW
+
+#define OLD_PORT
+#define LOOP_CHECK_OLD_PORT_BOFFSET 0
+#define LOOP_CHECK_OLD_PORT_BLEN 4
+#define LOOP_CHECK_OLD_PORT_FLAG HSL_RW
+
+
+ /* Flood Mask Register */
+#define FLOOD_MASK "fmask"
+#define FLOOD_MASK_ID 5
+#define FLOOD_MASK_OFFSET 0x002c
+#define FLOOD_MASK_E_LENGTH 4
+#define FLOOD_MASK_E_OFFSET 0
+#define FLOOD_MASK_NR_E 1
+
+#define BC_FLOOD_DP "fmask_bfdp"
+#define FLOOD_MASK_BC_FLOOD_DP_BOFFSET 25
+#define FLOOD_MASK_BC_FLOOD_DP_BLEN 7
+#define FLOOD_MASK_BC_FLOOD_DP_FLAG HSL_RW
+
+#define ARL_UNI_LEAKY "fmask_aulky"
+#define FLOOD_MASK_ARL_UNI_LEAKY_BOFFSET 24
+#define FLOOD_MASK_ARL_UNI_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_UNI_LEAKY_FLAG HSL_RW
+
+#define ARL_MUL_LEAKY "fmask_amlky"
+#define FLOOD_MASK_ARL_MUL_LEAKY_BOFFSET 23
+#define FLOOD_MASK_ARL_MUL_LEAKY_BLEN 1
+#define FLOOD_MASK_ARL_MUL_LEAKY_FLAG HSL_RW
+
+#define MUL_FLOOD_DP "fmask_mfdp"
+#define FLOOD_MASK_MUL_FLOOD_DP_BOFFSET 16
+#define FLOOD_MASK_MUL_FLOOD_DP_BLEN 7
+#define FLOOD_MASK_MUL_FLOOD_DP_FLAG HSL_RW
+
+#define IGMP_DP "fmask_igmpdp"
+#define FLOOD_MASK_IGMP_DP_BOFFSET 8
+#define FLOOD_MASK_IGMP_DP_BLEN 7
+#define FLOOD_MASK_IGMP_DP_FLAG HSL_RW
+
+#define UNI_FLOOD_DP "fmask_ufdp"
+#define FLOOD_MASK_UNI_FLOOD_DP_BOFFSET 0
+#define FLOOD_MASK_UNI_FLOOD_DP_BLEN 7
+#define FLOOD_MASK_UNI_FLOOD_DP_FLAG HSL_RW
+
+
+ /* Global Control Register */
+#define GLOBAL_CTL "gctl"
+#define GLOBAL_CTL_ID 5
+#define GLOBAL_CTL_OFFSET 0x0030
+#define GLOBAL_CTL_E_LENGTH 4
+#define GLOBAL_CTL_E_OFFSET 0
+#define GLOBAL_CTL_NR_E 1
+
+#define RATE_DROP_EN "gctl_rden"
+#define GLOBAL_CTL_RATE_DROP_EN_BOFFSET 29
+#define GLOBAL_CTL_RATE_DROP_EN_BLEN 1
+#define GLOBAL_CTL_RATE_DROP_EN_FLAG HSL_RW
+
+#define QM_PRI_MODE "gctl_qmpm"
+#define GLOBAL_CTL_QM_PRI_MODE_BOFFSET 28
+#define GLOBAL_CTL_QM_PRI_MODE_BLEN 1
+#define GLOBAL_CTL_QM_PRI_MODE_FLAG HSL_RW
+
+#define RATE_CRE_LIMIT "gctl_rcrl"
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BOFFSET 26
+#define GLOBAL_CTL_RATE_CRE_LIMIT_BLEN 2
+#define GLOBAL_CTL_RATE_CRE_LIMIT_FLAG HSL_RW
+
+#define RATE_TIME_SLOT "gctl_rtms"
+#define GLOBAL_CTL_RATE_TIME_SLOT_BOFFSET 24
+#define GLOBAL_CTL_RATE_TIME_SLOT_BLEN 2
+#define GLOBAL_CTL_RATE_TIME_SLOT_FLAG HSL_RW
+
+#define RELOAD_TIMER "gctl_rdtm"
+#define GLOBAL_CTL_RELOAD_TIMER_BOFFSET 20
+#define GLOBAL_CTL_RELOAD_TIMER_BLEN 4
+#define GLOBAL_CTL_RELOAD_TIMER_FLAG HSL_RW
+
+#define QM_CNT_LOCK "gctl_qmcl"
+#define GLOBAL_CTL_QM_CNT_LOCK_BOFFSET 19
+#define GLOBAL_CTL_QM_CNT_LOCK_BLEN 1
+#define GLOBAL_CTL_QM_CNT_LOCK_FLAG HSL_RO
+
+#define BROAD_DROP_EN "gctl_bden"
+#define GLOBAL_CTL_BROAD_DROP_EN_BOFFSET 18
+#define GLOBAL_CTL_BROAD_DROP_EN_BLEN 1
+#define GLOBAL_CTL_BROAD_DROP_EN_FLAG HSL_RW
+
+#define MAX_FRAME_SIZE "gctl_mfsz"
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BOFFSET 0
+#define GLOBAL_CTL_MAX_FRAME_SIZE_BLEN 14
+#define GLOBAL_CTL_MAX_FRAME_SIZE_FLAG HSL_RW
+
+
+ /* Flow Control Register */
+#define FLOW_CTL0 "fctl"
+#define FLOW_CTL0_ID 6
+#define FLOW_CTL0_OFFSET 0x0034
+#define FLOW_CTL0_E_LENGTH 4
+#define FLOW_CTL0_E_OFFSET 0
+#define FLOW_CTL0_NR_E 1
+
+#define TEST_PAUSE "fctl_tps"
+#define FLOW_CTL0_TEST_PAUSE_BOFFSET 31
+#define FLOW_CTL0_TEST_PAUSE_BLEN 1
+#define FLOW_CTL0_TEST_PAUSE_FLAG HSL_RW
+
+
+#define GOL_PAUSE_ON_THRES "fctl_gont"
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define GOL_PAUSE_OFF_THRES "fctl_gofft"
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL0_GOL_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* Flow Control1 Register */
+#define FLOW_CTL1 "fctl1"
+#define FLOW_CTL1_ID 6
+#define FLOW_CTL1_OFFSET 0x0038
+#define FLOW_CTL1_E_LENGTH 4
+#define FLOW_CTL1_E_OFFSET 0
+#define FLOW_CTL1_NR_E 1
+
+#define PORT_PAUSE_ON_THRES "fctl1_pont"
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BOFFSET 16
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_ON_THRES_FLAG HSL_RW
+
+#define PORT_PAUSE_OFF_THRES "fctl1_pofft"
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BOFFSET 0
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_BLEN 8
+#define FLOW_CTL1_PORT_PAUSE_OFF_THRES_FLAG HSL_RW
+
+
+
+
+ /* QM Control Register */
+#define QM_CTL "qmct"
+#define QM_CTL_ID 7
+#define QM_CTL_OFFSET 0x003c
+#define QM_CTL_E_LENGTH 4
+#define QM_CTL_E_OFFSET 0
+#define QM_CTL_NR_E 1
+
+#define QM_ERR_RST_EN "qmct_qeren"
+#define QM_CTL_QM_ERR_RST_EN_BOFFSET 31
+#define QM_CTL_QM_ERR_RST_EN_BLEN 1
+#define QM_CTL_QM_ERR_RST_EN_FLAG HSL_RW
+
+#define LOOKUP_ERR_RST_EN "qmct_lpesen"
+#define QM_CTL_LOOKUP_ERR_RST_EN_BOFFSET 30
+#define QM_CTL_LOOKUP_ERR_RST_EN_BLEN 1
+#define QM_CTL_LOOKUP_ERR_RST_EN_FLAG HSL_RW
+
+#define IGMP_JOIN_STATIC "qmct_igmpjs"
+#define QM_CTL_IGMP_JOIN_STATIC_BOFFSET 24
+#define QM_CTL_IGMP_JOIN_STATIC_BLEN 4
+#define QM_CTL_IGMP_JOIN_STATIC_FLAG HSL_RW
+
+#define IGMP_JOIN_LEAKY "qmct_igmpjl"
+#define QM_CTL_IGMP_JOIN_LEAKY_BOFFSET 23
+#define QM_CTL_IGMP_JOIN_LEAKY_BLEN 1
+#define QM_CTL_IGMP_JOIN_LEAKY_FLAG HSL_RW
+
+#define IGMP_CREAT_EN "qmct_igmpcrt"
+#define QM_CTL_IGMP_CREAT_EN_BOFFSET 22
+#define QM_CTL_IGMP_CREAT_EN_BLEN 1
+#define QM_CTL_IGMP_CREAT_EN_FLAG HSL_RW
+
+#define ACL_EN "qmct_aclen"
+#define QM_CTL_ACL_EN_BOFFSET 21
+#define QM_CTL_ACL_EN_BLEN 1
+#define QM_CTL_ACL_EN_FLAG HSL_RW
+
+#define PPPOE_RDT_EN "qmct_pppoerdten"
+#define QM_CTL_PPPOE_RDT_EN_BOFFSET 20
+#define QM_CTL_PPPOE_RDT_EN_BLEN 1
+#define QM_CTL_PPPOE_RDT_EN_FLAG HSL_RW
+
+#define IGMP_V3_EN "qmct_igmpv3e"
+#define QM_CTL_IGMP_V3_EN_BOFFSET 19
+#define QM_CTL_IGMP_V3_EN_BLEN 1
+#define QM_CTL_IGMP_V3_EN_FLAG HSL_RW
+
+#define IGMP_PRI_EN "qmct_igmpprie"
+#define QM_CTL_IGMP_PRI_EN_BOFFSET 18
+#define QM_CTL_IGMP_PRI_EN_BLEN 1
+#define QM_CTL_IGMP_PRI_EN_FLAG HSL_RW
+
+#define IGMP_PRI "qmct_igmppri"
+#define QM_CTL_IGMP_PRI_BOFFSET 16
+#define QM_CTL_IGMP_PRI_BLEN 2
+#define QM_CTL_IGMP_PRI_FLAG HSL_RW
+
+#define ARP_EN "qmct_arpe"
+#define QM_CTL_ARP_EN_BOFFSET 15
+#define QM_CTL_ARP_EN_BLEN 1
+#define QM_CTL_ARP_EN_FLAG HSL_RW
+
+#define ARP_CMD "qmct_arpc"
+#define QM_CTL_ARP_CMD_BOFFSET 14
+#define QM_CTL_ARP_CMD_BLEN 1
+#define QM_CTL_ARP_CMD_FLAG HSL_RW
+
+#define RIP_CPY_EN "qmct_ripcpyen"
+#define QM_CTL_RIP_CPY_EN_BOFFSET 13
+#define QM_CTL_RIP_CPY_EN_BLEN 1
+#define QM_CTL_RIP_CPY_EN_FLAG HSL_RW
+
+#define EAPOL_CMD "qmct_eapolc"
+#define QM_CTL_EAPOL_CMD_BOFFSET 12
+#define QM_CTL_EAPOL_CMD_BLEN 1
+#define QM_CTL_EAPOL_CMD_FLAG HSL_RW
+
+#define IGMP_COPY_EN "qmct_igmpcpy"
+#define QM_CTL_IGMP_COPY_EN_BOFFSET 11
+#define QM_CTL_IGMP_COPY_EN_BLEN 1
+#define QM_CTL_IGMP_COPY_EN_FLAG HSL_RW
+
+#define PPPOE_EN "qmct_pppoeen"
+#define QM_CTL_PPPOE_EN_BOFFSET 10
+#define QM_CTL_PPPOE_EN_BLEN 1
+#define QM_CTL_PPPOE_EN_FLAG HSL_RW
+
+#define QM_FUNC_TEST "qmct_qmft"
+#define QM_CTL_QM_FUNC_TEST_BOFFSET 9
+#define QM_CTL_QM_FUNC_TEST_BLEN 1
+#define QM_CTL_QM_FUNC_TEST_FLAG HSL_RW
+
+#define MS_FC_EN "qmct_msfe"
+#define QM_CTL_MS_FC_EN_BOFFSET 8
+#define QM_CTL_MS_FC_EN_BLEN 1
+#define QM_CTL_MS_FC_EN_FLAG HSL_RW
+
+#define FLOW_DROP_EN "qmct_fden"
+#define QM_CTL_FLOW_DROP_EN_BOFFSET 7
+#define QM_CTL_FLOW_DROP_EN_BLEN 1
+#define QM_CTL_FLOW_DROP_EN_FLAG HSL_RW
+
+#define MANAGE_VID_VIO_DROP_EN "qmct_mden"
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BOFFSET 6
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_BLEN 1
+#define QM_CTL_MANAGE_VID_VIO_DROP_EN_FLAG HSL_RW
+
+#define FLOW_DROP_CNT "qmct_fdcn"
+#define QM_CTL_FLOW_DROP_CNT_BOFFSET 0
+#define QM_CTL_FLOW_DROP_CNT_BLEN 6
+#define QM_CTL_FLOW_DROP_CNT_FLAG HSL_RW
+
+
+ /* Vlan Table Function Register */
+#define VLAN_TABLE_FUNC0 "vtbf0"
+#define VLAN_TABLE_FUNC0_ID 9
+#define VLAN_TABLE_FUNC0_OFFSET 0x0040
+#define VLAN_TABLE_FUNC0_E_LENGTH 4
+#define VLAN_TABLE_FUNC0_E_OFFSET 0
+#define VLAN_TABLE_FUNC0_NR_E 1
+
+#define VT_PRI_EN "vtbf_vtpen"
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BOFFSET 31
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_PRI_EN_FLAG HSL_RW
+
+#define VT_PRI "vtbf_vtpri"
+#define VLAN_TABLE_FUNC0_VT_PRI_BOFFSET 28
+#define VLAN_TABLE_FUNC0_VT_PRI_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_PRI_FLAG HSL_RW
+
+#define VLAN_ID "vtbf_vid"
+#define VLAN_TABLE_FUNC0_VLAN_ID_BOFFSET 16
+#define VLAN_TABLE_FUNC0_VLAN_ID_BLEN 12
+#define VLAN_TABLE_FUNC0_VLAN_ID_FLAG HSL_RW
+
+#define VT_PORT_NUM "vtbf_vtpn"
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BOFFSET 8
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_BLEN 4
+#define VLAN_TABLE_FUNC0_VT_PORT_NUM_FLAG HSL_RW
+
+#define VT_FULL_VIO "vtbf_vtflv"
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BOFFSET 4
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_FULL_VIO_FLAG HSL_RW
+
+#define VT_BUSY "vtbf_vtbs"
+#define VLAN_TABLE_FUNC0_VT_BUSY_BOFFSET 3
+#define VLAN_TABLE_FUNC0_VT_BUSY_BLEN 1
+#define VLAN_TABLE_FUNC0_VT_BUSY_FLAG HSL_RW
+
+#define VT_FUNC "vtbf_vtfc"
+#define VLAN_TABLE_FUNC0_VT_FUNC_BOFFSET 0
+#define VLAN_TABLE_FUNC0_VT_FUNC_BLEN 3
+#define VLAN_TABLE_FUNC0_VT_FUNC_FLAG HSL_RW
+
+#define VLAN_TABLE_FUNC1 "vtbf1"
+#define VLAN_TABLE_FUNC1_ID 10
+#define VLAN_TABLE_FUNC1_OFFSET 0x0044
+#define VLAN_TABLE_FUNC1_E_LENGTH 4
+#define VLAN_TABLE_FUNC1_E_OFFSET 0
+#define VLAN_TABLE_FUNC1_NR_E 1
+
+#define VT_VALID "vtbf_vtvd"
+#define VLAN_TABLE_FUNC1_VT_VALID_BOFFSET 11
+#define VLAN_TABLE_FUNC1_VT_VALID_BLEN 1
+#define VLAN_TABLE_FUNC1_VT_VALID_FLAG HSL_RW
+
+#define VID_MEM "vtbf_vidm"
+#define VLAN_TABLE_FUNC1_VID_MEM_BOFFSET 0
+#define VLAN_TABLE_FUNC1_VID_MEM_BLEN 7
+#define VLAN_TABLE_FUNC1_VID_MEM_FLAG HSL_RW
+
+
+ /* Address Table Function Register */
+#define ADDR_TABLE_FUNC0 "atbf0"
+#define ADDR_TABLE_FUNC0_ID 11
+#define ADDR_TABLE_FUNC0_OFFSET 0x0050
+#define ADDR_TABLE_FUNC0_E_LENGTH 4
+#define ADDR_TABLE_FUNC0_E_OFFSET 0
+#define ADDR_TABLE_FUNC0_NR_E 1
+
+#define AT_ADDR_BYTE4 "atbf_adb4"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BOFFSET 24
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE4_FLAG HSL_RW
+
+#define AT_ADDR_BYTE5 "atbf_adb5"
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BOFFSET 16
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_BLEN 8
+#define ADDR_TABLE_FUNC0_AT_ADDR_BYTE5_FLAG HSL_RW
+
+#define AT_FULL_VIO "atbf_atfv"
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BOFFSET 12
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_FULL_VIO_FLAG HSL_RW
+
+#define AT_PORT_NUM "atbf_atpn"
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BOFFSET 8
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_BLEN 4
+#define ADDR_TABLE_FUNC0_AT_PORT_NUM_FLAG HSL_RW
+
+#define FLUSH_ST_EN "atbf_fsen"
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BOFFSET 4
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_BLEN 1
+#define ADDR_TABLE_FUNC0_FLUSH_ST_EN_FLAG HSL_RW
+
+#define AT_BUSY "atbf_atbs"
+#define ADDR_TABLE_FUNC0_AT_BUSY_BOFFSET 3
+#define ADDR_TABLE_FUNC0_AT_BUSY_BLEN 1
+#define ADDR_TABLE_FUNC0_AT_BUSY_FLAG HSL_RW
+
+#define AT_FUNC "atbf_atfc"
+#define ADDR_TABLE_FUNC0_AT_FUNC_BOFFSET 0
+#define ADDR_TABLE_FUNC0_AT_FUNC_BLEN 3
+#define ADDR_TABLE_FUNC0_AT_FUNC_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC1 "atbf1"
+#define ADDR_TABLE_FUNC1_ID 12
+#define ADDR_TABLE_FUNC1_OFFSET 0x0054
+#define ADDR_TABLE_FUNC1_E_LENGTH 4
+#define ADDR_TABLE_FUNC1_E_OFFSET 0
+#define ADDR_TABLE_FUNC1_NR_E 0
+
+#define AT_ADDR_BYTE0 "atbf_adb0"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BOFFSET 24
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE0_FLAG HSL_RW
+
+#define AT_ADDR_BYTE1 "atbf_adb1"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BOFFSET 16
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE1_FLAG HSL_RW
+
+#define AT_ADDR_BYTE2 "atbf_adb2"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BOFFSET 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE2_FLAG HSL_RW
+
+#define AT_ADDR_BYTE3 "atbf_adb3"
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BOFFSET 0
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_BLEN 8
+#define ADDR_TABLE_FUNC1_AT_ADDR_BYTE3_FLAG HSL_RW
+
+#define ADDR_TABLE_FUNC2 "atbf2"
+#define ADDR_TABLE_FUNC2_ID 13
+#define ADDR_TABLE_FUNC2_OFFSET 0x0058
+#define ADDR_TABLE_FUNC2_E_LENGTH 4
+#define ADDR_TABLE_FUNC2_E_OFFSET 0
+#define ADDR_TABLE_FUNC2_NR_E 0
+
+#define COPY_TO_CPU "atbf_cpcpu"
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BOFFSET 26
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_COPY_TO_CPU_FLAG HSL_RW
+
+#define REDRCT_TO_CPU "atbf_rdcpu"
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BOFFSET 25
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_BLEN 1
+#define ADDR_TABLE_FUNC2_REDRCT_TO_CPU_FLAG HSL_RW
+
+#define LEAKY_EN "atbf_lkyen"
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BOFFSET 24
+#define ADDR_TABLE_FUNC2_LEAKY_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_LEAKY_EN_FLAG HSL_RW
+
+#define AT_STATUS "atbf_atsts"
+#define ADDR_TABLE_FUNC2_AT_STATUS_BOFFSET 16
+#define ADDR_TABLE_FUNC2_AT_STATUS_BLEN 4
+#define ADDR_TABLE_FUNC2_AT_STATUS_FLAG HSL_RW
+
+#define CLONE_EN "atbf_clone"
+#define ADDR_TABLE_FUNC2_CLONE_EN_BOFFSET 15
+#define ADDR_TABLE_FUNC2_CLONE_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_CLONE_EN_FLAG HSL_RW
+
+#define SA_DROP_EN "atbf_saden"
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BOFFSET 14
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_SA_DROP_EN_FLAG HSL_RW
+
+#define MIRROR_EN "atbf_miren"
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BOFFSET 13
+#define ADDR_TABLE_FUNC2_MIRROR_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_MIRROR_EN_FLAG HSL_RW
+
+#define AT_PRI_EN "atbf_atpen"
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BOFFSET 12
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_BLEN 1
+#define ADDR_TABLE_FUNC2_AT_PRI_EN_FLAG HSL_RW
+
+#define AT_PRI "atbf_atpri"
+#define ADDR_TABLE_FUNC2_AT_PRI_BOFFSET 10
+#define ADDR_TABLE_FUNC2_AT_PRI_BLEN 2
+#define ADDR_TABLE_FUNC2_AT_PRI_FLAG HSL_RW
+
+#define CROSS_PT "atbf_cpt"
+#define ADDR_TABLE_FUNC2_CROSS_PT_BOFFSET 8
+#define ADDR_TABLE_FUNC2_CROSS_PT_BLEN 1
+#define ADDR_TABLE_FUNC2_CROSS_PT_FLAG HSL_RW
+
+#define DES_PORT "atbf_desp"
+#define ADDR_TABLE_FUNC2_DES_PORT_BOFFSET 0
+#define ADDR_TABLE_FUNC2_DES_PORT_BLEN 7
+#define ADDR_TABLE_FUNC2_DES_PORT_FLAG HSL_RW
+
+
+ /* FDB entry Register0 */
+#define FDB_TABLE_FUNC0 "fdb0"
+#define FDB_TABLE_FUNC0_ID 11
+#define FDB_TABLE_FUNC0_OFFSET 0x30000
+#define FDB_TABLE_FUNC0_E_LENGTH 4
+#define FDB_TABLE_FUNC0_E_OFFSET 0
+#define FDB_TABLE_FUNC0_NR_E 1
+
+#define FDB_ADDR_BYTE2
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BOFFSET 24
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_BLEN 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE2_FLAG HSL_RW
+
+#define FDB_ADDR_BYTE3
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BOFFSET 16
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_BLEN 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE3_FLAG HSL_RW
+
+#define FDB_ADDR_BYTE4
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BOFFSET 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_BLEN 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE4_FLAG HSL_RW
+
+#define FDB_ADDR_BYTE5
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BOFFSET 0
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_BLEN 8
+#define FDB_TABLE_FUNC0_FDB_ADDR_BYTE5_FLAG HSL_RW
+
+
+ /* FDB entry Register1 */
+#define FDB_TABLE_FUNC1 "fdb1"
+#define FDB_TABLE_FUNC1_ID 11
+#define FDB_TABLE_FUNC1_OFFSET 0x30004
+#define FDB_TABLE_FUNC1_E_LENGTH 4
+#define FDB_TABLE_FUNC1_E_OFFSET 0
+#define FDB_TABLE_FUNC1_NR_E 1
+
+#define FDB_MACCLONE_EN
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BOFFSET 31
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_BLEN 1
+#define FDB_TABLE_FUNC1_FDB_MACCLONE_EN_FLAG HSL_RW
+
+#define FDB_SADROP_EN
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BOFFSET 30
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_BLEN 1
+#define FDB_TABLE_FUNC1_FDB_SADROP_EN_FLAG HSL_RW
+
+#define FDB_MIRROR_EN
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BOFFSET 29
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_BLEN 1
+#define FDB_TABLE_FUNC1_FDB_MIRROR_EN_FLAG HSL_RW
+
+#define FDB_PRIORITY_EN
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BOFFSET 28
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_BLEN 1
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_EN_FLAG HSL_RW
+
+#define FDB_PRIORITY
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_BOFFSET 26
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_BLEN 2
+#define FDB_TABLE_FUNC1_FDB_PRIORITY_FLAG HSL_RW
+
+#define FDB_CROSS_STATE
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BOFFSET 24
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_BLEN 1
+#define FDB_TABLE_FUNC1_FDB_CROSS_STATE_FLAG HSL_RW
+
+#define FDB_DES_PORT
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_BOFFSET 16
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_BLEN 7
+#define FDB_TABLE_FUNC1_FDB_DES_PORT_FLAG HSL_RW
+
+#define FDB_ADDR_BYTE0
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BOFFSET 8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_BLEN 8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE0_FLAG HSL_RW
+
+#define FDB_ADDR_BYTE1
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BOFFSET 0
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_BLEN 8
+#define FDB_TABLE_FUNC1_FDB_ADDR_BYTE1_FLAG HSL_RW
+
+
+ /* FDB entry Register2 */
+#define FDB_TABLE_FUNC2 "fdb2"
+#define FDB_TABLE_FUNC2_ID 11
+#define FDB_TABLE_FUNC2_OFFSET 0x30008
+#define FDB_TABLE_FUNC2_E_LENGTH 4
+#define FDB_TABLE_FUNC2_E_OFFSET 0
+#define FDB_TABLE_FUNC2_NR_E 1
+
+#define FDB_CPYCPU_EN
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BOFFSET 6
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_BLEN 1
+#define FDB_TABLE_FUNC2_FDB_CPYCPU_EN_FLAG HSL_RW
+
+#define FDB_RDTCPU_EN
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BOFFSET 5
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_BLEN 1
+#define FDB_TABLE_FUNC2_FDB_RDTCPU_EN_FLAG HSL_RW
+
+#define FDB_LEANKY_EN
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BOFFSET 4
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_BLEN 1
+#define FDB_TABLE_FUNC2_FDB_LEANKY_EN_FLAG HSL_RW
+
+#define FDB_STATUS
+#define FDB_TABLE_FUNC2_FDB_STATUS_BOFFSET 0
+#define FDB_TABLE_FUNC2_FDB_STATUS_BLEN 4
+#define FDB_TABLE_FUNC2_FDB_STATUS_FLAG HSL_RW
+
+
+ /* Address Table Control Register */
+#define ADDR_TABLE_CTL "atbc"
+#define ADDR_TABLE_CTL_ID 14
+#define ADDR_TABLE_CTL_OFFSET 0x005C
+#define ADDR_TABLE_CTL_E_LENGTH 4
+#define ADDR_TABLE_CTL_E_OFFSET 0
+#define ADDR_TABLE_CTL_NR_E 1
+
+#define LOOP_CHK_TIME "atbc_lctime"
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BOFFSET 24
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_BLEN 3
+#define ADDR_TABLE_CTL_LOOP_CHK_TIME_FLAG HSL_RW
+
+#define RESVID_DROP "atbc_rviddrop"
+#define ADDR_TABLE_CTL_RESVID_DROP_BOFFSET 22
+#define ADDR_TABLE_CTL_RESVID_DROP_BLEN 1
+#define ADDR_TABLE_CTL_RESVID_DROP_FLAG HSL_RW
+
+#define STAG_MODE "atbc_stag"
+#define ADDR_TABLE_CTL_STAG_MODE_BOFFSET 21
+#define ADDR_TABLE_CTL_STAG_MODE_BLEN 1
+#define ADDR_TABLE_CTL_STAG_MODE_FLAG HSL_RW
+
+#define ARL_INI_EN "atbc_arlie"
+#define ADDR_TABLE_CTL_ARL_INI_EN_BOFFSET 19
+#define ADDR_TABLE_CTL_ARL_INI_EN_BLEN 1
+#define ADDR_TABLE_CTL_ARL_INI_EN_FLAG HSL_RW
+
+#define LEARN_CHANGE_EN "atbc_lcen"
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BOFFSET 18
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_LEARN_CHANGE_EN_FLAG HSL_RW
+
+#define AGE_EN "atbc_agee"
+#define ADDR_TABLE_CTL_AGE_EN_BOFFSET 17
+#define ADDR_TABLE_CTL_AGE_EN_BLEN 1
+#define ADDR_TABLE_CTL_AGE_EN_FLAG HSL_RW
+
+#define AGE_TIME "atbc_aget"
+#define ADDR_TABLE_CTL_AGE_TIME_BOFFSET 0
+#define ADDR_TABLE_CTL_AGE_TIME_BLEN 16
+#define ADDR_TABLE_CTL_AGE_TIME_FLAG HSL_RW
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING "imap"
+#define IP_PRI_MAPPING_ID 15
+#define IP_PRI_MAPPING_OFFSET 0x0060
+#define IP_PRI_MAPPING_E_LENGTH 4
+#define IP_PRI_MAPPING_E_OFFSET 0
+#define IP_PRI_MAPPING_NR_E 1
+
+
+ /* IP Priority Mapping Register */
+#define IP_PRI_MAPPING0 "imap0"
+#define IP_PRI_MAPPING0_ID 15
+#define IP_PRI_MAPPING0_OFFSET 0x0060
+#define IP_PRI_MAPPING0_E_LENGTH 4
+#define IP_PRI_MAPPING0_E_OFFSET 0
+#define IP_PRI_MAPPING0_NR_E 0
+
+#define IP_0X3C "imap_ip3c"
+#define IP_PRI_MAPPING0_IP_0X3C_BOFFSET 30
+#define IP_PRI_MAPPING0_IP_0X3C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X3C_FLAG HSL_RW
+
+#define IP_0X38 "imap_ip38"
+#define IP_PRI_MAPPING0_IP_0X38_BOFFSET 28
+#define IP_PRI_MAPPING0_IP_0X38_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X38_FLAG HSL_RW
+
+#define IP_0X34 "imap_ip34"
+#define IP_PRI_MAPPING0_IP_0X34_BOFFSET 26
+#define IP_PRI_MAPPING0_IP_0X34_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X34_FLAG HSL_RW
+
+#define IP_0X30 "imap_ip30"
+#define IP_PRI_MAPPING0_IP_0X30_BOFFSET 24
+#define IP_PRI_MAPPING0_IP_0X30_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X30_FLAG HSL_RW
+
+#define IP_0X2C "imap_ip2c"
+#define IP_PRI_MAPPING0_IP_0X2C_BOFFSET 22
+#define IP_PRI_MAPPING0_IP_0X2C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X2C_FLAG HSL_RW
+
+#define IP_0X28 "imap_ip28"
+#define IP_PRI_MAPPING0_IP_0X28_BOFFSET 20
+#define IP_PRI_MAPPING0_IP_0X28_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X28_FLAG HSL_RW
+
+#define IP_0X24 "imap_ip24"
+#define IP_PRI_MAPPING0_IP_0X24_BOFFSET 18
+#define IP_PRI_MAPPING0_IP_0X24_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X24_FLAG HSL_RW
+
+#define IP_0X20 "imap_ip20"
+#define IP_PRI_MAPPING0_IP_0X20_BOFFSET 16
+#define IP_PRI_MAPPING0_IP_0X20_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X20_FLAG HSL_RW
+
+#define IP_0X1C "imap_ip1c"
+#define IP_PRI_MAPPING0_IP_0X1C_BOFFSET 14
+#define IP_PRI_MAPPING0_IP_0X1C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X1C_FLAG HSL_RW
+
+#define IP_0X18 "imap_ip18"
+#define IP_PRI_MAPPING0_IP_0X18_BOFFSET 12
+#define IP_PRI_MAPPING0_IP_0X18_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X18_FLAG HSL_RW
+
+#define IP_0X14 "imap_ip14"
+#define IP_PRI_MAPPING0_IP_0X14_BOFFSET 10
+#define IP_PRI_MAPPING0_IP_0X14_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X14_FLAG HSL_RW
+
+#define IP_0X10 "imap_ip10"
+#define IP_PRI_MAPPING0_IP_0X10_BOFFSET 8
+#define IP_PRI_MAPPING0_IP_0X10_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X10_FLAG HSL_RW
+
+#define IP_0X0C "imap_ip0c"
+#define IP_PRI_MAPPING0_IP_0X0C_BOFFSET 6
+#define IP_PRI_MAPPING0_IP_0X0C_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X0C_FLAG HSL_RW
+
+#define IP_0X08 "imap_ip08"
+#define IP_PRI_MAPPING0_IP_0X08_BOFFSET 4
+#define IP_PRI_MAPPING0_IP_0X08_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X08_FLAG HSL_RW
+
+#define IP_0X04 "imap_ip04"
+#define IP_PRI_MAPPING0_IP_0X04_BOFFSET 2
+#define IP_PRI_MAPPING0_IP_0X04_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X04_FLAG HSL_RW
+
+#define IP_0X00 "imap_ip00"
+#define IP_PRI_MAPPING0_IP_0X00_BOFFSET 0
+#define IP_PRI_MAPPING0_IP_0X00_BLEN 2
+#define IP_PRI_MAPPING0_IP_0X00_FLAG HSL_RW
+
+#define IP_PRI_MAPPING1 "imap1"
+#define IP_PRI_MAPPING1_ID 16
+#define IP_PRI_MAPPING1_OFFSET 0x0064
+#define IP_PRI_MAPPING1_E_LENGTH 4
+#define IP_PRI_MAPPING1_E_OFFSET 0
+#define IP_PRI_MAPPING1_NR_E 0
+
+#define IP_0X7C "imap_ip7c"
+#define IP_PRI_MAPPING1_IP_0X7C_BOFFSET 30
+#define IP_PRI_MAPPING1_IP_0X7C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X7C_FLAG HSL_RW
+
+#define IP_0X78 "imap_ip78"
+#define IP_PRI_MAPPING1_IP_0X78_BOFFSET 28
+#define IP_PRI_MAPPING1_IP_0X78_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X78_FLAG HSL_RW
+
+#define IP_0X74 "imap_ip74"
+#define IP_PRI_MAPPING1_IP_0X74_BOFFSET 26
+#define IP_PRI_MAPPING1_IP_0X74_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X74_FLAG HSL_RW
+
+#define IP_0X70 "imap_ip70"
+#define IP_PRI_MAPPING1_IP_0X70_BOFFSET 24
+#define IP_PRI_MAPPING1_IP_0X70_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X70_FLAG HSL_RW
+
+#define IP_0X6C "imap_ip6c"
+#define IP_PRI_MAPPING1_IP_0X6C_BOFFSET 22
+#define IP_PRI_MAPPING1_IP_0X6C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X6C_FLAG HSL_RW
+
+#define IP_0X68 "imap_ip68"
+#define IP_PRI_MAPPING1_IP_0X68_BOFFSET 20
+#define IP_PRI_MAPPING1_IP_0X68_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X68_FLAG HSL_RW
+
+#define IP_0X64 "imap_ip64"
+#define IP_PRI_MAPPING1_IP_0X64_BOFFSET 18
+#define IP_PRI_MAPPING1_IP_0X64_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X64_FLAG HSL_RW
+
+#define IP_0X60 "imap_ip60"
+#define IP_PRI_MAPPING1_IP_0X60_BOFFSET 16
+#define IP_PRI_MAPPING1_IP_0X60_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X60_FLAG HSL_RW
+
+#define IP_0X5C "imap_ip5c"
+#define IP_PRI_MAPPING1_IP_0X5C_BOFFSET 14
+#define IP_PRI_MAPPING1_IP_0X5C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X5C_FLAG HSL_RW
+
+#define IP_0X58 "imap_ip58"
+#define IP_PRI_MAPPING1_IP_0X58_BOFFSET 12
+#define IP_PRI_MAPPING1_IP_0X58_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X58_FLAG HSL_RW
+
+#define IP_0X54 "imap_ip54"
+#define IP_PRI_MAPPING1_IP_0X54_BOFFSET 10
+#define IP_PRI_MAPPING1_IP_0X54_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X54_FLAG HSL_RW
+
+#define IP_0X50 "imap_ip50"
+#define IP_PRI_MAPPING1_IP_0X50_BOFFSET 8
+#define IP_PRI_MAPPING1_IP_0X50_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X50_FLAG HSL_RW
+
+#define IP_0X4C "imap_ip4c"
+#define IP_PRI_MAPPING1_IP_0X4C_BOFFSET 6
+#define IP_PRI_MAPPING1_IP_0X4C_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X4C_FLAG HSL_RW
+
+#define IP_0X48 "imap_ip48"
+#define IP_PRI_MAPPING1_IP_0X48_BOFFSET 4
+#define IP_PRI_MAPPING1_IP_0X48_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X48_FLAG HSL_RW
+
+#define IP_0X44 "imap_ip44"
+#define IP_PRI_MAPPING1_IP_0X44_BOFFSET 2
+#define IP_PRI_MAPPING1_IP_0X44_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X44_FLAG HSL_RW
+
+#define IP_0X40 "imap_ip40"
+#define IP_PRI_MAPPING1_IP_0X40_BOFFSET 0
+#define IP_PRI_MAPPING1_IP_0X40_BLEN 2
+#define IP_PRI_MAPPING1_IP_0X40_FLAG HSL_RW
+
+
+#define IP_PRI_MAPPING2 "imap2"
+#define IP_PRI_MAPPING2_ID 17
+#define IP_PRI_MAPPING2_OFFSET 0x0068
+#define IP_PRI_MAPPING2_E_LENGTH 4
+#define IP_PRI_MAPPING2_E_OFFSET 0
+#define IP_PRI_MAPPING2_NR_E 0
+
+#define IP_0XBC "imap_ipbc"
+#define IP_PRI_MAPPING2_IP_0XBC_BOFFSET 30
+#define IP_PRI_MAPPING2_IP_0XBC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XBC_FLAG HSL_RW
+
+#define IP_0XB8 "imap_ipb8"
+#define IP_PRI_MAPPING2_IP_0XB8_BOFFSET 28
+#define IP_PRI_MAPPING2_IP_0XB8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB8_FLAG HSL_RW
+
+#define IP_0XB4 "imap_ipb4"
+#define IP_PRI_MAPPING2_IP_0XB4_BOFFSET 26
+#define IP_PRI_MAPPING2_IP_0XB4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB4_FLAG HSL_RW
+
+#define IP_0XB0 "imap_ipb0"
+#define IP_PRI_MAPPING2_IP_0XB0_BOFFSET 24
+#define IP_PRI_MAPPING2_IP_0XB0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XB0_FLAG HSL_RW
+
+#define IP_0XAC "imap_ipac"
+#define IP_PRI_MAPPING2_IP_0XAC_BOFFSET 22
+#define IP_PRI_MAPPING2_IP_0XAC_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XAC_FLAG HSL_RW
+
+#define IP_0XA8 "imap_ipa8"
+#define IP_PRI_MAPPING2_IP_0XA8_BOFFSET 20
+#define IP_PRI_MAPPING2_IP_0XA8_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA8_FLAG HSL_RW
+
+#define IP_0XA4 "imap_ipa4"
+#define IP_PRI_MAPPING2_IP_0XA4_BOFFSET 18
+#define IP_PRI_MAPPING2_IP_0XA4_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA4_FLAG HSL_RW
+
+#define IP_0XA0 "imap_ipa0"
+#define IP_PRI_MAPPING2_IP_0XA0_BOFFSET 16
+#define IP_PRI_MAPPING2_IP_0XA0_BLEN 2
+#define IP_PRI_MAPPING2_IP_0XA0_FLAG HSL_RW
+
+#define IP_0X9C "imap_ip9c"
+#define IP_PRI_MAPPING2_IP_0X9C_BOFFSET 14
+#define IP_PRI_MAPPING2_IP_0X9C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X9C_FLAG HSL_RW
+
+#define IP_0X98 "imap_ip98"
+#define IP_PRI_MAPPING2_IP_0X98_BOFFSET 12
+#define IP_PRI_MAPPING2_IP_0X98_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X98_FLAG HSL_RW
+
+#define IP_0X94 "imap_ip94"
+#define IP_PRI_MAPPING2_IP_0X94_BOFFSET 10
+#define IP_PRI_MAPPING2_IP_0X94_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X94_FLAG HSL_RW
+
+#define IP_0X90 "imap_ip90"
+#define IP_PRI_MAPPING2_IP_0X90_BOFFSET 8
+#define IP_PRI_MAPPING2_IP_0X90_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X90_FLAG HSL_RW
+
+#define IP_0X8C "imap_ip8c"
+#define IP_PRI_MAPPING2_IP_0X8C_BOFFSET 6
+#define IP_PRI_MAPPING2_IP_0X8C_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X8C_FLAG HSL_RW
+
+#define IP_0X88 "imap_ip88"
+#define IP_PRI_MAPPING2_IP_0X88_BOFFSET 4
+#define IP_PRI_MAPPING2_IP_0X88_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X88_FLAG HSL_RW
+
+#define IP_0X84 "imap_ip84"
+#define IP_PRI_MAPPING2_IP_0X84_BOFFSET 2
+#define IP_PRI_MAPPING2_IP_0X84_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X84_FLAG HSL_RW
+
+#define IP_0X80 "imap_ip80"
+#define IP_PRI_MAPPING2_IP_0X80_BOFFSET 0
+#define IP_PRI_MAPPING2_IP_0X80_BLEN 2
+#define IP_PRI_MAPPING2_IP_0X80_FLAG HSL_RW
+
+#define IP_PRI_MAPPING3 "imap3"
+#define IP_PRI_MAPPING3_ID 18
+#define IP_PRI_MAPPING3_OFFSET 0x006C
+#define IP_PRI_MAPPING3_E_LENGTH 4
+#define IP_PRI_MAPPING3_E_OFFSET 0
+#define IP_PRI_MAPPING3_NR_E 0
+
+#define IP_0XFC "imap_ipfc"
+#define IP_PRI_MAPPING3_IP_0XFC_BOFFSET 30
+#define IP_PRI_MAPPING3_IP_0XFC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XFC_FLAG HSL_RW
+
+#define IP_0XF8 "imap_ipf8"
+#define IP_PRI_MAPPING3_IP_0XF8_BOFFSET 28
+#define IP_PRI_MAPPING3_IP_0XF8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF8_FLAG HSL_RW
+
+#define IP_0XF4 "imap_ipf4"
+#define IP_PRI_MAPPING3_IP_0XF4_BOFFSET 26
+#define IP_PRI_MAPPING3_IP_0XF4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF4_FLAG HSL_RW
+
+#define IP_0XF0 "imap_ipf0"
+#define IP_PRI_MAPPING3_IP_0XF0_BOFFSET 24
+#define IP_PRI_MAPPING3_IP_0XF0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XF0_FLAG HSL_RW
+
+#define IP_0XEC "imap_ipec"
+#define IP_PRI_MAPPING3_IP_0XEC_BOFFSET 22
+#define IP_PRI_MAPPING3_IP_0XEC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XEC_FLAG HSL_RW
+
+#define IP_0XE8 "imap_ipe8"
+#define IP_PRI_MAPPING3_IP_0XE8_BOFFSET 20
+#define IP_PRI_MAPPING3_IP_0XE8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE8_FLAG HSL_RW
+
+#define IP_0XE4 "imap_ipe4"
+#define IP_PRI_MAPPING3_IP_0XE4_BOFFSET 18
+#define IP_PRI_MAPPING3_IP_0XE4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE4_FLAG HSL_RW
+
+#define IP_0XE0 "imap_ipe0"
+#define IP_PRI_MAPPING3_IP_0XE0_BOFFSET 16
+#define IP_PRI_MAPPING3_IP_0XE0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XE0_FLAG HSL_RW
+
+#define IP_0XDC "imap_ipdc"
+#define IP_PRI_MAPPING3_IP_0XDC_BOFFSET 14
+#define IP_PRI_MAPPING3_IP_0XDC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XDC_FLAG HSL_RW
+
+#define IP_0XD8 "imap_ipd8"
+#define IP_PRI_MAPPING3_IP_0XD8_BOFFSET 12
+#define IP_PRI_MAPPING3_IP_0XD8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD8_FLAG HSL_RW
+
+#define IP_0XD4 "imap_ipd4"
+#define IP_PRI_MAPPING3_IP_0XD4_BOFFSET 10
+#define IP_PRI_MAPPING3_IP_0XD4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD4_FLAG HSL_RW
+
+#define IP_0XD0 "imap_ipd0"
+#define IP_PRI_MAPPING3_IP_0XD0_BOFFSET 8
+#define IP_PRI_MAPPING3_IP_0XD0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XD0_FLAG HSL_RW
+
+#define IP_0XCC "imap_ipcc"
+#define IP_PRI_MAPPING3_IP_0XCC_BOFFSET 6
+#define IP_PRI_MAPPING3_IP_0XCC_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XCC_FLAG HSL_RW
+
+#define IP_0XC8 "imap_ipc8"
+#define IP_PRI_MAPPING3_IP_0XC8_BOFFSET 4
+#define IP_PRI_MAPPING3_IP_0XC8_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC8_FLAG HSL_RW
+
+#define IP_0XC4 "imap_ipc4"
+#define IP_PRI_MAPPING3_IP_0XC4_BOFFSET 2
+#define IP_PRI_MAPPING3_IP_0XC4_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC4_FLAG HSL_RW
+
+#define IP_0XC0 "imap_ipc0"
+#define IP_PRI_MAPPING3_IP_0XC0_BOFFSET 0
+#define IP_PRI_MAPPING3_IP_0XC0_BLEN 2
+#define IP_PRI_MAPPING3_IP_0XC0_FLAG HSL_RW
+
+
+ /* Tag Priority Mapping Register */
+#define TAG_PRI_MAPPING "tpmap"
+#define TAG_PRI_MAPPING_ID 19
+#define TAG_PRI_MAPPING_OFFSET 0x0070
+#define TAG_PRI_MAPPING_E_LENGTH 4
+#define TAG_PRI_MAPPING_E_OFFSET 0
+#define TAG_PRI_MAPPING_NR_E 1
+
+#define TAG_0X07 "tpmap_tg07"
+#define TAG_PRI_MAPPING_TAG_0X07_BOFFSET 14
+#define TAG_PRI_MAPPING_TAG_0X07_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X07_FLAG HSL_RW
+
+#define TAG_0X06 "tpmap_tg06"
+#define TAG_PRI_MAPPING_TAG_0X06_BOFFSET 12
+#define TAG_PRI_MAPPING_TAG_0X06_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X06_FLAG HSL_RW
+
+#define TAG_0X05 "tpmap_tg05"
+#define TAG_PRI_MAPPING_TAG_0X05_BOFFSET 10
+#define TAG_PRI_MAPPING_TAG_0X05_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X05_FLAG HSL_RW
+
+#define TAG_0X04 "tpmap_tg04"
+#define TAG_PRI_MAPPING_TAG_0X04_BOFFSET 8
+#define TAG_PRI_MAPPING_TAG_0X04_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X04_FLAG HSL_RW
+
+#define TAG_0X03 "tpmap_tg03"
+#define TAG_PRI_MAPPING_TAG_0X03_BOFFSET 6
+#define TAG_PRI_MAPPING_TAG_0X03_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X03_FLAG HSL_RW
+
+#define TAG_0X02 "tpmap_tg02"
+#define TAG_PRI_MAPPING_TAG_0X02_BOFFSET 4
+#define TAG_PRI_MAPPING_TAG_0X02_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X02_FLAG HSL_RW
+
+#define TAG_0X01 "tpmap_tg01"
+#define TAG_PRI_MAPPING_TAG_0X01_BOFFSET 2
+#define TAG_PRI_MAPPING_TAG_0X01_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X01_FLAG HSL_RW
+
+#define TAG_0X00 "tpmap_tg00"
+#define TAG_PRI_MAPPING_TAG_0X00_BOFFSET 0
+#define TAG_PRI_MAPPING_TAG_0X00_BLEN 2
+#define TAG_PRI_MAPPING_TAG_0X00_FLAG HSL_RW
+
+
+ /* Service tag Register */
+#define SERVICE_TAG "servicetag"
+#define SERVICE_TAG_ID 20
+#define SERVICE_TAG_OFFSET 0x0074
+#define SERVICE_TAG_E_LENGTH 4
+#define SERVICE_TAG_E_OFFSET 0
+#define SERVICE_TAG_NR_E 1
+
+#define TAG_VALUE "servicetag_val"
+#define SERVICE_TAG_TAG_VALUE_BOFFSET 0
+#define SERVICE_TAG_TAG_VALUE_BLEN 16
+#define SERVICE_TAG_TAG_VALUE_FLAG HSL_RW
+
+
+ /* Cpu Port Register */
+#define CPU_PORT "cpup"
+#define CPU_PORT_ID 20
+#define CPU_PORT_OFFSET 0x0078
+#define CPU_PORT_E_LENGTH 4
+#define CPU_PORT_E_OFFSET 0
+#define CPU_PORT_NR_E 0
+
+#define CPU_PORT_EN "cpup_cpupe"
+#define CPU_PORT_CPU_PORT_EN_BOFFSET 8
+#define CPU_PORT_CPU_PORT_EN_BLEN 1
+#define CPU_PORT_CPU_PORT_EN_FLAG HSL_RW
+
+#define MIRROR_PORT_NUM "cpup_mirpn"
+#define CPU_PORT_MIRROR_PORT_NUM_BOFFSET 4
+#define CPU_PORT_MIRROR_PORT_NUM_BLEN 4
+#define CPU_PORT_MIRROR_PORT_NUM_FLAG HSL_RW
+
+
+ /* MIB Function Register */
+#define MIB_FUNC "mibfunc"
+#define MIB_FUNC_ID 21
+#define MIB_FUNC_OFFSET 0x0080
+#define MIB_FUNC_E_LENGTH 4
+#define MIB_FUNC_E_OFFSET 0
+#define MIB_FUNC_NR_E 1
+
+#define MAC_CRC_EN "mibfunc_crcen"
+#define MIB_FUNC_MAC_CRC_EN_BOFFSET 31
+#define MIB_FUNC_MAC_CRC_EN_BLEN 1
+#define MIB_FUNC_MAC_CRC_EN_FLAG HSL_RW
+
+#define MIB_EN "mib_en"
+#define MIB_FUNC_MIB_EN_BOFFSET 30
+#define MIB_FUNC_MIB_EN_BLEN 1
+#define MIB_FUNC_MIB_EN_FLAG HSL_RW
+
+#define MIB_FUN "mibfunc_mibf"
+#define MIB_FUNC_MIB_FUN_BOFFSET 24
+#define MIB_FUNC_MIB_FUN_BLEN 3
+#define MIB_FUNC_MIB_FUN_FLAG HSL_RW
+
+#define MIB_BUSY "mibfunc_mibb"
+#define MIB_FUNC_MIB_BUSY_BOFFSET 17
+#define MIB_FUNC_MIB_BUSY_BLEN 1
+#define MIB_FUNC_MIB_BUSY_FLAG HSL_RW
+
+#define MIB_AT_HALF_EN "mibfunc_mibhe"
+#define MIB_FUNC_MIB_AT_HALF_EN_BOFFSET 16
+#define MIB_FUNC_MIB_AT_HALF_EN_BLEN 1
+#define MIB_FUNC_MIB_AT_HALF_EN_FLAG HSL_RW
+
+#define MIB_TIMER "mibfunc_mibt"
+#define MIB_FUNC_MIB_TIMER_BOFFSET 0
+#define MIB_FUNC_MIB_TIMER_BLEN 16
+#define MIB_FUNC_MIB_TIMER_FLAG HSL_RW
+
+
+ /* Mdio control Register */
+#define MDIO_CTRL "mctrl"
+#define MDIO_CTRL_ID 24
+#define MDIO_CTRL_OFFSET 0x0098
+#define MDIO_CTRL_E_LENGTH 4
+#define MDIO_CTRL_E_OFFSET 0
+#define MDIO_CTRL_NR_E 1
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define MSTER_EN "mctrl_msteren"
+#define MDIO_CTRL_MSTER_EN_BOFFSET 30
+#define MDIO_CTRL_MSTER_EN_BLEN 1
+#define MDIO_CTRL_MSTER_EN_FLAG HSL_RW
+
+#define CMD "mctrl_cmd"
+#define MDIO_CTRL_CMD_BOFFSET 27
+#define MDIO_CTRL_CMD_BLEN 1
+#define MDIO_CTRL_CMD_FLAG HSL_RW
+
+#define SUP_PRE "mctrl_spre"
+#define MDIO_CTRL_SUP_PRE_BOFFSET 26
+#define MDIO_CTRL_SUP_PRE_BLEN 1
+#define MDIO_CTRL_SUP_PRE_FLAG HSL_RW
+
+#define PHY_ADDR "mctrl_phyaddr"
+#define MDIO_CTRL_PHY_ADDR_BOFFSET 21
+#define MDIO_CTRL_PHY_ADDR_BLEN 5
+#define MDIO_CTRL_PHY_ADDR_FLAG HSL_RW
+
+#define REG_ADDR "mctrl_regaddr"
+#define MDIO_CTRL_REG_ADDR_BOFFSET 16
+#define MDIO_CTRL_REG_ADDR_BLEN 5
+#define MDIO_CTRL_REG_ADDR_FLAG HSL_RW
+
+#define DATA "mctrl_data"
+#define MDIO_CTRL_DATA_BOFFSET 0
+#define MDIO_CTRL_DATA_BLEN 16
+#define MDIO_CTRL_DATA_FLAG HSL_RW
+
+
+
+
+ /* BIST control Register */
+#define BIST_CTRL "bctrl"
+#define BIST_CTRL_ID 24
+#define BIST_CTRL_OFFSET 0x00a0
+#define BIST_CTRL_E_LENGTH 4
+#define BIST_CTRL_E_OFFSET 0
+#define BIST_CTRL_NR_E 1
+
+#define BIST_BUSY "bctrl_bb"
+#define BIST_CTRL_BIST_BUSY_BOFFSET 31
+#define BIST_CTRL_BIST_BUSY_BLEN 1
+#define BIST_CTRL_BIST_BUSY_FLAG HSL_RW
+
+#define ONE_ERR "bctrl_oe"
+#define BIST_CTRL_ONE_ERR_BOFFSET 30
+#define BIST_CTRL_ONE_ERR_BLEN 1
+#define BIST_CTRL_ONE_ERR_FLAG HSL_RO
+
+#define ERR_MEM "bctrl_em"
+#define BIST_CTRL_ERR_MEM_BOFFSET 24
+#define BIST_CTRL_ERR_MEM_BLEN 4
+#define BIST_CTRL_ERR_MEM_FLAG HSL_RO
+
+#define PTN_EN2 "bctrl_pe2"
+#define BIST_CTRL_PTN_EN2_BOFFSET 22
+#define BIST_CTRL_PTN_EN2_BLEN 1
+#define BIST_CTRL_PTN_EN2_FLAG HSL_RW
+
+#define PTN_EN1 "bctrl_pe1"
+#define BIST_CTRL_PTN_EN1_BOFFSET 21
+#define BIST_CTRL_PTN_EN1_BLEN 1
+#define BIST_CTRL_PTN_EN1_FLAG HSL_RW
+
+#define PTN_EN0 "bctrl_pe0"
+#define BIST_CTRL_PTN_EN0_BOFFSET 20
+#define BIST_CTRL_PTN_EN0_BLEN 1
+#define BIST_CTRL_PTN_EN0_FLAG HSL_RW
+
+#define ERR_PTN "bctrl_ep"
+#define BIST_CTRL_ERR_PTN_BOFFSET 16
+#define BIST_CTRL_ERR_PTN_BLEN 2
+#define BIST_CTRL_ERR_PTN_FLAG HSL_RO
+
+#define ERR_CNT "bctrl_ec"
+#define BIST_CTRL_ERR_CNT_BOFFSET 13
+#define BIST_CTRL_ERR_CNT_BLEN 2
+#define BIST_CTRL_ERR_CNT_FLAG HSL_RO
+
+#define ERR_ADDR "bctrl_ea"
+#define BIST_CTRL_ERR_ADDR_BOFFSET 0
+#define BIST_CTRL_ERR_ADDR_BLEN 12
+#define BIST_CTRL_ERR_ADDR_FLAG HSL_RO
+
+
+
+
+ /* BIST recover Register */
+#define BIST_RCV "brcv"
+#define BIST_RCV_ID 24
+#define BIST_RCV_OFFSET 0x00a4
+#define BIST_RCV_E_LENGTH 4
+#define BIST_RCV_E_OFFSET 0
+#define BIST_RCV_NR_E 1
+
+#define RCV_EN "brcv_en"
+#define BIST_RCV_RCV_EN_BOFFSET 31
+#define BIST_RCV_RCV_EN_BLEN 1
+#define BIST_RCV_RCV_EN_FLAG HSL_RW
+
+#define RCV_ADDR "brcv_addr"
+#define BIST_RCV_RCV_ADDR_BOFFSET 0
+#define BIST_RCV_RCV_ADDR_BLEN 12
+#define BIST_RCV_RCV_ADDR_FLAG HSL_RW
+
+
+
+
+ /* LED control Register */
+#define LED_CTRL "ledctrl"
+#define LED_CTRL_ID 25
+#define LED_CTRL_OFFSET 0x00b0
+#define LED_CTRL_E_LENGTH 4
+#define LED_CTRL_E_OFFSET 0
+#define LED_CTRL_NR_E 1
+
+#define PATTERN_EN "lctrl_pen"
+#define LED_CTRL_PATTERN_EN_BOFFSET 14
+#define LED_CTRL_PATTERN_EN_BLEN 2
+#define LED_CTRL_PATTERN_EN_FLAG HSL_RW
+
+#define FULL_LIGHT_EN "lctrl_fen"
+#define LED_CTRL_FULL_LIGHT_EN_BOFFSET 13
+#define LED_CTRL_FULL_LIGHT_EN_BLEN 1
+#define LED_CTRL_FULL_LIGHT_EN_FLAG HSL_RW
+
+#define HALF_LIGHT_EN "lctrl_hen"
+#define LED_CTRL_HALF_LIGHT_EN_BOFFSET 12
+#define LED_CTRL_HALF_LIGHT_EN_BLEN 1
+#define LED_CTRL_HALF_LIGHT_EN_FLAG HSL_RW
+
+#define POWERON_LIGHT_EN "lctrl_poen"
+#define LED_CTRL_POWERON_LIGHT_EN_BOFFSET 11
+#define LED_CTRL_POWERON_LIGHT_EN_BLEN 1
+#define LED_CTRL_POWERON_LIGHT_EN_FLAG HSL_RW
+
+#define GE_LIGHT_EN "lctrl_geen"
+#define LED_CTRL_GE_LIGHT_EN_BOFFSET 10
+#define LED_CTRL_GE_LIGHT_EN_BLEN 1
+#define LED_CTRL_GE_LIGHT_EN_FLAG HSL_RW
+
+#define FE_LIGHT_EN "lctrl_feen"
+#define LED_CTRL_FE_LIGHT_EN_BOFFSET 9
+#define LED_CTRL_FE_LIGHT_EN_BLEN 1
+#define LED_CTRL_FE_LIGHT_EN_FLAG HSL_RW
+
+#define ETH_LIGHT_EN "lctrl_ethen"
+#define LED_CTRL_ETH_LIGHT_EN_BOFFSET 8
+#define LED_CTRL_ETH_LIGHT_EN_BLEN 1
+#define LED_CTRL_ETH_LIGHT_EN_FLAG HSL_RW
+
+#define COL_BLINK_EN "lctrl_cen"
+#define LED_CTRL_COL_BLINK_EN_BOFFSET 7
+#define LED_CTRL_COL_BLINK_EN_BLEN 1
+#define LED_CTRL_COL_BLINK_EN_FLAG HSL_RW
+
+#define RX_BLINK_EN "lctrl_rxen"
+#define LED_CTRL_RX_BLINK_EN_BOFFSET 5
+#define LED_CTRL_RX_BLINK_EN_BLEN 1
+#define LED_CTRL_RX_BLINK_EN_FLAG HSL_RW
+
+#define TX_BLINK_EN "lctrl_txen"
+#define LED_CTRL_TX_BLINK_EN_BOFFSET 4
+#define LED_CTRL_TX_BLINK_EN_BLEN 1
+#define LED_CTRL_TX_BLINK_EN_FLAG HSL_RW
+
+#define LINKUP_OVER_EN "lctrl_loen"
+#define LED_CTRL_LINKUP_OVER_EN_BOFFSET 2
+#define LED_CTRL_LINKUP_OVER_EN_BLEN 1
+#define LED_CTRL_LINKUP_OVER_EN_FLAG HSL_RW
+
+#define BLINK_FREQ "lctrl_bfreq"
+#define LED_CTRL_BLINK_FREQ_BOFFSET 0
+#define LED_CTRL_BLINK_FREQ_BLEN 2
+#define LED_CTRL_BLINK_FREQ_FLAG HSL_RW
+
+ /* LED control Register */
+#define LED_PATTERN "ledpatten"
+#define LED_PATTERN_ID 25
+#define LED_PATTERN_OFFSET 0x00bc
+#define LED_PATTERN_E_LENGTH 4
+#define LED_PATTERN_E_OFFSET 0
+#define LED_PATTERN_NR_E 1
+
+#define P3L1_MODE "p3l1_mode"
+#define LED_PATTERN_P3L1_MODE_BOFFSET 24
+#define LED_PATTERN_P3L1_MODE_BLEN 2
+#define LED_PATTERN_P3L1_MODE_FLAG HSL_RW
+
+#define P3L0_MODE "p3l0_mode"
+#define LED_PATTERN_P3L0_MODE_BOFFSET 22
+#define LED_PATTERN_P3L0_MODE_BLEN 2
+#define LED_PATTERN_P3L0_MODE_FLAG HSL_RW
+
+#define P2L1_MODE "p2l1_mode"
+#define LED_PATTERN_P2L1_MODE_BOFFSET 20
+#define LED_PATTERN_P2L1_MODE_BLEN 2
+#define LED_PATTERN_P2L1_MODE_FLAG HSL_RW
+
+#define P2L0_MODE "p2l0_mode"
+#define LED_PATTERN_P2L0_MODE_BOFFSET 18
+#define LED_PATTERN_P2L0_MODE_BLEN 2
+#define LED_PATTERN_P2L0_MODE_FLAG HSL_RW
+
+#define P1L1_MODE "p1l1_mode"
+#define LED_PATTERN_P1L1_MODE_BOFFSET 16
+#define LED_PATTERN_P1L1_MODE_BLEN 2
+#define LED_PATTERN_P1L1_MODE_FLAG HSL_RW
+
+#define P1L0_MODE "p1l0_mode"
+#define LED_PATTERN_P1L0_MODE_BOFFSET 14
+#define LED_PATTERN_P1L0_MODE_BLEN 2
+#define LED_PATTERN_P1L0_MODE_FLAG HSL_RW
+
+#define M6_MODE "m6_mode"
+#define LED_PATTERN_M6_MODE_BOFFSET 12
+#define LED_PATTERN_M6_MODE_BLEN 2
+#define LED_PATTERN_M6_MODE_FLAG HSL_RW
+
+#define M5_MODE "m5_mode"
+#define LED_PATTERN_M5_MODE_BOFFSET 10
+#define LED_PATTERN_M5_MODE_BLEN 2
+#define LED_PATTERN_M5_MODE_FLAG HSL_RW
+
+
+ /* Port Status Register */
+#define PORT_STATUS "ptsts"
+#define PORT_STATUS_ID 29
+#define PORT_STATUS_OFFSET 0x0100
+#define PORT_STATUS_E_LENGTH 4
+#define PORT_STATUS_E_OFFSET 0x0100
+#define PORT_STATUS_NR_E 7
+
+#define FLOW_LINK_EN "ptsts_flen"
+#define PORT_STATUS_FLOW_LINK_EN_BOFFSET 12
+#define PORT_STATUS_FLOW_LINK_EN_BLEN 1
+#define PORT_STATUS_FLOW_LINK_EN_FLAG HSL_RW
+
+
+#define LINK_ASYN_PAUSE "ptsts_lasynp"
+#define PORT_STATUS_LINK_ASYN_PAUSE_BOFFSET 11
+#define PORT_STATUS_LINK_ASYN_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_ASYN_PAUSE_FLAG HSL_RO
+
+#define LINK_PAUSE "ptsts_lpause"
+#define PORT_STATUS_LINK_PAUSE_BOFFSET 10
+#define PORT_STATUS_LINK_PAUSE_BLEN 1
+#define PORT_STATUS_LINK_PAUSE_FLAG HSL_RO
+
+#define LINK_EN "ptsts_linken"
+#define PORT_STATUS_LINK_EN_BOFFSET 9
+#define PORT_STATUS_LINK_EN_BLEN 1
+#define PORT_STATUS_LINK_EN_FLAG HSL_RW
+
+#define LINK "ptsts_ptlink"
+#define PORT_STATUS_LINK_BOFFSET 8
+#define PORT_STATUS_LINK_BLEN 1
+#define PORT_STATUS_LINK_FLAG HSL_RO
+
+#define TX_HALF_FLOW_EN
+#define PORT_STATUS_TX_HALF_FLOW_EN_BOFFSET 7
+#define PORT_STATUS_TX_HALF_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_HALF_FLOW_EN_FLAG HSL_RW
+
+#define DUPLEX_MODE "ptsts_dupmod"
+#define PORT_STATUS_DUPLEX_MODE_BOFFSET 6
+#define PORT_STATUS_DUPLEX_MODE_BLEN 1
+#define PORT_STATUS_DUPLEX_MODE_FLAG HSL_RW
+
+#define RX_FLOW_EN "ptsts_rxfwen"
+#define PORT_STATUS_RX_FLOW_EN_BOFFSET 5
+#define PORT_STATUS_RX_FLOW_EN_BLEN 1
+#define PORT_STATUS_RX_FLOW_EN_FLAG HSL_RW
+
+#define TX_FLOW_EN "ptsts_txfwen"
+#define PORT_STATUS_TX_FLOW_EN_BOFFSET 4
+#define PORT_STATUS_TX_FLOW_EN_BLEN 1
+#define PORT_STATUS_TX_FLOW_EN_FLAG HSL_RW
+
+#define RXMAC_EN "ptsts_rxmacen"
+#define PORT_STATUS_RXMAC_EN_BOFFSET 3
+#define PORT_STATUS_RXMAC_EN_BLEN 1
+#define PORT_STATUS_RXMAC_EN_FLAG HSL_RW
+
+#define TXMAC_EN "ptsts_txmacen"
+#define PORT_STATUS_TXMAC_EN_BOFFSET 2
+#define PORT_STATUS_TXMAC_EN_BLEN 1
+#define PORT_STATUS_TXMAC_EN_FLAG HSL_RW
+
+#define SPEED_MODE "ptsts_speed"
+#define PORT_STATUS_SPEED_MODE_BOFFSET 0
+#define PORT_STATUS_SPEED_MODE_BLEN 2
+#define PORT_STATUS_SPEED_MODE_FLAG HSL_RW
+
+
+ /* Port Control Register */
+#define PORT_CTL "pctl"
+#define PORT_CTL_ID 30
+#define PORT_CTL_OFFSET 0x0104
+#define PORT_CTL_E_LENGTH 4
+#define PORT_CTL_E_OFFSET 0x0100
+#define PORT_CTL_NR_E 7
+
+#define EAPOL_EN "pctl_eapolen"
+#define PORT_CTL_EAPOL_EN_BOFFSET 23
+#define PORT_CTL_EAPOL_EN_BLEN 1
+#define PORT_CTL_EAPOL_EN_FLAG HSL_RW
+
+#define ARP_LEAKY_EN "pbvlan_alen"
+#define PORT_CTL_ARP_LEAKY_EN_BOFFSET 22
+#define PORT_CTL_ARP_LEAKY_EN_BLEN 1
+#define PORT_CTL_ARP_LEAKY_EN_FLAG HSL_RW
+
+#define LEAVE_EN "pctl_leaveen"
+#define PORT_CTL_LEAVE_EN_BOFFSET 21
+#define PORT_CTL_LEAVE_EN_BLEN 1
+#define PORT_CTL_LEAVE_EN_FLAG HSL_RW
+
+#define JOIN_EN "pctl_joinen"
+#define PORT_CTL_JOIN_EN_BOFFSET 20
+#define PORT_CTL_JOIN_EN_BLEN 1
+#define PORT_CTL_JOIN_EN_FLAG HSL_RW
+
+#define DHCP_EN "pctl_dhcpen"
+#define PORT_CTL_DHCP_EN_BOFFSET 19
+#define PORT_CTL_DHCP_EN_BLEN 1
+#define PORT_CTL_DHCP_EN_FLAG HSL_RW
+
+#define ING_MIRROR_EN "pctl_ingmiren"
+#define PORT_CTL_ING_MIRROR_EN_BOFFSET 17
+#define PORT_CTL_ING_MIRROR_EN_BLEN 1
+#define PORT_CTL_ING_MIRROR_EN_FLAG HSL_RW
+
+#define EG_MIRROR_EN "pctl_egmiren"
+#define PORT_CTL_EG_MIRROR_EN_BOFFSET 16
+#define PORT_CTL_EG_MIRROR_EN_BLEN 1
+#define PORT_CTL_EG_MIRROR_EN_FLAG HSL_RW
+
+#define DTAG_EN "pctl_dtagen"
+#define PORT_CTL_DTAG_EN_BOFFSET 15
+#define PORT_CTL_DTAG_EN_BLEN 1
+#define PORT_CTL_DTAG_EN_FLAG HSL_RW
+
+#define LEARN_EN "pctl_learnen"
+#define PORT_CTL_LEARN_EN_BOFFSET 14
+#define PORT_CTL_LEARN_EN_BLEN 1
+#define PORT_CTL_LEARN_EN_FLAG HSL_RW
+
+#define SINGLE_VLAN_EN "pctl_svlanen"
+#define PORT_CTL_SINGLE_VLAN_EN_BOFFSET 13
+#define PORT_CTL_SINGLE_VLAN_EN_BLEN 1
+#define PORT_CTL_SINGLE_VLAN_EN_FLAG HSL_RW
+
+#define MAC_LOOP_BACK "pctl_maclp"
+#define PORT_CTL_MAC_LOOP_BACK_BOFFSET 12
+#define PORT_CTL_MAC_LOOP_BACK_BLEN 1
+#define PORT_CTL_MAC_LOOP_BACK_FLAG HSL_RW
+
+#define HEAD_EN "pctl_headen"
+#define PORT_CTL_HEAD_EN_BOFFSET 11
+#define PORT_CTL_HEAD_EN_BLEN 1
+#define PORT_CTL_HEAD_EN_FLAG HSL_RW
+
+#define IGMP_MLD_EN "pctl_imlden"
+#define PORT_CTL_IGMP_MLD_EN_BOFFSET 10
+#define PORT_CTL_IGMP_MLD_EN_BLEN 1
+#define PORT_CTL_IGMP_MLD_EN_FLAG HSL_RW
+
+#define EG_VLAN_MODE "pctl_egvmode"
+#define PORT_CTL_EG_VLAN_MODE_BOFFSET 8
+#define PORT_CTL_EG_VLAN_MODE_BLEN 2
+#define PORT_CTL_EG_VLAN_MODE_FLAG HSL_RW
+
+#define LEARN_ONE_LOCK "pctl_lonelck"
+#define PORT_CTL_LEARN_ONE_LOCK_BOFFSET 7
+#define PORT_CTL_LEARN_ONE_LOCK_BLEN 1
+#define PORT_CTL_LEARN_ONE_LOCK_FLAG HSL_RW
+
+#define PORT_LOCK_EN "pctl_locken"
+#define PORT_CTL_PORT_LOCK_EN_BOFFSET 6
+#define PORT_CTL_PORT_LOCK_EN_BLEN 1
+#define PORT_CTL_PORT_LOCK_EN_FLAG HSL_RW
+
+#define LOCK_DROP_EN "pctl_dropen"
+#define PORT_CTL_LOCK_DROP_EN_BOFFSET 5
+#define PORT_CTL_LOCK_DROP_EN_BLEN 1
+#define PORT_CTL_LOCK_DROP_EN_FLAG HSL_RW
+
+#define PORT_STATE "pctl_pstate"
+#define PORT_CTL_PORT_STATE_BOFFSET 0
+#define PORT_CTL_PORT_STATE_BLEN 3
+#define PORT_CTL_PORT_STATE_FLAG HSL_RW
+
+
+ /* Port dot1ad Register */
+#define PORT_DOT1AD "pdot1ad"
+#define PORT_DOT1AD_ID 31
+#define PORT_DOT1AD_OFFSET 0x0108
+#define PORT_DOT1AD_E_LENGTH 4
+#define PORT_DOT1AD_E_OFFSET 0x0100
+#define PORT_DOT1AD_NR_E 7
+
+#define ING_PRI "pdot1ad_ingpri"
+#define PORT_DOT1AD_ING_PRI_BOFFSET 29
+#define PORT_DOT1AD_ING_PRI_BLEN 3
+#define PORT_DOT1AD_ING_PRI_FLAG HSL_RW
+
+#define FORCE_PVLAN "pdot1ad_fpvlan"
+#define PORT_DOT1AD_FORCE_PVLAN_BOFFSET 28
+#define PORT_DOT1AD_FORCE_PVLAN_BLEN 1
+#define PORT_DOT1AD_FORCE_PVLAN_FLAG HSL_RW
+
+#define DEF_CVID "pdot1ad_dcvid"
+#define PORT_DOT1AD_DEF_CVID_BOFFSET 16
+#define PORT_DOT1AD_DEF_CVID_BLEN 12
+#define PORT_DOT1AD_DEF_CVID_FLAG HSL_RW
+
+#define CLONE "pdot1ad_clone"
+#define PORT_DOT1AD_CLONE_BOFFSET 15
+#define PORT_DOT1AD_CLONE_BLEN 1
+#define PORT_DOT1AD_CLONE_FLAG HSL_RW
+
+#define PROPAGATION_EN "pdot1ad_pen"
+#define PORT_DOT1AD_PROPAGATION_EN_BOFFSET 14
+#define PORT_DOT1AD_PROPAGATION_EN_BLEN 1
+#define PORT_DOT1AD_PROPAGATION_EN_FLAG HSL_RW
+
+#define TLS_EN "pdot1ad_tlsen"
+#define PORT_DOT1AD_TLS_EN_BOFFSET 13
+#define PORT_DOT1AD_TLS_EN_BLEN 1
+#define PORT_DOT1AD_TLS_EN_FLAG HSL_RW
+
+#define FORCE_DEF_VID "pbot1ad_fdvid"
+#define PORT_DOT1AD_FORCE_DEF_VID_BOFFSET 12
+#define PORT_DOT1AD_FORCE_DEF_VID_BLEN 1
+#define PORT_DOT1AD_FORCE_DEF_VID_FLAG HSL_RW
+
+#define DEF_SVID "pdot1ad_dsvid"
+#define PORT_DOT1AD_DEF_SVID_BOFFSET 0
+#define PORT_DOT1AD_DEF_SVID_BLEN 12
+#define PORT_DOT1AD_DEF_SVID_FLAG HSL_RW
+
+
+ /* Port Based Vlan Register */
+#define PORT_BASE_VLAN "pbvlan"
+#define PORT_BASE_VLAN_ID 31
+#define PORT_BASE_VLAN_OFFSET 0x010c
+#define PORT_BASE_VLAN_E_LENGTH 4
+#define PORT_BASE_VLAN_E_OFFSET 0x0100
+#define PORT_BASE_VLAN_NR_E 7
+
+#define DOT1Q_MODE "pbvlan_8021q"
+#define PORT_BASE_VLAN_DOT1Q_MODE_BOFFSET 30
+#define PORT_BASE_VLAN_DOT1Q_MODE_BLEN 2
+#define PORT_BASE_VLAN_DOT1Q_MODE_FLAG HSL_RW
+
+#define COREP_EN "pbvlan_corepen"
+#define PORT_BASE_VLAN_COREP_EN_BOFFSET 29
+#define PORT_BASE_VLAN_COREP_EN_BLEN 1
+#define PORT_BASE_VLAN_COREP_EN_FLAG HSL_RW
+
+#define IN_VLAN_MODE "pbvlan_imode"
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BOFFSET 27
+#define PORT_BASE_VLAN_IN_VLAN_MODE_BLEN 2
+#define PORT_BASE_VLAN_IN_VLAN_MODE_FLAG HSL_RW
+
+#define PRI_PROPAGATION "pbvlan_prip"
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BOFFSET 23
+#define PORT_BASE_VLAN_PRI_PROPAGATION_BLEN 1
+#define PORT_BASE_VLAN_PRI_PROPAGATION_FLAG HSL_RW
+
+#define PORT_VID_MEM "pbvlan_pvidm"
+#define PORT_BASE_VLAN_PORT_VID_MEM_BOFFSET 16
+#define PORT_BASE_VLAN_PORT_VID_MEM_BLEN 7
+#define PORT_BASE_VLAN_PORT_VID_MEM_FLAG HSL_RW
+
+#define UNI_LEAKY_EN "pbvlan_ulen"
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BOFFSET 14
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_UNI_LEAKY_EN_FLAG HSL_RW
+
+#define MUL_LEAKY_EN "pbvlan_mlen"
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BOFFSET 13
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_BLEN 1
+#define PORT_BASE_VLAN_MUL_LEAKY_EN_FLAG HSL_RW
+
+
+ /* Port Rate Limit0 Register */
+#define RATE_LIMIT0 "rlmt0"
+#define RATE_LIMIT0_ID 32
+#define RATE_LIMIT0_OFFSET 0x0110
+#define RATE_LIMIT0_E_LENGTH 4
+#define RATE_LIMIT0_E_OFFSET 0x0100
+#define RATE_LIMIT0_NR_E 7
+
+#define ADD_RATE_BYTE "rlmt_addbyte"
+#define RATE_LIMIT0_ADD_RATE_BYTE_BOFFSET 24
+#define RATE_LIMIT0_ADD_RATE_BYTE_BLEN 8
+#define RATE_LIMIT0_ADD_RATE_BYTE_FLAG HSL_RW
+
+#define EG_RATE_EN "rlmt_egen"
+#define RATE_LIMIT0_EG_RATE_EN_BOFFSET 23
+#define RATE_LIMIT0_EG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_RATE_EN_FLAG HSL_RW
+
+#define EG_MNG_RATE_EN "rlmt_egmngen"
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BOFFSET 22
+#define RATE_LIMIT0_EG_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_EG_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MNG_RATE_EN "rlmt_inmngen"
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BOFFSET 21
+#define RATE_LIMIT0_IN_MNG_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MNG_RATE_EN_FLAG HSL_RW
+
+#define IN_MUL_RATE_EN "rlmt_inmulen"
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BOFFSET 20
+#define RATE_LIMIT0_IN_MUL_RATE_EN_BLEN 1
+#define RATE_LIMIT0_IN_MUL_RATE_EN_FLAG HSL_RW
+
+#define ING_RATE "rlmt_ingrate"
+#define RATE_LIMIT0_ING_RATE_BOFFSET 0
+#define RATE_LIMIT0_ING_RATE_BLEN 15
+#define RATE_LIMIT0_ING_RATE_FLAG HSL_RW
+
+
+ /* Priority Control Register */
+#define PRI_CTL "prctl"
+#define PRI_CTL_ID 33
+#define PRI_CTL_OFFSET 0x0114
+#define PRI_CTL_E_LENGTH 4
+#define PRI_CTL_E_OFFSET 0x0100
+#define PRI_CTL_NR_E 7
+
+#define PORT_PRI_EN "prctl_ptprien"
+#define PRI_CTL_PORT_PRI_EN_BOFFSET 19
+#define PRI_CTL_PORT_PRI_EN_BLEN 1
+#define PRI_CTL_PORT_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_EN "prctl_daprien"
+#define PRI_CTL_DA_PRI_EN_BOFFSET 18
+#define PRI_CTL_DA_PRI_EN_BLEN 1
+#define PRI_CTL_DA_PRI_EN_FLAG HSL_RW
+
+#define VLAN_PRI_EN "prctl_vprien"
+#define PRI_CTL_VLAN_PRI_EN_BOFFSET 17
+#define PRI_CTL_VLAN_PRI_EN_BLEN 1
+#define PRI_CTL_VLAN_PRI_EN_FLAG HSL_RW
+
+#define IP_PRI_EN "prctl_ipprien"
+#define PRI_CTL_IP_PRI_EN_BOFFSET 16
+#define PRI_CTL_IP_PRI_EN_BLEN 1
+#define PRI_CTL_IP_PRI_EN_FLAG HSL_RW
+
+#define DA_PRI_SEL "prctl_dapris"
+#define PRI_CTL_DA_PRI_SEL_BOFFSET 6
+#define PRI_CTL_DA_PRI_SEL_BLEN 2
+#define PRI_CTL_DA_PRI_SEL_FLAG HSL_RW
+
+#define VLAN_PRI_SEL "prctl_vpris"
+#define PRI_CTL_VLAN_PRI_SEL_BOFFSET 4
+#define PRI_CTL_VLAN_PRI_SEL_BLEN 2
+#define PRI_CTL_VLAN_PRI_SEL_FLAG HSL_RW
+
+#define IP_PRI_SEL "prctl_ippris"
+#define PRI_CTL_IP_PRI_SEL_BOFFSET 2
+#define PRI_CTL_IP_PRI_SEL_BLEN 2
+#define PRI_CTL_IP_PRI_SEL_FLAG HSL_RW
+
+#define PORT_PRI_SEL "prctl_ptpris"
+#define PRI_CTL_PORT_PRI_SEL_BOFFSET 0
+#define PRI_CTL_PORT_PRI_SEL_BLEN 2
+#define PRI_CTL_PORT_PRI_SEL_FLAG HSL_RW
+
+
+ /* Storm Control Register */
+#define STORM_CTL "sctrl"
+#define STORM_CTL_ID 33
+#define STORM_CTL_OFFSET 0x0118
+#define STORM_CTL_E_LENGTH 4
+#define STORM_CTL_E_OFFSET 0x0100
+#define STORM_CTL_NR_E 7
+
+#define UNIT "sctrl_unit"
+#define STORM_CTL_UNIT_BOFFSET 24
+#define STORM_CTL_UNIT_BLEN 2
+#define STORM_CTL_UNIT_FLAG HSL_RW
+
+#define MUL_EN "sctrl_mulen"
+#define STORM_CTL_MUL_EN_BOFFSET 10
+#define STORM_CTL_MUL_EN_BLEN 1
+#define STORM_CTL_MUL_EN_FLAG HSL_RW
+
+#define UNI_EN "sctrl_unien"
+#define STORM_CTL_UNI_EN_BOFFSET 9
+#define STORM_CTL_UNI_EN_BLEN 1
+#define STORM_CTL_UNI_EN_FLAG HSL_RW
+
+#define BRO_EN "sctrl_broen"
+#define STORM_CTL_BRO_EN_BOFFSET 8
+#define STORM_CTL_BRO_EN_BLEN 1
+#define STORM_CTL_BRO_EN_FLAG HSL_RW
+
+#define RATE "sctrl_rate"
+#define STORM_CTL_RATE_BOFFSET 0
+#define STORM_CTL_RATE_BLEN 4
+#define STORM_CTL_RATE_FLAG HSL_RW
+
+
+ /* Queue Control Register */
+#define QUEUE_CTL "qctl"
+#define QUEUE_CTL_ID 34
+#define QUEUE_CTL_OFFSET 0x011c
+#define QUEUE_CTL_E_LENGTH 4
+#define QUEUE_CTL_E_OFFSET 0x0100
+#define QUEUE_CTL_NR_E 7
+
+#define PORT_IN_DESC_EN "qctl_pdescen"
+#define QUEUE_CTL_PORT_IN_DESC_EN_BOFFSET 28
+#define QUEUE_CTL_PORT_IN_DESC_EN_BLEN 4
+#define QUEUE_CTL_PORT_IN_DESC_EN_FLAG HSL_RW
+
+#define PORT_DESC_EN "qctl_pdescen"
+#define QUEUE_CTL_PORT_DESC_EN_BOFFSET 25
+#define QUEUE_CTL_PORT_DESC_EN_BLEN 1
+#define QUEUE_CTL_PORT_DESC_EN_FLAG HSL_RW
+
+#define QUEUE_DESC_EN "qctl_qdescen"
+#define QUEUE_CTL_QUEUE_DESC_EN_BOFFSET 24
+#define QUEUE_CTL_QUEUE_DESC_EN_BLEN 1
+#define QUEUE_CTL_QUEUE_DESC_EN_FLAG HSL_RW
+
+#define PORT_DESC_NR "qctl_pdscpnr"
+#define QUEUE_CTL_PORT_DESC_NR_BOFFSET 16
+#define QUEUE_CTL_PORT_DESC_NR_BLEN 6
+#define QUEUE_CTL_PORT_DESC_NR_FLAG HSL_RW
+
+#define QUEUE3_DESC_NR "qctl_q3dscpnr"
+#define QUEUE_CTL_QUEUE3_DESC_NR_BOFFSET 12
+#define QUEUE_CTL_QUEUE3_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE3_DESC_NR_FLAG HSL_RW
+
+#define QUEUE2_DESC_NR "qctl_q2dscpnr"
+#define QUEUE_CTL_QUEUE2_DESC_NR_BOFFSET 8
+#define QUEUE_CTL_QUEUE2_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE2_DESC_NR_FLAG HSL_RW
+
+#define QUEUE1_DESC_NR "qctl_q1dscpnr"
+#define QUEUE_CTL_QUEUE1_DESC_NR_BOFFSET 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE1_DESC_NR_FLAG HSL_RW
+
+#define QUEUE0_DESC_NR "qctl_q0dscpnr"
+#define QUEUE_CTL_QUEUE0_DESC_NR_BOFFSET 0
+#define QUEUE_CTL_QUEUE0_DESC_NR_BLEN 4
+#define QUEUE_CTL_QUEUE0_DESC_NR_FLAG HSL_RW
+
+
+ /* Port Rate Limit1 Register */
+#define RATE_LIMIT1 "rlmt1"
+#define RATE_LIMIT1_ID 32
+#define RATE_LIMIT1_OFFSET 0x0120
+#define RATE_LIMIT1_E_LENGTH 4
+#define RATE_LIMIT1_E_OFFSET 0x0100
+#define RATE_LIMIT1_NR_E 7
+
+#define EG_Q1_RATE "rlmt_egq1rate"
+#define RATE_LIMIT1_EG_Q1_RATE_BOFFSET 16
+#define RATE_LIMIT1_EG_Q1_RATE_BLEN 15
+#define RATE_LIMIT1_EG_Q1_RATE_FLAG HSL_RW
+
+#define EG_Q0_RATE "rlmt_egq0rate"
+#define RATE_LIMIT1_EG_Q0_RATE_BOFFSET 0
+#define RATE_LIMIT1_EG_Q0_RATE_BLEN 15
+#define RATE_LIMIT1_EG_Q0_RATE_FLAG HSL_RW
+
+
+ /* Port Rate Limit2 Register */
+#define RATE_LIMIT2 "rlmt2"
+#define RATE_LIMIT2_ID 32
+#define RATE_LIMIT2_OFFSET 0x0124
+#define RATE_LIMIT2_E_LENGTH 4
+#define RATE_LIMIT2_E_OFFSET 0x0100
+#define RATE_LIMIT2_NR_E 7
+
+#define EG_Q3_RATE "rlmt_egq3rate"
+#define RATE_LIMIT2_EG_Q3_RATE_BOFFSET 16
+#define RATE_LIMIT2_EG_Q3_RATE_BLEN 15
+#define RATE_LIMIT2_EG_Q3_RATE_FLAG HSL_RW
+
+#define EG_Q2_RATE "rlmt_egq2rate"
+#define RATE_LIMIT2_EG_Q2_RATE_BOFFSET 0
+#define RATE_LIMIT2_EG_Q2_RATE_BLEN 15
+#define RATE_LIMIT2_EG_Q2_RATE_FLAG HSL_RW
+
+
+
+
+ /* Port Rate Limit3 Register */
+#define RATE_LIMIT3 "rlmt3"
+#define RATE_LIMIT3_ID 32
+#define RATE_LIMIT3_OFFSET 0x0128
+#define RATE_LIMIT3_E_LENGTH 4
+#define RATE_LIMIT3_E_OFFSET 0x0100
+#define RATE_LIMIT3_NR_E 7
+
+#define EG_Q3_CBS "rlmt_egq3cbs"
+#define RATE_LIMIT3_EG_Q3_CBS_BOFFSET 22
+#define RATE_LIMIT3_EG_Q3_CBS_BLEN 2
+#define RATE_LIMIT3_EG_Q3_CBS_FLAG HSL_RW
+
+#define EG_Q2_CBS "rlmt_egq2cbs"
+#define RATE_LIMIT3_EG_Q2_CBS_BOFFSET 20
+#define RATE_LIMIT3_EG_Q2_CBS_BLEN 2
+#define RATE_LIMIT3_EG_Q2_CBS_FLAG HSL_RW
+
+#define EG_Q1_CBS "rlmt_egq1cbs"
+#define RATE_LIMIT3_EG_Q1_CBS_BOFFSET 18
+#define RATE_LIMIT3_EG_Q1_CBS_BLEN 2
+#define RATE_LIMIT3_EG_Q1_CBS_FLAG HSL_RW
+
+#define EG_Q0_CBS "rlmt_egq0cbs"
+#define RATE_LIMIT3_EG_Q0_CBS_BOFFSET 16
+#define RATE_LIMIT3_EG_Q0_CBS_BLEN 2
+#define RATE_LIMIT3_EG_Q0_CBS_FLAG HSL_RW
+
+#define EG_TS "rlmt_egts"
+#define RATE_LIMIT3_EG_TS_BOFFSET 0
+#define RATE_LIMIT3_EG_TS_BLEN 3
+#define RATE_LIMIT3_EG_TS_FLAG HSL_RW
+
+
+
+
+ /* Port Rate Limit2 Register */
+#define WRR_CTRL "wrrc"
+#define WRR_CTRL_ID 32
+#define WRR_CTRL_OFFSET 0x012c
+#define WRR_CTRL_E_LENGTH 4
+#define WRR_CTRL_E_OFFSET 0x0100
+#define WRR_CTRL_NR_E 7
+
+#define SCH_MODE "wrrc_mode"
+#define WRR_CTRL_SCH_MODE_BOFFSET 29
+#define WRR_CTRL_SCH_MODE_BLEN 2
+#define WRR_CTRL_SCH_MODE_FLAG HSL_RW
+
+#define Q3_W "wrrc_q3w"
+#define WRR_CTRL_Q3_W_BOFFSET 24
+#define WRR_CTRL_Q3_W_BLEN 5
+#define WRR_CTRL_Q3_W_FLAG HSL_RW
+
+#define Q2_W "wrrc_q2w"
+#define WRR_CTRL_Q2_W_BOFFSET 16
+#define WRR_CTRL_Q2_W_BLEN 5
+#define WRR_CTRL_Q2_W_FLAG HSL_RW
+
+#define Q1_W "wrrc_q1w"
+#define WRR_CTRL_Q1_W_BOFFSET 8
+#define WRR_CTRL_Q1_W_BLEN 5
+#define WRR_CTRL_Q1_W_FLAG HSL_RW
+
+#define Q0_W "wrrc_q0w"
+#define WRR_CTRL_Q0_W_BOFFSET 0
+#define WRR_CTRL_Q0_W_BLEN 5
+#define WRR_CTRL_Q0_W_FLAG HSL_RW
+
+
+ /* mib memory info */
+#define MIB_RXBROAD "RxBroad"
+#define MIB_RXBROAD_ID 34
+#define MIB_RXBROAD_OFFSET 0x20000
+#define MIB_RXBROAD_E_LENGTH 4
+#define MIB_RXBROAD_E_OFFSET 0x100
+#define MIB_RXBROAD_NR_E 6
+
+#define MIB_RXPAUSE "RxPause"
+#define MIB_RXPAUSE_ID 35
+#define MIB_RXPAUSE_OFFSET 0x20004
+#define MIB_RXPAUSE_E_LENGTH 4
+#define MIB_RXPAUSE_E_OFFSET 0x100
+#define MIB_RXPAUSE_NR_E 6
+
+#define MIB_RXMULTI "RxMulti"
+#define MIB_RXMULTI_ID 36
+#define MIB_RXMULTI_OFFSET 0x20008
+#define MIB_RXMULTI_E_LENGTH 4
+#define MIB_RXMULTI_E_OFFSET 0x100
+#define MIB_RXMULTI_NR_E 6
+
+#define MIB_RXFCSERR "RxFcsErr"
+#define MIB_RXFCSERR_ID 37
+#define MIB_RXFCSERR_OFFSET 0x2000c
+#define MIB_RXFCSERR_E_LENGTH 4
+#define MIB_RXFCSERR_E_OFFSET 0x100
+#define MIB_RXFCSERR_NR_E 6
+
+#define MIB_RXALLIGNERR "RxAllignErr"
+#define MIB_RXALLIGNERR_ID 38
+#define MIB_RXALLIGNERR_OFFSET 0x20010
+#define MIB_RXALLIGNERR_E_LENGTH 4
+#define MIB_RXALLIGNERR_E_OFFSET 0x100
+#define MIB_RXALLIGNERR_NR_E 6
+
+#define MIB_RXRUNT "RxRunt"
+#define MIB_RXRUNT_ID 39
+#define MIB_RXRUNT_OFFSET 0x20014
+#define MIB_RXRUNT_E_LENGTH 4
+#define MIB_RXRUNT_E_OFFSET 0x100
+#define MIB_RXRUNT_NR_E 6
+
+#define MIB_RXFRAGMENT "RxFragment"
+#define MIB_RXFRAGMENT_ID 40
+#define MIB_RXFRAGMENT_OFFSET 0x20018
+#define MIB_RXFRAGMENT_E_LENGTH 4
+#define MIB_RXFRAGMENT_E_OFFSET 0x100
+#define MIB_RXFRAGMENT_NR_E 6
+
+#define MIB_RX64BYTE "Rx64Byte"
+#define MIB_RX64BYTE_ID 41
+#define MIB_RX64BYTE_OFFSET 0x2001c
+#define MIB_RX64BYTE_E_LENGTH 4
+#define MIB_RX64BYTE_E_OFFSET 0x100
+#define MIB_RX64BYTE_NR_E 6
+
+#define MIB_RX128BYTE "Rx128Byte"
+#define MIB_RX128BYTE_ID 42
+#define MIB_RX128BYTE_OFFSET 0x20020
+#define MIB_RX128BYTE_E_LENGTH 4
+#define MIB_RX128BYTE_E_OFFSET 0x100
+#define MIB_RX128BYTE_NR_E 6
+
+#define MIB_RX256BYTE "Rx256Byte"
+#define MIB_RX256BYTE_ID 43
+#define MIB_RX256BYTE_OFFSET 0x20024
+#define MIB_RX256BYTE_E_LENGTH 4
+#define MIB_RX256BYTE_E_OFFSET 0x100
+#define MIB_RX256BYTE_NR_E 6
+
+#define MIB_RX512BYTE "Rx512Byte"
+#define MIB_RX512BYTE_ID 44
+#define MIB_RX512BYTE_OFFSET 0x20028
+#define MIB_RX512BYTE_E_LENGTH 4
+#define MIB_RX512BYTE_E_OFFSET 0x100
+#define MIB_RX512BYTE_NR_E 6
+
+#define MIB_RX1024BYTE "Rx1024Byte"
+#define MIB_RX1024BYTE_ID 45
+#define MIB_RX1024BYTE_OFFSET 0x2002c
+#define MIB_RX1024BYTE_E_LENGTH 4
+#define MIB_RX1024BYTE_E_OFFSET 0x100
+#define MIB_RX1024BYTE_NR_E 6
+
+#define MIB_RX1518BYTE "Rx1518Byte"
+#define MIB_RX1518BYTE_ID 45
+#define MIB_RX1518BYTE_OFFSET 0x20030
+#define MIB_RX1518BYTE_E_LENGTH 4
+#define MIB_RX1518BYTE_E_OFFSET 0x100
+#define MIB_RX1518BYTE_NR_E 6
+
+#define MIB_RXMAXBYTE "RxMaxByte"
+#define MIB_RXMAXBYTE_ID 46
+#define MIB_RXMAXBYTE_OFFSET 0x20034
+#define MIB_RXMAXBYTE_E_LENGTH 4
+#define MIB_RXMAXBYTE_E_OFFSET 0x100
+#define MIB_RXMAXBYTE_NR_E 6
+
+#define MIB_RXTOOLONG "RxTooLong"
+#define MIB_RXTOOLONG_ID 47
+#define MIB_RXTOOLONG_OFFSET 0x20038
+#define MIB_RXTOOLONG_E_LENGTH 4
+#define MIB_RXTOOLONG_E_OFFSET 0x100
+#define MIB_RXTOOLONG_NR_E 6
+
+#define MIB_RXGOODBYTE_LO "RxGoodByteLo"
+#define MIB_RXGOODBYTE_LO_ID 48
+#define MIB_RXGOODBYTE_LO_OFFSET 0x2003c
+#define MIB_RXGOODBYTE_LO_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_LO_NR_E 6
+
+#define MIB_RXGOODBYTE_HI "RxGoodByteHi"
+#define MIB_RXGOODBYTE_HI_ID 49
+#define MIB_RXGOODBYTE_HI_OFFSET 0x20040
+#define MIB_RXGOODBYTE_HI_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_E_OFFSET 0x100
+#define MIB_RXGOODBYTE_HI_NR_E 6
+
+#define MIB_RXBADBYTE_LO "RxBadByteLo"
+#define MIB_RXBADBYTE_LO_ID 50
+#define MIB_RXBADBYTE_LO_OFFSET 0x20044
+#define MIB_RXBADBYTE_LO_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_E_OFFSET 0x100
+#define MIB_RXBADBYTE_LO_NR_E 6
+
+#define MIB_RXBADBYTE_HI "RxBadByteHi"
+#define MIB_RXBADBYTE_HI_ID 51
+#define MIB_RXBADBYTE_HI_OFFSET 0x20048
+#define MIB_RXBADBYTE_HI_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_E_OFFSET 0x100
+#define MIB_RXBADBYTE_HI_NR_E 6
+
+#define MIB_RXOVERFLOW "RxOverFlow"
+#define MIB_RXOVERFLOW_ID 52
+#define MIB_RXOVERFLOW_OFFSET 0x2004c
+#define MIB_RXOVERFLOW_E_LENGTH 4
+#define MIB_RXOVERFLOW_E_OFFSET 0x100
+#define MIB_RXOVERFLOW_NR_E 6
+
+#define MIB_FILTERED "Filtered"
+#define MIB_FILTERED_ID 53
+#define MIB_FILTERED_OFFSET 0x20050
+#define MIB_FILTERED_E_LENGTH 4
+#define MIB_FILTERED_E_OFFSET 0x100
+#define MIB_FILTERED_NR_E 6
+
+#define MIB_TXBROAD "TxBroad"
+#define MIB_TXBROAD_ID 54
+#define MIB_TXBROAD_OFFSET 0x20054
+#define MIB_TXBROAD_E_LENGTH 4
+#define MIB_TXBROAD_E_OFFSET 0x100
+#define MIB_TXBROAD_NR_E 6
+
+#define MIB_TXPAUSE "TxPause"
+#define MIB_TXPAUSE_ID 55
+#define MIB_TXPAUSE_OFFSET 0x20058
+#define MIB_TXPAUSE_E_LENGTH 4
+#define MIB_TXPAUSE_E_OFFSET 0x100
+#define MIB_TXPAUSE_NR_E 6
+
+#define MIB_TXMULTI "TxMulti"
+#define MIB_TXMULTI_ID 56
+#define MIB_TXMULTI_OFFSET 0x2005c
+#define MIB_TXMULTI_E_LENGTH 4
+#define MIB_TXMULTI_E_OFFSET 0x100
+#define MIB_TXMULTI_NR_E 6
+
+#define MIB_TXUNDERRUN "TxUnderRun"
+#define MIB_TXUNDERRUN_ID 57
+#define MIB_TXUNDERRUN_OFFSET 0x20060
+#define MIB_TXUNDERRUN_E_LENGTH 4
+#define MIB_TXUNDERRUN_E_OFFSET 0x100
+#define MIB_TXUNDERRUN_NR_E 6
+
+#define MIB_TX64BYTE "Tx64Byte"
+#define MIB_TX64BYTE_ID 58
+#define MIB_TX64BYTE_OFFSET 0x20064
+#define MIB_TX64BYTE_E_LENGTH 4
+#define MIB_TX64BYTE_E_OFFSET 0x100
+#define MIB_TX64BYTE_NR_E 6
+
+#define MIB_TX128BYTE "Tx128Byte"
+#define MIB_TX128BYTE_ID 59
+#define MIB_TX128BYTE_OFFSET 0x20068
+#define MIB_TX128BYTE_E_LENGTH 4
+#define MIB_TX128BYTE_E_OFFSET 0x100
+#define MIB_TX128BYTE_NR_E 6
+
+#define MIB_TX256BYTE "Tx256Byte"
+#define MIB_TX256BYTE_ID 60
+#define MIB_TX256BYTE_OFFSET 0x2006c
+#define MIB_TX256BYTE_E_LENGTH 4
+#define MIB_TX256BYTE_E_OFFSET 0x100
+#define MIB_TX256BYTE_NR_E 6
+
+#define MIB_TX512BYTE "Tx512Byte"
+#define MIB_TX512BYTE_ID 61
+#define MIB_TX512BYTE_OFFSET 0x20070
+#define MIB_TX512BYTE_E_LENGTH 4
+#define MIB_TX512BYTE_E_OFFSET 0x100
+#define MIB_TX512BYTE_NR_E 6
+
+#define MIB_TX1024BYTE "Tx1024Byte"
+#define MIB_TX1024BYTE_ID 62
+#define MIB_TX1024BYTE_OFFSET 0x20074
+#define MIB_TX1024BYTE_E_LENGTH 4
+#define MIB_TX1024BYTE_E_OFFSET 0x100
+#define MIB_TX1024BYTE_NR_E 6
+
+#define MIB_TX1518BYTE "Tx1518Byte"
+#define MIB_TX1518BYTE_ID 62
+#define MIB_TX1518BYTE_OFFSET 0x20078
+#define MIB_TX1518BYTE_E_LENGTH 4
+#define MIB_TX1518BYTE_E_OFFSET 0x100
+#define MIB_TX1518BYTE_NR_E 6
+
+#define MIB_TXMAXBYTE "TxMaxByte"
+#define MIB_TXMAXBYTE_ID 63
+#define MIB_TXMAXBYTE_OFFSET 0x2007c
+#define MIB_TXMAXBYTE_E_LENGTH 4
+#define MIB_TXMAXBYTE_E_OFFSET 0x100
+#define MIB_TXMAXBYTE_NR_E 6
+
+#define MIB_TXOVERSIZE "TxOverSize"
+#define MIB_TXOVERSIZE_ID 64
+#define MIB_TXOVERSIZE_OFFSET 0x20080
+#define MIB_TXOVERSIZE_E_LENGTH 4
+#define MIB_TXOVERSIZE_E_OFFSET 0x100
+#define MIB_TXOVERSIZE_NR_E 6
+
+#define MIB_TXBYTE_LO "TxByteLo"
+#define MIB_TXBYTE_LO_ID 65
+#define MIB_TXBYTE_LO_OFFSET 0x20084
+#define MIB_TXBYTE_LO_E_LENGTH 4
+#define MIB_TXBYTE_LO_E_OFFSET 0x100
+#define MIB_TXBYTE_LO_NR_E 6
+
+#define MIB_TXBYTE_HI "TxByteHi"
+#define MIB_TXBYTE_HI_ID 66
+#define MIB_TXBYTE_HI_OFFSET 0x20088
+#define MIB_TXBYTE_HI_E_LENGTH 4
+#define MIB_TXBYTE_HI_E_OFFSET 0x100
+#define MIB_TXBYTE_HI_NR_E 6
+
+#define MIB_TXCOLLISION "TxCollision"
+#define MIB_TXCOLLISION_ID 67
+#define MIB_TXCOLLISION_OFFSET 0x2008c
+#define MIB_TXCOLLISION_E_LENGTH 4
+#define MIB_TXCOLLISION_E_OFFSET 0x100
+#define MIB_TXCOLLISION_NR_E 6
+
+#define MIB_TXABORTCOL "TxAbortCol"
+#define MIB_TXABORTCOL_ID 68
+#define MIB_TXABORTCOL_OFFSET 0x20090
+#define MIB_TXABORTCOL_E_LENGTH 4
+#define MIB_TXABORTCOL_E_OFFSET 0x100
+#define MIB_TXABORTCOL_NR_E 6
+
+#define MIB_TXMULTICOL "TxMultiCol"
+#define MIB_TXMULTICOL_ID 69
+#define MIB_TXMULTICOL_OFFSET 0x20094
+#define MIB_TXMULTICOL_E_LENGTH 4
+#define MIB_TXMULTICOL_E_OFFSET 0x100
+#define MIB_TXMULTICOL_NR_E 6
+
+#define MIB_TXSINGALCOL "TxSingalCol"
+#define MIB_TXSINGALCOL_ID 70
+#define MIB_TXSINGALCOL_OFFSET 0x20098
+#define MIB_TXSINGALCOL_E_LENGTH 4
+#define MIB_TXSINGALCOL_E_OFFSET 0x100
+#define MIB_TXSINGALCOL_NR_E 6
+
+#define MIB_TXEXCDEFER "TxExcDefer"
+#define MIB_TXEXCDEFER_ID 71
+#define MIB_TXEXCDEFER_OFFSET 0x2009c
+#define MIB_TXEXCDEFER_E_LENGTH 4
+#define MIB_TXEXCDEFER_E_OFFSET 0x100
+#define MIB_TXEXCDEFER_NR_E 6
+
+#define MIB_TXDEFER "TxDefer"
+#define MIB_TXDEFER_ID 72
+#define MIB_TXDEFER_OFFSET 0x200a0
+#define MIB_TXDEFER_E_LENGTH 4
+#define MIB_TXDEFER_E_OFFSET 0x100
+#define MIB_TXDEFER_NR_E 6
+
+#define MIB_TXLATECOL "TxLateCol"
+#define MIB_TXLATECOL_ID 73
+#define MIB_TXLATECOL_OFFSET 0x200a4
+#define MIB_TXLATECOL_E_LENGTH 4
+#define MIB_TXLATECOL_E_OFFSET 0x100
+#define MIB_TXLATECOL_NR_E 6
+
+#if 0
+ /* mib info second mem block */
+#define MIB_RXBROAD_2 "RxBroad_2"
+#define MIB_RXBROAD_2_ID 34
+#define MIB_RXBROAD_2_OFFSET (MIB_RXBROAD_OFFSET + 0x400)
+#define MIB_RXBROAD_2_E_LENGTH 4
+#define MIB_RXBROAD_2_E_OFFSET 0xa8
+#define MIB_RXBROAD_2_NR_E 6
+
+#define MIB_RXPAUSE_2 "RxPause_2"
+#define MIB_RXPAUSE_2_ID 35
+#define MIB_RXPAUSE_2_OFFSET (MIB_RXPAUSE_OFFSET + 0x400)
+#define MIB_RXPAUSE_2_E_LENGTH 4
+#define MIB_RXPAUSE_2_E_OFFSET 0xa8
+#define MIB_RXPAUSE_2_NR_E 6
+
+#define MIB_RXMULTI_2 "RxMulti_2"
+#define MIB_RXMULTI_2_ID 36
+#define MIB_RXMULTI_2_OFFSET (MIB_RXMULTI_OFFSET + 0x400)
+#define MIB_RXMULTI_2_E_LENGTH 4
+#define MIB_RXMULTI_2_E_OFFSET 0xa8
+#define MIB_RXMULTI_2_NR_E 6
+
+#define MIB_RXFCSERR_2 "RxFcsErr_2"
+#define MIB_RXFCSERR_2_ID 37
+#define MIB_RXFCSERR_2_OFFSET (MIB_RXFCSERR_OFFSET + 0x400)
+#define MIB_RXFCSERR_2_E_LENGTH 4
+#define MIB_RXFCSERR_2_E_OFFSET 0xa8
+#define MIB_RXFCSERR_2_NR_E 6
+
+#define MIB_RXALLIGNERR_2 "RxAllignErr_2"
+#define MIB_RXALLIGNERR_2_ID 38
+#define MIB_RXALLIGNERR_2_OFFSET (MIB_RXALLIGNERR_OFFSET + 0x400)
+#define MIB_RXALLIGNERR_2_E_LENGTH 4
+#define MIB_RXALLIGNERR_2_E_OFFSET 0xa8
+#define MIB_RXALLIGNERR_2_NR_E 6
+
+#define MIB_RXRUNT_2 "RxRunt_2"
+#define MIB_RXRUNT_2_ID 39
+#define MIB_RXRUNT_2_OFFSET (MIB_RXRUNT_OFFSET + 0x400)
+#define MIB_RXRUNT_2_E_LENGTH 4
+#define MIB_RXRUNT_2_E_OFFSET 0xa8
+#define MIB_RXRUNT_2_NR_E 6
+
+#define MIB_RXFRAGMENT_2 "RxFragment_2"
+#define MIB_RXFRAGMENT_2_ID 40
+#define MIB_RXFRAGMENT_2_OFFSET (MIB_RXFRAGMENT_OFFSET + 0x400)
+#define MIB_RXFRAGMENT_2_E_LENGTH 4
+#define MIB_RXFRAGMENT_2_E_OFFSET 0xa8
+#define MIB_RXFRAGMENT_2_NR_E 6
+
+#define MIB_RX64BYTE_2 "Rx64Byte_2"
+#define MIB_RX64BYTE_2_ID 41
+#define MIB_RX64BYTE_2_OFFSET (MIB_RX64BYTE_OFFSET + 0x400)
+#define MIB_RX64BYTE_2_E_LENGTH 4
+#define MIB_RX64BYTE_2_E_OFFSET 0xa8
+#define MIB_RX64BYTE_2_NR_E 6
+
+#define MIB_RX128BYTE_2 "Rx128Byte_2"
+#define MIB_RX128BYTE_2_ID 42
+#define MIB_RX128BYTE_2_OFFSET (MIB_RX128BYTE_OFFSET + 0x400)
+#define MIB_RX128BYTE_2_E_LENGTH 4
+#define MIB_RX128BYTE_2_E_OFFSET 0xa8
+#define MIB_RX128BYTE_2_NR_E 6
+
+#define MIB_RX256BYTE_2 "Rx256Byte_2"
+#define MIB_RX256BYTE_2_ID 43
+#define MIB_RX256BYTE_2_OFFSET (MIB_RX256BYTE_OFFSET + 0x400)
+#define MIB_RX256BYTE_2_E_LENGTH 4
+#define MIB_RX256BYTE_2_E_OFFSET 0xa8
+#define MIB_RX256BYTE_2_NR_E 6
+
+#define MIB_RX512BYTE_2 "Rx512Byte_2"
+#define MIB_RX512BYTE_2_ID 44
+#define MIB_RX512BYTE_2_OFFSET (MIB_RX512BYTE_OFFSET + 0x400)
+#define MIB_RX512BYTE_2_E_LENGTH 4
+#define MIB_RX512BYTE_2_E_OFFSET 0xa8
+#define MIB_RX512BYTE_2_NR_E 6
+
+#define MIB_RX1024BYTE_2 "Rx1024Byte_2"
+#define MIB_RX1024BYTE_2_ID 45
+#define MIB_RX1024BYTE_2_OFFSET (MIB_RX1024BYTE_OFFSET + 0x400)
+#define MIB_RX1024BYTE_2_E_LENGTH 4
+#define MIB_RX1024BYTE_2_E_OFFSET 0xa8
+#define MIB_RX1024BYTE_2_NR_E 6
+
+#define MIB_RX1518BYTE_2 "Rx1518Byte_2"
+#define MIB_RX1518BYTE_2_ID 45
+#define MIB_RX1518BYTE_2_OFFSET (MIB_RX1518BYTE_OFFSET + 0x400)
+#define MIB_RX1518BYTE_2_E_LENGTH 4
+#define MIB_RX1518BYTE_2_E_OFFSET 0xa8
+#define MIB_RX1518BYTE_2_NR_E 6
+
+#define MIB_RXMAXBYTE_2 "RxMaxByte_2"
+#define MIB_RXMAXBYTE_2_ID 46
+#define MIB_RXMAXBYTE_2_OFFSET (MIB_RXMAXBYTE_OFFSET + 0x400)
+#define MIB_RXMAXBYTE_2_E_LENGTH 4
+#define MIB_RXMAXBYTE_2_E_OFFSET 0xa8
+#define MIB_RXMAXBYTE_2_NR_E 6
+
+#define MIB_RXTOOLONG_2 "RxTooLong_2"
+#define MIB_RXTOOLONG_2_ID 47
+#define MIB_RXTOOLONG_2_OFFSET (MIB_RXTOOLONG_OFFSET + 0x400)
+#define MIB_RXTOOLONG_2_E_LENGTH 4
+#define MIB_RXTOOLONG_2_E_OFFSET 0xa8
+#define MIB_RXTOOLONG_2_NR_E 6
+
+#define MIB_RXGOODBYTE_LO_2 "RxGoodByteLo_2"
+#define MIB_RXGOODBYTE_LO_2_ID 48
+#define MIB_RXGOODBYTE_LO_2_OFFSET (MIB_RXGOODBYTE_LO_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_LO_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_RXGOODBYTE_LO_2_NR_E 6
+
+#define MIB_RXGOODBYTE_HI_2 "RxGoodByteHi_2"
+#define MIB_RXGOODBYTE_HI_2_ID 49
+#define MIB_RXGOODBYTE_HI_2_OFFSET (MIB_RXGOODBYTE_HI_OFFSET + 0x400)
+#define MIB_RXGOODBYTE_HI_2_E_LENGTH 4
+#define MIB_RXGOODBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_RXGOODBYTE_HI_2_NR_E 6
+
+#define MIB_RXBADBYTE_LO_2 "RxBadByteLo_2"
+#define MIB_RXBADBYTE_LO_2_ID 50
+#define MIB_RXBADBYTE_LO_2_OFFSET (MIB_RXBADBYTE_LO_OFFSET + 0x400)
+#define MIB_RXBADBYTE_LO_2_E_LENGTH 4
+#define MIB_RXBADBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_RXBADBYTE_LO_2_NR_E 6
+
+#define MIB_RXBADBYTE_HI_2 "RxBadByteHi_2"
+#define MIB_RXBADBYTE_HI_2_ID 51
+#define MIB_RXBADBYTE_HI_2_OFFSET (MIB_RXBADBYTE_HI_OFFSET + 0x400)
+#define MIB_RXBADBYTE_HI_2_E_LENGTH 4
+#define MIB_RXBADBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_RXBADBYTE_HI_2_NR_E 6
+
+#define MIB_RXOVERFLOW_2 "RxOverFlow_2"
+#define MIB_RXOVERFLOW_2_ID 52
+#define MIB_RXOVERFLOW_2_OFFSET (MIB_RXOVERFLOW_OFFSET + 0x400)
+#define MIB_RXOVERFLOW_2_E_LENGTH 4
+#define MIB_RXOVERFLOW_2_E_OFFSET 0xa8
+#define MIB_RXOVERFLOW_2_NR_E 6
+
+#define MIB_FILTERED_2 "Filtered_2"
+#define MIB_FILTERED_2_ID 53
+#define MIB_FILTERED_2_OFFSET (MIB_FILTERED_OFFSET + 0x400)
+#define MIB_FILTERED_2_E_LENGTH 4
+#define MIB_FILTERED_2_E_OFFSET 0xa8
+#define MIB_FILTERED_2_NR_E 6
+
+#define MIB_TXBROAD_2 "TxBroad_2"
+#define MIB_TXBROAD_2_ID 54
+#define MIB_TXBROAD_2_OFFSET (MIB_TXBROAD_OFFSET + 0x400)
+#define MIB_TXBROAD_2_E_LENGTH 4
+#define MIB_TXBROAD_2_E_OFFSET 0xa8
+#define MIB_TXBROAD_2_NR_E 6
+
+#define MIB_TXPAUSE_2 "TxPause_2"
+#define MIB_TXPAUSE_2_ID 55
+#define MIB_TXPAUSE_2_OFFSET (MIB_TXPAUSE_OFFSET + 0x400)
+#define MIB_TXPAUSE_2_E_LENGTH 4
+#define MIB_TXPAUSE_2_E_OFFSET 0xa8
+#define MIB_TXPAUSE_2_NR_E 6
+
+#define MIB_TXMULTI_2 "TxMulti_2"
+#define MIB_TXMULTI_2_ID 56
+#define MIB_TXMULTI_2_OFFSET (MIB_TXMULTI_OFFSET + 0x400)
+#define MIB_TXMULTI_2_E_LENGTH 4
+#define MIB_TXMULTI_2_E_OFFSET 0xa8
+#define MIB_TXMULTI_2_NR_E 6
+
+#define MIB_TXUNDERRUN_2 "TxUnderRun_2"
+#define MIB_TXUNDERRUN_2_ID 57
+#define MIB_TXUNDERRUN_2_OFFSET (MIB_TXUNDERRUN_OFFSET + 0x400)
+#define MIB_TXUNDERRUN_2_E_LENGTH 4
+#define MIB_TXUNDERRUN_2_E_OFFSET 0xa8
+#define MIB_TXUNDERRUN_2_NR_E 6
+
+#define MIB_TX64BYTE_2 "Tx64Byte_2"
+#define MIB_TX64BYTE_2_ID 58
+#define MIB_TX64BYTE_2_OFFSET (MIB_TX64BYTE_OFFSET + 0x400)
+#define MIB_TX64BYTE_2_E_LENGTH 4
+#define MIB_TX64BYTE_2_E_OFFSET 0xa8
+#define MIB_TX64BYTE_2_NR_E 6
+
+#define MIB_TX128BYTE_2 "Tx128Byte_2"
+#define MIB_TX128BYTE_2_ID 59
+#define MIB_TX128BYTE_2_OFFSET (MIB_TX128BYTE_OFFSET + 0x400)
+#define MIB_TX128BYTE_2_E_LENGTH 4
+#define MIB_TX128BYTE_2_E_OFFSET 0xa8
+#define MIB_TX128BYTE_2_NR_E 6
+
+#define MIB_TX256BYTE_2 "Tx256Byte_2"
+#define MIB_TX256BYTE_2_ID 60
+#define MIB_TX256BYTE_2_OFFSET (MIB_TX256BYTE_OFFSET + 0x400)
+#define MIB_TX256BYTE_2_E_LENGTH 4
+#define MIB_TX256BYTE_2_E_OFFSET 0xa8
+#define MIB_TX256BYTE_2_NR_E 6
+
+#define MIB_TX512BYTE_2 "Tx512Byte_2"
+#define MIB_TX512BYTE_2_ID 61
+#define MIB_TX512BYTE_2_OFFSET (MIB_TX512BYTE_OFFSET + 0x400)
+#define MIB_TX512BYTE_2_E_LENGTH 4
+#define MIB_TX512BYTE_2_E_OFFSET 0xa8
+#define MIB_TX512BYTE_2_NR_E 6
+
+#define MIB_TX1024BYTE_2 "Tx1024Byte_2"
+#define MIB_TX1024BYTE_2_ID 62
+#define MIB_TX1024BYTE_2_OFFSET (MIB_TX1024BYTE_OFFSET + 0x400)
+#define MIB_TX1024BYTE_2_E_LENGTH 4
+#define MIB_TX1024BYTE_2_E_OFFSET 0xa8
+#define MIB_TX1024BYTE_2_NR_E 6
+
+#define MIB_TX1518BYTE_2 "Tx1518Byte_2"
+#define MIB_TX1518BYTE_2_ID 62
+#define MIB_TX1518BYTE_2_OFFSET (MIB_TX1518BYTE_OFFSET + 0x400)
+#define MIB_TX1518BYTE_2_E_LENGTH 4
+#define MIB_TX1518BYTE_2_E_OFFSET 0xa8
+#define MIB_TX1518BYTE_2_NR_E 6
+
+#define MIB_TXMAXBYTE_2 "TxMaxByte_2"
+#define MIB_TXMAXBYTE_2_ID 63
+#define MIB_TXMAXBYTE_2_OFFSET (MIB_TXMAXBYTE_OFFSET + 0x400)
+#define MIB_TXMAXBYTE_2_E_LENGTH 4
+#define MIB_TXMAXBYTE_2_E_OFFSET 0xa8
+#define MIB_TXMAXBYTE_2_NR_E 6
+
+#define MIB_TXOVERSIZE_2 "TxOverSize_2"
+#define MIB_TXOVERSIZE_2_ID 64
+#define MIB_TXOVERSIZE_2_OFFSET (MIB_TXOVERSIZE_OFFSET + 0x400)
+#define MIB_TXOVERSIZE_2_E_LENGTH 4
+#define MIB_TXOVERSIZE_2_E_OFFSET 0xa8
+#define MIB_TXOVERSIZE_2_NR_E 6
+
+#define MIB_TXBYTE_LO_2 "TxByteLo_2"
+#define MIB_TXBYTE_LO_2_ID 65
+#define MIB_TXBYTE_LO_2_OFFSET (MIB_TXBYTE_LO_OFFSET + 0x400)
+#define MIB_TXBYTE_LO_2_E_LENGTH 4
+#define MIB_TXBYTE_LO_2_E_OFFSET 0xa8
+#define MIB_TXBYTE_LO_2_NR_E 6
+
+#define MIB_TXBYTE_HI_2 "TxByteHi_2"
+#define MIB_TXBYTE_HI_2_ID 66
+#define MIB_TXBYTE_HI_2_OFFSET (MIB_TXBYTE_HI_OFFSET + 0x400)
+#define MIB_TXBYTE_HI_2_E_LENGTH 4
+#define MIB_TXBYTE_HI_2_E_OFFSET 0xa8
+#define MIB_TXBYTE_HI_2_NR_E 6
+
+#define MIB_TXCOLLISION_2 "TxCollision_2"
+#define MIB_TXCOLLISION_2_ID 67
+#define MIB_TXCOLLISION_2_OFFSET (MIB_TXCOLLISION_OFFSET + 0x400)
+#define MIB_TXCOLLISION_2_E_LENGTH 4
+#define MIB_TXCOLLISION_2_E_OFFSET 0xa8
+#define MIB_TXCOLLISION_2_NR_E 6
+
+#define MIB_TXABORTCOL_2 "TxAbortCol_2"
+#define MIB_TXABORTCOL_2_ID 68
+#define MIB_TXABORTCOL_2_OFFSET (MIB_TXABORTCOL_OFFSET + 0x400)
+#define MIB_TXABORTCOL_2_E_LENGTH 4
+#define MIB_TXABORTCOL_2_E_OFFSET 0xa8
+#define MIB_TXABORTCOL_2_NR_E 6
+
+#define MIB_TXMULTICOL_2 "TxMultiCol_2"
+#define MIB_TXMULTICOL_2_ID 69
+#define MIB_TXMULTICOL_2_OFFSET (MIB_TXMULTICOL_OFFSET + 0x400)
+#define MIB_TXMULTICOL_2_E_LENGTH 4
+#define MIB_TXMULTICOL_2_E_OFFSET 0xa8
+#define MIB_TXMULTICOL_2_NR_E 6
+
+#define MIB_TXSINGALCOL_2 "TxSingalCol_2"
+#define MIB_TXSINGALCOL_2_ID 70
+#define MIB_TXSINGALCOL_2_OFFSET (MIB_TXSINGALCOL_OFFSET + 0x400)
+#define MIB_TXSINGALCOL_2_E_LENGTH 4
+#define MIB_TXSINGALCOL_2_E_OFFSET 0xa8
+#define MIB_TXSINGALCOL_2_NR_E 6
+
+#define MIB_TXEXCDEFER_2 "TxExcDefer_2"
+#define MIB_TXEXCDEFER_2_ID 71
+#define MIB_TXEXCDEFER_2_OFFSET (MIB_TXEXCDEFER_OFFSET + 0x400)
+#define MIB_TXEXCDEFER_2_E_LENGTH 4
+#define MIB_TXEXCDEFER_2_E_OFFSET 0xa8
+#define MIB_TXEXCDEFER_2_NR_E 6
+
+#define MIB_TXDEFER_2 "TxDefer_2"
+#define MIB_TXDEFER_2_ID 72
+#define MIB_TXDEFER_2_OFFSET (MIB_TXDEFER_OFFSET + 0x400)
+#define MIB_TXDEFER_2_E_LENGTH 4
+#define MIB_TXDEFER_2_E_OFFSET 0xa8
+#define MIB_TXDEFER_2_NR_E 6
+
+#define MIB_TXLATECOL_2 "TxLateCol_2"
+#define MIB_TXLATECOL_2_ID 73
+#define MIB_TXLATECOL_2_OFFSET (MIB_TXLATECOL_OFFSET + 0x400)
+#define MIB_TXLATECOL_2_E_LENGTH 4
+#define MIB_TXLATECOL_2_E_OFFSET 0xa8
+#define MIB_TXLATECOL_2_NR_E 6
+#endif
+
+
+
+
+#define ACL_RSLT0 "aclact0"
+#define ACL_RSLT0_ID 13
+#define ACL_RSLT0_OFFSET 0x58000
+#define ACL_RSLT0_E_LENGTH 4
+#define ACL_RSLT0_E_OFFSET 0x20
+#define ACL_RSLT0_NR_E 32
+
+#define MATCH_CNT "aclact_cnt"
+#define ACL_RSLT0_MATCH_CNT_BOFFSET 0
+#define ACL_RSLT0_MATCH_CNT_BLEN 32
+#define ACL_RSLT0_MATCH_CNT_FLAG HSL_RW
+
+
+
+
+#define ACL_RSLT1 "aclact1"
+#define ACL_RSLT1_ID 13
+#define ACL_RSLT1_OFFSET 0x58004
+#define ACL_RSLT1_E_LENGTH 4
+#define ACL_RSLT1_E_OFFSET 0x20
+#define ACL_RSLT1_NR_E 32
+
+#define MIRR_EN "aclact1_mirr"
+#define ACL_RSLT1_MIRR_EN_BOFFSET 31
+#define ACL_RSLT1_MIRR_EN_BLEN 1
+#define ACL_RSLT1_MIRR_EN_FLAG HSL_RW
+
+#define STAG_CHG_EN "aclact1_rdcpu"
+#define ACL_RSLT1_STAG_CHG_EN_BOFFSET 30
+#define ACL_RSLT1_STAG_CHG_EN_BLEN 1
+#define ACL_RSLT1_STAG_CHG_EN_FLAG HSL_RW
+
+#define VID_MEM_EN "aclact1_rdcpu"
+#define ACL_RSLT1_VID_MEM_EN_BOFFSET 29
+#define ACL_RSLT1_VID_MEM_EN_BLEN 1
+#define ACL_RSLT1_VID_MEM_EN_FLAG HSL_RW
+
+#define DES_PORT_EN "aclact1_rdcpu"
+#define ACL_RSLT1_DES_PORT_EN_BOFFSET 28
+#define ACL_RSLT1_DES_PORT_EN_BLEN 1
+#define ACL_RSLT1_DES_PORT_EN_FLAG HSL_RW
+
+#define PORT_MEM "aclact1_rdcpu"
+#define ACL_RSLT1_PORT_MEM_BOFFSET 20
+#define ACL_RSLT1_PORT_MEM_BLEN 7
+#define ACL_RSLT1_PORT_MEM_FLAG HSL_RW
+
+#define REMARK_PRI_QU "aclact1_rdcpu"
+#define ACL_RSLT1_REMARK_PRI_QU_BOFFSET 19
+#define ACL_RSLT1_REMARK_PRI_QU_BLEN 1
+#define ACL_RSLT1_REMARK_PRI_QU_FLAG HSL_RW
+
+#define DOT1P "aclact1_rdcpu"
+#define ACL_RSLT1_DOT1P_BOFFSET 16
+#define ACL_RSLT1_DOT1P_BLEN 3
+#define ACL_RSLT1_DOT1P_FLAG HSL_RW
+
+#define PRI_QU "aclact1_rdcpu"
+#define ACL_RSLT1_PRI_QU_BOFFSET 14
+#define ACL_RSLT1_PRI_QU_BLEN 2
+#define ACL_RSLT1_PRI_QU_FLAG HSL_RW
+
+#define REMARK_DOT1P "aclact1_rdcpu"
+#define ACL_RSLT1_REMARK_DOT1P_BOFFSET 13
+#define ACL_RSLT1_REMARK_DOT1P_BLEN 1
+#define ACL_RSLT1_REMARK_DOT1P_FLAG HSL_RW
+
+#define CHG_VID_EN "aclact1_rdcpu"
+#define ACL_RSLT1_CHG_VID_EN_BOFFSET 12
+#define ACL_RSLT1_CHG_VID_EN_BLEN 1
+#define ACL_RSLT1_CHG_VID_EN_FLAG HSL_RW
+
+#define VID "aclact1_rdcpu"
+#define ACL_RSLT1_VID_BOFFSET 0
+#define ACL_RSLT1_VID_BLEN 12
+#define ACL_RSLT1_VID_FLAG HSL_RW
+
+
+
+
+#define ACL_RSLT2 "aclact2"
+#define ACL_RSLT2_ID 13
+#define ACL_RSLT2_OFFSET 0x58008
+#define ACL_RSLT2_E_LENGTH 4
+#define ACL_RSLT2_E_OFFSET 0x20
+#define ACL_RSLT2_NR_E 32
+
+#define RDTCPU "aclact2_rdtpu"
+#define ACL_RSLT2_RDTCPU_BOFFSET 1
+#define ACL_RSLT2_RDTCPU_BLEN 1
+#define ACL_RSLT2_RDTCPU_FLAG HSL_RW
+
+#define CPYCPU "aclact2_cpcpu"
+#define ACL_RSLT2_CPYCPU_BOFFSET 0
+#define ACL_RSLT2_CPYCPU_BLEN 1
+#define ACL_RSLT2_CPYCPU_FLAG HSL_RW
+
+
+
+
+
+#define RUL_SLCT0 "rulslct0"
+#define RUL_SLCT0_ID 13
+#define RUL_SLCT0_OFFSET 0x58800
+#define RUL_SLCT0_E_LENGTH 4
+#define RUL_SLCT0_E_OFFSET 0x20
+#define RUL_SLCT0_NR_E 32
+
+#define ADDR3_EN "rulslct_addr3en"
+#define RUL_SLCT0_ADDR3_EN_BOFFSET 3
+#define RUL_SLCT0_ADDR3_EN_BLEN 1
+#define RUL_SLCT0_ADDR3_EN_FLAG HSL_RW
+
+#define ADDR2_EN "rulslct_addr2en"
+#define RUL_SLCT0_ADDR2_EN_BOFFSET 2
+#define RUL_SLCT0_ADDR2_EN_BLEN 1
+#define RUL_SLCT0_ADDR2_EN_FLAG HSL_RW
+
+#define ADDR1_EN "rulslct_addr1en"
+#define RUL_SLCT0_ADDR1_EN_BOFFSET 1
+#define RUL_SLCT0_ADDR1_EN_BLEN 1
+#define RUL_SLCT0_ADDR1_EN_FLAG HSL_RW
+
+#define ADDR0_EN "rulslct_addr0en"
+#define RUL_SLCT0_ADDR0_EN_BOFFSET 0
+#define RUL_SLCT0_ADDR0_EN_BLEN 1
+#define RUL_SLCT0_ADDR0_EN_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT1 "rulslct1"
+#define RUL_SLCT1_ID 13
+#define RUL_SLCT1_OFFSET 0x58804
+#define RUL_SLCT1_E_LENGTH 4
+#define RUL_SLCT1_E_OFFSET 0x20
+#define RUL_SLCT1_NR_E 32
+
+#define ADDR0 "rulslct1_addr0"
+#define RUL_SLCT1_ADDR0_BOFFSET 0
+#define RUL_SLCT1_ADDR0_BLEN 5
+#define RUL_SLCT1_ADDR0_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT2 "rulslct2"
+#define RUL_SLCT2_ID 13
+#define RUL_SLCT2_OFFSET 0x58808
+#define RUL_SLCT2_E_LENGTH 4
+#define RUL_SLCT2_E_OFFSET 0x20
+#define RUL_SLCT2_NR_E 32
+
+#define ADDR1 "rulslct2_addr1"
+#define RUL_SLCT2_ADDR1_BOFFSET 0
+#define RUL_SLCT2_ADDR1_BLEN 5
+#define RUL_SLCT2_ADDR1_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT3 "rulslct3"
+#define RUL_SLCT3_ID 13
+#define RUL_SLCT3_OFFSET 0x5880c
+#define RUL_SLCT3_E_LENGTH 4
+#define RUL_SLCT3_E_OFFSET 0x20
+#define RUL_SLCT3_NR_E 32
+
+#define ADDR2 "rulslct3_addr2"
+#define RUL_SLCT3_ADDR2_BOFFSET 0
+#define RUL_SLCT3_ADDR2_BLEN 5
+#define RUL_SLCT3_ADDR2_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT4 "rulslct4"
+#define RUL_SLCT4_ID 13
+#define RUL_SLCT4_OFFSET 0x58810
+#define RUL_SLCT4_E_LENGTH 4
+#define RUL_SLCT4_E_OFFSET 0x20
+#define RUL_SLCT4_NR_E 32
+
+#define ADDR3 "rulslct4_addr3"
+#define RUL_SLCT4_ADDR3_BOFFSET 0
+#define RUL_SLCT4_ADDR3_BLEN 5
+#define RUL_SLCT4_ADDR3_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT5 "rulslct5"
+#define RUL_SLCT5_ID 13
+#define RUL_SLCT5_OFFSET 0x58814
+#define RUL_SLCT5_E_LENGTH 4
+#define RUL_SLCT5_E_OFFSET 0x20
+#define RUL_SLCT5_NR_E 32
+
+#define SRC_PT "rulslct5_srcpt"
+#define RUL_SLCT5_SRC_PT_BOFFSET 0
+#define RUL_SLCT5_SRC_PT_BLEN 7
+#define RUL_SLCT5_SRC_PT_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT6 "rulslct6"
+#define RUL_SLCT6_ID 13
+#define RUL_SLCT6_OFFSET 0x58818
+#define RUL_SLCT6_E_LENGTH 4
+#define RUL_SLCT6_E_OFFSET 0x20
+#define RUL_SLCT6_NR_E 32
+
+#define RULE_LEN "rulslct6_rulelen"
+#define RUL_SLCT6_RULE_LEN_BOFFSET 0
+#define RUL_SLCT6_RULE_LEN_BLEN 8
+#define RUL_SLCT6_RULE_LEN_FLAG HSL_RW
+
+
+
+
+#define RUL_SLCT7 "rulslct7"
+#define RUL_SLCT7_ID 13
+#define RUL_SLCT7_OFFSET 0x5881c
+#define RUL_SLCT7_E_LENGTH 4
+#define RUL_SLCT7_E_OFFSET 0x20
+#define RUL_SLCT7_NR_E 32
+
+#define RULE_TYP "rulslct7_ruletyp"
+#define RUL_SLCT7_RULE_TYP_BOFFSET 0
+#define RUL_SLCT7_RULE_TYP_BLEN 3
+#define RUL_SLCT7_RULE_TYP_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V0 "macrv0"
+#define MAC_RUL_V0_ID 13
+#define MAC_RUL_V0_OFFSET 0x58400
+#define MAC_RUL_V0_E_LENGTH 4
+#define MAC_RUL_V0_E_OFFSET 0x20
+#define MAC_RUL_V0_NR_E 32
+
+#define DAV_BYTE2 "macrv0_dav2"
+#define MAC_RUL_V0_DAV_BYTE2_BOFFSET 24
+#define MAC_RUL_V0_DAV_BYTE2_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE2_FLAG HSL_RW
+
+#define DAV_BYTE3 "macrv0_dav3"
+#define MAC_RUL_V0_DAV_BYTE3_BOFFSET 16
+#define MAC_RUL_V0_DAV_BYTE3_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE3_FLAG HSL_RW
+
+#define DAV_BYTE4 "macrv0_dav4"
+#define MAC_RUL_V0_DAV_BYTE4_BOFFSET 8
+#define MAC_RUL_V0_DAV_BYTE4_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE4_FLAG HSL_RW
+
+#define DAV_BYTE5 "macrv0_dav5"
+#define MAC_RUL_V0_DAV_BYTE5_BOFFSET 0
+#define MAC_RUL_V0_DAV_BYTE5_BLEN 8
+#define MAC_RUL_V0_DAV_BYTE5_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V1 "macrv1"
+#define MAC_RUL_V1_ID 13
+#define MAC_RUL_V1_OFFSET 0x58404
+#define MAC_RUL_V1_E_LENGTH 4
+#define MAC_RUL_V1_E_OFFSET 0x20
+#define MAC_RUL_V1_NR_E 32
+
+#define SAV_BYTE4 "macrv1_sav4"
+#define MAC_RUL_V1_SAV_BYTE4_BOFFSET 24
+#define MAC_RUL_V1_SAV_BYTE4_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE4_FLAG HSL_RW
+
+#define SAV_BYTE5 "macrv1_sav5"
+#define MAC_RUL_V1_SAV_BYTE5_BOFFSET 16
+#define MAC_RUL_V1_SAV_BYTE5_BLEN 8
+#define MAC_RUL_V1_SAV_BYTE5_FLAG HSL_RW
+
+#define DAV_BYTE0 "macrv1_dav0"
+#define MAC_RUL_V1_DAV_BYTE0_BOFFSET 8
+#define MAC_RUL_V1_DAV_BYTE0_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE0_FLAG HSL_RW
+
+#define DAV_BYTE1 "macrv1_dav1"
+#define MAC_RUL_V1_DAV_BYTE1_BOFFSET 0
+#define MAC_RUL_V1_DAV_BYTE1_BLEN 8
+#define MAC_RUL_V1_DAV_BYTE1_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V2 "macrv2"
+#define MAC_RUL_V2_ID 13
+#define MAC_RUL_V2_OFFSET 0x58408
+#define MAC_RUL_V2_E_LENGTH 4
+#define MAC_RUL_V2_E_OFFSET 0x20
+#define MAC_RUL_V2_NR_E 32
+
+#define SAV_BYTE0 "macrv2_sav0"
+#define MAC_RUL_V2_SAV_BYTE0_BOFFSET 24
+#define MAC_RUL_V2_SAV_BYTE0_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE0_FLAG HSL_RW
+
+#define SAV_BYTE1 "macrv2_sav1"
+#define MAC_RUL_V2_SAV_BYTE1_BOFFSET 16
+#define MAC_RUL_V2_SAV_BYTE1_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE1_FLAG HSL_RW
+
+#define SAV_BYTE2 "macrv2_sav2"
+#define MAC_RUL_V2_SAV_BYTE2_BOFFSET 8
+#define MAC_RUL_V2_SAV_BYTE2_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE2_FLAG HSL_RW
+
+#define SAV_BYTE3 "macrv2_sav3"
+#define MAC_RUL_V2_SAV_BYTE3_BOFFSET 0
+#define MAC_RUL_V2_SAV_BYTE3_BLEN 8
+#define MAC_RUL_V2_SAV_BYTE3_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V3 "macrv3"
+#define MAC_RUL_V3_ID 13
+#define MAC_RUL_V3_OFFSET 0x5840c
+#define MAC_RUL_V3_E_LENGTH 4
+#define MAC_RUL_V3_E_OFFSET 0x20
+#define MAC_RUL_V3_NR_E 32
+
+#define ETHTYPV "macrv3_ethtypv"
+#define MAC_RUL_V3_ETHTYPV_BOFFSET 16
+#define MAC_RUL_V3_ETHTYPV_BLEN 16
+#define MAC_RUL_V3_ETHTYPV_FLAG HSL_RW
+
+#define VLANPRIV "macrv3_vlanpriv"
+#define MAC_RUL_V3_VLANPRIV_BOFFSET 13
+#define MAC_RUL_V3_VLANPRIV_BLEN 3
+#define MAC_RUL_V3_VLANPRIV_FLAG HSL_RW
+
+#define VLANCFIV "macrv3_vlancfiv"
+#define MAC_RUL_V3_VLANCFIV_BOFFSET 12
+#define MAC_RUL_V3_VLANCFIV_BLEN 1
+#define MAC_RUL_V3_VLANCFIV_FLAG HSL_RW
+
+#define VLANIDV "macrv3_vlanidv"
+#define MAC_RUL_V3_VLANIDV_BOFFSET 0
+#define MAC_RUL_V3_VLANIDV_BLEN 12
+#define MAC_RUL_V3_VLANIDV_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_V4 "macrv4"
+#define MAC_RUL_V4_ID 13
+#define MAC_RUL_V4_OFFSET 0x58410
+#define MAC_RUL_V4_E_LENGTH 4
+#define MAC_RUL_V4_E_OFFSET 0x20
+#define MAC_RUL_V4_NR_E 32
+
+#define TAGGEDM "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDM_BOFFSET 7
+#define MAC_RUL_V4_TAGGEDM_BLEN 1
+#define MAC_RUL_V4_TAGGEDM_FLAG HSL_RW
+
+#define TAGGEDV "macrv4_vlanid"
+#define MAC_RUL_V4_TAGGEDV_BOFFSET 6
+#define MAC_RUL_V4_TAGGEDV_BLEN 1
+#define MAC_RUL_V4_TAGGEDV_FLAG HSL_RW
+
+#define VIDMSK "macrv4_vidmsk"
+#define MAC_RUL_V4_VIDMSK_BOFFSET 0
+#define MAC_RUL_V4_VIDMSK_BLEN 1
+#define MAC_RUL_V4_VIDMSK_FLAG HSL_RW
+
+
+
+
+
+#define MAC_RUL_M0 "macrv0"
+#define MAC_RUL_M0_ID 13
+#define MAC_RUL_M0_OFFSET 0x58c00
+#define MAC_RUL_M0_E_LENGTH 4
+#define MAC_RUL_M0_E_OFFSET 0x20
+#define MAC_RUL_M0_NR_E 32
+
+#define DAM_BYTE2 "macrv0_dam2"
+#define MAC_RUL_M0_DAM_BYTE2_BOFFSET 24
+#define MAC_RUL_M0_DAM_BYTE2_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE2_FLAG HSL_RW
+
+#define DAM_BYTE3 "macrv0_dam3"
+#define MAC_RUL_M0_DAM_BYTE3_BOFFSET 16
+#define MAC_RUL_M0_DAM_BYTE3_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE3_FLAG HSL_RW
+
+#define DAM_BYTE4 "macrv0_dam4"
+#define MAC_RUL_M0_DAM_BYTE4_BOFFSET 8
+#define MAC_RUL_M0_DAM_BYTE4_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE4_FLAG HSL_RW
+
+#define DAM_BYTE5 "macrv0_dam5"
+#define MAC_RUL_M0_DAM_BYTE5_BOFFSET 0
+#define MAC_RUL_M0_DAM_BYTE5_BLEN 8
+#define MAC_RUL_M0_DAM_BYTE5_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M1 "macrm1"
+#define MAC_RUL_M1_ID 13
+#define MAC_RUL_M1_OFFSET 0x58c04
+#define MAC_RUL_M1_E_LENGTH 4
+#define MAC_RUL_M1_E_OFFSET 0x20
+#define MAC_RUL_M1_NR_E 32
+
+#define SAM_BYTE4 "macrm1_sam4"
+#define MAC_RUL_M1_SAM_BYTE4_BOFFSET 24
+#define MAC_RUL_M1_SAM_BYTE4_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE4_FLAG HSL_RW
+
+#define SAM_BYTE5 "macrm1_sam5"
+#define MAC_RUL_M1_SAM_BYTE5_BOFFSET 16
+#define MAC_RUL_M1_SAM_BYTE5_BLEN 8
+#define MAC_RUL_M1_SAM_BYTE5_FLAG HSL_RW
+
+#define DAM_BYTE0 "macrm1_dam0"
+#define MAC_RUL_M1_DAM_BYTE0_BOFFSET 8
+#define MAC_RUL_M1_DAM_BYTE0_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE0_FLAG HSL_RW
+
+#define DAM_BYTE1 "macrm1_dam1"
+#define MAC_RUL_M1_DAM_BYTE1_BOFFSET 0
+#define MAC_RUL_M1_DAM_BYTE1_BLEN 8
+#define MAC_RUL_M1_DAM_BYTE1_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M2 "macrm2"
+#define MAC_RUL_M2_ID 13
+#define MAC_RUL_M2_OFFSET 0x58c08
+#define MAC_RUL_M2_E_LENGTH 4
+#define MAC_RUL_M2_E_OFFSET 0x20
+#define MAC_RUL_M2_NR_E 32
+
+#define SAM_BYTE0 "macrm2_sam0"
+#define MAC_RUL_M2_SAM_BYTE0_BOFFSET 24
+#define MAC_RUL_M2_SAM_BYTE0_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE0_FLAG HSL_RW
+
+#define SAM_BYTE1 "macrm2_samv1"
+#define MAC_RUL_M2_SAM_BYTE1_BOFFSET 16
+#define MAC_RUL_M2_SAM_BYTE1_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE1_FLAG HSL_RW
+
+#define SAM_BYTE2 "macrm2_sam2"
+#define MAC_RUL_M2_SAM_BYTE2_BOFFSET 8
+#define MAC_RUL_M2_SAM_BYTE2_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE2_FLAG HSL_RW
+
+#define SAM_BYTE3 "macrm2_sam3"
+#define MAC_RUL_M2_SAM_BYTE3_BOFFSET 0
+#define MAC_RUL_M2_SAM_BYTE3_BLEN 8
+#define MAC_RUL_M2_SAM_BYTE3_FLAG HSL_RW
+
+
+
+
+#define MAC_RUL_M3 "macrv3"
+#define MAC_RUL_M3_ID 13
+#define MAC_RUL_M3_OFFSET 0x58c0c
+#define MAC_RUL_M3_E_LENGTH 4
+#define MAC_RUL_M3_E_OFFSET 0x20
+#define MAC_RUL_M3_NR_E 32
+
+#define ETHTYPM "macrm3_ethtypm"
+#define MAC_RUL_M3_ETHTYPM_BOFFSET 16
+#define MAC_RUL_M3_ETHTYPM_BLEN 16
+#define MAC_RUL_M3_ETHTYPM_FLAG HSL_RW
+
+#define VLANPRIM "macrm3_vlanprim"
+#define MAC_RUL_M3_VLANPRIM_BOFFSET 13
+#define MAC_RUL_M3_VLANPRIM_BLEN 3
+#define MAC_RUL_M3_VLANPRIM_FLAG HSL_RW
+
+#define VLANCFIM "macrm3_vlancfim"
+#define MAC_RUL_M3_VLANCFIM_BOFFSET 12
+#define MAC_RUL_M3_VLANCFIM_BLEN 1
+#define MAC_RUL_M3_VLANCFIM_FLAG HSL_RW
+
+#define VLANIDM "macrm3_vlanidm"
+#define MAC_RUL_M3_VLANIDM_BOFFSET 0
+#define MAC_RUL_M3_VLANIDM_BLEN 12
+#define MAC_RUL_M3_VLANIDM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V0 "ip4v0"
+#define IP4_RUL_V0_ID 13
+#define IP4_RUL_V0_OFFSET 0x58400
+#define IP4_RUL_V0_E_LENGTH 4
+#define IP4_RUL_V0_E_OFFSET 0x20
+#define IP4_RUL_V0_NR_E 32
+
+#define DIPV "ip4v0_dipv"
+#define IP4_RUL_V0_DIPV_BOFFSET 0
+#define IP4_RUL_V0_DIPV_BLEN 32
+#define IP4_RUL_V0_DIPV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V1 "ip4v1"
+#define IP4_RUL_V1_ID 13
+#define IP4_RUL_V1_OFFSET 0x58404
+#define IP4_RUL_V1_E_LENGTH 4
+#define IP4_RUL_V1_E_OFFSET 0x20
+#define IP4_RUL_V1_NR_E 32
+
+#define SIPV "ip4v1_sipv"
+#define IP4_RUL_V1_SIPV_BOFFSET 0
+#define IP4_RUL_V1_SIPV_BLEN 32
+#define IP4_RUL_V1_SIPV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V2 "ip4v2"
+#define IP4_RUL_V2_ID 13
+#define IP4_RUL_V2_OFFSET 0x58408
+#define IP4_RUL_V2_E_LENGTH 4
+#define IP4_RUL_V2_E_OFFSET 0x20
+#define IP4_RUL_V2_NR_E 32
+
+#define IP4PROTV "ip4v2_protv"
+#define IP4_RUL_V2_IP4PROTV_BOFFSET 0
+#define IP4_RUL_V2_IP4PROTV_BLEN 8
+#define IP4_RUL_V2_IP4PROTV_FLAG HSL_RW
+
+#define IP4DSCPV "ip4v2_dscpv"
+#define IP4_RUL_V2_IP4DSCPV_BOFFSET 8
+#define IP4_RUL_V2_IP4DSCPV_BLEN 8
+#define IP4_RUL_V2_IP4DSCPV_FLAG HSL_RW
+
+#define IP4DPORTV "ip4v2_dportv"
+#define IP4_RUL_V2_IP4DPORTV_BOFFSET 16
+#define IP4_RUL_V2_IP4DPORTV_BLEN 16
+#define IP4_RUL_V2_IP4DPORTV_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_V3 "ip4v3"
+#define IP4_RUL_V3_ID 13
+#define IP4_RUL_V3_OFFSET 0x5840c
+#define IP4_RUL_V3_E_LENGTH 4
+#define IP4_RUL_V3_E_OFFSET 0x20
+#define IP4_RUL_V3_NR_E 32
+
+#define IP4SPORTV "ip4v3_sportv"
+#define IP4_RUL_V3_IP4SPORTV_BOFFSET 0
+#define IP4_RUL_V3_IP4SPORTV_BLEN 16
+#define IP4_RUL_V3_IP4SPORTV_FLAG HSL_RW
+
+
+#define IP4_RUL_V4 "ip4v2"
+#define IP4_RUL_V4_ID 13
+#define IP4_RUL_V4_OFFSET 0x58410
+#define IP4_RUL_V4_E_LENGTH 4
+#define IP4_RUL_V4_E_OFFSET 0x20
+#define IP4_RUL_V4_NR_E 32
+
+#define IP4_INPT "ip4rv4_inpt"
+#define IP4_RUL_V4_IP4_INPT_BOFFSET 0
+#define IP4_RUL_V4_IP4_INPT_BLEN 6
+#define IP4_RUL_V4_IP4_INPT_FLAG HSL_RW
+
+
+
+
+
+
+#define IP4_RUL_M0 "ip4m0"
+#define IP4_RUL_M0_ID 13
+#define IP4_RUL_M0_OFFSET 0x58c00
+#define IP4_RUL_M0_E_LENGTH 4
+#define IP4_RUL_M0_E_OFFSET 0x20
+#define IP4_RUL_M0_NR_E 32
+
+#define DIPM "ip4m0_dipm"
+#define IP4_RUL_M0_DIPM_BOFFSET 0
+#define IP4_RUL_M0_DIPM_BLEN 32
+#define IP4_RUL_M0_DIPM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M1 "ip4m1"
+#define IP4_RUL_M1_ID 13
+#define IP4_RUL_M1_OFFSET 0x58c04
+#define IP4_RUL_M1_E_LENGTH 4
+#define IP4_RUL_M1_E_OFFSET 0x20
+#define IP4_RUL_M1_NR_E 32
+
+#define SIPM "ip4m1_sipm"
+#define IP4_RUL_M1_SIPM_BOFFSET 0
+#define IP4_RUL_M1_SIPM_BLEN 32
+#define IP4_RUL_M1_SIPM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M2 "ip4m2"
+#define IP4_RUL_M2_ID 13
+#define IP4_RUL_M2_OFFSET 0x58c08
+#define IP4_RUL_M2_E_LENGTH 4
+#define IP4_RUL_M2_E_OFFSET 0x20
+#define IP4_RUL_M2_NR_E 32
+
+#define IP4PROTM "ip4m2_protm"
+#define IP4_RUL_M2_IP4PROTM_BOFFSET 0
+#define IP4_RUL_M2_IP4PROTM_BLEN 8
+#define IP4_RUL_M2_IP4PROTM_FLAG HSL_RW
+
+#define IP4DSCPM "ip4m2_dscpm"
+#define IP4_RUL_M2_IP4DSCPM_BOFFSET 8
+#define IP4_RUL_M2_IP4DSCPM_BLEN 8
+#define IP4_RUL_M2_IP4DSCPM_FLAG HSL_RW
+
+#define IP4DPORTM "ip4m2_dportm"
+#define IP4_RUL_M2_IP4DPORTM_BOFFSET 16
+#define IP4_RUL_M2_IP4DPORTM_BLEN 16
+#define IP4_RUL_M2_IP4DPORTM_FLAG HSL_RW
+
+
+
+
+#define IP4_RUL_M3 "ip4m3"
+#define IP4_RUL_M3_ID 13
+#define IP4_RUL_M3_OFFSET 0x58c0c
+#define IP4_RUL_M3_E_LENGTH 4
+#define IP4_RUL_M3_E_OFFSET 0x20
+#define IP4_RUL_M3_NR_E 32
+
+#define IP4SPORTM "ip4m3_sportm"
+#define IP4_RUL_M3_IP4SPORTM_BOFFSET 0
+#define IP4_RUL_M3_IP4SPORTM_BLEN 16
+#define IP4_RUL_M3_IP4SPORTM_FLAG HSL_RW
+
+#define IP4SPORTM_EN "ip4m3_sportmen"
+#define IP4_RUL_M3_IP4SPORTM_EN_BOFFSET 16
+#define IP4_RUL_M3_IP4SPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4SPORTM_EN_FLAG HSL_RW
+
+#define IP4DPORTM_EN "ip4m3_dportmen"
+#define IP4_RUL_M3_IP4DPORTM_EN_BOFFSET 17
+#define IP4_RUL_M3_IP4DPORTM_EN_BLEN 1
+#define IP4_RUL_M3_IP4DPORTM_EN_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V0 "ip6r1v0"
+#define IP6_RUL1_V0_ID 13
+#define IP6_RUL1_V0_OFFSET 0x58400
+#define IP6_RUL1_V0_E_LENGTH 4
+#define IP6_RUL1_V0_E_OFFSET 0x20
+#define IP6_RUL1_V0_NR_E 32
+
+#define IP6_DIPV0 "ip6r1v0_dipv0"
+#define IP6_RUL1_V0_IP6_DIPV0_BOFFSET 0
+#define IP6_RUL1_V0_IP6_DIPV0_BLEN 32
+#define IP6_RUL1_V0_IP6_DIPV0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V1 "ip6r1v1"
+#define IP6_RUL1_V1_ID 13
+#define IP6_RUL1_V1_OFFSET 0x58404
+#define IP6_RUL1_V1_E_LENGTH 4
+#define IP6_RUL1_V1_E_OFFSET 0x20
+#define IP6_RUL1_V1_NR_E 32
+
+#define IP6_DIPV1 "ip6r1v1_dipv1"
+#define IP6_RUL1_V1_IP6_DIPV1_BOFFSET 0
+#define IP6_RUL1_V1_IP6_DIPv1_BLEN 32
+#define IP6_RUL1_V1_IP6_DIPV1_FLAG HSL_RW
+
+
+
+#define IP6_RUL1_V2 "ip6r1v2"
+#define IP6_RUL1_V2_ID 13
+#define IP6_RUL1_V2_OFFSET 0x58408
+#define IP6_RUL1_V2_E_LENGTH 4
+#define IP6_RUL1_V2_E_OFFSET 0x20
+#define IP6_RUL1_V2_NR_E 32
+
+#define IP6_DIPV2 "ip6r1v2_dipv2"
+#define IP6_RUL1_V2_IP6_DIPV2_BOFFSET 0
+#define IP6_RUL1_V2_IP6_DIPv2_BLEN 32
+#define IP6_RUL1_V2_IP6_DIPV2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V3 "ip6r1v3"
+#define IP6_RUL1_V3_ID 13
+#define IP6_RUL1_V3_OFFSET 0x5840c
+#define IP6_RUL1_V3_E_LENGTH 4
+#define IP6_RUL1_V3_E_OFFSET 0x20
+#define IP6_RUL1_V3_NR_E 32
+
+#define IP6_DIPV3 "ip6r1v3_dipv3"
+#define IP6_RUL1_V3_IP6_DIPV3_BOFFSET 0
+#define IP6_RUL1_V3_IP6_DIPv3_BLEN 32
+#define IP6_RUL1_V3_IP6_DIPV3_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_V4 "ip6r1v4"
+#define IP6_RUL1_V4_ID 13
+#define IP6_RUL1_V4_OFFSET 0x58410
+#define IP6_RUL1_V4_E_LENGTH 4
+#define IP6_RUL1_V4_E_OFFSET 0x20
+#define IP6_RUL1_V4_NR_E 32
+
+#define IP6_RUL1_INPT "ip6r1v4_inpt"
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BOFFSET 0
+#define IP6_RUL1_V4_IP6_RUL1_INPT_BLEN 6
+#define IP6_RUL1_V4_IP6_RUL1_INPT_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL1_M0 "ip6r1m0"
+#define IP6_RUL1_M0_ID 13
+#define IP6_RUL1_M0_OFFSET 0x58c00
+#define IP6_RUL1_M0_E_LENGTH 4
+#define IP6_RUL1_M0_E_OFFSET 0x20
+#define IP6_RUL1_M0_NR_E 32
+
+#define IP6_DIPM0 "ip6r1m0_dipm0"
+#define IP6_RUL1_M0_IP6_DIPM0_BOFFSET 0
+#define IP6_RUL1_M0_IP6_DIPM0_BLEN 32
+#define IP6_RUL1_M0_IP6_DIPM0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_M1 "ip6r1m1"
+#define IP6_RUL1_M1_ID 13
+#define IP6_RUL1_M1_OFFSET 0x58c04
+#define IP6_RUL1_M1_E_LENGTH 4
+#define IP6_RUL1_M1_E_OFFSET 0x20
+#define IP6_RUL1_M1_NR_E 32
+
+#define IP6_DIPM1 "ip6r1m1_dipm1"
+#define IP6_RUL1_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL1_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL1_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+
+#define IP6_RUL1_M2 "ip6r1m2"
+#define IP6_RUL1_M2_ID 13
+#define IP6_RUL1_M2_OFFSET 0x58c08
+#define IP6_RUL1_M2_E_LENGTH 4
+#define IP6_RUL1_M2_E_OFFSET 0x20
+#define IP6_RUL1_M2_NR_E 32
+
+#define IP6_DIPM2 "ip6r1m2_dipm2"
+#define IP6_RUL1_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL1_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL1_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL1_M3 "ip6r1m3"
+#define IP6_RUL1_M3_ID 13
+#define IP6_RUL1_M3_OFFSET 0x58c0c
+#define IP6_RUL1_M3_E_LENGTH 4
+#define IP6_RUL1_M3_E_OFFSET 0x20
+#define IP6_RUL1_M3_NR_E 32
+
+#define IP6_DIPM3 "ip6r1m3_dipm3"
+#define IP6_RUL1_M3_IP6_DIPM3_BOFFSET 0
+#define IP6_RUL1_M3_IP6_DIPM3_BLEN 32
+#define IP6_RUL1_M3_IP6_DIPM3_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL2_V0 "ip6r2v0"
+#define IP6_RUL2_V0_ID 13
+#define IP6_RUL2_V0_OFFSET 0x58400
+#define IP6_RUL2_V0_E_LENGTH 4
+#define IP6_RUL2_V0_E_OFFSET 0x20
+#define IP6_RUL2_V0_NR_E 32
+
+#define IP6_SIPV0 "ip6r2v0_sipv0"
+#define IP6_RUL2_V0_IP6_SIPV0_BOFFSET 0
+#define IP6_RUL2_V0_IP6_SIPv0_BLEN 32
+#define IP6_RUL2_V0_IP6_SIPV0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V1 "ip6r2v1"
+#define IP6_RUL2_V1_ID 13
+#define IP6_RUL2_V1_OFFSET 0x58404
+#define IP6_RUL2_V1_E_LENGTH 4
+#define IP6_RUL2_V1_E_OFFSET 0x20
+#define IP6_RUL2_V1_NR_E 32
+
+#define IP6_SIPV1 "ip6r2v1_sipv1"
+#define IP6_RUL2_V1_IP6_SIPV1_BOFFSET 0
+#define IP6_RUL2_V1_IP6_SIPv1_BLEN 32
+#define IP6_RUL2_V1_IP6_SIPV1_FLAG HSL_RW
+
+
+
+#define IP6_RUL2_V2 "ip6r2v2"
+#define IP6_RUL2_V2_ID 13
+#define IP6_RUL2_V2_OFFSET 0x58408
+#define IP6_RUL2_V2_E_LENGTH 4
+#define IP6_RUL2_V2_E_OFFSET 0x20
+#define IP6_RUL2_V2_NR_E 32
+
+#define IP6_SIPV2 "ip6r2v2_sipv2"
+#define IP6_RUL2_V2_IP6_SIPV2_BOFFSET 0
+#define IP6_RUL2_V2_IP6_SIPv2_BLEN 32
+#define IP6_RUL2_V2_IP6_SIPV2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V3 "ip6r2v3"
+#define IP6_RUL2_V3_ID 13
+#define IP6_RUL2_V3_OFFSET 0x5840c
+#define IP6_RUL2_V3_E_LENGTH 4
+#define IP6_RUL2_V3_E_OFFSET 0x20
+#define IP6_RUL2_V3_NR_E 32
+
+#define IP6_SIPV3 "ip6r2v3_sipv3"
+#define IP6_RUL2_V3_IP6_SIPV3_BOFFSET 0
+#define IP6_RUL2_V3_IP6_SIPv3_BLEN 32
+#define IP6_RUL2_V3_IP6_SIPV3_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_V4 "ip6r2v4"
+#define IP6_RUL2_V4_ID 13
+#define IP6_RUL2_V4_OFFSET 0x58410
+#define IP6_RUL2_V4_E_LENGTH 4
+#define IP6_RUL2_V4_E_OFFSET 0x20
+#define IP6_RUL2_V4_NR_E 32
+
+#define IP6_RUL2_INPT "ip6r2v4_inptm"
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BOFFSET 0
+#define IP6_RUL2_V4_IP6_RUL2_INPT_BLEN 6
+#define IP6_RUL2_V4_IP6_RUL2_INPT_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M0 "ip6r2m0"
+#define IP6_RUL2_M0_ID 13
+#define IP6_RUL2_M0_OFFSET 0x58c00
+#define IP6_RUL2_M0_E_LENGTH 4
+#define IP6_RUL2_M0_E_OFFSET 0x20
+#define IP6_RUL2_M0_NR_E 32
+
+#define IP6_SIPM0 "ip6r2m0_sipm0"
+#define IP6_RUL2_M0_IP6_SIPM0_BOFFSET 0
+#define IP6_RUL2_M0_IP6_SIPM0_BLEN 32
+#define IP6_RUL2_M0_IP6_SIPM0_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M1 "ip6r2m1"
+#define IP6_RUL2_M1_ID 13
+#define IP6_RUL2_M1_OFFSET 0x58c04
+#define IP6_RUL2_M1_E_LENGTH 4
+#define IP6_RUL2_M1_E_OFFSET 0x20
+#define IP6_RUL2_M1_NR_E 32
+
+#define IP6_SIPM1 "ip6r2m1_sipm1"
+#define IP6_RUL2_M1_IP6_DIPM1_BOFFSET 0
+#define IP6_RUL2_M1_IP6_DIPM1_BLEN 32
+#define IP6_RUL2_M1_IP6_DIPM1_FLAG HSL_RW
+
+
+
+#define IP6_RUL2_M2 "ip6r2m2"
+#define IP6_RUL2_M2_ID 13
+#define IP6_RUL2_M2_OFFSET 0x58c08
+#define IP6_RUL2_M2_E_LENGTH 4
+#define IP6_RUL2_M2_E_OFFSET 0x20
+#define IP6_RUL2_M2_NR_E 32
+
+#define IP6_SIPM2 "ip6r2m2_sipm2"
+#define IP6_RUL2_M2_IP6_DIPM2_BOFFSET 0
+#define IP6_RUL2_M2_IP6_DIPM2_BLEN 32
+#define IP6_RUL2_M2_IP6_DIPM2_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL2_M3 "ip6r2m3"
+#define IP6_RUL2_M3_ID 13
+#define IP6_RUL2_M3_OFFSET 0x58c0c
+#define IP6_RUL2_M3_E_LENGTH 4
+#define IP6_RUL2_M3_E_OFFSET 0x20
+#define IP6_RUL2_M3_NR_E 32
+
+#define IP6_SIPM3 "ip6r2m3_sipm3"
+#define IP6_RUL2_M3_IP6_SIPM3_BOFFSET 0
+#define IP6_RUL2_M3_IP6_SIPM3_BLEN 32
+#define IP6_RUL2_M3_IP6_SIPM3_FLAG HSL_RW
+
+
+
+
+
+#define IP6_RUL3_V0 "ip6r3v0"
+#define IP6_RUL3_V0_ID 13
+#define IP6_RUL3_V0_OFFSET 0x58400
+#define IP6_RUL3_V0_E_LENGTH 4
+#define IP6_RUL3_V0_E_OFFSET 0x20
+#define IP6_RUL3_V0_NR_E 32
+
+#define IP6PROTV "ip6r3v0_protv"
+#define IP6_RUL3_V0_IP6PROTV_BOFFSET 0
+#define IP6_RUL3_V0_IP6PROTV_BLEN 8
+#define IP6_RUL3_V0_IP6PROTV_FLAG HSL_RW
+
+#define IP6DSCPV "ip6r3v0_dscpv"
+#define IP6_RUL3_V0_IP6DSCPV_BOFFSET 8
+#define IP6_RUL3_V0_IP6DSCPV_BLEN 8
+#define IP6_RUL3_V0_IP6DSCPV_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V1 "ip6r3v1"
+#define IP6_RUL3_V1_ID 13
+#define IP6_RUL3_V1_OFFSET 0x58404
+#define IP6_RUL3_V1_E_LENGTH 4
+#define IP6_RUL3_V1_E_OFFSET 0x20
+#define IP6_RUL3_V1_NR_E 32
+
+#define IP6LABEL1V "ip6r3v1_label1v"
+#define IP6_RUL3_V1_IP6LABEL1V_BOFFSET 16
+#define IP6_RUL3_V1_IP6LABEL1V_BLEN 16
+#define IP6_RUL3_V1_IP6LABEL1V_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V2 "ip6r3v2"
+#define IP6_RUL3_V2_ID 13
+#define IP6_RUL3_V2_OFFSET 0x58408
+#define IP6_RUL3_V2_E_LENGTH 4
+#define IP6_RUL3_V2_E_OFFSET 0x20
+#define IP6_RUL3_V2_NR_E 32
+
+#define IP6LABEL2V "ip6r3v2_label2v"
+#define IP6_RUL3_V2_IP6LABEL2V_BOFFSET 0
+#define IP6_RUL3_V2_IP6LABEL2V_BLEN 4
+#define IP6_RUL3_V2_IP6LABEL2V_FLAG HSL_RW
+
+#define IP6DPORTV "ip6r3v2_dportv"
+#define IP6_RUL3_V2_IP6DPORTV_BOFFSET 16
+#define IP6_RUL3_V2_IP6DPORTV_BLEN 16
+#define IP6_RUL3_V2_IP6DPORTV_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_V3 "ip6r3v3"
+#define IP6_RUL3_V3_ID 13
+#define IP6_RUL3_V3_OFFSET 0x5840c
+#define IP6_RUL3_V3_E_LENGTH 4
+#define IP6_RUL3_V3_E_OFFSET 0x20
+#define IP6_RUL3_V3_NR_E 32
+
+#define IP6SPORTV "ip6r3v3_sportv"
+#define IP6_RUL3_V3_IP6SPORTV_BOFFSET 0
+#define IP6_RUL3_V3_IP6SPORTV_BLEN 16
+#define IP6_RUL3_V3_IP6SPORTV_FLAG HSL_RW
+
+
+
+#define IP6_RUL3_M0 "ip6r3m0"
+#define IP6_RUL3_M0_ID 13
+#define IP6_RUL3_M0_OFFSET 0x58c00
+#define IP6_RUL3_M0_E_LENGTH 4
+#define IP6_RUL3_M0_E_OFFSET 0x20
+#define IP6_RUL3_M0_NR_E 32
+
+#define IP6PROTM "ip6r3m0_protm"
+#define IP6_RUL3_M0_IP6PROTM_BOFFSET 0
+#define IP6_RUL3_M0_IP6PROTM_BLEN 8
+#define IP6_RUL3_M0_IP6PROTM_FLAG HSL_RW
+
+#define IP6DSCPM "ip6r3m0_dscpm"
+#define IP6_RUL3_M0_IP6DSCPM_BOFFSET 8
+#define IP6_RUL3_M0_IP6DSCPM_BLEN 8
+#define IP6_RUL3_M0_IP6DSCPM_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M1 "ip6r3m1"
+#define IP6_RUL3_M1_ID 13
+#define IP6_RUL3_M1_OFFSET 0x58c04
+#define IP6_RUL3_M1_E_LENGTH 4
+#define IP6_RUL3_M1_E_OFFSET 0x20
+#define IP6_RUL3_M1_NR_E 32
+
+#define IP6LABEL1M "ip6r3m1_label1m"
+#define IP6_RUL3_M1_IP6LABEL1M_BOFFSET 16
+#define IP6_RUL3_M1_IP6LABEL1M_BLEN 16
+#define IP6_RUL3_M1_IP6LABEL1M_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M2 "ip6r3m2"
+#define IP6_RUL3_M2_ID 13
+#define IP6_RUL3_M2_OFFSET 0x58c08
+#define IP6_RUL3_M2_E_LENGTH 4
+#define IP6_RUL3_M2_E_OFFSET 0x20
+#define IP6_RUL3_M2_NR_E 32
+
+#define IP6LABEL2M "ip6r3m2_label2m"
+#define IP6_RUL3_M2_IP6LABEL2M_BOFFSET 0
+#define IP6_RUL3_M2_IP6LABEL2M_BLEN 4
+#define IP6_RUL3_M2_IP6LABEL21M_FLAG HSL_RW
+
+#define IP6DPORTM "ip6r3m2_dportm"
+#define IP6_RUL3_M2_IP6DPORTM_BOFFSET 16
+#define IP6_RUL3_M2_IP6DPORTM_BLEN 16
+#define IP6_RUL3_M2_IP6DPORTM_FLAG HSL_RW
+
+
+
+
+#define IP6_RUL3_M3 "ip6r3m3"
+#define IP6_RUL3_M3_ID 13
+#define IP6_RUL3_M3_OFFSET 0x58c0c
+#define IP6_RUL3_M3_E_LENGTH 4
+#define IP6_RUL3_M3_E_OFFSET 0x20
+#define IP6_RUL3_M3_NR_E 32
+
+#define IP6SPORTM "ip6r3m3_sportm"
+#define IP6_RUL3_M3_IP6SPORTM_BOFFSET 0
+#define IP6_RUL3_M3_IP6SPORTM_BLEN 16
+#define IP6_RUL3_M3_IP6SPORTM_FLAG HSL_RW
+
+#define IP6DPORTM_EN "ip6r3m3_dportmen"
+#define IP6_RUL3_M3_IP6DPORTM_EN_BOFFSET 17
+#define IP6_RUL3_M3_IP6DPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6DPORTM_EN_FLAG HSL_RW
+
+#define IP6SPORTM_EN "ip6r3m3_sportmen"
+#define IP6_RUL3_M3_IP6SPORTM_EN_BOFFSET 16
+#define IP6_RUL3_M3_IP6SPORTM_EN_BLEN 1
+#define IP6_RUL3_M3_IP6SPORTM_EN_FLAG HSL_RW
+
+
+
+
+#define UDF_RUL_V4 "udfv4"
+#define UDF_RUL_V4_ID 13
+#define UDF_RUL_V4_OFFSET 0x58410
+#define UDF_RUL_V4_E_LENGTH 4
+#define UDF_RUL_V4_E_OFFSET 0x20
+#define UDF_RUL_V4_NR_E 32
+
+
+#define LAYER_TYP "udfv4_typ"
+#define UDF_RUL_V4_LAYER_TYP_BOFFSET 7
+#define UDF_RUL_V4_LAYER_TYP_BLEN 1
+#define UDF_RUL_V4_LAYER_TYP_FLAG HSL_RW
+
+#define LAYER_OFFSET "udfv4_offset"
+#define UDF_RUL_V4_LAYER_OFFSET_BOFFSET 0
+#define UDF_RUL_V4_LAYER_OFFSET_BLEN 7
+#define UDF_RUL_V4_LAYER_OFFSET_FLAG HSL_RW
+
+
+
+
+#define PPPOE_SESSION "pppoes"
+#define PPPOE_SESSION_ID 13
+#define PPPOE_SESSION_OFFSET 0x59100
+#define PPPOE_SESSION_E_LENGTH 4
+#define PPPOE_SESSION_E_OFFSET 0x4
+#define PPPOE_SESSION_NR_E 16
+
+#define ENTRY_VALID "pppoes_v"
+#define PPPOE_SESSION_ENTRY_VALID_BOFFSET 19
+#define PPPOE_SESSION_ENTRY_VALID_BLEN 1
+#define PPPOE_SESSION_ENTRY_VALID_FLAG HSL_RW
+
+#define STRIP_EN "pppoes_s"
+#define PPPOE_SESSION_STRIP_EN_BOFFSET 16
+#define PPPOE_SESSION_STRIP_EN_BLEN 1
+#define PPPOE_SESSION_STRIP_EN_FLAG HSL_RW
+
+#define SEESION_ID "pppoes_id"
+#define PPPOE_SESSION_SEESION_ID_BOFFSET 0
+#define PPPOE_SESSION_SEESION_ID_BLEN 16
+#define PPPOE_SESSION_SEESION_ID_FLAG HSL_RW
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_REG_H_ */
+
diff --git a/include/hsl/shiva/shiva_reg_access.h b/include/hsl/shiva/shiva_reg_access.h
new file mode 100644
index 0000000..2955560
--- /dev/null
+++ b/include/hsl/shiva/shiva_reg_access.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SHIVA_REG_ACCESS_H_
+#define _SHIVA_REG_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t
+ shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value);
+
+ sw_error_t
+ shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value);
+
+ sw_error_t
+ shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len);
+
+ sw_error_t
+ shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len);
+
+ sw_error_t
+ shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode);
+
+ sw_error_t
+ shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_REG_ACCESS_H_ */
+
diff --git a/include/hsl/shiva/shiva_stp.h b/include/hsl/shiva/shiva_stp.h
new file mode 100644
index 0000000..cf0263c
--- /dev/null
+++ b/include/hsl/shiva/shiva_stp.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_stp SHIVA_STP
+ * @{
+ */
+#ifndef _SHIVA_STP_H_
+#define _SHIVA_STP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_stp.h"
+
+ sw_error_t shiva_stp_init(a_uint32_t dev_id);
+
+#ifdef IN_STP
+#define SHIVA_STP_INIT(rv, dev_id) \
+ { \
+ rv = shiva_stp_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_STP_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SHIVA_STP_H_ */
+/**
+ * @}
+ */
diff --git a/include/hsl/shiva/shiva_vlan.h b/include/hsl/shiva/shiva_vlan.h
new file mode 100644
index 0000000..6c93d61
--- /dev/null
+++ b/include/hsl/shiva/shiva_vlan.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_vlan SHIVA_VLAN
+ * @{
+ */
+#ifndef _SHIVA_VLAN_H_
+#define _SHIVA_VLAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "fal/fal_vlan.h"
+
+ sw_error_t
+ shiva_vlan_init(a_uint32_t dev_id);
+
+#ifdef IN_VLAN
+#define SHIVA_VLAN_INIT(rv, dev_id) \
+ { \
+ rv = shiva_vlan_init(dev_id); \
+ SW_RTN_ON_ERROR(rv); \
+ }
+#else
+#define SHIVA_VLAN_INIT(rv, dev_id)
+#endif
+
+#ifdef HSL_STANDALONG
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id);
+
+
+ HSL_LOCAL sw_error_t
+ shiva_vlan_flush(a_uint32_t dev_id);
+
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHIVA_VLAN_H_ */
+/**
+ * @}
+ */
diff --git a/include/init/ssdk_init.h b/include/init/ssdk_init.h
new file mode 100644
index 0000000..fd06b41
--- /dev/null
+++ b/include/init/ssdk_init.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SSDK_INIT_H_
+#define _SSDK_INIT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ typedef enum {
+ HSL_MDIO = 1,
+ HSL_HEADER,
+ }
+ hsl_access_mode;
+
+ typedef enum
+ {
+ HSL_NO_CPU = 0,
+ HSL_CPU_1,
+ HSL_CPU_2,
+ HSL_CPU_1_PLUS,
+ } hsl_init_mode;
+
+ typedef sw_error_t
+ (*mdio_reg_set) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+ a_uint16_t data);
+
+ typedef sw_error_t
+ (*mdio_reg_get) (a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+ a_uint16_t * data);
+
+ typedef sw_error_t
+ (*hdr_reg_set) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+ typedef sw_error_t
+ (*hdr_reg_get) (a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t *reg_data, a_uint32_t len);
+
+ typedef struct
+ {
+ mdio_reg_set mdio_set;
+ mdio_reg_get mdio_get;
+ hdr_reg_set header_reg_set;
+ hdr_reg_get header_reg_get;
+ } hsl_reg_func;
+
+ typedef struct
+ {
+ a_bool_t mac0_rgmii;
+ a_bool_t mac5_rgmii;
+ a_bool_t rx_delay_s0;
+ a_bool_t rx_delay_s1;
+ a_bool_t tx_delay_s0;
+ a_bool_t tx_delay_s1;
+ a_bool_t rgmii_rxclk_delay;
+ a_bool_t rgmii_txclk_delay;
+ a_bool_t phy4_rx_delay;
+ a_bool_t phy4_tx_delay;
+ } garuda_init_spec_cfg;
+
+ typedef enum
+ {
+ CHIP_UNSPECIFIED = 0,
+ CHIP_ATHENA,
+ CHIP_GARUDA,
+ CHIP_SHIVA,
+ CHIP_HORUS,
+ CHIP_ISIS,
+ CHIP_ISISC,
+ } ssdk_chip_type;
+
+ typedef struct
+ {
+ hsl_init_mode cpu_mode;
+ hsl_access_mode reg_mode;
+ hsl_reg_func reg_func;
+
+ ssdk_chip_type chip_type;
+
+ /* os specific parameter */
+ /* when uk_if based on netlink, it's netlink protocol type*/
+ /* when uk_if based on ioctl, it's minor device number, major number
+ is always 10(misc device) */
+ a_uint32_t nl_prot;
+
+ /* chip specific parameter */
+ void * chip_spec_cfg;
+ } ssdk_init_cfg;
+
+#if defined ATHENA
+#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined GARUDA
+
+#define def_init_cfg_cpu2 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2,};
+
+#define def_init_spec_cfg_cpu2 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_TRUE, \
+ .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+ .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
+ .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE,\
+ .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1 {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
+
+#define def_init_spec_cfg_cpu1 {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
+ .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+ .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
+ .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+ .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1plus {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1_PLUS,};
+
+#define def_init_spec_cfg_cpu1plus {.mac0_rgmii = A_TRUE, .mac5_rgmii = A_FALSE, \
+ .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+ .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\
+ .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+ .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_nocpu {.reg_mode = HSL_MDIO, .cpu_mode = HSL_NO_CPU,};
+
+#define def_init_spec_cfg_nocpu { .mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
+ .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+ .tx_delay_s0 = A_FALSE, .tx_delay_s1 = A_FALSE,\
+ .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+ .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg_cpu1_gmii {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_1,};
+
+#define def_init_spec_cfg_cpu1_gmii {.mac0_rgmii = A_FALSE, .mac5_rgmii = A_FALSE, \
+ .rx_delay_s0 = A_FALSE, .rx_delay_s1 = A_FALSE, \
+ .tx_delay_s0 = A_TRUE, .tx_delay_s1 = A_FALSE,\
+ .rgmii_rxclk_delay = A_TRUE, .rgmii_txclk_delay = A_TRUE, \
+ .phy4_rx_delay = A_TRUE, .phy4_tx_delay = A_TRUE,}
+
+#define def_init_cfg def_init_cfg_cpu2
+#define def_init_spec_cfg def_init_spec_cfg_cpu2
+
+#elif defined SHIVA
+#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined HORUS
+#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined ISIS
+#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#elif defined ISISC
+#define def_init_cfg {.reg_mode = HSL_MDIO, .cpu_mode = HSL_CPU_2};
+#endif
+
+ typedef struct
+ {
+ a_bool_t in_acl;
+ a_bool_t in_fdb;
+ a_bool_t in_igmp;
+ a_bool_t in_leaky;
+ a_bool_t in_led;
+ a_bool_t in_mib;
+ a_bool_t in_mirror;
+ a_bool_t in_misc;
+ a_bool_t in_portcontrol;
+ a_bool_t in_portvlan;
+ a_bool_t in_qos;
+ a_bool_t in_rate;
+ a_bool_t in_stp;
+ a_bool_t in_vlan;
+ a_bool_t in_reduced_acl;
+ a_bool_t in_ip;
+ a_bool_t in_nat;
+ a_bool_t in_cosmap;
+ a_bool_t in_sec;
+ a_bool_t in_trunk;
+ a_bool_t in_nathelper;
+ a_bool_t in_interfacectrl;
+ } ssdk_features;
+
+#define CFG_STR_SIZE 20
+ typedef struct
+ {
+ a_uint8_t build_ver[CFG_STR_SIZE];
+ a_uint8_t build_date[CFG_STR_SIZE];
+
+ a_uint8_t chip_type[CFG_STR_SIZE]; //GARUDA
+ a_uint8_t cpu_type[CFG_STR_SIZE]; //mips
+ a_uint8_t os_info[CFG_STR_SIZE]; //OS=linux OS_VER=2_6
+
+ a_bool_t fal_mod;
+ a_bool_t kernel_mode;
+ a_bool_t uk_if;
+
+ ssdk_features features;
+ ssdk_init_cfg init_cfg;
+ } ssdk_cfg_t;
+
+ sw_error_t
+ ssdk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg);
+
+ sw_error_t
+ ssdk_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode,
+ hsl_access_mode reg_mode);
+
+ sw_error_t
+ ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SSDK_INIT_H */
diff --git a/include/sal/os/aos_lock.h b/include/sal/os/aos_lock.h
new file mode 100644
index 0000000..942a9ae
--- /dev/null
+++ b/include/sal/os/aos_lock.h
@@ -0,0 +1,33 @@
+#ifndef _AOS_LOCK_H
+#define _AOS_LOCK_H
+
+
+#ifdef KERNEL_MODULE
+#include "sal/os/linux/aos_lock_pvt.h"
+#else
+#include "sal/os/linux_user/aos_lock_pvt.h"
+#endif
+
+
+typedef aos_lock_pvt_t aos_lock_t;
+
+
+#define aos_lock_init(lock) __aos_lock_init(lock)
+
+
+#define aos_lock(lock) __aos_lock(lock)
+
+
+#define aos_unlock(lock) __aos_unlock(lock)
+
+
+#define aos_irq_save(flags) __aos_irq_save(flags)
+
+
+#define aos_irq_restore(flags) __aos_irq_restore(flags)
+
+
+#define aos_default_unlock __aos_default_unlock
+
+
+#endif
diff --git a/include/sal/os/aos_mem.h b/include/sal/os/aos_mem.h
new file mode 100644
index 0000000..063e9bf
--- /dev/null
+++ b/include/sal/os/aos_mem.h
@@ -0,0 +1,102 @@
+#ifndef _AOS_MEM_H
+#define _AOS_MEM_H
+
+#include "sal/os/aos_types.h"
+#ifdef KERNEL_MODULE
+#include "sal/os/linux/aos_mem_pvt.h"
+#else
+#include "sal/os/linux_user/aos_mem_pvt.h"
+#endif
+
+/**
+ * @g aos_mem mem
+ * @{
+ *
+ * @ig shim_ext
+ */
+
+/**
+ * @brief Allocate a memory buffer. Note it's a non-blocking call.
+ * This call can block.
+ *
+ * @param[in] size buffer size
+ *
+ * @return Buffer pointer or NULL if there's not enough memory.
+ */
+static inline void *
+aos_mem_alloc(aos_size_t size)
+{
+ return __aos_mem_alloc(size);
+}
+
+/**
+ * @brief Free malloc'ed buffer
+ *
+ * @param[in] buf buffer pointer allocated by aos_alloc()
+ * @param[in] size buffer size
+ */
+static inline void
+aos_mem_free(void *buf)
+{
+ __aos_mem_free(buf);
+}
+
+/**
+ * @brief Move a memory buffer
+ *
+ * @param[in] dst destination address
+ * @param[in] src source address
+ * @param[in] size buffer size
+ */
+static inline void
+aos_mem_copy(void *dst, void *src, aos_size_t size)
+{
+ __aos_mem_copy(dst, src, size);
+}
+
+/**
+ * @brief Fill a memory buffer
+ *
+ * @param[in] buf buffer to be filled
+ * @param[in] b byte to fill
+ * @param[in] size buffer size
+ */
+static inline void
+aos_mem_set(void *buf, a_uint8_t b, aos_size_t size)
+{
+ __aos_mem_set(buf, b, size);
+}
+
+/**
+ * @brief Zero a memory buffer
+ *
+ * @param[in] buf buffer to be zeroed
+ * @param[in] size buffer size
+ */
+static inline void
+aos_mem_zero(void *buf, aos_size_t size)
+{
+ __aos_mem_zero(buf, size);
+}
+
+/**
+ * @brief Compare two memory buffers
+ *
+ * @param[in] buf1 first buffer
+ * @param[in] buf2 second buffer
+ * @param[in] size buffer size
+ *
+ * @retval 0 equal
+ * @retval 1 not equal
+ */
+static inline int
+aos_mem_cmp(void *buf1, void *buf2, aos_size_t size)
+{
+ return __aos_mem_cmp(buf1, buf2, size);
+}
+
+/**
+ * @}
+ */
+
+#endif
diff --git a/include/sal/os/aos_timer.h b/include/sal/os/aos_timer.h
new file mode 100644
index 0000000..5e6769b
--- /dev/null
+++ b/include/sal/os/aos_timer.h
@@ -0,0 +1,36 @@
+
+#ifndef _AOS_TIMER_H
+#define _AOS_TIMER_H
+
+#include "sal/os/aos_types.h"
+#ifdef KERNEL_MODULE
+#include "sal/os/linux/aos_timer_pvt.h"
+#else
+#include "sal/os/linux_user/aos_timer_pvt.h"
+#endif
+
+
+typedef __aos_timer_t aos_timer_t;
+
+
+/*
+ * Delay in microseconds
+ */
+static inline void
+aos_udelay(int usecs)
+{
+ return __aos_udelay(usecs);
+}
+
+/*
+ * Delay in milliseconds.
+ */
+static inline void
+aos_mdelay(int msecs)
+{
+ return __aos_mdelay(msecs);
+}
+
+
+#endif
+
diff --git a/include/sal/os/aos_types.h b/include/sal/os/aos_types.h
new file mode 100644
index 0000000..555e4b8
--- /dev/null
+++ b/include/sal/os/aos_types.h
@@ -0,0 +1,169 @@
+#ifndef _AOS_TYPES_H
+#define _AOS_TYPES_H
+
+#ifdef KERNEL_MODULE
+#include "sal/os/linux/aos_types_pvt.h"
+#else
+#include "sal/os/linux_user/aos_types_pvt.h"
+#endif
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @g aos_types types
+ * @{
+ *
+ * @ig shim_ext
+ */
+/*
+ *@ basic data types.
+ */
+typedef enum
+{
+ A_FALSE,
+ A_TRUE
+} a_bool_t;
+
+typedef __a_uint8_t a_uint8_t;
+typedef __a_int8_t a_int8_t;
+typedef __a_uint16_t a_uint16_t;
+typedef __a_int16_t a_int16_t;
+typedef __a_uint32_t a_uint32_t;
+typedef __a_int32_t a_int32_t;
+typedef __a_uint64_t a_uint64_t;
+typedef __a_int64_t a_int64_t;
+
+
+typedef void * acore_t;
+
+/**
+ * @brief Platform/bus generic handle. Used for bus specific functions.
+ */
+typedef __aos_device_t aos_device_t;
+
+/**
+ * @brief size of an object
+ */
+typedef __aos_size_t aos_size_t;
+
+/**
+ * @brief Generic status to be used by acore.
+ */
+typedef enum
+{
+ A_STATUS_OK,
+ A_STATUS_FAILED,
+ A_STATUS_ENOENT,
+ A_STATUS_ENOMEM,
+ A_STATUS_EINVAL,
+ A_STATUS_EINPROGRESS,
+ A_STATUS_ENOTSUPP,
+ A_STATUS_EBUSY,
+} a_status_t;
+
+/*
+ * An ecore needs to provide a table of all pci device/vendor id's it
+ * supports
+ *
+ * This table should be terminated by a NULL entry , i.e. {0}
+ */
+typedef struct
+{
+ a_uint32_t vendor;
+ a_uint32_t device;
+ a_uint32_t subvendor;
+ a_uint32_t subdevice;
+} aos_pci_dev_id_t;
+
+#define AOS_PCI_ANY_ID (~0)
+
+/*
+ * Typically core's can use this macro to create a table of various device
+ * ID's
+ */
+#define AOS_PCI_DEVICE(_vendor, _device) \
+ (_vendor), (_device), AOS_PCI_ANY_ID, AOS_PCI_ANY_ID
+
+
+typedef __aos_iomem_t aos_iomem_t;
+/*
+ * These define the hw resources the OS has allocated for the device
+ * Note that start defines a mapped area.
+ */
+typedef enum
+{
+ AOS_RESOURCE_TYPE_MEM,
+ AOS_RESOURCE_TYPE_IO,
+} aos_resource_type_t;
+
+typedef struct
+{
+ a_uint32_t start;
+ a_uint32_t end;
+ aos_resource_type_t type;
+} aos_resource_t;
+
+#define AOS_DEV_ID_TABLE_MAX 256
+
+typedef union
+{
+ aos_pci_dev_id_t *pci;
+ void *raw;
+} aos_bus_reg_data_t;
+
+typedef void *aos_attach_data_t;
+
+#define AOS_REGIONS_MAX 5
+
+typedef enum
+{
+ AOS_BUS_TYPE_PCI = 1,
+ AOS_BUS_TYPE_GENERIC,
+} aos_bus_type_t;
+
+typedef enum
+{
+ AOS_IRQ_NONE,
+ AOS_IRQ_HANDLED,
+} aos_irq_resp_t;
+
+typedef enum
+{
+ AOS_DMA_MASK_32BIT,
+ AOS_DMA_MASK_64BIT,
+} aos_dma_mask_t;
+
+
+/**
+ * @brief DMA directions
+ */
+typedef enum
+{
+ AOS_DMA_TO_DEVICE = 0, /**< Data is transfered from device to memory */
+ AOS_DMA_FROM_DEVICE, /**< Data is transfered from memory to device */
+} aos_dma_dir_t;
+
+/*
+ * Protoypes shared between public and private headers
+ */
+
+
+/*
+ * work queue(kernel thread) function callback
+ */
+typedef void (*aos_work_func_t)(void *);
+
+/**
+ * @brief Prototype of the critical region function that is to be
+ * executed with spinlock held and interrupt disalbed
+ */
+typedef a_bool_t (*aos_irqlocked_func_t)(void *);
+
+/**
+ * @brief Prototype of timer function
+ */
+typedef void (*aos_timer_func_t)(void *);
+
+#endif
diff --git a/include/sal/os/linux/aos_lock_pvt.h b/include/sal/os/linux/aos_lock_pvt.h
new file mode 100644
index 0000000..07a0a1c
--- /dev/null
+++ b/include/sal/os/linux/aos_lock_pvt.h
@@ -0,0 +1,31 @@
+#ifndef _AOS_LOCK_PVT_H
+#define _AOS_LOCK_PVT_H
+
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+
+typedef spinlock_t aos_lock_pvt_t;
+
+
+#define __aos_lock_init(lock) spin_lock_init(lock)
+
+
+#define __aos_lock(lock) spin_lock(lock)
+
+
+#define __aos_unlock(lock) spin_unlock(lock)
+
+
+#define __aos_irq_save(flags) local_irq_save(flags)
+
+
+#define __aos_irq_restore(flags) local_irq_restore(flags)
+
+#ifndef KVER32
+#define __aos_default_unlock SPIN_LOCK_UNLOCKED
+#endif
+
+#endif /*_AOS_LOCK_PVT_H*/
+
diff --git a/include/sal/os/linux/aos_mem_pvt.h b/include/sal/os/linux/aos_mem_pvt.h
new file mode 100644
index 0000000..01b7433
--- /dev/null
+++ b/include/sal/os/linux/aos_mem_pvt.h
@@ -0,0 +1,46 @@
+#ifndef _AOS_MEM_PVT_H
+#define _AOS_MEM_PVT_H
+
+#include <linux/slab.h>
+
+static inline void *__aos_mem_alloc(aos_size_t size)
+{
+ return (kmalloc(size, GFP_KERNEL));
+}
+
+static inline void __aos_mem_free(void *buf)
+{
+ kfree(buf);
+}
+
+/* move a memory buffer */
+static inline void
+__aos_mem_copy(void *dst, void *src, aos_size_t size)
+{
+ memcpy(dst, src, size);
+}
+
+/* set a memory buffer */
+static inline void
+__aos_mem_set(void *buf, a_uint8_t b, aos_size_t size)
+{
+ memset(buf, b, size);
+}
+
+/* zero a memory buffer */
+static inline void
+__aos_mem_zero(void *buf, aos_size_t size)
+{
+ memset(buf, 0, size);
+}
+
+/* compare two memory buffers */
+static inline int
+__aos_mem_cmp(void *buf1, void *buf2, aos_size_t size)
+{
+ return (memcmp(buf1, buf2, size) == 0) ? 0 : 1;
+}
+
+
+
+#endif /*_AOS_MEM_PVT_H*/
diff --git a/include/sal/os/linux/aos_timer_pvt.h b/include/sal/os/linux/aos_timer_pvt.h
new file mode 100644
index 0000000..b9a4caa
--- /dev/null
+++ b/include/sal/os/linux/aos_timer_pvt.h
@@ -0,0 +1,29 @@
+#ifndef _AOS_TIMER_PVT_H
+#define _AOS_TIMER_PVT_H
+
+#ifdef KVER26
+#include <linux/jiffies.h>
+#endif
+#include <linux/delay.h>
+#include <linux/timer.h>
+
+
+/*
+ * timer data type
+ */
+typedef struct timer_list __aos_timer_t;
+
+
+static inline void
+__aos_udelay(int usecs)
+{
+ udelay(usecs);
+}
+
+static inline void
+__aos_mdelay(int msecs)
+{
+ mdelay(msecs);
+}
+
+#endif /*_AOS_TIMER_PVT_H*/
diff --git a/include/sal/os/linux/aos_types_pvt.h b/include/sal/os/linux/aos_types_pvt.h
new file mode 100644
index 0000000..8f0206f
--- /dev/null
+++ b/include/sal/os/linux/aos_types_pvt.h
@@ -0,0 +1,64 @@
+#ifndef _AOS_PVTTYPES_H
+#define _AOS_PVTTYPES_H
+
+#ifdef GCCV4
+#ifdef KVER32
+#include <generated/autoconf.h>
+#else
+#include <linux/autoconf.h>
+#endif
+#endif
+#include <asm/types.h>
+#include <linux/compiler.h>
+/*
+ * Private definitions of general data types
+ */
+
+/* generic data types */
+typedef struct device * __aos_device_t;
+typedef int __aos_size_t;
+
+#ifdef KVER26
+#ifdef LNX26_22
+typedef __u8 * __aos_iomem_t;
+#else
+typedef u8 __iomem * __aos_iomem_t;
+#endif
+#else /*Linux Kernel 2.4 */
+typedef u8 * __aos_iomem_t;
+#endif
+
+#ifdef KVER32
+typedef u8 __iomem * __aos_iomem_t;
+#endif
+
+#ifdef LNX26_22 /* > Linux 2.6.22 */
+typedef __u8 __a_uint8_t;
+typedef __s8 __a_int8_t;
+typedef __u16 __a_uint16_t;
+typedef __s16 __a_int16_t;
+typedef __u32 __a_uint32_t;
+typedef __s32 __a_int32_t;
+typedef __u64 __a_uint64_t;
+typedef __s64 __a_int64_t;
+#else
+typedef u8 __a_uint8_t;
+typedef s8 __a_int8_t;
+typedef u16 __a_uint16_t;
+typedef s16 __a_int16_t;
+typedef u32 __a_uint32_t;
+typedef s32 __a_int32_t;
+typedef u64 __a_uint64_t;
+typedef s64 __a_int64_t;
+#endif
+
+#define aos_printk printk
+
+// #define AUTO_UPDATE_PPPOE_INFO 1
+#undef AUTO_UPDATE_PPPOE_INFO
+
+#ifdef AUTO_UPDATE_PPPOE_INFO
+#include "lib/ppp_generic.h"
+#endif
+
+#endif
diff --git a/include/sal/os/linux/lib/ppp_generic.h b/include/sal/os/linux/lib/ppp_generic.h
new file mode 100644
index 0000000..b0f29fb
--- /dev/null
+++ b/include/sal/os/linux/lib/ppp_generic.h
@@ -0,0 +1,174 @@
+/* FIXME: Directly copy from Linux. */
+/*
+ * Generic PPP layer for Linux.
+ *
+ * Copyright 1999-2002 Paul Mackerras.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * The generic PPP layer handles the PPP network interfaces, the
+ * /dev/ppp device, packet and VJ compression, and multilink.
+ * It talks to PPP `channels' via the interface defined in
+ * include/linux/ppp_channel.h. Channels provide the basic means for
+ * sending and receiving PPP frames on some kind of communications
+ * channel.
+ *
+ * Part of the code in this driver was inspired by the old async-only
+ * PPP driver, written by Michael Callahan and Al Longyear, and
+ * subsequently hacked by Paul Mackerras.
+ *
+ * ==FILEVERSION 20041108==
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/kmod.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/idr.h>
+#include <linux/netdevice.h>
+#include <linux/poll.h>
+#include <linux/ppp_defs.h>
+#include <linux/filter.h>
+#include <linux/if_ppp.h>
+#include <linux/ppp_channel.h>
+#include <linux/ppp-comp.h>
+#include <linux/skbuff.h>
+#include <linux/rtnetlink.h>
+#include <linux/if_arp.h>
+#include <linux/ip.h>
+#include <linux/tcp.h>
+#include <linux/smp_lock.h>
+#include <linux/spinlock.h>
+#include <linux/rwsem.h>
+#include <linux/stddef.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <net/slhc_vj.h>
+#include <asm/atomic.h>
+
+#include <linux/nsproxy.h>
+#include <net/net_namespace.h>
+#include <net/netns/generic.h>
+
+#define PPP_VERSION "2.4.2"
+
+/*
+ * Network protocols we support.
+ */
+#define NP_IP 0 /* Internet Protocol V4 */
+#define NP_IPV6 1 /* Internet Protocol V6 */
+#define NP_IPX 2 /* IPX protocol */
+#define NP_AT 3 /* Appletalk protocol */
+#define NP_MPLS_UC 4 /* MPLS unicast */
+#define NP_MPLS_MC 5 /* MPLS multicast */
+#define NUM_NP 6 /* Number of NPs. */
+
+#define MPHDRLEN 6 /* multilink protocol header length */
+#define MPHDRLEN_SSN 4 /* ditto with short sequence numbers */
+#define MIN_FRAG_SIZE 64
+
+/*
+ * An instance of /dev/ppp can be associated with either a ppp
+ * interface unit or a ppp channel. In both cases, file->private_data
+ * points to one of these.
+ */
+struct ppp_file {
+ enum {
+ INTERFACE=1, CHANNEL
+ } kind;
+ struct sk_buff_head xq; /* pppd transmit queue */
+ struct sk_buff_head rq; /* receive queue for pppd */
+ wait_queue_head_t rwait; /* for poll on reading /dev/ppp */
+ atomic_t refcnt; /* # refs (incl /dev/ppp attached) */
+ int hdrlen; /* space to leave for headers */
+ int index; /* interface unit / channel number */
+ int dead; /* unit/channel has been shut down */
+};
+
+#define PF_TO_X(pf, X) container_of(pf, X, file)
+
+#define PF_TO_PPP(pf) PF_TO_X(pf, struct ppp)
+#define PF_TO_CHANNEL(pf) PF_TO_X(pf, struct channel)
+
+/*
+ * Data structure describing one ppp unit.
+ * A ppp unit corresponds to a ppp network interface device
+ * and represents a multilink bundle.
+ * It can have 0 or more ppp channels connected to it.
+ */
+struct ppp {
+ struct ppp_file file; /* stuff for read/write/poll 0 */
+ struct file *owner; /* file that owns this unit 48 */
+ struct list_head channels; /* list of attached channels 4c */
+ int n_channels; /* how many channels are attached 54 */
+ spinlock_t rlock; /* lock for receive side 58 */
+ spinlock_t wlock; /* lock for transmit side 5c */
+ int mru; /* max receive unit 60 */
+ unsigned int flags; /* control bits 64 */
+ unsigned int xstate; /* transmit state bits 68 */
+ unsigned int rstate; /* receive state bits 6c */
+ int debug; /* debug flags 70 */
+ struct slcompress *vj; /* state for VJ header compression */
+ enum NPmode npmode[NUM_NP]; /* what to do with each net proto 78 */
+ struct sk_buff *xmit_pending; /* a packet ready to go out 88 */
+ struct compressor *xcomp; /* transmit packet compressor 8c */
+ void *xc_state; /* its internal state 90 */
+ struct compressor *rcomp; /* receive decompressor 94 */
+ void *rc_state; /* its internal state 98 */
+ unsigned long last_xmit; /* jiffies when last pkt sent 9c */
+ unsigned long last_recv; /* jiffies when last pkt rcvd a0 */
+ struct net_device *dev; /* network interface device a4 */
+ int closing; /* is device closing down? a8 */
+#ifdef CONFIG_PPP_MULTILINK
+ int nxchan; /* next channel to send something on */
+ u32 nxseq; /* next sequence number to send */
+ int mrru; /* MP: max reconst. receive unit */
+ u32 nextseq; /* MP: seq no of next packet */
+ u32 minseq; /* MP: min of most recent seqnos */
+ struct sk_buff_head mrq; /* MP: receive reconstruction queue */
+#endif /* CONFIG_PPP_MULTILINK */
+#ifdef CONFIG_PPP_FILTER
+ struct sock_filter *pass_filter; /* filter for packets to pass */
+ struct sock_filter *active_filter;/* filter for pkts to reset idle */
+ unsigned pass_len, active_len;
+#endif /* CONFIG_PPP_FILTER */
+ struct net *ppp_net; /* the net we belong to */
+};
+
+/*
+ * Bits in flags: SC_NO_TCP_CCID, SC_CCP_OPEN, SC_CCP_UP, SC_LOOP_TRAFFIC,
+ * SC_MULTILINK, SC_MP_SHORTSEQ, SC_MP_XSHORTSEQ, SC_COMP_TCP, SC_REJ_COMP_TCP,
+ * SC_MUST_COMP
+ * Bits in rstate: SC_DECOMP_RUN, SC_DC_ERROR, SC_DC_FERROR.
+ * Bits in xstate: SC_COMP_RUN
+ */
+#define SC_FLAG_BITS (SC_NO_TCP_CCID|SC_CCP_OPEN|SC_CCP_UP|SC_LOOP_TRAFFIC \
+ |SC_MULTILINK|SC_MP_SHORTSEQ|SC_MP_XSHORTSEQ \
+ |SC_COMP_TCP|SC_REJ_COMP_TCP|SC_MUST_COMP)
+
+/*
+ * Private data structure for each channel.
+ * This includes the data structure used for multilink.
+ */
+struct channel {
+ struct ppp_file file; /* stuff for read/write/poll */
+ struct list_head list; /* link in all/new_channels list */
+ struct ppp_channel *chan; /* public channel data structure */
+ struct rw_semaphore chan_sem; /* protects `chan' during chan ioctl */
+ spinlock_t downl; /* protects `chan', file.xq dequeue */
+ struct ppp *ppp; /* ppp unit we're connected to */
+ struct net *chan_net; /* the net channel belongs to */
+ struct list_head clist; /* link in list of channels per unit */
+ rwlock_t upl; /* protects `ppp' */
+#ifdef CONFIG_PPP_MULTILINK
+ u8 avail; /* flag used in multilink stuff */
+ u8 had_frag; /* >= 1 fragments have been sent */
+ u32 lastseq; /* MP: last sequence # received */
+ int speed; /* speed of the corresponding ppp channel*/
+#endif /* CONFIG_PPP_MULTILINK */
+};
+
diff --git a/include/sal/os/linux_user/aos_lock_pvt.h b/include/sal/os/linux_user/aos_lock_pvt.h
new file mode 100644
index 0000000..1f72e31
--- /dev/null
+++ b/include/sal/os/linux_user/aos_lock_pvt.h
@@ -0,0 +1,32 @@
+#ifndef _AOS_LOCK_PVT_H
+#define _AOS_LOCK_PVT_H
+
+#include <pthread.h>
+#include "sal/os/aos_types.h"
+
+
+typedef pthread_mutex_t aos_lock_pvt_t;
+
+
+#define __aos_lock_init(lock) \
+ pthread_mutex_init(lock, NULL); \
+ pthread_mutexattr_setpshared(lock, PTHREAD_PROCESS_SHARED)
+
+
+#define __aos_lock(lock) pthread_mutex_lock(lock)
+
+
+#define __aos_unlock(lock) pthread_mutex_unlock(lock)
+
+
+#define __aos_irq_save(flags)
+
+
+#define __aos_irq_restore(flags)
+
+
+#define __aos_default_unlock PTHREAD_MUTEX_INITIALIZER
+
+
+#endif /*_AOS_LOCK_PVT_H*/
+
diff --git a/include/sal/os/linux_user/aos_mem_pvt.h b/include/sal/os/linux_user/aos_mem_pvt.h
new file mode 100644
index 0000000..bb7dac5
--- /dev/null
+++ b/include/sal/os/linux_user/aos_mem_pvt.h
@@ -0,0 +1,47 @@
+#ifndef _AOS_MEM_PVT_H
+#define _AOS_MEM_PVT_H
+
+#include <stdlib.h>
+#include <string.h>
+
+static inline void *__aos_mem_alloc(aos_size_t size)
+{
+ return (malloc(size));
+}
+
+static inline void __aos_mem_free(void *buf)
+{
+ free(buf);
+}
+
+/* move a memory buffer */
+static inline void
+__aos_mem_copy(void *dst, void *src, aos_size_t size)
+{
+ memcpy(dst, src, size);
+}
+
+/* set a memory buffer */
+static inline void
+__aos_mem_set(void *buf, a_uint8_t b, aos_size_t size)
+{
+ memset(buf, b, size);
+}
+
+/* zero a memory buffer */
+static inline void
+__aos_mem_zero(void *buf, aos_size_t size)
+{
+ memset(buf, 0, size);
+}
+
+/* compare two memory buffers */
+static inline int
+__aos_mem_cmp(void *buf1, void *buf2, aos_size_t size)
+{
+ return (memcmp(buf1, buf2, size) == 0) ? 0 : 1;
+}
+
+
+
+#endif /*_AOS_MEM_PVT_H*/
diff --git a/include/sal/os/linux_user/aos_timer_pvt.h b/include/sal/os/linux_user/aos_timer_pvt.h
new file mode 100644
index 0000000..d8a61aa
--- /dev/null
+++ b/include/sal/os/linux_user/aos_timer_pvt.h
@@ -0,0 +1,22 @@
+#ifndef _AOS_TIMER_PVT_H
+#define _AOS_TIMER_PVT_H
+
+#include <unistd.h>
+
+typedef int __aos_timer_t;
+
+static inline void
+__aos_udelay(int usecs)
+{
+ usleep(usecs);
+ return;
+}
+
+static inline void
+__aos_mdelay(int msecs)
+{
+ usleep(1000*msecs);
+ return;
+}
+
+#endif /*_AOS_TIMER_PVT_H*/
diff --git a/include/sal/os/linux_user/aos_types_pvt.h b/include/sal/os/linux_user/aos_types_pvt.h
new file mode 100644
index 0000000..20e57cd
--- /dev/null
+++ b/include/sal/os/linux_user/aos_types_pvt.h
@@ -0,0 +1,30 @@
+#ifndef _AOS_PVTTYPES_H
+#define _AOS_PVTTYPES_H
+
+#include <asm/types.h>
+#ifndef GCCV4
+#include <linux/compiler.h>
+#endif
+#include <stdio.h>
+/*
+ * Private definitions of general data types
+ */
+
+typedef void* __aos_device_t;
+typedef int __aos_size_t;
+typedef int __aos_iomem_t;
+
+typedef __u8 __a_uint8_t;
+typedef __s8 __a_int8_t;
+typedef __u16 __a_uint16_t;
+typedef __s16 __a_int16_t;
+typedef __u32 __a_uint32_t;
+typedef __s32 __a_int32_t;
+typedef __u64 __a_uint64_t;
+typedef __s64 __a_int64_t;
+
+
+#define aos_printk printf
+
+
+#endif
diff --git a/include/sal/sd/linux/uk_interface/sw_api_ks.h b/include/sal/sd/linux/uk_interface/sw_api_ks.h
new file mode 100644
index 0000000..295ff90
--- /dev/null
+++ b/include/sal/sd/linux/uk_interface/sw_api_ks.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_API_KS_H
+#define _SW_API_KS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t sw_uk_init(a_uint32_t nl_prot);
+
+ sw_error_t sw_uk_cleanup(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_API_KS_H */
diff --git a/include/sal/sd/linux/uk_interface/sw_api_us.h b/include/sal/sd/linux/uk_interface/sw_api_us.h
new file mode 100644
index 0000000..b696022
--- /dev/null
+++ b/include/sal/sd/linux/uk_interface/sw_api_us.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SW_API_US_H
+#define _SW_API_US_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include "common/sw.h"
+
+ sw_error_t sw_uk_init(a_uint32_t nl_prot);
+
+ sw_error_t sw_uk_cleanup(void);
+
+ sw_error_t sw_uk_if(a_uint32_t arg_val[SW_MAX_API_PARAM]);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_API_INTERFACE_H */
diff --git a/include/sal/sd/sd.h b/include/sal/sd/sd.h
new file mode 100644
index 0000000..2bb9973
--- /dev/null
+++ b/include/sal/sd/sd.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#ifndef _SD_H_
+#define _SD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+ sw_error_t
+ sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+ a_uint16_t data);
+
+ sw_error_t
+ sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+ a_uint16_t * data);
+
+ sw_error_t
+ sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t * reg_data, a_uint32_t len);
+
+ sw_error_t
+ sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t * reg_data, a_uint32_t len);
+
+ sw_error_t sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _SD_H_ */
diff --git a/include/shell/shell.h b/include/shell/shell.h
new file mode 100644
index 0000000..71e065b
--- /dev/null
+++ b/include/shell/shell.h
@@ -0,0 +1,28 @@
+#ifndef _SW_SHELL_H
+#define _SW_SHELL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sw.h"
+#include "sw_api.h"
+#include "ssdk_init.h"
+
+ extern a_uint32_t *ioctl_buf;
+ extern ssdk_init_cfg init_cfg;
+
+#define IOCTL_BUF_SIZE 1024
+#define CMDSTR_BUF_SIZE 1024
+#define CMDSTR_ARGS_MAX 128
+#define dprintf cmd_print
+ extern sw_error_t cmd_exec_api(a_uint32_t *arg_val);
+ extern void cmd_print(char *fmt, ...);
+ void cmd_print_error(sw_error_t rtn);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_SHELL_H */
diff --git a/include/shell/shell_config.h b/include/shell/shell_config.h
new file mode 100644
index 0000000..be55969
--- /dev/null
+++ b/include/shell/shell_config.h
@@ -0,0 +1,64 @@
+#ifndef _SHELL_CONFIG_H_
+#define _SHELL_CONFIG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "sw_api.h"
+
+#define SW_CMD_SET_DEVID (SW_API_MAX + 1)
+#define SW_CMD_VLAN_SHOW (SW_API_MAX + 2)
+#define SW_CMD_FDB_SHOW (SW_API_MAX + 3)
+#define SW_CMD_RESV_FDB_SHOW (SW_API_MAX + 4)
+#define SW_CMD_HOST_SHOW (SW_API_MAX + 5)
+#define SW_CMD_NAT_SHOW (SW_API_MAX + 6)
+#define SW_CMD_NAPT_SHOW (SW_API_MAX + 7)
+#define SW_CMD_INTFMAC_SHOW (SW_API_MAX + 8)
+#define SW_CMD_PUBADDR_SHOW (SW_API_MAX + 9)
+#define SW_CMD_MAX (SW_API_MAX + 10)
+
+#define MAX_SUB_CMD_DES_NUM 60
+
+ struct sub_cmd_des_t
+ {
+ char *sub_name;
+ char *sub_act;
+ char *sub_memo;
+ char *sub_usage;
+ int sub_api;
+ sw_error_t (*sub_func) ();
+ };
+ struct cmd_des_t
+ {
+ char *name;
+ char *memo;
+ struct sub_cmd_des_t sub_cmd_des[MAX_SUB_CMD_DES_NUM];
+ };
+ extern struct cmd_des_t gcmd_des[];
+
+#define GCMD_DES gcmd_des
+
+#define GCMD_NAME(cmd_nr) GCMD_DES[cmd_nr].name
+#define GCMD_MEMO(cmd_nr) GCMD_DES[cmd_nr].memo
+
+#define GCMD_SUB_NAME(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_name
+#define GCMD_SUB_ACT(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_act
+#define GCMD_SUB_MEMO(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_memo
+#define GCMD_SUB_USAGE(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_usage
+#define GCMD_SUB_API(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_api
+#define GCMD_SUB_FUNC(cmd_nr, sub_cmd_nr) GCMD_DES[cmd_nr].sub_cmd_des[sub_cmd_nr].sub_func
+
+#define GCMD_DESC_VALID(cmd_nr) GCMD_NAME(cmd_nr)
+#define GCMD_SUB_DESC_VALID(cmd_nr, sub_cmd_nr) GCMD_SUB_API(cmd_nr, sub_cmd_nr)
+
+
+#define GCMD_DESC_NO_MATCH 0xffffffff
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHELL_CONFIG_H_ */
diff --git a/include/shell/shell_io.h b/include/shell/shell_io.h
new file mode 100644
index 0000000..c433efc
--- /dev/null
+++ b/include/shell/shell_io.h
@@ -0,0 +1,309 @@
+#ifndef _SHELL_IO_H
+#define _SHELL_IO_H
+
+#include "sw.h"
+#include "sw_api.h"
+#include "fal.h"
+
+#define SW_TYPE_DEF(type, parser, show) {type, parser, show}
+typedef struct
+{
+ sw_data_type_e data_type;
+ sw_error_t(*param_check) ();
+ void (*show_func) ();
+} sw_data_type_t;
+
+void set_talk_mode(int mode);
+int get_talk_mode(void);
+void set_full_cmdstrp(char **cmdstrp);
+sw_data_type_t * cmd_data_type_find(sw_data_type_e type);
+void cmd_strtol(char *str, a_uint32_t * arg_val);
+
+
+sw_error_t cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size);
+sw_error_t cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val, a_uint32_t size);
+
+sw_error_t cmd_data_check_uint32(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_uint16(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_enable(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_pbmp(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_duplex(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_speed(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_1qmode(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_egmode(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_capable(char *cmd_str, a_uint32_t * arg_val,
+ a_uint32_t size);
+sw_error_t cmd_data_check_fdbentry(char *cmdstr, void *val, a_uint32_t size);
+sw_error_t cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size);
+
+void cmd_data_print_uint32(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_uint16(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_enable(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_pbmp(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_duplex(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_speed(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size);
+void cmd_data_print_vlan(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_mib(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_1qmode(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_egmode(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_capable(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_fdbentry(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+void cmd_data_print_macaddr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val,
+ a_uint32_t size);
+void cmd_data_print_qos_sch(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val,
+ a_uint32_t size);
+void cmd_data_print_qos_pt(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val,
+ a_uint32_t size);
+void cmd_data_print_storm(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val,
+ a_uint32_t size);
+void cmd_data_print_stp_state(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val,
+ a_uint32_t size);
+void cmd_data_print_leaky(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_uinta(char *cmdstr, a_uint32_t * val,
+ a_uint32_t size);
+void cmd_data_print_uinta(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+sw_error_t cmd_data_check_maccmd(char *cmdstr, fal_fwd_cmd_t * val,
+ a_uint32_t size);
+void cmd_data_print_maccmd(char * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+
+sw_error_t cmd_data_check_aclrule(char *info, void *val, a_uint32_t size);
+
+void cmd_data_print_aclrule(char * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ledpattern(char *info, void * val, a_uint32_t size);
+
+void
+cmd_data_print_ledpattern(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+
+sw_error_t
+cmd_data_check_invlan_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+void
+cmd_data_print_invlan_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+sw_error_t
+cmd_data_check_vlan_propagation(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+void
+cmd_data_print_vlan_propagation(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+sw_error_t
+cmd_data_check_vlan_translation(char *info, fal_vlan_trans_entry_t *val, a_uint32_t size);
+void
+cmd_data_print_vlan_translation(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+sw_error_t
+cmd_data_check_qinq_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+void
+cmd_data_print_qinq_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+sw_error_t
+cmd_data_check_qinq_role(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+void
+cmd_data_print_qinq_role(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+void
+cmd_data_print_cable_status(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+void
+cmd_data_print_cable_len(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+void
+cmd_data_print_ssdk_cfg(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_hdrmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_hdrmode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_fdboperation(char *cmd_str, void * val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_pppoe(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_pppoe(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_udf_type(char *cmdstr, fal_acl_udf_type_t * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_udf_type(char * param_name, a_uint32_t * buf,
+ a_uint32_t size);
+
+sw_error_t
+cmd_data_check_host_entry(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_host_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_arp_learn_mode(char *cmd_str, fal_arp_learn_mode_t * arg_val,
+ a_uint32_t size);
+
+void
+cmd_data_print_arp_learn_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip_guard_mode(char *cmd_str, fal_source_guard_mode_t * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_ip_guard_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_nat_entry(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_nat_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_napt_entry(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_napt_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_napt_mode(char *cmd_str, fal_napt_mode_t * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_napt_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_intf_mac_entry(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_intf_mac_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip4addr(char *cmdstr, void * val, a_uint32_t size);
+
+void
+cmd_data_print_ip4addr(char * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_ip6addr(char *cmdstr, void * val, a_uint32_t size);
+
+void
+cmd_data_print_ip6addr(char * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_pub_addr_entry(char *cmd_str, void * val, a_uint32_t size);
+
+
+void
+cmd_data_print_pub_addr_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_egress_shaper(char *cmd_str, void * val, a_uint32_t size);
+
+
+void
+cmd_data_print_egress_shaper(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_acl_policer(char *cmd_str, void * val, a_uint32_t size);
+
+
+void
+cmd_data_print_acl_policer(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+
+sw_error_t
+cmd_data_check_port_policer(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_port_policer(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_mac_config(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_mac_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_phy_config(char *cmd_str, void * val, a_uint32_t size);
+
+void
+cmd_data_print_phy_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_fdb_smode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_fdb_smode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_fx100_config(char *cmd_str, void * arg_val, a_uint32_t size);
+
+void
+cmd_data_print_fx100_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_multi(char *info, void *val, a_uint32_t size);
+void
+cmd_data_print_multi(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_mac(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_ip6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_tcp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_udp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_icmp4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_sec_icmp6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size);
+
+sw_error_t
+cmd_data_check_remark_entry(char *info, void *val, a_uint32_t size);
+
+void
+cmd_data_print_remark_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size);
+
+#endif
+
diff --git a/include/shell/shell_lib.h b/include/shell/shell_lib.h
new file mode 100644
index 0000000..140d4ce
--- /dev/null
+++ b/include/shell/shell_lib.h
@@ -0,0 +1,17 @@
+#ifndef _SW_SHELL_LIB_H
+#define _SW_SHELL_LIB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ int next_cmd(char *out_cmd);
+ ssize_t getline(char **lineptr, size_t *n, FILE *stream);
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SW_SHELL_LIB_H */
+
diff --git a/include/shell/shell_sw.h b/include/shell/shell_sw.h
new file mode 100644
index 0000000..88f9b3f
--- /dev/null
+++ b/include/shell/shell_sw.h
@@ -0,0 +1,25 @@
+#ifndef _SHELL_SW_H_
+#define _SHELL_SW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sw.h"
+
+ int get_devid(void);
+ sw_error_t cmd_set_devid(a_uint32_t *arg_val);
+ sw_error_t cmd_show_fdb(a_uint32_t *arg_val);
+ sw_error_t cmd_show_vlan(a_uint32_t *arg_val);
+ sw_error_t cmd_show_resv_fdb(a_uint32_t *arg_val);
+ sw_error_t cmd_show_host(a_uint32_t *arg_val);
+ sw_error_t cmd_show_nat(a_uint32_t *arg_val);
+ sw_error_t cmd_show_napt(a_uint32_t *arg_val);
+ sw_error_t cmd_show_intfmac(a_uint32_t *arg_val);
+ sw_error_t cmd_show_pubaddr(a_uint32_t *arg_val);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _SHELL_SW_H_ */
diff --git a/ko_Makefile b/ko_Makefile
new file mode 100644
index 0000000..70649b0
--- /dev/null
+++ b/ko_Makefile
@@ -0,0 +1,3 @@
+obj-m := qca-ssdk.o
+OBJ_LIST:=$(wildcard ./*.o)
+qca-ssdk-objs := api_access.o hsl_port_prop.o isisc_igmp.o isisc_led.o isisc_sec.o isisc_nat.o isisc_reg_access.o sd.o f1_phy.o isisc_acl.o isisc_init.o isisc_mib.o isisc_port_ctrl.o isisc_stp.o ssdk_init.o hsl_acl.o isisc_acl_parse.o isisc_interface_ctrl.o isisc_mirror.o isisc_portvlan.o isisc_trunk.o hsl_api.o isisc_cosmap.o isisc_ip.o isisc_misc.o isisc_qos.o isisc_vlan.o sw_api_ks_ioctl.o hsl_dev.o isisc_fdb.o isisc_leaky.o isisc_multicast_acl.o isisc_rate.o util.o
diff --git a/make/.build_number b/make/.build_number
new file mode 100644
index 0000000..0cfbf08
--- /dev/null
+++ b/make/.build_number
@@ -0,0 +1 @@
+2
diff --git a/make/components.mk b/make/components.mk
new file mode 100644
index 0000000..bd162be
--- /dev/null
+++ b/make/components.mk
@@ -0,0 +1,36 @@
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifeq (TRUE, $(KERNEL_MODE))
+ COMPONENTS = HSL SAL INIT UTIL
+ ifeq (TRUE, $(FAL))
+ COMPONENTS += FAL
+ endif
+ else
+ COMPONENTS = HSL SAL INIT
+ endif
+
+ ifeq (TRUE, $(UK_IF))
+ COMPONENTS += API
+ endif
+ endif
+
+ ifeq (USLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ COMPONENTS = HSL SAL INIT UTIL
+ ifeq (TRUE, $(FAL))
+ COMPONENTS += FAL
+ endif
+ else
+ COMPONENTS = UK_IF SAL
+ endif
+
+ ifeq (TRUE, $(UK_IF))
+ COMPONENTS += API
+ endif
+ endif
+
+ ifeq (SHELL, $(MODULE_TYPE))
+ COMPONENTS = SHELL
+ endif
+endif
diff --git a/make/config.mk b/make/config.mk
new file mode 100644
index 0000000..6a2c15f
--- /dev/null
+++ b/make/config.mk
@@ -0,0 +1,91 @@
+
+include $(PRJ_PATH)/config
+
+ifndef SYS_PATH
+ $(error SYS_PATH isn't defined!)
+endif
+
+ifndef TOOL_PATH
+ $(error TOOL_PATH isn't defined!)
+endif
+
+#define cpu type such as PPC MIPS ARM X86
+ifndef CPU
+ CPU=mips
+endif
+
+#define os type such as linux netbsd vxworks
+ifndef OS
+ OS=linux
+endif
+
+ifndef OS_VER
+ OS_VER=2_6
+endif
+
+#support chip type such as ATHENA GARUDA
+ifndef CHIP_TYPE
+ SUPPORT_CHIP = GARUDA
+else
+ ifeq (GARUDA, $(CHIP_TYPE))
+ SUPPORT_CHIP = GARUDA
+ endif
+
+ ifeq (ATHENA, $(CHIP_TYPE))
+ SUPPORT_CHIP = ATHENA
+ endif
+
+ ifeq (SHIVA, $(CHIP_TYPE))
+ SUPPORT_CHIP = SHIVA
+ endif
+
+ ifeq (HORUS, $(CHIP_TYPE))
+ SUPPORT_CHIP = HORUS
+ endif
+
+ ifeq (ISIS, $(CHIP_TYPE))
+ SUPPORT_CHIP = ISIS
+ endif
+
+ ifeq (ISISC, $(CHIP_TYPE))
+ SUPPORT_CHIP = ISISC
+ endif
+
+ ifeq (ALL_CHIP, $(CHIP_TYPE))
+ ifneq (TRUE, $(FAL))
+ $(error FAL must be TRUE when CHIP_TYPE is defined as ALL_CHIP!)
+ endif
+ SUPPORT_CHIP = GARUDA SHIVA HORUS ISIS ISISC
+ endif
+
+ ifndef SUPPORT_CHIP
+ $(error defined CHIP_TYPE isn't supported!)
+ endif
+endif
+
+#define compile tool prefix
+ifndef TOOLPREFIX
+ TOOLPREFIX=$(CPU)-$(OS)-uclibc-
+endif
+
+DEBUG_ON=FALSE
+OPT_FLAG=
+LD_FLAG=
+
+SHELLOBJ=ssdk_sh
+US_MOD=ssdk_us
+KS_MOD=ssdk_ks
+
+ifeq (TRUE, $(KERNEL_MODE))
+ RUNMODE=km
+else
+ RUNMODE=um
+endif
+
+BLD_DIR=$(PRJ_PATH)/build/$(OS)_$(CPU)
+BIN_DIR=$(PRJ_PATH)/build/bin
+
+VER=1.1.3
+BUILD_NUMBER=$(shell cat $(PRJ_PATH)/make/.build_number)
+VERSION=$(VER).$(BUILD_NUMBER)
+BUILD_DATE=$(shell date -u +%F-%T)
diff --git a/make/defs.mk b/make/defs.mk
new file mode 100644
index 0000000..7d1c75b
--- /dev/null
+++ b/make/defs.mk
@@ -0,0 +1,28 @@
+DST_DIR=$(BLD_DIR)/$(MODULE_TYPE)
+
+SUB_DIR=$(patsubst %/, %, $(dir $(wildcard ./*/Makefile)))
+
+ifeq (,$(findstring $(LIB), $(COMPONENTS)))
+ SRC_LIST=
+endif
+
+SRC_FILE=$(addprefix $(PRJ_PATH)/$(LOC_DIR)/, $(SRC_LIST))
+
+OBJ_LIST=$(SRC_LIST:.c=.o)
+OBJ_FILE=$(addprefix $(DST_DIR)/, $(OBJ_LIST))
+
+DEP_LIST=$(SRC_LIST:.c=.d)
+DEP_FILE=$(addprefix $(DST_DIR)/, $(DEP_LIST))
+
+vpath %.c $(PRJ_PATH)/$(LOC_DIR)
+vpath %.c $(PRJ_PATH)/app/nathelper/linux
+vpath %.c $(PRJ_PATH)/app/nathelper/linux/lib
+vpath %.o $(DST_DIR)
+vpath %.d $(DST_DIR)
+
+DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) dep || exit 1;)
+OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) obj || exit 1;)
+CLEAN_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean;)
+CLEAN_OBJ_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_o;)
+CLEAN_DEP_LOOP=$(foreach i, $(SUB_DIR), $(MAKE) -C $(i) clean_d;)
+
diff --git a/make/linux_opt.mk b/make/linux_opt.mk
new file mode 100644
index 0000000..df65d8b
--- /dev/null
+++ b/make/linux_opt.mk
@@ -0,0 +1,277 @@
+ifeq (TRUE, $(IN_ACL))
+ MODULE_CFLAG += -DIN_ACL
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ MODULE_CFLAG += -DIN_FDB
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ MODULE_CFLAG += -DIN_IGMP
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ MODULE_CFLAG += -DIN_LEAKY
+endif
+
+ifeq (TRUE, $(IN_LED))
+ MODULE_CFLAG += -DIN_LED
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ MODULE_CFLAG += -DIN_MIB
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ MODULE_CFLAG += -DIN_MIRROR
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ MODULE_CFLAG += -DIN_MISC
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ MODULE_CFLAG += -DIN_PORTCONTROL
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ MODULE_CFLAG += -DIN_PORTVLAN
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ MODULE_CFLAG += -DIN_QOS
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ MODULE_CFLAG += -DIN_RATE
+endif
+
+ifeq (TRUE, $(IN_STP))
+ MODULE_CFLAG += -DIN_STP
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ MODULE_CFLAG += -DIN_VLAN
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ MODULE_CFLAG += -DIN_REDUCED_ACL
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+ MODULE_CFLAG += -DIN_COSMAP
+endif
+
+ifeq (TRUE, $(IN_IP))
+ MODULE_CFLAG += -DIN_IP
+endif
+
+ifeq (TRUE, $(IN_NAT))
+ MODULE_CFLAG += -DIN_NAT
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+ MODULE_CFLAG += -DIN_TRUNK
+endif
+
+ifeq (TRUE, $(IN_SEC))
+ MODULE_CFLAG += -DIN_SEC
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+ MODULE_CFLAG += -DIN_NAT_HELPER
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+ MODULE_CFLAG += -DIN_INTERFACECONTROL
+endif
+
+ifeq (TRUE, $(IN_MACBLOCK))
+ MODULE_CFLAG += -DIN_MACBLOCK
+endif
+
+ifneq (TRUE, $(FAL))
+ MODULE_CFLAG += -DHSL_STANDALONG
+endif
+
+ifeq (TRUE, $(UK_IF))
+ MODULE_CFLAG += -DUK_IF
+endif
+
+#ifdef UK_NL_PROT
+ MODULE_CFLAG += -DUK_NL_PROT=$(UK_NL_PROT)
+#endif
+
+#ifdef UK_MINOR_DEV
+ MODULE_CFLAG += -DUK_MINOR_DEV=$(UK_MINOR_DEV)
+#endif
+
+ifeq (TRUE, $(API_LOCK))
+ MODULE_CFLAG += -DAPI_LOCK
+endif
+
+ifeq (TRUE, $(REG_ACCESS_SPEEDUP))
+ MODULE_CFLAG += -DREG_ACCESS_SPEEDUP
+endif
+
+ifeq (TRUE, $(DEBUG_ON))
+ MODULE_CFLAG += -g
+endif
+
+MODULE_CFLAG += $(OPT_FLAG) -Wall -DVERSION=\"$(VERSION)\" -DBUILD_DATE=\"$(BUILD_DATE)\" -DCPU=\"$(CPU)\" -DOS=\"$(OS)\"
+
+MODULE_INC += -I$(PRJ_PATH)/include \
+ -I$(PRJ_PATH)/include/common \
+ -I$(PRJ_PATH)/include/api \
+ -I$(PRJ_PATH)/include/fal \
+ -I$(PRJ_PATH)/include/hsl \
+ -I$(PRJ_PATH)/include/hsl/phy \
+ -I$(PRJ_PATH)/include/sal/os \
+ -I$(PRJ_PATH)/include/sal/sd \
+ -I$(PRJ_PATH)/include/sal/sd/linux/hydra_howl \
+ -I$(PRJ_PATH)/include/sal/sd/linux/uk_interface \
+ -I$(PRJ_PATH)/include/init
+
+ifneq (,$(findstring ATHENA, $(SUPPORT_CHIP)))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/athena
+ MODULE_CFLAG += -DATHENA
+endif
+
+ifneq (,$(findstring GARUDA, $(SUPPORT_CHIP)))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/garuda
+ MODULE_CFLAG += -DGARUDA
+endif
+
+ifneq (,$(findstring SHIVA, $(SUPPORT_CHIP)))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/shiva
+ MODULE_CFLAG += -DSHIVA
+endif
+
+ifneq (,$(findstring HORUS, $(SUPPORT_CHIP)))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/horus
+ MODULE_CFLAG += -DHORUS
+endif
+
+ifneq (,$(findstring ISIS, $(SUPPORT_CHIP)))
+ ifneq (ISISC, $(SUPPORT_CHIP))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/isis
+ MODULE_CFLAG += -DISIS
+ endif
+endif
+
+ifneq (,$(findstring ISISC, $(SUPPORT_CHIP)))
+ MODULE_INC += -I$(PRJ_PATH)/include/hsl/isisc
+ MODULE_CFLAG += -DISISC
+endif
+
+# check for GCC version
+ifeq (4, $(GCC_VER))
+ MODULE_CFLAG += -DGCCV4
+endif
+
+ifeq (KSLIB, $(MODULE_TYPE))
+
+ ifeq (3_4, $(OS_VER))
+ MODULE_CFLAG += -DKVER34
+ MODULE_CFLAG += -DKVER32
+ MODULE_CFLAG += -DLNX26_22
+ MODULE_INC += -I$(SYS_PATH) \
+ -I$(SYS_PATH)/include \
+ -I$(SYS_PATH)/source/include \
+ -I$(SYS_PATH)/source/arch/arm/mach-msm/include \
+ -I$(SYS_PATH)/source/arch/arm/include \
+ -I$(SYS_PATH)/source/arch/arm/include/asm \
+ -I$(SYS_PATH)/arch/arm/include/generated \
+ -I$(SYS_PATH)/source/arch/arm/include/asm/mach \
+ -I$(SYS_PATH)/usr/include
+
+ endif
+
+ ifeq (3_2, $(OS_VER))
+ MODULE_CFLAG += -DKVER32
+ MODULE_CFLAG += -DLNX26_22
+ ifeq (mips, $(CPU))
+ MODULE_INC += -I$(SYS_PATH) \
+ -I$(SYS_PATH)/include \
+ -I$(SYS_PATH)/arch/mips/include \
+ -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \
+ -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \
+ -I$(SYS_PATH)/usr/include
+
+ #CPU_CFLAG = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2
+ ifndef CPU_CFLAG
+ CPU_CFLAG = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \
+ -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+ endif
+ else
+ MODULE_INC += -I$(SYS_PATH) \
+ -I$(SYS_PATH)/include \
+ -I$(SYS_PATH)/arch/arm/include \
+ -I$(SYS_PATH)/arch/arm/include/asm \
+ -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \
+ -I$(SYS_PATH)/arch/arm/include/generated \
+ -I$(SYS_PATH)/include/generated \
+ -I$(SYS_PATH)/usr/include
+ endif
+
+
+ endif
+
+ ifeq (2_6, $(OS_VER))
+ MODULE_CFLAG += -DKVER26
+ MODULE_CFLAG += -DLNX26_22
+ ifeq (mips, $(CPU))
+ MODULE_INC += -I$(SYS_PATH) \
+ -I$(SYS_PATH)/include \
+ -I$(SYS_PATH)/arch/mips/include \
+ -I$(SYS_PATH)/arch/mips/include/asm/mach-ar7240 \
+ -I$(SYS_PATH)/arch/mips/include/asm/mach-generic \
+ -I$(SYS_PATH)/usr/include
+
+ #CPU_CFLAG = -G 0 -mno-abicalls -fno-pic -pipe -mabi=32 -march=mips32r2
+ ifndef CPU_CFLAG
+ CPU_CFLAG = -Wstrict-prototypes -fomit-frame-pointer -G 0 -mno-abicalls -fno-strict-aliasing \
+ -O2 -fno-pic -pipe -mabi=32 -march=mips32r2 -DMODULE -mlong-calls -DEXPORT_SYMTAB
+ endif
+ else
+ MODULE_INC += -I$(SYS_PATH) \
+ -I$(SYS_PATH)/include \
+ -I$(SYS_PATH)/arch/arm/include \
+ -I$(SYS_PATH)/arch/arm/include/asm \
+ -I$(SYS_PATH)/arch/arm/mach-fv16xx/include \
+ -I$(SYS_PATH)/arch/arm/include/generated \
+ -I$(SYS_PATH)/include/generated \
+ -I$(SYS_PATH)/usr/include
+ endif
+
+
+ endif
+
+ MODULE_CFLAG += -D__KERNEL__ -DKERNEL_MODULE $(CPU_CFLAG)
+
+
+endif
+
+ifeq (SHELL, $(MODULE_TYPE))
+ MODULE_INC += -I$(PRJ_PATH)/include/shell
+
+ ifeq (2_6, $(OS_VER))
+ MODULE_CFLAG += -DKVER26
+ else
+ MODULE_CFLAG += -DKVER24
+ endif
+
+ ifeq (TRUE, $(KERNEL_MODE))
+ MODULE_CFLAG += -static
+ else
+ MODULE_CFLAG += -static -DUSER_MODE
+ endif
+endif
+
+ifneq (TRUE, $(KERNEL_MODE))
+ ifneq (SHELL, $(MODULE_TYPE))
+ MODULE_CFLAG += -DUSER_MODE
+ endif
+endif
+
+CFLAGS += $(MODULE_INC) $(MODULE_CFLAG)
diff --git a/make/target.mk b/make/target.mk
new file mode 100644
index 0000000..a72c239
--- /dev/null
+++ b/make/target.mk
@@ -0,0 +1,49 @@
+
+include $(PRJ_PATH)/make/$(OS)_opt.mk
+
+include $(PRJ_PATH)/make/tools.mk
+
+obj: $(OBJ_LIST)
+ $(OBJ_LOOP)
+
+dep: build_dir $(DEP_LIST)
+ $(DEP_LOOP)
+
+$(OBJ_LIST): %.o : %.c %.d
+ $(CC) $(CFLAGS) -c $< -o $(DST_DIR)/$@
+
+$(DEP_LIST) : %.d : %.c
+ $(CC) $(CFLAGS) -MM $< > $(DST_DIR)/$@.tmp
+ sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < $(DST_DIR)/$@.tmp > $(DST_DIR)/$@
+ $(RM) -f $(DST_DIR)/$@.tmp;
+
+build_dir: $(DST_DIR)
+
+$(DST_DIR):
+ $(MKDIR) -p $(DST_DIR)
+
+.PHONY: clean
+clean: clean_o clean_d
+ $(CLEAN_LOOP)
+
+.PHONY: clean_o
+clean_o: clean_obj
+ $(CLEAN_OBJ_LOOP)
+
+.PHONY: clean_d
+clean_d: clean_dep
+ $(CLEAN_DEP_LOOP)
+
+clean_obj:
+ifneq (,$(word 1, $(OBJ_FILE)))
+ $(RM) -f $(OBJ_FILE)
+endif
+
+clean_dep:
+ifneq (,$(word 1, $(DEP_FILE)))
+ $(RM) -f $(DEP_FILE)
+endif
+
+ifneq (,$(word 1, $(DEP_FILE)))
+ sinclude $(DEP_FILE)
+endif
diff --git a/make/tools.mk b/make/tools.mk
new file mode 100644
index 0000000..6ed3872
--- /dev/null
+++ b/make/tools.mk
@@ -0,0 +1,12 @@
+
+ifeq (linux, $(OS))
+ CC=$(TOOL_PATH)/$(TOOLPREFIX)gcc
+ AR=$(TOOL_PATH)/$(TOOLPREFIX)ar
+ LD=$(TOOL_PATH)/$(TOOLPREFIX)ld
+ STRIP=$(TOOL_PATH)/$(TOOLPREFIX)strip
+ MAKE=make -S
+ CP=cp
+ MKDIR=mkdir
+ RM=rm
+ PERL=perl
+endif
diff --git a/src/api/Makefile b/src/api/Makefile
new file mode 100644
index 0000000..25c788a
--- /dev/null
+++ b/src/api/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal
+LIB=API
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/api/api_access.c b/src/api/api_access.c
new file mode 100644
index 0000000..1891c77
--- /dev/null
+++ b/src/api/api_access.c
@@ -0,0 +1,262 @@
+#include "sw.h"
+#include "fal.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#if defined ATHENA
+#include "fal_igmp.h"
+#include "fal_leaky.h"
+#include "athena_mib.h"
+#include "athena_port_ctrl.h"
+#include "athena_portvlan.h"
+#include "athena_fdb.h"
+#include "athena_vlan.h"
+#include "athena_init.h"
+#include "athena_reg_access.h"
+#include "athena_reg.h"
+#elif defined GARUDA
+#include "garuda_mib.h"
+#include "garuda_qos.h"
+#include "garuda_rate.h"
+#include "garuda_port_ctrl.h"
+#include "garuda_portvlan.h"
+#include "garuda_fdb.h"
+#include "garuda_vlan.h"
+#include "garuda_mirror.h"
+#include "garuda_stp.h"
+#include "garuda_misc.h"
+#include "garuda_leaky.h"
+#include "garuda_igmp.h"
+#include "garuda_acl.h"
+#include "garuda_led.h"
+#include "garuda_init.h"
+#include "garuda_reg_access.h"
+#include "garuda_reg.h"
+#elif defined SHIVA
+#include "shiva_mib.h"
+#include "shiva_qos.h"
+#include "shiva_rate.h"
+#include "shiva_port_ctrl.h"
+#include "shiva_portvlan.h"
+#include "shiva_fdb.h"
+#include "shiva_vlan.h"
+#include "shiva_mirror.h"
+#include "shiva_stp.h"
+#include "shiva_misc.h"
+#include "shiva_leaky.h"
+#include "shiva_igmp.h"
+#include "shiva_acl.h"
+#include "shiva_led.h"
+#include "shiva_init.h"
+#include "shiva_reg_access.h"
+#include "shiva_reg.h"
+#elif defined HORUS
+#include "horus_mib.h"
+#include "horus_qos.h"
+#include "horus_rate.h"
+#include "horus_port_ctrl.h"
+#include "horus_portvlan.h"
+#include "horus_fdb.h"
+#include "horus_vlan.h"
+#include "horus_mirror.h"
+#include "horus_stp.h"
+#include "horus_misc.h"
+#include "horus_leaky.h"
+#include "horus_igmp.h"
+#include "horus_led.h"
+#include "horus_init.h"
+#include "horus_reg_access.h"
+#include "horus_reg.h"
+#elif defined ISIS
+#include "isis_mib.h"
+#include "isis_qos.h"
+#include "isis_cosmap.h"
+#include "isis_rate.h"
+#include "isis_port_ctrl.h"
+#include "isis_portvlan.h"
+#include "isis_fdb.h"
+#include "isis_vlan.h"
+#include "isis_mirror.h"
+#include "isis_stp.h"
+#include "isis_misc.h"
+#include "isis_leaky.h"
+#include "isis_igmp.h"
+#include "isis_acl.h"
+#include "isis_led.h"
+#include "isis_cosmap.h"
+#include "isis_ip.h"
+#include "isis_nat.h"
+#include "isis_trunk.h"
+#include "isis_sec.h"
+#include "isis_interface_ctrl.h"
+#include "isis_init.h"
+#include "isis_reg_access.h"
+#include "isis_reg.h"
+#elif defined ISISC
+#include "isisc_mib.h"
+#include "isisc_qos.h"
+#include "isisc_cosmap.h"
+#include "isisc_rate.h"
+#include "isisc_port_ctrl.h"
+#include "isisc_portvlan.h"
+#include "isisc_fdb.h"
+#include "isisc_vlan.h"
+#include "isisc_mirror.h"
+#include "isisc_stp.h"
+#include "isisc_misc.h"
+#include "isisc_leaky.h"
+#include "isisc_igmp.h"
+#include "isisc_acl.h"
+#include "isisc_led.h"
+#include "isisc_cosmap.h"
+#include "isisc_ip.h"
+#include "isisc_nat.h"
+#include "isisc_trunk.h"
+#include "isisc_sec.h"
+#include "isisc_interface_ctrl.h"
+#include "isisc_init.h"
+#include "isisc_reg_access.h"
+#include "isisc_reg.h"
+#endif
+
+#include "sw_api.h"
+#include "api_desc.h"
+#if (((!defined(USER_MODE)) && defined(KERNEL_MODULE)) || (defined(USER_MODE) && (!defined(KERNEL_MODULE))))
+#ifdef HSL_STANDALONG
+#if defined ATHENA
+#include "athena_api.h"
+#elif defined GARUDA
+#include "garuda_api.h"
+#elif defined SHIVA
+#include "shiva_api.h"
+#elif defined HORUS
+#include "horus_api.h"
+#elif defined ISIS
+#include "isis_api.h"
+#elif defined ISISC
+#include "isisc_api.h"
+#endif
+#else
+#include "fal_api.h"
+#endif
+#elif (defined(USER_MODE))
+#if defined ATHENA
+#include "athena_api.h"
+#elif defined GARUDA
+#include "garuda_api.h"
+#elif defined SHIVA
+#include "shiva_api.h"
+#elif defined HORUS
+#include "horus_api.h"
+#elif defined ISIS
+#include "isis_api.h"
+#elif defined ISISC
+#include "isisc_api.h"
+#endif
+#else
+#include "fal_api.h"
+#endif
+
+
+static sw_api_func_t sw_api_func[] = { SSDK_API };
+static sw_api_param_t sw_api_param[] = { SSDK_PARAM };
+
+sw_api_func_t *
+sw_api_func_find(a_uint32_t api_id)
+{
+ a_uint32_t i = 0;
+ static a_uint32_t save = 0;
+
+ if(api_id == sw_api_func[save].api_id)
+ return &sw_api_func[save];
+
+ do
+ {
+ if (api_id == sw_api_func[i].api_id)
+ {
+ save = i;
+ return &sw_api_func[i];
+ }
+
+ }
+ while (++i < (sizeof(sw_api_func)/sizeof(sw_api_func[0])));
+
+ return NULL;
+}
+
+sw_api_param_t *
+sw_api_param_find(a_uint32_t api_id)
+{
+ a_uint32_t i = 0;
+ static a_uint32_t save = 0;
+
+ if(api_id == sw_api_param[save].api_id)
+ return &sw_api_param[save];
+
+ do
+ {
+ if (api_id == sw_api_param[i].api_id)
+ {
+ save = i;
+ return &sw_api_param[i];
+ }
+ }
+ while (++i < (sizeof(sw_api_param)/sizeof(sw_api_param[0])));
+
+ return NULL;
+}
+
+a_uint32_t
+sw_api_param_nums(a_uint32_t api_id)
+{
+ a_uint32_t i = 0;
+ sw_api_param_t *p = NULL;
+ static sw_api_param_t *savep = NULL;
+ static a_uint32_t save = 0;
+
+ p = sw_api_param_find(api_id);
+ if (!p)
+ {
+ return 0;
+ }
+
+ if (p == savep)
+ {
+ return save;
+ }
+
+ savep = p;
+ while (api_id == p->api_id)
+ {
+ p++;
+ i++;
+ }
+
+ /*error*/
+ if(i >= sizeof(sw_api_param)/sizeof(sw_api_param[0]))
+ {
+ savep = NULL;
+ save = 0;
+ return 0;
+ }
+ save = i;
+
+ return i;
+}
+
+sw_error_t
+sw_api_get(sw_api_t *sw_api)
+{
+ if(!sw_api)
+ return SW_FAIL;
+
+ if ((sw_api->api_fp = sw_api_func_find(sw_api->api_id)) == NULL)
+ return SW_NOT_SUPPORTED;
+
+ if ((sw_api->api_pp = sw_api_param_find(sw_api->api_id)) == NULL)
+ return SW_NOT_SUPPORTED;
+
+ if((sw_api->api_nr = sw_api_param_nums(sw_api->api_id)) == 0)
+ return SW_NOT_SUPPORTED;
+
+ return SW_OK;
+}
diff --git a/src/fal/Makefile b/src/fal/Makefile
new file mode 100644
index 0000000..a534765
--- /dev/null
+++ b/src/fal/Makefile
@@ -0,0 +1,92 @@
+LOC_DIR=src/fal
+LIB=FAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=fal_init.c fal_reg_access.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += fal_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += fal_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += fal_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += fal_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += fal_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += fal_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += fal_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += fal_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += fal_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += fal_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += fal_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += fal_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += fal_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += fal_vlan.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+ SRC_LIST += fal_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+ SRC_LIST += fal_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+ SRC_LIST += fal_nat.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+ SRC_LIST += fal_sec.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+ SRC_LIST += fal_trunk.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+ SRC_LIST += fal_interface_ctrl.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/fal/fal_acl.c b/src/fal/fal_acl.c
new file mode 100644
index 0000000..f6510ce
--- /dev/null
+++ b/src/fal/fal_acl.c
@@ -0,0 +1,595 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_acl FAL_ACL
+ * @{
+ */
+#include "sw.h"
+#include "fal_acl.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_list_creat)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_list_creat(dev_id, list_id, prio);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_list_destroy)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_list_destroy(dev_id, list_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_delete)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_query)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_query(dev_id, list_id, rule_id, rule);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_list_bind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_list_unbind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_port_udf_profile_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_port_udf_profile_set(dev_id, port_id, udf_type, offset, length);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_port_udf_profile_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_port_udf_profile_get(dev_id, port_id, udf_type, offset, length);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_active)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_active(dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_deactive)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_deactive(dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_src_filter_sts_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_src_filter_sts_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+ return rv;
+}
+
+
+
+sw_error_t
+fal_acl_list_dump(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_list_dump)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_list_dump(dev_id);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_dump(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->acl_rule_dump)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_dump(dev_id);
+ return rv;
+}
+/**
+ * @brief Creat an acl list
+ * @details Comments:
+ * If the priority of a list is more small then the priority is more high,
+ * that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_list_creat(dev_id, list_id, prio);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_list_destroy(dev_id, list_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_query(dev_id, list_id, rule_id, rule);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+ length);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+ length);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_active(dev_id, list_id, rule_id, rule_nr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_deactive(dev_id, list_id, rule_id, rule_nr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief set status of one rule source filter
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get status of one rule source filter
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_cosmap.c b/src/fal/fal_cosmap.c
new file mode 100644
index 0000000..7caa626
--- /dev/null
+++ b/src/fal/fal_cosmap.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_cosmap FAL_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "fal_cosmap.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_to_pri_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_to_pri_set(dev_id, dscp, pri);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_to_pri_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_to_pri_get(dev_id, dscp, pri);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_to_dp_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_to_dp_set(dev_id, dscp, dp);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_to_dp_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_to_dp_get(dev_id, dscp, dp);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_to_pri_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_to_pri_set(dev_id, up, pri);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_to_pri_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_to_pri_get(dev_id, up, pri);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_to_dp_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_to_dp_set(dev_id, up, dp);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_to_dp_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_to_dp_get(dev_id, up, dp);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_pri_to_queue_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_pri_to_queue_set(dev_id, pri, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_pri_to_queue_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_pri_to_queue_get(dev_id, pri, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_pri_to_ehqueue_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_pri_to_ehqueue_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_egress_remark_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+ return rv;
+}
+
+static sw_error_t
+_fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_egress_remark_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+ return rv;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_to_pri_set(dev_id, dscp, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_to_pri_get(dev_id, dscp, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_to_dp_set(dev_id, dscp, dp);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_to_dp_get(dev_id, dscp, dp);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_to_pri_set(dev_id, up, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_to_pri_get(dev_id, up, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_to_dp_set(dev_id, up, dp);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_to_dp_get(dev_id, up, dp);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_pri_to_queue_set(dev_id, pri, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_pri_to_queue_get(dev_id, pri, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_fdb.c b/src/fal/fal_fdb.c
new file mode 100644
index 0000000..24944a5
--- /dev/null
+++ b/src/fal/fal_fdb.c
@@ -0,0 +1,1208 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_fdb FAL_FDB
+ * @{
+ */
+#include "sw.h"
+#include "fal_fdb.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_add(dev_id, entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_del_all)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_del_all(dev_id, flag);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_del_by_port)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_del_by_port(dev_id, port_id, flag);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_del_by_mac)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_del_by_mac(dev_id, entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_first)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_first(dev_id, entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_next(dev_id, entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_find)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_find(dev_id, entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_learn_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_learn_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_learn_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_learn_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->age_ctrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->age_ctrl_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->age_ctrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->age_ctrl_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_ivl_svl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_ivl_svl_set(dev_id, smode);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_ivl_svl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_ivl_svl_get(dev_id, smode);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->age_time_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->age_time_set(dev_id, time);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->age_time_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->age_time_get(dev_id, time);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_iterate)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_iterate(dev_id, iterator, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_extend_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_extend_next(dev_id, option, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_extend_first)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_extend_first(dev_id, option, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_transfer)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_transfer(dev_id, old_port, new_port, fid, option);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_fdb_learn_limit_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_fdb_learn_limit_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_fdb_learn_exceed_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_fdb_learn_exceed_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_learn_limit_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_learn_limit_set(dev_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_learn_limit_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_learn_limit_get(dev_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_learn_exceed_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_learn_exceed_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_learn_exceed_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_learn_exceed_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_resv_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_resv_add(dev_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_resv_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_resv_del(dev_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_resv_find)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_resv_find(dev_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_resv_iterate)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_resv_iterate(dev_id, iterator, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_port_learn_static_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_port_learn_static_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_port_learn_static_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_port_learn_static_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_port_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_port_add(dev_id, fid, addr, port_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->fdb_port_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->fdb_port_del(dev_id, fid, addr, port_id);
+ return rv;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_add(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_del_all(dev_id, flag);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_del_by_port(dev_id, port_id, flag);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_del_by_mac(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_first(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_next(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_find(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_learn_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_learn_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_age_ctrl_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_age_ctrl_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief set arl search mode as ivl or svl when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_vlan_ivl_svl_set(dev_id, smode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get arl search mode when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_vlan_ivl_svl_get(dev_id, smode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_age_time_set(dev_id, time);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_age_time_get(dev_id, time);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_iterate(dev_id, iterator, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_extend_next(dev_id, option, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_extend_first(dev_id, option, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_transfer(dev_id, old_port, new_port, fid, option);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_learn_limit_set(dev_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_learn_limit_get(dev_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_learn_exceed_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_learn_exceed_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_resv_add(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_resv_del(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_resv_find(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_resv_iterate(dev_id, iterator, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_learn_static_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_learn_static_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+sw_error_t
+fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_add(dev_id, fid, addr, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+sw_error_t
+fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_fdb_port_del(dev_id, fid, addr, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_igmp.c b/src/fal/fal_igmp.c
new file mode 100644
index 0000000..e3e1cd1
--- /dev/null
+++ b/src/fal/fal_igmp.c
@@ -0,0 +1,927 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+* @defgroup fal_igmp FAL_IGMP
+* @{
+*/
+#include "sw.h"
+#include "fal_igmp.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmps_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmps_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmps_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmps_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_mld_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_mld_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_mld_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_mld_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_join_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_join_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_join_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_join_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_leave_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_leave_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_leave_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_leave_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_rp_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_rp_set(dev_id, pts);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_rp_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_rp_get(dev_id, pts);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_creat_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_creat_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_creat_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_creat_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_static_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_static_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_static_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_static_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_leaky_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_leaky_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_leaky_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_leaky_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_v3_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_v3_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_v3_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_v3_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_queue_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_queue_set(dev_id, enable, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_entry_queue_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_entry_queue_get(dev_id, enable, queue);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_mld_learn_limit_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_mld_learn_limit_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_igmp_mld_learn_exceed_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_sg_entry_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_sg_entry_set(dev_id, entry);
+ return rv;
+}
+static sw_error_t
+_fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_sg_entry_clear)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_sg_entry_clear(dev_id, entry);
+ return rv;
+}
+static sw_error_t
+_fal_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->igmp_sg_entry_show)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->igmp_sg_entry_show(dev_id);
+ return rv;
+}
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmps_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmps_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_join_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_join_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp join feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_leave_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_leave_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_rp_set(dev_id, pts);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_rp_get(dev_id, pts);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_creat_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_creat_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * static status hardware will not age out multicast entry which leardned by hardware,
+ * otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_static_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_static_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_leaky_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_leaky_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details Comments:
+ * After enabling igmp join/leave feature on a particular port hardware will dynamic
+ * creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_v3_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_v3_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_queue_set(dev_id, enable, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_mld_entry_queue_get(dev_id, enable, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_sg_entry_set(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+sw_error_t
+fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_sg_entry_clear(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+sw_error_t
+fal_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_igmp_sg_entry_show(dev_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_init.c b/src/fal/fal_init.c
new file mode 100644
index 0000000..c7102c4
--- /dev/null
+++ b/src/fal/fal_init.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_init FAL_INIT
+ * @{
+ */
+#include "sw.h"
+#include "fal_vlan.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_api.h"
+
+
+/**
+ * @brief Init fal layer.
+ * @details Comments:
+ * This operation will init fal layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ sw_error_t rv;
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = hsl_api_init(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = hsl_dev_init(dev_id, cfg);
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef IN_VLAN
+ rv = fal_vlan_init(dev_id);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ return rv;
+}
+
+
+/**
+ * @brief Init fal layer.
+ * @details Comments:
+ * This operation will init fal layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cpu_mode cpu port connecting mode
+ * @param[in] reg_mode register access mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode, hsl_access_mode reg_mode)
+{
+ sw_error_t rv;
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = hsl_api_init(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = hsl_dev_reduced_init(dev_id, cpu_mode, reg_mode);
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef IN_VLAN
+ rv = fal_vlan_init(dev_id);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ return rv;
+}
+
+
+static sw_error_t
+_fal_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->dev_reset)
+ return SW_NOT_SUPPORTED;
+
+#ifdef IN_VLAN
+ rv = fal_vlan_reset(dev_id);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ rv = p_api->dev_reset(dev_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+ sw_error_t rv;
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = hsl_ssdk_cfg(dev_id, ssdk_cfg);
+
+ return rv;
+}
+
+sw_error_t
+fal_cleanup(void)
+{
+ sw_error_t rv;
+
+ rv = hsl_dev_cleanup();
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef IN_VLAN
+ rv = fal_vlan_cleanup();
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @brief Reset fal layer.
+ * @details Comments:
+ * This operation will reset fal layer and hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_reset(dev_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get SSDK config infomation.
+ * @param[in] dev_id device id
+ * @param[out] ssdk_cfg SSDK config infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ssdk_cfg(dev_id, ssdk_cfg);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_interface_ctrl.c b/src/fal/fal_interface_ctrl.c
new file mode 100644
index 0000000..e9a10c1
--- /dev/null
+++ b/src/fal/fal_interface_ctrl.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_interface_ctrl FAL_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "fal_interface_ctrl.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_3az_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_3az_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_3az_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_3az_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_mac_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_mac_mode_set(dev_id, port_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_mac_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_mac_mode_get(dev_id, port_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_phy_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_phy_mode_set(dev_id, phy_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_phy_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_phy_mode_get(dev_id, phy_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_fx100_ctrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_fx100_ctrl_set(dev_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_fx100_ctrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_fx100_ctrl_get(dev_id, config);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_fx100_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_fx100_status_get(dev_id, status);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_mac06_exch_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_mac06_exch_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->interface_mac06_exch_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->interface_mac06_exch_get(dev_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_3az_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_3az_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_mac_mode_set(dev_id, port_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_mac_mode_get(dev_id, port_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_phy_mode_set(dev_id, phy_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_phy_mode_get(dev_id, phy_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[in] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_fx100_ctrl_set(dev_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_fx100_ctrl_get(dev_id, config);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] fx100 status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_fx100_status_get(dev_id, status);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_mac06_exch_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_interface_mac06_exch_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_ip.c b/src/fal/fal_ip.c
new file mode 100644
index 0000000..64e3806
--- /dev/null
+++ b/src/fal/fal_ip.c
@@ -0,0 +1,950 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_ip FAL_IP
+ * @{
+ */
+#include "sw.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_add(dev_id, host_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_del(dev_id, del_mode, host_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_get(dev_id, get_mode, host_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_next(dev_id, next_mode, host_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_counter_bind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_host_pppoe_bind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_pt_arp_learn_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_pt_arp_learn_set(dev_id, port_id, flags);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_pt_arp_learn_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_pt_arp_learn_get(dev_id, port_id, flags);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_arp_learn_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_arp_learn_set(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_arp_learn_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_arp_learn_get(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_source_guard_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_source_guard_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_source_guard_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_source_guard_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_unk_source_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_unk_source_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_unk_source_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_unk_source_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_arp_guard_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_arp_guard_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_arp_guard_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_arp_guard_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_unk_source_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_unk_source_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_unk_source_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_unk_source_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_route_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_route_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_route_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_route_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_intf_entry_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_intf_entry_add(dev_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_intf_entry_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_intf_entry_del(dev_id, del_mode, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_intf_entry_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_intf_entry_next(dev_id, next_mode, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_age_time_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_age_time_set(dev_id, time);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_age_time_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_age_time_get(dev_id, time);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_wcmp_hash_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_wcmp_hash_mode_set(dev_id, hash_mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ip_wcmp_hash_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ip_wcmp_hash_mode_get(dev_id, hash_mode);
+ return rv;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry added related interface entry and ip6 base address
+ must be set at first.
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_add(dev_id, host_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_del(dev_id, del_mode, host_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_get(dev_id, get_mode, host_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For next_mode please refer IP entry operation flags.
+ For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_next(dev_id, next_mode, host_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_pt_arp_learn_set(dev_id, port_id, flags);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_pt_arp_learn_get(dev_id, port_id, flags);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_arp_learn_set(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_arp_learn_get(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_source_guard_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_source_guard_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_unk_source_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_unk_source_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_arp_guard_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_arp_guard_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_unk_source_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_unk_source_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_route_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_route_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_intf_entry_add(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_intf_entry_del(dev_id, del_mode, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_intf_entry_next(dev_id, next_mode, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details Comments:
+ * This operation will set dynamic entry aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_age_time_set(dev_id, time);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_age_time_get(dev_id, time);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_leaky.c b/src/fal/fal_leaky.c
new file mode 100644
index 0000000..9b41dcd
--- /dev/null
+++ b/src/fal/fal_leaky.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_leaky FAL_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "fal_leaky.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->uc_leaky_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->uc_leaky_mode_set(dev_id, ctrl_mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->uc_leaky_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->uc_leaky_mode_get(dev_id, ctrl_mode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mc_leaky_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mc_leaky_mode_set(dev_id, ctrl_mode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mc_leaky_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mc_leaky_mode_get(dev_id, ctrl_mode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_leaky_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_leaky_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_leaky_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_leaky_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_uc_leaky_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_uc_leaky_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_uc_leaky_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_uc_leaky_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+
+static sw_error_t
+_fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mc_leaky_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mc_leaky_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mc_leaky_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mc_leaky_get(dev_id, port_id, enable);
+ return rv;
+}
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_uc_leaky_mode_set(dev_id, ctrl_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_uc_leaky_mode_get(dev_id, ctrl_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mc_leaky_mode_set(dev_id, ctrl_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mc_leaky_mode_get(dev_id, ctrl_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_leaky_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_leaky_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_uc_leaky_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_uc_leaky_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mc_leaky_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mc_leaky_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_led.c b/src/fal/fal_led.c
new file mode 100644
index 0000000..4819480
--- /dev/null
+++ b/src/fal/fal_led.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_led FAL_LED
+ * @{
+ */
+
+#include "sw.h"
+#include "fal_led.h"
+#include "hsl_api.h"
+
+
+
+static sw_error_t
+_fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->led_ctrl_pattern_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->led_ctrl_pattern_set(dev_id, group, id, pattern);
+ return rv;
+}
+
+
+
+static sw_error_t
+_fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->led_ctrl_pattern_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->led_ctrl_pattern_get(dev_id, group, id, pattern);
+ return rv;
+}
+
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+sw_error_t
+fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_mib.c b/src/fal/fal_mib.c
new file mode 100644
index 0000000..0d0117b
--- /dev/null
+++ b/src/fal/fal_mib.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_mib FAL_MIB
+ * @{
+ */
+
+#include "sw.h"
+#include "fal_mib.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_Info)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->get_mib_info)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->get_mib_info(dev_id, port_id, mib_Info);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mib_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mib_status_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mib_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mib_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mib_port_flush_counters)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mib_port_flush_counters(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mib_cpukeep_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mib_cpukeep_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mib_cpukeep_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mib_cpukeep_get(dev_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_Info)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_get_mib_info(dev_id, port_id, mib_Info);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mib_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mib_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Flush mib counters on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id )
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mib_port_flush_counters(dev_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mib_cpukeep_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mib_cpukeep_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_mirror.c b/src/fal/fal_mirror.c
new file mode 100644
index 0000000..7256632
--- /dev/null
+++ b/src/fal/fal_mirror.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_mirror FAL_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "fal_mirror.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_analysis_port_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_analysis_port_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_analysis_port_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_analysis_port_get(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_port_in_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_port_in_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_port_in_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_port_in_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_port_eg_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_port_eg_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->mirr_port_eg_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->mirr_port_eg_get(dev_id, port_id, enable);
+ return rv;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_analysis_port_set(dev_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_analysis_port_get(dev_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_port_in_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_port_in_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_port_eg_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_mirr_port_eg_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_misc.c b/src/fal/fal_misc.c
new file mode 100644
index 0000000..f64f90f
--- /dev/null
+++ b/src/fal/fal_misc.c
@@ -0,0 +1,1955 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+* @defgroup fal_gen FAL_MISC
+* @{
+*/
+#include "sw.h"
+#include "fal_misc.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_status_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_status_get(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->frame_max_size_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->frame_max_size_set(dev_id, size);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->frame_max_size_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->frame_max_size_get(dev_id, size);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_sa_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_sa_cmd_set(dev_id, port_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_sa_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_sa_cmd_get(dev_id, port_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_uc_filter_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_uc_filter_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_uc_filter_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_uc_filter_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_mc_filter_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_mc_filter_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_unk_mc_filter_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_unk_mc_filter_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_bc_filter_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_bc_filter_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_bc_filter_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_bc_filter_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cpu_port_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cpu_port_status_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cpu_port_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cpu_port_status_get(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->bc_to_cpu_port_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->bc_to_cpu_port_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->bc_to_cpu_port_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->bc_to_cpu_port_get(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_dhcp_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_dhcp_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_dhcp_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_dhcp_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->arp_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->arp_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eapol_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eapol_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eapol_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eapol_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_add(dev_id, session_id, strip_hdr);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_del(dev_id, session_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_get(dev_id, session_id, strip_hdr);
+ return rv;
+}
+
+static sw_error_t
+_fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eapol_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eapol_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eapol_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eapol_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ripv1_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ripv1_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->ripv1_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->ripv1_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_table_add(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_table_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_table_add(dev_id, session_tbl);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_pppoe_session_table_del(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_table_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_table_del(dev_id, session_tbl);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_table_get(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_table_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_table_get(dev_id, session_tbl);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_id_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_id_set(dev_id, index, id);
+ return rv;
+}
+
+static sw_error_t
+_fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->pppoe_session_id_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->pppoe_session_id_get(dev_id, index, id);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_req_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_req_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_req_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_req_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_ack_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_ack_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_arp_ack_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_arp_ack_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_mask_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_mask_set(dev_id, intr_mask);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_mask_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_mask_get(dev_id, intr_mask);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_status_get(dev_id, intr_status);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_status_clear)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_status_clear(dev_id, intr_status);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_mask_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_port_link_mask_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_port_link_mask_set(dev_id, port_id, intr_mask);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_mask_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_port_link_mask_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_port_link_mask_get(dev_id, port_id, intr_mask);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_port_link_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_port_link_status_get(dev_id, port_id, intr_mask);
+ return rv;
+}
+
+
+
+static sw_error_t
+_fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_mask_mac_linkchg_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_mask_mac_linkchg_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_status_mac_linkchg_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_status_mac_linkchg_get(dev_id, port_bitmap);
+ return rv;
+}
+
+static sw_error_t
+_fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cpu_vid_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cpu_vid_en_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cpu_vid_en_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cpu_vid_en_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rtd_pppoe_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rtd_pppoe_en_set(dev_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rtd_pppoe_en_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rtd_pppoe_en_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->intr_status_mac_linkchg_clear)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->intr_status_mac_linkchg_clear(dev_id);
+ return rv;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_frame_max_size_set(dev_id, size);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_frame_max_size_get(dev_id, size);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_sa_cmd_get(dev_id, port_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_uc_filter_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_uc_filter_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_mc_filter_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_unk_mc_filter_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_bc_filter_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_bc_filter_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cpu_port_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cpu_port_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_bc_to_cpu_port_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_bc_to_cpu_port_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_dhcp_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_dhcp_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling arp
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_arp_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eapol_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eapol_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[in] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_add(dev_id, session_id, strip_hdr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_del(dev_id, session_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[out] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_get(dev_id, session_id, strip_hdr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eapol_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eapol_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ripv1 packets hardware acknowledgement on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling eapol
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ripv1_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ripv1 packets hardware acknowledgement on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_ripv1_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_add(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_table_add(dev_id, session_tbl);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_del(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_table_del(dev_id, session_tbl);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_table_get(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_table_get(dev_id, session_tbl);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_id_set(dev_id, index, id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry to a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_pppoe_session_id_get(dev_id, index, id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_req_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_req_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_ack_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_arp_ack_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_mask_set(dev_id, intr_mask);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_mask_get(dev_id, intr_mask);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_status_get(dev_id, intr_status);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_status_clear(dev_id, intr_status);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_intr_port_link_mask_set(dev_id, port_id, intr_mask_flag);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_port_link_mask_get(dev_id, port_id, intr_mask_flag);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_port_link_status_get(dev_id, port_id, intr_mask_flag);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable ports intr mask enabled
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port interrupt mask or not
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] ports bitmap which generates interrupt
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_status_mac_linkchg_get(dev_id, port_bitmap);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set to cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cpu_vid_en_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get to cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cpu_vid_en_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rtd_pppoe_en_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rtd_pppoe_en_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_intr_status_mac_linkchg_clear(dev_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_nat.c b/src/fal/fal_nat.c
new file mode 100644
index 0000000..e0b7385
--- /dev/null
+++ b/src/fal/fal_nat.c
@@ -0,0 +1,986 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_nat FAL_NAT
+ * @{
+ */
+#include "sw.h"
+#include "fal_nat.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_add(dev_id, nat_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_del(dev_id, del_mode, nat_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_get(dev_id, get_mode, nat_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_next(dev_id, next_mode, nat_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_counter_bind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_add(dev_id, napt_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_del(dev_id, del_mode, napt_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_get(dev_id, get_mode, napt_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_next(dev_id, next_mode, napt_entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_counter_bind)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_hash_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_hash_mode_set(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_hash_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_hash_mode_get(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_status_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_status_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_mode_set(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->napt_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->napt_mode_get(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_base_addr_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_base_addr_set(dev_id, addr);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_base_addr_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_base_addr_get(dev_id, addr);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_base_mask_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_base_mask_set(dev_id, addr);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_base_mask_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_base_mask_get(dev_id, addr);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_addr_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_addr_mode_set(dev_id, map_en);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_prv_addr_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_prv_addr_mode_get(dev_id, map_en);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_pub_addr_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_pub_addr_add(dev_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_pub_addr_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_pub_addr_del(dev_id, del_mode, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_pub_addr_next)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_pub_addr_next(dev_id, next_mode, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_unk_session_cmd_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_unk_session_cmd_set(dev_id, cmd);
+ return rv;
+}
+
+static sw_error_t
+_fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nat_unk_session_cmd_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nat_unk_session_cmd_get(dev_id, cmd);
+ return rv;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ * @details Comments:
+ Before NAT entry added ip4 private base address must be set
+ at first.
+ In parameter nat_entry entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_add(dev_id, nat_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_del(dev_id, del_mode, nat_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_get(dev_id, get_mode, nat_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_next(dev_id, next_mode, nat_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ * @details Comments:
+ Before NAPT entry added related ip4 private base address must be set
+ at first.
+ In parameter napt_entry related entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_add(dev_id, napt_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_del(dev_id, del_mode, napt_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_get(dev_id, get_mode, napt_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_next(dev_id, next_mode, napt_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_hash_mode_set(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_hash_mode_get(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_status_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_status_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_mode_set(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_napt_mode_get(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @details Comments:
+ Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_base_addr_set(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_base_addr_get(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_base_mask_set(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_base_mask_get(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ * @details Comments:
+ If map_en equal true means bits31-20 bits15-8 are base address
+ else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_addr_mode_set(dev_id, map_en);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_prv_addr_mode_get(dev_id, map_en);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ * @details Comments:
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_pub_addr_add(dev_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_pub_addr_del(dev_id, del_mode, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_pub_addr_next(dev_id, next_mode, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_unk_session_cmd_set(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nat_unk_session_cmd_get(dev_id, cmd);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_port_ctrl.c b/src/fal/fal_port_ctrl.c
new file mode 100644
index 0000000..1c72305
--- /dev/null
+++ b/src/fal/fal_port_ctrl.c
@@ -0,0 +1,1425 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_port_ctrl FAL_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_duplex_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_duplex_set(dev_id, port_id, duplex);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_duplex_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_duplex_get(dev_id, port_id, pduplex);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_speed_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_speed_set(dev_id, port_id, speed);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_speed_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_speed_get(dev_id, port_id, pspeed);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_autoneg_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_autoneg_status_get(dev_id, port_id, status);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_autoneg_enable)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_autoneg_enable(dev_id, port_id);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_autoneg_restart)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_autoneg_restart(dev_id, port_id);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_autoneg_adv_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_autoneg_adv_set(dev_id, port_id, autoadv);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_autoneg_adv_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_autoneg_adv_get(dev_id, port_id, autoadv);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_hdr_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_hdr_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_hdr_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_hdr_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_flowctrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_flowctrl_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_flowctrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_flowctrl_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_flowctrl_forcemode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_flowctrl_forcemode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_powersave_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_powersave_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_powersave_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_powersave_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_hibernate_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_hibernate_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_hibernate_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_hibernate_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ a_uint32_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_cdt)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxhdr_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxhdr_mode_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxhdr_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxhdr_mode_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txhdr_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txhdr_mode_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txhdr_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txhdr_mode_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->header_type_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->header_type_set(dev_id, enable, type);
+ return rv;
+}
+
+static sw_error_t
+_fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->header_type_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->header_type_get(dev_id, enable, type);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txmac_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txmac_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txmac_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txmac_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxmac_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxmac_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxmac_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxmac_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txfc_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txfc_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_txfc_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_txfc_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxfc_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxfc_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_rxfc_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_rxfc_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_bp_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_bp_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_bp_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_bp_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_link_forcemode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_link_forcemode_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_link_forcemode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_link_forcemode_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_link_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_link_status_get(dev_id, port_id, status);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mac_loopback_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mac_loopback_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mac_loopback_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mac_loopback_get(dev_id, port_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_duplex_set(dev_id, port_id, duplex);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_duplex_get(dev_id, port_id, pduplex);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_speed_set(dev_id, port_id, speed);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_speed_get(dev_id, port_id, pspeed);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_autoneg_status_get(dev_id, port_id, status);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_autoneg_enable(dev_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_autoneg_restart(dev_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_hdr_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_hdr_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_flowctrl_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_flowctrl_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_powersave_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_powersave_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_hibernate_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_hibernate_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief cable diagnostic test.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ a_uint32_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_rxhdr_mode_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_rxhdr_mode_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_txhdr_mode_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_txhdr_mode_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_header_type_set(dev_id, enable, type);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_header_type_get(dev_id, enable, type);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_port_txmac_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_txmac_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_port_rxmac_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_rxmac_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _fal_port_txfc_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_txfc_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_rxfc_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_rxfc_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_bp_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_bp_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_link_forcemode_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_link_forcemode_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_link_status_get(dev_id, port_id, status);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @brief Set loopback on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mac_loopback_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mac_loopback_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+/**
+ * @}
+ */
+
diff --git a/src/fal/fal_portvlan.c b/src/fal/fal_portvlan.c
new file mode 100644
index 0000000..f7f5003
--- /dev/null
+++ b/src/fal/fal_portvlan.c
@@ -0,0 +1,1535 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_port_vlan FAL_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "fal_portvlan.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_1qmode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_1qmode_set(dev_id, port_id, port_1qmode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_1qmode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_1qmode_get(dev_id, port_id, pport_1qmode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_egvlanmode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_egvlanmode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ return rv;
+}
+
+static sw_error_t
+_fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->portvlan_member_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->portvlan_member_add(dev_id, port_id, mem_port_id);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->portvlan_member_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->portvlan_member_del(dev_id, port_id, mem_port_id);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->portvlan_member_update)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->portvlan_member_update(dev_id, port_id, mem_port_map);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->portvlan_member_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->portvlan_member_get(dev_id, port_id, mem_port_map);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_vid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_vid_set(dev_id, port_id, vid);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_vid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_vid_get(dev_id, port_id, vid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_force_default_vid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_force_default_vid_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_force_default_vid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_force_default_vid_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_force_portvlan_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_force_portvlan_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_force_portvlan_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_force_portvlan_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_nestvlan_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_nestvlan_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_nestvlan_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_nestvlan_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nestvlan_tpid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nestvlan_tpid_set(dev_id, tpid);
+ return rv;
+}
+
+static sw_error_t
+_fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->nestvlan_tpid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->nestvlan_tpid_get(dev_id, tpid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_invlan_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_invlan_mode_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_invlan_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_invlan_mode_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_tls_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_tls_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_tls_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_tls_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_pri_propagation_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_pri_propagation_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_pri_propagation_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_pri_propagation_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_svid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_svid_set(dev_id, port_id, vid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_svid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_svid_get(dev_id, port_id, vid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_cvid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_cvid_set(dev_id, port_id, vid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_default_cvid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_default_cvid_get(dev_id, port_id, vid);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_propagation_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_propagation_set(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_propagation_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_propagation_get(dev_id, port_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_trans_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_trans_add(dev_id, port_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_trans_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_trans_del(dev_id, port_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_trans_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_trans_get(dev_id, port_id, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qinq_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qinq_mode_set(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qinq_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qinq_mode_get(dev_id, mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_qinq_role_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_qinq_role_set(dev_id, port_id, role);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_qinq_role_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_qinq_role_get(dev_id, port_id, role);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_vlan_trans_iterate)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mac_vlan_xlt_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mac_vlan_xlt_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->port_mac_vlan_xlt_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->port_mac_vlan_xlt_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->netisolate_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->netisolate_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->netisolate_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->netisolate_get(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eg_trans_filter_bypass_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eg_trans_filter_bypass_en_set(dev_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->eg_trans_filter_bypass_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->eg_trans_filter_bypass_en_get(dev_id, enable);
+ return rv;
+}
+
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_1qmode_set(dev_id, port_id, port_1qmode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_portvlan_member_add(dev_id, port_id, mem_port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_portvlan_member_del(dev_id, port_id, mem_port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_portvlan_member_update(dev_id, port_id, mem_port_map);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_portvlan_member_get(dev_id, port_id, mem_port_map);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_vid_set(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_vid_get(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_force_default_vid_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_force_default_vid_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_force_portvlan_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_force_portvlan_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_nestvlan_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_nestvlan_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nestvlan_tpid_set(dev_id, tpid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_nestvlan_tpid_get(dev_id, tpid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_invlan_mode_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_invlan_mode_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_tls_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_tls_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_pri_propagation_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_pri_propagation_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_svid_set(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_svid_get(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_cvid_set(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_default_cvid_get(dev_id, port_id, vid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_propagation_set(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_propagation_get(dev_id, port_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_trans_add(dev_id, port_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_trans_del(dev_id, port_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_trans_get(dev_id, port_id, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qinq_mode_set(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qinq_mode_get(dev_id, mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_qinq_role_set(dev_id, port_id, role);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_qinq_role_get(dev_id, port_id, role);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set net isolate function.
+ * @param[in] dev_id device id
+ * @param[in] enable tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_netisolate_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get net isolate status.
+ * @param[in] dev_id device id
+ * @param[out] enable tag protocol identification
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_netisolate_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eg_trans_filter_bypass_en_set(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_eg_trans_filter_bypass_en_get(dev_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_qos.c b/src/fal/fal_qos.c
new file mode 100644
index 0000000..2df329f
--- /dev/null
+++ b/src/fal/fal_qos.c
@@ -0,0 +1,1337 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_qos FAL_QOS
+ * @{
+ */
+#include "sw.h"
+#include "fal_qos.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_sch_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_sch_mode_set(dev_id, mode, weight);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_sch_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_sch_mode_get(dev_id, mode, weight);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_tx_buf_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_tx_buf_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_tx_buf_nr_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_tx_buf_nr_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_tx_buf_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_tx_buf_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_red_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_red_en_set(dev_id, port_id, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_red_en_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_red_en_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_tx_buf_nr_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_tx_buf_nr_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_rx_buf_nr_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_rx_buf_nr_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_queue_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_queue_set(dev_id, up, queue);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_up_queue_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_up_queue_get(dev_id, up, queue);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_queue_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_queue_set(dev_id, dscp, queue);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->cosmap_dscp_queue_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->cosmap_dscp_queue_get(dev_id, dscp, queue);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_mode_set(dev_id, port_id, mode, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_mode_get(dev_id, port_id, mode, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_mode_pri_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_mode_pri_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_up_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_up_set(dev_id, port_id, up);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_up_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_up_get(dev_id, port_id, up);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_sch_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_sch_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_spri_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_spri_set(dev_id, port_id, spri);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_spri_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_spri_get(dev_id, port_id, spri);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_cpri_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_cpri_set(dev_id, port_id, cpri);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_default_cpri_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_default_cpri_get(dev_id, port_id, cpri);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_force_spri_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_force_spri_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_force_spri_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_force_spri_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_force_cpri_status_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_force_cpri_status_set(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_port_force_cpri_status_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_port_force_cpri_status_get(dev_id, port_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_remark_table_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+ return rv;
+}
+
+static sw_error_t
+_fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->qos_queue_remark_table_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one device.
+ * @details Comments:
+ * Particular device may only support parts of input options. Such as
+ * GARUDA doesn't support variable weight in wrr mode.
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_sch_mode_set(dev_id, mode, weight);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_sch_mode_get(dev_id, mode, weight);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ * Because different device has differnet hardware granularity
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ * If enable tx buffer on one port that means this port will have fixed
+ * number buffers when transmitting packets. Otherwise they will
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_red_en_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_red_en_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ * Because different device has differnet hardware granularity
+ * function will return actual buffer number in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max reserved buffer number of receiving port on one particular port.
+ * @details Comments:
+ * Because different device has differnet hardware granularity
+ * function will return actual buffer number in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max reserved buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user priority to queue mapping.
+ * @param[in] dev_id device id
+ * @param[in] up 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_queue_set(dev_id, up, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user priority to queue mapping.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_up_queue_get(dev_id, up, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_queue_set(dev_id, dscp, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_cosmap_dscp_queue_get(dev_id, dscp, queue);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_mode_set(dev_id, port_id, mode, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_mode_get(dev_id, port_id, mode, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ * If the priority of a mode is more small then the priority is more high.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_up_set(dev_id, port_id, up);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_up_get(dev_id, port_id, up);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ * @details Comments:
+ * Particular device may only support parts of input options. Such as
+ * GARUDA doesn't support variable weight in wrr mode.
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_spri_set(dev_id, port_id, spri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_spri_get(dev_id, port_id, spri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_cpri_set(dev_id, port_id, cpri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_default_cpri_get(dev_id, port_id, cpri);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force stag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_force_spri_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Get force stag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_force_spri_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force ctag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_force_spri_status_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force ctag priority flag on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_port_force_cpri_status_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+
+sw_error_t
+fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_rate.c b/src/fal/fal_rate.c
new file mode 100644
index 0000000..f40c7a4
--- /dev/null
+++ b/src/fal/fal_rate.c
@@ -0,0 +1,831 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_rate FAL_RATE
+ * @{
+ */
+#include "sw.h"
+#include "fal_rate.h"
+#include "hsl_api.h"
+
+
+static sw_error_t
+_fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_queue_egrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_queue_egrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_egrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_egrl_set(dev_id, port_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_egrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_egrl_get(dev_id, port_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_inrl_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_inrl_set(dev_id, port_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_inrl_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_inrl_get(dev_id, port_id, speed, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->storm_ctrl_frame_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->storm_ctrl_frame_set(dev_id, port_id, frame_type, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->storm_ctrl_frame_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->storm_ctrl_frame_get(dev_id, port_id, frame_type, enable);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->storm_ctrl_rate_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->storm_ctrl_rate_set(dev_id, port_id, rate);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->storm_ctrl_rate_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->storm_ctrl_rate_get(dev_id, port_id, rate);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_policer_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_policer_set(dev_id, port_id, policer);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_policer_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_policer_get(dev_id, port_id, policer);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_shaper_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_shaper_set(dev_id, port_id, enable, shaper);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_shaper_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_shaper_get(dev_id, port_id, enable, shaper);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_queue_shaper_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_queue_shaper_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_acl_policer_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_acl_policer_set(dev_id, policer_id, policer);
+ return rv;
+}
+
+static sw_error_t
+_fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_acl_policer_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_acl_policer_get(dev_id, policer_id, policer);
+ return rv;
+}
+
+sw_error_t
+_fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_add_rate_byte_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_add_rate_byte_set(dev_id, port_id, number);
+ return rv;
+}
+
+sw_error_t
+_fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_add_rate_byte_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_add_rate_byte_get(dev_id, port_id, number);
+ return rv;
+}
+
+sw_error_t
+_fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_gol_flow_en_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_gol_flow_en_set(dev_id, port_id, enable);
+ return rv;
+}
+
+sw_error_t
+_fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->rate_port_gol_flow_en_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->rate_port_gol_flow_en_get(dev_id, port_id, enable);
+ return rv;
+}
+
+
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ * @details Comments:
+ * The granularity of speed is bps.
+ * Because different device has differnet hardware granularity function
+ * will return actual speed in hardware.
+ * When disable queue egress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ * @details Comments:
+ * The granularity of speed is bps.
+ * Because different device has differnet hardware granularity function
+ * will return actual speed in hardware.
+ * When disable port egress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_egrl_set(dev_id, port_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_egrl_get(dev_id, port_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ * @details Comments:
+ * The granularity of speed is bps.
+ * Because different device has differnet hardware granularity function
+ * will return actual speed in hardware.
+ * When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_inrl_set(dev_id, port_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_inrl_get(dev_id, port_id, speed, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ * @details Comments:
+ * When enable one particular packets type storm control this type packets
+ * speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_storm_ctrl_frame_set(dev_id, port_id, frame_type, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_storm_ctrl_frame_get(dev_id, port_id, frame_type, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ * @details Comments:
+ * The granularity of speed is packets per second.
+ * Because different device has differnet hardware granularity function
+ * will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_storm_ctrl_rate_set(dev_id, port_id, rate);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_storm_ctrl_rate_get(dev_id, port_id, rate);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_policer_set(dev_id, port_id, policer);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_policer_get(dev_id, port_id, policer);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_acl_policer_set(dev_id, policer_id, policer);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_acl_policer_get(dev_id, policer_id, policer);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+sw_error_t
+fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ _fal_rate_port_add_rate_byte_set(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ _fal_rate_port_add_rate_byte_get(dev_id, port_id, number);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port global flow control when global threshold is reached.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_gol_flow_en_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get status of port global flow control when global threshold is reached.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_rate_port_gol_flow_en_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_reg_access.c b/src/fal/fal_reg_access.c
new file mode 100644
index 0000000..e80373c
--- /dev/null
+++ b/src/fal/fal_reg_access.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_reg_access FAL_REG_ACCESS
+ * @{
+ */
+#include "sw.h"
+#include "fal_reg_access.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->phy_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->phy_get(dev_id, phy_addr, reg, value);
+ return rv;
+}
+
+static sw_error_t
+_fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->phy_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->phy_set(dev_id, phy_addr, reg, value);
+ return rv;
+}
+
+static sw_error_t
+_fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->reg_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->reg_get(dev_id, reg_addr, value, value_len);
+ return rv;
+}
+
+static sw_error_t
+_fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->reg_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->reg_set(dev_id, reg_addr, value, value_len);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->reg_field_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ return rv;
+}
+
+static sw_error_t
+_fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->reg_field_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ return rv;
+}
+
+
+/**
+ * fal_phy_get - get value of specific phy device
+ * @phy_addr: id of the phy device
+ * @reg: register id of phy device
+ * @value: pointer to the memory storing the value.
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_phy_get(dev_id, phy_addr, reg, value);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * fal_phy_set - set value of specific phy device
+ * @phy_addr: id of the phy device
+ * @reg: register id of phy device
+ * @value: register value.
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_phy_set(dev_id, phy_addr, reg, value);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * fal_reg_get - get value of specific register
+ * @reg_addr: address of the register
+ * @value: pointer to the memory storing the value.
+ * @value_len: length of the value.
+ *
+ * Get the value of a specific register field with related parameter
+ */
+sw_error_t
+fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_reg_get(dev_id, reg_addr, value, value_len);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * fal_reg_set - set value of specific register
+ * @reg_addr: address of the register
+ * @value: pointer to the memory storing the value.
+ * @value_len: length of the value.
+ *
+ * Get the value of a specific register field with related parameter
+ */
+sw_error_t
+fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_reg_set(dev_id, reg_addr, value, value_len);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * fal_reg_field_get - get value of specific register field
+ * @reg_addr: address of the register
+ * @bit_offset: position of the field in bit
+ * @field_len: length of the field in bit
+ * @value: pointer to the memory storing the value.
+ * @value_len: length of the value.
+ *
+ * Get the value of a specific register field with related parameter
+ */
+sw_error_t
+fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_reg_field_get(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * fal_reg_field_set - set value of specific register field
+ * @reg_addr: address of the register
+ * @bit_offset: position of the field in bit
+ * @field_len: length of the field in bit
+ * @value: pointer to the memory storing the value.
+ * @value_len: length of the value.
+ *
+ * Set the value of a specific register field with related parameter
+ */
+sw_error_t
+fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_reg_field_set(dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_sec.c b/src/fal/fal_sec.c
new file mode 100644
index 0000000..71dd8d8
--- /dev/null
+++ b/src/fal/fal_sec.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_sec FAL_SEC
+ * @{
+ */
+#include "sw.h"
+#include "fal_sec.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->sec_norm_item_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->sec_norm_item_set(dev_id, item, value);
+ return rv;
+}
+
+static sw_error_t
+_fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->sec_norm_item_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->sec_norm_item_get(dev_id, item, value);
+ return rv;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_sec_norm_item_set(dev_id, item, value);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_sec_norm_item_get(dev_id, item, value);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_stp.c b/src/fal/fal_stp.c
new file mode 100644
index 0000000..d17d3b4
--- /dev/null
+++ b/src/fal/fal_stp.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_stp FAL_STP
+ * @{
+ */
+#include "sw.h"
+#include "fal_stp.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->stp_port_state_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->stp_port_state_set(dev_id, st_id, port_id, state);
+ return rv;
+}
+
+static sw_error_t
+_fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->stp_port_state_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->stp_port_state_get(dev_id, st_id, port_id, state);
+ return rv;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ * For those devices which only support single spanning tree st_id should
+ * be FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_stp_port_state_set(dev_id, st_id, port_id, state);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ * For those devices which only support single spanning tree st_id should
+ * be FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_stp_port_state_get(dev_id, st_id, port_id, state);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_trunk.c b/src/fal/fal_trunk.c
new file mode 100644
index 0000000..5bebaa3
--- /dev/null
+++ b/src/fal/fal_trunk.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup fal_trunk FAL_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "fal_trunk.h"
+#include "hsl_api.h"
+
+static sw_error_t
+_fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_group_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_group_set(dev_id, trunk_id, enable, member);
+ return rv;
+}
+
+static sw_error_t
+_fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_group_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_group_get(dev_id, trunk_id, enable, member);
+ return rv;
+}
+
+static sw_error_t
+_fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_hash_mode_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_hash_mode_set(dev_id, hash_mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_hash_mode_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_hash_mode_get(dev_id, hash_mode);
+ return rv;
+}
+
+static sw_error_t
+_fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_manipulate_sa_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_manipulate_sa_set(dev_id, addr);
+ return rv;
+}
+
+static sw_error_t
+_fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->trunk_manipulate_sa_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->trunk_manipulate_sa_get(dev_id, addr);
+ return rv;
+}
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_group_set(dev_id, trunk_id, enable, member);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_group_get(dev_id, trunk_id, enable, member);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_hash_mode_set(dev_id, hash_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_hash_mode_get(dev_id, hash_mode);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr manipulate SA
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_manipulate_sa_set(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[out] addr manipulate SA
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_trunk_manipulate_sa_get(dev_id, addr);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @}
+ */
diff --git a/src/fal/fal_vlan.c b/src/fal/fal_vlan.c
new file mode 100644
index 0000000..f9badd9
--- /dev/null
+++ b/src/fal/fal_vlan.c
@@ -0,0 +1,918 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup fal_vlan FAL_VLAN
+ * @{
+ */
+
+#include "sw.h"
+#include "util.h"
+#include "fal_vlan.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_api.h"
+
+typedef struct
+{
+ a_uint32_t idx;
+ fal_vlan_t entry;
+} v_array_t;
+
+static v_array_t * vlan_db[SW_MAX_NR_DEV] = { 0 };
+static sid_pool_t * vlan_pool[SW_MAX_NR_DEV] = { 0 };
+static sll_head_t * vlan_list[SW_MAX_NR_DEV] = { 0 };
+
+
+static sw_error_t
+_fal_vlan_search(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+ a_uint32_t iterator;
+ v_array_t v_tbl;
+ v_array_t * p_tbl;
+ hsl_dev_t * p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ v_tbl.entry = * vlan_entry;
+ p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+
+ if (NULL == p_tbl)
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ * vlan_entry = p_tbl->entry;
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_fal_vlan_following(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+ a_uint32_t iterator = 0;
+ v_array_t v_tbl;
+ v_array_t * p_tbl;
+ hsl_dev_t * p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ sll_lock(vlan_list[dev_id]);
+
+ v_tbl.entry = *vlan_entry;
+
+ if (0 == v_tbl.entry.vid)
+ {
+ p_tbl = sll_nd_next(vlan_list[dev_id], &iterator);
+ }
+ else
+ {
+ p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+ if (NULL == p_tbl)
+ {
+ sll_unlock(vlan_list[dev_id]);
+ return SW_NO_MORE;
+ }
+
+ p_tbl = sll_nd_next(vlan_list[dev_id], &iterator);
+ }
+
+ if (NULL == p_tbl)
+ {
+ sll_unlock(vlan_list[dev_id]);
+ return SW_NO_MORE;
+ }
+
+ * vlan_entry = p_tbl->entry;
+ sll_unlock(vlan_list[dev_id]);
+ return SW_OK;
+}
+
+static sw_error_t
+_fal_vlan_del(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+ v_array_t * p_tbl;
+ v_array_t ent;
+ sw_error_t rv;
+ a_uint32_t iterator;
+ a_uint32_t id;
+ hsl_dev_t * p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ ent.entry.vid = vlan_id;
+ p_tbl = sll_nd_find(vlan_list[dev_id], &ent, &iterator);
+ if (NULL == p_tbl)
+ {
+ return SW_NOT_FOUND;
+ }
+ id = p_tbl->idx;
+
+ rv = sll_nd_delete(vlan_list[dev_id], p_tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = sid_pool_id_free(vlan_pool[dev_id], id);
+ return rv;
+}
+
+static sw_error_t
+_fal_vlan_creat(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ v_array_t * v_tbl;
+ sw_error_t rv;
+ a_uint32_t id;
+ hsl_dev_t * p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ rv = sid_pool_id_alloc(vlan_pool[dev_id], &id);
+ SW_RTN_ON_ERROR(rv);
+
+ v_tbl = &vlan_db[dev_id][id];
+ v_tbl->idx = id;
+ v_tbl->entry = *vlan_entry;
+ rv = sll_nd_insert(vlan_list[dev_id], v_tbl);
+ return rv;
+}
+
+static sw_error_t
+_fal_vlan_update(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ a_uint32_t iterator;
+ v_array_t v_tbl;
+ v_array_t * p_tbl;
+ hsl_dev_t * p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ sll_lock(vlan_list[dev_id]);
+ v_tbl.entry = *vlan_entry;
+ p_tbl = sll_nd_find(vlan_list[dev_id], &v_tbl, &iterator);
+
+ if (NULL == p_tbl)
+ {
+ sll_unlock(vlan_list[dev_id]);
+ return SW_NOT_FOUND;
+ }
+
+ p_tbl->entry = * vlan_entry;
+ sll_unlock(vlan_list[dev_id]);
+ return SW_OK;
+}
+
+static ll_cmp_rslt_t
+_fal_vlan_entry_cmp(void * src, void * dest)
+{
+ v_array_t * src_nd, * dest_nd;
+
+ src_nd = (v_array_t*)src;
+ dest_nd = (v_array_t*)dest;
+
+ if (src_nd->entry.vid == dest_nd->entry.vid)
+ {
+ return LL_CMP_EQUAL;
+ }
+ else if (src_nd->entry.vid > dest_nd->entry.vid)
+ {
+ return LL_CMP_GREATER;
+ }
+ else
+ {
+ return LL_CMP_SMALLER;
+ }
+}
+
+static void
+_fal_vlan_entry_dump(void * data)
+{
+ v_array_t * nd;
+
+ nd = (v_array_t*)data;
+ aos_printk("vid = %d member = 0x%x\n", nd->entry.vid, nd->entry.mem_ports);
+}
+
+
+static sw_error_t
+_fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ rv = _fal_vlan_search(dev_id, vlan_entry);
+ if (SW_OK == rv)
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ if (NULL == p_api->vlan_entry_append)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_entry_append(dev_id, vlan_entry);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _fal_vlan_creat(dev_id, vlan_entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ fal_vlan_t entry;
+ hsl_api_t *p_api;
+
+ aos_mem_zero(&(entry), sizeof(fal_vlan_t));
+ entry.vid = vlan_id;
+ rv = _fal_vlan_search(dev_id, &entry);
+ if (SW_OK == rv)
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ if (NULL == p_api->vlan_creat)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_creat(dev_id, vlan_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _fal_vlan_creat(dev_id, &entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_next)
+ {
+ p_vlan->vid = vlan_id;
+ rv = _fal_vlan_following(dev_id, p_vlan);
+ }
+ else
+ {
+ rv = p_api->vlan_next(dev_id, vlan_id, p_vlan);
+ }
+ return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_find)
+ {
+ p_vlan->vid = vlan_id;
+ rv = _fal_vlan_search(dev_id, p_vlan);
+ }
+ else
+ {
+ rv = p_api->vlan_find(dev_id, vlan_id, p_vlan);
+ }
+ return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+ fal_vlan_t vlan_entry;
+ hsl_api_t *p_api;
+ hsl_dev_t *p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_FALSE == p_dev->hw_vlan_query)
+ {
+ vlan_entry.vid = vlan_id;
+ rv = _fal_vlan_search(dev_id, &vlan_entry);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ vlan_entry.mem_ports = member;
+ vlan_entry.u_ports = u_member;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ if (NULL == p_api->vlan_member_update)
+ {
+ if ((NULL == p_api->vlan_entry_append)
+ || (NULL == p_api->vlan_delete))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ p_api->vlan_delete(dev_id, vlan_id);
+
+ rv = p_api->vlan_entry_append(dev_id, &vlan_entry);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+
+ rv = p_api->vlan_member_update(dev_id, vlan_id, member, u_member);
+ SW_RTN_ON_ERROR(rv);
+ }
+ rv = _fal_vlan_update(dev_id, &vlan_entry);
+ return rv;
+}
+
+
+static sw_error_t
+_fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_delete)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_delete(dev_id, vlan_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _fal_vlan_del(dev_id, vlan_id);
+ return rv;
+}
+
+static sw_error_t
+_fal_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_flush)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_flush(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = fal_vlan_reset(dev_id);
+ return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_fid_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_fid_set(dev_id, vlan_id, fid);
+ return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_fid_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_fid_get(dev_id, vlan_id, fid);
+ return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_member_add)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_member_add(dev_id, vlan_id, port_id, port_info);
+ return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_member_del)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_member_del(dev_id, vlan_id, port_id);
+ return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_learning_state_set)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_learning_state_set(dev_id, vlan_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+static sw_error_t
+_fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ if (NULL == p_api->vlan_learning_state_get)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->vlan_learning_state_get(dev_id, vlan_id, enable);
+ return rv;
+}
+
+/**
+ * @brief Reset fal vlan module on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_reset(a_uint32_t dev_id)
+{
+ a_uint32_t entry_nr;
+ hsl_dev_t *p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ entry_nr = p_dev->nr_vlans;
+ if ((0 == entry_nr) || (4096 < entry_nr))
+ {
+ return SW_FAIL;
+ }
+
+ if (NULL != vlan_pool[dev_id])
+ {
+ sid_pool_destroy(vlan_pool[dev_id]);
+ vlan_pool[dev_id] = NULL;
+ }
+
+ if (NULL != vlan_list[dev_id])
+ {
+ sll_destroy(vlan_list[dev_id]);
+ vlan_list[dev_id] = NULL;
+ }
+
+ aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t)));
+
+ vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0);
+ if (NULL == vlan_pool[dev_id])
+ {
+ return SW_FAIL;
+ }
+
+ vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump,
+ LL_FIX_NDNR | LL_IN_ORDER, entry_nr);
+ if (NULL == vlan_list[dev_id])
+ {
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+
+/**
+ * @brief Init fal vlan module on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_init(a_uint32_t dev_id)
+{
+ a_uint32_t entry_nr;
+ hsl_dev_t *p_dev = NULL;
+
+ p_dev = hsl_dev_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_dev);
+
+ if (A_TRUE == p_dev->hw_vlan_query)
+ {
+ return SW_OK;
+ }
+
+ entry_nr = p_dev->nr_vlans;
+ if ((0 == entry_nr) || (4096 < entry_nr))
+ {
+ return SW_FAIL;
+ }
+
+ vlan_pool[dev_id] = sid_pool_creat(entry_nr, 0);
+ if (NULL == vlan_pool[dev_id])
+ {
+ return SW_FAIL;
+ }
+
+ /* allocate memory for vlan entry */
+ vlan_db[dev_id] = aos_mem_alloc(entry_nr * (sizeof (v_array_t)));
+ if (NULL == vlan_db[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+ aos_mem_zero(vlan_db[dev_id], entry_nr * (sizeof (v_array_t)));
+
+ vlan_list[dev_id] = sll_creat(_fal_vlan_entry_cmp, _fal_vlan_entry_dump,
+ LL_FIX_NDNR | LL_IN_ORDER, entry_nr);
+
+ if (NULL == vlan_list[dev_id])
+ {
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+fal_vlan_cleanup(void)
+{
+ a_uint32_t dev_id;
+
+ for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++)
+ {
+ if (vlan_db[dev_id])
+ {
+ aos_mem_free(vlan_db[dev_id]);
+ vlan_db[dev_id] = NULL;
+ }
+
+ if (vlan_pool[dev_id])
+ {
+ sid_pool_destroy(vlan_pool[dev_id]);
+ vlan_pool[dev_id] = NULL;
+ }
+
+ if (vlan_list[dev_id])
+ {
+ sll_destroy(vlan_list[dev_id]);
+ vlan_list[dev_id] = NULL;
+ }
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_entry_append(dev_id, vlan_entry);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_create(dev_id, vlan_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_next(dev_id, vlan_id, p_vlan);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_find(dev_id, vlan_id, p_vlan);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_member_update(dev_id, vlan_id, member, u_member);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_delete(dev_id, vlan_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_flush(dev_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_fid_set(dev_id, vlan_id, fid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_fid_get(dev_id, vlan_id, fid);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_member_del(dev_id, vlan_id, port_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_learning_state_set(dev_id, vlan_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+sw_error_t
+fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _fal_vlan_learning_state_get(dev_id, vlan_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @}
+ */
diff --git a/src/fal_uk/Makefile b/src/fal_uk/Makefile
new file mode 100644
index 0000000..66d4270
--- /dev/null
+++ b/src/fal_uk/Makefile
@@ -0,0 +1,92 @@
+LOC_DIR=src/fal_uk
+LIB=UK_IF
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=fal_init.c fal_uk_if.c fal_reg_access.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += fal_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += fal_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += fal_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += fal_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += fal_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += fal_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += fal_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += fal_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += fal_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += fal_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += fal_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += fal_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += fal_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += fal_vlan.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+ SRC_LIST += fal_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+ SRC_LIST += fal_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+ SRC_LIST += fal_nat.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+ SRC_LIST += fal_sec.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+ SRC_LIST += fal_trunk.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+ SRC_LIST += fal_interface_ctrl.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/fal_uk/fal_acl.c b/src/fal_uk/fal_acl.c
new file mode 100644
index 0000000..d80dbb6
--- /dev/null
+++ b/src/fal_uk/fal_acl.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw_ioctl.h"
+#include "fal_acl.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t prio)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_LIST_CREAT, dev_id, list_id, prio);
+ return rv;
+}
+
+sw_error_t
+fal_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_LIST_DESTROY, dev_id, list_id);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_ADD, dev_id, list_id, rule_id,
+ rule_nr, (a_uint32_t) rule);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_DELETE, dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_QUERY, dev_id, list_id, rule_id, (a_uint32_t) rule);
+ return rv;
+}
+
+sw_error_t
+fal_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_LIST_BIND, dev_id, list_id, direc, obj_t, obj_idx);
+ return rv;
+}
+
+sw_error_t
+fal_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_LIST_UNBIND, dev_id, list_id, direc, obj_t, obj_idx);
+ return rv;
+}
+
+sw_error_t
+fal_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_acl_list_dump(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_LIST_DUMP, dev_id);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_dump(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_DUMP, dev_id);
+ return rv;
+}
+
+sw_error_t
+fal_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t offset, a_uint32_t length)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_PT_UDF_PROFILE_SET, dev_id, port_id, udf_type, offset, length);
+ return rv;
+}
+
+sw_error_t
+fal_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id, fal_acl_udf_type_t udf_type, a_uint32_t * offset, a_uint32_t * length)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_PT_UDF_PROFILE_GET, dev_id, port_id, udf_type, (a_uint32_t)offset, (a_uint32_t)length);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_ACTIVE, dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_DEACTIVE, dev_id, list_id, rule_id, rule_nr);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_SRC_FILTER_STS_SET, dev_id, rule_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ACL_RULE_SRC_FILTER_STS_GET, dev_id, rule_id, enable);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_cosmap.c b/src/fal_uk/fal_cosmap.c
new file mode 100644
index 0000000..eb024f2
--- /dev/null
+++ b/src/fal_uk/fal_cosmap.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_cosmap.h"
+#include "fal_uk_if.h"
+
+
+sw_error_t
+fal_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ rv= sw_uk_exec(SW_API_COSMAP_DSCP_TO_PRI_SET, dev_id, dscp, pri);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_DSCP_TO_PRI_GET, dev_id, dscp, (a_uint32_t)pri);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ rv= sw_uk_exec(SW_API_COSMAP_DSCP_TO_DP_SET, dev_id, dscp, dp);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_DSCP_TO_DP_GET, dev_id, dscp, (a_uint32_t)dp);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_TO_PRI_SET, dev_id, up, pri);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_TO_PRI_GET, dev_id, up, (a_uint32_t)pri);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_TO_DP_SET, dev_id, up, dp);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_TO_DP_GET, dev_id, up, (a_uint32_t)dp);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_PRI_TO_QU_SET, dev_id, pri, queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_PRI_TO_QU_GET, dev_id, pri, (a_uint32_t)queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_PRI_TO_EHQU_SET, dev_id, pri, queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_PRI_TO_EHQU_GET, dev_id, pri, (a_uint32_t)queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_EG_REMARK_SET, dev_id, tbl_id, tbl);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_EG_REMARK_GET, dev_id, tbl_id, tbl);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_fdb.c b/src/fal_uk/fal_fdb.c
new file mode 100644
index 0000000..47b2354
--- /dev/null
+++ b/src/fal_uk/fal_fdb.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_fdb.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_ADD, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_DELALL, dev_id, flag);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_DELPORT, dev_id, port_id, flag);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_DELMAC, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_FIRST, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_NEXT, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_FIND, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PT_LEARN_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PT_LEARN_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_AGE_CTRL_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_AGE_CTRL_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_VLAN_IVL_SVL_SET, dev_id, (a_uint32_t) smode);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_VLAN_IVL_SVL_GET, dev_id, (a_uint32_t) smode);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_AGE_TIME_SET, dev_id, (a_uint32_t) time);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_AGE_TIME_GET, dev_id, (a_uint32_t) time);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_ITERATE, dev_id, (a_uint32_t) iterator, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_EXTEND_NEXT, dev_id, (a_uint32_t)option, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_EXTEND_FIRST, dev_id, (a_uint32_t)option, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_TRANSFER, dev_id, old_port, new_port, fid, (a_uint32_t)option);
+ return rv;
+}
+
+sw_error_t
+fal_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FDB_LEARN_LIMIT_SET, dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+sw_error_t
+fal_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FDB_LEARN_LIMIT_GET, dev_id, port_id, (a_uint32_t)enable, (a_uint32_t)cnt);
+ return rv;
+}
+
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, dev_id, port_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, dev_id, port_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_LEARN_LIMIT_SET, dev_id, enable, cnt);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_LEARN_LIMIT_GET, dev_id, (a_uint32_t)enable, (a_uint32_t)cnt);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_LEARN_EXCEED_CMD_SET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_LEARN_EXCEED_CMD_GET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_RESV_ADD, dev_id, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_RESV_DEL, dev_id, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_RESV_FIND, dev_id, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_RESV_ITERATE, dev_id, (a_uint32_t)iterator, (a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PT_LEARN_STATIC_SET, dev_id, port_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PT_LEARN_STATIC_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PORT_ADD, dev_id, fid, addr, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FDB_PORT_DEL, dev_id, fid, addr, port_id);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_igmp.c b/src/fal_uk/fal_igmp.c
new file mode 100644
index 0000000..7bafe69
--- /dev/null
+++ b/src/fal_uk/fal_igmp.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_igmp.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMPS_MODE_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMPS_MODE_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_MLD_CMD_SET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_MLD_CMD_GET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_PT_JOIN_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_PT_JOIN_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_PT_LEAVE_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_PT_LEAVE_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_RP_SET, dev_id, (a_uint32_t) pts);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_RP_GET, dev_id, (a_uint32_t) pts);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_CREAT_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_CREAT_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_STATIC_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_STATIC_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_LEAKY_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_LEAKY_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_V3_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_V3_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_QUEUE_SET, dev_id, (a_uint32_t)enable, (a_uint32_t)queue);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_ENTRY_QUEUE_GET, dev_id, (a_uint32_t)enable, (a_uint32_t)queue);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMP_LEARN_LIMIT_SET, dev_id, port_id, enable, cnt);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMP_LEARN_LIMIT_GET, dev_id, port_id, (a_uint32_t)enable, (a_uint32_t)cnt);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, dev_id, port_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, dev_id, port_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_SG_ENTRY_SET, dev_id, entry);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_SG_ENTRY_CLEAR, dev_id, entry);
+ return rv;
+}
+
+sw_error_t
+fal_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IGMP_SG_ENTRY_SHOW, dev_id);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_init.c b/src/fal_uk/fal_init.c
new file mode 100644
index 0000000..1bfa951
--- /dev/null
+++ b/src/fal_uk/fal_init.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_SWITCH_RESET, dev_id);
+ return rv;
+}
+
+sw_error_t
+fal_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_SSDK_CFG, dev_id, ssdk_cfg);
+ return rv;
+}
diff --git a/src/fal_uk/fal_interface_ctrl.c b/src/fal_uk/fal_interface_ctrl.c
new file mode 100644
index 0000000..8fdde43
--- /dev/null
+++ b/src/fal_uk/fal_interface_ctrl.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_interface_ctrl.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PORT_3AZ_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PORT_3AZ_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MAC_MODE_SET, dev_id, port_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MAC_MODE_GET, dev_id, port_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PHY_MODE_SET, dev_id, phy_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PHY_MODE_GET, dev_id, phy_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FX100_CTRL_SET, dev_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t * config)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FX100_CTRL_GET, dev_id, (a_uint32_t)config);
+ return rv;
+}
+
+sw_error_t
+fal_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t *status)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FX100_STATUS_GET, dev_id, (a_uint32_t)status);
+ return rv;
+}
+
+sw_error_t
+fal_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MAC06_EXCH_SET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MAC06_EXCH_GET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
diff --git a/src/fal_uk/fal_ip.c b/src/fal_uk/fal_ip.c
new file mode 100644
index 0000000..96c9609
--- /dev/null
+++ b/src/fal_uk/fal_ip.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_ip.h"
+#include "fal_uk_if.h"
+
+
+sw_error_t
+fal_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_ADD, dev_id, (a_uint32_t) host_entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_DEL, dev_id, del_mode, (a_uint32_t) host_entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_GET, dev_id, get_mode, (a_uint32_t) host_entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_NEXT, dev_id, next_mode, (a_uint32_t) host_entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_COUNTER_BIND, dev_id, entry_id, cnt_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_HOST_PPPOE_BIND, dev_id, entry_id, pppoe_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flags)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_PT_ARP_LEARN_SET, dev_id, port_id, flags);
+ return rv;
+}
+
+sw_error_t
+fal_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t * flags)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_PT_ARP_LEARN_GET, dev_id, port_id, (a_uint32_t)flags);
+ return rv;
+}
+
+sw_error_t
+fal_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ARP_LEARN_SET, dev_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ARP_LEARN_GET, dev_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id, fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_SOURCE_GUARD_SET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id, fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_SOURCE_GUARD_GET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id, fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ARP_GUARD_SET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id, fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ARP_GUARD_GET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ROUTE_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_ROUTE_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_INTF_ENTRY_ADD, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_INTF_ENTRY_DEL, dev_id, del_mode, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_INTF_ENTRY_NEXT, dev_id, next_mode, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_UNK_SOURCE_CMD_SET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_UNK_SOURCE_CMD_GET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_UNK_SOURCE_CMD_SET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_UNK_SOURCE_CMD_GET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_AGE_TIME_SET, dev_id, (a_uint32_t) time);
+ return rv;
+}
+
+sw_error_t
+fal_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_IP_AGE_TIME_GET, dev_id, (a_uint32_t) time);
+ return rv;
+}
+
+sw_error_t
+fal_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_WCMP_HASH_MODE_SET, dev_id, hash_mode);
+ return rv;
+}
+
+sw_error_t
+fal_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_WCMP_HASH_MODE_GET, dev_id, (a_uint32_t) hash_mode);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_leaky.c b/src/fal_uk/fal_leaky.c
new file mode 100644
index 0000000..911bea5
--- /dev/null
+++ b/src/fal_uk/fal_leaky.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_leaky.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_uc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_UC_LEAKY_MODE_SET, dev_id, (a_uint32_t) ctrl_mode);
+ return rv;
+}
+
+sw_error_t
+fal_uc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_UC_LEAKY_MODE_GET, dev_id, (a_uint32_t) ctrl_mode);
+ return rv;
+}
+
+sw_error_t
+fal_mc_leaky_mode_set(a_uint32_t dev_id, fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MC_LEAKY_MODE_SET, dev_id, (a_uint32_t) ctrl_mode);
+ return rv;
+}
+
+sw_error_t
+fal_mc_leaky_mode_get(a_uint32_t dev_id, fal_leaky_ctrl_mode_t * ctrl_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MC_LEAKY_MODE_GET, dev_id, (a_uint32_t) ctrl_mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_LEAKY_MODE_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_LEAKY_MODE_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UC_LEAKY_MODE_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UC_LEAKY_MODE_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MC_LEAKY_MODE_SET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MC_LEAKY_MODE_GET, dev_id, (a_uint32_t) port_id, (a_uint32_t) enable);
+ return rv;
+}
diff --git a/src/fal_uk/fal_led.c b/src/fal_uk/fal_led.c
new file mode 100644
index 0000000..fcb8152
--- /dev/null
+++ b/src/fal_uk/fal_led.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_led.h"
+#include "fal_uk_if.h"
+
+
+sw_error_t
+fal_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_LED_PATTERN_SET, dev_id, (a_uint32_t)group,
+ (a_uint32_t)id, (a_uint32_t)pattern);
+ return rv;
+}
+
+sw_error_t
+fal_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_LED_PATTERN_GET, dev_id, (a_uint32_t)group,
+ (a_uint32_t)id, (a_uint32_t)pattern);
+ return rv;
+}
diff --git a/src/fal_uk/fal_mib.c b/src/fal_uk/fal_mib.c
new file mode 100644
index 0000000..e33d8ba
--- /dev/null
+++ b/src/fal_uk/fal_mib.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_mib.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_Info)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MIB_GET, dev_id, port_id,
+ (a_uint32_t) mib_Info);
+ return rv;
+}
+
+sw_error_t
+fal_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIB_STATUS_SET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIB_STATUS_GET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MIB_FLUSH_COUNTERS, dev_id, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIB_CPU_KEEP_SET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIB_CPU_KEEP_GET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
\ No newline at end of file
diff --git a/src/fal_uk/fal_mirror.c b/src/fal_uk/fal_mirror.c
new file mode 100644
index 0000000..475ea9d
--- /dev/null
+++ b/src/fal_uk/fal_mirror.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_mirror.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_ANALY_PT_SET, dev_id, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_ANALY_PT_GET, dev_id,
+ (a_uint32_t) port_id);
+ return rv;
+}
+
+sw_error_t
+fal_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_IN_PT_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_IN_PT_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_EG_PT_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_MIRROR_EG_PT_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
diff --git a/src/fal_uk/fal_misc.c b/src/fal_uk/fal_misc.c
new file mode 100644
index 0000000..9bfcf44
--- /dev/null
+++ b/src/fal_uk/fal_misc.c
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_misc.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_arp_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FRAME_MAX_SIZE_SET, dev_id, size);
+ return rv;
+}
+
+sw_error_t
+fal_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_FRAME_MAX_SIZE_GET, dev_id, (a_uint32_t) size);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_SA_CMD_SET, dev_id, port_id,
+ (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_SA_CMD_GET, dev_id, port_id,
+ (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_UC_FILTER_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_UC_FILTER_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_MC_FILTER_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_UNK_MC_FILTER_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_BC_FILTER_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_BC_FILTER_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_CPU_PORT_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_CPU_PORT_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_BC_TO_CPU_PORT_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_BC_TO_CPU_PORT_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_CMD_SET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_CMD_GET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DHCP_SET, dev_id, (a_uint32_t)port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DHCP_GET, dev_id, (a_uint32_t)port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_CMD_SET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_ARP_CMD_GET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EAPOL_CMD_SET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EAPOL_CMD_GET, dev_id, (a_uint32_t)cmd);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_ADD, dev_id, session_id, (a_uint32_t)strip_hdr);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_DEL, dev_id, session_id);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_GET, dev_id, session_id, (a_uint32_t)strip_hdr);
+ return rv;
+}
+
+sw_error_t
+fal_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EAPOL_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EAPOL_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RIPV1_STATUS_SET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RIPV1_STATUS_GET, dev_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ARP_REQ_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ARP_REQ_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ARP_ACK_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ARP_ACK_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_table_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_TABLE_ADD, dev_id, (a_uint32_t)session_tbl);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_table_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_TABLE_DEL, dev_id, (a_uint32_t)session_tbl);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_table_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_TABLE_GET, dev_id, (a_uint32_t)session_tbl);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_ID_SET, dev_id, index, id);
+ return rv;
+}
+
+sw_error_t
+fal_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PPPOE_SESSION_ID_GET, dev_id, index, (a_uint32_t)id);
+ return rv;
+}
+
+sw_error_t
+fal_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_MASK_SET, dev_id, intr_mask);
+ return rv;
+}
+
+sw_error_t
+fal_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_MASK_GET, dev_id, (a_uint32_t)intr_mask);
+ return rv;
+}
+
+sw_error_t
+fal_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_STATUS_GET, dev_id, (a_uint32_t)intr_status);
+ return rv;
+}
+
+sw_error_t
+fal_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_STATUS_CLEAR, dev_id, intr_status);
+ return rv;
+}
+
+sw_error_t
+fal_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_PORT_LINK_MASK_SET, dev_id, port_id, intr_mask);
+ return rv;
+}
+
+sw_error_t
+fal_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_PORT_LINK_MASK_GET, dev_id, port_id, (a_uint32_t)intr_mask);
+ return rv;
+}
+
+sw_error_t
+fal_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_PORT_LINK_STATUS_GET, dev_id, port_id, (a_uint32_t)intr_mask);
+ return rv;
+}
+
+sw_error_t
+fal_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_MASK_MAC_LINKCHG_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_MASK_MAC_LINKCHG_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t *port_bitmap)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_STATUS_MAC_LINKCHG_GET, dev_id, (a_uint32_t)port_bitmap);
+ return rv;
+}
+
+sw_error_t
+fal_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_CPU_VID_EN_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_CPU_VID_EN_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RTD_PPPOE_EN_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RTD_PPPOE_EN_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, dev_id);
+ return rv;
+}
\ No newline at end of file
diff --git a/src/fal_uk/fal_nat.c b/src/fal_uk/fal_nat.c
new file mode 100644
index 0000000..35e6c74
--- /dev/null
+++ b/src/fal_uk/fal_nat.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_nat.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_ADD, dev_id, (a_uint32_t) nat_entry);
+ return rv;
+}
+
+
+sw_error_t
+fal_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_DEL, dev_id, del_mode, (a_uint32_t) nat_entry);
+ return rv;
+}
+
+
+sw_error_t
+fal_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_GET, dev_id, get_mode, (a_uint32_t) nat_entry);
+ return rv;
+}
+
+sw_error_t
+fal_nat_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_NEXT, dev_id, next_mode, (a_uint32_t) nat_entry);
+ return rv;
+}
+
+sw_error_t
+fal_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_COUNTER_BIND, dev_id, entry_id, cnt_id, (a_uint32_t) enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_ADD, dev_id, (a_uint32_t) napt_entry);
+ return rv;
+}
+
+sw_error_t
+fal_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_DEL, dev_id, del_mode, (a_uint32_t) napt_entry);
+ return rv;
+}
+
+sw_error_t
+fal_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_GET, dev_id, get_mode, (a_uint32_t) napt_entry);
+ return rv;
+}
+
+sw_error_t
+fal_napt_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_NEXT, dev_id, next_mode, (a_uint32_t) napt_entry);
+ return rv;
+}
+
+sw_error_t
+fal_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_COUNTER_BIND, dev_id, entry_id, cnt_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_HASH_MODE_SET, dev_id, mode);
+ return rv;
+}
+
+sw_error_t
+fal_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_HASH_MODE_GET, dev_id, (a_uint32_t) mode);
+ return rv;
+}
+
+sw_error_t
+fal_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_STATUS_SET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_STATUS_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_MODE_SET, dev_id, (a_uint32_t) mode);
+ return rv;
+}
+
+sw_error_t
+fal_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAPT_MODE_GET, dev_id, (a_uint32_t) mode);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_BASE_ADDR_SET, dev_id, (a_uint32_t) addr);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_BASE_ADDR_GET, dev_id, (a_uint32_t) addr);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_BASE_MASK_SET, dev_id, (a_uint32_t) addr);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_BASE_MASK_GET, dev_id, (a_uint32_t) addr);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_ADDR_MODE_SET, dev_id, (a_uint32_t) map_en);
+ return rv;
+}
+
+sw_error_t
+fal_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PRV_ADDR_MODE_GET, dev_id, (a_uint32_t) map_en);
+ return rv;
+}
+
+sw_error_t
+fal_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PUB_ADDR_ENTRY_ADD, dev_id, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PUB_ADDR_ENTRY_DEL, dev_id, del_mode, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PUB_ADDR_ENTRY_NEXT, dev_id, next_mode, (a_uint32_t) entry);
+ return rv;
+}
+
+sw_error_t
+fal_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_UNK_SESSION_CMD_SET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
+sw_error_t
+fal_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NAT_UNK_SESSION_CMD_GET, dev_id, (a_uint32_t) cmd);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_port_ctrl.c b/src/fal_uk/fal_port_ctrl.c
new file mode 100644
index 0000000..4454fd5
--- /dev/null
+++ b/src/fal_uk/fal_port_ctrl.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_port_ctrl.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DUPLEX_SET, dev_id, port_id,
+ (a_uint32_t) duplex);
+ return rv;
+}
+
+sw_error_t
+fal_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DUPLEX_GET, dev_id, port_id,
+ (a_uint32_t) pduplex);
+ return rv;
+}
+
+sw_error_t
+fal_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_SPEED_SET, dev_id, port_id,
+ (a_uint32_t) speed);
+ return rv;
+}
+
+sw_error_t
+fal_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_SPEED_GET, dev_id, port_id,
+ (a_uint32_t) pspeed);
+ return rv;
+}
+
+sw_error_t
+fal_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_AN_GET, dev_id, port_id, (a_uint32_t) status);
+ return rv;
+}
+
+sw_error_t
+fal_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_AN_ENABLE, dev_id, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_AN_RESTART, dev_id, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_AN_ADV_SET, dev_id, port_id, autoadv);
+ return rv;
+}
+
+sw_error_t
+fal_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_AN_ADV_GET, dev_id, port_id,
+ (a_uint32_t) autoadv);
+ return rv;
+}
+
+sw_error_t
+fal_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_HDR_SET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_HDR_GET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FLOWCTRL_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FLOWCTRL_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FLOWCTRL_MODE_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FLOWCTRL_MODE_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_POWERSAVE_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_POWERSAVE_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_HIBERNATE_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_HIBERNATE_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ a_uint32_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_CDT, dev_id, port_id, mdi_pair,
+ (a_uint32_t) cable_status, (a_uint32_t)cable_len);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_RXHDR_SET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_RXHDR_GET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_TXHDR_SET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_TXHDR_GET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_HEADER_TYPE_SET, dev_id, (a_uint32_t)enable, type);
+ return rv;
+}
+
+sw_error_t
+fal_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_HEADER_TYPE_GET, dev_id, (a_uint32_t)enable, (a_uint32_t)type);
+ return rv;
+}
+
+sw_error_t
+fal_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TXMAC_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TXMAC_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RXMAC_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RXMAC_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TXFC_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TXFC_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RXFC_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RXFC_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_BP_STATUS_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_BP_STATUS_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_LINK_MODE_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_LINK_MODE_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_LINK_STATUS_GET, dev_id, port_id, (a_uint32_t)status);
+ return rv;
+}
+
+sw_error_t
+fal_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MAC_LOOPBACK_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MAC_LOOPBACK_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
diff --git a/src/fal_uk/fal_portvlan.c b/src/fal_uk/fal_portvlan.c
new file mode 100644
index 0000000..572ec88
--- /dev/null
+++ b/src/fal_uk/fal_portvlan.c
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_portvlan.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ING_MODE_SET, dev_id, port_id,
+ (a_uint32_t) port_1qmode);
+ return rv;
+}
+
+sw_error_t
+fal_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_ING_MODE_GET, dev_id, port_id,
+ (a_uint32_t) pport_1qmode);
+ return rv;
+}
+
+sw_error_t
+fal_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_EG_MODE_SET, dev_id, port_id,
+ (a_uint32_t) port_egvlanmode);
+ return rv;
+}
+
+sw_error_t
+fal_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_EG_MODE_GET, dev_id, port_id,
+ (a_uint32_t) pport_egvlanmode);
+ return rv;
+}
+
+sw_error_t
+fal_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_MEM_ADD, dev_id, port_id,
+ (a_uint32_t) mem_port_id);
+ return rv;
+}
+
+sw_error_t
+fal_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_MEM_DEL, dev_id, port_id,
+ (a_uint32_t) mem_port_id);
+ return rv;
+}
+
+sw_error_t
+fal_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_MEM_UPDATE, dev_id, port_id,
+ (a_uint32_t) mem_port_map);
+ return rv;
+}
+
+sw_error_t
+fal_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_MEM_GET, dev_id, port_id,
+ (a_uint32_t) mem_port_map);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_VID_SET, dev_id, port_id,
+ vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_VID_GET, dev_id, port_id,
+ (a_uint32_t) vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FORCE_DEF_VID_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FORCE_DEF_VID_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FORCE_PORTVLAN_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_FORCE_PORTVLAN_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_NESTVLAN_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_NESTVLAN_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NESTVLAN_TPID_SET, dev_id, tpid);
+ return rv;
+}
+
+sw_error_t
+fal_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NESTVLAN_TPID_GET, dev_id, (a_uint32_t) tpid);
+ return rv;
+}
+
+sw_error_t
+fal_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IN_VLAN_MODE_SET, dev_id, port_id, (a_uint32_t) mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_IN_VLAN_MODE_GET, dev_id, port_id, (a_uint32_t) mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_TLS_SET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_TLS_GET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_PRI_PROPAGATION_SET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_PRI_PROPAGATION_GET, dev_id, port_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_SVID_SET, dev_id, port_id, vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_SVID_GET, dev_id, port_id, (a_uint32_t)vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_CVID_SET, dev_id, port_id, vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_DEF_CVID_GET, dev_id, port_id, (a_uint32_t)vid);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_PROPAGATION_SET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_PROPAGATION_GET, dev_id, port_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_TRANS_ADD, dev_id, port_id, entry);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_TRANS_DEL, dev_id, port_id, entry);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_TRANS_GET, dev_id, port_id, entry);
+ return rv;
+}
+
+sw_error_t
+fal_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QINQ_MODE_SET, dev_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QINQ_MODE_GET, dev_id, (a_uint32_t)mode);
+ return rv;
+}
+
+sw_error_t
+fal_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_QINQ_ROLE_SET, dev_id, port_id, (a_uint32_t)role);
+ return rv;
+}
+
+sw_error_t
+fal_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_QINQ_ROLE_GET, dev_id, port_id, (a_uint32_t)role);
+ return rv;
+}
+
+sw_error_t
+fal_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_VLAN_TRANS_ITERATE, dev_id, port_id,
+ (a_uint32_t)iterator,(a_uint32_t)entry);
+ return rv;
+}
+
+sw_error_t
+fal_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MAC_VLAN_XLT_SET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PT_MAC_VLAN_XLT_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NETISOLATE_SET, dev_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_NETISOLATE_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EG_FLTR_BYPASS_EN_SET, dev_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_EG_FLTR_BYPASS_EN_GET, dev_id, (a_uint32_t) enable);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_qos.c b/src/fal_uk/fal_qos.c
new file mode 100644
index 0000000..c82342e
--- /dev/null
+++ b/src/fal_uk/fal_qos.c
@@ -0,0 +1,393 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_qos.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_SCH_MODE_SET, dev_id, mode,
+ (a_uint32_t) weight);
+ return rv;
+}
+
+sw_error_t
+fal_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_SCH_MODE_GET, dev_id, mode,
+ (a_uint32_t) weight);
+ return rv;
+}
+
+sw_error_t
+fal_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QU_TX_BUF_ST_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QU_TX_BUF_ST_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QU_TX_BUF_NR_SET, dev_id, port_id, queue_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QU_TX_BUF_NR_GET, dev_id, port_id, queue_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_TX_BUF_ST_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_TX_BUF_ST_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_RED_EN_SET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_RED_EN_GET, dev_id, port_id,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_TX_BUF_NR_SET, dev_id, port_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_TX_BUF_NR_GET, dev_id, port_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_RX_BUF_NR_SET, dev_id, port_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_RX_BUF_NR_GET, dev_id, port_id,
+ (a_uint32_t) number);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up, fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_QU_SET, dev_id, up,
+ (a_uint32_t) queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_UP_QU_GET, dev_id, up,
+ (a_uint32_t) queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp, fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_DSCP_QU_SET, dev_id, dscp,
+ (a_uint32_t) queue);
+ return rv;
+}
+
+sw_error_t
+fal_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_COSMAP_DSCP_QU_GET, dev_id, dscp,
+ (a_uint32_t) queue);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_MODE_SET, dev_id, port_id, mode,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_MODE_GET, dev_id, port_id, mode,
+ (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_MODE_PRI_SET, dev_id, port_id, mode, pri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_MODE_PRI_GET, dev_id, port_id, mode,
+ (a_uint32_t) pri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PORT_DEF_UP_SET, dev_id, port_id, up);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PORT_DEF_UP_GET, dev_id, port_id, (a_uint32_t) up);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PORT_SCH_MODE_SET, dev_id, port_id, mode,
+ (a_uint32_t) weight);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PORT_SCH_MODE_GET, dev_id, port_id, mode,
+ (a_uint32_t) weight);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_DEF_SPRI_SET, dev_id, port_id, spri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_DEF_SPRI_GET, dev_id, port_id, (a_uint32_t)spri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_DEF_CPRI_SET, dev_id, port_id, cpri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_DEF_CPRI_GET, dev_id, port_id, (a_uint32_t)cpri);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_FORCE_SPRI_ST_SET, dev_id, port_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ rv = sw_uk_exec(SW_API_QOS_PT_FORCE_SPRI_ST_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_FORCE_CPRI_ST_SET, dev_id, port_id, enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_PT_FORCE_CPRI_ST_GET, dev_id, port_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QUEUE_REMARK_SET, dev_id, port_id, queue_id, tbl_id, enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_QOS_QUEUE_REMARK_GET, dev_id, port_id, queue_id, (a_uint32_t)tbl_id, (a_uint32_t)enable);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_rate.c b/src/fal_uk/fal_rate.c
new file mode 100644
index 0000000..cef5ecd
--- /dev/null
+++ b/src/fal_uk/fal_rate.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_rate.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_QU_EGRL_SET, dev_id, port_id, queue_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_QU_EGRL_GET, dev_id, port_id, queue_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_EGRL_SET, dev_id, port_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_EGRL_GET, dev_id, port_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_INRL_SET, dev_id, port_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_INRL_GET, dev_id, port_id,
+ (a_uint32_t) speed, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STORM_CTRL_FRAME_SET, dev_id, port_id,
+ (a_uint32_t) frame_type, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t frame_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STORM_CTRL_FRAME_GET, dev_id, port_id,
+ (a_uint32_t) frame_type, (a_uint32_t) enable);
+ return rv;
+}
+
+sw_error_t
+fal_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STORM_CTRL_RATE_SET, dev_id, port_id,
+ (a_uint32_t) rate);
+ return rv;
+}
+
+sw_error_t
+fal_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STORM_CTRL_RATE_GET, dev_id, port_id,
+ (a_uint32_t) rate);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PORT_POLICER_SET, dev_id, port_id,
+ (a_uint32_t) policer);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PORT_POLICER_GET, dev_id, port_id,
+ (a_uint32_t) policer);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PORT_SHAPER_SET, dev_id, port_id,
+ (a_uint32_t) enable, (a_uint32_t) shaper);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PORT_SHAPER_GET, dev_id, port_id,
+ (a_uint32_t) enable, (a_uint32_t) shaper);
+ return rv;
+}
+
+sw_error_t
+fal_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_QUEUE_SHAPER_SET, dev_id, port_id, queue_id,
+ (a_uint32_t) enable, (a_uint32_t) shaper);
+ return rv;
+}
+
+sw_error_t
+fal_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_QUEUE_SHAPER_GET, dev_id, port_id, queue_id,
+ (a_uint32_t) enable, (a_uint32_t) shaper);
+ return rv;
+}
+
+sw_error_t
+fal_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_ACL_POLICER_SET, dev_id, policer_id, (a_uint32_t) policer);
+ return rv;
+}
+
+sw_error_t
+fal_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_ACL_POLICER_GET, dev_id, policer_id, (a_uint32_t) policer);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_ADDRATEBYTE_SET, dev_id, port_id, number);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_ADDRATEBYTE_GET, dev_id, port_id, number);
+ return rv;
+}
+
+sw_error_t
+fal_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_GOL_FLOW_EN_SET, dev_id, port_id, enable);
+ return rv;
+}
+
+
+sw_error_t
+fal_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_RATE_PT_GOL_FLOW_EN_GET, dev_id, port_id, enable);
+ return rv;
+}
+
+
diff --git a/src/fal_uk/fal_reg_access.c b/src/fal_uk/fal_reg_access.c
new file mode 100644
index 0000000..fecca00
--- /dev/null
+++ b/src/fal_uk/fal_reg_access.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_reg_access.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PHY_GET, dev_id, phy_addr, reg, value);
+ return rv;
+}
+
+sw_error_t
+fal_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_PHY_SET, dev_id, phy_addr, reg, value);
+ return rv;
+}
+
+sw_error_t
+fal_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_REG_GET, dev_id, reg_addr, value, value_len);
+ return rv;
+}
+
+sw_error_t
+fal_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_REG_SET, dev_id, reg_addr, value, value_len);
+ return rv;
+}
+
+
+sw_error_t
+fal_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_REG_FIELD_GET, dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ return rv;
+}
+
+
+sw_error_t
+fal_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_REG_FIELD_SET, dev_id, reg_addr, bit_offset, field_len, value, value_len);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_sec.c b/src/fal_uk/fal_sec.c
new file mode 100644
index 0000000..c29a78e
--- /dev/null
+++ b/src/fal_uk/fal_sec.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_sec.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void * value)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_SEC_NORM_SET, dev_id, item, (a_uint32_t) value);
+ return rv;
+}
+
+sw_error_t
+fal_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void * value)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_SEC_NORM_GET, dev_id, item, (a_uint32_t) value);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_stp.c b/src/fal_uk/fal_stp.c
new file mode 100644
index 0000000..9554ff4
--- /dev/null
+++ b/src/fal_uk/fal_stp.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_stp.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STP_PT_STATE_SET, dev_id, st_id, port_id,
+ (a_uint32_t) state);
+ return rv;
+}
+
+sw_error_t
+fal_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_STP_PT_STATE_GET, dev_id, st_id, port_id,
+ (a_uint32_t) state);
+ return rv;
+}
diff --git a/src/fal_uk/fal_trunk.c b/src/fal_uk/fal_trunk.c
new file mode 100644
index 0000000..ae3a293
--- /dev/null
+++ b/src/fal_uk/fal_trunk.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_trunk.h"
+#include "fal_uk_if.h"
+
+
+sw_error_t
+fal_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_GROUP_SET, dev_id, trunk_id, enable,
+ (a_uint32_t) member);
+ return rv;
+}
+
+sw_error_t
+fal_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_GROUP_GET, dev_id, trunk_id, enable,
+ (a_uint32_t) member);
+ return rv;
+}
+
+sw_error_t
+fal_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_HASH_SET, dev_id, hash_mode);
+ return rv;
+}
+
+sw_error_t
+fal_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_HASH_GET, dev_id, hash_mode);
+ return rv;
+}
+
+sw_error_t
+fal_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_MAN_SA_SET, dev_id, addr);
+ return rv;
+}
+
+sw_error_t
+fal_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_TRUNK_MAN_SA_GET, dev_id, addr);
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_uk_if.c b/src/fal_uk/fal_uk_if.c
new file mode 100644
index 0000000..d56b3dc
--- /dev/null
+++ b/src/fal_uk/fal_uk_if.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include <stdarg.h>
+#include "sw.h"
+#include "ssdk_init.h"
+#include "sw_api.h"
+#include "sw_api_us.h"
+#include "api_access.h"
+
+sw_error_t
+sw_uk_exec(a_uint32_t api_id, ...)
+{
+ a_uint32_t value[SW_MAX_API_PARAM] = { 0 };
+ a_uint32_t rtn = SW_OK, i;
+ sw_error_t rv;
+ va_list arg_ptr;
+ a_uint32_t nr_param = 0;
+
+ if((nr_param = sw_api_param_nums(api_id)) == 0)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ value[0] = api_id;
+ value[1] = (a_uint32_t)&rtn;
+
+ va_start(arg_ptr, api_id);
+ for (i = 0; i < nr_param; i++)
+ {
+ value[i + 2] = va_arg(arg_ptr, a_uint32_t);
+ }
+ va_end(arg_ptr);
+
+ rv = sw_uk_if(value);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+ return rtn;
+}
+
+sw_error_t
+ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_init(cfg->nl_prot);
+ return rv;
+}
+
+sw_error_t
+ssdk_cleanup(void)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_cleanup();
+ return rv;
+}
+
diff --git a/src/fal_uk/fal_vlan.c b/src/fal_uk/fal_vlan.c
new file mode 100644
index 0000000..43cfd67
--- /dev/null
+++ b/src/fal_uk/fal_vlan.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_ioctl.h"
+#include "fal_vlan.h"
+#include "fal_uk_if.h"
+
+sw_error_t
+fal_vlan_entry_append(a_uint32_t dev_id, fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_APPEND, dev_id, (a_uint32_t) vlan_entry);
+ return rv;
+}
+
+
+sw_error_t
+fal_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_ADD, dev_id, vlan_id);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_NEXT, dev_id, vlan_id, (a_uint32_t) p_vlan);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_FIND, dev_id, vlan_id, (a_uint32_t) p_vlan);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_MEM_UPDATE, dev_id, vlan_id, member,
+ u_member);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_DEL, dev_id, vlan_id);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_FLUSH, dev_id);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_FID_SET, dev_id, vlan_id, fid);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_FID_GET, dev_id, vlan_id, (a_uint32_t)fid);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_MEMBER_ADD, dev_id, vlan_id, port_id, port_info);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_MEMBER_DEL, dev_id, vlan_id, port_id);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_LEARN_STATE_SET, dev_id, vlan_id, (a_uint32_t)enable);
+ return rv;
+}
+
+sw_error_t
+fal_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ rv = sw_uk_exec(SW_API_VLAN_LEARN_STATE_GET, dev_id, vlan_id, (a_uint32_t)enable);
+ return rv;
+}
+
+
diff --git a/src/hsl/Makefile b/src/hsl/Makefile
new file mode 100644
index 0000000..98888da
--- /dev/null
+++ b/src/hsl/Makefile
@@ -0,0 +1,28 @@
+LOC_DIR=/src/hsl
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=hsl_dev.c hsl_port_prop.c hsl_api.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += hsl_acl.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=hsl_dev.c hsl_api.c
+ endif
+ endif
+endif
+
+ifeq (TRUE, $(API_LOCK))
+ SRC_LIST += hsl_lock.c
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/hsl/athena/Makefile b/src/hsl/athena/Makefile
new file mode 100644
index 0000000..7cce5d2
--- /dev/null
+++ b/src/hsl/athena/Makefile
@@ -0,0 +1,44 @@
+LOC_DIR=src/hsl/athena
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=athena_reg_access.c athena_init.c
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += athena_fdb.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += athena_mib.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += athena_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += athena_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += athena_vlan.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=athena_reg_access.c athena_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring ATHENA, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/hsl/athena/athena_fdb.c b/src/hsl/athena/athena_fdb.c
new file mode 100644
index 0000000..bb58d01
--- /dev/null
+++ b/src/hsl/athena/athena_fdb.c
@@ -0,0 +1,630 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_fdb ATHENA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_fdb.h"
+#include "athena_reg.h"
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+
+#define ARL_FIRST_ENTRY 1001
+
+static a_bool_t
+athena_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+athena_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+athena_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 2, reg[2]);
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ hsl_dev_t *p_dev;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+ if (entry->da_queue > (p_dev->nr_queue - 1))
+ return SW_BAD_PARAM;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+ athena_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ return SW_OK;
+}
+
+static void
+athena_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (1 == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x3;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 0; i < 4; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+ }
+
+ for (i = 4; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+ }
+
+ return;
+}
+
+static sw_error_t
+athena_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 1000;
+ a_uint32_t entry;
+
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_BUSY;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, op, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 1000;
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+ (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (full_vio)
+ {
+ if (ARL_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == op)
+ || (ARL_FLUSH_PORT_UNICAST == op))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+athena_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0 };
+ a_uint32_t destport = 0;
+ a_uint32_t hwop = op;
+
+ if (ARL_NEXT_ENTRY == op)
+ {
+ athena_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set destport not zero */
+ if (ARL_NEXT_ENTRY == op)
+ {
+ reg[2] = 0xf;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ /* get hardware enrety */
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, destport, reg[2]);
+
+ athena_atu_hw_to_sw(reg, entry);
+
+ /* If hardware return back with address and status all zero,
+ that means no other next valid entry in fdb table */
+ if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr))
+ && (0 == destport)
+ && (ARL_NEXT_ENTRY == hwop))
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0, 0, 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((A_TRUE == athena_fdb_is_zeroaddr(entry->addr))
+ && (0 == entry->port.map)
+ && (0 == entry->port.id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = athena_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = athena_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = athena_fdb_commit(dev_id, ARL_FLUSH_PORT_UNICAST);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ athena_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = athena_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = athena_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+ return rv;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * Athena doesn't support flag option, flag should be setted as zero.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_first(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ * @details Comments:
+ * For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_fdb_next(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+athena_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = athena_fdb_add;
+ p_api->fdb_del_all = athena_fdb_del_all;
+ p_api->fdb_del_by_port = athena_fdb_del_by_port;
+ p_api->fdb_del_by_mac = athena_fdb_del_by_mac;
+ p_api->fdb_first = athena_fdb_first;
+ p_api->fdb_next = athena_fdb_next;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/athena/athena_init.c b/src/hsl/athena/athena_init.c
new file mode 100644
index 0000000..8a3345a
--- /dev/null
+++ b/src/hsl/athena/athena_init.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_init ATHENA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_mib.h"
+#include "athena_port_ctrl.h"
+#include "athena_portvlan.h"
+#include "athena_vlan.h"
+#include "athena_fdb.h"
+#include "athena_reg_access.h"
+#include "athena_reg.h"
+#include "athena_init.h"
+
+static ssdk_init_cfg * athena_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+athena_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ if (HSL_CPU_1_PLUS == mode)
+ {
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != (pdev->nr_ports -1)))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port but exclude wan port in some cases */
+ if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ if ((port_id != pdev->cpu_port_nr)
+ && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+athena_hw_init(a_uint32_t dev_id)
+{
+ hsl_dev_t *pdev = NULL;
+ a_uint32_t port_id, data;
+ sw_error_t rv;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (NULL == pdev)
+ {
+ return SW_NOT_INITIALIZED;
+ }
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (port_id == pdev->cpu_port_nr)
+ {
+ continue;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+
+#endif
+
+static sw_error_t
+athena_dev_init(a_uint32_t dev_id)
+{
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ pdev->nr_ports = 6;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 16;
+ pdev->hw_vlan_query = A_FALSE;
+ pdev->nr_queue = 4;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_athena_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ a_uint32_t val;
+ sw_error_t rv;
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ ATHENA_VLAN_RESET(rv, dev_id);
+
+ rv = athena_hw_init(dev_id);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_cleanup(a_uint32_t dev_id)
+{
+ if (athena_cfg[dev_id])
+ {
+ aos_mem_free(athena_cfg[dev_id]);
+ athena_cfg[dev_id] = NULL;
+ }
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ sw_error_t rv;
+ ATHENA_VLAN_CLEANUP(rv, dev_id);
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @brief Reset Athena module.
+ * @details Comments:
+ * This operation will reset athena.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init Athena module.
+ * @details Comments:
+ * This operation will init athena.
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+athena_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == athena_cfg[dev_id])
+ {
+ athena_cfg[dev_id] = (ssdk_init_cfg *)aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == athena_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(athena_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(athena_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(athena_dev_init(dev_id));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ sw_error_t rv;
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(athena_portproperty_init(dev_id, cfg->cpu_mode));
+
+ ATHENA_MIB_INIT(rv, dev_id);
+ ATHENA_PORT_CTRL_INIT(rv, dev_id);
+ ATHENA_PORTVLAN_INIT(rv, dev_id);
+ ATHENA_VLAN_INIT(rv, dev_id);
+ ATHENA_FDB_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = athena_reset;
+ p_api->dev_clean = athena_cleanup;
+ }
+
+ SW_RTN_ON_ERROR(athena_hw_init(dev_id));
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/athena/athena_mib.c b/src/hsl/athena/athena_mib.c
new file mode 100644
index 0000000..050a668
--- /dev/null
+++ b/src/hsl/athena/athena_mib.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_mib ATHENA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_mib.h"
+#include "athena_reg.h"
+
+static sw_error_t
+_athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val0 = 0, val1 = 0;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val0 + val1;
+
+ mib_info->Rx1518Byte = 0; //reserved for s16
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val0 + val1;
+
+ mib_info->Tx1518Byte = 0; //reserved for s16
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val0 + val1;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val0), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL_2, port_id,
+ (a_uint8_t *) (&val1), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val0 + val1;
+
+ return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+athena_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = athena_get_mib_info;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/athena/athena_port_ctrl.c b/src/hsl/athena/athena_port_ctrl.c
new file mode 100644
index 0000000..354f402
--- /dev/null
+++ b/src/hsl/athena/athena_port_ctrl.c
@@ -0,0 +1,727 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_port_ctrl ATHENA_PORT_CTRL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_port_ctrl.h"
+#include "athena_reg.h"
+#include "f2_phy.h"
+
+
+static sw_error_t
+_athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+ a_uint32_t reg_save = 0;
+ a_uint32_t reg_val = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ //save reg value
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ reg_save = reg_val;
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ //set mac be config by sw and turn off RX TX MAC_EN
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = f2_phy_set_duplex(dev_id, phy_id, duplex);
+
+ //retore reg value
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_duplex(dev_id, phy_id, pduplex);
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SPEED_100 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = f2_phy_set_speed(dev_id, phy_id, speed);
+
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_speed(dev_id, phy_id, pspeed);
+
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f2_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f2_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * Auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp snooping feature on a particular port all kinds
+ * igmp packets received on this port would be acknowledged by hardware.
+ * Athena only supports igmp packets, it doesn't support mld packets.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_igmps_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp packets snooping status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_igmps_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+athena_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = athena_port_duplex_get;
+ p_api->port_duplex_set = athena_port_duplex_set;
+ p_api->port_speed_get = athena_port_speed_get;
+ p_api->port_speed_set = athena_port_speed_set;
+ p_api->port_autoneg_status_get = athena_port_autoneg_status_get;
+ p_api->port_autoneg_enable = athena_port_autoneg_enable;
+ p_api->port_autoneg_restart = athena_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = athena_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = athena_port_autoneg_adv_set;
+ p_api->port_igmps_status_set = athena_port_igmps_status_set;
+ p_api->port_igmps_status_get = athena_port_igmps_status_get;
+ p_api->port_powersave_set = athena_port_powersave_set;
+ p_api->port_powersave_get = athena_port_powersave_get;
+ p_api->port_hibernate_set = athena_port_hibernate_set;
+ p_api->port_hibernate_get = athena_port_hibernate_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/athena/athena_portvlan.c b/src/hsl/athena/athena_portvlan.c
new file mode 100644
index 0000000..3869fb1
--- /dev/null
+++ b/src/hsl/athena/athena_portvlan.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_port_vlan ATHENA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_portvlan.h"
+#include "athena_reg.h"
+
+
+static sw_error_t
+_athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+
+static sw_error_t
+_athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_EG_TAGGED == port_egvlanmode) || (FAL_EG_HYBRID == port_egvlanmode))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+athena_portvlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = athena_port_1qmode_get;
+ p_api->port_1qmode_set = athena_port_1qmode_set;
+ p_api->port_egvlanmode_get = athena_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = athena_port_egvlanmode_set;
+ p_api->portvlan_member_add = athena_portvlan_member_add;
+ p_api->portvlan_member_del = athena_portvlan_member_del;
+ p_api->portvlan_member_update = athena_portvlan_member_update;
+ p_api->portvlan_member_get = athena_portvlan_member_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/athena/athena_reg_access.c b/src/hsl/athena/athena_reg_access.c
new file mode 100644
index 0000000..dd7fad4
--- /dev/null
+++ b/src/hsl/athena/athena_reg_access.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "athena_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_athena_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_athena_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in lower address, we should write the higher 16-bit register then the */
+ /* lower one */
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in lower address */
+ reg_word_addr--;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+athena_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+athena_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _athena_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+athena_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _athena_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+athena_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ return SW_OK;
+}
+
+sw_error_t
+athena_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(athena_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+ SW_RTN_ON_ERROR(athena_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->phy_get = athena_phy_get;
+ p_api->phy_set = athena_phy_set;
+ p_api->reg_get = athena_reg_get;
+ p_api->reg_set = athena_reg_set;
+ p_api->reg_field_get = athena_reg_field_get;
+ p_api->reg_field_set = athena_reg_field_set;
+ p_api->dev_access_set= athena_access_mode_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
+
diff --git a/src/hsl/athena/athena_vlan.c b/src/hsl/athena/athena_vlan.c
new file mode 100644
index 0000000..7040ecb
--- /dev/null
+++ b/src/hsl/athena/athena_vlan.c
@@ -0,0 +1,613 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup athena_vlan ATHENA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "athena_vlan.h"
+#include "athena_reg.h"
+
+#define MAX_VLAN_ENTRY 16
+#define MAX_VLAN_ID 4094
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+
+typedef struct
+{
+ fal_vlan_t vlan_entry;
+ a_bool_t active;
+} v_array_t;
+
+static v_array_t *p_vlan_table[SW_MAX_NR_DEV] = { 0 };
+
+static sw_error_t
+athena_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+athena_vlan_table_location(a_uint32_t dev_id, a_uint16_t vlan_id,
+ a_int16_t * loc)
+{
+ a_int16_t i = 0;
+ v_array_t *p_v_array;
+
+ if (p_vlan_table[dev_id] == NULL)
+ return SW_NOT_INITIALIZED;
+
+ p_v_array = p_vlan_table[dev_id];
+
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ if ((p_v_array[i].active == A_TRUE)
+ && (p_v_array[i].vlan_entry.vid == vlan_id))
+ break;
+ }
+
+ if (i == MAX_VLAN_ENTRY)
+ return SW_NOT_FOUND;
+
+ *loc = i;
+
+ return SW_OK;
+}
+
+static sw_error_t
+athena_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+ if (0 != vlan_entry->u_ports)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+#ifdef HSL_STANDALONG
+ a_int16_t i, loc = MAX_VLAN_ENTRY;
+ v_array_t *p_v_array;
+#endif
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+#ifdef HSL_STANDALONG
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ if (p_v_array[i].active == A_FALSE)
+ {
+ loc = i;
+ }
+ else if (p_v_array[i].vlan_entry.vid == vlan_entry->vid)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+
+ if (loc == MAX_VLAN_ENTRY)
+ return SW_FULL;
+#endif
+
+ rv = athena_vlan_sw_to_hw(vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+ p_v_array[loc].vlan_entry = *vlan_entry;
+ p_v_array[loc].active = A_TRUE;
+#endif
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t vtable_entry = 0;
+#ifdef HSL_STANDALONG
+ a_int16_t i, loc = MAX_VLAN_ENTRY;
+ v_array_t *p_v_array;
+#endif
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+#ifdef HSL_STANDALONG
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ if (p_v_array[i].active == A_FALSE)
+ {
+ loc = i;
+ }
+ else if (p_v_array[i].vlan_entry.vid == vlan_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+
+ if (loc == MAX_VLAN_ENTRY)
+ return SW_FULL;
+#endif
+
+ /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+ vtable_entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, vtable_entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ /* set default value for VLAN_TABLE_FUNC1, all 0 */
+ vtable_entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, vtable_entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&vtable_entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+ p_v_array[loc].vlan_entry.vid = vlan_id;
+ p_v_array[loc].vlan_entry.mem_ports = 0;
+ p_v_array[loc].vlan_entry.u_ports = 0;
+ p_v_array[loc].vlan_entry.vid_pri_en = A_FALSE;
+ p_v_array[loc].vlan_entry.vid_pri = 0;
+ p_v_array[loc].active = A_TRUE;
+#endif
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+#ifdef HSL_STANDALONG
+ a_uint16_t i = 0, loc = MAX_VLAN_ENTRY;
+ a_uint16_t tmp_vid = MAX_VLAN_ID + 1;
+ v_array_t *p_v_array;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ if ((p_v_array[i].active == A_TRUE)
+ && (p_v_array[i].vlan_entry.vid > vlan_id))
+ {
+ if (tmp_vid > p_v_array[i].vlan_entry.vid)
+ {
+ loc = i;
+ tmp_vid = p_v_array[i].vlan_entry.vid;
+ }
+ }
+ }
+
+ if (loc == MAX_VLAN_ENTRY)
+ return SW_NO_MORE;
+
+ *p_vlan = p_v_array[loc].vlan_entry;
+
+ return SW_OK;
+#else
+ return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+#ifdef HSL_STANDALONG
+ a_int16_t loc;
+ v_array_t *p_v_array;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+ SW_RTN_ON_ERROR(rv);
+ *p_vlan = p_v_array[loc].vlan_entry;
+
+ return SW_OK;
+#else
+ return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+#ifdef HSL_STANDALONG
+ sw_error_t rv;
+ a_int16_t loc;
+ a_uint32_t reg_tmp;
+ v_array_t *p_v_array;
+ fal_vlan_t *p_sw_vlan;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ if (u_member != 0)
+ return SW_BAD_PARAM;
+
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+ SW_RTN_ON_ERROR(rv);
+ p_sw_vlan = &p_v_array[loc].vlan_entry;
+
+ /* set value for VLAN_TABLE_FUNC0, all 0 except vid */
+ reg_tmp = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg_tmp);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN,
+ (a_int32_t)p_sw_vlan->vid_pri_en, reg_tmp);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, p_sw_vlan->vid_pri, reg_tmp);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®_tmp), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set vlan member for VLAN_TABLE_FUNC1 */
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+ (a_uint8_t *) (&member), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ p_v_array[loc].vlan_entry.mem_ports = member;
+
+ return SW_OK;
+#else
+ return SW_NOT_SUPPORTED;
+#endif
+}
+
+
+static sw_error_t
+_athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_int16_t loc;
+ a_uint32_t reg_tmp;
+#ifdef HSL_STANDALONG
+ v_array_t *p_v_array;
+#endif
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+#ifdef HSL_STANDALONG
+ if ((p_v_array = p_vlan_table[dev_id]) == NULL)
+ return SW_NOT_INITIALIZED;
+
+ rv = athena_vlan_table_location(dev_id, vlan_id, &loc);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ reg_tmp = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+ (a_uint8_t *) (®_tmp), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = athena_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+#ifdef HSL_STANDALONG
+ p_v_array[loc].active = A_FALSE;
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_vlan_reset(a_uint32_t dev_id)
+{
+#ifdef HSL_STANDALONG
+ a_int16_t i;
+ v_array_t *p_v_array;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_zero(p_vlan_table[dev_id], MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+
+ p_v_array = p_vlan_table[dev_id];
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ p_v_array[i].active = A_FALSE;
+ }
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+athena_vlan_cleanup(a_uint32_t dev_id)
+{
+ if (p_vlan_table[dev_id])
+ {
+ aos_mem_free(p_vlan_table[dev_id]);
+ p_vlan_table[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_member_update(dev_id, vlan_id, member, u_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+athena_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _athena_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+athena_vlan_init(a_uint32_t dev_id)
+{
+#ifdef HSL_STANDALONG
+ a_int16_t i;
+ v_array_t *p_v_array;
+ v_array_t *p_mem;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ /* allocate memory for vlan info */
+ p_mem = aos_mem_alloc(MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+ if (p_mem == NULL)
+ return SW_OUT_OF_MEM;
+
+ aos_mem_zero(p_mem, MAX_VLAN_ENTRY * (sizeof (v_array_t)));
+
+ /* start address for vlan info */
+ p_vlan_table[dev_id] = p_v_array = p_mem;
+
+ for (i = 0; i < MAX_VLAN_ENTRY; i++)
+ {
+ p_v_array[i].active = A_FALSE;
+ }
+#endif
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = athena_vlan_entry_append;
+ p_api->vlan_creat = athena_vlan_create;
+ p_api->vlan_delete = athena_vlan_delete;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/Makefile b/src/hsl/garuda/Makefile
new file mode 100644
index 0000000..67ebb12
--- /dev/null
+++ b/src/hsl/garuda/Makefile
@@ -0,0 +1,84 @@
+LOC_DIR=src/hsl/garuda
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=garuda_reg_access.c garuda_init.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += garuda_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += garuda_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += garuda_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += garuda_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += garuda_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += garuda_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += garuda_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += garuda_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += garuda_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += garuda_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += garuda_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += garuda_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += garuda_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += garuda_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ SRC_LIST += garuda_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=garuda_reg_access.c garuda_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring GARUDA, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/hsl/garuda/garuda_acl.c b/src/hsl/garuda/garuda_acl.c
new file mode 100644
index 0000000..0af2a8d
--- /dev/null
+++ b/src/hsl/garuda/garuda_acl.c
@@ -0,0 +1,3025 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_acl GARUDA_ACL
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "hsl_port_prop.h"
+#include "garuda_acl.h"
+#include "garuda_reg.h"
+
+//#define GARUDA_ACL_DEBUG
+//#define GARUDA_SW_ENTRY
+//#define GARUDA_ENTRY_DUMP
+
+typedef struct
+{
+ a_uint32_t list_id;
+ a_uint32_t list_pri;
+ a_uint32_t addr;
+ a_uint32_t size;
+ a_uint32_t status;
+ fal_pbmp_t bind_pts;
+} garuda_acl_list_t;
+
+typedef struct
+{
+ a_uint32_t slct[8];
+ a_uint32_t vlu[5];
+ a_uint32_t msk[5];
+ a_uint32_t typ;
+ a_uint32_t act;
+} garuda_acl_hw_rule_t;
+
+static garuda_acl_list_t *list_ent[SW_MAX_NR_DEV];
+static garuda_acl_hw_rule_t *hw_rule_ent;
+
+static a_uint32_t filter[SW_MAX_NR_DEV];
+static a_uint32_t filter_snap[SW_MAX_NR_DEV];
+
+#define GARUDA_MAX_LIST 32
+#define GARUDA_MAX_RULE 32
+
+#define ENT_FREE 0x1
+#define ENT_USED 0x2
+
+#define GARUDA_RULE_VLU_ADDR 0x58400
+#define GARUDA_RULE_MSK_ADDR 0x58c00
+#define GARUDA_RULE_TYP_ADDR 0x5881c
+#define GARUDA_RULE_ACT_ADDR 0x58000
+#define GARUDA_RULE_SLCT_ADDR 0x58800
+
+#define GARUDA_MAC_FILTER 1
+#define GARUDA_IP4_FILTER 2
+#define GARUDA_IP6R1_FILTER 3
+#define GARUDA_IP6R2_FILTER 4
+#define GARUDA_IP6R3_FILTER 5
+
+#ifdef GARUDA_SW_ENTRY
+static char *flt_vlu_mem = NULL;
+static char *flt_msk_mem = NULL;
+static char *flt_typ_mem = NULL;
+static char *act_mem = NULL;
+static char *slct_mem = NULL;
+#endif
+
+static a_bool_t _garuda_acl_zero_addr(const fal_mac_addr_t addr);
+
+static a_bool_t
+_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu);
+
+static sw_error_t
+_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx);
+
+static sw_error_t
+_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx[], a_uint32_t * flt_nr);
+
+static sw_error_t
+_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len);
+
+static sw_error_t
+_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw);
+
+static sw_error_t
+_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx);
+
+static void
+_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx);
+
+static void
+_garuda_acl_filter_snap(a_uint32_t dev_id);
+
+static void
+_garuda_acl_filter_commit(a_uint32_t dev_id);
+
+static sw_error_t
+_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t act_idx);
+
+static sw_error_t
+_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx);
+
+static sw_error_t
+_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t act_idx);
+
+static sw_error_t
+_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx);
+
+static sw_error_t
+_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+ const garuda_acl_hw_rule_t * hw_rule_ent,
+ a_uint32_t rule_nr);
+
+static sw_error_t
+_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t * ent_idx, a_uint32_t rule_idx);
+
+static sw_error_t
+_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw,
+ a_uint32_t * idx, a_uint32_t * flt_len);
+
+static sw_error_t
+_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw,
+ a_uint32_t ent_idx, a_uint32_t ent_nr);
+
+static sw_error_t
+_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+ a_uint32_t dst_slct_idx, a_uint32_t size);
+
+static sw_error_t
+_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+ a_uint32_t size);
+
+static sw_error_t
+_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+ a_uint32_t flag);
+
+static sw_error_t
+_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t list_id);
+
+static sw_error_t
+_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports);
+
+#ifdef GARUDA_ACL_DEBUG
+static void
+_garuda_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+
+ aos_printk("\ndev_id=%d list control infomation", dev_id);
+ for (i = 0; i < GARUDA_MAX_LIST; i++)
+ {
+ if (ENT_USED == list_ent[dev_id][i].status)
+ {
+ aos_printk("\nlist_id=%d list_pri=%d addr=%d size=%d idx=%d ",
+ list_ent[dev_id][i].list_id,
+ list_ent[dev_id][i].list_pri,
+ list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i);
+ }
+ }
+ aos_printk("\n");
+}
+#else
+#define _garuda_acl_list_dump(dev_id)
+#endif
+
+static a_bool_t
+_garuda_acl_zero_addr(const fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+ return A_TRUE;
+}
+
+static a_bool_t
+_garuda_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu)
+{
+ if (FAL_ACL_FIELD_MASK == op)
+ {
+ if (0 == mask)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_RANGE == op)
+ {
+ if ((0 == val) && (chkvlu == mask))
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_LE == op)
+ {
+ if (chkvlu == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_GE == op)
+ {
+ if (0 == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_NE == op)
+ {
+ return A_TRUE;
+ }
+
+ return A_TRUE;
+}
+
+static sw_error_t
+_garuda_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < GARUDA_MAX_LIST; i++)
+ {
+ if ((ENT_USED == list_ent[dev_id][i].status)
+ && (list_id == list_ent[dev_id][i].list_id))
+ {
+ *idx = i;
+ return SW_OK;
+ }
+ }
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_garuda_acl_filter_map_get(const garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx[], a_uint32_t * flt_nr)
+{
+ a_uint32_t flt_en, idx, i = 0;
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ *flt_nr = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_mac_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ *len = 0;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, bind_pts, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_MAC_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _garuda_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ *len = 6;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+ hw->vlu[1]);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+ hw->msk[1]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _garuda_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ *len = 12;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+ hw->vlu[2]);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 14;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ if (0x0 != sw->tagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tagged_val &= sw->tagged_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ if (0x0 != sw->up_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->up_val &= sw->up_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+ && (FAL_ACL_FIELD_LE != sw->vid_op)
+ && (FAL_ACL_FIELD_GE != sw->vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->vid_op)
+ {
+ sw->vid_val &= sw->vid_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VIDMSK, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->vid_op)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]);
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip4_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len)
+{
+ *b_care = A_FALSE;
+ *len = 0;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_V4, IP4_INPT, bind_pts, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP4_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 16;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 24;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask,
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+ {
+ if (0x0 != sw->src_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 30;
+ }
+ sw->src_ip4_val &= sw->src_ip4_mask;
+ hw->vlu[1] = sw->src_ip4_val;
+ hw->msk[1] = sw->src_ip4_mask;
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+ {
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 34;
+ }
+ sw->dest_ip4_val &= sw->dest_ip4_mask;
+ hw->vlu[0] = sw->dest_ip4_val;
+ hw->msk[0] = sw->dest_ip4_mask;
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ *b_care = A_TRUE;
+ *len = 36;
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val,
+ hw->msk[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ *b_care = A_TRUE;
+ *len = 38;
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val,
+ hw->msk[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]);
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ *len = 0;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+ SW_SET_REG_BY_FIELD(IP6_RUL1_V4, IP6_RUL1_INPT, bind_pts, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R1_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ *len = 54;
+ }
+
+ sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ *len = 0;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+ SW_SET_REG_BY_FIELD(IP6_RUL2_V4, IP6_RUL2_INPT, bind_pts, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R2_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ *len = 38;
+ }
+
+ sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_parse(fal_acl_rule_t * sw, fal_pbmp_t bind_pts,
+ garuda_acl_hw_rule_t * hw, a_bool_t * b_care,
+ a_uint32_t * len)
+{
+ *b_care = A_FALSE;
+ *len = 0;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V4, IP6_RUL3_INPT, bind_pts, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(RUL_TYPE, TYP, GARUDA_IP6R3_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 38;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask,
+ hw->msk[0]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+ {
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 18;
+ }
+
+ sw->ip6_lable_val &= sw->ip6_lable_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val,
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+ hw->msk[1]);
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16),
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16),
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ *len = 21;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val,
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask,
+ hw->msk[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ *b_care = A_TRUE;
+ *len = 56;
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[1]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, 0, hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_val,
+ hw->msk[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6SPORTM, 0xffff, hw->msk[1]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ *b_care = A_TRUE;
+ *len = 58;
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[0]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, 0, hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_val,
+ hw->msk[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DPORTM, 0xffff, hw->msk[0]);
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ garuda_acl_hw_rule_t * hw)
+{
+ hw->act = 0;
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ /* FAL_ACL_ACTION_PERMIT need't process */
+
+ /* we should ignore any other action flags when DENY bit is settd. */
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, 0, hw->act);
+ return SW_OK;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, RDTCPU, 1, hw->act);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, CPYCPU, 1, hw->act);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, MIRR_EN, 1, hw->act);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, DES_PORT_EN, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_DOT1P, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, DOT1P, sw->up, hw->act);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, REMARK_PRI_QU, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, PRI_QU, sw->queue, hw->act);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+
+ SW_SET_REG_BY_FIELD(ACL_RSLT, CHG_VID_EN, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, VID, sw->vid, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 1, hw->act);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, STAG_CHG_EN, 0, hw->act);
+
+ if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT, VID_MEM_EN, 1, hw->act);
+ SW_SET_REG_BY_FIELD(ACL_RSLT, PORT_MEM, sw->ports, hw->act);
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+
+ /* destnation mac address */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+ hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+ hw->vlu[1]);
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+ hw->msk[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+ hw->msk[1]);
+ if (A_FALSE == _garuda_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ /* source mac address */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+ hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+ hw->vlu[1]);
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+ hw->msk[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+ hw->msk[1]);
+ if (A_FALSE == _garuda_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ /* ethernet type */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet tagged */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+ if (0x0 != sw->tagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+ }
+
+ /* vlan priority */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+ if (0x0 != sw->up_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+ }
+
+ /* vlanid */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VIDMSK, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+ (a_uint32_t) sw->vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+
+ sw->dest_ip4_val = hw->vlu[0];
+ sw->dest_ip4_mask = hw->msk[0];
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+
+ sw->src_ip4_val = hw->vlu[1];
+ sw->src_ip4_mask = hw->msk[1];
+ if (0x0 != sw->src_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+ a_uint32_t tmp;
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6SPORTV, sw->src_l4port_val, hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[1]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _garuda_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+ hw->msk[1]);
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]);
+ sw->ip6_lable_val |= (tmp << 16);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]);
+ sw->ip6_lable_mask |= (tmp << 16);
+
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_action_reparse(fal_acl_rule_t * sw,
+ const garuda_acl_hw_rule_t * hw)
+{
+ a_uint32_t data;
+
+ sw->action_flg = 0;
+ SW_GET_FIELD_BY_REG(ACL_RSLT, DES_PORT_EN, data, (hw->act));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act));
+ sw->ports = data;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, RDTCPU, data, (hw->act));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, CPYCPU, data, (hw->act));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, MIRR_EN, data, (hw->act));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_DOT1P, data, (hw->act));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT, DOT1P, data, (hw->act));
+ sw->up = data & 0x7;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, REMARK_PRI_QU, data, (hw->act));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT, PRI_QU, data, (hw->act));
+ sw->queue = data & 0x3;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, CHG_VID_EN, data, (hw->act));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT, STAG_CHG_EN, data, (hw->act));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN);
+ }
+ else
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN);
+ SW_GET_FIELD_BY_REG(ACL_RSLT, PORT_MEM, data, (hw->act));
+ sw->ports = data;
+ }
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT, VID, data, (hw->act));
+ sw->vid = data & 0xfff;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < GARUDA_MAX_RULE; i++)
+ {
+ if (0 == (filter_snap[dev_id] & (0x1UL << i)))
+ {
+ filter_snap[dev_id] |= (0x1UL << i);
+ *idx = i;
+ return SW_OK;
+ }
+ }
+ return SW_NO_RESOURCE;
+}
+
+static void
+_garuda_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx)
+{
+ filter_snap[dev_id] &= (~(0x1UL << idx));
+}
+
+static void
+_garuda_acl_filter_snap(a_uint32_t dev_id)
+{
+ filter_snap[dev_id] = filter[dev_id];
+ return;
+}
+
+static void
+_garuda_acl_filter_commit(a_uint32_t dev_id)
+{
+ filter[dev_id] = filter_snap[dev_id];
+ return;
+}
+
+static sw_error_t
+_garuda_acl_slct_update(garuda_acl_hw_rule_t * hw, a_uint32_t offset,
+ a_uint32_t flt_idx)
+{
+ switch (offset)
+ {
+ case 0:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]);
+ break;
+
+ case 1:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]);
+ break;
+
+ case 2:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]);
+ break;
+
+ case 3:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]);
+ break;
+
+ default:
+ return SW_FAIL;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+ a_uint32_t i;
+
+ memaddr = flt_vlu_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), 20);
+
+ memaddr = flt_msk_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->msk[0]), 20);
+
+ memaddr = flt_typ_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->typ), 4);
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* set filter value */
+ base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter mask */
+ base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter type */
+ addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_filter_write flt_idx = %d\n", flt_idx);
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", rule->vlu[i]);
+ }
+ aos_printk("\n");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", rule->msk[i]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t act_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = act_mem + (act_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->act), 4);
+
+#else
+ sw_error_t rv;
+ a_uint32_t addr;
+
+ /* set rule action */
+ addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_action_write act_idx = %d ", act_idx);
+ aos_printk("%08x ", rule->act);
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_slct_write(a_uint32_t dev_id, const garuda_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+ a_uint32_t i;
+
+ memaddr = slct_mem + (slct_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->slct[0]), 32);
+
+#else
+ sw_error_t rv;
+ a_uint32_t base, addr;
+ a_uint32_t i;
+
+ base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* set filter length */
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, (base + 24), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[6])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set filter address */
+ for (i = 1; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter enable */
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_slct_write slct_idx = %d\n", slct_idx);
+ for (i = 0; i < 8; i++)
+ {
+ aos_printk("%08x ", rule->slct[i]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_filter_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+ a_uint32_t i;
+
+ memaddr = flt_vlu_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20);
+
+ memaddr = flt_msk_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20);
+
+ memaddr = flt_typ_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->typ), memaddr, 4);
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* get filter value */
+ base = GARUDA_RULE_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get filter mask */
+ base = GARUDA_RULE_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get filter type */
+ addr = GARUDA_RULE_TYP_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_filter_read flt_idx = %d\n", flt_idx);
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", rule->vlu[i]);
+ }
+ aos_printk("\n");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", rule->msk[i]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_action_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t act_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = act_mem + (act_idx << 5);
+ aos_mem_copy((char *) &(rule->act), memaddr, 4);
+
+#else
+ sw_error_t rv;
+ a_uint32_t addr;
+
+ /* get rule action */
+ addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->act)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_action_read act_idx = %d ", act_idx);
+ aos_printk("%08x ", rule->act);
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_slct_read(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx)
+{
+#ifdef GARUDA_SW_ENTRY
+ char *memaddr;
+ a_uint32_t i;
+
+ memaddr = slct_mem + (slct_idx << 5);
+ aos_mem_copy((char *) &(rule->slct[0]), memaddr, 32);
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* get filter type */
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 28), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[7])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter length */
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, (base + 24), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[6])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter address and enable */
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#endif
+
+#ifdef GARUDA_ENTRY_DUMP
+ aos_printk("\n_garuda_acl_slct_read slct_idx = %d\n", slct_idx);
+ for (i = 0; i < 8; i++)
+ {
+ aos_printk("%08x ", rule->slct[i]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+ const garuda_acl_hw_rule_t * rule, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ a_uint32_t ent_idx, tmp_ent_idx;
+ a_uint32_t i, flt_nr, flt_idx[4];
+ a_uint32_t act_idx, slct_idx;
+
+ act_idx = base_addr;
+ slct_idx = base_addr;
+ ent_idx = 0;
+ for (i = 0; i < rule_nr; i++)
+ {
+ tmp_ent_idx = ent_idx;
+
+ rv = _garuda_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!flt_nr)
+ {
+ return SW_FAIL;
+ }
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _garuda_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]);
+ ent_idx++;
+ }
+
+ rv = _garuda_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ act_idx++;
+ slct_idx++;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_get(a_uint32_t dev_id, garuda_acl_hw_rule_t * rule,
+ a_uint32_t * ent_idx, a_uint32_t rule_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, tmp_idx, flt_nr, flt_idx[4];
+
+ tmp_idx = *ent_idx;
+
+ rv = _garuda_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_action_read(dev_id, &rule[tmp_idx], rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _garuda_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]);
+ SW_RTN_ON_ERROR(rv);
+
+ tmp_idx++;
+ }
+
+ *ent_idx = tmp_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ fal_pbmp_t bind_pts, garuda_acl_hw_rule_t * hw,
+ a_uint32_t * idx, a_uint32_t * flt_len)
+{
+ sw_error_t rv;
+ a_bool_t b_care;
+ a_bool_t b_valid = A_FALSE;
+ a_uint32_t tmp_idx;
+ a_uint32_t len1 = 0, len2 = 0, len3 = 0, maxlen = 0;
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ tmp_idx = *idx;
+ if (FAL_ACL_RULE_MAC == sw->rule_type)
+ {
+ rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len1);
+ SW_RTN_ON_ERROR(rv);
+ tmp_idx++;
+
+ if (0 == len1)
+ {
+ *flt_len = 14;
+ }
+ else
+ {
+ *flt_len = len1;
+ }
+ }
+ else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len1);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _garuda_acl_rule_ip4_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len1);
+ SW_RTN_ON_ERROR(rv);
+ tmp_idx++;
+
+ if (0 == len1)
+ {
+ *flt_len = 34;
+ }
+ else
+ {
+ *flt_len = len1;
+ }
+ }
+ else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ rv = _garuda_acl_rule_mac_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len1);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _garuda_acl_rule_ip6r1_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len1);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_valid = A_TRUE;
+ }
+
+ rv = _garuda_acl_rule_ip6r2_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len2);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_valid = A_TRUE;
+ }
+
+ rv = _garuda_acl_rule_ip6r3_parse(sw, bind_pts, &hw[tmp_idx], &b_care,
+ &len3);
+ SW_RTN_ON_ERROR(rv);
+ if ((A_TRUE == b_care) || (A_FALSE == b_valid))
+ {
+ tmp_idx++;
+ }
+
+ if (len1 >= len2)
+ {
+ if (len1 >= len3)
+ {
+ maxlen = len1;
+ }
+ else
+ {
+ maxlen = len3;
+ }
+ }
+ else
+ {
+ if (len2 >= len3)
+ {
+ maxlen = len2;
+ }
+ else
+ {
+ maxlen = len3;
+ }
+ }
+
+ if (0 == maxlen)
+ {
+ *flt_len = 54;
+ }
+ else
+ {
+ *flt_len = maxlen;
+ }
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _garuda_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx]));
+ SW_RTN_ON_ERROR(rv);
+
+ *idx = tmp_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const garuda_acl_hw_rule_t * hw,
+ a_uint32_t ent_idx, a_uint32_t ent_nr)
+{
+ sw_error_t rv;
+ a_uint32_t i, flt_typ;
+ a_bool_t b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+
+ rv = _garuda_acl_rule_action_reparse(sw, &hw[ent_idx]);
+ SW_RTN_ON_ERROR(rv);
+
+ sw->rule_type = FAL_ACL_RULE_MAC;
+ for (i = 0; i < ent_nr; i++)
+ {
+ SW_GET_FIELD_BY_REG(RUL_TYPE, TYP, flt_typ, hw[ent_idx + i].typ);
+
+ if (GARUDA_MAC_FILTER == flt_typ)
+ {
+ rv = _garuda_acl_rule_mac_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (GARUDA_IP4_FILTER == flt_typ)
+ {
+ rv = _garuda_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip4 = A_TRUE;
+ }
+ else if (GARUDA_IP6R1_FILTER == flt_typ)
+ {
+ rv = _garuda_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (GARUDA_IP6R2_FILTER == flt_typ)
+ {
+ rv = _garuda_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (GARUDA_IP6R3_FILTER == flt_typ)
+ {
+ rv = _garuda_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ if (A_TRUE == b_ip4)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP4;
+ }
+
+ if (A_TRUE == b_ip6)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP6;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+ a_uint32_t dst_slct_idx, a_uint32_t size)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ a_int32_t step, src_idx, dst_idx;
+ garuda_acl_hw_rule_t rule;
+
+ if (dst_slct_idx <= src_slct_idx)
+ {
+ src_idx = src_slct_idx & 0x7fffffff;
+ dst_idx = dst_slct_idx & 0x7fffffff;
+ step = 1;
+ }
+ else
+ {
+ src_idx = (src_slct_idx + size - 1) & 0x7fffffff;
+ dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff;
+ step = -1;
+ }
+
+ aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+ for (i = 0; i < size; i++)
+ {
+ rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ src_idx += step;
+ dst_idx += step;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+ a_uint32_t size)
+{
+ sw_error_t rv;
+ a_uint32_t base, flag, i;
+
+ flag = 0;
+ for (i = 0; i < size; i++)
+ {
+ base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+ a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t base, i;
+
+ for (i = 0; i < size; i++)
+ {
+ base = GARUDA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t list_id)
+{
+ sw_error_t rv;
+ a_uint32_t idx;
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (old_addr != list_ent[dev_id][idx].addr)
+ {
+ return SW_FAIL;
+ }
+
+ list_ent[dev_id][idx].addr = new_addr;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports)
+{
+ sw_error_t rv;
+ a_uint32_t flt_idx[4], flt_nr;
+ a_uint32_t bind_pts = 0, addr, i, ret = 0;
+ garuda_acl_hw_rule_t rule;
+
+ aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+
+ rv = _garuda_acl_slct_read(dev_id, &rule, rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_rule_invalid(dev_id, rule_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ addr = GARUDA_RULE_VLU_ADDR + (flt_idx[i] << 5) + 16;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t));
+
+ /* source port field in different type rules has the same
+ hardware bit position */
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, MAC_INPT, ports, bind_pts);
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&bind_pts), sizeof (a_uint32_t));
+ ret += rv;
+ }
+
+ rv = _garuda_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]);
+ ret += rv;
+ if (0 != ret)
+ {
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri)
+{
+ a_uint32_t i, loc = GARUDA_MAX_LIST;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ for (i = 0; i < GARUDA_MAX_LIST; i++)
+ {
+ if ((ENT_USED == list_ent[dev_id][i].status)
+ && (list_id == list_ent[dev_id][i].list_id))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ if (ENT_FREE == list_ent[dev_id][i].status)
+ {
+ loc = i;
+ }
+ }
+
+ if (GARUDA_MAX_LIST == loc)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (garuda_acl_list_t));
+ list_ent[dev_id][loc].list_id = list_id;
+ list_ent[dev_id][loc].list_pri = list_pri;
+ list_ent[dev_id][loc].status = ENT_USED;
+ _garuda_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ a_uint32_t list_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ for (list_idx = 0; list_idx < GARUDA_MAX_LIST; list_idx++)
+ {
+ if ((ENT_USED == list_ent[dev_id][list_idx].status)
+ && (list_id == list_ent[dev_id][list_idx].list_id))
+ {
+ break;
+ }
+ }
+
+ if (list_idx >= GARUDA_MAX_LIST)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (0 != list_ent[dev_id][list_idx].bind_pts)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (0 != list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (garuda_acl_list_t));
+ list_ent[dev_id][list_idx].status = ENT_FREE;
+ _garuda_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ a_uint32_t hsl_f_rsc, list_new_size, list_addr;
+ a_uint32_t list_pri, list_idx, load_addr, bind_pts;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((0 == rule_nr) || (NULL == rule))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc);
+ SW_RTN_ON_ERROR(rv);
+ if (hsl_f_rsc < rule_nr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (rule_id != list_ent[dev_id][list_idx].size)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ bind_pts = list_ent[dev_id][list_idx].bind_pts;
+
+ _garuda_acl_filter_snap(dev_id);
+
+ /* parse rule entry and alloc rule resource */
+ {
+ a_uint32_t i, j;
+ a_uint32_t ent_idx, tmp_ent_idx, flt_idx, flt_len;
+
+ aos_mem_zero(hw_rule_ent,
+ GARUDA_MAX_RULE * sizeof (garuda_acl_hw_rule_t));
+
+ ent_idx = 0;
+ for (i = 0; i < rule_nr; i++)
+ {
+ tmp_ent_idx = ent_idx;
+ rv = _garuda_acl_rule_sw_to_hw(dev_id, &rule[i], bind_pts,
+ &hw_rule_ent[ent_idx], &ent_idx,
+ &flt_len);
+ SW_RTN_ON_ERROR(rv);
+
+ for (j = tmp_ent_idx; j < ent_idx; j++)
+ {
+ rv = _garuda_acl_filter_alloc(dev_id, &flt_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_slct_update(&hw_rule_ent[tmp_ent_idx],
+ j - tmp_ent_idx, flt_idx);
+ SW_RTN_ON_ERROR(rv);
+ }
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, flt_len,
+ hw_rule_ent[tmp_ent_idx].slct[6]);
+ }
+ }
+
+ /* alloc hardware select entry resource */
+ if (0 == list_ent[dev_id][list_idx].size)
+ {
+ list_new_size = rule_nr;
+ list_pri = list_ent[dev_id][list_idx].list_pri;
+
+ rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id,
+ &list_addr);
+ SW_RTN_ON_ERROR(rv);
+
+ load_addr = list_addr;
+ }
+ else
+ {
+ list_new_size = list_ent[dev_id][list_idx].size + rule_nr;
+ list_addr = list_ent[dev_id][list_idx].addr;
+
+ rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size);
+ SW_RTN_ON_ERROR(rv);
+
+ /* must be careful resize opration maybe change list base address */
+ list_addr = list_ent[dev_id][list_idx].addr;
+ load_addr = list_ent[dev_id][list_idx].size + list_addr;
+ }
+
+ /* load acl rule to hardware */
+ rv = _garuda_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr);
+ if (SW_OK != rv)
+ {
+ (void) hsl_acl_blk_resize(dev_id, list_addr,
+ list_ent[dev_id][list_idx].size);
+ return rv;
+ }
+
+ /* update software list control information */
+ list_ent[dev_id][list_idx].size = list_new_size;
+ list_ent[dev_id][list_idx].addr = list_addr;
+
+ /* update hardware acl rule resource information */
+ _garuda_acl_filter_commit(dev_id);
+ _garuda_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ a_uint32_t flt_idx[4];
+ a_uint32_t i, j, flt_nr;
+ a_uint32_t list_idx, addr, size, rule_idx, cnt;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == rule_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ _garuda_acl_filter_snap(dev_id);
+
+ /* free hardware filter resource */
+ addr = list_ent[dev_id][list_idx].addr + rule_id;
+ for (i = 0; i < rule_nr; i++)
+ {
+ rv = _garuda_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ for (j = 0; j < flt_nr; j++)
+ {
+ _garuda_acl_filter_free(dev_id, flt_idx[j]);
+ }
+ }
+
+ cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr);
+ rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr);
+ rv = _garuda_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = list_ent[dev_id][list_idx].addr;
+ size = list_ent[dev_id][list_idx].size;
+ rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ list_ent[dev_id][list_idx].size -= rule_nr;
+ _garuda_acl_filter_commit(dev_id);
+ _garuda_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (rule_id >= list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+
+ ent_idx = 0;
+ tmp_ent_idx = 0;
+ rule_idx = list_ent[dev_id][list_idx].addr + rule_id;
+ rv = _garuda_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _garuda_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx,
+ tmp_ent_idx - ent_idx);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, list_idx, rule_idx, base, ports;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ base = list_ent[dev_id][list_idx].addr;
+ ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx);
+ for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+ {
+ rule_idx = base + i;
+ rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ list_ent[dev_id][list_idx].bind_pts = ports;
+ return SW_OK;
+}
+
+
+
+static sw_error_t
+_garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, list_idx, rule_idx, base, ports;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _garuda_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ base = list_ent[dev_id][list_idx].addr;
+ ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx));
+ for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+ {
+ rule_idx = base + i;
+ rv = _garuda_acl_rule_bind(dev_id, rule_idx, ports);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ list_ent[dev_id][list_idx].bind_pts = ports;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+garuda_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t idx;
+
+ aos_printk("\ngaruda_acl_list_dump:\n");
+ for (idx = 0; idx < GARUDA_MAX_LIST; idx++)
+ {
+ if (ENT_USED == list_ent[dev_id][idx].status)
+ {
+ aos_printk
+ ("\n[id]:%02d [pri]:%02d [size]:%02d [addr]:%02d [pts_map]:0x%02x",
+ list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri,
+ list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr,
+ list_ent[dev_id][idx].bind_pts);
+ }
+ }
+ aos_printk("\n");
+
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+garuda_acl_rule_dump(a_uint32_t dev_id)
+{
+ a_uint32_t slt_idx, flt_nr, i, j;
+ a_uint32_t flt_idx[4];
+ sw_error_t rv;
+ garuda_acl_hw_rule_t rule;
+
+ aos_printk("\ngaruda_acl_rule_dump:\n");
+
+ aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]);
+ for (slt_idx = 0; slt_idx < GARUDA_MAX_RULE; slt_idx++)
+ {
+ aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+
+ rv = _garuda_acl_slct_read(dev_id, &rule, slt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ rv = _garuda_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\nslct_idx=%d ", slt_idx);
+ for (i = 0; i < flt_nr; i++)
+ {
+ aos_printk("flt%d_idx=%d ", i, flt_idx[i]);
+ }
+
+ aos_printk("\nslt:");
+ for (i = 0; i < 8; i++)
+ {
+ aos_printk("%08x ", rule.slct[i]);
+ }
+
+ if (flt_nr)
+ {
+ rv = _garuda_acl_action_read(dev_id, &rule, slt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+ aos_printk("\nact:%08x ", rule.act);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _garuda_acl_filter_read(dev_id, &rule, flt_idx[i]);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\ntyp:%08x ", rule.typ);
+ aos_printk("\nvlu:");
+ for (j = 0; j < 5; j++)
+ {
+ aos_printk("%08x ", rule.vlu[j]);
+ }
+
+ aos_printk("\nmsk:");
+ for (j = 0; j < 5; j++)
+ {
+ aos_printk("%08x ", rule.msk[j]);
+ }
+ aos_printk("\n");
+ }
+ }
+ aos_printk("\n");
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_zero(hw_rule_ent,
+ (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t));
+
+ aos_mem_zero(list_ent[dev_id],
+ GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+
+ for (i = 0; i < GARUDA_MAX_LIST; i++)
+ {
+ list_ent[dev_id][i].status = ENT_FREE;
+ }
+
+ filter[dev_id] = 0;
+ filter_snap[dev_id] = 0;
+
+ rv = hsl_acl_pool_destroy(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details Comments:
+ * If the priority of a list is more small then the priority is more high,
+ * that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_list_creat(dev_id, list_id, list_pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_list_destroy(dev_id, list_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_rule_query(dev_id, list_id, rule_id, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_acl_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_acl_init(a_uint32_t dev_id)
+{
+ static a_bool_t b_hw_rule = A_FALSE;
+ hsl_acl_func_t *acl_func;
+ garuda_acl_hw_rule_t rule;
+ sw_error_t rv;
+ a_uint32_t i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == b_hw_rule)
+ {
+ hw_rule_ent = (garuda_acl_hw_rule_t *)
+ aos_mem_alloc((GARUDA_MAX_RULE +
+ 3) * sizeof (garuda_acl_hw_rule_t));
+ if (NULL == hw_rule_ent)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(hw_rule_ent,
+ (GARUDA_MAX_RULE + 3) * sizeof (garuda_acl_hw_rule_t));
+ b_hw_rule = A_TRUE;
+ }
+
+ list_ent[dev_id] = (garuda_acl_list_t *)
+ aos_mem_alloc(GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+ if (NULL == list_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(list_ent[dev_id],
+ GARUDA_MAX_LIST * sizeof (garuda_acl_list_t));
+
+ for (i = 0; i < GARUDA_MAX_LIST; i++)
+ {
+ list_ent[dev_id][i].status = ENT_FREE;
+ }
+
+ filter[dev_id] = 0;
+ filter_snap[dev_id] = 0;
+
+ rv = hsl_acl_pool_creat(dev_id, GARUDA_MAX_LIST, GARUDA_MAX_RULE);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_func = hsl_acl_ptr_get(dev_id);
+ SW_RTN_ON_NULL(acl_func);
+
+ acl_func->acl_rule_copy = _garuda_acl_rule_copy;
+ acl_func->acl_rule_invalid = _garuda_acl_rule_invalid;
+ acl_func->acl_addr_update = _garuda_acl_addr_update;
+
+ /* zero acl hardware memory */
+ aos_mem_zero(&rule, sizeof (garuda_acl_hw_rule_t));
+ for (i = 0; i < GARUDA_MAX_RULE; i++)
+ {
+ rv = _garuda_acl_slct_write(dev_id, &rule, i);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+#ifdef GARUDA_SW_ENTRY
+ flt_vlu_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+ if (NULL == flt_vlu_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_vlu_mem, GARUDA_MAX_RULE * 32);
+
+ flt_msk_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+ if (NULL == flt_msk_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_msk_mem, GARUDA_MAX_RULE * 32);
+
+ flt_typ_mem = aos_mem_alloc(GARUDA_MAX_RULE * 4);
+ if (NULL == flt_typ_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_typ_mem, GARUDA_MAX_RULE * 4);
+
+ act_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+ if (NULL == act_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(act_mem, GARUDA_MAX_RULE * 32);
+
+ slct_mem = aos_mem_alloc(GARUDA_MAX_RULE * 32);
+ if (NULL == slct_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(slct_mem, GARUDA_MAX_RULE * 32);
+#endif
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->acl_list_creat = garuda_acl_list_creat;
+ p_api->acl_list_destroy = garuda_acl_list_destroy;
+ p_api->acl_list_bind = garuda_acl_list_bind;
+ p_api->acl_list_unbind = garuda_acl_list_unbind;
+ p_api->acl_rule_add = garuda_acl_rule_add;
+ p_api->acl_rule_delete = garuda_acl_rule_delete;
+ p_api->acl_rule_query = garuda_acl_rule_query;
+ p_api->acl_status_set = garuda_acl_status_set;
+ p_api->acl_status_get = garuda_acl_status_get;
+ p_api->acl_list_dump = garuda_acl_list_dump;
+ p_api->acl_rule_dump = garuda_acl_rule_dump;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_fdb.c b/src/hsl/garuda/garuda_fdb.c
new file mode 100644
index 0000000..51eac61
--- /dev/null
+++ b/src/hsl/garuda/garuda_fdb.c
@@ -0,0 +1,998 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_fdb GARUDA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_fdb.h"
+#include "garuda_reg.h"
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+#define ARL_FIND_ENTRY 7
+
+#define ARL_FIRST_ENTRY 1001
+#define ARL_FLUSH_PORT_NO_STATIC 1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+garuda_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+garuda_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+garuda_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->clone_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ hsl_dev_t *p_dev;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+ if (entry->da_queue > (p_dev->nr_queue - 1))
+ return SW_BAD_PARAM;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+ garuda_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ return SW_OK;
+}
+
+static void
+garuda_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->clone_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->clone_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x3;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 0; i < 4; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+ }
+
+ for (i = 4; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+ }
+
+ return;
+}
+
+static sw_error_t
+garuda_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 1000;
+ a_uint32_t entry;
+ a_uint32_t hwop = op;
+
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_BUSY;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+ if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+ }
+
+ if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 1000;
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+ (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (full_vio)
+ {
+ /* must clear AT_FULL_VOI bit */
+ entry = 0x1000;
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ARL_LOAD_ENTRY == hwop)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == hwop)
+ || (ARL_FLUSH_PORT_UNICAST == hwop))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+garuda_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0 };
+ a_uint32_t status = 0;
+ a_uint32_t hwop = op;
+
+ if ((ARL_NEXT_ENTRY == op)
+ || (ARL_FIND_ENTRY == op))
+ {
+ garuda_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set status not zero */
+ if (ARL_NEXT_ENTRY == op)
+ {
+ reg[2] = 0xf0000;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ /* get hardware enrety */
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+ garuda_atu_hw_to_sw(reg, entry);
+
+ /* If hardware return back with address and status all zero,
+ that means no other next valid entry in fdb table */
+ if ((A_TRUE == garuda_fdb_is_zeroaddr(entry->addr))
+ && (0 == status))
+ {
+ if (ARL_NEXT_ENTRY == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if ((ARL_FIND_ENTRY == op)
+ || (ARL_FIRST_ENTRY == op))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0, 0, 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = garuda_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = garuda_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+ }
+ else
+ {
+ rv = garuda_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+ }
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ garuda_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = garuda_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = garuda_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = garuda_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((65535 * 7 < *time) || (7 > *time))
+ {
+ return SW_BAD_PARAM;
+ }
+ data = *time / 7;
+ *time = data * 7;
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 7;
+ return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ * @details Comments:
+ * For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_next(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_first(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_port_learn_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_port_learn_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_age_ctrl_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_age_ctrl_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_fdb_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = garuda_fdb_add;
+ p_api->fdb_del_all = garuda_fdb_del_all;
+ p_api->fdb_del_by_port = garuda_fdb_del_by_port;
+ p_api->fdb_del_by_mac = garuda_fdb_del_by_mac;
+ p_api->fdb_first = garuda_fdb_first;
+ p_api->fdb_next = garuda_fdb_next;
+ p_api->fdb_find = garuda_fdb_find;
+ p_api->port_learn_set = garuda_fdb_port_learn_set;
+ p_api->port_learn_get = garuda_fdb_port_learn_get;
+ p_api->age_ctrl_set = garuda_fdb_age_ctrl_set;
+ p_api->age_ctrl_get = garuda_fdb_age_ctrl_get;
+ p_api->age_time_set = garuda_fdb_age_time_set;
+ p_api->age_time_get = garuda_fdb_age_time_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_igmp.c b/src/hsl/garuda/garuda_igmp.c
new file mode 100644
index 0000000..ef581ac
--- /dev/null
+++ b/src/hsl/garuda/garuda_igmp.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_igmp GARUDA_IGMP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_igmp.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+ {
+ return SW_BAD_PARAM;
+ }
+ val = pts;
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *pts = val;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmps_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmps_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmp_mld_join_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmp_mld_join_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp join feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmp_mld_leave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_igmp_mld_leave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_rp_set(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_rp_get(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_entry_creat_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_igmp_mld_entry_creat_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_igmp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_igmps_status_set = garuda_port_igmps_status_set;
+ p_api->port_igmps_status_get = garuda_port_igmps_status_get;
+ p_api->igmp_mld_cmd_set = garuda_igmp_mld_cmd_set;
+ p_api->igmp_mld_cmd_get = garuda_igmp_mld_cmd_get;
+ p_api->port_igmp_join_set = garuda_port_igmp_mld_join_set;
+ p_api->port_igmp_join_get = garuda_port_igmp_mld_join_get;
+ p_api->port_igmp_leave_set = garuda_port_igmp_mld_leave_set;
+ p_api->port_igmp_leave_get = garuda_port_igmp_mld_leave_get;
+ p_api->igmp_rp_set = garuda_igmp_mld_rp_set;
+ p_api->igmp_rp_get = garuda_igmp_mld_rp_get;
+ p_api->igmp_entry_creat_set = garuda_igmp_mld_entry_creat_set;
+ p_api->igmp_entry_creat_get = garuda_igmp_mld_entry_creat_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_init.c b/src/hsl/garuda/garuda_init.c
new file mode 100644
index 0000000..51ef79f
--- /dev/null
+++ b/src/hsl/garuda/garuda_init.c
@@ -0,0 +1,633 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_init GARUDA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mib.h"
+#include "garuda_port_ctrl.h"
+#include "garuda_portvlan.h"
+#include "garuda_vlan.h"
+#include "garuda_fdb.h"
+#include "garuda_qos.h"
+#include "garuda_mirror.h"
+#include "garuda_stp.h"
+#include "garuda_rate.h"
+#include "garuda_misc.h"
+#include "garuda_leaky.h"
+#include "garuda_igmp.h"
+#include "garuda_acl.h"
+#include "garuda_led.h"
+#include "garuda_reg_access.h"
+#include "garuda_reg.h"
+#include "garuda_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * garuda_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+garuda_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ if (HSL_CPU_1 != mode)
+ {
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != (pdev->nr_ports -1)))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port but exclude wan port in some cases */
+ if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ if ((port_id != pdev->cpu_port_nr)
+ && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static void
+phy_dport_set(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask)
+{
+ a_uint16_t phy_data;
+ sw_error_t rv;
+
+ HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr);
+ HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data);
+ phy_data |= val_mask;
+ HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+}
+
+static void
+phy_dport_clear(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t dport_addr, a_uint16_t val_mask)
+{
+ a_uint16_t phy_data;
+ sw_error_t rv;
+
+ HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, dport_addr);
+ HSL_PHY_GET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, &phy_data);
+ phy_data &= ~val_mask;
+ HSL_PHY_SET(rv, dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+}
+
+static sw_error_t
+garuda_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ garuda_init_spec_cfg *garuda_init_cfg = NULL;
+ hsl_dev_t *pdev = NULL;
+ hsl_init_mode cpu_mode;
+ a_uint32_t port_id;
+ a_uint32_t data;
+ sw_error_t rv;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (NULL == pdev)
+ {
+ return SW_NOT_INITIALIZED;
+ }
+ cpu_mode = cfg->cpu_mode;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, POSTRIP, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* phy pll on */
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY_PLL_ON, 1, data);
+
+ garuda_init_cfg = (garuda_init_spec_cfg* )(cfg->chip_spec_cfg);
+ if (!garuda_init_cfg)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* delay */
+ if (A_TRUE == garuda_init_cfg->rx_delay_s1)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S1, 0, data);
+ }
+
+ if (A_TRUE == garuda_init_cfg->rx_delay_s0)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RXDELAY_S0, 0, data);
+ }
+
+ if (A_TRUE == garuda_init_cfg->tx_delay_s1)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S1, 0, data);
+ }
+
+ if (A_TRUE == garuda_init_cfg->tx_delay_s0)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
+ }
+
+ /* tx/rx delay enable */
+ if (A_TRUE == garuda_init_cfg->rgmii_txclk_delay)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RGMII_TXCLK_DELAY_EN, 0, data);
+ }
+
+ /* tx/rx delay enable */
+ if (A_TRUE == garuda_init_cfg->rgmii_rxclk_delay)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, RGMII_RXCLK_DELAY_EN, 0, data);
+ }
+
+ /* mac5 default mode */
+ /*SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);*/
+
+ /* mac0 default phy mode */
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC0_MAC_MODE, 0, data);
+
+ /* mac0 default rgmii mode */
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 1, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 0, data);
+
+ /* mac5 default disable mode */
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC5_PHY_MODE, 0, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 0, data);
+
+ /* phy default mode */
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
+
+ /* modify default mode */
+ if (A_FALSE == garuda_init_cfg->mac0_rgmii)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC0_RGMII_EN, 0, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC0_GMII_EN, 1, data);
+
+ /*invert clock output for port0 gmii pad.*/
+ a_uint32_t temp;
+ HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (&temp), sizeof (a_uint32_t));
+ temp |= 1<<MASK_CTL_MII_CLK0_SEL_BOFFSET;
+ HSL_REG_ENTRY_SET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (&temp), sizeof (a_uint32_t));
+ }
+
+ if(HSL_CPU_2 == cpu_mode)
+ {
+ if (A_TRUE == garuda_init_cfg->mac5_rgmii)
+ {
+
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 1, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 0, data);
+
+ a_uint32_t phy_id = 4;
+ /* phy4 rgmii mode enable */
+ phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RGMII_MODE, F1_DEBUG_PORT_RGMII_MODE_EN);
+
+ /* Rx delay enable */
+ if (A_TRUE == garuda_init_cfg->phy4_rx_delay)
+ {
+ phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
+ }
+ else
+ {
+ phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_RX_DELAY, F1_DEBUG_PORT_RX_DELAY_EN);
+ }
+
+ /* Tx delay enable */
+ if (A_TRUE == garuda_init_cfg->phy4_tx_delay)
+ {
+ phy_dport_set(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
+ }
+ else
+ {
+ phy_dport_clear(dev_id, phy_id, F1_DEBUG_PORT_TX_DELAY, F1_DEBUG_PORT_TX_DELAY_EN);
+ }
+
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_RGMII_EN, 0, data);
+ SW_SET_REG_BY_FIELD(POSTRIP, PHY4_GMII_EN, 1, data);
+ }
+ }
+ else if (HSL_CPU_1 == cpu_mode)
+ {
+ //SW_SET_REG_BY_FIELD(POSTRIP, TXDELAY_S0, 0, data);
+
+ }
+ else if (HSL_CPU_1_PLUS == cpu_mode)
+ {
+ SW_SET_REG_BY_FIELD(POSTRIP, MAC5_MAC_MODE, 1, data);
+
+ }
+ else if (HSL_NO_CPU == cpu_mode)
+ {
+
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, POSTRIP, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (port_id == pdev->cpu_port_nr)
+ {
+ continue;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+garuda_bist_test(a_uint32_t dev_id)
+{
+ a_uint32_t entry, data, i;
+ sw_error_t rv;
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+ if (!data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ return SW_OK;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ return SW_OK;
+}
+
+
+#endif
+
+static sw_error_t
+garuda_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ pdev->nr_ports = 6;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 4;
+ pdev->cpu_mode = cpu_mode;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_hw_init(dev_id, garuda_cfg[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ GARUDA_ACL_RESET(rv, dev_id);
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_cleanup(a_uint32_t dev_id)
+{
+ if (garuda_cfg[dev_id])
+ {
+ aos_mem_free(garuda_cfg[dev_id]);
+ garuda_cfg[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ * This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ * This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+garuda_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ a_uint8_t *p_mem;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ p_mem = (a_uint8_t *)garuda_cfg[dev_id];
+ if (NULL == p_mem)
+ {
+ p_mem = aos_mem_alloc(sizeof (ssdk_init_cfg)
+ + sizeof(garuda_init_spec_cfg));
+ garuda_cfg[dev_id] = (ssdk_init_cfg *)p_mem;
+ garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
+ (p_mem + sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == p_mem)
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(garuda_cfg[dev_id]->chip_spec_cfg,
+ cfg->chip_spec_cfg, sizeof (garuda_init_spec_cfg));
+ aos_mem_copy(garuda_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+ garuda_cfg[dev_id]->chip_spec_cfg = (garuda_init_spec_cfg *)
+ (p_mem + sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(garuda_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(garuda_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ a_uint32_t i, entry;
+ sw_error_t rv;
+
+ if(HSL_MDIO == cfg->reg_mode)
+ {
+ SW_RTN_ON_ERROR(garuda_bist_test(dev_id));
+
+ entry = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ i = 0x10;
+ do
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mdelay(10);
+ }
+ while (entry && --i);
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+ }
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(garuda_portproperty_init(dev_id, cfg->cpu_mode));
+
+ GARUDA_MIB_INIT(rv, dev_id);
+ GARUDA_PORT_CTRL_INIT(rv, dev_id);
+ GARUDA_PORTVLAN_INIT(rv, dev_id);
+ GARUDA_VLAN_INIT(rv, dev_id);
+ GARUDA_FDB_INIT(rv, dev_id);
+ GARUDA_QOS_INIT(rv, dev_id);
+ GARUDA_STP_INIT(rv, dev_id);
+ GARUDA_MIRR_INIT(rv, dev_id);
+ GARUDA_RATE_INIT(rv, dev_id);
+ GARUDA_MISC_INIT(rv, dev_id);
+ GARUDA_LEAKY_INIT(rv, dev_id);
+ GARUDA_IGMP_INIT(rv, dev_id);
+ GARUDA_ACL_INIT(rv, dev_id);
+ GARUDA_LED_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = garuda_reset;
+ p_api->dev_clean = garuda_cleanup;
+ }
+
+ if(cfg->reg_mode == HSL_MDIO)
+ {
+ SW_RTN_ON_ERROR(garuda_hw_init(dev_id, cfg));
+ }
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_leaky.c b/src/hsl/garuda/garuda_leaky.c
new file mode 100644
index 0000000..86a4288
--- /dev/null
+++ b/src/hsl/garuda/garuda_leaky.c
@@ -0,0 +1,522 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_leaky GARUDA_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_leaky.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+
+static sw_error_t
+_garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_uc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_uc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_arp_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_arp_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_uc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_uc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_mc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_mc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_leaky_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->uc_leaky_mode_set = garuda_uc_leaky_mode_set;
+ p_api->uc_leaky_mode_get = garuda_uc_leaky_mode_get;
+ p_api->mc_leaky_mode_set = garuda_mc_leaky_mode_set;
+ p_api->mc_leaky_mode_get = garuda_mc_leaky_mode_get;
+ p_api->port_arp_leaky_set = garuda_port_arp_leaky_set;
+ p_api->port_arp_leaky_get = garuda_port_arp_leaky_get;
+ p_api->port_uc_leaky_set = garuda_port_uc_leaky_set;
+ p_api->port_uc_leaky_get = garuda_port_uc_leaky_get;
+ p_api->port_mc_leaky_set = garuda_port_mc_leaky_set;
+ p_api->port_mc_leaky_get = garuda_port_mc_leaky_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_led.c b/src/hsl/garuda/garuda_led.c
new file mode 100644
index 0000000..98b9ce9
--- /dev/null
+++ b/src/hsl/garuda/garuda_led.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_led GARUDA_LED
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "garuda_led.h"
+#include "garuda_reg.h"
+
+#define MAX_LED_PATTERN_ID 2
+#define LED_PATTERN_ADDR 0xB0
+
+
+static sw_error_t
+_garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((LED_LAN_PORT_GROUP != group) && (LED_WAN_PORT_GROUP != group))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 0, data);
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 1, data);
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 2, data);
+ }
+ else if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+ }
+ else if (LED_BLINK_TXRX == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ reg &= 0xffff0000;
+ reg |= data;
+ }
+ else
+ {
+ reg &= 0xffff;
+ reg |= (data << 16);
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, tmp;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (group >= LED_GROUP_BUTT)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ data = reg & 0xffff;
+ }
+ else
+ {
+ data = (reg >> 16) & 0xffff;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_OFF;
+ }
+ else if (1 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_BLINK;
+ }
+ else if (2 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_ON;
+ }
+ else
+ {
+ pattern->mode = LED_PATTERN_MAP_EN;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->freq = LED_BLINK_2HZ;
+ }
+ else if (1 == tmp)
+ {
+ pattern->freq = LED_BLINK_4HZ;
+ }
+ else if (2 == tmp)
+ {
+ pattern->freq = LED_BLINK_8HZ;
+ }
+ else
+ {
+ pattern->freq = LED_BLINK_TXRX;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+garuda_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_led_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->led_ctrl_pattern_set = garuda_led_ctrl_pattern_set;
+ p_api->led_ctrl_pattern_get = garuda_led_ctrl_pattern_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_mib.c b/src/hsl/garuda/garuda_mib.c
new file mode 100644
index 0000000..63d091f
--- /dev/null
+++ b/src/hsl/garuda/garuda_mib.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_mib GARUDA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mib.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mib_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mib_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = garuda_get_mib_info;
+ p_api->mib_status_set = garuda_mib_status_set;
+ p_api->mib_status_get = garuda_mib_status_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_mirror.c b/src/hsl/garuda/garuda_mirror.c
new file mode 100644
index 0000000..51f83cd
--- /dev/null
+++ b/src/hsl/garuda/garuda_mirror.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_mirror GARUDA_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_mirror.h"
+#include "garuda_reg.h"
+
+static sw_error_t
+_garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *port_id = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_analysis_port_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_analysis_port_get(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_port_in_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_port_in_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_port_eg_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_mirr_port_eg_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_mirr_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->mirr_analysis_port_set = garuda_mirr_analysis_port_set;
+ p_api->mirr_analysis_port_get = garuda_mirr_analysis_port_get;
+ p_api->mirr_port_in_set = garuda_mirr_port_in_set;
+ p_api->mirr_port_in_get = garuda_mirr_port_in_get;
+ p_api->mirr_port_eg_set = garuda_mirr_port_eg_set;
+ p_api->mirr_port_eg_get = garuda_mirr_port_eg_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_misc.c b/src/hsl/garuda/garuda_misc.c
new file mode 100644
index 0000000..e3c6cb9
--- /dev/null
+++ b/src/hsl/garuda/garuda_misc.c
@@ -0,0 +1,1000 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_misc GARUDA_MISC
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_misc.h"
+#include "garuda_reg.h"
+
+#define GARUDA_MAX_FRMAE_SIZE 9216
+
+
+static sw_error_t
+_garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (GARUDA_MAX_FRMAE_SIZE < size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = size;
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *size = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+ a_uint32_t port_lock_en, port_drop_en;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+ SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+ if (1 == port_lock_en)
+ {
+ if (1 == port_drop_en)
+ {
+ *action = FAL_MAC_DROP;
+ }
+ else
+ {
+ *action = FAL_MAC_RDT_TO_CPU;
+ }
+ }
+ else
+ {
+ *action = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BROAD_TO_CPU,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+
+static sw_error_t
+_garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_arp_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_arp_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_frame_max_size_set(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_frame_max_size_get(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_sa_cmd_get(dev_id, port_id, action);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_uc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_uc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_mc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_unk_mc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cpu_port_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cpu_port_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_bc_to_cpu_port_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_bc_to_cpu_port_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of braodcast packets broadcasting to cpu on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_bc_to_cpu_port_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_bc_to_cpu_port_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_pppoe_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_pppoe_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_pppoe_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_pppoe_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_dhcp_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_dhcp_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_misc_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->arp_status_set = garuda_arp_status_set;
+ p_api->arp_status_get = garuda_arp_status_get;
+ p_api->frame_max_size_set = garuda_frame_max_size_set;
+ p_api->frame_max_size_get = garuda_frame_max_size_get;
+ p_api->port_unk_sa_cmd_set = garuda_port_unk_sa_cmd_set;
+ p_api->port_unk_sa_cmd_get = garuda_port_unk_sa_cmd_get;
+ p_api->port_unk_uc_filter_set = garuda_port_unk_uc_filter_set;
+ p_api->port_unk_uc_filter_get = garuda_port_unk_uc_filter_get;
+ p_api->port_unk_mc_filter_set = garuda_port_unk_mc_filter_set;
+ p_api->port_unk_mc_filter_get = garuda_port_unk_mc_filter_get;
+ p_api->cpu_port_status_set = garuda_cpu_port_status_set;
+ p_api->cpu_port_status_get = garuda_cpu_port_status_get;
+ p_api->bc_to_cpu_port_set = garuda_bc_to_cpu_port_set;
+ p_api->bc_to_cpu_port_get = garuda_bc_to_cpu_port_get;
+ p_api->pppoe_cmd_set = garuda_pppoe_cmd_set;
+ p_api->pppoe_cmd_get = garuda_pppoe_cmd_get;
+ p_api->pppoe_status_set = garuda_pppoe_status_set;
+ p_api->pppoe_status_get = garuda_pppoe_status_get;
+ p_api->port_dhcp_set = garuda_port_dhcp_set;
+ p_api->port_dhcp_get = garuda_port_dhcp_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_port_ctrl.c b/src/hsl/garuda/garuda_port_ctrl.c
new file mode 100644
index 0000000..9c4e08f
--- /dev/null
+++ b/src/hsl/garuda/garuda_port_ctrl.c
@@ -0,0 +1,990 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_port_ctrl GARUDA_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_port_ctrl.h"
+#include "garuda_reg.h"
+#include "f1_phy.h"
+
+static sw_error_t
+_garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+ a_uint32_t reg_save = 0;
+ a_uint32_t reg_val = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ //save reg value
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ reg_save = reg_val;
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ //set mac be config by sw and turn off RX TX MAC_EN
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = f1_phy_set_duplex(dev_id, phy_id, duplex);
+
+ //retore reg value
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_duplex(dev_id, phy_id, pduplex);
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SPEED_1000 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = f1_phy_set_speed(dev_id, phy_id, speed);
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_speed(dev_id, phy_id, pspeed);
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ a_uint32_t phy_id;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f1_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f1_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t tx, rx, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg);
+
+ if (1 == rx)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force != (a_uint32_t) enable)
+ {
+ return SW_OK;
+ }
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (0 == force)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+ return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_hdr_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_hdr_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_flowctrl_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_flowctrl_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = garuda_port_duplex_get;
+ p_api->port_duplex_set = garuda_port_duplex_set;
+ p_api->port_speed_get = garuda_port_speed_get;
+ p_api->port_speed_set = garuda_port_speed_set;
+ p_api->port_autoneg_status_get = garuda_port_autoneg_status_get;
+ p_api->port_autoneg_enable = garuda_port_autoneg_enable;
+ p_api->port_autoneg_restart = garuda_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = garuda_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = garuda_port_autoneg_adv_set;
+ p_api->port_hdr_status_set = garuda_port_hdr_status_set;
+ p_api->port_hdr_status_get = garuda_port_hdr_status_get;
+ p_api->port_flowctrl_set = garuda_port_flowctrl_set;
+ p_api->port_flowctrl_get = garuda_port_flowctrl_get;
+ p_api->port_flowctrl_forcemode_set = garuda_port_flowctrl_forcemode_set;
+ p_api->port_flowctrl_forcemode_get = garuda_port_flowctrl_forcemode_get;
+ p_api->port_powersave_set = garuda_port_powersave_set;
+ p_api->port_powersave_get = garuda_port_powersave_get;
+ p_api->port_hibernate_set = garuda_port_hibernate_set;
+ p_api->port_hibernate_get = garuda_port_hibernate_get;
+ p_api->port_cdt = garuda_port_cdt;
+
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_portvlan.c b/src/hsl/garuda/garuda_portvlan.c
new file mode 100644
index 0000000..118ad7c
--- /dev/null
+++ b/src/hsl/garuda/garuda_portvlan.c
@@ -0,0 +1,903 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_port_vlan GARUDA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_portvlan.h"
+#include "garuda_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+
+static sw_error_t
+_garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+
+static sw_error_t
+_garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_EG_HYBRID == port_egvlanmode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[3] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((0 == vid) || (vid > MAX_VLAN_ID))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id,
+ DTAG_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id,
+ DTAG_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = tpid;
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tpid = val;
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_default_vid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_default_vid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_force_default_vid_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_force_default_vid_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_force_portvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_force_portvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_nestvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_nestvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan feature status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_port_nestvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_port_nestvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_nestvlan_tpid_set(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_nestvlan_tpid_get(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_portvlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = garuda_port_1qmode_get;
+ p_api->port_1qmode_set = garuda_port_1qmode_set;
+ p_api->port_egvlanmode_get = garuda_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = garuda_port_egvlanmode_set;
+ p_api->portvlan_member_add = garuda_portvlan_member_add;
+ p_api->portvlan_member_del = garuda_portvlan_member_del;
+ p_api->portvlan_member_update = garuda_portvlan_member_update;
+ p_api->portvlan_member_get = garuda_portvlan_member_get;
+ p_api->port_default_vid_set = garuda_port_default_vid_set;
+ p_api->port_default_vid_get = garuda_port_default_vid_get;
+ p_api->port_force_default_vid_set = garuda_port_force_default_vid_set;
+ p_api->port_force_default_vid_get = garuda_port_force_default_vid_get;
+ p_api->port_force_portvlan_set = garuda_port_force_portvlan_set;
+ p_api->port_force_portvlan_get = garuda_port_force_portvlan_get;
+ p_api->port_nestvlan_set = garuda_port_nestvlan_set;
+ p_api->port_nestvlan_get = garuda_port_nestvlan_get;
+ p_api->nestvlan_tpid_set = garuda_nestvlan_tpid_set;
+ p_api->nestvlan_tpid_get = garuda_nestvlan_tpid_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_qos.c b/src/hsl/garuda/garuda_qos.c
new file mode 100644
index 0000000..1ba84e1
--- /dev/null
+++ b/src/hsl/garuda/garuda_qos.c
@@ -0,0 +1,1182 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_qos GARUDA_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_qos.h"
+#include "garuda_reg.h"
+
+#define GARUDA_QOS_QUEUE_TX_BUFFER_MAX 60
+#define GARUDA_QOS_PORT_TX_BUFFER_MAX 252
+
+//#define GARUDA_MIN_QOS_MODE_PRI 0
+#define GARUDA_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_garuda_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t val, wrr, mix;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SCH_SP_MODE == mode)
+ {
+ wrr = 0;
+ mix = 0;
+ }
+ else if (FAL_SCH_WRR_MODE == mode)
+ {
+ wrr = 1;
+ mix = 0;
+ }
+ else if (FAL_SCH_MIX_MODE == mode)
+ {
+ wrr = 1;
+ mix = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val);
+ SW_SET_REG_BY_FIELD(GLOBAL_CTL, MIX_PRIORITY, mix, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_CTL, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t idx, val, wrr, mix;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_CTL, 0, (a_uint32_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(GLOBAL_CTL, WEIGHT_PRIORITY, wrr, val);
+ SW_GET_FIELD_BY_REG(GLOBAL_CTL, MIX_PRIORITY, mix, val);
+
+ if (0 == wrr)
+ {
+ *mode = FAL_SCH_SP_MODE;
+ for (idx = 0; idx < 4; idx++)
+ {
+ weight[idx] = 0;
+ }
+ }
+ else
+ {
+ if (0 == mix)
+ {
+ *mode = FAL_SCH_WRR_MODE;
+ weight[0] = 1;
+ for (idx = 1; idx < 4; idx++)
+ {
+ weight[idx] = weight[idx - 1] << 1;
+ }
+ }
+ else
+ {
+ *mode = FAL_SCH_MIX_MODE;
+ weight[3] = 0;
+ weight[2] = 4;
+ weight[1] = 2;
+ weight[0] = 1;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (GARUDA_QOS_QUEUE_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (GARUDA_QOS_PORT_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp >> 4) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp / 16) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (GARUDA_MAX_QOS_MODE_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ a_uint32_t entry, f_val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *pri = f_val;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = up;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *up = val;
+ return SW_OK;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one device.
+ * @details Comments:
+ * GARUDA doesn't support variable weight in wrr mode, the weight for four queues
+ * are 8:4:2:1.
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * When scheduling mode is sp the weight for four queues are 0:4:2:1
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_sch_mode_set(a_uint32_t dev_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_sch_mode_set(dev_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular device.
+ * @param[in] dev_id device id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_sch_mode_get(a_uint32_t dev_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_sch_mode_get(dev_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ If enable tx buffer on one port that means this port will have fixed
+ number buffers when transmitting packets. Otherwise they will
+ share the whole buffers with other ports in device.
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ The step of buffer number in GARUDA is 4, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for queue is 4 to 60.
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ The step of buffer number in GARUDA is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cosmap_up_queue_set(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cosmap_up_queue_get(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cosmap_dscp_queue_set(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_cosmap_dscp_queue_get(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_mode_set(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_mode_get(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ If the priority of a mode is more small then the priority is more high.
+ Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_default_up_set(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_qos_port_default_up_get(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_qos_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->qos_sch_mode_set = garuda_qos_sch_mode_set;
+ p_api->qos_sch_mode_get = garuda_qos_sch_mode_get;
+ p_api->qos_queue_tx_buf_status_set = garuda_qos_queue_tx_buf_status_set;
+ p_api->qos_queue_tx_buf_status_get = garuda_qos_queue_tx_buf_status_get;
+ p_api->qos_port_tx_buf_status_set = garuda_qos_port_tx_buf_status_set;
+ p_api->qos_port_tx_buf_status_get = garuda_qos_port_tx_buf_status_get;
+ p_api->qos_queue_tx_buf_nr_set = garuda_qos_queue_tx_buf_nr_set;
+ p_api->qos_queue_tx_buf_nr_get = garuda_qos_queue_tx_buf_nr_get;
+ p_api->qos_port_tx_buf_nr_set = garuda_qos_port_tx_buf_nr_set;
+ p_api->qos_port_tx_buf_nr_get = garuda_qos_port_tx_buf_nr_get;
+ p_api->cosmap_up_queue_set = garuda_cosmap_up_queue_set;
+ p_api->cosmap_up_queue_get = garuda_cosmap_up_queue_get;
+ p_api->cosmap_dscp_queue_set = garuda_cosmap_dscp_queue_set;
+ p_api->cosmap_dscp_queue_get = garuda_cosmap_dscp_queue_get;
+ p_api->qos_port_mode_set = garuda_qos_port_mode_set;
+ p_api->qos_port_mode_get = garuda_qos_port_mode_get;
+ p_api->qos_port_mode_pri_set = garuda_qos_port_mode_pri_set;
+ p_api->qos_port_mode_pri_get = garuda_qos_port_mode_pri_get;
+ p_api->qos_port_default_up_set = garuda_qos_port_default_up_set;
+ p_api->qos_port_default_up_get = garuda_qos_port_default_up_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_rate.c b/src/hsl/garuda/garuda_rate.c
new file mode 100644
index 0000000..8ed4ab1
--- /dev/null
+++ b/src/hsl/garuda/garuda_rate.c
@@ -0,0 +1,842 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup garuda_rate GARUDA_RATE
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_rate.h"
+#include "garuda_reg.h"
+
+#define GARUDA_STORM_MIN_RATE_PPS 1000
+#define GARUDA_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+garuda_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+ a_uint32_t shrnr = 0;
+ a_uint32_t tmp = swrate / 1000;
+
+ if ((GARUDA_STORM_MIN_RATE_PPS > swrate)
+ || (GARUDA_STORM_MAX_RATE_PPS < swrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ while ((tmp != 0) && (shrnr < 12))
+ {
+ tmp = tmp >> 1;
+ shrnr++;
+ }
+
+ if (12 == shrnr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *hwrate = shrnr;
+ return SW_OK;
+}
+
+static sw_error_t
+garuda_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+ if (0 == hwrate)
+ {
+ hwrate = 1;
+ }
+
+ if ((1 > hwrate) || (11 < hwrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *swrate = (1 << (hwrate - 1)) * 1000;
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t portrl;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (1 == portrl)
+ {
+ /* already enable port egress rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+ val = *speed >> 5;
+ *speed = val << 5;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0x7fff;
+ *speed = 0;
+ if (1 == portrl)
+ {
+ /* already enable port egress rate limit */
+ return SW_OK;
+ }
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ /* already enable port egress rate limit */
+ *speed = 0;
+ *enable = A_FALSE;
+
+ return SW_OK;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff == val)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t portrl;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ *speed = 0;
+
+ /* if port egress rate limit current enable then disable */
+ if (1 == portrl)
+ {
+ val = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = 0x7fff;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ rv = SW_OK;
+ }
+ else
+ {
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* not enable egress port rate limit */
+ if (0 == portrl)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue0 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue1 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue2 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue3 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ val = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ val = *speed >> 5;
+ *speed = val << 5;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *speed = 0;
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ *enable = A_TRUE;
+ *speed = val << 5;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+ val = *speed >> 5;
+ *speed = val << 5;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0x7fff;
+ *speed = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff == val)
+ {
+ *enable = A_FALSE;
+ *speed = 0;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ data = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ data = 1;
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = garuda_stormrate_sw_to_hw(*rate_in_pps, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_stormrate_hw_to_sw(data, rate_in_pps);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_stormrate_hw_to_sw(data, rate_in_pps);
+ return rv;
+}
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress rate limit input parameter speed is meaningless.
+ Egress queue rate limit can't coexist with port egress rate limit.
+ The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress rate limit input parameter speed is meaningless.
+ Egress port rate limit can't coexist with queue egress rate limit.
+ The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_port_egrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_port_egrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress rate limit input parameter speed is meaningless.
+ The step of speed is 32kbps.
+ * When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_port_inrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_rate_port_inrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ * @details Comments:
+ * When enable one particular packets type storm control this type packets
+ * speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ * @details Comments:
+ Because of hardware granularity function will return actual speed in hardware.
+ The step of speed is kpps.
+ The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_rate_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->rate_queue_egrl_set = garuda_rate_queue_egrl_set;
+ p_api->rate_queue_egrl_get = garuda_rate_queue_egrl_get;
+ p_api->rate_port_egrl_set = garuda_rate_port_egrl_set;
+ p_api->rate_port_egrl_get = garuda_rate_port_egrl_get;
+ p_api->rate_port_inrl_set = garuda_rate_port_inrl_set;
+ p_api->rate_port_inrl_get = garuda_rate_port_inrl_get;
+ p_api->storm_ctrl_frame_set = garuda_storm_ctrl_frame_set;
+ p_api->storm_ctrl_frame_get = garuda_storm_ctrl_frame_get;
+ p_api->storm_ctrl_rate_set = garuda_storm_ctrl_rate_set;
+ p_api->storm_ctrl_rate_get = garuda_storm_ctrl_rate_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_reduced_acl.c b/src/hsl/garuda/garuda_reduced_acl.c
new file mode 100644
index 0000000..d05f0f1
--- /dev/null
+++ b/src/hsl/garuda/garuda_reduced_acl.c
@@ -0,0 +1,156 @@
+#include "sw.h"
+#include "garuda_reduced_acl.h"
+#include "hsl.h"
+
+#define GARUDA_RULE_VLU_ADDR 0x58400
+#define GARUDA_RULE_MSK_ADDR 0x58c00
+#define GARUDA_RULE_ACT_ADDR 0x58000
+#define GARUDA_RULE_SLCT_ADDR 0x58800
+
+sw_error_t
+garuda_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* set rule value */
+ base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set rule mask */
+ base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act)
+{
+ sw_error_t rv;
+ a_uint32_t addr;
+
+ /* set rule action */
+ addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8])
+{
+ sw_error_t rv;
+ a_uint32_t base, addr;
+ a_uint32_t i;
+
+ base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* set rule address */
+ for (i = 1; i < 7; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set rule enable */
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* get rule value */
+ base = GARUDA_RULE_VLU_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get rule mask */
+ base = GARUDA_RULE_MSK_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t * act)
+{
+ sw_error_t rv;
+ a_uint32_t addr;
+
+ /* get rule action */
+ addr = GARUDA_RULE_ACT_ADDR + (act_idx << 5);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) act, sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = GARUDA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* get filter address and enable */
+ for (i = 0; i < 7; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
diff --git a/src/hsl/garuda/garuda_reg_access.c b/src/hsl/garuda/garuda_reg_access.c
new file mode 100644
index 0000000..292a27e
--- /dev/null
+++ b/src/hsl/garuda/garuda_reg_access.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "garuda_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_garuda_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in lower address, we should write the higher 16-bit register then the */
+ /* lower one */
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in lower address */
+ reg_word_addr--;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+garuda_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+garuda_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _garuda_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+garuda_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _garuda_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+garuda_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ return SW_OK;
+}
+
+sw_error_t
+garuda_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(garuda_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+ SW_RTN_ON_ERROR(garuda_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->phy_get = garuda_phy_get;
+ p_api->phy_set = garuda_phy_set;
+ p_api->reg_get = garuda_reg_get;
+ p_api->reg_set = garuda_reg_set;
+ p_api->reg_field_get = garuda_reg_field_get;
+ p_api->reg_field_set = garuda_reg_field_set;
+ p_api->dev_access_set= garuda_access_mode_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+garuda_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
diff --git a/src/hsl/garuda/garuda_stp.c b/src/hsl/garuda/garuda_stp.c
new file mode 100644
index 0000000..5544dae
--- /dev/null
+++ b/src/hsl/garuda/garuda_stp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_stp GARUDA_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_stp.h"
+#include "garuda_reg.h"
+
+#define GARUDA_PORT_DISABLED 0
+#define GARUDA_STP_BLOCKING 1
+#define GARUDA_STP_LISTENING 2
+#define GARUDA_STP_LEARNING 3
+#define GARUDA_STP_FARWARDING 4
+
+static sw_error_t
+_garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ switch (state)
+ {
+ case FAL_STP_BLOKING:
+ val = GARUDA_STP_BLOCKING;
+ break;
+ case FAL_STP_LISTENING:
+ val = GARUDA_STP_LISTENING;
+ break;
+ case FAL_STP_LEARNING:
+ val = GARUDA_STP_LEARNING;
+ break;
+ case FAL_STP_FARWARDING:
+ val = GARUDA_STP_FARWARDING;
+ break;
+ case FAL_STP_DISABLED:
+ val = GARUDA_PORT_DISABLED;
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ switch (val)
+ {
+ case GARUDA_STP_BLOCKING:
+ *state = FAL_STP_BLOKING;
+ break;
+ case GARUDA_STP_LISTENING:
+ *state = FAL_STP_LISTENING;
+ break;
+ case GARUDA_STP_LEARNING:
+ *state = FAL_STP_LEARNING;
+ break;
+ case GARUDA_STP_FARWARDING:
+ *state = FAL_STP_FARWARDING;
+ break;
+ case GARUDA_PORT_DISABLED:
+ *state = FAL_STP_DISABLED;
+ break;
+ default:
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ GARUDA only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_stp_port_state_set(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ GARUDA only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_stp_port_state_get(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_stp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->stp_port_state_set = garuda_stp_port_state_set;
+ p_api->stp_port_state_get = garuda_stp_port_state_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/garuda/garuda_vlan.c b/src/hsl/garuda/garuda_vlan.c
new file mode 100644
index 0000000..63ff859
--- /dev/null
+++ b/src/hsl/garuda/garuda_vlan.c
@@ -0,0 +1,489 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup garuda_vlan GARUDA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "garuda_vlan.h"
+#include "garuda_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+#define VLAN_NEXT_ENTRY 5
+#define VLAN_FIND_ENTRY 6
+
+static void
+garuda_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+ a_uint32_t data;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->vid_pri_en = A_TRUE;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+ vlan_entry->vid_pri = data & 0xff;
+ }
+ else
+ {
+ vlan_entry->vid_pri_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+ vlan_entry->vid = data & 0xffff;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+ vlan_entry->mem_ports = data;
+
+ return;
+}
+
+static sw_error_t
+garuda_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+ if (0 != vlan_entry->u_ports)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+garuda_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ vt_busy = 1;
+ i = 0x1000;
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (!val)
+ {
+ if (VLAN_FIND_ENTRY == op)
+ return SW_NOT_FOUND;
+
+ if (VLAN_NEXT_ENTRY == op)
+ return SW_NO_MORE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ rv = garuda_vlan_sw_to_hw(vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ /* set default value for VLAN_TABLE_FUNC1, all 0 */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ garuda_vlan_hw_to_sw(reg, p_vlan);
+
+ if (0 == p_vlan->vid)
+ return SW_NO_MORE;
+ else
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ garuda_vlan_hw_to_sw(reg, p_vlan);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ if (u_member != 0)
+ return SW_BAD_PARAM;
+
+ /* get vlan entry first */
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ /* set vlan member for VLAN_TABLE_FUNC1 */
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+ (a_uint8_t *) (&member), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ /* when update port member through LOAD opration, hardware will
+ return VT_FULL_VIO, we should ignore it */
+ if (SW_FULL == rv)
+ rv = SW_OK;
+
+ return rv;
+}
+
+
+static sw_error_t
+_garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ reg = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = garuda_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_member_update(dev_id, vlan_id, member, u_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+garuda_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _garuda_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+garuda_vlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = garuda_vlan_entry_append;
+ p_api->vlan_creat = garuda_vlan_create;
+ p_api->vlan_member_update = garuda_vlan_member_update;
+ p_api->vlan_delete = garuda_vlan_delete;
+ p_api->vlan_next = garuda_vlan_next;
+ p_api->vlan_find = garuda_vlan_find;
+
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/horus/Makefile b/src/hsl/horus/Makefile
new file mode 100644
index 0000000..bdbd6c0
--- /dev/null
+++ b/src/hsl/horus/Makefile
@@ -0,0 +1,80 @@
+LOC_DIR=src/hsl/horus
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=horus_reg_access.c horus_init.c
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += horus_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += horus_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += horus_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += horus_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += horus_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += horus_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += horus_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += horus_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += horus_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += horus_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += horus_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += horus_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += horus_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ SRC_LIST += horus_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=horus_reg_access.c horus_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring HORUS, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/hsl/horus/horus_fdb.c b/src/hsl/horus/horus_fdb.c
new file mode 100644
index 0000000..ccd0d08
--- /dev/null
+++ b/src/hsl/horus/horus_fdb.c
@@ -0,0 +1,990 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_fdb HORUS_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_fdb.h"
+#include "horus_reg.h"
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+#define ARL_FIND_ENTRY 7
+
+#define ARL_FIRST_ENTRY 1001
+#define ARL_FLUSH_PORT_NO_STATIC 1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+horus_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+horus_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+horus_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->clone_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ hsl_dev_t *p_dev;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+ if (entry->da_queue > (p_dev->nr_queue - 1))
+ return SW_BAD_PARAM;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+ horus_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ return SW_OK;
+}
+
+static void
+horus_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->clone_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->clone_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x3;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 0; i < 4; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+ }
+
+ for (i = 4; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+ }
+
+ return;
+}
+
+static sw_error_t
+horus_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 1000;
+ a_uint32_t entry;
+ a_uint32_t hwop = op;
+
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_BUSY;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+ if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+ }
+
+ if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 1000;
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+ (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (full_vio)
+ {
+ /* must clear AT_FULL_VOI bit */
+ entry = 0x1000;
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ARL_LOAD_ENTRY == hwop)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == hwop)
+ || (ARL_FLUSH_PORT_UNICAST == hwop))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+horus_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0 };
+ a_uint32_t status = 0;
+ a_uint32_t hwop = op;
+
+ if ((ARL_NEXT_ENTRY == op)
+ || (ARL_FIND_ENTRY == op))
+ {
+ horus_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set status not zero */
+ if (ARL_NEXT_ENTRY == op)
+ {
+ reg[2] = 0xf0000;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ /* get hardware enrety */
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+ horus_atu_hw_to_sw(reg, entry);
+
+ /* If hardware return back with address and status all zero,
+ that means no other next valid entry in fdb table */
+ if ((A_TRUE == horus_fdb_is_zeroaddr(entry->addr))
+ && (0 == status))
+ {
+ if (ARL_NEXT_ENTRY == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if ((ARL_FIND_ENTRY == op)
+ || (ARL_FIRST_ENTRY == op))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0, 0, 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = horus_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = horus_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+ }
+ else
+ {
+ rv = horus_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ horus_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = horus_atu_get(dev_id, entry, ARL_NEXT_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = horus_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = horus_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((65535 * 7 < *time) || (7 > *time))
+ {
+ return SW_BAD_PARAM;
+ }
+ data = *time / 7;
+ *time = data * 7;
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 7;
+ return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from particular device
+ * @details Comments:
+ * For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_next(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_first(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_port_learn_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_port_learn_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_age_ctrl_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_age_ctrl_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_fdb_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = horus_fdb_add;
+ p_api->fdb_del_all = horus_fdb_del_all;
+ p_api->fdb_del_by_port = horus_fdb_del_by_port;
+ p_api->fdb_del_by_mac = horus_fdb_del_by_mac;
+ p_api->fdb_first = horus_fdb_first;
+ p_api->fdb_next = horus_fdb_next;
+ p_api->fdb_find = horus_fdb_find;
+ p_api->port_learn_set = horus_fdb_port_learn_set;
+ p_api->port_learn_get = horus_fdb_port_learn_get;
+ p_api->age_ctrl_set = horus_fdb_age_ctrl_set;
+ p_api->age_ctrl_get = horus_fdb_age_ctrl_get;
+ p_api->age_time_set = horus_fdb_age_time_set;
+ p_api->age_time_get = horus_fdb_age_time_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_igmp.c b/src/hsl/horus/horus_igmp.c
new file mode 100644
index 0000000..afac7e5
--- /dev/null
+++ b/src/hsl/horus/horus_igmp.c
@@ -0,0 +1,970 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_igmp HORUS_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_igmp.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+ {
+ return SW_BAD_PARAM;
+ }
+ val = pts;
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *pts = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0xe;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+ hsl_dev_t *p_dev;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (queue >= p_dev->nr_queue)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
+ if (data)
+ {
+ *enable = A_TRUE;
+ SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
+ *queue = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *queue = 0;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmps_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmps_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmp_mld_join_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmp_mld_join_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp leave feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmp_mld_leave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_igmp_mld_leave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_rp_set(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_rp_get(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_creat_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_creat_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * static status hardware will not age out multicast entry which leardned by hardware,
+ * otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_static_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_static_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_leaky_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_leaky_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details Comments:
+ * After enabling igmp join/leave feature on a particular port hardware will dynamic
+ * creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_v3_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_v3_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_queue_set(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_igmp_mld_entry_queue_get(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_igmp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_igmps_status_set = horus_port_igmps_status_set;
+ p_api->port_igmps_status_get = horus_port_igmps_status_get;
+ p_api->igmp_mld_cmd_set = horus_igmp_mld_cmd_set;
+ p_api->igmp_mld_cmd_get = horus_igmp_mld_cmd_get;
+ p_api->port_igmp_join_set = horus_port_igmp_mld_join_set;
+ p_api->port_igmp_join_get = horus_port_igmp_mld_join_get;
+ p_api->port_igmp_leave_set = horus_port_igmp_mld_leave_set;
+ p_api->port_igmp_leave_get = horus_port_igmp_mld_leave_get;
+ p_api->igmp_rp_set = horus_igmp_mld_rp_set;
+ p_api->igmp_rp_get = horus_igmp_mld_rp_get;
+ p_api->igmp_entry_creat_set = horus_igmp_mld_entry_creat_set;
+ p_api->igmp_entry_creat_get = horus_igmp_mld_entry_creat_get;
+ p_api->igmp_entry_static_set = horus_igmp_mld_entry_static_set;
+ p_api->igmp_entry_static_get = horus_igmp_mld_entry_static_get;
+ p_api->igmp_entry_leaky_set = horus_igmp_mld_entry_leaky_set;
+ p_api->igmp_entry_leaky_get = horus_igmp_mld_entry_leaky_get;
+ p_api->igmp_entry_v3_set = horus_igmp_mld_entry_v3_set;
+ p_api->igmp_entry_v3_get = horus_igmp_mld_entry_v3_get;
+ p_api->igmp_entry_queue_set = horus_igmp_mld_entry_queue_set;
+ p_api->igmp_entry_queue_get = horus_igmp_mld_entry_queue_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_init.c b/src/hsl/horus/horus_init.c
new file mode 100644
index 0000000..473cd83
--- /dev/null
+++ b/src/hsl/horus/horus_init.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_init HORUS_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mib.h"
+#include "horus_port_ctrl.h"
+#include "horus_portvlan.h"
+#include "horus_vlan.h"
+#include "horus_fdb.h"
+#include "horus_qos.h"
+#include "horus_mirror.h"
+#include "horus_stp.h"
+#include "horus_rate.h"
+#include "horus_misc.h"
+#include "horus_leaky.h"
+#include "horus_igmp.h"
+#include "horus_led.h"
+#include "horus_reg_access.h"
+#include "horus_reg.h"
+#include "f2_phy.h"
+
+static ssdk_init_cfg * horus_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+static sw_error_t
+horus_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ if (HSL_CPU_1 != mode)
+ {
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != (pdev->nr_ports -1)))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port and wan port in some cases */
+ if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ if ((port_id != pdev->cpu_port_nr)
+ && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 1)))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+horus_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ hsl_dev_t *pdev = NULL;
+ a_uint32_t port_id;
+ a_uint32_t data;
+ sw_error_t rv;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (NULL == pdev)
+ {
+ return SW_NOT_INITIALIZED;
+ }
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (port_id == pdev->cpu_port_nr)
+ {
+ continue;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+horus_bist_test(a_uint32_t dev_id)
+{
+ a_uint32_t entry, data, i;
+ sw_error_t rv;
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+ if (!data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ return SW_OK;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ return SW_OK;
+}
+#endif
+
+static sw_error_t
+horus_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ pdev->nr_ports = 6;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 16;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 4;
+ pdev->cpu_mode = cpu_mode;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_hw_init(dev_id, horus_cfg[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ return SW_OK;
+}
+
+
+sw_error_t
+horus_cleanup(a_uint32_t dev_id)
+{
+
+ if (horus_cfg[dev_id])
+ {
+ aos_mem_free(horus_cfg[dev_id]);
+ horus_cfg[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ * This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+sw_error_t
+horus_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ * This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+horus_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == horus_cfg[dev_id])
+ {
+ horus_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == horus_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(horus_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(horus_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(horus_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ a_uint32_t i, entry;
+ sw_error_t rv;
+
+ SW_RTN_ON_ERROR(horus_bist_test(dev_id));
+
+ entry = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ i = 0x10;
+ do
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mdelay(10);
+ }
+ while (entry && --i);
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(horus_portproperty_init(dev_id, cfg->cpu_mode));
+
+ HORUS_MIB_INIT(rv, dev_id);
+ HORUS_PORT_CTRL_INIT(rv, dev_id);
+ HORUS_PORTVLAN_INIT(rv, dev_id);
+ HORUS_VLAN_INIT(rv, dev_id);
+ HORUS_FDB_INIT(rv, dev_id);
+ HORUS_QOS_INIT(rv, dev_id);
+ HORUS_STP_INIT(rv, dev_id);
+ HORUS_MIRR_INIT(rv, dev_id);
+ HORUS_RATE_INIT(rv, dev_id);
+ HORUS_MISC_INIT(rv, dev_id);
+ HORUS_LEAKY_INIT(rv, dev_id);
+ HORUS_IGMP_INIT(rv, dev_id);
+ HORUS_LED_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = horus_reset;
+ p_api->dev_clean = horus_cleanup;
+ }
+
+ SW_RTN_ON_ERROR(horus_hw_init(dev_id, cfg));
+ }
+#endif
+
+ return SW_OK;
+}
+
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_leaky.c b/src/hsl/horus/horus_leaky.c
new file mode 100644
index 0000000..4c38da1
--- /dev/null
+++ b/src/hsl/horus/horus_leaky.c
@@ -0,0 +1,516 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_leaky HORUS_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_leaky.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_uc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_uc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_arp_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_arp_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_uc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_uc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_mc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_mc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_leaky_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->uc_leaky_mode_set = horus_uc_leaky_mode_set;
+ p_api->uc_leaky_mode_get = horus_uc_leaky_mode_get;
+ p_api->mc_leaky_mode_set = horus_mc_leaky_mode_set;
+ p_api->mc_leaky_mode_get = horus_mc_leaky_mode_get;
+ p_api->port_arp_leaky_set = horus_port_arp_leaky_set;
+ p_api->port_arp_leaky_get = horus_port_arp_leaky_get;
+ p_api->port_uc_leaky_set = horus_port_uc_leaky_set;
+ p_api->port_uc_leaky_get = horus_port_uc_leaky_get;
+ p_api->port_mc_leaky_set = horus_port_mc_leaky_set;
+ p_api->port_mc_leaky_get = horus_port_mc_leaky_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_led.c b/src/hsl/horus/horus_led.c
new file mode 100644
index 0000000..ce8e130
--- /dev/null
+++ b/src/hsl/horus/horus_led.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_led HORUS_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_led.h"
+#include "horus_reg.h"
+
+#define MAX_LED_PATTERN_ID 1
+#define LED_PATTERN_ADDR 0xB0
+
+static sw_error_t
+_horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, mode;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (group >= LED_GROUP_BUTT)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (LED_MAC_PORT_GROUP == group)
+ {
+ addr = LED_PATTERN_ADDR + 8;
+ }
+ else
+ {
+ addr = LED_PATTERN_ADDR + (id << 2);
+ }
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ mode = 0;
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ mode = 1;
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ mode = 2;
+ }
+ else if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ mode = 3;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+ }
+ else if (LED_BLINK_TXRX == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ reg &= 0xffff;
+ reg |= (data << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= data;
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ if (id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+ }
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, tmp;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (group >= LED_GROUP_BUTT)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+ if (LED_MAC_PORT_GROUP == group)
+ {
+ addr = LED_PATTERN_ADDR + 8;
+ }
+ else
+ {
+ addr = LED_PATTERN_ADDR + (id << 2);
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ data = (reg >> 16) & 0xffff;
+ }
+ else
+ {
+ data = reg & 0xffff;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_OFF;
+ }
+ else if (1 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_BLINK;
+ }
+ else if (2 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_ON;
+ }
+ else
+ {
+ pattern->mode = LED_PATTERN_MAP_EN;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->freq = LED_BLINK_2HZ;
+ }
+ else if (1 == tmp)
+ {
+ pattern->freq = LED_BLINK_4HZ;
+ }
+ else if (2 == tmp)
+ {
+ pattern->freq = LED_BLINK_8HZ;
+ }
+ else
+ {
+ pattern->freq = LED_BLINK_TXRX;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+horus_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_led_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->led_ctrl_pattern_set = horus_led_ctrl_pattern_set;
+ p_api->led_ctrl_pattern_get = horus_led_ctrl_pattern_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_mib.c b/src/hsl/horus/horus_mib.c
new file mode 100644
index 0000000..ef63583
--- /dev/null
+++ b/src/hsl/horus/horus_mib.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_mib HORUS_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mib.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mib_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mib_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = horus_get_mib_info;
+ p_api->mib_status_set = horus_mib_status_set;
+ p_api->mib_status_get = horus_mib_status_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_mirror.c b/src/hsl/horus/horus_mirror.c
new file mode 100644
index 0000000..afcfb8f
--- /dev/null
+++ b/src/hsl/horus/horus_mirror.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_mirror HORUS_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_mirror.h"
+#include "horus_reg.h"
+
+static sw_error_t
+_horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *port_id = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_analysis_port_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_analysis_port_get(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_port_in_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_port_in_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_port_eg_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_mirr_port_eg_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_mirr_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->mirr_analysis_port_set = horus_mirr_analysis_port_set;
+ p_api->mirr_analysis_port_get = horus_mirr_analysis_port_get;
+ p_api->mirr_port_in_set = horus_mirr_port_in_set;
+ p_api->mirr_port_in_get = horus_mirr_port_in_get;
+ p_api->mirr_port_eg_set = horus_mirr_port_eg_set;
+ p_api->mirr_port_eg_get = horus_mirr_port_eg_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_misc.c b/src/hsl/horus/horus_misc.c
new file mode 100644
index 0000000..df61cae
--- /dev/null
+++ b/src/hsl/horus/horus_misc.c
@@ -0,0 +1,1387 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_misc HORUS_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_misc.h"
+#include "horus_reg.h"
+
+#define HORUS_MAX_FRMAE_SIZE 9216
+
+static sw_error_t
+_horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (HORUS_MAX_FRMAE_SIZE < size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = size;
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *size = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+ a_uint32_t port_lock_en, port_drop_en;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+ SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+ if (1 == port_lock_en)
+ {
+ if (1 == port_drop_en)
+ {
+ *action = FAL_MAC_DROP;
+ }
+ else
+ {
+ *action = FAL_MAC_RDT_TO_CPU;
+ }
+ }
+ else
+ {
+ *action = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_arp_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_arp_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_frame_max_size_set(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_frame_max_size_get(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_sa_cmd_get(dev_id, port_id, action);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_uc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_uc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_mc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_unk_mc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_bc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_bc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cpu_port_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cpu_port_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_pppoe_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_pppoe_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_pppoe_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_pppoe_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_dhcp_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_dhcp_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling arp packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_arp_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_arp_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling eapol packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_eapol_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_eapol_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_eapol_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_eapol_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_ripv1_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_ripv1_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_misc_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->arp_status_set = horus_arp_status_set;
+ p_api->arp_status_get = horus_arp_status_get;
+ p_api->frame_max_size_set = horus_frame_max_size_set;
+ p_api->frame_max_size_get = horus_frame_max_size_get;
+ p_api->port_unk_sa_cmd_set = horus_port_unk_sa_cmd_set;
+ p_api->port_unk_sa_cmd_get = horus_port_unk_sa_cmd_get;
+ p_api->port_unk_uc_filter_set = horus_port_unk_uc_filter_set;
+ p_api->port_unk_uc_filter_get = horus_port_unk_uc_filter_get;
+ p_api->port_unk_mc_filter_set = horus_port_unk_mc_filter_set;
+ p_api->port_unk_mc_filter_get = horus_port_unk_mc_filter_get;
+ p_api->port_bc_filter_set = horus_port_bc_filter_set;
+ p_api->port_bc_filter_get = horus_port_bc_filter_get;
+ p_api->cpu_port_status_set = horus_cpu_port_status_set;
+ p_api->cpu_port_status_get = horus_cpu_port_status_get;
+ p_api->pppoe_cmd_set = horus_pppoe_cmd_set;
+ p_api->pppoe_cmd_get = horus_pppoe_cmd_get;
+ p_api->pppoe_status_set = horus_pppoe_status_set;
+ p_api->pppoe_status_get = horus_pppoe_status_get;
+ p_api->port_dhcp_set = horus_port_dhcp_set;
+ p_api->port_dhcp_get = horus_port_dhcp_get;
+ p_api->arp_cmd_set = horus_arp_cmd_set;
+ p_api->arp_cmd_get = horus_arp_cmd_get;
+ p_api->eapol_cmd_set = horus_eapol_cmd_set;
+ p_api->eapol_cmd_get = horus_eapol_cmd_get;
+ p_api->eapol_status_set = horus_eapol_status_set;
+ p_api->eapol_status_get = horus_eapol_status_get;
+ p_api->ripv1_status_set = horus_ripv1_status_set;
+ p_api->ripv1_status_get = horus_ripv1_status_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_port_ctrl.c b/src/hsl/horus/horus_port_ctrl.c
new file mode 100644
index 0000000..587df66
--- /dev/null
+++ b/src/hsl/horus/horus_port_ctrl.c
@@ -0,0 +1,982 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_port_ctrl HORUS_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_port_ctrl.h"
+#include "horus_reg.h"
+#include "f2_phy.h"
+
+static sw_error_t
+_horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+ a_uint32_t reg_save = 0;
+ a_uint32_t reg_val = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ //save reg value
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ reg_save = reg_val;
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ //set mac be config by sw and turn off RX TX MAC_EN
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = f2_phy_set_duplex(dev_id, phy_id, duplex);
+
+ //retore reg value
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_duplex(dev_id, phy_id, pduplex);
+ return rv;
+}
+
+static sw_error_t
+_horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SPEED_100 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = f2_phy_set_speed(dev_id, phy_id, speed);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_speed(dev_id, phy_id, pspeed);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ a_uint32_t phy_id;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f2_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f2_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t tx, rx, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg);
+
+ if (1 == rx)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force != (a_uint32_t) enable)
+ {
+ return SW_OK;
+ }
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (0 == force)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+ return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_hdr_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_hdr_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_flowctrl_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_flowctrl_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = horus_port_duplex_get;
+ p_api->port_duplex_set = horus_port_duplex_set;
+ p_api->port_speed_get = horus_port_speed_get;
+ p_api->port_speed_set = horus_port_speed_set;
+ p_api->port_autoneg_status_get = horus_port_autoneg_status_get;
+ p_api->port_autoneg_enable = horus_port_autoneg_enable;
+ p_api->port_autoneg_restart = horus_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = horus_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = horus_port_autoneg_adv_set;
+ p_api->port_hdr_status_set = horus_port_hdr_status_set;
+ p_api->port_hdr_status_get = horus_port_hdr_status_get;
+ p_api->port_flowctrl_set = horus_port_flowctrl_set;
+ p_api->port_flowctrl_get = horus_port_flowctrl_get;
+ p_api->port_flowctrl_forcemode_set = horus_port_flowctrl_forcemode_set;
+ p_api->port_flowctrl_forcemode_get = horus_port_flowctrl_forcemode_get;
+ p_api->port_powersave_set = horus_port_powersave_set;
+ p_api->port_powersave_get = horus_port_powersave_get;
+ p_api->port_hibernate_set = horus_port_hibernate_set;
+ p_api->port_hibernate_get = horus_port_hibernate_get;
+ p_api->port_cdt = horus_port_cdt;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_portvlan.c b/src/hsl/horus/horus_portvlan.c
new file mode 100644
index 0000000..3a84209
--- /dev/null
+++ b/src/hsl/horus/horus_portvlan.c
@@ -0,0 +1,1175 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_port_vlan HORUS_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_portvlan.h"
+#include "horus_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+static sw_error_t
+_horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+static sw_error_t
+_horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED, FAL_EG_HYBRID
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((0 == vid) || (vid > MAX_VLAN_ID))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+ DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+ DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+
+static sw_error_t
+_horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = tpid;
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tpid = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_INVLAN_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val[mode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+ FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(mode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (regval >= 3)
+ {
+ return SW_FAIL;
+ }
+ *mode = retval[regval & 0x3];
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_QINQ_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_STAG_MODE == mode)
+ {
+ stag = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ STAG_MODE, (a_uint8_t *) (&stag),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ STAG_MODE, (a_uint8_t *) (&stag),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (stag)
+ {
+ *mode = FAL_QINQ_STAG_MODE;
+ }
+ else
+ {
+ *mode = FAL_QINQ_CTAG_MODE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_CORE_PORT == role)
+ {
+ core = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ COREP_EN, (a_uint8_t *) (&core),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ COREP_EN, (a_uint8_t *) (&core),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (core)
+ {
+ *role = FAL_QINQ_CORE_PORT;
+ }
+ else
+ {
+ *role = FAL_QINQ_EDGE_PORT;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_default_vid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default vlan id on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid default vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_default_vid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_force_default_vid_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_force_default_vid_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_force_portvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_force_portvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_nestvlan_tpid_set(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_nestvlan_tpid_get(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_invlan_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_invlan_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_pri_propagation_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_pri_propagation_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qinq_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qinq_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_qinq_role_set(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_port_qinq_role_get(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_portvlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = horus_port_1qmode_get;
+ p_api->port_1qmode_set = horus_port_1qmode_set;
+ p_api->port_egvlanmode_get = horus_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = horus_port_egvlanmode_set;
+ p_api->portvlan_member_add = horus_portvlan_member_add;
+ p_api->portvlan_member_del = horus_portvlan_member_del;
+ p_api->portvlan_member_update = horus_portvlan_member_update;
+ p_api->portvlan_member_get = horus_portvlan_member_get;
+ p_api->port_default_vid_set = horus_port_default_vid_set;
+ p_api->port_default_vid_get = horus_port_default_vid_get;
+ p_api->port_force_default_vid_set = horus_port_force_default_vid_set;
+ p_api->port_force_default_vid_get = horus_port_force_default_vid_get;
+ p_api->port_force_portvlan_set = horus_port_force_portvlan_set;
+ p_api->port_force_portvlan_get = horus_port_force_portvlan_get;
+ p_api->nestvlan_tpid_set = horus_nestvlan_tpid_set;
+ p_api->nestvlan_tpid_get = horus_nestvlan_tpid_get;
+ p_api->port_invlan_mode_set = horus_port_invlan_mode_set;
+ p_api->port_invlan_mode_get = horus_port_invlan_mode_get;
+ p_api->port_pri_propagation_set = horus_port_pri_propagation_set;
+ p_api->port_pri_propagation_get = horus_port_pri_propagation_get;
+ p_api->qinq_mode_set = horus_qinq_mode_set;
+ p_api->qinq_mode_get = horus_qinq_mode_get;
+ p_api->port_qinq_role_set = horus_port_qinq_role_set;
+ p_api->port_qinq_role_get = horus_port_qinq_role_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_qos.c b/src/hsl/horus/horus_qos.c
new file mode 100644
index 0000000..ce20440
--- /dev/null
+++ b/src/hsl/horus/horus_qos.c
@@ -0,0 +1,1251 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_qos HORUS_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_qos.h"
+#include "horus_reg.h"
+
+#define HORUS_QOS_QUEUE_TX_BUFFER_MAX 60
+#define HORUS_QOS_PORT_TX_BUFFER_MAX 252
+#define HORUS_QOS_PORT_RX_BUFFER_MAX 60
+
+//#define HORUS_MIN_QOS_MODE_PRI 0
+#define HORUS_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (HORUS_QOS_QUEUE_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (HORUS_QOS_PORT_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (HORUS_QOS_PORT_RX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp >> 4) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp / 16) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (HORUS_MAX_QOS_MODE_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ a_uint32_t entry, f_val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *pri = f_val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = up;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1Q, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *up = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SCH_SP_MODE == mode)
+ {
+ val = 0;
+ }
+ else if (FAL_SCH_WRR_MODE == mode)
+ {
+ val = 3;
+ }
+ else if (FAL_SCH_MIX_MODE == mode)
+ {
+ val = 1;
+ }
+ else if (FAL_SCH_MIX_PLUS_MODE == mode)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t sch, i;
+ a_uint32_t w[4] = {1, 2, 4, 8};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, WRR_CTRL, port_id, SCH_MODE,
+ (a_uint8_t *) (&sch), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == sch)
+ {
+ *mode = FAL_SCH_SP_MODE;
+ for (i = 0; i < 4; i++)
+ {
+ w[i] = 0;
+ }
+ }
+ else if (1 == sch)
+ {
+ *mode = FAL_SCH_MIX_MODE;
+ w[3] = 0;
+ }
+ else if (2 == sch)
+ {
+ *mode = FAL_SCH_MIX_PLUS_MODE;
+ w[3] = 0;
+ w[2] = 0;
+ }
+ else
+ {
+ *mode = FAL_SCH_WRR_MODE;
+ }
+
+ for (i = 0; i < 4; i++)
+ {
+ weight[i] = w[i];
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ If enable tx buffer on one port that means this port will have fixed
+ number buffers when transmitting packets. Otherwise they will
+ share the whole buffers with other ports in device.
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is 4, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for queue is 4 to 60.
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ * @details Comments:
+ The step of buffer number in Horus is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cosmap_up_queue_set(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cosmap_up_queue_get(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cosmap_dscp_queue_set(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_cosmap_dscp_queue_get(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_mode_set(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_mode_get(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ If the priority of a mode is more small then the priority is more high.
+ Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_default_up_set(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_default_up_get(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ * @details Comments:
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+ Horus only support fixed weight 1:2:4:8 for four queues.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_qos_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->qos_queue_tx_buf_status_set = horus_qos_queue_tx_buf_status_set;
+ p_api->qos_queue_tx_buf_status_get = horus_qos_queue_tx_buf_status_get;
+ p_api->qos_port_tx_buf_status_set = horus_qos_port_tx_buf_status_set;
+ p_api->qos_port_tx_buf_status_get = horus_qos_port_tx_buf_status_get;
+ p_api->qos_queue_tx_buf_nr_set = horus_qos_queue_tx_buf_nr_set;
+ p_api->qos_queue_tx_buf_nr_get = horus_qos_queue_tx_buf_nr_get;
+ p_api->qos_port_tx_buf_nr_set = horus_qos_port_tx_buf_nr_set;
+ p_api->qos_port_tx_buf_nr_get = horus_qos_port_tx_buf_nr_get;
+ p_api->qos_port_rx_buf_nr_set = horus_qos_port_rx_buf_nr_set;
+ p_api->qos_port_rx_buf_nr_get = horus_qos_port_rx_buf_nr_get;
+ p_api->cosmap_up_queue_set = horus_cosmap_up_queue_set;
+ p_api->cosmap_up_queue_get = horus_cosmap_up_queue_get;
+ p_api->cosmap_dscp_queue_set = horus_cosmap_dscp_queue_set;
+ p_api->cosmap_dscp_queue_get = horus_cosmap_dscp_queue_get;
+ p_api->qos_port_mode_set = horus_qos_port_mode_set;
+ p_api->qos_port_mode_get = horus_qos_port_mode_get;
+ p_api->qos_port_mode_pri_set = horus_qos_port_mode_pri_set;
+ p_api->qos_port_mode_pri_get = horus_qos_port_mode_pri_get;
+ p_api->qos_port_default_up_set = horus_qos_port_default_up_set;
+ p_api->qos_port_default_up_get = horus_qos_port_default_up_get;
+ p_api->qos_port_sch_mode_set = horus_qos_port_sch_mode_set;
+ p_api->qos_port_sch_mode_get = horus_qos_port_sch_mode_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_rate.c b/src/hsl/horus/horus_rate.c
new file mode 100644
index 0000000..6d084b0
--- /dev/null
+++ b/src/hsl/horus/horus_rate.c
@@ -0,0 +1,569 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_rate HORUS_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_rate.h"
+#include "horus_reg.h"
+
+#define HORUS_STORM_MIN_RATE_PPS 1000
+#define HORUS_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+horus_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+ a_uint32_t shrnr = 0;
+ a_uint32_t tmp = swrate / 1000;
+
+ if ((HORUS_STORM_MIN_RATE_PPS > swrate)
+ || (HORUS_STORM_MAX_RATE_PPS < swrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ while ((tmp != 0) && (shrnr < 12))
+ {
+ tmp = tmp >> 1;
+ shrnr++;
+ }
+
+ if (12 == shrnr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *hwrate = shrnr;
+ return SW_OK;
+}
+
+static sw_error_t
+horus_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+ if (0 == hwrate)
+ {
+ hwrate = 1;
+ }
+
+ if ((1 > hwrate) || (11 < hwrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *swrate = (1 << (hwrate - 1)) * 1000;
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == enable)
+ {
+ *speed = 0;
+
+ val = 0x1fff;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ if ((0x1ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *speed >> 5;
+ *speed = val << 5;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x1fff == val)
+ {
+ *speed = 0;
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+ val = *speed >> 5;
+ *speed = val << 5;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0x7fff;
+ *speed = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff == val)
+ {
+ *enable = A_FALSE;
+ *speed = 0;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ data = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ data = 1;
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = horus_stormrate_sw_to_hw(*rate_in_pps, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_stormrate_hw_to_sw(data, rate_in_pps);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_stormrate_hw_to_sw(data, rate_in_pps);
+ return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress rate limit input parameter speed is meaningless.
+ The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_rate_port_egrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_rate_port_egrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress rate limit input parameter speed is meaningless.
+ The step of speed is 32kbps.
+ * When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_rate_port_inrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_rate_port_inrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ * @details Comments:
+ * When enable one particular packets type storm control this type packets
+ * speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ * @details Comments:
+ Because of hardware granularity function will return actual speed in hardware.
+ The step of speed is kpps.
+ The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_rate_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->rate_port_egrl_set = horus_rate_port_egrl_set;
+ p_api->rate_port_egrl_get = horus_rate_port_egrl_get;
+ p_api->rate_port_inrl_set = horus_rate_port_inrl_set;
+ p_api->rate_port_inrl_get = horus_rate_port_inrl_get;
+ p_api->storm_ctrl_frame_set = horus_storm_ctrl_frame_set;
+ p_api->storm_ctrl_frame_get = horus_storm_ctrl_frame_get;
+ p_api->storm_ctrl_rate_set = horus_storm_ctrl_rate_set;
+ p_api->storm_ctrl_rate_get = horus_storm_ctrl_rate_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_reg_access.c b/src/hsl/horus/horus_reg_access.c
new file mode 100644
index 0000000..ff02517
--- /dev/null
+++ b/src/hsl/horus/horus_reg_access.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "horus_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_horus_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in lower address, we should write the higher 16-bit register then the */
+ /* lower one */
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in lower address */
+ reg_word_addr--;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+horus_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+horus_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+horus_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _horus_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+horus_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _horus_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+horus_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ return SW_OK;
+}
+
+sw_error_t
+horus_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(horus_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+ SW_RTN_ON_ERROR(horus_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+horus_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->phy_get = horus_phy_get;
+ p_api->phy_set = horus_phy_set;
+ p_api->reg_get = horus_reg_get;
+ p_api->reg_set = horus_reg_set;
+ p_api->reg_field_get = horus_reg_field_get;
+ p_api->reg_field_set = horus_reg_field_set;
+ p_api->dev_access_set= horus_access_mode_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+horus_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
+
diff --git a/src/hsl/horus/horus_stp.c b/src/hsl/horus/horus_stp.c
new file mode 100644
index 0000000..f907569
--- /dev/null
+++ b/src/hsl/horus/horus_stp.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_stp HORUS_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_stp.h"
+#include "horus_reg.h"
+
+#define HORUS_PORT_DISABLED 0
+#define HORUS_STP_BLOCKING 1
+#define HORUS_STP_LISTENING 2
+#define HORUS_STP_LEARNING 3
+#define HORUS_STP_FARWARDING 4
+
+static sw_error_t
+_horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ switch (state)
+ {
+ case FAL_STP_BLOKING:
+ val = HORUS_STP_BLOCKING;
+ break;
+ case FAL_STP_LISTENING:
+ val = HORUS_STP_LISTENING;
+ break;
+ case FAL_STP_LEARNING:
+ val = HORUS_STP_LEARNING;
+ break;
+ case FAL_STP_FARWARDING:
+ val = HORUS_STP_FARWARDING;
+ break;
+ case FAL_STP_DISABLED:
+ val = HORUS_PORT_DISABLED;
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ switch (val)
+ {
+ case HORUS_STP_BLOCKING:
+ *state = FAL_STP_BLOKING;
+ break;
+ case HORUS_STP_LISTENING:
+ *state = FAL_STP_LISTENING;
+ break;
+ case HORUS_STP_LEARNING:
+ *state = FAL_STP_LEARNING;
+ break;
+ case HORUS_STP_FARWARDING:
+ *state = FAL_STP_FARWARDING;
+ break;
+ case HORUS_PORT_DISABLED:
+ *state = FAL_STP_DISABLED;
+ break;
+ default:
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_stp_port_state_set(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_stp_port_state_get(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_stp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->stp_port_state_set = horus_stp_port_state_set;
+ p_api->stp_port_state_get = horus_stp_port_state_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/horus/horus_vlan.c b/src/hsl/horus/horus_vlan.c
new file mode 100644
index 0000000..97f52d2
--- /dev/null
+++ b/src/hsl/horus/horus_vlan.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup horus_vlan HORUS_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "horus_vlan.h"
+#include "horus_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+#define VLAN_NEXT_ENTRY 5
+#define VLAN_FIND_ENTRY 6
+
+static void
+horus_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+ a_uint32_t data;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->vid_pri_en = A_TRUE;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+ vlan_entry->vid_pri = data & 0xff;
+ }
+ else
+ {
+ vlan_entry->vid_pri_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+ vlan_entry->vid = data & 0xffff;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+ vlan_entry->mem_ports = data;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, LEARN_DIS, data, reg[1]);
+ if (1 == data)
+ {
+ vlan_entry->learn_dis = A_TRUE;
+ }
+ else
+ {
+ vlan_entry->learn_dis = A_FALSE;
+ }
+
+ return;
+}
+
+static sw_error_t
+horus_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+ if (A_TRUE == vlan_entry->learn_dis)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 1, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, LEARN_DIS, 0, reg[1]);
+ }
+
+ if (0 != vlan_entry->u_ports)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+horus_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ vt_busy = 1;
+ i = 0x1000;
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (!val)
+ {
+ if (VLAN_FIND_ENTRY == op)
+ return SW_NOT_FOUND;
+
+ if (VLAN_NEXT_ENTRY == op)
+ return SW_NO_MORE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ rv = horus_vlan_sw_to_hw(vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_vlan_create(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ /* set default value for VLAN_TABLE_FUNC1, all 0 */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_horus_vlan_next(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ horus_vlan_hw_to_sw(reg, p_vlan);
+
+ if (0 == p_vlan->vid)
+ return SW_NO_MORE;
+ else
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_find(a_uint32_t dev_id, a_uint16_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ horus_vlan_hw_to_sw(reg, p_vlan);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_horus_vlan_member_update(a_uint32_t dev_id, a_uint16_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ if (u_member != 0)
+ return SW_BAD_PARAM;
+
+ /* get vlan entry first */
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ /* set vlan member for VLAN_TABLE_FUNC1 */
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+ (a_uint8_t *) (&member), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ /* when update port member through LOAD opration, hardware will
+ return VT_FULL_VIO, we should ignore it */
+ if (SW_FULL == rv)
+ rv = SW_OK;
+
+ return rv;
+}
+
+static sw_error_t
+_horus_vlan_delete(a_uint32_t dev_id, a_uint16_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ reg = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = horus_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_member_update(dev_id, vlan_id, member, u_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+horus_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _horus_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+horus_vlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = horus_vlan_entry_append;
+ p_api->vlan_creat = horus_vlan_create;
+ p_api->vlan_member_update = horus_vlan_member_update;
+ p_api->vlan_delete = horus_vlan_delete;
+ p_api->vlan_next = horus_vlan_next;
+ p_api->vlan_find = horus_vlan_find;
+
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/hsl_acl.c b/src/hsl/hsl_acl.c
new file mode 100644
index 0000000..a660060
--- /dev/null
+++ b/src/hsl/hsl_acl.c
@@ -0,0 +1,963 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw_config.h"
+#include "aos_head.h"
+#include "sw_error.h"
+#include "shared_func.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+
+typedef struct
+{
+ a_uint32_t pri;
+ a_uint32_t addr;
+ a_uint32_t size;
+ a_uint32_t status;
+ a_uint32_t info;
+} hsl_acl_blk_t;
+
+typedef struct
+{
+ a_uint32_t used_blk;
+ a_uint32_t total_blk;
+ a_uint32_t free_rsc;
+ hsl_acl_blk_t *blk_ent;
+} hsl_acl_pool_t;
+
+#define MEM_FREE 1
+#define MEM_USED 2
+
+static hsl_acl_pool_t acl_pool[SW_MAX_NR_DEV];
+
+static sw_error_t
+_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx);
+
+static sw_error_t
+_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr);
+
+static sw_error_t _hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx);
+
+static sw_error_t
+_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset);
+
+static sw_error_t
+_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset);
+
+static sw_error_t
+_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size,
+ a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr,
+ a_uint32_t * f_size);
+
+static sw_error_t
+_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx,
+ a_uint32_t t_size, a_bool_t b_must,
+ a_uint32_t * f_idx, a_uint32_t * f_nr,
+ a_uint32_t * f_size);
+
+static sw_error_t
+_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri,
+ a_uint32_t size, a_uint32_t info, a_uint32_t * addr);
+
+static sw_error_t
+_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+ a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+ a_uint32_t new_size);
+
+static sw_error_t
+_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr,
+ a_uint32_t size);
+
+static sw_error_t
+_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size);
+
+static sw_error_t
+_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t info);
+
+//#define ACL_POOL_DEBUG
+#ifdef ACL_POOL_DEBUG
+static void
+_hsl_acl_blk_dump(a_uint32_t dev_id, const char *info)
+{
+ a_uint32_t i;
+
+ aos_printk("\n%s dev_id=%d free_rsc=%d total_blk=%d used_blk=%d",
+ info, dev_id, acl_pool[dev_id].free_rsc,
+ acl_pool[dev_id].total_blk, acl_pool[dev_id].used_blk);
+
+ for (i = 0; i < acl_pool[dev_id].used_blk; i++)
+ {
+ aos_printk("\naddr=%d status = %d size=%d list_id=%d list_pri=%d",
+ acl_pool[dev_id].blk_ent[i].addr,
+ acl_pool[dev_id].blk_ent[i].status,
+ acl_pool[dev_id].blk_ent[i].size,
+ acl_pool[dev_id].blk_ent[i].info,
+ acl_pool[dev_id].blk_ent[i].pri);
+ }
+ aos_printk("\n");
+}
+#else
+#define _hsl_acl_blk_dump(dev_id, info)
+#endif
+
+static sw_error_t
+_hsl_acl_blk_loc(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t * idx)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < acl_pool[dev_id].used_blk; i++)
+ {
+ if (addr == acl_pool[dev_id].blk_ent[i].addr)
+ {
+ *idx = i;
+ return SW_OK;
+ }
+ }
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_hsl_acl_blk_comb(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t nr)
+{
+ sw_error_t rv;
+ a_uint32_t i, size;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb before combine");
+
+ if ((idx + nr) > acl_pool[dev_id].used_blk)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (nr < 2)
+ {
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine");
+ return SW_OK;
+ }
+
+ size = 0;
+ for (i = 0; i < nr; i++)
+ {
+ size += acl_pool[dev_id].blk_ent[idx + i].size;
+ }
+ acl_pool[dev_id].blk_ent[idx].size = size;
+
+ rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + nr, nr - 1);
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_comb after combine");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_free_blk_comb(a_uint32_t dev_id, a_uint32_t idx)
+{
+ sw_error_t rv;
+ a_uint32_t first, num;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb before combine");
+
+ first = idx;
+ num = 1;
+ if (0 != idx)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[idx - 1].status)
+ {
+ num++;
+ first = idx - 1;
+ }
+ }
+
+ if ((acl_pool[dev_id].used_blk - 1) != idx)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[idx + 1].status)
+ {
+ num++;
+ }
+ }
+
+ rv = _hsl_acl_blk_comb(dev_id, first, num);
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_free_blk_comb after combine");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_ent_left_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset)
+{
+ a_uint32_t i;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv before move");
+
+ if (offset > idx)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = idx; i < acl_pool[dev_id].used_blk; i++)
+ {
+ acl_pool[dev_id].blk_ent[i - offset] = acl_pool[dev_id].blk_ent[i];
+ }
+
+ acl_pool[dev_id].used_blk -= offset;
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_left_mv after move");
+ return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_ent_right_mv(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t offset)
+{
+ a_uint32_t i, cnt, tmp;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv before move");
+
+ if (acl_pool[dev_id].total_blk < (acl_pool[dev_id].used_blk + offset))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* we support to increase used block number without block moving */
+ if (idx > acl_pool[dev_id].used_blk)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ cnt = acl_pool[dev_id].used_blk - idx;
+ tmp = acl_pool[dev_id].used_blk - 1;
+ for (i = 0; i < cnt; i++)
+ {
+ acl_pool[dev_id].blk_ent[tmp + offset - i]
+ = acl_pool[dev_id].blk_ent[tmp - i];
+ }
+
+ acl_pool[dev_id].used_blk += offset;
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_ent_right_mv after move");
+ return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_left_defrag(a_uint32_t dev_id, a_uint32_t p_idx, a_uint32_t t_size,
+ a_bool_t b_must, a_uint32_t * f_idx, a_uint32_t * f_nr,
+ a_uint32_t * f_size)
+{
+ sw_error_t rv;
+ a_int32_t idx;
+ a_uint32_t i, f_rsc, f_blk, dest_addr;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag before defrag");
+
+ f_rsc = 0;
+ for (idx = p_idx - 1; idx >= 0; idx--)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status)
+ {
+ f_rsc += acl_pool[dev_id].blk_ent[idx].size;
+ }
+
+ if (t_size <= f_rsc)
+ {
+ break;
+ }
+ }
+
+ if ((f_rsc < t_size) && (A_TRUE == b_must))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (0 == f_rsc)
+ {
+ *f_idx = p_idx;
+ *f_nr = 0;
+ *f_size = 0;
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag");
+ return SW_OK;
+ }
+
+ if (idx < 0)
+ {
+ idx = 0;
+ }
+
+ f_blk = 0;
+ f_rsc = 0;
+ dest_addr = acl_pool[dev_id].blk_ent[idx].addr;
+ for (i = idx; i < p_idx; i++)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+ {
+ f_blk += 1;
+ f_rsc += acl_pool[dev_id].blk_ent[i].size;
+ }
+
+ if (MEM_USED == acl_pool[dev_id].blk_ent[i].status)
+ {
+ if (dest_addr != acl_pool[dev_id].blk_ent[i].addr)
+ {
+ /* update acl rules hardware position */
+ rv = _hsl_acl_rule_copy(dev_id,
+ acl_pool[dev_id].blk_ent[i].addr,
+ dest_addr,
+ acl_pool[dev_id].blk_ent[i].size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_addr_update(dev_id,
+ acl_pool[dev_id].blk_ent[i].addr,
+ dest_addr,
+ acl_pool[dev_id].blk_ent[i].info);
+ SW_RTN_ON_ERROR(rv);
+
+ /* update acl memory block control infomation */
+ acl_pool[dev_id].blk_ent[i - f_blk] =
+ acl_pool[dev_id].blk_ent[i];
+ acl_pool[dev_id].blk_ent[i - f_blk].addr -= f_rsc;
+ }
+ dest_addr += acl_pool[dev_id].blk_ent[i].size;
+ }
+ }
+
+ for (i = p_idx - f_blk; i < p_idx; i++)
+ {
+ acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+ acl_pool[dev_id].blk_ent[i].addr = dest_addr;
+ acl_pool[dev_id].blk_ent[i].size = 0;
+ acl_pool[dev_id].blk_ent[i].info = 0;
+ acl_pool[dev_id].blk_ent[i].pri = 0;
+ }
+ acl_pool[dev_id].blk_ent[p_idx - f_blk].size = f_rsc;
+
+ *f_idx = p_idx - f_blk;
+ *f_nr = f_blk;
+ *f_size = f_rsc;
+ rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr,
+ f_rsc);
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_left_defrag after defrag");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_right_defrag(a_uint32_t dev_id, a_uint32_t p_idx,
+ a_uint32_t t_size, a_bool_t b_must,
+ a_uint32_t * f_idx, a_uint32_t * f_nr,
+ a_uint32_t * f_size)
+{
+ sw_error_t rv;
+ a_uint32_t i, cnt;
+ a_uint32_t idx, f_rsc, f_blk, dest_addr;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag before defrag");
+
+ f_rsc = 0;
+ for (idx = p_idx; idx < acl_pool[dev_id].used_blk; idx++)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[idx].status)
+ {
+ f_rsc += acl_pool[dev_id].blk_ent[idx].size;
+ }
+
+ if (t_size <= f_rsc)
+ {
+ break;
+ }
+ }
+
+ if ((f_rsc < t_size) && (A_TRUE == b_must))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (0 == f_rsc)
+ {
+ *f_idx = p_idx;
+ *f_nr = 0;
+ *f_size = 0;
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag");
+ return SW_OK;
+ }
+
+ if (idx >= acl_pool[dev_id].used_blk)
+ {
+ idx = acl_pool[dev_id].used_blk - 1;
+ }
+
+ f_blk = 0;
+ f_rsc = 0;
+ dest_addr = acl_pool[dev_id].blk_ent[idx].addr
+ + acl_pool[dev_id].blk_ent[idx].size;
+ for (cnt = 0; cnt <= (idx -p_idx); cnt++)
+ {
+ i = idx - cnt;
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+ {
+ f_blk += 1;
+ f_rsc += acl_pool[dev_id].blk_ent[i].size;
+ }
+
+ if (MEM_USED == acl_pool[dev_id].blk_ent[i].status)
+ {
+ dest_addr -= acl_pool[dev_id].blk_ent[i].size;
+
+ if (dest_addr != acl_pool[dev_id].blk_ent[i].addr)
+ {
+ /* update acl rules hardware position */
+ rv = _hsl_acl_rule_copy(dev_id,
+ acl_pool[dev_id].blk_ent[i].addr,
+ dest_addr,
+ acl_pool[dev_id].blk_ent[i].size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_addr_update(dev_id,
+ acl_pool[dev_id].blk_ent[i].addr,
+ dest_addr,
+ acl_pool[dev_id].blk_ent[i].info);
+ SW_RTN_ON_ERROR(rv);
+
+ /* update acl memory block control infomation */
+ acl_pool[dev_id].blk_ent[i + f_blk] =
+ acl_pool[dev_id].blk_ent[i];
+ acl_pool[dev_id].blk_ent[i + f_blk].addr += f_rsc;
+ }
+ }
+ }
+
+ for (i = p_idx; i < (p_idx + f_blk); i++)
+ {
+ acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+ acl_pool[dev_id].blk_ent[i].size = 0;
+ acl_pool[dev_id].blk_ent[i].addr = dest_addr - f_rsc;
+ }
+ acl_pool[dev_id].blk_ent[p_idx].size = f_rsc;
+
+ *f_idx = p_idx;
+ *f_nr = f_blk;
+ *f_size = f_rsc;
+ rv = _hsl_acl_rule_invalid(dev_id, acl_pool[dev_id].blk_ent[*f_idx].addr,
+ f_rsc);
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_right_defrag after defrag");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t free_idx, a_uint32_t pri,
+ a_uint32_t size, a_uint32_t info, a_uint32_t * addr)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ a_bool_t b_comb = A_FALSE;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc before alloc");
+
+ if (MEM_FREE != acl_pool[dev_id].blk_ent[free_idx].status)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (size > acl_pool[dev_id].blk_ent[free_idx].size)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (size != acl_pool[dev_id].blk_ent[free_idx].size)
+ {
+ b_comb = A_TRUE;
+ i = free_idx + 1;
+ rv = _hsl_acl_blk_ent_right_mv(dev_id, i, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_pool[dev_id].blk_ent[i].addr =
+ acl_pool[dev_id].blk_ent[free_idx].addr + size;
+ acl_pool[dev_id].blk_ent[i].size =
+ acl_pool[dev_id].blk_ent[free_idx].size - size;
+ acl_pool[dev_id].blk_ent[i].status = MEM_FREE;
+ acl_pool[dev_id].blk_ent[i].pri = 0;
+ acl_pool[dev_id].blk_ent[i].info = 0;
+ }
+
+ acl_pool[dev_id].blk_ent[free_idx].status = MEM_USED;
+ acl_pool[dev_id].blk_ent[free_idx].size = size;
+ acl_pool[dev_id].blk_ent[free_idx].pri = pri;
+ acl_pool[dev_id].blk_ent[free_idx].info = info;
+ acl_pool[dev_id].free_rsc -= size;
+
+ if (A_TRUE == b_comb)
+ {
+ /* try to combine neighbor free memory blocks */
+ rv = _hsl_acl_free_blk_comb(dev_id, free_idx + 1);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ *addr = acl_pool[dev_id].blk_ent[free_idx].addr;
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_alloc after alloc");
+ return SW_OK;
+}
+
+static sw_error_t
+_hsl_acl_blk_reduce(a_uint32_t dev_id, a_uint32_t idx, a_uint32_t new_size)
+{
+ sw_error_t rv;
+ a_uint32_t addr, old_size;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce before reduce");
+
+ addr = acl_pool[dev_id].blk_ent[idx].addr;
+ old_size = acl_pool[dev_id].blk_ent[idx].size;
+
+ rv = _hsl_acl_blk_ent_right_mv(dev_id, idx + 1, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_pool[dev_id].blk_ent[idx].size = new_size;
+ acl_pool[dev_id].blk_ent[idx + 1].status = MEM_FREE;
+ acl_pool[dev_id].blk_ent[idx + 1].addr = addr + new_size;
+ acl_pool[dev_id].blk_ent[idx + 1].size = old_size - new_size;
+ acl_pool[dev_id].blk_ent[idx + 1].pri = 0;
+ acl_pool[dev_id].blk_ent[idx + 1].info = 0;
+ acl_pool[dev_id].free_rsc += (old_size - new_size);
+
+ /* try to combine neighbor free blocks */
+ rv = _hsl_acl_free_blk_comb(dev_id, idx + 1);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_rule_invalid(dev_id, addr + new_size, old_size - new_size);
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_reduce after reduce");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_left_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+ a_uint32_t new_size)
+{
+ sw_error_t rv;
+ a_uint32_t old_size, old_addr, new_addr;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge before enlarge");
+
+ if (0 == idx)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (MEM_FREE != acl_pool[dev_id].blk_ent[idx - 1].status)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_size = acl_pool[dev_id].blk_ent[idx].size;
+ if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx - 1].size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_addr = acl_pool[dev_id].blk_ent[idx].addr;
+ new_addr = old_addr - (new_size - old_size);
+ rv = _hsl_acl_rule_copy(dev_id, old_addr, new_addr, old_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_rule_invalid(dev_id, new_addr + old_size, new_size - old_size);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_pool[dev_id].blk_ent[idx].size = new_size;
+ acl_pool[dev_id].blk_ent[idx].addr = new_addr;
+ acl_pool[dev_id].free_rsc -= (new_size - old_size);
+ rv = _hsl_acl_addr_update(dev_id, old_addr, new_addr,
+ acl_pool[dev_id].blk_ent[idx].info);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = SW_OK;
+ if ((new_size - old_size) == acl_pool[dev_id].blk_ent[idx - 1].size)
+ {
+ rv = _hsl_acl_blk_ent_left_mv(dev_id, idx, 1);
+ }
+ else
+ {
+ acl_pool[dev_id].blk_ent[idx - 1].size -= (new_size - old_size);
+ }
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_left_enlarge after enlarge");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_blk_right_enlarge(a_uint32_t dev_id, a_uint32_t idx,
+ a_uint32_t new_size)
+{
+ sw_error_t rv;
+ a_uint32_t old_size;
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge before enlarge");
+
+ if ((idx + 1) >= acl_pool[dev_id].used_blk)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (MEM_FREE != acl_pool[dev_id].blk_ent[idx + 1].status)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_size = acl_pool[dev_id].blk_ent[idx].size;
+ if ((new_size - old_size) > acl_pool[dev_id].blk_ent[idx + 1].size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ acl_pool[dev_id].blk_ent[idx].size = new_size;
+ acl_pool[dev_id].free_rsc -= (new_size - old_size);
+ rv = SW_OK;
+ if ((new_size - old_size) < acl_pool[dev_id].blk_ent[idx + 1].size)
+ {
+ acl_pool[dev_id].blk_ent[idx + 1].size -= (new_size - old_size);
+ acl_pool[dev_id].blk_ent[idx + 1].addr += (new_size - old_size);
+ }
+ else
+ {
+ if ((idx + 2) < acl_pool[dev_id].used_blk)
+ {
+ rv = _hsl_acl_blk_ent_left_mv(dev_id, idx + 2, 1);
+ }
+ }
+
+ _hsl_acl_blk_dump(dev_id, "_hsl_acl_blk_right_enlarge after enlarge");
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_addr, a_uint32_t dest_addr,
+ a_uint32_t size)
+{
+ hsl_acl_func_t * p_api;
+ sw_error_t rv;
+
+ p_api = hsl_acl_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_api);
+
+ if (NULL == p_api->acl_rule_copy)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_copy(dev_id, src_addr, dest_addr, size);
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t size)
+{
+ hsl_acl_func_t * p_api;
+ sw_error_t rv;
+
+ p_api = hsl_acl_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_api);
+
+ if (NULL == p_api->acl_rule_invalid)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_rule_invalid(dev_id, addr, size);
+ return rv;
+}
+
+static sw_error_t
+_hsl_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t info)
+{
+ hsl_acl_func_t * p_api;
+ sw_error_t rv;
+
+ p_api = hsl_acl_ptr_get(dev_id);
+ SW_RTN_ON_NULL(p_api);
+
+ if (NULL == p_api->acl_addr_update)
+ return SW_NOT_SUPPORTED;
+
+ rv = p_api->acl_addr_update(dev_id, old_addr, new_addr, info);
+ return rv;
+}
+
+sw_error_t
+hsl_acl_pool_creat(a_uint32_t dev_id, a_uint32_t blk_nr, a_uint32_t rsc_nr)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ acl_pool[dev_id].blk_ent = aos_mem_alloc(blk_nr * (sizeof (hsl_acl_blk_t)));
+ if (NULL == acl_pool[dev_id].blk_ent)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(acl_pool[dev_id].blk_ent, blk_nr * (sizeof (hsl_acl_blk_t)));
+
+ acl_pool[dev_id].used_blk = 1;
+ acl_pool[dev_id].total_blk = blk_nr;
+ acl_pool[dev_id].free_rsc = rsc_nr;
+
+ acl_pool[dev_id].blk_ent[0].addr = 0;
+ acl_pool[dev_id].blk_ent[0].size = rsc_nr;
+ acl_pool[dev_id].blk_ent[0].status = MEM_FREE;
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_pool_creat after creat");
+ return SW_OK;
+}
+
+sw_error_t
+hsl_acl_pool_destroy(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == acl_pool[dev_id].blk_ent)
+ {
+ return SW_FAIL;
+ }
+
+ aos_mem_free(acl_pool[dev_id].blk_ent);
+ aos_mem_zero(&acl_pool[dev_id], sizeof (hsl_acl_pool_t));
+ return SW_OK;
+}
+
+sw_error_t
+hsl_acl_blk_alloc(a_uint32_t dev_id, a_uint32_t pri, a_uint32_t size,
+ a_uint32_t info, a_uint32_t * addr)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ a_uint32_t blk_nr;
+ a_uint32_t p_idx, largest_idx, prev_f_s, largest_f_s;
+ a_uint32_t l_idx, l_nr, l_size, r_idx, r_nr, r_size;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc before alloc");
+
+ if (0 == size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (size > acl_pool[dev_id].free_rsc)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ blk_nr = acl_pool[dev_id].used_blk;
+
+ p_idx = 0;
+ prev_f_s = 0;
+ largest_f_s = 0;
+ largest_idx = 0;
+
+ for (i = 0; i < blk_nr; i++)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+ {
+ prev_f_s += acl_pool[dev_id].blk_ent[i].size;
+ continue;
+ }
+
+ p_idx = i;
+ if (pri <= acl_pool[dev_id].blk_ent[i].pri)
+ {
+ break;
+ }
+ }
+
+ if (i == blk_nr)
+ {
+ p_idx = blk_nr;
+ }
+
+ for (i = p_idx; i < blk_nr; i++)
+ {
+ if (MEM_FREE == acl_pool[dev_id].blk_ent[i].status)
+ {
+ if (largest_f_s < acl_pool[dev_id].blk_ent[i].size)
+ {
+ largest_idx = i;
+ largest_f_s = acl_pool[dev_id].blk_ent[i].size;
+ }
+ continue;
+ }
+
+ if (pri != acl_pool[dev_id].blk_ent[i].pri)
+ {
+ break;
+ }
+ }
+
+ if (largest_f_s >= size)
+ {
+ rv = _hsl_acl_blk_alloc(dev_id, largest_idx, pri, size, info,
+ addr);
+
+ }
+ else if (prev_f_s >= size)
+ {
+ rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_TRUE, &l_idx,
+ &l_nr, &l_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr);
+ }
+ else if ((acl_pool[dev_id].free_rsc - prev_f_s) >= size)
+ {
+ rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_TRUE, &r_idx,
+ &r_nr, &r_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_alloc(dev_id, r_idx, pri, size, info, addr);
+ }
+ else
+ {
+ rv = _hsl_acl_blk_left_defrag(dev_id, p_idx, size, A_FALSE, &l_idx,
+ &l_nr, &l_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_right_defrag(dev_id, p_idx, size, A_FALSE, &r_idx,
+ &r_nr, &r_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_comb(dev_id, l_idx, (l_nr + r_nr));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_alloc(dev_id, l_idx, pri, size, info, addr);
+ }
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_alloc after alloc");
+ return rv;
+}
+
+sw_error_t
+hsl_acl_blk_free(a_uint32_t dev_id, a_uint32_t addr)
+{
+ sw_error_t rv;
+ a_uint32_t idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free before free");
+
+ rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_pool[dev_id].blk_ent[idx].status = MEM_FREE;
+ acl_pool[dev_id].blk_ent[idx].pri = 0;
+ acl_pool[dev_id].blk_ent[idx].info = 0;
+ acl_pool[dev_id].free_rsc += acl_pool[dev_id].blk_ent[idx].size;
+
+ rv = _hsl_acl_rule_invalid(dev_id, addr, acl_pool[dev_id].blk_ent[idx].size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_free_blk_comb(dev_id, idx);
+ SW_RTN_ON_ERROR(rv);
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_free after free");
+ return SW_OK;
+}
+
+sw_error_t
+hsl_acl_blk_resize(a_uint32_t dev_id, a_uint32_t addr, a_uint32_t new_size)
+{
+ sw_error_t rv;
+ a_uint32_t idx, l_idx, l_nr, l_size, r_idx, r_nr, r_size, old_size;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize before resize");
+
+ rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (MEM_USED != acl_pool[dev_id].blk_ent[idx].status)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_size = acl_pool[dev_id].blk_ent[idx].size;
+ if (new_size == old_size)
+ {
+ return SW_OK;
+ }
+
+ if (0 == new_size)
+ {
+ rv = hsl_acl_blk_free(dev_id, addr);
+ return rv;
+ }
+
+ /* reduce acl memory block size */
+ if (new_size < old_size)
+ {
+ rv = _hsl_acl_blk_reduce(dev_id, idx, new_size);
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+ return rv;
+ }
+
+ /* enlarge acl memory block size */
+ if (acl_pool[dev_id].free_rsc < (new_size - old_size))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ rv = _hsl_acl_blk_left_defrag(dev_id, idx, new_size - old_size,
+ A_FALSE, &l_idx, &l_nr, &l_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_comb(dev_id, l_idx, l_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (l_size >= (new_size - old_size))
+ {
+ rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size);
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+ return rv;
+ }
+
+ if (idx >= (acl_pool[dev_id].used_blk - 1))
+ {
+ return SW_NO_RESOURCE;
+ }
+ rv = _hsl_acl_blk_right_defrag(dev_id, idx + 1, new_size - old_size,
+ A_FALSE, &r_idx, &r_nr, &r_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_comb(dev_id, r_idx, r_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_loc(dev_id, addr, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (r_size >= (new_size - old_size))
+ {
+ rv = _hsl_acl_blk_right_enlarge(dev_id, idx, new_size);
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+ return rv;
+ }
+
+ rv = _hsl_acl_blk_right_enlarge(dev_id, idx, old_size + r_size);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _hsl_acl_blk_left_enlarge(dev_id, idx, new_size);
+ _hsl_acl_blk_dump(dev_id, "hsl_acl_blk_resize after resize");
+ return rv;
+}
+
+sw_error_t
+hsl_acl_free_rsc_get(a_uint32_t dev_id, a_uint32_t * free_rsc)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ * free_rsc = acl_pool[dev_id].free_rsc;
+ return SW_OK;
+}
diff --git a/src/hsl/hsl_api.c b/src/hsl/hsl_api.c
new file mode 100644
index 0000000..2aef737
--- /dev/null
+++ b/src/hsl/hsl_api.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "hsl_api.h"
+
+static hsl_api_t hsl_api_table[SW_MAX_NR_DEV];
+
+hsl_api_t *
+hsl_api_ptr_get(a_uint32_t dev_id)
+{
+ if (dev_id >= SW_MAX_NR_DEV)
+ return NULL;
+
+ return &(hsl_api_table[dev_id]);
+}
+
+sw_error_t
+hsl_api_init(a_uint32_t dev_id)
+{
+ if (SW_MAX_NR_DEV <= dev_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_set(&hsl_api_table[dev_id], 0, sizeof (hsl_api_t));
+ return SW_OK;
+}
+
diff --git a/src/hsl/hsl_dev.c b/src/hsl/hsl_dev.c
new file mode 100644
index 0000000..691023a
--- /dev/null
+++ b/src/hsl/hsl_dev.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_lock.h"
+#include "sd.h"
+
+#if defined ATHENA
+#include "athena_init.h"
+#endif
+#if defined GARUDA
+#include "garuda_init.h"
+#endif
+#if defined SHIVA
+#include "shiva_init.h"
+#endif
+#if defined HORUS
+#include "horus_init.h"
+#endif
+#if defined ISIS
+#include "isis_init.h"
+#endif
+#if defined ISISC
+#include "isisc_init.h"
+#endif
+#include "sw_api.h"
+#ifdef KERNEL_MODULE
+#include "sw_api_ks.h"
+#else
+#include "sw_api_us.h"
+#endif
+
+static hsl_dev_t dev_table[SW_MAX_NR_DEV];
+static ssdk_init_cfg *dev_ssdk_cfg[SW_MAX_NR_DEV] = { 0 };
+ssdk_chip_type SSDK_CURRENT_CHIP_TYPE = CHIP_UNSPECIFIED;
+
+static sw_error_t hsl_set_current_chip_type(ssdk_chip_type chip_type)
+{
+ sw_error_t rv = SW_OK;
+
+ SSDK_CURRENT_CHIP_TYPE = chip_type;
+
+ if (SSDK_CURRENT_CHIP_TYPE == CHIP_UNSPECIFIED)
+ {
+#if defined ATHENA
+ SSDK_CURRENT_CHIP_TYPE = CHIP_ATHENA;
+#elif defined GARUDA
+ SSDK_CURRENT_CHIP_TYPE = CHIP_GARUDA;
+#elif defined SHIVA
+ SSDK_CURRENT_CHIP_TYPE = CHIP_SHIVA;
+#elif defined HORUS
+ SSDK_CURRENT_CHIP_TYPE = CHIP_HORUS;
+#elif defined ISIS
+ SSDK_CURRENT_CHIP_TYPE = CHIP_ISIS;
+#elif defined ISISC
+ SSDK_CURRENT_CHIP_TYPE = CHIP_ISISC;
+#else
+ rv = SW_FAIL;
+#endif
+ }
+ return rv;
+}
+
+hsl_dev_t *
+hsl_dev_ptr_get(a_uint32_t dev_id)
+{
+ if (dev_id >= SW_MAX_NR_DEV)
+ return NULL;
+
+ return &dev_table[dev_id];
+}
+
+hsl_acl_func_t *
+hsl_acl_ptr_get(a_uint32_t dev_id)
+{
+ if (dev_id >= SW_MAX_NR_DEV)
+ return NULL;
+
+ return &(dev_table[dev_id].acl_func);
+}
+
+sw_error_t
+hsl_dev_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ sw_error_t rv = SW_OK;
+
+ if (SW_MAX_NR_DEV <= dev_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_set(&dev_table[dev_id], 0, sizeof (hsl_dev_t));
+
+ SW_RTN_ON_ERROR(sd_init(dev_id,cfg));
+
+#ifdef UK_IF
+ SW_RTN_ON_ERROR(sw_uk_init(cfg->nl_prot));
+#endif
+
+#if defined API_LOCK
+ SW_RTN_ON_ERROR(hsl_api_lock_init());
+#endif
+ rv = hsl_set_current_chip_type(cfg->chip_type);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = SW_INIT_ERROR;
+ switch (cfg->chip_type)
+ {
+ case CHIP_ATHENA:
+#if defined ATHENA
+ rv = athena_init(dev_id, cfg);
+#endif
+ break;
+
+ case CHIP_GARUDA:
+#if defined GARUDA
+ rv = garuda_init(dev_id, cfg);
+#endif
+ break;
+
+ case CHIP_SHIVA:
+#if defined SHIVA
+ rv = shiva_init(dev_id, cfg);
+#endif
+ break;
+
+ case CHIP_HORUS:
+#if defined HORUS
+ rv = horus_init(dev_id, cfg);
+#endif
+ break;
+
+ case CHIP_ISIS:
+#if defined ISIS
+ rv = isis_init(dev_id, cfg);
+#endif
+ break;
+ case CHIP_ISISC:
+#if defined ISISC
+ rv = isisc_init(dev_id, cfg);
+#endif
+ break;
+
+ case CHIP_UNSPECIFIED:
+#if defined ATHENA
+ rv = athena_init(dev_id, cfg);
+#elif defined GARUDA
+ rv = garuda_init(dev_id, cfg);
+#elif defined SHIVA
+ rv = shiva_init(dev_id, cfg);
+#elif defined HORUS
+ rv = horus_init(dev_id, cfg);
+#elif defined ISIS
+ rv = isis_init(dev_id, cfg);
+#elif defined ISISC
+ rv = isisc_init(dev_id, cfg);
+#endif
+ break;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (NULL == dev_ssdk_cfg[dev_id])
+ {
+ dev_ssdk_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == dev_ssdk_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(dev_ssdk_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+#if defined UK_MINOR_DEV
+ dev_ssdk_cfg[dev_id]->nl_prot = UK_MINOR_DEV;
+#endif
+
+ return rv;
+}
+
+sw_error_t
+hsl_dev_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode, hsl_access_mode reg_mode)
+{
+ sw_error_t rv = SW_OK;
+
+ if (SW_MAX_NR_DEV <= dev_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_set(&dev_table[dev_id], 0, sizeof (hsl_dev_t));
+
+#if defined API_LOCK
+ SW_RTN_ON_ERROR(hsl_api_lock_init());
+#endif
+
+#if defined ATHENA
+ {
+ ssdk_init_cfg cfg = def_init_cfg;
+ cfg.reg_mode = reg_mode;
+ cfg.cpu_mode = cpu_mode;
+ rv = athena_init(dev_id, &cfg);
+ }
+#elif defined GARUDA
+ switch (cpu_mode)
+ {
+ case HSL_NO_CPU:
+ {
+ ssdk_init_cfg cfg = def_init_cfg_nocpu;
+ garuda_init_spec_cfg garuda_init_cfg = def_init_spec_cfg_nocpu;
+
+ cfg.chip_spec_cfg = &garuda_init_cfg;
+ cfg.reg_mode = reg_mode;
+ rv = garuda_init(dev_id, &cfg);
+ break;
+ }
+ case HSL_CPU_2:
+ {
+ ssdk_init_cfg cfg = def_init_cfg_cpu2;
+ garuda_init_spec_cfg garuda_init_cfg = def_init_spec_cfg_cpu2;
+
+ cfg.chip_spec_cfg = &garuda_init_cfg;
+ cfg.reg_mode = reg_mode;
+ rv = garuda_init(dev_id, &cfg);
+ break;
+ }
+ case HSL_CPU_1:
+ {
+ ssdk_init_cfg cfg = def_init_cfg_cpu1;
+ garuda_init_spec_cfg garuda_init_cfg = def_init_spec_cfg_cpu1;
+
+ cfg.chip_spec_cfg = &garuda_init_cfg;
+ cfg.reg_mode = reg_mode;
+ rv = garuda_init(dev_id, &cfg);
+ break;
+ }
+
+ case HSL_CPU_1_PLUS:
+ {
+ ssdk_init_cfg cfg = def_init_cfg_cpu1plus;
+ garuda_init_spec_cfg garuda_init_cfg = def_init_spec_cfg_cpu1plus;
+
+ cfg.chip_spec_cfg = &garuda_init_cfg;
+ cfg.reg_mode = reg_mode;
+ rv = garuda_init(dev_id, &cfg);
+ break;
+ }
+
+ default:
+ return SW_BAD_PARAM;
+ }
+#elif defined SHIVA
+ ssdk_init_cfg cfg = def_init_cfg;
+ cfg.reg_mode = reg_mode;
+ cfg.cpu_mode = cpu_mode;
+ rv = shiva_init(dev_id, &cfg);
+#endif
+
+ return rv;
+}
+
+sw_error_t
+hsl_ssdk_cfg(a_uint32_t dev_id, ssdk_cfg_t *ssdk_cfg)
+{
+ aos_mem_set(&(ssdk_cfg->init_cfg), 0, sizeof(ssdk_init_cfg));
+
+ aos_mem_copy(&(ssdk_cfg->init_cfg), dev_ssdk_cfg[dev_id], sizeof(ssdk_init_cfg));
+
+#ifdef VERSION
+ aos_mem_copy(ssdk_cfg->build_ver, VERSION, sizeof(VERSION));
+#endif
+
+#ifdef BUILD_DATE
+ aos_mem_copy(ssdk_cfg->build_date, BUILD_DATE, sizeof(BUILD_DATE));
+#endif
+
+ switch (dev_ssdk_cfg[dev_id]->chip_type)
+ {
+ case CHIP_ATHENA:
+ aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena"));
+ break;
+
+ case CHIP_GARUDA:
+ aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda"));
+ break;
+
+ case CHIP_SHIVA:
+ aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva"));
+ break;
+
+ case CHIP_HORUS:
+ aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus"));
+ break;
+
+ case CHIP_ISIS:
+ aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis"));
+ break;
+
+ case CHIP_ISISC:
+ aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc"));
+ break;
+
+ case CHIP_UNSPECIFIED:
+#if defined ATHENA
+ aos_mem_copy(ssdk_cfg->chip_type, "athena", sizeof("athena"));
+#elif defined GARUDA
+ aos_mem_copy(ssdk_cfg->chip_type, "garuda", sizeof("garuda"));
+#elif defined SHIVA
+ aos_mem_copy(ssdk_cfg->chip_type, "shiva", sizeof("shiva"));
+#elif defined HORUS
+ aos_mem_copy(ssdk_cfg->chip_type, "horus", sizeof("horus"));
+#elif defined ISIS
+ aos_mem_copy(ssdk_cfg->chip_type, "isis", sizeof("isis"));
+#elif defined ISISC
+ aos_mem_copy(ssdk_cfg->chip_type, "isisc", sizeof("isisc"));
+#endif
+ break;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+
+#ifdef CPU
+ aos_mem_copy(ssdk_cfg->cpu_type, CPU, sizeof(CPU));
+#endif
+
+#ifdef OS
+ aos_mem_copy(ssdk_cfg->os_info, OS, sizeof(OS));
+#if defined KVER26
+ aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.6", sizeof(" version 2.6"));
+#elif defined KVER24
+ aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version 2.4", sizeof(" version 2.4"));
+#else
+ aos_mem_copy(ssdk_cfg->os_info+sizeof(OS)-1, " version unknown", sizeof(" version unknown"));
+#endif
+#endif
+
+#ifdef HSL_STANDALONG
+ ssdk_cfg->fal_mod = A_FALSE;
+#else
+ ssdk_cfg->fal_mod = A_TRUE;
+#endif
+
+#ifdef USER_MODE
+ ssdk_cfg->kernel_mode = A_FALSE;
+#else
+ ssdk_cfg->kernel_mode = A_TRUE;
+#endif
+
+#ifdef UK_IF
+ ssdk_cfg->uk_if = A_TRUE;
+#else
+ ssdk_cfg->uk_if = A_FALSE;
+#endif
+
+#ifdef IN_ACL
+ ssdk_cfg->features.in_acl = A_TRUE;
+#endif
+#ifdef IN_FDB
+ ssdk_cfg->features.in_fdb = A_TRUE;
+#endif
+#ifdef IN_IGMP
+ ssdk_cfg->features.in_igmp = A_TRUE;
+#endif
+#ifdef IN_LEAKY
+ ssdk_cfg->features.in_leaky = A_TRUE;
+#endif
+#ifdef IN_LED
+ ssdk_cfg->features.in_led = A_TRUE;
+#endif
+#ifdef IN_MIB
+ ssdk_cfg->features.in_mib = A_TRUE;
+#endif
+#ifdef IN_MIRROR
+ ssdk_cfg->features.in_mirror = A_TRUE;
+#endif
+#ifdef IN_MISC
+ ssdk_cfg->features.in_misc = A_TRUE;
+#endif
+#ifdef IN_PORTCONTROL
+ ssdk_cfg->features.in_portcontrol = A_TRUE;
+#endif
+#ifdef IN_PORTVLAN
+ ssdk_cfg->features.in_portvlan = A_TRUE;
+#endif
+#ifdef IN_QOS
+ ssdk_cfg->features.in_qos = A_TRUE;
+#endif
+#ifdef IN_RATE
+ ssdk_cfg->features.in_rate = A_TRUE;
+#endif
+#ifdef IN_STP
+ ssdk_cfg->features.in_stp = A_TRUE;
+#endif
+#ifdef IN_VLAN
+ ssdk_cfg->features.in_vlan = A_TRUE;
+#endif
+#ifdef IN_REDUCED_ACL
+ ssdk_cfg->features.in_reduced_acl = A_TRUE;
+#endif
+#ifdef IN_IP
+ ssdk_cfg->features.in_ip = A_TRUE;
+#endif
+#ifdef IN_NAT
+ ssdk_cfg->features.in_nat = A_TRUE;
+#endif
+#ifdef IN_COSMAP
+ ssdk_cfg->features.in_cosmap = A_TRUE;
+#endif
+#ifdef IN_SEC
+ ssdk_cfg->features.in_sec = A_TRUE;
+#endif
+#ifdef IN_TRUNK
+ ssdk_cfg->features.in_trunk = A_TRUE;
+#endif
+#ifdef IN_NAT_HELPER
+ ssdk_cfg->features.in_nathelper= A_TRUE;
+#endif
+#ifdef IN_INTERFACECONTROL
+ ssdk_cfg->features.in_interfacectrl= A_TRUE;
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_dev_cleanup(void)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t dev_id;
+
+ for (dev_id = 0; dev_id < SW_MAX_NR_DEV; dev_id++)
+ {
+ if (dev_ssdk_cfg[dev_id])
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ if (p_api->dev_clean)
+ {
+ rv = p_api->dev_clean(dev_id);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ aos_mem_free(dev_ssdk_cfg[dev_id]);
+ dev_ssdk_cfg[dev_id] = NULL;
+ }
+ }
+
+#ifdef UK_IF
+ SW_RTN_ON_ERROR(sw_uk_cleanup());
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode)
+{
+ sw_error_t rv;
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ if (p_api->dev_access_set)
+ {
+ rv = p_api->dev_access_set(dev_id, reg_mode);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
diff --git a/src/hsl/hsl_lock.c b/src/hsl/hsl_lock.c
new file mode 100644
index 0000000..24d69ba
--- /dev/null
+++ b/src/hsl/hsl_lock.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+
+#ifdef KVER32
+aos_lock_t sw_hsl_api_lock;
+#else
+aos_lock_t sw_hsl_api_lock = aos_default_unlock;
+#endif
+
+sw_error_t
+hsl_api_lock_init(void)
+{
+ aos_lock_init(&sw_hsl_api_lock);
+ return SW_OK;
+}
diff --git a/src/hsl/hsl_port_prop.c b/src/hsl/hsl_port_prop.c
new file mode 100644
index 0000000..08bf127
--- /dev/null
+++ b/src/hsl/hsl_port_prop.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw_config.h"
+#include "aos_head.h"
+#include "sw_error.h"
+#include "shared_func.h"
+#include "fal_type.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+
+typedef struct
+{
+ a_uint32_t phy_id[SW_MAX_NR_PORT];
+ fal_pbmp_t dev_portmap;
+ fal_pbmp_t property[HSL_PP_BUTT];
+} port_info_t;
+
+static port_info_t *p_port_info[SW_MAX_NR_DEV] = { 0 };
+
+a_bool_t
+hsl_port_prop_check(a_uint32_t dev_id, fal_port_t port_id,
+ hsl_port_prop_t p_type)
+{
+ fal_pbmp_t pbitmap;
+
+ if (dev_id >= SW_MAX_NR_DEV)
+ return A_FALSE;
+
+ if (HSL_PP_BUTT <= p_type)
+ {
+ return A_FALSE;
+ }
+
+ pbitmap = p_port_info[dev_id]->property[p_type];
+
+ return SW_IS_PBMP_MEMBER(pbitmap, port_id);
+}
+
+a_bool_t
+hsl_mports_prop_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap,
+ hsl_port_prop_t p_type)
+{
+ fal_pbmp_t pbitmap;
+
+ if (dev_id >= SW_MAX_NR_DEV)
+ return A_FALSE;
+
+ if (HSL_PP_BUTT <= p_type)
+ {
+ return A_FALSE;
+ }
+
+ pbitmap = p_port_info[dev_id]->property[p_type];
+
+ return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap));
+}
+
+a_bool_t
+hsl_port_validity_check(a_uint32_t dev_id, fal_port_t port_id)
+{
+ fal_pbmp_t pbitmap;
+
+ if (dev_id >= SW_MAX_NR_DEV)
+ return A_FALSE;
+
+ pbitmap = p_port_info[dev_id]->dev_portmap;
+
+ return SW_IS_PBMP_MEMBER(pbitmap, port_id);
+}
+
+a_bool_t
+hsl_mports_validity_check(a_uint32_t dev_id, fal_pbmp_t port_bitmap)
+{
+ fal_pbmp_t pbitmap;
+
+ if (dev_id >= SW_MAX_NR_DEV)
+ return A_FALSE;
+
+ pbitmap = p_port_info[dev_id]->dev_portmap;
+
+ return (SW_IS_PBMP_INCLUDE(pbitmap, port_bitmap));
+}
+
+sw_error_t
+hsl_port_prop_set(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ if (HSL_PP_BUTT <= p_type)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_PBMP_ADD_PORT(p_port_info[dev_id]->property[p_type], port_id);
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_clr(a_uint32_t dev_id, fal_port_t port_id, hsl_port_prop_t p_type)
+{
+ HSL_DEV_ID_CHECK(dev_id);;
+
+ if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ if (HSL_PP_BUTT <= p_type)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_PBMP_DEL_PORT(p_port_info[dev_id]->property[p_type], port_id);
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_get_phyid(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * phy_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *phy_id = p_port_info[dev_id]->phy_id[port_id];
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_set_phyid(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t phy_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_validity_check(dev_id, port_id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ p_port_info[dev_id]->phy_id[port_id] = phy_id;
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_portmap_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (port_id > SW_MAX_NR_PORT)
+ return SW_OUT_OF_RANGE;
+
+ SW_PBMP_ADD_PORT(p_port_info[dev_id]->dev_portmap, port_id);
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_init_by_dev(a_uint32_t dev_id)
+{
+ port_info_t *p_mem;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ p_mem = aos_mem_alloc(sizeof (port_info_t));
+ if (p_mem == NULL)
+ return SW_OUT_OF_MEM;
+
+ aos_mem_zero(p_mem, sizeof (port_info_t));
+ p_port_info[dev_id] = p_mem;
+
+ return SW_OK;
+}
+
+sw_error_t
+hsl_port_prop_init(void)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < SW_MAX_NR_DEV; i++)
+ p_port_info[i] = NULL;
+
+ return SW_OK;
+}
diff --git a/src/hsl/isis/Makefile b/src/hsl/isis/Makefile
new file mode 100644
index 0000000..37bd2a2
--- /dev/null
+++ b/src/hsl/isis/Makefile
@@ -0,0 +1,129 @@
+LOC_DIR=src/hsl/isis
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=isis_reg_access.c isis_init.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += isis_acl.c isis_acl_parse.c isis_multicast_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += isis_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += isis_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += isis_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += isis_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += isis_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += isis_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += isis_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += isis_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += isis_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += isis_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += isis_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += isis_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += isis_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ SRC_LIST += isis_reduced_acl.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+ SRC_LIST += isis_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+ SRC_LIST += isis_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+ SRC_LIST += isis_nat.c
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+ SRC_LIST += nat_helper_dt.c
+ SRC_LIST += nat_helper_hsl.c
+# SRC_LIST += nat_ipt_helper.c
+ SRC_LIST += napt_helper.c
+ SRC_LIST += host_helper.c
+ SRC_LIST += nat_helper.c
+ SRC_LIST += napt_acl.c
+ SRC_LIST += napt_procfs.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+ SRC_LIST += isis_trunk.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+ SRC_LIST += isis_sec.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+ SRC_LIST += isis_interface_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_MACBLOCK))
+ SRC_LIST += isis_mac_block.c
+endif
+
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=isis_reg_access.c isis_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring ISIS, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+ifeq (ISISC, $(SUPPORT_CHIP))
+ SRC_LIST=
+endif
+
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/hsl/isis/isis_acl.c b/src/hsl/isis/isis_acl.c
new file mode 100644
index 0000000..bab6ef6
--- /dev/null
+++ b/src/hsl/isis/isis_acl.c
@@ -0,0 +1,1853 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_acl ISIS_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isis_acl.h"
+#include "isis_reg.h"
+#include "isis_acl_prv.h"
+
+//#define ISIS_ACL_DEBUG
+//#define ISIS_SW_ENTRY
+#define ISIS_HW_ENTRY
+
+static isis_acl_list_t *sw_list_ent[SW_MAX_NR_DEV];
+static isis_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV];
+
+static isis_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV];
+static isis_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV];
+#ifdef ISIS_SW_ENTRY
+static a_uint8_t *sw_filter_mem = NULL;
+#endif
+
+static sw_error_t
+_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag);
+
+static sw_error_t
+_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx,
+ a_uint32_t ports);
+
+static sw_error_t
+_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op);
+
+static sw_error_t
+_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op);
+
+static sw_error_t
+_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx);
+
+static void
+_isis_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+ isis_acl_list_t *sw_list;
+
+ aos_printk("\ndev_id=%d list control infomation:", dev_id);
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_list = &(sw_list_ent[dev_id][i]);
+ if (ENT_USED & sw_list->status)
+ {
+ aos_printk
+ ("\nlist_id=%02d list_pri=%02d rule_nr=%02d [pts_map]:0x%02x idx=%02d ",
+ sw_list->list_id, sw_list->list_pri, sw_list->rule_nr,
+ sw_list->bind_pts, i);
+ }
+ }
+ aos_printk("\n");
+}
+
+static void
+_isis_acl_sw_rule_dump(char *info, isis_acl_rule_t * sw_rule)
+{
+#ifdef ISIS_ACL_DEBUG
+ a_uint32_t flt_idx, i;
+
+ aos_printk("\n%s", info);
+ for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++)
+ {
+ aos_printk("\n%d software filter:", flt_idx);
+ aos_printk("\nact:");
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.msk[i]);
+ }
+
+ aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+ sw_rule[flt_idx].status,
+ sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id);
+
+ aos_printk("\n\n");
+ }
+#else
+ return;
+#endif
+}
+
+static isis_acl_list_t *
+_isis_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ if ((ENT_USED & sw_list_ent[dev_id][i].status)
+ && (list_id == sw_list_ent[dev_id][i].list_id))
+ {
+ return &(sw_list_ent[dev_id][i]);
+ }
+ }
+ return NULL;
+}
+
+static sw_error_t
+_isis_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag)
+{
+#ifdef ISIS_SW_ENTRY
+ hw_filter_t filter;
+
+ _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+ filter.msk[4] &= 0xfffffff8;
+ filter.msk[4] |= (flag & 0x7);
+
+ _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+#ifdef ISIS_HW_ENTRY
+ hw_filter_t filter;
+
+ filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+ filter.msk[4] &= 0xfffffff8;
+ filter.msk[4] |= (flag & 0x7);
+
+ _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+#else
+ sw_error_t rv;
+ a_uint32_t addr, data = 0;
+
+ /* read filter mask at first */
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter mask and modify it */
+ addr = ISIS_RULE_FUNC_ADDR + 20;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= 0xfffffff8;
+ data |= (flag & 0x7);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* write back filter mask */
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isis_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
+{
+#ifdef ISIS_SW_ENTRY
+ hw_filter_t filter;
+
+ _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+ filter.vlu[4] &= 0xffffff80;
+ filter.vlu[4] |= (ports & 0x7f);
+
+ _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+#ifdef ISIS_HW_ENTRY
+ hw_filter_t filter;
+
+ filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+ filter.vlu[4] &= 0xffffff80;
+ filter.vlu[4] |= (ports & 0x7f);
+
+ _isis_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+ sw_error_t rv;
+ a_uint32_t addr, data;
+
+ /* read filter value at first */
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter value and modify it */
+ addr = ISIS_RULE_FUNC_ADDR + 20;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= 0xffffff80;
+ data |= (ports & 0x7f);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* write back filter value */
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isis_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op)
+{
+ a_uint32_t i, addr, data, idx = 6;
+ sw_error_t rv;
+
+ if (ISIS_FILTER_ACT_OP == op)
+ {
+ idx = 4;
+ }
+
+ for (i = 1; i < idx; i++)
+ {
+ addr = ISIS_RULE_FUNC_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(reg[i - 1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op)
+{
+ a_uint32_t i, addr, data, idx = 6;
+ sw_error_t rv;
+
+ addr = ISIS_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISIS_FILTER_ACT_OP == op)
+ {
+ idx = 4;
+ }
+
+ for (i = 1; i < idx; i++)
+ {
+ addr = ISIS_RULE_FUNC_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(reg[i - 1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx)
+{
+#ifdef ISIS_SW_ENTRY
+ a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+ aos_mem_copy(tbl, filter, sizeof (hw_filter_t));
+#else
+#ifdef ISIS_HW_ENTRY
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->act[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#else
+ sw_error_t rv;
+
+ rv = _isis_filter_write(dev_id, &(filter->act[0]), flt_idx,
+ ISIS_FILTER_ACT_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_filter_write(dev_id, &(filter->vlu[0]), flt_idx,
+ ISIS_FILTER_VLU_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_filter_write(dev_id, &(filter->msk[0]), flt_idx,
+ ISIS_FILTER_MSK_OP);
+ SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx)
+{
+#ifdef ISIS_SW_ENTRY
+ a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+ aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
+#else
+#ifdef ISIS_HW_ENTRY
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = ISIS_FILTER_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISIS_FILTER_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISIS_FILTER_ACT_ADDR + (flt_idx << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->act[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#else
+ sw_error_t rv;
+
+ rv = _isis_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
+ ISIS_FILTER_VLU_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_filter_read(dev_id, &(filter->msk[0]), flt_idx,
+ ISIS_FILTER_MSK_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_filter_read(dev_id, &(filter->act[0]), flt_idx,
+ ISIS_FILTER_ACT_OP);
+ SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx,
+ a_uint32_t * dst_idx, isis_acl_rule_t * src_rule,
+ isis_acl_rule_t * dst_rule)
+{
+ a_uint32_t i, data, rule_id, list_id, list_pri;
+
+ rule_id = 0;
+ list_id = src_rule[*src_idx].list_id;
+ list_pri = src_rule[*src_idx].list_pri;
+
+ for (i = *src_idx; i < ISIS_MAX_FILTER; i++)
+ {
+ if (!(ENT_USED & src_rule[i].status))
+ {
+ continue; // was: break;
+ }
+
+ if (src_rule[i].list_id != list_id)
+ {
+ break;
+ }
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+ src_rule[i].filter.msk[4]);
+ if (!data)
+ {
+ continue;
+ }
+
+ if (ISIS_MAX_FILTER <= *dst_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (ENT_USED & dst_rule[*dst_idx].status)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data,
+ src_rule[i].filter.msk[4]);
+ if ((FLT_START == data) && (*dst_idx % 2))
+ {
+ if (*src_idx != i)
+ {
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id - 1;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ }
+
+ (*dst_idx)++;
+ if (ISIS_MAX_FILTER <= *dst_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (ENT_USED & dst_rule[*dst_idx].status)
+ {
+ return SW_NO_RESOURCE;
+ }
+ }
+
+ aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter),
+ sizeof (hw_filter_t));
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ if (ENT_DEACTIVE & src_rule[i].status)
+ {
+ dst_rule[*dst_idx].status |= ENT_DEACTIVE;
+ }
+ (*dst_idx)++;
+
+ if ((FLT_END == data) && (*dst_idx % 2))
+ {
+ if (ISIS_MAX_FILTER > *dst_idx)
+ {
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ (*dst_idx)++;
+ }
+ }
+
+ if ((FLT_END == data) || (FLT_STARTEND == data))
+ {
+ rule_id++;
+ }
+ }
+
+ *src_idx = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_alloc(a_uint32_t dev_id, isis_acl_list_t * sw_list,
+ a_uint32_t filter_nr)
+{
+ a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i;
+ a_uint32_t largest_nr, largest_idx;
+ sw_error_t rv;
+
+ /* calculate the proper location, [start_idx, end_idx) */
+ start_idx = 0;
+ end_idx = ISIS_MAX_FILTER;
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri)
+ {
+ start_idx = i + 1;
+ }
+ else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri)
+ {
+ end_idx = i;
+ break;
+ }
+ }
+ }
+
+ /* find the larget free filters block */
+ largest_nr = 0;
+ largest_idx = 0;
+ free_flt_nr = 0;
+ begin_idx = start_idx;
+ for (i = start_idx; i < end_idx; i++)
+ {
+ if (!(ENT_USED & sw_rule_ent[dev_id][i].status))
+ {
+ free_flt_nr++;
+ }
+ else
+ {
+ if (free_flt_nr > largest_nr)
+ {
+ largest_nr = free_flt_nr;
+ largest_idx = begin_idx;
+ }
+ free_flt_nr = 0;
+ begin_idx = i + 1;
+ }
+ }
+
+ if (free_flt_nr > largest_nr)
+ {
+ largest_nr = free_flt_nr;
+ largest_idx = begin_idx;
+ }
+
+ if ((!largest_nr) || ((largest_nr + 1) < filter_nr))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]),
+ sizeof (isis_acl_rule_t));
+ }
+ }
+
+ begin_idx = 0;
+ load_idx = largest_idx;
+ rv = _isis_acl_list_insert(dev_id, &begin_idx, &load_idx,
+ hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+ return rv;
+}
+
+static sw_error_t
+_isis_acl_rule_reorder(a_uint32_t dev_id, isis_acl_list_t * sw_list)
+{
+ a_uint32_t i, src_idx, dst_idx;
+ sw_error_t rv;
+
+ dst_idx = 0;
+ for (i = 0; i < ISIS_MAX_FILTER;)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri)
+ {
+ rv = _isis_acl_list_insert(dev_id, &i, &dst_idx,
+ sw_rule_ent[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ break;
+ }
+ }
+ else
+ {
+ i++;
+ }
+ }
+
+ src_idx = 0;
+ rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ for (; i < ISIS_MAX_FILTER;)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ rv = _isis_acl_list_insert(dev_id, &i, &dst_idx,
+ sw_rule_ent[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ i++;
+ }
+ }
+
+ return SW_OK;
+}
+
+static void
+_isis_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr)
+{
+ a_uint32_t i, data;
+
+ for (i = flt_idx; i < (flt_idx + flt_nr); i++)
+ {
+ if (aos_mem_cmp
+ (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+ sizeof (isis_acl_rule_t)))
+ {
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+ sw_rule_tmp[dev_id][i].filter.msk[4]);
+ if (data)
+ {
+ _isis_filter_down_to_hw(dev_id,
+ &(sw_rule_tmp[dev_id][i].filter), i);
+ }
+ else
+ {
+ _isis_filter_valid_set(dev_id, i, 0);
+ }
+
+ aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+ sizeof (isis_acl_rule_t));
+ }
+ }
+}
+
+static sw_error_t
+_isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+ a_uint32_t i, loc = ISIS_MAX_FILTER;
+ isis_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((ISIS_MAX_LIST_ID < list_id) || (ISIS_MAX_LIST_PRI < list_pri))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_list = &(sw_list_ent[dev_id][i]);
+ if (ENT_USED & sw_list->status)
+ {
+ if (list_id == sw_list->list_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+ else
+ {
+ loc = i;
+ }
+ }
+
+ if (ISIS_MAX_FILTER == loc)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ sw_list = &(sw_list_ent[dev_id][loc]);
+ aos_mem_zero(sw_list, sizeof (isis_acl_list_t));
+ sw_list->list_id = list_id;
+ sw_list->list_pri = list_pri;
+ sw_list->status |= ENT_USED;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ isis_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (0 != sw_list->bind_pts)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (0 != sw_list->rule_nr)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(sw_list, sizeof (isis_acl_list_t));
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ isis_acl_list_t *sw_list;
+ isis_acl_rule_t *sw_rule;
+ a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if ((0 == rule_nr) || (NULL == rule))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (rule_id != sw_list->rule_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_flt_idx = 0;
+ old_flt_nr = 0;
+ free_flt_nr = 0;
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ if (sw_rule->list_id == sw_list->list_id)
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule,
+ sizeof (isis_acl_rule_t));
+ if (!old_flt_nr)
+ {
+ old_flt_idx = i;
+ }
+ old_flt_nr++;
+ }
+ }
+ else
+ {
+ free_flt_nr++;
+ }
+ }
+
+ if (!free_flt_nr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ /* parse rule entry and alloc rule resource */
+ new_flt_nr = old_flt_nr;
+ for (i = 0; i < rule_nr; i++)
+ {
+ rv = _isis_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id],
+ &new_flt_nr);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if (free_flt_nr < (new_flt_nr - old_flt_nr))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = old_flt_nr; i < new_flt_nr; i++)
+ {
+ hw_rule_tmp[dev_id][i].status |= ENT_USED;
+ hw_rule_tmp[dev_id][i].list_id = sw_list->list_id;
+ hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri;
+ bind_pts = sw_list->bind_pts;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts,
+ (hw_rule_tmp[dev_id][i].filter.vlu[4]));
+ }
+
+ for (i = 0; i < old_flt_nr; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]);
+ sw_rule->status &= (~ENT_USED);
+ sw_rule->status |= (ENT_TMP);
+ }
+
+ rv = _isis_acl_rule_alloc(dev_id, sw_list, new_flt_nr);
+ if (SW_OK != rv)
+ {
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+ rv = _isis_acl_rule_reorder(dev_id, sw_list);
+ }
+
+ for (i = 0; i < old_flt_nr; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]);
+ sw_rule->status |= (ENT_USED);
+ sw_rule->status &= (~ENT_TMP);
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_acl_rule_sync(dev_id, 0, ISIS_MAX_FILTER);
+ sw_list->rule_nr += rule_nr;
+
+ _isis_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ isis_acl_rule_t *sw_rule;
+ isis_acl_list_t *sw_list;
+ a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->rule_nr < (rule_id + rule_nr))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id))
+ {
+ if (!flt_nr)
+ {
+ flt_idx = i;
+ }
+
+ if ((sw_rule->rule_id >= rule_id)
+ && (sw_rule->rule_id < (rule_id + rule_nr)))
+ {
+ del_nr++;
+ }
+ else
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule,
+ sizeof (isis_acl_rule_t));
+ }
+ flt_nr++;
+ }
+ }
+
+ if (!del_nr)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ _isis_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ break;
+ }
+ }
+
+ if (i != flt_nr)
+ {
+ src_idx = flt_idx + i;
+ dst_idx = flt_idx;
+ rv = _isis_acl_list_insert(dev_id, &src_idx, &dst_idx,
+ hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ _isis_acl_rule_sync(dev_id, flt_idx, flt_nr);
+ sw_list->rule_nr -= rule_nr;
+
+ _isis_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ isis_acl_rule_t *sw_rule;
+ a_uint32_t flt_nr = 0, i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISIS_HW_RULE_TMP_CNT * sizeof (isis_acl_rule_t));
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id))
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule,
+ sizeof (isis_acl_rule_t));
+ flt_nr++;
+ }
+ }
+ }
+
+ if (!flt_nr)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+ rv = _isis_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr);
+ return rv;
+}
+
+static sw_error_t
+_isis_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ isis_acl_rule_t *sw_rule;
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id)
+ && (!(ENT_DEACTIVE & sw_rule->status)))
+ {
+ rv = _isis_filter_ports_bind(dev_id, i, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+ (sw_rule->filter.vlu[4]));
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t ports;
+ isis_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->bind_pts & (0x1 << obj_idx))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ ports = (sw_list->bind_pts) | (0x1 << obj_idx);
+ rv = _isis_acl_rule_bind(dev_id, list_id, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ sw_list->bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t ports;
+ isis_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (!(sw_list->bind_pts & (0x1 << obj_idx)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx));
+ rv = _isis_acl_rule_bind(dev_id, list_id, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ sw_list->bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_UDF_MAX_OFFSET < offset)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_UDF_MAX_OFFSET < length)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ switch (udf_type)
+ {
+ case FAL_ACL_UDF_TYPE_L2:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L4:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L2_SNAP:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3_PLUS:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg);
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ switch (udf_type)
+ {
+ case FAL_ACL_UDF_TYPE_L2:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L4:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L2_SNAP:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3_PLUS:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active)
+{
+ sw_error_t rv;
+ a_uint32_t i, ports;
+ isis_acl_list_t *sw_list;
+ isis_acl_rule_t *sw_rule;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_list = _isis_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->rule_nr < (rule_id + rule_nr))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == active)
+ {
+ ports = (sw_list->bind_pts);
+ }
+ else
+ {
+ ports = 0;
+ }
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id)
+ && (rule_id <= sw_rule->rule_id)
+ && ((rule_id + rule_nr) > sw_rule->rule_id))
+ {
+ rv = _isis_filter_ports_bind(dev_id, i, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+ (sw_rule->filter.vlu[4]));
+
+ if (A_TRUE == active)
+ {
+ sw_rule->status &= (~ENT_DEACTIVE);
+ }
+ else
+ {
+ sw_rule->status |= (ENT_DEACTIVE);
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isis_acl_list_dump(a_uint32_t dev_id)
+{
+ _isis_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isis_acl_rule_dump(a_uint32_t dev_id)
+{
+ a_uint32_t flt_idx, i;
+ sw_error_t rv;
+ hw_filter_t filter;
+
+ aos_printk("\nisis_acl_rule_dump:\n");
+
+ for (flt_idx = 0; flt_idx < ISIS_MAX_FILTER; flt_idx++)
+ {
+ aos_mem_zero(&filter, sizeof (hw_filter_t));
+
+ rv = _isis_filter_up_to_sw(dev_id, &filter, flt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\n%d filter dump:", flt_idx);
+
+ aos_printk("\nhardware content:");
+ aos_printk("\nact:");
+ for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.msk[i]);
+ }
+
+ aos_printk("\nsoftware content:");
+ aos_printk("\nact:");
+ for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]);
+ }
+
+ aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+ sw_rule_ent[dev_id][flt_idx].status,
+ sw_rule_ent[dev_id][flt_idx].list_id,
+ sw_rule_ent[dev_id][flt_idx].rule_id);
+
+ aos_printk("\n\n");
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_acl_reset(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_zero(sw_list_ent[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_list_t));
+
+ aos_mem_zero(sw_rule_ent[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+ return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details Comments:
+ * If the value of list_pri is more small then the priority is more high,
+ * that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_list_creat(dev_id, list_id, list_pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_list_destroy(dev_id, list_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_rule_query(dev_id, list_id, rule_id, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL a_uint32_t
+isis_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id)
+{
+ a_uint32_t i, pos=0;
+ isis_acl_rule_t *sw_rule;
+
+ for (i = 0; i < ISIS_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[0][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id)
+ && (!(ENT_DEACTIVE & sw_rule->status)))
+ {
+ pos = i;
+ break;
+
+ }
+ }
+
+ return pos;
+}
+
+
+HSL_LOCAL sw_error_t
+isis_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act)
+{
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_LIST_ID < pos)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_rule_ent[dev_id][pos].filter.act[1] = act[1];
+ sw_rule_ent[dev_id][pos].filter.act[2] = act[2];
+
+ sw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+ sw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+ hw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+ hw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+
+ return SW_OK;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+ length);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+ length);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_acl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_list_ent[dev_id] =
+ (isis_acl_list_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+ sizeof (isis_acl_list_t));
+ if (NULL == sw_list_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_list_ent[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_list_t));
+
+ sw_rule_ent[dev_id] =
+ (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+ sizeof (isis_acl_rule_t));
+ if (NULL == sw_rule_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_rule_ent[dev_id],
+ ISIS_MAX_FILTER * sizeof (isis_acl_rule_t));
+
+ hw_rule_tmp[dev_id] =
+ (isis_acl_rule_t *) aos_mem_alloc(ISIS_HW_RULE_TMP_CNT *
+ sizeof (isis_acl_rule_t));
+ if (NULL == hw_rule_tmp[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ sw_rule_tmp[dev_id] =
+ (isis_acl_rule_t *) aos_mem_alloc(ISIS_MAX_FILTER *
+ sizeof (isis_acl_rule_t));
+ if (NULL == sw_rule_tmp[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+#ifdef ISIS_SW_ENTRY
+ sw_filter_mem = aos_mem_alloc(ISIS_MAX_FILTER * sizeof (hw_filter_t));
+ if (NULL == sw_filter_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_filter_mem, ISIS_MAX_FILTER * sizeof (hw_filter_t));
+#endif
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->acl_list_creat = isis_acl_list_creat;
+ p_api->acl_list_destroy = isis_acl_list_destroy;
+ p_api->acl_list_bind = isis_acl_list_bind;
+ p_api->acl_list_unbind = isis_acl_list_unbind;
+ p_api->acl_rule_add = isis_acl_rule_add;
+ p_api->acl_rule_delete = isis_acl_rule_delete;
+ p_api->acl_rule_query = isis_acl_rule_query;
+ p_api->acl_status_set = isis_acl_status_set;
+ p_api->acl_status_get = isis_acl_status_get;
+ p_api->acl_list_dump = isis_acl_list_dump;
+ p_api->acl_rule_dump = isis_acl_rule_dump;
+ p_api->acl_port_udf_profile_set = isis_acl_port_udf_profile_set;
+ p_api->acl_port_udf_profile_get = isis_acl_port_udf_profile_get;
+ p_api->acl_rule_active = isis_acl_rule_active;
+ p_api->acl_rule_deactive = isis_acl_rule_deactive;
+ p_api->acl_rule_get_offset = isis_acl_rule_get_offset;
+ p_api->acl_rule_sync_multi_portmap = isis_acl_rule_sync_multi_portmap;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_acl_parse.c b/src/hsl/isis/isis_acl_parse.c
new file mode 100644
index 0000000..6a1bdde
--- /dev/null
+++ b/src/hsl/isis/isis_acl_parse.c
@@ -0,0 +1,2440 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isis_acl.h"
+#include "isis_reg.h"
+#include "isis_acl_prv.h"
+
+#define DAH 0x1
+#define SAH 0x2
+#define TAG 0x4
+#define STAG 0x8
+#define CTAG 0x10
+
+typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw,
+ hw_filter_t * hw_filter_snap,
+ a_bool_t * b_care);
+
+static a_bool_t
+_isis_acl_zero_addr(const fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+ return A_TRUE;
+}
+
+static a_bool_t
+_isis_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu)
+{
+ if (FAL_ACL_FIELD_MASK == op)
+ {
+ if (0 == mask)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_RANGE == op)
+ {
+ if ((0 == val) && (chkvlu == mask))
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_LE == op)
+ {
+ if (chkvlu == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_GE == op)
+ {
+ if (0 == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_NE == op)
+ {
+ return A_TRUE;
+ }
+
+ return A_TRUE;
+}
+
+static sw_error_t
+_isis_acl_rule_bmac_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_MAC_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_SET(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_SET(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+
+ FIELD_SET(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_SET(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ if (0x0 != sw->tagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tagged_val &= sw->tagged_mask;
+ FIELD_SET(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+ FIELD_SET(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ if (0x0 != sw->up_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->up_val &= sw->up_mask;
+ FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+ FIELD_SET(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+ }
+
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+ && (FAL_ACL_FIELD_LE != sw->vid_op)
+ && (FAL_ACL_FIELD_GE != sw->vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->vid_op)
+ {
+ sw->vid_val &= sw->vid_mask;
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->vid_op)
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, 0);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_val);
+ }
+ else
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, 0xfff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ if (0x0 != sw->cfi_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->cfi_val &= sw->cfi_mask;
+ FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+ FIELD_SET(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ehmac_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+ a_bool_t da_h = A_FALSE, sa_h = A_FALSE;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_EHMAC_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->dest_mac_mask.uc[i])
+ {
+ da_h = A_TRUE;
+ break;
+ }
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->src_mac_mask.uc[i])
+ {
+ sa_h = A_TRUE;
+ break;
+ }
+ }
+ }
+
+ /* if sa_h and da_h both are true need't process mac address fileds */
+ if ((A_TRUE == da_h) && ((A_TRUE == sa_h)))
+ {
+ da_h = A_FALSE;
+ sa_h = A_FALSE;
+ }
+
+ if (A_TRUE == da_h)
+ {
+ FIELD_SET(EHMAC_RUL_V3, DA_EN, 1);
+
+ if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_SET(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ }
+ }
+
+ if (A_TRUE == sa_h)
+ {
+ if (A_TRUE != _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]);
+
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+ FIELD_SET(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_SET(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ }
+
+ /* Process Stag Fields */
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+ {
+ if (0x0 != sw->stagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stagged_val &= sw->stagged_mask;
+ FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+ FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+ }
+
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_LE != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_GE != sw->stag_vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+ sw->stag_vid_mask, 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->stag_vid_op)
+ {
+ sw->stag_vid_val &= sw->stag_vid_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->stag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val);
+
+ }
+ else
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, 0xfff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+ {
+ if (0x0 != sw->stag_pri_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stag_pri_val &= sw->stag_pri_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+ {
+ if (0x0 != sw->stag_dei_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stag_dei_val &= sw->stag_dei_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+ }
+
+ /* Process Ctag Fields */
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+ {
+ if (0x0 != sw->ctagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctagged_val &= sw->ctagged_mask;
+ FIELD_SET(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+ FIELD_SET(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+ }
+
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_LE != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_GE != sw->ctag_vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+ sw->ctag_vid_mask, 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op)
+ {
+ sw->ctag_vid_val &= sw->ctag_vid_mask;
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0);
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8));
+
+ }
+ else
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, 0xff);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, 0xf);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+ {
+ if (0x0 != sw->ctag_pri_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctag_pri_val &= sw->ctag_pri_mask;
+ FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+ {
+ if (0x0 != sw->ctag_cfi_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctag_cfi_val &= sw->ctag_cfi_mask;
+ FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static void
+_isis_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac,
+ a_bool_t * eh_mac)
+{
+ a_uint32_t bm = 0, i, tmp;
+
+ *b_mac = A_FALSE;
+ *eh_mac = A_FALSE;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->dest_mac_mask.uc[i])
+ {
+ bm |= DAH;
+ break;
+ }
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->src_mac_mask.uc[i])
+ {
+ bm |= SAH;
+ break;
+ }
+ }
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ tmp |= ((sw->tagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ tmp |= ((sw->up_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ tmp |= ((sw->cfi_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= TAG;
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+ {
+ tmp |= ((sw->stagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+ {
+ tmp |= ((sw->stag_pri_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+ {
+ tmp |= ((sw->stag_dei_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+ {
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+ sw->stag_vid_mask, 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= STAG;
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+ {
+ tmp |= ((sw->ctagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+ {
+ tmp |= ((sw->ctag_pri_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+ {
+ tmp |= ((sw->ctag_cfi_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+ {
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+ sw->ctag_vid_mask, 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= CTAG;
+ }
+
+ if ((bm & CTAG) || (bm & STAG))
+ {
+ *eh_mac = A_TRUE;
+ }
+
+ if ((bm & TAG) || ((bm & DAH) && (bm & SAH)))
+ {
+ *b_mac = A_TRUE;
+ }
+}
+
+static sw_error_t
+_isis_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_IP4_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+ FIELD_SET(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+ FIELD_SET(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+ {
+ if (0x0 != sw->src_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->src_ip4_val &= sw->src_ip4_mask;
+ hw->vlu[1] = sw->src_ip4_val;
+ hw->msk[1] = sw->src_ip4_mask;
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+ {
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->dest_ip4_val &= sw->dest_ip4_mask;
+ hw->vlu[0] = sw->dest_ip4_val;
+ hw->msk[0] = sw->dest_ip4_mask;
+ }
+
+ if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, 0xffff);
+ }
+ }
+
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, 0xffff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ {
+ if (0x0 != sw->icmp_type_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+ sw->icmp_type_val &= sw->icmp_type_mask;
+ FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+ FIELD_SET(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+ {
+ if (0x0 != sw->icmp_code_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+ sw->icmp_code_val &= sw->icmp_code_mask;
+ FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+ FIELD_SET(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+ {
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tcp_flag_val &= sw->tcp_flag_mask;
+ FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+ FIELD_SET(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1))
+ {
+ if (0x0 != sw->ripv1_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ripv1_val &= sw->ripv1_mask;
+ FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+ FIELD_SET(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4))
+ {
+ if (0x0 != sw->dhcpv4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dhcpv4_val &= sw->dhcpv4_mask;
+ FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+ FIELD_SET(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_IP6R1_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_IP6R2_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_IP6R3_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+ {
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip6_lable_val &= sw->ip6_lable_mask;
+ FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+ FIELD_SET(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+ FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16));
+ FIELD_SET(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16));
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+ FIELD_SET(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+ FIELD_SET(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+ }
+
+ if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isis_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val);
+
+ }
+ else
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, 0xffff);
+ }
+ }
+
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isis_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, 0xffff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ {
+ if (0x0 != sw->icmp_type_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+ sw->icmp_type_val &= sw->icmp_type_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+ FIELD_SET(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+ {
+ if (0x0 != sw->icmp_code_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+ sw->icmp_code_val &= sw->icmp_code_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+ FIELD_SET(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+ {
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tcp_flag_val &= sw->tcp_flag_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+ FIELD_SET(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6))
+ {
+ if (0x0 != sw->dhcpv6_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dhcpv6_val &= sw->dhcpv6_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+ FIELD_SET(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_udf_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISIS_UDF_FILTER);
+
+ if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+ {
+ if (FAL_ACL_RULE_UDF == sw->rule_type)
+ {
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+ *b_care = A_TRUE;
+ }
+ return SW_OK;
+ }
+
+ if (ISIS_MAX_UDF_LENGTH < sw->udf_len)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *b_care = A_TRUE;
+ for (i = 0; i < sw->udf_len; i++)
+ {
+ hw->vlu[3 - i / 4] |=
+ ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+ hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i));
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ hw_filter_t * hw)
+{
+ fal_pbmp_t des_pts;
+
+ aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+ /* FAL_ACL_ACTION_PERMIT need't process */
+
+ /* we should ignore any other action flags when DENY bit is settd. */
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x7);
+ return SW_OK;
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x3);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+ {
+ FIELD_SET(ACL_RSLT2, MIRR_EN, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ FIELD_SET(ACL_RSLT2, DES_PORT_EN, 1);
+
+ des_pts = (sw->ports >> 3) & 0xf;
+ FIELD_SET(ACL_RSLT2, DES_PORT1, des_pts);
+
+ des_pts = sw->ports & 0x7;
+ FIELD_SET(ACL_RSLT1, DES_PORT0, des_pts);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+ {
+ FIELD_SET(ACL_RSLT1, PRI_QU_EN, 1);
+ FIELD_SET(ACL_RSLT1, PRI_QU, sw->queue);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+ {
+ FIELD_SET(ACL_RSLT1, DSCPV, sw->dscp);
+ FIELD_SET(ACL_RSLT1, DSCP_REMAP, 1);
+ }
+
+ FIELD_SET(ACL_RSLT0, STAGVID, sw->stag_vid);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+ {
+ FIELD_SET(ACL_RSLT1, TRANS_SVID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+ {
+ FIELD_SET(ACL_RSLT0, STAGPRI, sw->stag_pri);
+ FIELD_SET(ACL_RSLT1, STAG_PRI_REMAP, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+ {
+ FIELD_SET(ACL_RSLT0, STAGDEI, sw->stag_dei);
+ FIELD_SET(ACL_RSLT1, STAG_DEI_CHG, 1);
+ }
+
+ FIELD_SET(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+ {
+ FIELD_SET(ACL_RSLT1, TRANS_CVID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+ {
+ FIELD_SET(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+ FIELD_SET(ACL_RSLT1, CTAG_PRI_REMAP, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+ {
+ FIELD_SET(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+ FIELD_SET(ACL_RSLT1, CTAG_CFI_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+ {
+ FIELD_SET(ACL_RSLT1, LOOK_VID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN))
+ {
+ FIELD_SET(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+ FIELD_SET(ACL_RSLT2, POLICER_EN, 1);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+ {
+ FIELD_SET(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+ FIELD_SET(ACL_RSLT1, ARP_PTR_EN, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))
+ {
+ FIELD_SET(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+ FIELD_SET(ACL_RSLT1, WCMP_EN, 1);
+ FIELD_SET(ACL_RSLT1, ARP_PTR_EN, 1);
+ }
+
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x0);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+ {
+ if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x1);
+ }
+ else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x2);
+ }
+ else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x3);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+ {
+ FIELD_SET(ACL_RSLT2, EG_BYPASS, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+ {
+ FIELD_SET(ACL_RSLT2, TRIGGER_INTR, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en;
+
+ /* destnation mac address */
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_GET(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_GET(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+ if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ /* source mac address */
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_GET(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_GET(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ /* ethernet type */
+ FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_GET(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet tagged */
+ FIELD_GET(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+ FIELD_GET(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+ if (0x0 != sw->tagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+ }
+
+ /* vlan priority */
+ FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+ FIELD_GET(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+ if (0x0 != sw->up_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+ }
+
+ /* vlanid */
+ FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_GET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ FIELD_GET(MAC_RUL_M4, VIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+ (a_uint32_t) sw->vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+ }
+
+ /* vlan cfi */
+ FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+ FIELD_GET(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+ if (0x0 != sw->cfi_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i, mask_en, data;
+
+ FIELD_GET(EHMAC_RUL_V3, DA_EN, data);
+ if (data)
+ {
+ for (i = 2; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+ sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+ sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+ }
+
+ if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_GET(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+
+ if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+ }
+ else
+ {
+ for (i = 2; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+ sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+ sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+ }
+
+ if (A_FALSE == _isis_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+ FIELD_GET(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ if (A_FALSE == _isis_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+ }
+
+ /* ethernet type */
+ FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_GET(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet stagged */
+ FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+ FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+ if (0x0 != sw->stagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+ }
+
+ /* stag vid */
+ FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+ FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->stag_vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->stag_vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val,
+ (a_uint32_t) sw->stag_vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+ }
+
+ /* stag priority */
+ FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+ if (0x0 != sw->stag_pri_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+ }
+
+ /* stag dei */
+ FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+ if (0x0 != sw->stag_dei_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+ }
+
+ /* packet ctagged */
+ FIELD_GET(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+ FIELD_GET(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+ if (0x0 != sw->ctagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+ }
+
+ /* ctag vid */
+ FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data);
+ sw->ctag_vid_val |= (data << 8);
+ FIELD_GET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_VIDHM, data);
+ sw->ctag_vid_mask |= (data << 8);
+
+ FIELD_GET(EHMAC_RUL_M4, CVIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->ctag_vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val,
+ (a_uint32_t) sw->ctag_vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+ }
+
+ /* ctag priority */
+ FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+ if (0x0 != sw->ctag_pri_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+ }
+
+ /* ctag dei */
+ FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+ if (0x0 != sw->ctag_cfi_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en, icmp_en;
+
+ sw->dest_ip4_val = hw->vlu[0];
+ sw->dest_ip4_mask = hw->msk[0];
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+
+ sw->src_ip4_val = hw->vlu[1];
+ sw->src_ip4_mask = hw->msk[1];
+ if (0x0 != sw->src_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+ FIELD_GET(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+ FIELD_GET(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_GET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ FIELD_GET(IP4_RUL_M3, IP4DPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en);
+ if (icmp_en)
+ {
+ FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+ FIELD_GET(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+ if (0x0 != sw->icmp_type_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+ FIELD_GET(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+ if (0x0 != sw->icmp_code_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+ }
+ }
+ else
+ {
+ FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_GET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ FIELD_GET(IP4_RUL_M3, IP4SPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+ FIELD_GET(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+ FIELD_GET(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+ if (0x0 != sw->ripv1_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+ FIELD_GET(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+ if (0x0 != sw->dhcpv4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en, icmp6_en, tmp;
+
+ FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+ FIELD_GET(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+ FIELD_GET(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_GET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ FIELD_GET(IP6_RUL3_M3, IP6DPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en);
+ if (icmp6_en)
+ {
+ FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+ FIELD_GET(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+ if (0x0 != sw->icmp_type_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+ FIELD_GET(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+ if (0x0 != sw->icmp_code_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+ }
+ }
+ else
+ {
+ FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_GET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+ FIELD_GET(IP6_RUL3_M3, IP6SPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isis_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ }
+
+ FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+ FIELD_GET(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+ FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp);
+ sw->ip6_lable_val |= (tmp << 16);
+ FIELD_GET(IP6_RUL3_M2, IP6LABEL2M, tmp);
+ sw->ip6_lable_mask |= (tmp << 16);
+
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+ FIELD_GET(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+ FIELD_GET(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+ if (0x0 != sw->dhcpv6_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+ /* for ISIS UDF type, length and offset no meanging in rules, just set default value */
+ sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+ sw->udf_len = 16;
+ sw->udf_offset = 0;
+
+ for (i = 0; i < ISIS_MAX_UDF_LENGTH; i++)
+ {
+ sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t data;
+
+ sw->action_flg = 0;
+
+ FIELD_GET(ACL_RSLT2, DES_PORT_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+ FIELD_GET(ACL_RSLT1, DES_PORT0, sw->ports);
+ FIELD_GET(ACL_RSLT2, DES_PORT1, data);
+ sw->ports |= (data << 3);
+ }
+
+ FIELD_GET(ACL_RSLT2, FWD_CMD, data);
+ if (0x7 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY);
+ }
+ else if (0x3 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+ }
+ else if (0x1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+ }
+ else
+ {
+ /* need't set permit action */
+ }
+
+ FIELD_GET(ACL_RSLT2, MIRR_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+ }
+
+ FIELD_GET(ACL_RSLT1, PRI_QU_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+ FIELD_GET(ACL_RSLT1, PRI_QU, sw->queue);
+ }
+
+ FIELD_GET(ACL_RSLT1, DSCP_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+ FIELD_GET(ACL_RSLT1, DSCPV, sw->dscp);
+ }
+
+ FIELD_GET(ACL_RSLT0, STAGVID, sw->stag_vid);
+
+ FIELD_GET(ACL_RSLT1, TRANS_SVID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+ }
+
+ FIELD_GET(ACL_RSLT1, STAG_PRI_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+ FIELD_GET(ACL_RSLT0, STAGPRI, sw->stag_pri);
+ }
+
+ FIELD_GET(ACL_RSLT1, STAG_DEI_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+ FIELD_GET(ACL_RSLT0, STAGDEI, sw->stag_dei);
+ }
+
+ FIELD_GET(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+
+ FIELD_GET(ACL_RSLT1, TRANS_CVID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+ }
+
+ FIELD_GET(ACL_RSLT1, CTAG_PRI_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+ FIELD_GET(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+ }
+
+ FIELD_GET(ACL_RSLT1, CTAG_CFI_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+ FIELD_GET(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+ }
+
+ FIELD_GET(ACL_RSLT1, LOOK_VID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+ }
+
+ FIELD_GET(ACL_RSLT2, POLICER_EN, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN);
+ FIELD_GET(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+ }
+
+ FIELD_GET(ACL_RSLT1, ARP_PTR_EN, data);
+ if (data)
+ {
+ FIELD_GET(ACL_RSLT1, WCMP_EN, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN);
+ FIELD_GET(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+ }
+ else
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN);
+ FIELD_GET(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+ }
+ }
+
+ FIELD_GET(ACL_RSLT1, FORCE_L3_MODE, data);
+ if ((0 != data) && (3 != data))
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+ if (0x1 == data)
+ {
+ sw->policy_fwd = FAL_ACL_POLICY_SNAT;
+ }
+ else
+ {
+ sw->policy_fwd = FAL_ACL_POLICY_DNAT;
+ }
+ }
+
+ FIELD_GET(ACL_RSLT2, EG_BYPASS, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+ }
+
+ FIELD_GET(ACL_RSLT2, TRIGGER_INTR, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ isis_acl_rule_t * hw_rule_snap, a_uint32_t * idx)
+{
+ sw_error_t rv;
+ a_uint32_t tmp_idx, i, b_rule[7] = { 0 };
+ parse_func_t ptr[7] = { NULL };
+ a_bool_t b_care, b_mac, eh_mac;
+
+ rv = _isis_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter));
+ SW_RTN_ON_ERROR(rv);
+
+ ptr[0] = _isis_acl_rule_udf_parse;
+ _isis_acl_rule_mac_preparse(sw, &b_mac, &eh_mac);
+
+ /* ehmac rule must be parsed bofore mac rule.
+ it's important for reparse process */
+ if (A_TRUE == eh_mac)
+ {
+ ptr[1] = _isis_acl_rule_ehmac_parse;
+ }
+
+ if (A_TRUE == b_mac)
+ {
+ ptr[2] = _isis_acl_rule_bmac_parse;
+ }
+
+ if ((A_FALSE == b_mac) && (A_FALSE == eh_mac))
+ {
+ ptr[2] = _isis_acl_rule_bmac_parse;
+ }
+
+ if (FAL_ACL_RULE_MAC == sw->rule_type)
+ {
+ }
+ else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ ptr[3] = _isis_acl_rule_ip4_parse;
+ }
+ else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ ptr[4] = _isis_acl_rule_ip6r1_parse;
+ ptr[5] = _isis_acl_rule_ip6r2_parse;
+ ptr[6] = _isis_acl_rule_ip6r3_parse;
+ }
+ else if (FAL_ACL_RULE_UDF == sw->rule_type)
+ {
+ ptr[1] = NULL;
+ ptr[2] = NULL;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ tmp_idx = *idx;
+ for (i = 0; i < 7; i++)
+ {
+ if (ptr[i])
+ {
+ if (ISIS_HW_RULE_TMP_CNT <= tmp_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_rule[i] = 1;
+ }
+ }
+ }
+
+ if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6]))
+ {
+ tmp_idx++;
+ }
+ }
+
+ if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ if (!b_rule[3])
+ {
+ tmp_idx++;
+ }
+ }
+
+ if (tmp_idx == *idx)
+ {
+ /* set type start & end */
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ (*idx)++;
+ }
+ else
+ {
+ if (1 == (tmp_idx - *idx))
+ {
+ if (FAL_ACL_COMBINED_START == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else if (FAL_ACL_COMBINED_CONTINUE == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else if (FAL_ACL_COMBINED_END == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ }
+ else
+ {
+ for (i = *idx; i < tmp_idx; i++)
+ {
+ if (i == *idx)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ else if (i == (tmp_idx - 1))
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ aos_mem_copy(&(hw_rule_snap[i].filter.act[0]),
+ &(hw_rule_snap[*idx].filter.act[0]),
+ sizeof (hw_rule_snap[*idx].filter.act));
+ }
+ }
+ *idx = tmp_idx;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ isis_acl_rule_t * hw_rule_snap, a_uint32_t idx,
+ a_uint32_t ent_nr)
+{
+ a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+ sw_error_t rv;
+ a_uint32_t i, flt_typ;
+ hw_filter_t *hw;
+
+ rv = _isis_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter));
+ SW_RTN_ON_ERROR(rv);
+
+ sw->rule_type = FAL_ACL_RULE_UDF;
+ for (i = 0; i < ent_nr; i++)
+ {
+ hw = &(hw_rule_snap[idx + i].filter);
+ FIELD_GET(MAC_RUL_M4, RULE_TYP, flt_typ);
+
+ if (ISIS_UDF_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_udf_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (ISIS_MAC_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_bmac_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_mac = A_TRUE;
+ }
+ else if (ISIS_EHMAC_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_ehmac_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_mac = A_TRUE;
+ }
+ else if (ISIS_IP4_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_ip4_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip4 = A_TRUE;
+ }
+ else if (ISIS_IP6R1_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_ip6r1_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (ISIS_IP6R2_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_ip6r2_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (ISIS_IP6R3_FILTER == flt_typ)
+ {
+ rv = _isis_acl_rule_ip6r3_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else
+ {
+ /* ignore fill gap filters */
+ }
+ }
+
+ if (A_TRUE == b_mac)
+ {
+ sw->rule_type = FAL_ACL_RULE_MAC;
+ }
+
+ if (A_TRUE == b_ip4)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP4;
+ }
+
+ if (A_TRUE == b_ip6)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP6;
+ }
+
+ return SW_OK;
+}
diff --git a/src/hsl/isis/isis_acl_prv.h b/src/hsl/isis/isis_acl_prv.h
new file mode 100644
index 0000000..d261c9e
--- /dev/null
+++ b/src/hsl/isis/isis_acl_prv.h
@@ -0,0 +1,96 @@
+
+
+typedef struct
+{
+ a_uint8_t status;
+ a_uint8_t list_id;
+ a_uint8_t list_pri;
+ a_uint8_t rule_nr;
+ fal_pbmp_t bind_pts;
+} isis_acl_list_t;
+
+
+typedef struct
+{
+ a_uint32_t vlu[5];
+ a_uint32_t msk[5];
+ a_uint32_t act[3];
+} hw_filter_t;
+
+
+typedef struct
+{
+ a_uint8_t status;
+ a_uint8_t list_id;
+ a_uint8_t list_pri;
+ a_uint8_t rule_id;
+ hw_filter_t filter;
+} isis_acl_rule_t;
+
+
+#define ENT_USED 0x1
+#define ENT_TMP 0x2
+#define ENT_DEACTIVE 0x4
+
+#define FLT_START 0x0
+#define FLT_CONTINUE 0x1
+#define FLT_END 0x2
+#define FLT_STARTEND 0x3
+
+
+#define ISIS_MAC_FILTER 1
+#define ISIS_IP4_FILTER 2
+#define ISIS_IP6R1_FILTER 3
+#define ISIS_IP6R2_FILTER 4
+#define ISIS_IP6R3_FILTER 5
+#define ISIS_UDF_FILTER 6
+#define ISIS_EHMAC_FILTER 7
+
+
+#define ISIS_MAX_UDF_OFFSET 31
+#define ISIS_MAX_UDF_LENGTH 16
+
+
+#define ISIS_FILTER_VLU_OP 0x0
+#define ISIS_FILTER_MSK_OP 0x1
+#define ISIS_FILTER_ACT_OP 0x2
+
+
+
+//#define ISIS_MAX_FILTER 8
+#define ISIS_MAX_FILTER 96
+#define ISIS_RULE_FUNC_ADDR 0x0400
+#define ISIS_HW_RULE_TMP_CNT (ISIS_MAX_FILTER + 4)
+
+#define ISIS_MAX_LIST_ID 255
+#define ISIS_MAX_LIST_PRI 255
+
+#define ISIS_UDF_MAX_LENGTH 15
+#define ISIS_UDF_MAX_OFFSET 31
+
+#define WIN_RULE_CTL0_ADDR 0x218
+#define WIN_RULE_CTL1_ADDR 0x234
+
+
+#define ISIS_FILTER_VLU_ADDR 0x58000
+#define ISIS_FILTER_MSK_ADDR 0x59000
+#define ISIS_FILTER_ACT_ADDR 0x5a000
+
+
+#define FIELD_SET(reg, field, val) \
+ SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+#define FIELD_GET(reg, field, val) \
+ SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+
+sw_error_t
+_isis_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t * idx);
+
+
+sw_error_t
+_isis_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isis_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr);
+
+
diff --git a/src/hsl/isis/isis_cosmap.c b/src/hsl/isis/isis_cosmap.c
new file mode 100644
index 0000000..5ca98af
--- /dev/null
+++ b/src/hsl/isis/isis_cosmap.c
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_cosmap ISIS_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_cosmap.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_DSCP 63
+#define ISIS_MAX_UP 7
+#define ISIS_MAX_PRI 7
+#define ISIS_MAX_DP 1
+#define ISIS_MAX_QUEUE 3
+#define ISIS_MAX_EH_QUEUE 5
+
+#define ISIS_DSCP_TO_PRI 0
+#define ISIS_DSCP_TO_DP 1
+#define ISIS_UP_TO_PRI 2
+#define ISIS_UP_TO_DP 3
+
+#define ISIS_EGRESS_REAMRK_ADDR 0x5ae00
+#define ISIS_EGRESS_REAMRK_NUM 16
+
+static sw_error_t
+_isis_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+ a_uint32_t dscp, a_uint32_t val)
+{
+ sw_error_t rv;
+ a_uint32_t index, data;
+
+ if (ISIS_MAX_DSCP < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ index = dscp >> 3;
+ HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISIS_DSCP_TO_PRI == mode)
+ {
+ if (ISIS_MAX_PRI < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x7 << ((dscp & 0x7) << 2)));
+ data |= (val << ((dscp & 0x7) << 2));
+ }
+ else
+ {
+ if (ISIS_MAX_DP < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+ data |= (val << (((dscp & 0x7) << 2) + 3));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+ a_uint32_t dscp, a_uint32_t * val)
+{
+ sw_error_t rv;
+ a_uint32_t index, data;
+
+ if (ISIS_MAX_DSCP < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ index = dscp >> 3;
+ HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+ if (ISIS_DSCP_TO_PRI == mode)
+ {
+ *val = data & 0x7;
+ }
+ else
+ {
+ *val = (data & 0x8) >> 3;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+ a_uint32_t val)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISIS_MAX_UP < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISIS_UP_TO_PRI == mode)
+ {
+ if (ISIS_MAX_PRI < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x7 << (up << 2)));
+ data |= (val << (up << 2));
+ }
+ else
+ {
+ if (ISIS_MAX_DP < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x1 << ((up << 2) + 3)));
+ data |= (val << ((up << 2) + 3));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+ a_uint32_t * val)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISIS_MAX_UP < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (data >> (up << 2)) & 0xf;
+
+ if (ISIS_UP_TO_PRI == mode)
+ {
+ *val = (data & 0x7);
+ }
+ else
+ {
+ *val = (data & 0x8) >> 3;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_QUEUE < queue))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x3 << (pri << 2)));
+ data |= (queue << (pri << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISIS_MAX_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = (data >> (pri << 2)) & 0x3;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if ((ISIS_MAX_PRI < pri) || (ISIS_MAX_EH_QUEUE < queue))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x7 << (pri << 2)));
+ data |= (queue << (pri << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISIS_MAX_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = (data >> (pri << 2)) & 0x7;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ if (ISIS_EGRESS_REAMRK_NUM <= tbl_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = (tbl->y_up & 0x7)
+ | ((tbl->g_up & 0x7) << 4)
+ | ((tbl->y_dscp & 0x3f) << 8)
+ | ((tbl->g_dscp & 0x3f) << 16)
+ | ((tbl->remark_dscp & 0x1) << 23)
+ | ((tbl->remark_up & 0x1) << 22);
+
+ addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ if (ISIS_EGRESS_REAMRK_NUM <= tbl_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t));
+
+ addr = ISIS_EGRESS_REAMRK_ADDR + (tbl_id << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data & (0x1 << 23))
+ {
+ tbl->remark_dscp = A_TRUE;
+ tbl->y_dscp = (data >> 8) & 0x3f;
+ tbl->g_dscp = (data >> 16) & 0x3f;
+ }
+
+ if (data & (0x1 << 22))
+ {
+ tbl->remark_up = A_TRUE;
+ tbl->y_up = data & 0x7;
+ tbl->g_up = (data >> 4) & 0x7;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_PRI, dscp, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_PRI, dscp, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_dscp_to_pri_dp_set(dev_id, ISIS_DSCP_TO_DP, dscp, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_dscp_to_pri_dp_get(dev_id, ISIS_DSCP_TO_DP, dscp, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_PRI, up, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_PRI, up, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_up_to_pri_dp_set(dev_id, ISIS_UP_TO_DP, up, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_up_to_pri_dp_get(dev_id, ISIS_UP_TO_DP, up, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_pri_to_queue_set(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_pri_to_queue_get(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_cosmap_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->cosmap_dscp_to_pri_set = isis_cosmap_dscp_to_pri_set;
+ p_api->cosmap_dscp_to_pri_get = isis_cosmap_dscp_to_pri_get;
+ p_api->cosmap_dscp_to_dp_set = isis_cosmap_dscp_to_dp_set;
+ p_api->cosmap_dscp_to_dp_get = isis_cosmap_dscp_to_dp_get;
+ p_api->cosmap_up_to_pri_set = isis_cosmap_up_to_pri_set;
+ p_api->cosmap_up_to_pri_get = isis_cosmap_up_to_pri_get;
+ p_api->cosmap_up_to_dp_set = isis_cosmap_up_to_dp_set;
+ p_api->cosmap_up_to_dp_get = isis_cosmap_up_to_dp_get;
+ p_api->cosmap_pri_to_queue_set = isis_cosmap_pri_to_queue_set;
+ p_api->cosmap_pri_to_queue_get = isis_cosmap_pri_to_queue_get;
+ p_api->cosmap_pri_to_ehqueue_set = isis_cosmap_pri_to_ehqueue_set;
+ p_api->cosmap_pri_to_ehqueue_get = isis_cosmap_pri_to_ehqueue_get;
+ p_api->cosmap_egress_remark_set = isis_cosmap_egress_remark_set;
+ p_api->cosmap_egress_remark_get = isis_cosmap_egress_remark_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_fdb.c b/src/hsl/isis/isis_fdb.c
new file mode 100644
index 0000000..e2d10c9
--- /dev/null
+++ b/src/hsl/isis/isis_fdb.c
@@ -0,0 +1,2208 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_fdb ISIS_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_fdb.h"
+#include "isis_reg.h"
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+#define ARL_FIND_ENTRY 7
+#define ARL_TRANSFER_ENTRY 8
+
+#define ARL_FIRST_ENTRY 1001
+#define ARL_FLUSH_PORT_NO_STATIC 1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+#define ISIS_MAX_FID 4095
+#define ISIS_MAX_LEARN_LIMIT_CNT 2047
+#define ISIS_MAX_PORT_LEARN_LIMIT_CNT 1023
+
+static sw_error_t
+_isis_wl_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static a_bool_t
+_isis_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+_isis_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+_isis_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+ sw_error_t rv;
+
+ if (A_TRUE == entry->white_list_en)
+ {
+ rv = _isis_wl_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]);
+ }
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISIS_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]);
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7),
+ reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]);
+ }
+
+ _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ return SW_OK;
+}
+
+static void
+_isis_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]);
+ if (data)
+ {
+ entry->fid = FAL_SVL_FID;
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]);
+ entry->fid = data;
+ }
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x7;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]);
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 2; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+ }
+
+ entry->white_list_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->white_list_en = A_TRUE;
+ }
+
+ return;
+}
+
+static sw_error_t
+_isis_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (®[3]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (®[3]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 2000;
+ a_uint32_t entry;
+ a_uint32_t hwop = op;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry);
+
+ if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry);
+ }
+
+ if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 2000;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry);
+
+ if (full_vio)
+ {
+ /* must clear AT_FULL_VOI bit */
+ entry = 0x1000;
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ARL_LOAD_ENTRY == hwop)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == hwop)
+ || (ARL_FLUSH_PORT_UNICAST == hwop))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry,
+ a_uint32_t hwop)
+{
+ sw_error_t rv;
+ a_uint32_t i, port = 0, status, reg[4] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == option->port_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]);
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map,
+ HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ status = 0;
+ for (i = 0; i < SW_MAX_NR_PORT; i++)
+ {
+ if ((entry->port.map) & (0x1UL << i))
+ {
+ if (status)
+ {
+ return SW_BAD_PARAM;
+ }
+ port = i;
+ status = 1;
+ }
+ }
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]);
+ }
+
+ if (A_TRUE == option->fid_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+ }
+
+ if (A_TRUE == option->multicast_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+ }
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISIS_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ARL_FIRST_ENTRY != hwop)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]);
+ }
+
+ _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ rv = _isis_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_atu_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_atu_hw_to_sw(reg, entry);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+ if ((A_TRUE == _isis_fdb_is_zeroaddr(entry->addr))
+ && (0 == status))
+ {
+ if (ARL_NEXT_ENTRY == hwop)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+ else
+ {
+ return SW_OK;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[4] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = _isis_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+ }
+ else
+ {
+ rv = _isis_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ _isis_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1);
+ }
+ else if (ISIS_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (®2),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_fdb_op_t option;
+
+ aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+ rv = _isis_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = _isis_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = _isis_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+ a_uint32_t reg[4] = { 0 };
+
+ if (A_TRUE == option->port_en)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == option->fid_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+ }
+
+ if (A_TRUE == option->multicast_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+ }
+
+ if (FAL_SVL_FID == fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISIS_MAX_FID >= fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]);
+
+ rv = _isis_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_fdb_commit(dev_id, ARL_TRANSFER_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((65535 * 7 < *time) || (7 > *time))
+ {
+ return SW_BAD_PARAM;
+ }
+ data = *time / 7;
+ *time = data * 7;
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 7;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISIS_MAX_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1,
+ reg);
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0,
+ reg);
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data,
+ reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data,
+ reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+#define ISIS_RESV_ADDR_NUM 32
+#define RESV_ADDR_TBL0_ADDR 0x3c000
+#define RESV_ADDR_TBL1_ADDR 0x3c004
+#define RESV_ADDR_TBL2_ADDR 0x3c008
+
+static void
+_isis_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr)
+{
+ a_uint32_t i;
+
+ for (i = 2; i < 6; i++)
+ {
+ addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+ }
+}
+
+static sw_error_t
+_isis_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = entry->port.map;
+ }
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]);
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]);
+ }
+
+ if (A_TRUE != entry->static_en)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]);
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7),
+ reg[1]);
+ }
+
+ _isis_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ return SW_OK;
+}
+
+static void
+_isis_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->fid = FAL_SVL_FID;
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_TRUE;
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x7;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]);
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ _isis_resv_addr_parse(reg, &(entry->addr));
+ return;
+}
+
+static sw_error_t
+_isis_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op,
+ a_uint32_t * empty)
+{
+ a_uint32_t index, addr, data, tbl[3] = { 0 };
+ sw_error_t rv;
+ fal_mac_addr_t mac_tmp;
+
+ *empty = ISIS_RESV_ADDR_NUM;
+ for (index = 0; index < ISIS_RESV_ADDR_NUM; index++)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+ if (data)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_resv_addr_parse(tbl, &mac_tmp);
+ if (!aos_mem_cmp
+ ((void *) &(entry->addr), (void *) &mac_tmp,
+ sizeof (fal_mac_addr_t)))
+ {
+ if (ARL_PURGE_ENTRY == op)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ tbl[2] = 0;
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])),
+ sizeof (a_uint32_t));
+ return rv;
+ }
+ else if (ARL_LOAD_ENTRY == op)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ else if (ARL_FIND_ENTRY == op)
+ {
+ _isis_resv_atu_hw_to_sw(tbl, entry);
+ return SW_OK;
+ }
+ }
+ }
+ else
+ {
+ *empty = index;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, empty, addr, tbl[3] = { 0 };
+
+ rv = _isis_resv_atu_sw_to_hw(dev_id, entry, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty);
+ if (SW_ALREADY_EXIST == rv)
+ {
+ return rv;
+ }
+
+ if (ISIS_RESV_ADDR_NUM == empty)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < 3; i++)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty;
+
+ rv = _isis_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty;
+
+ rv = _isis_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty);
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ a_uint32_t index, addr, data, tbl[3] = { 0 };
+ sw_error_t rv;
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (ISIS_RESV_ADDR_NUM < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < ISIS_RESV_ADDR_NUM; index++)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+ if (data)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_resv_atu_hw_to_sw(tbl, entry);
+ break;
+ }
+ }
+
+ if (ISIS_RESV_ADDR_NUM == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0x7;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_STATUS, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_STATUS, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ fal_fdb_entry_t entry;
+ fal_fdb_op_t option;
+ a_uint32_t reg, port;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SVL_FID < fid)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(&option, sizeof(fal_fdb_op_t));
+ aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t));
+ entry.fid = fid & 0xffff;
+ rv = _isis_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+ if (op)
+ {
+ port |= (0x1 << port_id);
+ }
+ else
+ {
+ port &= (~(0x1 << port_id));
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ rv = _isis_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+ return rv;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_extend_next(dev_id, option, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_extend_first(dev_id, option, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_transfer(dev_id, old_port, new_port, fid, option);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_learn_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_learn_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_age_ctrl_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_age_ctrl_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_learn_limit_set(dev_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_learn_limit_get(dev_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_learn_exceed_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_learn_exceed_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_resv_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_resv_del(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_resv_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_resv_iterate(dev_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_learn_static_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_learn_static_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 1);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isis_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_fdb_port_update(dev_id, fid, addr, port_id, 0);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = isis_fdb_add;
+ p_api->fdb_del_all = isis_fdb_del_all;
+ p_api->fdb_del_by_port = isis_fdb_del_by_port;
+ p_api->fdb_del_by_mac = isis_fdb_del_by_mac;
+ p_api->fdb_extend_first = isis_fdb_extend_first;
+ p_api->fdb_extend_next = isis_fdb_extend_next;
+ p_api->fdb_find = isis_fdb_find;
+ p_api->port_learn_set = isis_fdb_port_learn_set;
+ p_api->port_learn_get = isis_fdb_port_learn_get;
+ p_api->age_ctrl_set = isis_fdb_age_ctrl_set;
+ p_api->age_ctrl_get = isis_fdb_age_ctrl_get;
+ p_api->age_time_set = isis_fdb_age_time_set;
+ p_api->age_time_get = isis_fdb_age_time_get;
+ p_api->fdb_extend_next = isis_fdb_extend_next;
+ p_api->fdb_extend_first = isis_fdb_extend_first;
+ p_api->fdb_transfer = isis_fdb_transfer;
+ p_api->port_fdb_learn_limit_set = isis_port_fdb_learn_limit_set;
+ p_api->port_fdb_learn_limit_get = isis_port_fdb_learn_limit_get;
+ p_api->port_fdb_learn_exceed_cmd_set = isis_port_fdb_learn_exceed_cmd_set;
+ p_api->port_fdb_learn_exceed_cmd_get = isis_port_fdb_learn_exceed_cmd_get;
+ p_api->fdb_learn_limit_set = isis_fdb_learn_limit_set;
+ p_api->fdb_learn_limit_get = isis_fdb_learn_limit_get;
+ p_api->fdb_learn_exceed_cmd_set = isis_fdb_learn_exceed_cmd_set;
+ p_api->fdb_learn_exceed_cmd_get = isis_fdb_learn_exceed_cmd_get;
+ p_api->fdb_resv_add = isis_fdb_resv_add;
+ p_api->fdb_resv_del = isis_fdb_resv_del;
+ p_api->fdb_resv_find = isis_fdb_resv_find;
+ p_api->fdb_resv_iterate = isis_fdb_resv_iterate;
+ p_api->fdb_port_learn_static_set = isis_fdb_port_learn_static_set;
+ p_api->fdb_port_learn_static_get = isis_fdb_port_learn_static_get;
+ p_api->fdb_port_add = isis_fdb_port_add;
+ p_api->fdb_port_del = isis_fdb_port_del;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_igmp.c b/src/hsl/isis/isis_igmp.c
new file mode 100644
index 0000000..3013235
--- /dev/null
+++ b/src/hsl/isis/isis_igmp.c
@@ -0,0 +1,1134 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_igmp ISIS_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_igmp.h"
+#include "isis_reg.h"
+
+#define LEAVE_EN_OFFSET 2
+#define JOIN_EN_OFFSET 1
+#define IGMP_MLD_EN_OFFSET 0
+
+#define ISIS_MAX_PORT_LEARN_LIMIT_CNT 1023
+
+extern sw_error_t
+isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isis_igmp_sg_entry_show(a_uint32_t dev_id);
+
+static sw_error_t
+_isis_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << ((port_id << 3) + item));
+ reg |= (val << ((port_id << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+ reg |= (val << (((port_id - 4) << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+ }
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+ {
+ return SW_BAD_PARAM;
+ }
+ val = pts;
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *pts = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0xe;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry);
+ if (data)
+ {
+ *enable = A_TRUE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry);
+ *queue = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *queue = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISIS_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = data;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_set(dev_id, port_id, enable,
+ IGMP_MLD_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_get(dev_id, port_id, enable,
+ IGMP_MLD_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp leave feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_rp_set(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_rp_get(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_creat_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_creat_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * static status hardware will not age out multicast entry which leardned by hardware,
+ * otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_static_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_static_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_leaky_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_leaky_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details Comments:
+ * After enabling igmp join/leave feature on a particular port hardware will dynamic
+ * creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_v3_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_v3_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_queue_set(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_igmp_mld_entry_queue_get(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_igmp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_igmps_status_set = isis_port_igmps_status_set;
+ p_api->port_igmps_status_get = isis_port_igmps_status_get;
+ p_api->igmp_mld_cmd_set = isis_igmp_mld_cmd_set;
+ p_api->igmp_mld_cmd_get = isis_igmp_mld_cmd_get;
+ p_api->port_igmp_join_set = isis_port_igmp_mld_join_set;
+ p_api->port_igmp_join_get = isis_port_igmp_mld_join_get;
+ p_api->port_igmp_leave_set = isis_port_igmp_mld_leave_set;
+ p_api->port_igmp_leave_get = isis_port_igmp_mld_leave_get;
+ p_api->igmp_rp_set = isis_igmp_mld_rp_set;
+ p_api->igmp_rp_get = isis_igmp_mld_rp_get;
+ p_api->igmp_entry_creat_set = isis_igmp_mld_entry_creat_set;
+ p_api->igmp_entry_creat_get = isis_igmp_mld_entry_creat_get;
+ p_api->igmp_entry_static_set = isis_igmp_mld_entry_static_set;
+ p_api->igmp_entry_static_get = isis_igmp_mld_entry_static_get;
+ p_api->igmp_entry_leaky_set = isis_igmp_mld_entry_leaky_set;
+ p_api->igmp_entry_leaky_get = isis_igmp_mld_entry_leaky_get;
+ p_api->igmp_entry_v3_set = isis_igmp_mld_entry_v3_set;
+ p_api->igmp_entry_v3_get = isis_igmp_mld_entry_v3_get;
+ p_api->igmp_entry_queue_set = isis_igmp_mld_entry_queue_set;
+ p_api->igmp_entry_queue_get = isis_igmp_mld_entry_queue_get;
+ p_api->port_igmp_mld_learn_limit_set = isis_port_igmp_mld_learn_limit_set;
+ p_api->port_igmp_mld_learn_limit_get = isis_port_igmp_mld_learn_limit_get;
+ p_api->port_igmp_mld_learn_exceed_cmd_set = isis_port_igmp_mld_learn_exceed_cmd_set;
+ p_api->port_igmp_mld_learn_exceed_cmd_get = isis_port_igmp_mld_learn_exceed_cmd_get;
+ p_api->igmp_sg_entry_set = isis_igmp_sg_entry_set;
+ p_api->igmp_sg_entry_clear = isis_igmp_sg_entry_clear;
+ p_api->igmp_sg_entry_show = isis_igmp_sg_entry_show;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_init.c b/src/hsl/isis/isis_init.c
new file mode 100644
index 0000000..e6cb7dd
--- /dev/null
+++ b/src/hsl/isis/isis_init.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_init ISIS_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mib.h"
+#include "isis_port_ctrl.h"
+#include "isis_portvlan.h"
+#include "isis_vlan.h"
+#include "isis_fdb.h"
+#include "isis_qos.h"
+#include "isis_mirror.h"
+#include "isis_stp.h"
+#include "isis_rate.h"
+#include "isis_misc.h"
+#include "isis_leaky.h"
+#include "isis_igmp.h"
+#include "isis_acl.h"
+#include "isis_led.h"
+#include "isis_cosmap.h"
+#include "isis_ip.h"
+#include "isis_nat.h"
+#if defined(IN_NAT_HELPER)
+#include "isis_nat_helper.h"
+#endif
+#include "isis_sec.h"
+#include "isis_trunk.h"
+#include "isis_interface_ctrl.h"
+#include "isis_reg_access.h"
+#include "isis_reg.h"
+#include "isis_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * isis_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For isis there are five internal PHY devices and seven MAC devices.
+ MAC0 always connect to external MAC device.
+ PHY4 can connect to MAC5 or external MAC device.
+ MAC6 always connect to external devices.
+ MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+isis_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ /* for port property set, SSDK should not generate some limitations */
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ /* Only port0/port6 without PHY device */
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != pdev->nr_ports - 1))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port but exclude wan port in some cases */
+ /* but which port is wan port, we are no meaning */
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ /* which port is wan port, we are no meaning but port0 is
+ always CPU port */
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+isis_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ return SW_OK;
+}
+
+#endif
+
+static sw_error_t
+isis_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+ a_uint32_t entry;
+ sw_error_t rv;
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17_DEVICE_ID == entry)
+ {
+ pdev->nr_ports = 7;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 6;
+ pdev->cpu_mode = cpu_mode;
+ }
+ else
+ {
+ pdev->nr_ports = 6;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 6;
+ pdev->cpu_mode = cpu_mode;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_isis_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = isis_hw_init(dev_id, isis_cfg[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ ISIS_ACL_RESET(rv, dev_id);
+ ISIS_IP_RESET(rv, dev_id);
+ ISIS_NAT_RESET(rv, dev_id);
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_cleanup(a_uint32_t dev_id)
+{
+ if (isis_cfg[dev_id])
+ {
+#if defined(IN_NAT_HELPER)
+ sw_error_t rv;
+ ISIS_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+
+ aos_mem_free(isis_cfg[dev_id]);
+ isis_cfg[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ * This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ * This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+isis_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == isis_cfg[dev_id])
+ {
+ isis_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == isis_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(isis_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(isis_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(isis_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ sw_error_t rv;
+
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(isis_portproperty_init(dev_id, cfg->cpu_mode));
+
+ ISIS_MIB_INIT(rv, dev_id);
+ ISIS_PORT_CTRL_INIT(rv, dev_id);
+ ISIS_PORTVLAN_INIT(rv, dev_id);
+ ISIS_VLAN_INIT(rv, dev_id);
+ ISIS_FDB_INIT(rv, dev_id);
+ ISIS_QOS_INIT(rv, dev_id);
+ ISIS_STP_INIT(rv, dev_id);
+ ISIS_MIRR_INIT(rv, dev_id);
+ ISIS_RATE_INIT(rv, dev_id);
+ ISIS_MISC_INIT(rv, dev_id);
+ ISIS_LEAKY_INIT(rv, dev_id);
+ ISIS_IGMP_INIT(rv, dev_id);
+ ISIS_ACL_INIT(rv, dev_id);
+ ISIS_LED_INIT(rv, dev_id);
+ ISIS_COSMAP_INIT(rv, dev_id);
+ ISIS_IP_INIT(rv, dev_id);
+ ISIS_NAT_INIT(rv, dev_id);
+ ISIS_TRUNK_INIT(rv, dev_id);
+ ISIS_SEC_INIT(rv, dev_id);
+ ISIS_INTERFACE_CTRL_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = isis_reset;
+ p_api->dev_clean = isis_cleanup;
+ }
+
+ SW_RTN_ON_ERROR(isis_hw_init(dev_id, cfg));
+#if defined(IN_NAT_HELPER)
+ ISIS_NAT_HELPER_INIT(rv, dev_id);
+#endif
+
+#if defined(IN_MACBLOCK)
+ qca_mac_scan_helper_init();
+#endif
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_interface_ctrl.c b/src/hsl/isis/isis_interface_ctrl.c
new file mode 100644
index 0000000..0876d49
--- /dev/null
+++ b/src/hsl/isis/isis_interface_ctrl.c
@@ -0,0 +1,1520 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_interface_ctrl ISIS_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_interface_ctrl.h"
+#include "isis_reg.h"
+
+#define ISIS_MAC_0 0
+#define ISIS_MAC_5 5
+#define ISIS_MAC_6 6
+
+#define ISIS_PHY_MODE_PHY_ID 4
+#define ISIS_LPI_PORT1_OFFSET 4
+#define ISIS_LPI_BIT_STEP 2
+
+/* we need to do more about MAC5/PHY4 connection... */
+#if 0
+static sw_error_t
+_isis_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, rgmii, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, mii_mac, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, mii_phy, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, sgmii, reg);
+
+ if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii)
+ {
+ *inter_mode = A_FALSE;
+ }
+ else
+ {
+ *inter_mode = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, rgmii, gmii, mii;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg);
+
+ if (rgmii || gmii || mii)
+ {
+ *inter_mode = A_FALSE;
+ }
+ else
+ {
+ *inter_mode = A_TRUE;
+ }
+
+ return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, offset, device_id, rev_id, reverse = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+ if (S17_DEVICE_ID != device_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+ if (S17_REVISION_A == rev_id)
+ {
+ reverse = 0;
+ }
+ else
+ {
+ reverse = 1;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ field = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ field = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (reverse)
+ {
+ field = (~field) & 0x1UL;
+ }
+
+ offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET;
+ reg &= (~(0x1UL << offset));
+ reg |= (field << offset);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, offset, device_id, rev_id, reverse = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+ if (S17_DEVICE_ID != device_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+ if (S17_REVISION_A == rev_id)
+ {
+ reverse = 0;
+ }
+ else
+ {
+ reverse = 1;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ offset = (port_id - 1) * ISIS_LPI_BIT_STEP + ISIS_LPI_PORT1_OFFSET;
+ field = (reg >> offset) & 0x1;
+
+ if (reverse)
+ {
+ field = (~field) & 0x1UL;
+ }
+
+ if (field)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (A_TRUE == config->txclk_delay_cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ }
+
+ if (A_TRUE == config->rxclk_delay_cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ }
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg);
+ if (field)
+ {
+ config->txclk_delay_cmd = A_TRUE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg);
+ config->txclk_delay_sel = field;
+ }
+ else
+ {
+ config->txclk_delay_cmd = A_FALSE;
+ config->txclk_delay_sel = 0;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg);
+ if (field)
+ {
+ config->rxclk_delay_cmd = A_TRUE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg);
+ config->rxclk_delay_sel = field;
+ }
+ else
+ {
+ config->rxclk_delay_cmd = A_FALSE;
+ config->rxclk_delay_sel = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+ }
+ else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg);
+ if (field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg);
+ }
+ else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg);
+ if (field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+ /* TX/RX clock setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* SGMII control register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg);
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg);
+ }
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ /* nothing to do */
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ /* nothing to do */
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg);
+ if (field)
+ {
+ config->auto_neg = A_TRUE;
+ }
+ else
+ {
+ config->auto_neg = A_FALSE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg);
+ if (1 == field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+ /* TX/RX clock setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* SGMII control register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 3, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* Power on strip register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 0, reg);
+ }
+ HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ /* nothing to do */
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ /* nothing to do */
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg);
+ if (field)
+ {
+ config->auto_neg = A_TRUE;
+ }
+ else
+ {
+ config->auto_neg = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_MODE_RGMII == config->mac_mode)
+ {
+ rv = _isis_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii));
+ }
+ else if (FAL_MAC_MODE_GMII == config->mac_mode)
+ {
+ rv = _isis_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii));
+ }
+ else if (FAL_MAC_MODE_MII == config->mac_mode)
+ {
+ rv = _isis_port_mii_mode_set(dev_id, port_id, &(config->config.mii));
+ }
+ else if (FAL_MAC_MODE_SGMII == config->mac_mode)
+ {
+ rv = _isis_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii));
+ }
+ else if (FAL_MAC_MODE_FIBER == config->mac_mode)
+ {
+ rv = _isis_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber));
+ }
+ else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+ {
+ rv = _isis_port_default_mode_set(dev_id, port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, field2;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISIS_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(config, sizeof(fal_interface_mac_mode_t));
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg);
+ if (field)
+ {
+ config->mac_mode = FAL_MAC_MODE_RGMII;
+ rv = _isis_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg);
+ if (field || field2)
+ {
+ config->mac_mode = FAL_MAC_MODE_GMII;
+ rv = _isis_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg);
+ if (field || field2)
+ {
+ config->mac_mode = FAL_MAC_MODE_MII;
+ rv = _isis_port_mii_mode_get(dev_id, port_id, &(config->config.mii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg);
+ if (field)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg);
+ if (3 == field)
+ {
+ config->mac_mode = FAL_MAC_MODE_FIBER;
+ rv = _isis_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber));
+ }
+ else
+ {
+ config->mac_mode = FAL_MAC_MODE_SGMII;
+ rv = _isis_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii));
+ }
+ return rv;
+ }
+
+ config->mac_mode = FAL_MAC_MODE_DEFAULT;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ a_uint16_t data;
+ a_uint32_t reg, rgmii_mode, tx_delay = 2;;
+ a_bool_t tx_delay_cmd, rx_delay_cmd;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ /* only PHY4 support mode setting */
+ if (ISIS_PHY_MODE_PHY_ID != phy_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_MODE_RGMII == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg);
+ rgmii_mode = 1;
+ /* PHY TX delay */
+ if (A_TRUE == config->txclk_delay_cmd)
+ {
+ tx_delay_cmd = A_TRUE;
+ tx_delay = config->txclk_delay_sel;
+ }
+ else
+ {
+ tx_delay_cmd = A_FALSE;
+ }
+
+ /* PHY RX delay */
+ if (A_TRUE == config->rxclk_delay_cmd)
+ {
+ rx_delay_cmd = A_TRUE;
+ }
+ else
+ {
+ rx_delay_cmd = A_FALSE;
+ }
+ }
+ else if (FAL_MAC_MODE_GMII == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg);
+ rgmii_mode = 0;
+ tx_delay_cmd = A_FALSE;
+ rx_delay_cmd = A_FALSE;
+ }
+ else if (FAL_MAC_MODE_MII == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 1, reg);
+ rgmii_mode = 0;
+ tx_delay_cmd = A_FALSE;
+ rx_delay_cmd = A_FALSE;
+ }
+ else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_MII_EN, 0, reg);
+
+ rgmii_mode = 0;
+ tx_delay_cmd = A_FALSE;
+ rx_delay_cmd = A_FALSE;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RGMII mode, debug register18 bit3 */
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 18);
+ data &= 0xfff7UL;
+ data |= ((rgmii_mode & 0x1) << 3);
+ rv = f1_phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 18, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY TX delay command, debug regigster5 bit8 */
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5);
+ if (A_TRUE == tx_delay_cmd)
+ {
+ data |= 0x0100UL;
+ }
+ else
+ {
+ data &= 0xfeffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 5, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY TX delay select, debug register11 bit-6 */
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11);
+ data &= 0xff9fUL;
+ data |= ((tx_delay & 0x3UL) << 5);
+ if (A_TRUE == tx_delay_cmd)
+ {
+ data |= 0x0100UL;
+ }
+ else
+ {
+ data &= 0xfeffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 11, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RX delay command, debug regigster0 bit15 */
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0);
+ if (A_TRUE == rx_delay_cmd)
+ {
+ data |= 0x8000UL;
+ }
+ else
+ {
+ data &= 0x7fffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISIS_PHY_MODE_PHY_ID, 0, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RX delay select, now hardware not support */
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ a_uint16_t data;
+ a_uint32_t reg, rgmii, gmii, mii;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ /* only one PHY device support this */
+ if (ISIS_PHY_MODE_PHY_ID != phy_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(config, sizeof(fal_phy_config_t));
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg);
+
+ if ((rgmii) && (!gmii) && (!mii))
+ {
+ config->mac_mode = FAL_MAC_MODE_RGMII;
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 5);
+ if (data & 0x0100)
+ {
+ config->txclk_delay_cmd = A_TRUE;
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 11);
+ config->txclk_delay_sel = (data >> 5) & 0x3UL;
+ }
+ else
+ {
+ config->txclk_delay_cmd = A_FALSE;
+ }
+
+ data = f1_phy_debug_read(dev_id, ISIS_PHY_MODE_PHY_ID, 0);
+ if (data & 0x8000)
+ {
+ config->rxclk_delay_cmd = A_TRUE;
+ }
+ else
+ {
+ config->rxclk_delay_cmd = A_FALSE;
+ }
+ }
+ else if ((!rgmii) && (gmii) && (!mii))
+ {
+ config->mac_mode = FAL_MAC_MODE_GMII;
+ }
+ else if ((!rgmii) && (!gmii) && (mii))
+ {
+ config->mac_mode = FAL_MAC_MODE_MII;
+ }
+ else
+ {
+ config->mac_mode = FAL_MAC_MODE_DEFAULT;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_3az_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_3az_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_mode_set(dev_id, port_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_mode_get(dev_id, port_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_phy_mode_set(dev_id, phy_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_phy_mode_get(dev_id, phy_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_interface_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_3az_status_set = isis_port_3az_status_set;
+ p_api->port_3az_status_get = isis_port_3az_status_get;
+ p_api->interface_mac_mode_set = isis_interface_mac_mode_set;
+ p_api->interface_mac_mode_get = isis_interface_mac_mode_get;
+ p_api->interface_phy_mode_set = isis_interface_phy_mode_set;
+ p_api->interface_phy_mode_get = isis_interface_phy_mode_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_ip.c b/src/hsl/isis/isis_ip.c
new file mode 100644
index 0000000..e84f79c
--- /dev/null
+++ b/src/hsl/isis/isis_ip.c
@@ -0,0 +1,2499 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_ip ISIS_IP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_ip.h"
+#include "isis_reg.h"
+
+#define ISIS_HOST_ENTRY_DATA0_ADDR 0x0e48
+#define ISIS_HOST_ENTRY_DATA1_ADDR 0x0e4c
+#define ISIS_HOST_ENTRY_DATA2_ADDR 0x0e50
+#define ISIS_HOST_ENTRY_DATA3_ADDR 0x0e54
+#define ISIS_HOST_ENTRY_DATA4_ADDR 0x0e58
+
+#define ISIS_HOST_ENTRY_FLUSH 1
+#define ISIS_HOST_ENTRY_ADD 2
+#define ISIS_HOST_ENTRY_DEL 3
+#define ISIS_HOST_ENTRY_NEXT 4
+#define ISIS_HOST_ENTRY_SEARCH 5
+
+#define ISIS_ENTRY_ARP 3
+
+#define ISIS_INTF_MAC_ADDR_NUM 8
+#define ISIS_INTF_MAC_TBL0_ADDR 0x5a900
+#define ISIS_INTF_MAC_TBL1_ADDR 0x5a904
+#define ISIS_INTF_MAC_TBL2_ADDR 0x5a908
+#define ISIS_INTF_MAC_EDIT0_ADDR 0x02000
+#define ISIS_INTF_MAC_EDIT1_ADDR 0x02004
+#define ISIS_INTF_MAC_EDIT2_ADDR 0x02008
+
+#define ISIS_IP6_BASE_ADDR 0x0470
+
+#define ISIS_HOST_ENTRY_NUM 128
+
+#define ISIS_IP_COUTER_ADDR 0x2b000
+
+static a_uint32_t isis_mac_snap[SW_MAX_NR_DEV] = { 0 };
+static fal_intf_mac_entry_t isis_intf_snap[SW_MAX_NR_DEV][ISIS_INTF_MAC_ADDR_NUM];
+
+static void
+_isis_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ return;
+ }
+
+ *status = (data & 0x7f7f);
+
+ data &= 0xffff8080;
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return;
+}
+
+static void
+_isis_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ return;
+ }
+
+ data &= 0xffff8080;
+ data |= (status & 0x7f7f);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return;
+}
+
+static sw_error_t
+_isis_ip_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static sw_error_t
+_isis_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+ a_uint32_t counter[2])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ addr = ISIS_IP_COUTER_ADDR + (cnt_id << 3);
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(counter[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr += 4;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+ a_uint32_t busy = 1, i = 0x100, entry, j, try_num;
+ a_uint32_t learn_status = 0;
+ sw_error_t rv;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+ aos_udelay(500);
+ }
+
+ if (i == 0)
+ {
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* hardware requirements, we should disable ARP learn at first */
+ /* and maybe we should try several times... */
+ _isis_ip_pt_learn_save(dev_id, &learn_status);
+ if (learn_status)
+ {
+ try_num = 10;
+ }
+ else
+ {
+ try_num = 1;
+ }
+
+ for (j = 0; j < try_num; j++)
+ {
+ busy = 1;
+ i = 0x100;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ _isis_ip_pt_learn_restore(dev_id, learn_status);
+ return rv;
+ }
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+ aos_udelay(500);
+ }
+
+ if (i == 0)
+ {
+ _isis_ip_pt_learn_restore(dev_id, learn_status);
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ /* hardware requirement, we should read again... */
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ _isis_ip_pt_learn_restore(dev_id, learn_status);
+ return rv;
+ }
+
+ /* operation success...... */
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry);
+ if (busy)
+ {
+ _isis_ip_pt_learn_restore(dev_id, learn_status);
+ return SW_OK;
+ }
+ }
+
+ _isis_ip_pt_learn_restore(dev_id, learn_status);
+ if (ISIS_HOST_ENTRY_NEXT == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if (ISIS_HOST_ENTRY_SEARCH == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else if (ISIS_HOST_ENTRY_DEL == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+}
+
+static sw_error_t
+_isis_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+ a_uint32_t * hw_intf)
+{
+ sw_error_t rv;
+ a_uint32_t addr, lvid, hvid, tbl[3], i;
+ a_uint32_t sw_intf = entry->intf_id;
+ a_uint32_t vid_offset;
+
+ for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isis_mac_snap[dev_id] & (0x1 << i))
+ {
+ addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 8;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]);
+ hvid |= ((lvid & 0xff) << 4);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]);
+
+ if ((lvid <= sw_intf) && (hvid >= sw_intf))
+ {
+ vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid);
+ *hw_intf = (vid_offset << 3) | i;
+ return SW_OK;
+ }
+ }
+ }
+
+ return SW_BAD_PARAM;
+}
+
+static sw_error_t
+_isis_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf,
+ a_uint32_t * sw_intf)
+{
+ sw_error_t rv;
+ a_uint32_t addr, lvid, tbl, i;
+
+ i = hw_intf & 0x7;
+
+ addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&tbl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl);
+ *sw_intf = lvid + (hw_intf >> 3);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (255 < ((*time + 5) / 6))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = ((*time + 5) / 6);
+ *time = data * 6;
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 6;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+ a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ }
+
+ if (FAL_IP_IP6_ADDR & entry->flags)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]);
+
+ rv = _isis_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+
+ if (FAL_IP_CPU_ADDR & entry->flags)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, CPU_ADDR, 1, reg[2]);
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+
+ if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+ }
+
+ if (FAL_MAC_DROP == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, 7, reg[2]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 1, reg[3]);
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 2, reg[3]);
+ }
+ else
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 0, reg[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, ACTION, 3, reg[3]);
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[2];
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, IP_VER, data, reg[3]);
+ if (data)
+ {
+ entry->ip6_addr.ul[0] = reg[0];
+ entry->flags |= FAL_IP_IP6_ADDR;
+ }
+ else
+ {
+ entry->ip4_addr = reg[0];
+ entry->flags |= FAL_IP_IP4_ADDR;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR2, entry->mac_addr.uc[2], reg[1]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR3, entry->mac_addr.uc[3], reg[1]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR4, entry->mac_addr.uc[4], reg[1]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY1, MAC_ADDR5, entry->mac_addr.uc[5], reg[1]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR0, entry->mac_addr.uc[0], reg[2]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY2, MAC_ADDR1, entry->mac_addr.uc[1], reg[2]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY2, INTF_ID, data, reg[2]);
+ rv = _isis_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY2, CPU_ADDR, data, reg[2]);
+ if (data)
+ {
+ entry->flags |= FAL_IP_CPU_ADDR;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_EN, data, reg[3]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+ rv = _isis_ip_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->packet = cnt[0];
+ entry->byte = cnt[1];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_EN, data, reg[3]);
+ if (data)
+ {
+ entry->pppoe_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, PPPOE_IDX, data, reg[3]);
+ entry->pppoe_id = data;
+ }
+ else
+ {
+ entry->pppoe_en = A_FALSE;
+ }
+
+ if (7 == entry->port_id)
+ {
+ entry->port_id = 0;
+ entry->action = FAL_MAC_DROP;
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(HOST_ENTRY3, ACTION, data, reg[3]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < 5; i++)
+ {
+ addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < 5; i++)
+ {
+ addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (®[4]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[5] = { 0 }, op = ISIS_HOST_ENTRY_FLUSH;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_IP_ENTRY_ID_EN & del_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_IP_ENTRY_IPADDR_EN & del_mode)
+ {
+ op = ISIS_HOST_ENTRY_DEL;
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ }
+
+ if (FAL_IP_IP6_ADDR & entry->flags)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ }
+
+ if (FAL_IP_ENTRY_INTF_EN & del_mode)
+ {
+ rv = _isis_ip_intf_sw_to_hw(dev_id, entry->intf_id, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+ }
+
+ if (FAL_IP_ENTRY_PORT_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+ }
+
+ if (FAL_IP_ENTRY_STATUS_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+ }
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, op);
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_IP_ENTRY_IPADDR_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ }
+ else if (FAL_IP_IP6_ADDR & entry->flags)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP,
+ ISIS_HOST_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+ rv = _isis_host_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(entry->status))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (®[4]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t idx, data, reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = ISIS_HOST_ENTRY_NUM - 1;
+ }
+ else
+ {
+ if ((ISIS_HOST_ENTRY_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id;
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]);
+
+ if (FAL_IP_ENTRY_INTF_EN & next_mode)
+ {
+ rv = _isis_ip_intf_sw_to_hw(dev_id, entry->intf_id, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_VID, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, INTF_ID, data, reg[2]);
+ }
+
+ if (FAL_IP_ENTRY_PORT_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SP, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY2, SRC_PORT, entry->port_id, reg[2]);
+ }
+
+ if (FAL_IP_ENTRY_STATUS_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+ }
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+ rv = _isis_host_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(entry->status))
+ {
+ return SW_NO_MORE;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x7f;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ rv = _isis_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ tbl[0] = reg[0];
+ tbl[3] = (reg[3] >> 15) << 15;
+ rv = _isis_host_down_to_hw(dev_id, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 0, reg[3]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg[4] = 0x0;
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 }, tbl[5] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x7f;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_up_to_sw(dev_id, reg);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 0, reg[3]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY3, PPPOE_IDX, pppoe_id, reg[3]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ tbl[0] = reg[0];
+ tbl[3] = (reg[3] >> 15) << 15;
+ rv = _isis_host_down_to_hw(dev_id, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ reg[4] = 0x0;
+ rv = _isis_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_ARP_LEARN_REQ & flags)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ data &= (~(0x1 << port_id));
+ }
+
+ if (FAL_ARP_LEARN_ACK & flags)
+ {
+ data |= (0x1 << (8 + port_id));
+ }
+ else
+ {
+ data &= (~(0x1 << (8 + port_id)));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *flags = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data & (0x1 << port_id))
+ {
+ *flags |= FAL_ARP_LEARN_REQ;
+ }
+
+ if (data & (8 + (0x1 << port_id)))
+ {
+ *flags |= FAL_ARP_LEARN_ACK;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_ARP_LEARN_ALL == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_ARP_LEARN_LOCAL == mode)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *mode = FAL_ARP_LEARN_ALL;
+ }
+ else
+ {
+ *mode = FAL_ARP_LEARN_LOCAL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NO_SOURCE_GUARD < mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = 0;
+ if (FAL_MAC_IP_GUARD == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_IP_PORT_GUARD == mode)
+ {
+ data = 2;
+ }
+ else if (FAL_MAC_IP_VLAN_GUARD == mode)
+ {
+ data = 3;
+ }
+ else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+ {
+ data = 4;
+ }
+ reg &= (~(0x7 << (port_id * 3)));
+ reg |= ((data & 0x7) << (port_id * 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ if (FAL_NO_SOURCE_GUARD == mode)
+ {
+ data = 0;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (port_id * 3)) & 0x7;
+
+ *mode = FAL_NO_SOURCE_GUARD;
+ if (1 == data)
+ {
+ *mode = FAL_MAC_IP_GUARD;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_GUARD;
+ }
+ else if (3 == data)
+ {
+ *mode = FAL_MAC_IP_VLAN_GUARD;
+ }
+ else if (4 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ data = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+ else if (1 == data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NO_SOURCE_GUARD < mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = 0;
+ if (FAL_MAC_IP_GUARD == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_IP_PORT_GUARD == mode)
+ {
+ data = 2;
+ }
+ else if (FAL_MAC_IP_VLAN_GUARD == mode)
+ {
+ data = 3;
+ }
+ else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+ {
+ data = 4;
+ }
+ reg &= (~(0x7 << (port_id * 3)));
+ reg |= ((data & 0x7) << (port_id * 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (port_id * 3)) & 0x7;
+
+ *mode = FAL_NO_SOURCE_GUARD;
+ if (1 == data)
+ {
+ *mode = FAL_MAC_IP_GUARD;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_GUARD;
+ }
+ else if (3 == data)
+ {
+ *mode = FAL_MAC_IP_VLAN_GUARD;
+ }
+ else if (4 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ data = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+ else if (1 == data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 };
+ fal_intf_mac_entry_t * intf_entry;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isis_mac_snap[dev_id] & (0x1 << i))
+ {
+ intf_entry = &(isis_intf_snap[dev_id][i]);
+ if ((entry->vid_low == intf_entry->vid_low)
+ && (entry->vid_high == intf_entry->vid_high)
+ &&(!memcmp(&entry->mac_addr, &intf_entry->mac_addr, 6)))
+ {
+ /* all same, return OK directly */
+ if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t)))
+ {
+ return SW_OK;
+ }
+ else
+ {
+ /* update entry */
+ found = 1;
+ break;
+ }
+ }
+ else
+ {
+#if 0 /* Different mac should be ok for VID range? */
+ /* entry VID cross border, not support */
+ if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* entry VID cross border, not support */
+ if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+ {
+ return SW_BAD_PARAM;
+ }
+#endif
+ }
+ }
+ }
+
+ if (!found)
+ {
+ for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (!(isis_mac_snap[dev_id] & (0x1 << i)))
+ {
+ intf_entry = &(isis_intf_snap[dev_id][i]);
+ break;
+ }
+ }
+ }
+
+ if (ISIS_INTF_MAC_ADDR_NUM == i)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (512 <= (entry->vid_high - entry->vid_low))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+ tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+ tbl[1]);
+
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf),
+ tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4),
+ tbl[2]);
+
+ if (A_TRUE == entry->ip4_route)
+ {
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]);
+ }
+
+ if (A_TRUE == entry->ip6_route)
+ {
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]);
+ }
+
+ for (j = 0; j < 2; j++)
+ {
+ addr = ISIS_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ for (j = 0; j < 3; j++)
+ {
+ addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ isis_mac_snap[dev_id] |= (0x1 << i);
+ *intf_entry = *entry;
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t addr, tbl[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(FAL_IP_ENTRY_ID_EN & del_mode))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (ISIS_INTF_MAC_ADDR_NUM <= entry->entry_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* clear valid bits */
+ addr = ISIS_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isis_mac_snap[dev_id] &= (~(0x1 << entry->entry_id));
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, idx, addr, tbl[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISIS_INTF_MAC_ADDR_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id + 1;
+ }
+ }
+
+ for (i = idx; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isis_mac_snap[dev_id] & (0x1 << i))
+ {
+ break;
+ }
+ }
+
+ if (ISIS_INTF_MAC_ADDR_NUM == i)
+ {
+ return SW_NO_MORE;
+ }
+
+ for (j = 0; j < 3; j++)
+ {
+ addr = ISIS_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t));
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+ tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+ tbl[1]);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]);
+ entry->vid_high = j & 0xf;
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]);
+ entry->vid_high |= ((j & 0xff) << 4);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]);
+ if (j)
+ {
+ entry->ip4_route = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]);
+ if (j)
+ {
+ entry->ip6_route = A_TRUE;
+ }
+
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+#define ISIS_WCMP_ENTRY_MAX_ID 3
+#define ISIS_WCMP_HASH_MAX_NUM 16
+#define ISIS_IP_ENTRY_MAX_ID 127
+
+#define ISIS_WCMP_HASH_TBL_ADDR 0x0e10
+#define ISIS_WCMP_NHOP_TBL_ADDR 0x0e20
+
+static sw_error_t
+_isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, addr, data;
+ a_uint8_t idx, ptr[4] = { 0 }, pos[16] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_WCMP_HASH_MAX_NUM < wcmp->nh_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < wcmp->nh_nr; i++)
+ {
+ if (ISIS_IP_ENTRY_MAX_ID < wcmp->nh_id[i])
+ {
+ return SW_BAD_PARAM;
+ }
+
+ idx = 4;
+ for (j = 0; j < 4; j++)
+ {
+ if (ptr[j] & 0x80)
+ {
+ if ((ptr[j] & 0x7f) == wcmp->nh_id[i])
+ {
+ idx = j;
+ break;
+ }
+ }
+ else
+ {
+ idx = j;
+ }
+ }
+
+ if (4 == idx)
+ {
+ return SW_BAD_PARAM;
+ }
+ else
+ {
+ ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80;
+ pos[i] = idx;
+ }
+ }
+
+ data = 0;
+ for (j = 0; j < 4; j++)
+ {
+ data |= (ptr[j] << (j << 3));
+ }
+
+ addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 0;
+ for (j = 0; j < 16; j++)
+ {
+ data |= (pos[j] << (j << 1));
+ }
+
+ addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, data;
+ a_uint8_t ptr[4] = { 0 }, pos[16] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISIS_WCMP_ENTRY_MAX_ID < wcmp_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ wcmp->nh_nr = ISIS_WCMP_HASH_MAX_NUM;
+
+ addr = ISIS_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 4; i++)
+ {
+ ptr[i] = (data >> (i << 3)) & 0x7f;
+ }
+
+ addr = ISIS_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 16; i++)
+ {
+ pos[i] = (data >> (i << 1)) & 0x3;
+ }
+
+ for (i = 0; i < 16; i++)
+ {
+ wcmp->nh_id[i] = ptr[pos[i]];
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_WCMP_HASH_KEY_SIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_DIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_SPORT & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_DPORT & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data);
+ }
+
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data, field;
+
+ *hash_mode = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_SIP;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_SPORT;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_DPORT;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_ip_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_host_entry_commit(dev_id, ISIS_ENTRY_ARP, ISIS_HOST_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ isis_mac_snap[dev_id] = 0;
+ for (i = 0; i < ISIS_INTF_MAC_ADDR_NUM; i++)
+ {
+ addr = ISIS_INTF_MAC_TBL2_ADDR + (i << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry added related interface entry and ip6 base address
+ must be set at first.
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_add(dev_id, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_del(dev_id, del_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_get(dev_id, get_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For next_mode please refer IP entry operation flags.
+ For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_next(dev_id, next_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_pt_arp_learn_set(dev_id, port_id, flags);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_pt_arp_learn_get(dev_id, port_id, flags);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_arp_learn_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_arp_learn_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_source_guard_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_source_guard_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_unk_source_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_unk_source_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_arp_guard_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_arp_guard_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_arp_unk_source_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_arp_unk_source_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_route_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_route_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_intf_entry_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_intf_entry_del(dev_id, del_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_intf_entry_next(dev_id, next_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details Comments:
+ * This operation will set dynamic entry aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP WCMP table one particular device.
+ * @details Comments:
+ * Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[in] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP WCMP table one particular device.
+ * @details Comments:
+ * Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[out] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_ip_init(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = isis_ip_reset(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->ip_host_add = isis_ip_host_add;
+ p_api->ip_host_del = isis_ip_host_del;
+ p_api->ip_host_get = isis_ip_host_get;
+ p_api->ip_host_next = isis_ip_host_next;
+ p_api->ip_host_counter_bind = isis_ip_host_counter_bind;
+ p_api->ip_host_pppoe_bind = isis_ip_host_pppoe_bind;
+ p_api->ip_pt_arp_learn_set = isis_ip_pt_arp_learn_set;
+ p_api->ip_pt_arp_learn_get = isis_ip_pt_arp_learn_get;
+ p_api->ip_arp_learn_set = isis_ip_arp_learn_set;
+ p_api->ip_arp_learn_get = isis_ip_arp_learn_get;
+ p_api->ip_source_guard_set = isis_ip_source_guard_set;
+ p_api->ip_source_guard_get = isis_ip_source_guard_get;
+ p_api->ip_unk_source_cmd_set = isis_ip_unk_source_cmd_set;
+ p_api->ip_unk_source_cmd_get = isis_ip_unk_source_cmd_get;
+ p_api->ip_arp_guard_set = isis_ip_arp_guard_set;
+ p_api->ip_arp_guard_get = isis_ip_arp_guard_get;
+ p_api->arp_unk_source_cmd_set = isis_arp_unk_source_cmd_set;
+ p_api->arp_unk_source_cmd_get = isis_arp_unk_source_cmd_get;
+ p_api->ip_route_status_set = isis_ip_route_status_set;
+ p_api->ip_route_status_get = isis_ip_route_status_get;
+ p_api->ip_intf_entry_add = isis_ip_intf_entry_add;
+ p_api->ip_intf_entry_del = isis_ip_intf_entry_del;
+ p_api->ip_intf_entry_next = isis_ip_intf_entry_next;
+ p_api->ip_age_time_set = isis_ip_age_time_set;
+ p_api->ip_age_time_get = isis_ip_age_time_get;
+ p_api->ip_wcmp_hash_mode_set = isis_ip_wcmp_hash_mode_set;
+ p_api->ip_wcmp_hash_mode_get = isis_ip_wcmp_hash_mode_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_leaky.c b/src/hsl/isis/isis_leaky.c
new file mode 100644
index 0000000..05ba6ec
--- /dev/null
+++ b/src/hsl/isis/isis_leaky.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_leaky ISIS_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_leaky.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_uc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_uc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_arp_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_arp_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_uc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_uc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_mc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_mc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_leaky_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->uc_leaky_mode_set = isis_uc_leaky_mode_set;
+ p_api->uc_leaky_mode_get = isis_uc_leaky_mode_get;
+ p_api->mc_leaky_mode_set = isis_mc_leaky_mode_set;
+ p_api->mc_leaky_mode_get = isis_mc_leaky_mode_get;
+ p_api->port_arp_leaky_set = isis_port_arp_leaky_set;
+ p_api->port_arp_leaky_get = isis_port_arp_leaky_get;
+ p_api->port_uc_leaky_set = isis_port_uc_leaky_set;
+ p_api->port_uc_leaky_get = isis_port_uc_leaky_get;
+ p_api->port_mc_leaky_set = isis_port_mc_leaky_set;
+ p_api->port_mc_leaky_get = isis_port_mc_leaky_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_led.c b/src/hsl/isis/isis_led.c
new file mode 100644
index 0000000..aba9601
--- /dev/null
+++ b/src/hsl/isis/isis_led.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_led ISIS_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "isis_led.h"
+#include "isis_reg.h"
+
+#define MAX_LED_PATTERN_ID 2
+#define LED_PATTERN_ADDR 0x50
+
+static sw_error_t
+_isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, mode;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ mode = 0;
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ mode = 1;
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ mode = 2;
+ }
+ else if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ mode = 3;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+ }
+ else if (LED_BLINK_TXRX == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ reg &= 0xffff;
+ reg |= (data << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= data;
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ if (0 == id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+ }
+ else if (1 == id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, tmp;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ data = (reg >> 16) & 0xffff;
+ }
+ else
+ {
+ data = reg & 0xffff;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_OFF;
+ }
+ else if (1 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_BLINK;
+ }
+ else if (2 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_ON;
+ }
+ else
+ {
+ pattern->mode = LED_PATTERN_MAP_EN;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->freq = LED_BLINK_2HZ;
+ }
+ else if (1 == tmp)
+ {
+ pattern->freq = LED_BLINK_4HZ;
+ }
+ else if (2 == tmp)
+ {
+ pattern->freq = LED_BLINK_8HZ;
+ }
+ else
+ {
+ pattern->freq = LED_BLINK_TXRX;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isis_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_led_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->led_ctrl_pattern_set = isis_led_ctrl_pattern_set;
+ p_api->led_ctrl_pattern_get = isis_led_ctrl_pattern_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_mac_block.c b/src/hsl/isis/isis_mac_block.c
new file mode 100644
index 0000000..2750a25
--- /dev/null
+++ b/src/hsl/isis/isis_mac_block.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_port_ctrl.h"
+#include "isis_mib.h"
+#include "isis_misc.h"
+#include "isis_reg.h"
+#include "f1_phy.h"
+
+#include <linux/autoconf.h>
+#include <linux/kthread.h>
+#include <linux/in.h>
+#include <linux/if.h>
+#include <linux/inet.h>
+#include <linux/inetdevice.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/skbuff.h>
+#include <linux/ip.h>
+#include <linux/udp.h>
+#include <linux/rculist_nulls.h>
+
+static struct task_struct *mac_scan_task;
+static a_bool_t qca_phy_info[7] = {A_FALSE};
+static a_bool_t qca_portvlan_mem_info[7] = {A_FALSE};
+static struct net_device *master_dev = NULL;
+static fal_port_t uplink_portid =5;
+
+static void qca_cpu_pkt_xmit(struct net_device *dev)
+{
+ if (dev)
+ {
+ arp_send(ARPOP_RREQUEST, ETH_P_RARP, 0, dev, 0, NULL,
+ dev->dev_addr, dev->dev_addr);
+ }
+}
+
+static a_bool_t
+_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+ if ((0 == port_id) || (6 == port_id))
+ {
+ return A_FALSE;
+ }
+ else
+ {
+ return A_TRUE;
+ }
+}
+
+
+
+static sw_error_t qca_isis_rec_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t reg_val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+}
+
+
+static sw_error_t qca_isis_nor_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed, fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t reg_val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+ }
+
+ if (duplex == FAL_FULL_DUPLEX)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+}
+
+
+static void qca_mac_ctrl_init(void)
+{
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+ a_uint32_t dev_id = 0, reg_val = 0, reg_save = 0;
+ sw_error_t rv;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return;
+
+ /* for port property set, SSDK should not generate some limitations */
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ continue;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+
+ reg_save = reg_val;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+
+ }
+
+ isis_mib_status_set(dev_id, A_TRUE);
+}
+
+static void qca_mac_phy_poll(void)
+{
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+ a_uint32_t dev_id = 0, phy_id = 0;
+ a_bool_t status, lastStatus;
+ fal_mib_info_t counter;
+ fal_port_speed_t speed;
+ fal_port_duplex_t duplex;
+ a_uint32_t txok = 0;
+ sw_error_t rv;
+ a_uint32_t reg_val;
+ a_uint32_t index;
+ fal_pbmp_t uplink_portvlanmem = 0;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return;
+
+
+ /* for port property set, SSDK should not generate some limitations */
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ continue;
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ if (rv != SW_OK)
+ continue;
+
+ status = f1_phy_get_link_status(dev_id, phy_id);
+
+ lastStatus = qca_phy_info[phy_id];
+
+ if (lastStatus)
+ {
+ /*phy from up to down, disable mac rx/tx*/
+ if (!status)
+ {
+
+ /*make sure UNI port doesn't forward these types of pkts*/
+ isis_port_bc_filter_set(dev_id, port_id, A_TRUE);
+ isis_port_unk_mc_filter_set(dev_id, port_id, A_TRUE);
+ isis_port_unk_uc_filter_set(dev_id, port_id, A_TRUE);
+
+ /*make sure traffic from uplink port doesn't go to UNI port*/
+ isis_portvlan_member_get(0, uplink_portid, &uplink_portvlanmem);
+ if ((0x1UL<<port_id) & uplink_portvlanmem)
+ {
+ isis_portvlan_member_del(dev_id, uplink_portid, port_id);
+ qca_portvlan_mem_info[port_id] = A_TRUE;
+ printk("%s: del UNI port %d from uplink portID %d\n", __FUNCTION__, port_id, uplink_portid);
+ }
+ isis_port_force_portvlan_set(dev_id, uplink_portid, A_TRUE);
+
+ /*make sure traffic from cpu port doesn't go to UNI port*/
+ isis_port_force_portvlan_set(dev_id, 0, A_TRUE);
+ isis_portvlan_member_del(dev_id, 0, port_id);
+
+ index = 0;
+ /*loop used to make sure that the packets in the buffer are sent out*/
+ do
+ {
+ index ++;
+ }
+ while (index < 100);
+
+ /*disable UNI port rx/tx*/
+ isis_port_txmac_status_set(dev_id, port_id, A_FALSE);
+ isis_port_rxmac_status_set(dev_id, port_id, A_FALSE);
+ qca_phy_info[phy_id] = status;
+
+
+ isis_get_mib_info(dev_id, port_id, &counter);
+ txok = counter.Tx64Byte +
+ counter.Tx128Byte +
+ counter.Tx256Byte +
+ counter.Tx512Byte +
+ counter.Tx1024Byte +
+ counter.Tx1518Byte +
+ counter.TxMaxByte;
+ printk("%s: port %d down, counter %d\n", __FUNCTION__, port_id,
+ txok);
+ }
+ }
+ else
+ {
+ /*phy from down to up, disable mac rx/tx*/
+ if (status)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ if (SW_OK == f1_phy_get_speed(dev_id, phy_id, &speed))
+ qca_isis_rec_port_speed_set(dev_id, port_id, speed);
+
+ isis_port_txmac_status_set(dev_id, port_id, A_TRUE);
+
+ /*make sure cpu port can send pkts to UNI port*/
+ isis_portvlan_member_add(0, 0, port_id);
+ isis_port_force_portvlan_set(0, 0, A_FALSE);
+
+ /*detct port tx counts*/
+ isis_get_mib_info(dev_id, port_id, &counter);
+ txok = counter.Tx64Byte +
+ counter.Tx128Byte +
+ counter.Tx256Byte +
+ counter.Tx512Byte +
+ counter.Tx1024Byte +
+ counter.Tx1518Byte +
+ counter.TxMaxByte;
+ printk("%s: counter before sending pkts %d for port %d\n", __FUNCTION__,
+ txok, port_id);
+
+ /*make sure cpu port can send pkts to UNI port*/
+ isis_port_bc_filter_set(dev_id, port_id, A_FALSE);
+ isis_port_unk_mc_filter_set(dev_id, port_id, A_FALSE);
+ isis_port_unk_uc_filter_set(dev_id, port_id, A_FALSE);
+
+ do
+ {
+ qca_cpu_pkt_xmit(master_dev);
+ memset(&counter, 0, sizeof(fal_mib_info_t));
+ isis_get_mib_info(dev_id, port_id, &counter);
+ txok = counter.Tx64Byte +
+ counter.Tx128Byte +
+ counter.Tx256Byte +
+ counter.Tx512Byte +
+ counter.Tx1024Byte +
+ counter.Tx1518Byte +
+ counter.TxMaxByte;
+ printk("%s: cpu send pkts for port_id %d\n", __FUNCTION__, port_id);
+ }
+ while(txok == 0);
+
+ f1_phy_get_speed(dev_id, phy_id, &speed);
+ f1_phy_get_duplex(dev_id, phy_id, &duplex);
+ isis_port_txmac_status_set(dev_id, port_id, A_FALSE);
+ isis_port_rxmac_status_set(dev_id, port_id, A_FALSE);
+ qca_isis_nor_port_speed_set(dev_id, port_id, speed, duplex);
+ isis_port_txmac_status_set(dev_id, port_id, A_TRUE);
+ isis_port_rxmac_status_set(dev_id, port_id, A_TRUE);
+
+ /*restore uplink port-base vlan state*/
+ if (qca_portvlan_mem_info[port_id])
+ {
+ isis_portvlan_member_add(0, uplink_portid, port_id);
+ qca_portvlan_mem_info[port_id] = A_FALSE;
+ printk("%s: add UNI port %d to uplink portID %d\n", __FUNCTION__, port_id, uplink_portid);
+ }
+ isis_port_force_portvlan_set(0, uplink_portid, A_FALSE);
+
+ qca_phy_info[phy_id] = status;
+
+ }
+
+ }
+
+ }
+}
+
+static a_int32_t
+qca_mac_scan_thread(void *param)
+{
+#define QCA_MAC_SCAN_POLLING_MSEC 500
+
+ qca_mac_ctrl_init();
+
+ while(1)
+ {
+
+ qca_mac_phy_poll();
+
+ msleep_interruptible(QCA_MAC_SCAN_POLLING_MSEC);
+ }
+
+
+ return 0;
+}
+
+void
+qca_mac_scan_helper_init(void)
+{
+ const char mac_thread_name[] = "mac_scan";
+
+ mac_scan_task = kthread_create(qca_mac_scan_thread, NULL, mac_thread_name);
+
+
+ if(IS_ERR(mac_scan_task))
+ {
+ aos_printk("thread: %s create fail\n", mac_thread_name);
+ return;
+ }
+
+ wake_up_process(mac_scan_task);
+
+ printk("thread: %s create success pid:%d\n",
+ mac_thread_name, mac_scan_task->pid);
+}
+
+
+void
+qca_mac_scan_helper_exit(void)
+{
+ if(mac_scan_task)
+ {
+ kthread_stop(mac_scan_task);
+ }
+}
+
+void qca_set_master_dev(struct net_device *dev)
+{
+ master_dev = dev;
+
+}
+
+
+
diff --git a/src/hsl/isis/isis_mib.c b/src/hsl/isis/isis_mib.c
new file mode 100644
index 0000000..9853058
--- /dev/null
+++ b/src/hsl/isis/isis_mib.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_mib ISIS_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mib.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mib_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mib_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = isis_get_mib_info;
+ p_api->mib_status_set = isis_mib_status_set;
+ p_api->mib_status_get = isis_mib_status_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_mirror.c b/src/hsl/isis/isis_mirror.c
new file mode 100644
index 0000000..fdd67c3
--- /dev/null
+++ b/src/hsl/isis/isis_mirror.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_mirror ISIS_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_mirror.h"
+#include "isis_reg.h"
+
+static sw_error_t
+_isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *port_id = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_analysis_port_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_analysis_port_get(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_port_in_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_port_in_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_port_eg_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_mirr_port_eg_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_mirr_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->mirr_analysis_port_set = isis_mirr_analysis_port_set;
+ p_api->mirr_analysis_port_get = isis_mirr_analysis_port_get;
+ p_api->mirr_port_in_set = isis_mirr_port_in_set;
+ p_api->mirr_port_in_get = isis_mirr_port_in_get;
+ p_api->mirr_port_eg_set = isis_mirr_port_eg_set;
+ p_api->mirr_port_eg_get = isis_mirr_port_eg_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_misc.c b/src/hsl/isis/isis_misc.c
new file mode 100644
index 0000000..29a4cf3
--- /dev/null
+++ b/src/hsl/isis/isis_misc.c
@@ -0,0 +1,1810 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_misc ISIS_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_misc.h"
+#include "isis_reg.h"
+#include "f1_phy.h"
+
+#define ISIS_MAX_FRMAE_SIZE 9216
+
+#define ARP_REQ_EN_OFFSET 6
+#define ARP_ACK_EN_OFFSET 5
+#define DHCP_EN_OFFSET 4
+#define EAPOL_EN_OFFSET 3
+
+#define ISIS_SWITCH_INT_PHY_INT 0x8000
+
+static sw_error_t
+_isis_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << ((port_id << 3) + item));
+ reg |= (val << ((port_id << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+ reg |= (val << (((port_id - 4) << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ return rv;
+}
+
+static sw_error_t
+_isis_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+ }
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_FRMAE_SIZE < size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = size;
+ HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *size = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (0 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+#define ISIS_MAX_PPPOE_SESSION 16
+#define ISIS_MAX_SESSION_ID 0xffff
+
+static sw_error_t
+_isis_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id, entry_idx = ISIS_MAX_PPPOE_SESSION;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((A_FALSE == session_tbl->multi_session)
+ && (A_TRUE == session_tbl->uni_session))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((A_FALSE == session_tbl->multi_session)
+ && (A_FALSE == session_tbl->uni_session))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (!valid)
+ {
+ entry_idx = i;
+ }
+ else if (id == session_tbl->session_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+
+ if (ISIS_MAX_PPPOE_SESSION == entry_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (A_TRUE == session_tbl->uni_session)
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+ }
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id,
+ reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ session_tbl->entry_id = entry_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISIS_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISIS_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+ {
+ if (1 == valid)
+ {
+ session_tbl->multi_session = A_TRUE;
+ session_tbl->uni_session = A_FALSE;
+ }
+ else
+ {
+ session_tbl->multi_session = A_TRUE;
+ session_tbl->uni_session = A_TRUE;
+ }
+
+ session_tbl->entry_id = i;
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISIS_MAX_PPPOE_SESSION <= index)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAX_SESSION_ID < id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg = 0;
+ SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+ a_uint32_t reg, tmp;
+
+ if (ISIS_MAX_PPPOE_SESSION <= index)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ tmp = 0;
+ SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg);
+ *id = tmp;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS)
+ {
+ reg |= ISIS_SWITCH_INT_PHY_INT;
+ }
+ else
+ {
+ reg &= (~ISIS_SWITCH_INT_PHY_INT);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ *intr_mask = 0;
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (reg & ISIS_SWITCH_INT_PHY_INT)
+ {
+ *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ *intr_status = 0;
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (reg & ISIS_SWITCH_INT_PHY_INT)
+ {
+ *intr_status |= FAL_SWITCH_INTR_LINK_STATUS;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ reg = 0;
+ if (intr_status & FAL_SWITCH_INTR_LINK_STATUS)
+ {
+ reg |= ISIS_SWITCH_INT_PHY_INT;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_status_get(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_frame_max_size_set(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_frame_max_size_get(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_unk_uc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_unk_uc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_unk_mc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_unk_mc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_bc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_bc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cpu_port_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_cpu_port_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling arp packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_arp_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_arp_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling eapol packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_eapol_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_eapol_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_add(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_session_add(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_del(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_session_del(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_table_get(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_session_get(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_session_id_set(dev_id, index, id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry from a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_pppoe_session_id_get(dev_id, index, id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ripv1_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_ripv1_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_set(dev_id, port_id, enable,
+ ARP_REQ_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_get(dev_id, port_id, enable,
+ ARP_REQ_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_set(dev_id, port_id, enable,
+ ARP_ACK_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_misc_property_get(dev_id, port_id, enable,
+ ARP_ACK_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_intr_mask_set(dev_id, intr_mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_intr_mask_get(dev_id, intr_mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_intr_status_get(dev_id, intr_status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_intr_status_clear(dev_id, intr_status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_link_intr_status_get(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_misc_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->frame_max_size_set = isis_frame_max_size_set;
+ p_api->frame_max_size_get = isis_frame_max_size_get;
+ p_api->port_unk_uc_filter_set = isis_port_unk_uc_filter_set;
+ p_api->port_unk_uc_filter_get = isis_port_unk_uc_filter_get;
+ p_api->port_unk_mc_filter_set = isis_port_unk_mc_filter_set;
+ p_api->port_unk_mc_filter_get = isis_port_unk_mc_filter_get;
+ p_api->port_bc_filter_set = isis_port_bc_filter_set;
+ p_api->port_bc_filter_get = isis_port_bc_filter_get;
+ p_api->cpu_port_status_set = isis_cpu_port_status_set;
+ p_api->cpu_port_status_get = isis_cpu_port_status_get;
+ p_api->pppoe_cmd_set = isis_pppoe_cmd_set;
+ p_api->pppoe_cmd_get = isis_pppoe_cmd_get;
+ p_api->pppoe_status_set = isis_pppoe_status_set;
+ p_api->pppoe_status_get = isis_pppoe_status_get;
+ p_api->port_dhcp_set = isis_port_dhcp_set;
+ p_api->port_dhcp_get = isis_port_dhcp_get;
+ p_api->arp_cmd_set = isis_arp_cmd_set;
+ p_api->arp_cmd_get = isis_arp_cmd_get;
+ p_api->eapol_cmd_set = isis_eapol_cmd_set;
+ p_api->eapol_cmd_get = isis_eapol_cmd_get;
+ p_api->pppoe_session_table_add = isis_pppoe_session_table_add;
+ p_api->pppoe_session_table_del = isis_pppoe_session_table_del;
+ p_api->pppoe_session_table_get = isis_pppoe_session_table_get;
+ p_api->pppoe_session_id_set = isis_pppoe_session_id_set;
+ p_api->pppoe_session_id_get = isis_pppoe_session_id_get;
+ p_api->eapol_status_set = isis_eapol_status_set;
+ p_api->eapol_status_get = isis_eapol_status_get;
+ p_api->ripv1_status_set = isis_ripv1_status_set;
+ p_api->ripv1_status_get = isis_ripv1_status_get;
+ p_api->port_arp_req_status_set = isis_port_arp_req_status_set;
+ p_api->port_arp_req_status_get = isis_port_arp_req_status_get;
+ p_api->port_arp_ack_status_set = isis_port_arp_ack_status_set;
+ p_api->port_arp_ack_status_get = isis_port_arp_ack_status_get;
+ p_api->intr_mask_set = isis_intr_mask_set;
+ p_api->intr_mask_get = isis_intr_mask_get;
+ p_api->intr_status_get = isis_intr_status_get;
+ p_api->intr_status_clear = isis_intr_status_clear;
+ p_api->intr_port_link_mask_set = isis_intr_port_link_mask_set;
+ p_api->intr_port_link_mask_get = isis_intr_port_link_mask_get;
+ p_api->intr_port_link_status_get = isis_intr_port_link_status_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isis/isis_multicast_acl.c b/src/hsl/isis/isis_multicast_acl.c
new file mode 100644
index 0000000..496d5f0
--- /dev/null
+++ b/src/hsl/isis/isis_multicast_acl.c
@@ -0,0 +1,1000 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_igmp.h"
+#include "isis_reg.h"
+#include "fal_multi.h"
+#include "fal_acl.h"
+#include "hsl_shared_api.h"
+#include "sal/os/aos_lock.h"
+
+#if 0
+/**
+ * I/F prototype for complete igmpv3 & mldv2 support
+ */
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+ FAL_ADDR_IPV4 = 0,
+ FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+ fal_addr_type_t type;
+ union
+ {
+ fal_ip4_addr_t ip4_addr;
+ fal_ip6_addr_t ip6_addr;
+ } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+ fal_igmp_sg_addr_t source;
+ fal_igmp_sg_addr_t group;
+ fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+/**
+ * @brief set PortMap of IGMP sg entry.
+ * search entry according to source/group address,
+ * update PortMap if SG entry is found, otherwise create a new sg entry.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+/**
+ * @brief clear PortMap of IGMP sg entry.
+ * search entry according to source/group address,
+ * update PortMap if SG entry is found, delete the entry in case PortMap was 0.
+ * SW_NOT_FOUND will be returned in case search failed.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI 5
+
+#define MULT_ACTION_SET 1
+#define MULT_ACTION_CLEAR 1
+
+static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+ a_uint8_t index; //MAX is 32
+ fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+#endif
+void
+isis_multicast_init(a_uint32_t dev_id);
+
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry);
+
+static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX];
+static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX];
+
+static int ip6_addr_is_null(fal_ip6_addr_t *ip6)
+{
+ if (NULL == ip6)
+ {
+ aos_printk("Invalid ip6 address\n");
+ return -1;
+ }
+ if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3])
+ return 1;
+ else
+ return 0;
+}
+static int multi_source_is_null(fal_igmp_sg_addr_t *s)
+{
+ if (NULL == s)
+ {
+ aos_printk("Invalid source address\n");
+ return -1;
+ }
+ if(0 == s->type && 0==s->u.ip4_addr)
+ return 1;
+ if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr)))
+ return 1;
+
+ return 0;
+}
+
+HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t rule_id;
+ sw_error_t ret;
+ fal_acl_rule_t rule= {0};
+
+ if(start_n>=FAL_IGMP_SG_ENTRY_MAX)
+ {
+ return -1;
+ }
+
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ ret = ACL_RULE_QUERY(dev_id, list_id, rule_id, &rule);
+
+ if (ret==SW_NOT_FOUND )
+ break;//NOT found in ACL rule
+
+ multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n
+ //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n",
+ //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports);
+
+ if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val)) //only ip4
+ {
+ multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4;
+ multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4;
+ multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val;
+ multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val;
+ multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+ }
+ else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val)) //only ip6
+ {
+ multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6;
+ multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6;
+ memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val));
+ memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val));
+ multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+ }
+ }
+
+ return rule_id+start_n;
+}
+/*
+** Iterate the total 32 multicast ACL entries.
+ After the function completes:
+ 1. Stores all multicast related ACL rules in multi_acl_info[32]
+ 2. return the number of multicast related ACL rules
+*/
+HSL_LOCAL a_uint32_t isis_multicast_acl_query(void)
+{
+ int start_n;
+ int total_n;
+ //a_uint32_t i;
+
+ start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0);
+ if(-1 == start_n)
+ aos_printk("ACL rule1 is FULL\n");
+ total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n);
+ if(-1 == total_n)
+ aos_printk("ACL rule2 is FULL\n");
+
+ MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n);
+ /*
+ for(i=0;i<total_n;i++)
+ MULTI_DEBUG("KKK, indx=%d, multi_acl_info[%d].entry=[%d][%x]\n", multi_acl_info[i].index,i,
+ multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip4_addr );
+ */
+
+ return total_n;
+}
+
+HSL_LOCAL a_uint32_t isis_multicast_acl_total_n(a_uint32_t list_id)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t ret;
+ a_uint32_t rule_id;
+ fal_acl_rule_t rule= {0};
+
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ ret = ACL_RULE_QUERY(dev_id, list_id,
+ rule_id, &rule);
+ if(ret==SW_NOT_FOUND)
+ return rule_id;
+
+ }
+ return 0;
+}
+
+HSL_LOCAL a_uint32_t isis_acl_multigroup_cmp(fal_igmp_sg_addr_t *group, fal_acl_rule_t* rule)
+{
+ if(group->type == FAL_ADDR_IPV4)
+ return memcmp(&group->u.ip4_addr, &rule->dest_ip4_val, sizeof(rule->dest_ip4_val));
+ else if(group->type == FAL_ADDR_IPV6)
+ return memcmp(group->u.ip6_addr.ul, rule->dest_ip6_val.ul, sizeof(rule->dest_ip6_val));
+
+ return -1;
+}
+
+
+#define ISIS_FILTER_ACT_ADDR 0x5a000
+#define ISIS_FILTER_MSK_ADDR 0x59000
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set_all(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+ a_uint32_t i, base, addr;
+ a_uint32_t dev_id=0;
+ a_uint32_t msk_valid=0;
+ sw_error_t rv;
+
+ /* 2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end*/
+ for(i=pos; i<pos+4; i++)
+ {
+ base = ISIS_FILTER_MSK_ADDR +(i<<5);
+ addr = base+(4<<2); //fifth byte
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&msk_valid),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+ if ((((msk_valid>>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2))
+ {
+ rv = multi_portmap_aclreg_set(i, entry);
+ break;
+ }
+ else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1))
+ {
+ rv = multi_portmap_aclreg_set(i, entry);
+ continue;
+ }
+ else
+ {
+ aos_printk("The rule valid bit:6 7 is wrong!!!");
+ break;
+ }
+ }
+ return rv;
+}
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+ a_uint32_t i, base, addr;
+ a_uint32_t dev_id=0;
+ sw_error_t rv;
+ a_uint32_t act[3]= {0};
+ fal_pbmp_t pm;
+
+ pm = entry->port_map;
+
+ base = ISIS_FILTER_ACT_ADDR + (pos << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[i]),
+ sizeof (a_uint32_t));
+ //MULTI_DEBUG("2:Get register value 0x%x =%x\n", addr, act[i]);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ act[1] &= ~(0x7<<29); // clear the high 3 bits
+ act[1] |= (pm&0x7)<<29; //the low 3 bits of pm means redirect port 0,1,2
+
+ /* New modification: update acl ACTION register from DENY to redirect */
+ if((act[2]>>6)&0x7 == 0x7 ) //DENY mode
+ {
+ if(pm)
+ {
+ act[2] &= ~(0x7<<6);//clear DENY bits
+ act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable
+ }
+ }
+ else if((act[2]>>4)&0x1 == 0x1) //redirect mode
+ {
+ if(pm==0)
+ {
+ act[2] &= ~(0x1<<4);//clear redirect bits
+ act[2] |= (0x7<<6); //set to DENY
+ }
+ }
+
+ act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6
+ act[2] |= (pm>>3)&0xf;
+
+ addr = base + (1<<2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[1]), sizeof (a_uint32_t));
+ addr = base + (2<<2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[2]), sizeof (a_uint32_t));
+ MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]);
+ if((rv = ACL_RULE_SYNC_MULTI_PORTMAP(dev_id, pos, act)) < 0)
+ aos_printk("Sync multicast portmap error\n");
+ return rv;
+}
+
+HSL_LOCAL int multi_get_dp()
+{
+ a_uint32_t addr;
+ a_uint32_t dev_id=0;
+ sw_error_t rv;
+ int val=0;
+
+ addr = 0x624;//GLOBAL_FW_CTRL1
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP
+
+ return val;
+}
+static int old_bind_p=-1;
+HSL_LOCAL int multi_acl_bind()
+{
+ int bind_p;
+ int i;
+
+ bind_p = multi_get_dp();
+ if(bind_p == old_bind_p)
+ return 0;
+ old_bind_p = bind_p;
+
+ for(i=0; i<6; i++)
+ {
+ ACL_LIST_UNBIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_UNBIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+
+ if(bind_p==0)
+ {
+ for(i=0; i<6; i++)
+ {
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+ }
+ else
+ {
+ for(i=0; i<6; i++)
+ if((bind_p>>i) &0x1)
+ {
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+ else
+ continue;
+ }
+}
+/*
+** Only update the related portmap from the privious input.
+*/
+HSL_LOCAL sw_error_t isis_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+ a_uint32_t dev_id=0;
+ //a_uint32_t list_pos;
+ a_uint32_t rule_pos;
+ a_uint32_t list_pri;
+ sw_error_t rv;
+
+ //if(entry->port_map < 1 || acl_index<0)
+ if(acl_index<0)
+ aos_printk("Something is wrong...\n");
+
+ if(list_id == FAL_ACL_LIST_MULTICAST) //Update all matched group based acl_rule->source
+ list_pri=FAL_MULTICAST_PRI;
+ else if(list_id == FAL_ACL_LIST_MULTICAST+1) //only update the specific (G,*)entry
+ list_pri=FAL_MULTICAST_PRI+1;
+
+
+ //list_pos = isis_acl_rule_get_pos(dev_id, list_id, list_pri);
+ rule_pos = ACL_RULE_GET_OFFSET(dev_id, list_id, multi_acl_group[acl_index].index);
+ if(MULT_ACTION_SET == action)
+ {
+ multi_acl_group[acl_index].entry.port_map |= entry->port_map;
+ if(entry->port_map == 0)
+ {
+ multi_acl_group[acl_index].entry.port_map = 0;
+ }
+ }
+ else if(MULT_ACTION_CLEAR == action)
+ multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map);
+
+ rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry);
+
+ multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+ return rv;
+}
+
+HSL_LOCAL sw_error_t sw_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t rule_pos;
+ a_uint32_t list_pri;
+
+ if(list_id == FAL_ACL_LIST_MULTICAST) //Update all matched group based acl_rule->source
+ list_pri=FAL_MULTICAST_PRI;
+ else if(list_id == FAL_ACL_LIST_MULTICAST+1) //only update the specific (G,*)entry
+ list_pri=FAL_MULTICAST_PRI+1;
+
+ rule_pos = ACL_RULE_GET_OFFSET(dev_id, list_id, multi_acl_group[acl_index].index);
+
+ MULTI_DEBUG("SW update: rule_pos=%d, index=%d, old portmap=%x\n",
+ rule_pos, acl_index, multi_acl_group[acl_index].entry.port_map);
+ if(MULT_ACTION_SET == action)
+ entry->port_map |= multi_acl_group[acl_index].entry.port_map;
+ else if(MULT_ACTION_CLEAR == action)
+ entry->port_map &= ~multi_acl_group[acl_index].entry.port_map;
+
+ return SW_OK;
+}
+
+
+HSL_LOCAL sw_error_t isis_multicast_acl_del(int list_id, int index)
+{
+ sw_error_t rv;
+ int rule_id;
+
+ rule_id = multi_acl_group[index].index;
+
+ rv = ACL_RULE_DEL(0, list_id, rule_id, 1);
+ multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+}
+
+/*
+** Add new acl rule with parameters: DIP, SIP, redirect port.
+*/
+HSL_LOCAL sw_error_t isis_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t val;
+ a_uint32_t pos;
+ fal_acl_rule_t acl= {0};
+
+ /* IPv4 multicast */
+ if( entry->group.type == FAL_ADDR_IPV4 )
+ {
+ MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type,
+ entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr);
+
+ acl.rule_type = FAL_ACL_RULE_IP4;
+
+ if(entry->group.u.ip4_addr!= 0)
+ {
+ acl.dest_ip4_val = entry->group.u.ip4_addr;
+ acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+ if(entry->source.u.ip4_addr!= 0)
+ {
+ acl.src_ip4_val = entry->source.u.ip4_addr;
+ acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+ if( entry->port_map==0 )
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+ else
+ //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+ /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+ if( entry->port_map )
+ {
+ FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+ acl.ports = entry->port_map;
+ }
+ }
+ else if( entry->group.type == FAL_ADDR_IPV6 )
+ {
+ MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type,
+ entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map);
+
+ acl.rule_type = FAL_ACL_RULE_IP6;
+
+ if(!ip6_addr_is_null(&(entry->group.u.ip6_addr)))
+ {
+ memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr));
+ acl.dest_ip6_mask.ul[0] = 0xffffffff;
+ acl.dest_ip6_mask.ul[1] = 0xffffffff;
+ acl.dest_ip6_mask.ul[2] = 0xffffffff;
+ acl.dest_ip6_mask.ul[3] = 0xffffffff;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ if(!ip6_addr_is_null(&(entry->source.u.ip6_addr)))
+ {
+ memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr));
+ acl.src_ip6_mask.ul[0] = 0xffffffff;
+ acl.src_ip6_mask.ul[1] = 0xffffffff;
+ acl.src_ip6_mask.ul[2] = 0xffffffff;
+ acl.src_ip6_mask.ul[3] = 0xffffffff;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+
+ if( entry->port_map==0 )
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+ else
+ //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+ /* Be careful, _isis_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+ if( entry->port_map )
+ {
+ FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+ acl.ports = entry->port_map;
+ }
+ }
+
+ pos = isis_multicast_acl_total_n(list_id);
+
+ MULTI_DEBUG("In isis_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos);
+ val = ACL_RULE_ADD(0, list_id, pos, rule_nr, &acl);
+
+ multi_acl_bind();
+
+ return val;
+}
+
+
+HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry)
+{
+ int count=0;
+ int i;
+
+ if (number == 0)
+ return 0; //no any ACL rules based the query
+
+ for(i=0; i<number; i++)
+ {
+
+ /*MULTI_DEBUG("2:iterate_multicast_acl_group, index=%d, multi_acl_info[%d].entry=type[%d]-addr[%x], pm=%x, new entry=type[%d]-addr[%x], pm=%x\n",
+ multi_acl_info[i].index,i, multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip6_addr.ul[0], multi_acl_info[i].entry.port_map,
+ entry->group.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/
+
+ if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group)))
+ {
+ memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i]));
+ count++;//return the real number of multi_acl_group[]
+ MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i);
+ }
+ }
+
+ return count;
+}
+
+HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source)
+{
+ int rule_id;
+ int ret = 0;
+#if 0
+ if(source != NULL)
+ {
+ MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n",
+ group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3],
+ source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]);
+
+ MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n",
+ multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0],
+ multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3],
+ multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0],
+ multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]);
+ }
+#endif
+ if(source == NULL)
+ {
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+ (multi_source_is_null(&multi_acl_group[rule_id].entry.source)))
+ {
+ MULTI_DEBUG("Source=0:Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+ ret = rule_id+1; // ensure the return value is the actually number of entry
+ break;
+ }
+ }
+ }
+ else
+ {
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+ (0==memcmp(&multi_acl_group[rule_id].entry.source, source, sizeof(fal_igmp_sg_addr_t))))
+ {
+ MULTI_DEBUG("Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+ ret = rule_id+1; // ensure the return value is the actually number of entry
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+HSL_LOCAL int portmap_null(int index, fal_pbmp_t portmap)
+{
+ int val;
+ if (index<0)
+ aos_printk("portmap_null, index error\n");
+
+ val = multi_acl_group[index].entry.port_map&(~portmap);
+
+ if( 0 == (val&0xff) )
+ return 1;
+ else
+ return 0;
+}
+
+HSL_LOCAL int portmap_valid(fal_igmp_sg_entry_t *g_source, fal_igmp_sg_entry_t *g_star)
+{
+ /* return 0 means the portmap is Not valid
+ return 1 means the protmap is valid
+ */
+ /* MULTI_DEBUG("portmap_valid:g_source portmap=%x, source=%x,group=%x, g_star portmap=%x, source=%x, group=%x\n",
+ g_source->port_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr,
+ g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/
+
+ if(multi_source_is_null(&(g_star->source)))
+ {
+ if((g_source->port_map|g_star->port_map) == g_star->port_map)
+ {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+
+HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap)
+{
+ if(count>=0 && index<count) //new_index must >0; this means there're (G,*) and (G,S)
+ {
+ //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S)
+ if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map)
+ return 1; //delete
+
+
+ //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap.
+ if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map))
+ != (multi_acl_group[count].entry.port_map))
+ return 0;
+
+ return 2; //Normal update
+ }
+ ;
+}
+sw_error_t isis_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ HSL_API_LOCK;
+ int number, count;
+ int new_index=0;
+ int tmp_index=0;
+ sw_error_t rv;
+ int action = MULT_ACTION_SET;
+ fal_igmp_sg_entry_t tmp_entry[1]= {};
+ int i=0;
+
+ (void)isis_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map);
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isis_multicast_acl_query();
+ //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+ count = iterate_multicast_acl_group(number, entry);
+ //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry
+ new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+ MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map);
+ if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S)
+ {
+ MULTI_DEBUG("the new entry is (G,S)\n");
+ if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*)
+ {
+ //return SW_NO_CHANGE; // The new portmap is Not valid
+ MULTI_DEBUG("KKK, modified 1 !!!\n");
+ }
+
+ if(0 == new_index) //new entry, need add
+ {
+#if 0
+ /*The method:
+ 1. predict if the portmap should be modified.
+ 2. add new acl rule with new portmap value.
+ */
+ if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist
+ {
+ /*Here the update should new (G, S) OR orignal (G,*) portmap,
+ be careful, entry's portmap value will be modified, so I use tmp_entry.
+ */
+ memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t));
+ MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index);
+ sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action);
+
+ isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry);
+ return SW_OK;
+ }
+#endif
+ isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry);
+ MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map);
+ return SW_OK;
+ }
+ else
+ {
+ //Here update Just: the old exist entry portmap OR the new entry portmap
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ return SW_OK;
+ }
+ } //end of memcmp
+ else // new entry is (G, *)
+ {
+ if(0 == new_index) //new entry, need add
+ {
+ isis_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry);
+ rv = SW_OK;
+ }
+ else if(new_index > 0) // (G, *) entry exist?
+ {
+ //Update exist (G, *) portmap with new portmap
+ MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index );
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+ rv = SW_OK;
+ }
+
+ if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*)
+ {
+ for(i=count-2; i>=0; i--)
+ {
+ if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+ continue;
+
+ if(0 == portmap_valid(&(multi_acl_group[i].entry), &(multi_acl_group[count-1].entry)))
+ {
+ MULTI_DEBUG("1:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+ i, multi_acl_group[i].entry.port_map, multi_acl_group[count-1].entry.port_map);
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("1:Start update all (G,S),i=%d, gstar portmap=%x\n", i, multi_acl_group[count-1].entry.port_map);
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+ else if(new_index==0&&count>0) //only exist (G,S*) orignally
+ {
+ for(i=count-1; i>=0; i--)
+ {
+ if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+ continue;
+
+ if(0 == portmap_valid(&(multi_acl_group[i].entry), entry))
+ {
+ MULTI_DEBUG("2:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+ i, multi_acl_group[i].entry.port_map, entry->port_map);
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map);
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+ }
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t isis_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ HSL_API_LOCK;
+ a_uint32_t number, count;
+ int new_index=0;
+ sw_error_t rv;
+ int action= MULT_ACTION_CLEAR;
+ int i=0;
+ int pm_type;
+
+ (void)isis_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isis_multicast_acl_query();
+ //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+ count = iterate_multicast_acl_group(number, entry);
+ //new_index-1 is the found entry index in multi_acl_group[]
+ new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+ MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index);
+ if(0 == new_index) //new entry, the user command is wrong
+ {
+ return SW_NO_SUCH;
+ }
+
+ if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S)
+ {
+ if (portmap_null(new_index-1, entry->port_map))
+ {
+ MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n");
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+ return SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n");
+ /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */
+ if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source)))
+ {
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ }
+ else //(G,*) exist
+ {
+ pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map);
+ if(pm_type == 0)
+ return SW_NO_CHANGE;
+ else if(pm_type == 1)
+ {
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+ return SW_NO_MORE;
+ }
+ else
+ {
+ //normal update; consider here...wangson
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ }
+ }
+ }
+ return SW_OK;
+ }
+ else //clear entry is (G,*)
+ {
+ MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map);
+ if (portmap_null(new_index-1, entry->port_map))
+ {
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map);
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+ }
+ MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count);
+#if 0
+ if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+ {
+ //count must >=2
+ for(i=count-2; i>=0; i--)
+ {
+ if(portmap_null(i, entry->port_map))
+ {
+ MULTI_DEBUG("portmap_null, i=%d\n", i);
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+#else
+ if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+ {
+ //count must >=2
+ for(i=count-2; i>=0; i--)
+ {
+ //PortMap of entry (S,G) == (*,G) portmap after clear?
+ if((multi_acl_group[new_index-1].entry.port_map&(~(entry->port_map))) ==
+ multi_acl_group[i].entry.port_map)
+ isis_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ else
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isis_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+#endif
+ }
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+static void
+print_ip4addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip4_addr_t ip4;
+
+ ip4 = *((fal_ip4_addr_t *) buf);
+ aos_printk("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+ }
+ aos_printk("%d", (ip4 & 0xff));
+}
+static void
+print_ip6addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip6_addr_t ip6;
+
+ ip6 = *(fal_ip6_addr_t *) buf;
+ aos_printk("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+ }
+ aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+sw_error_t isis_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+ HSL_API_LOCK;
+ a_uint32_t number;
+ int i;
+
+ (void)isis_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isis_multicast_acl_query();
+
+ for(i=0; i<number; i++)
+ {
+ if(0 == multi_acl_info[i].entry.group.type) //ipv4
+ {
+ aos_printk("\n[%d]:", i);
+ print_ip4addr(" [Group IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip4_addr), sizeof (fal_ip4_addr_t));
+ print_ip4addr(" [Source IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip4_addr), sizeof (fal_ip4_addr_t));
+ aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+ }
+ else if(1 == multi_acl_info[i].entry.group.type) //ipv6
+ {
+ aos_printk("\n[%d]:", i);
+ print_ip6addr(" [Group IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip6_addr), sizeof (fal_ip6_addr_t));
+ print_ip6addr(" [Source IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip6_addr), sizeof (fal_ip6_addr_t));
+ aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+ }
+
+ }
+ aos_printk("\n\nTotal %d multicast ACL rules.\n", number);
+ HSL_API_UNLOCK;
+
+ return SW_OK;
+}
+
+void
+isis_multicast_init(a_uint32_t dev_id)
+{
+ sw_error_t val;
+
+ ACL_STATUS_SET(0, 1);
+
+ val = ACL_LIST_CREATE(0, FAL_ACL_LIST_MULTICAST, FAL_MULTICAST_PRI);
+ if(val !=SW_OK && val != SW_ALREADY_EXIST)
+ aos_printk("Multicast 1 acl list create error, val=%d\n", val);
+
+ val = ACL_LIST_CREATE(0, FAL_ACL_LIST_MULTICAST+1, FAL_MULTICAST_PRI+1);
+ if(val !=SW_OK && val != SW_ALREADY_EXIST)
+ aos_printk("Multicast 2 acl list create error, val=%d\n", val);
+
+}
+
diff --git a/src/hsl/isis/isis_nat.c b/src/hsl/isis/isis_nat.c
new file mode 100644
index 0000000..2800b39
--- /dev/null
+++ b/src/hsl/isis/isis_nat.c
@@ -0,0 +1,2405 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_ip ISIS_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_nat.h"
+#include "isis_reg.h"
+
+#define ISIS_HOST_ENTRY_DATA0_ADDR 0x0e48
+#define ISIS_HOST_ENTRY_DATA1_ADDR 0x0e4c
+#define ISIS_HOST_ENTRY_DATA2_ADDR 0x0e50
+#define ISIS_HOST_ENTRY_DATA3_ADDR 0x0e54
+#define ISIS_HOST_ENTRY_DATA4_ADDR 0x0e58
+
+#define ISIS_NAT_ENTRY_FLUSH 1
+#define ISIS_NAT_ENTRY_ADD 2
+#define ISIS_NAT_ENTRY_DEL 3
+#define ISIS_NAT_ENTRY_NEXT 4
+#define ISIS_NAT_ENTRY_SEARCH 5
+
+#define ISIS_ENTRY_NAPT 0
+#define ISIS_ENTRY_NAT 2
+#define ISIS_ENTRY_ARP 3
+
+#define ISIS_PUB_ADDR_NUM 16
+#define ISIS_PUB_ADDR_TBL0_ADDR 0x5aa00
+#define ISIS_PUB_ADDR_TBL1_ADDR 0x5aa04
+#define ISIS_PUB_ADDR_EDIT0_ADDR 0x02100
+#define ISIS_PUB_ADDR_EDIT1_ADDR 0x02104
+#define ISIS_PUB_ADDR_OFFLOAD_ADDR 0x2a000
+#define ISIS_PUB_ADDR_VALID_ADDR 0x2a040
+
+#define ISIS_NAT_ENTRY_NUM 32
+#define ISIS_NAPT_ENTRY_NUM 1024
+
+#define ISIS_NAT_COUTER_ADDR 0x2b000
+
+#define ISIS_NAT_PORT_NUM 255
+
+static a_uint32_t isis_nat_snap[SW_MAX_NR_DEV] = { 0 };
+
+static sw_error_t
+_isis_nat_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static sw_error_t
+_isis_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr,
+ a_uint32_t * hw_addr)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8);
+ }
+ else
+ {
+ *hw_addr = sw_addr & 0xfff;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr,
+ fal_ip4_addr_t * sw_addr)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8)
+ | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16);
+ }
+ else
+ {
+ *sw_addr = (addr << 12) | (hw_addr & 0xfff);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+ a_uint32_t counter[4])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ addr = ISIS_NAT_COUTER_ADDR + (cnt_id << 4);
+ for (i = 0; i < 4; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(counter[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr += 4;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+ a_uint32_t busy = 1, i = 0x100, entry;
+ sw_error_t rv;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+ aos_udelay(500);
+ }
+
+ if (i == 0)
+ {
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_SEL, entry_type, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, op, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 0x100;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_BUSY, busy, entry);
+ aos_udelay(500);
+#if 1
+ if(ISIS_NAT_ENTRY_SEARCH == op && busy) break;
+#endif
+ }
+
+ if (i == 0)
+ {
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ /* hardware requirement, we should delay... */
+ if ((ISIS_NAT_ENTRY_FLUSH == op) && (ISIS_ENTRY_NAPT == entry_type))
+ {
+ aos_mdelay(10);
+ }
+
+ /* hardware requirement, we should read again... */
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, busy, entry);
+ if (!busy)
+ {
+ if (ISIS_NAT_ENTRY_NEXT == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if (ISIS_NAT_ENTRY_SEARCH == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg[0] = entry->trans_addr;
+
+ if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]);
+ if (ISIS_NAT_PORT_NUM < entry->port_range)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, PORT_EN, 0, reg[2]);
+ }
+
+ rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]);
+
+ if (FAL_MAC_FRWRD == entry->action)
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]);
+ }
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags)
+ {
+ data = 3;
+ }
+ else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags))
+ {
+ data = 2;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRO_TYP, data, reg[2]);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ENTRY_VALID, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[4];
+
+ entry->trans_addr = reg[0];
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, PORT_EN, data, reg[2]);
+ if (data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]);
+ entry->port_range = data;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]);
+ entry->port_num = data;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+ entry->src_addr = data;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]);
+ data = (entry->src_addr & 0xff) | (data << 8);
+
+ rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+
+ rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->ingress_packet = cnt[0];
+ entry->ingress_byte = cnt[1];
+ entry->egress_packet = cnt[2];
+ entry->egress_byte = cnt[3];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRO_TYP, data, reg[2]);
+ if (3 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY;
+ }
+ else if (2 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (1 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (0 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]);
+ entry->slct_idx = data;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry,
+ a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ reg[0] = entry->dst_addr;
+
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+ rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+
+ if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags))
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+ if (FAL_MAC_FRWRD == entry->action)
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]);
+ }
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+ }
+
+ data = 2;
+ if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+ {
+ data = 1;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags)
+ {
+ data = 3;
+ }
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+ fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[4];
+
+ entry->dst_addr = reg[0];
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+ rv = _isis_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+ SW_RTN_ON_ERROR(rv);
+
+ entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+ rv = _isis_nat_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->ingress_packet = cnt[0];
+ entry->ingress_byte = cnt[1];
+ entry->egress_packet = cnt[2];
+ entry->egress_byte = cnt[3];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+ if (0 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ }
+ else if (1 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (3 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < 5; i++)
+ {
+ addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < 5; i++)
+ {
+ addr = ISIS_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < ISIS_NAT_ENTRY_NUM; i++)
+ {
+ if (!(isis_nat_snap[dev_id] & (0x1 << i)))
+ {
+ break;
+ }
+ }
+
+ if (ISIS_NAT_ENTRY_NUM == i)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ entry->entry_id = i;
+
+ rv = _isis_nat_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ isis_nat_snap[dev_id] |= (0x1 << i);
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, ENTRY_FUNC, ISIS_NAT_ENTRY_DEL, reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ isis_nat_snap[dev_id] &= (~(0x1 << entry->entry_id));
+ }
+ else
+ {
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ isis_nat_snap[dev_id] = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (!(isis_nat_snap[dev_id] & (0x1 << entry->entry_id)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_hw_to_sw(dev_id, reg, entry);
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ a_uint32_t i, idx, reg[5] = { 0 };
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISIS_NAT_ENTRY_NUM - 1) == nat_entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = nat_entry->entry_id + 1;
+ }
+ }
+
+ for (i = idx; i < ISIS_NAT_ENTRY_NUM; i++)
+ {
+ if (isis_nat_snap[dev_id] & (0x1 << i))
+ {
+ break;
+ }
+ }
+
+ if (ISIS_NAT_ENTRY_NUM == i)
+ {
+ return SW_NO_MORE;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, i, reg[4]);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+
+ rv = _isis_nat_hw_to_sw(dev_id, reg, nat_entry);
+ SW_RTN_ON_ERROR(rv);
+
+ nat_entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(isis_nat_snap[dev_id] & (0x1 << entry_id)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry_id, reg[4]);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* needn't set TBL_IDX, keep hardware register value */
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ /* needn't set TBL_IDX, keep hardware register value */
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN & del_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+ {
+ rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+ }
+ else
+ {
+ if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]);
+ rv = _isis_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, entry->status, reg[3]);
+ }
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH);
+ return rv;
+ }
+}
+
+static sw_error_t
+_isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t found, age, reg[5] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#if 0
+ if (FAL_NAT_ENTRY_ID_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+#else
+ rv = _isis_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, found, reg[4]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, AGE_FLAG, age, reg[3]);
+ if (found && age)
+ {
+ found = 1;
+ }
+ else
+ {
+ found = 0;
+ }
+
+ rv = _isis_napt_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!found)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ a_uint32_t data, idx, reg[5] = { 0 };
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+ {
+ idx = ISIS_NAPT_ENTRY_NUM - 1;
+ }
+ else
+ {
+ if ((ISIS_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = napt_entry->entry_id;
+ }
+ }
+
+ if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_PIP, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_SIP, 1, reg[4]);
+ rv = _isis_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR, data, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, SPEC_STATUS, 1, reg[4]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, AGE_FLAG, napt_entry->status, reg[3]);
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, idx, reg[4]);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+ rv = _isis_napt_hw_to_sw(dev_id, reg, napt_entry);
+ SW_RTN_ON_ERROR(rv);
+
+#if 0
+ a_uint32_t temp=0, complete=0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&temp),
+ sizeof (a_uint32_t));
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_STAUS, complete, temp);
+
+ if (!complete)
+ {
+ return SW_NO_MORE;
+ }
+#endif
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, napt_entry->entry_id, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[5] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x3ff;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_NEXT);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ rv = _isis_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, TBL_IDX, tbl_idx, reg[4]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ reg[4] = 0x0;
+ rv = _isis_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAPT_FULL_CONE == mode)
+ {
+ data = 0;
+ }
+ else if (FAL_NAPT_STRICT_CONE == mode)
+ {
+ data = 1;
+ }
+ else if ((FAL_NAPT_PORT_STRICT == mode)
+ || (FAL_NAPT_SYNMETRIC == mode))
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *mode = FAL_NAPT_FULL_CONE;
+ }
+ else if (1 == data)
+ {
+ *mode = FAL_NAPT_STRICT_CONE;
+ }
+ else
+ {
+ *mode = FAL_NAPT_PORT_STRICT;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if ((FAL_NAT_HASH_KEY_PORT & mode)
+ && (FAL_NAT_HASH_KEY_IPADDR & mode))
+ {
+ data = 2;
+ }
+ else if (FAL_NAT_HASH_KEY_PORT & mode)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_HASH_KEY_IPADDR & mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *mode = 0;
+ if (0 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_PORT;
+ }
+ else if (1 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_IPADDR;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_PORT;
+ *mode |= FAL_NAT_HASH_KEY_IPADDR;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+ }
+ else
+ {
+ data = (addr >> 12) & 0xfffff;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, OFFLOAD_PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+ a_uint32_t data, tmp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (tmp)
+ {
+ *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+ }
+ else
+ {
+ *addr = (data & 0xfffff) << 12;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+ }
+ else
+ {
+ data = (addr >> 12) & 0xfffff;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+ a_uint32_t data, tmp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (tmp)
+ {
+ *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+ }
+ else
+ {
+ *addr = (data & 0xfffff) << 12;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == map_en)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == map_en)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *map_en = A_TRUE;
+ }
+ else
+ {
+ *map_en = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry,
+ a_uint32_t op, a_uint32_t * empty)
+{
+ a_uint32_t index, addr, data, tbl[2] = { 0 };
+ sw_error_t rv;
+
+ *empty = ISIS_PUB_ADDR_NUM;
+ for (index = 0; index < ISIS_PUB_ADDR_NUM; index++)
+ {
+ addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+ if (data)
+ {
+ addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp
+ ((void *) &(entry->pub_addr), (void *) &(tbl[0]),
+ sizeof (fal_ip4_addr_t)))
+ {
+ if (ISIS_NAT_ENTRY_DEL == op)
+ {
+ addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+ tbl[1] = 0;
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ *empty = index;
+ return rv;
+ }
+ else if (ISIS_NAT_ENTRY_ADD == op)
+ {
+ entry->entry_id = index;
+ return SW_ALREADY_EXIST;
+ }
+ }
+ }
+ else
+ {
+ *empty = index;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, empty, addr, data, tbl[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl[0] = entry->pub_addr;
+ tbl[1] = 1;
+
+ rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_ADD, &empty);
+ if (SW_ALREADY_EXIST == rv)
+ {
+ return rv;
+ }
+
+ if (ISIS_PUB_ADDR_NUM == empty)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < 1; i++)
+ {
+ addr = ISIS_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ addr = ISIS_PUB_ADDR_OFFLOAD_ADDR + (empty << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISIS_PUB_ADDR_VALID_ADDR;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data |= (0x1 << empty);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 2; i++)
+ {
+ addr = ISIS_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ entry->entry_id = empty;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty, addr, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_pub_addr_commit(dev_id, entry, ISIS_NAT_ENTRY_DEL, &empty);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISIS_PUB_ADDR_VALID_ADDR;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x1 << empty));
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr, idx, index, tbl[2];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISIS_PUB_ADDR_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id + 1;
+ }
+ }
+
+ for (index = idx; index < ISIS_PUB_ADDR_NUM; index++)
+ {
+ addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+ if (data)
+ {
+ break;
+ }
+ }
+
+ if (ISIS_PUB_ADDR_NUM == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ addr = ISIS_PUB_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ entry->entry_id = index;
+ entry->pub_addr = tbl[0];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_nat_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t index, addr, data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ isis_nat_snap[dev_id] = 0;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAT, ISIS_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY4, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_nat_entry_commit(dev_id, ISIS_ENTRY_NAPT, ISIS_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ for (index = 0; index < ISIS_PUB_ADDR_NUM; index++)
+ {
+ addr = ISIS_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ * @details Comments:
+ Before NAT entry added ip4 private base address must be set
+ at first.
+ In parameter nat_entry entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_add(dev_id, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_del(dev_id, del_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_get(dev_id, get_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_next(dev_id, next_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ * @details Comments:
+ Before NAPT entry added related ip4 private base address must be set
+ at first.
+ In parameter napt_entry related entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+
+HSL_LOCAL sw_error_t
+isis_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_add(dev_id, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_del(dev_id, del_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_get(dev_id, get_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_next(dev_id, next_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_hash_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_hash_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_napt_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @details Comments:
+ Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_prv_base_addr_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_prv_base_addr_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @details Comments:
+ Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_psr_prv_base_addr_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_psr_prv_base_addr_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ * @details Comments:
+ If map_en equal true means bits31-20 bits15-8 are base address
+ else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_prv_addr_mode_set(dev_id, map_en);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_prv_addr_mode_get(dev_id, map_en);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ * @details Comments:
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_pub_addr_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_pub_addr_del(dev_id, del_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_pub_addr_next(dev_id, next_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_unk_session_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nat_unk_session_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_nat_init(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = isis_nat_reset(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->nat_add = isis_nat_add;
+ p_api->nat_del = isis_nat_del;
+ p_api->nat_get = isis_nat_get;
+ p_api->nat_next = isis_nat_next;
+ p_api->nat_counter_bind = isis_nat_counter_bind;
+ p_api->napt_add = isis_napt_add;
+ p_api->napt_del = isis_napt_del;
+ p_api->napt_get = isis_napt_get;
+ p_api->napt_next = isis_napt_next;
+ p_api->napt_counter_bind = isis_napt_counter_bind;
+ p_api->nat_status_set = isis_nat_status_set;
+ p_api->nat_status_get = isis_nat_status_get;
+ p_api->nat_hash_mode_set = isis_nat_hash_mode_set;
+ p_api->nat_hash_mode_get = isis_nat_hash_mode_get;
+ p_api->napt_status_set = isis_napt_status_set;
+ p_api->napt_status_get = isis_napt_status_get;
+ p_api->napt_mode_set = isis_napt_mode_set;
+ p_api->napt_mode_get = isis_napt_mode_get;
+ p_api->nat_prv_base_addr_set = isis_nat_prv_base_addr_set;
+ p_api->nat_prv_base_addr_get = isis_nat_prv_base_addr_get;
+ p_api->nat_prv_addr_mode_set = isis_nat_prv_addr_mode_set;
+ p_api->nat_prv_addr_mode_get = isis_nat_prv_addr_mode_get;
+ p_api->nat_pub_addr_add = isis_nat_pub_addr_add;
+ p_api->nat_pub_addr_del = isis_nat_pub_addr_del;
+ p_api->nat_pub_addr_next = isis_nat_pub_addr_next;
+ p_api->nat_unk_session_cmd_set = isis_nat_unk_session_cmd_set;
+ p_api->nat_unk_session_cmd_get = isis_nat_unk_session_cmd_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isis/isis_port_ctrl.c b/src/hsl/isis/isis_port_ctrl.c
new file mode 100644
index 0000000..d4ba147
--- /dev/null
+++ b/src/hsl/isis/isis_port_ctrl.c
@@ -0,0 +1,2154 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_port_ctrl ISIS_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_port_ctrl.h"
+#include "isis_reg.h"
+#include "f1_phy.h"
+
+static a_bool_t
+_isis_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+ if ((0 == port_id) || (6 == port_id))
+ {
+ return A_FALSE;
+ }
+ else
+ {
+ return A_TRUE;
+ }
+}
+
+static sw_error_t
+_isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id, reg_save, reg_val, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ if (FAL_HALF_DUPLEX == duplex)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+ reg_save = reg_val;
+ }
+ else
+ {
+ /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ reg_save = reg_val;
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_duplex(dev_id, phy_id, duplex);
+ SW_RTN_ON_ERROR(rv);
+
+ /* If MAC not in sync with PHY mode, the behavior is undefine.
+ You must be careful... */
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+ if (!force)
+ {
+ if (FAL_HALF_DUPLEX == duplex)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save);
+ }
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg);
+ if (field)
+ {
+ *pduplex = FAL_FULL_DUPLEX;
+ }
+ else
+ {
+ *pduplex = FAL_HALF_DUPLEX;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id, reg_save, reg_val, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_SPEED_1000 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+ }
+ reg_save = reg_val;
+
+ }
+ else
+ {
+ /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ reg_save = reg_val;
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_speed(dev_id, phy_id, speed);
+ SW_RTN_ON_ERROR(rv);
+
+ /* If MAC not in sync with PHY mode, the behavior is undefine.
+ You must be careful... */
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+ if (!force)
+ {
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save);
+ }
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg);
+ if (0 == field)
+ {
+ *pspeed = FAL_SPEED_10;
+ }
+ else if (1 == field)
+ {
+ *pspeed = FAL_SPEED_100;
+ }
+ else if (2 == field)
+ {
+ *pspeed = FAL_SPEED_1000;
+ }
+ else
+ {
+ *pspeed = FAL_SPEED_BUTT;
+ rv = SW_READ_ERROR;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ a_uint32_t phy_id;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f1_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f1_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t rx, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+ if (1 == rx)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ /* for those ports without PHY, it can't sync flow control status */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ return SW_DISABLE;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (0 == force)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_NO_HEADER_EN == mode)
+ {
+ val = 0;
+ }
+ else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+ {
+ val = 1;
+ }
+ else if (FAL_ALL_TYPE_FRAME_EN == mode)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *mode = FAL_ONLY_MANAGE_FRAME_EN;
+ }
+ else if (2 == val)
+ {
+ *mode = FAL_ALL_TYPE_FRAME_EN;
+ }
+ else
+ {
+ *mode = FAL_NO_HEADER_EN;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_NO_HEADER_EN == mode)
+ {
+ val = 0;
+ }
+ else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+ {
+ val = 1;
+ }
+ else if (FAL_ALL_TYPE_FRAME_EN == mode)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *mode = FAL_ONLY_MANAGE_FRAME_EN;
+ }
+ else if (2 == val)
+ {
+ *mode = FAL_ALL_TYPE_FRAME_EN;
+ }
+ else
+ {
+ *mode = FAL_NO_HEADER_EN;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ a_uint32_t reg;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (0xffff < type)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg);
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg);
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ a_uint32_t data, reg;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg);
+ *enable = A_TRUE;
+ *type = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *type = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, force, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg);
+ if (force)
+ {
+ /* link isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, force, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg);
+ if (force)
+ {
+ /* link isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, reg, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, reg, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ /* for those ports without PHY, it can't sync link status */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ return SW_DISABLE;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device supposed always link up */
+ if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
+ {
+ *status = A_TRUE;
+ }
+ else
+ {
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == f1_phy_get_link_status(dev_id, phy_id))
+ {
+ *status = A_TRUE;
+ }
+ else
+ {
+ *status = A_FALSE;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control(rx/tx/bp) status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_flowctrl_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_flowctrl_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_rxhdr_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_rxhdr_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_txhdr_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_txhdr_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_header_type_set(dev_id, enable, type);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_header_type_get(dev_id, enable, type);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_txmac_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_txmac_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_rxmac_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_rxmac_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_txfc_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_txfc_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_rxfc_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_rxfc_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_bp_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_bp_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_link_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_link_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_link_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isis_port_mac_loopback_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_mac_loopback_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = isis_port_duplex_get;
+ p_api->port_duplex_set = isis_port_duplex_set;
+ p_api->port_speed_get = isis_port_speed_get;
+ p_api->port_speed_set = isis_port_speed_set;
+ p_api->port_autoneg_status_get = isis_port_autoneg_status_get;
+ p_api->port_autoneg_enable = isis_port_autoneg_enable;
+ p_api->port_autoneg_restart = isis_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = isis_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = isis_port_autoneg_adv_set;
+ p_api->port_flowctrl_set = isis_port_flowctrl_set;
+ p_api->port_flowctrl_get = isis_port_flowctrl_get;
+ p_api->port_flowctrl_forcemode_set = isis_port_flowctrl_forcemode_set;
+ p_api->port_flowctrl_forcemode_get = isis_port_flowctrl_forcemode_get;
+ p_api->port_powersave_set = isis_port_powersave_set;
+ p_api->port_powersave_get = isis_port_powersave_get;
+ p_api->port_hibernate_set = isis_port_hibernate_set;
+ p_api->port_hibernate_get = isis_port_hibernate_get;
+ p_api->port_cdt = isis_port_cdt;
+ p_api->port_rxhdr_mode_set = isis_port_rxhdr_mode_set;
+ p_api->port_rxhdr_mode_get = isis_port_rxhdr_mode_get;
+ p_api->port_txhdr_mode_set = isis_port_txhdr_mode_set;
+ p_api->port_txhdr_mode_get = isis_port_txhdr_mode_get;
+ p_api->header_type_set = isis_header_type_set;
+ p_api->header_type_get = isis_header_type_get;
+ p_api->port_txmac_status_set = isis_port_txmac_status_set;
+ p_api->port_txmac_status_get = isis_port_txmac_status_get;
+ p_api->port_rxmac_status_set = isis_port_rxmac_status_set;
+ p_api->port_rxmac_status_get = isis_port_rxmac_status_get;
+ p_api->port_txfc_status_set = isis_port_txfc_status_set;
+ p_api->port_txfc_status_get = isis_port_txfc_status_get;
+ p_api->port_rxfc_status_set = isis_port_rxfc_status_set;
+ p_api->port_rxfc_status_get = isis_port_rxfc_status_get;
+ p_api->port_bp_status_set = isis_port_bp_status_set;
+ p_api->port_bp_status_get = isis_port_bp_status_get;
+ p_api->port_link_forcemode_set = isis_port_link_forcemode_set;
+ p_api->port_link_forcemode_get = isis_port_link_forcemode_get;
+ p_api->port_link_status_get = isis_port_link_status_get;
+ p_api->port_mac_loopback_set = isis_port_mac_loopback_set;
+ p_api->port_mac_loopback_get = isis_port_mac_loopback_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_portvlan.c b/src/hsl/isis/isis_portvlan.c
new file mode 100644
index 0000000..ef334a0
--- /dev/null
+++ b/src/hsl/isis/isis_portvlan.c
@@ -0,0 +1,2104 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_port_vlan ISIS_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_portvlan.h"
+#include "isis_reg.h"
+
+#define MAX_VLAN_ID 4095
+#define ISIS_MAX_VLAN_TRANS 64
+#define ISIS_VLAN_TRANS_ADDR 0x5ac00
+
+
+static sw_error_t
+_isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (port_id % 2)
+ {
+ reg &= 0xffff;
+ reg |= ((data & 0xfff) << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= (data & 0xfff);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_1Q_DISABLE == port_1qmode)
+ {
+ data = 1;
+ }
+ else
+ {
+ data = 0;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t data, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_EG_MODE_BUTT <= port_egvlanmode)
+ || (FAL_EG_HYBRID == port_egvlanmode))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x3 << (port_id << 2)));
+ data |= (regval[port_egvlanmode] << (port_id << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED, FAL_EG_UNTOUCHED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = tpid;
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tpid = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_INVLAN_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val[mode]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+ FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(mode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (regval >= 3)
+ {
+ return SW_FAIL;
+ }
+ *mode = retval[regval & 0x3];
+
+ return rv;
+}
+
+static sw_error_t
+_isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (vid > MAX_VLAN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (vid > MAX_VLAN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+ {
+ p = 0;
+ c = 0;
+ }
+ else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+ {
+ p = 1;
+ c = 1;
+ }
+ else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+ {
+ p = 1;
+ c = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg);
+ SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg);
+ SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg);
+
+ if (p)
+ {
+ if (c)
+ {
+ *mode = FAL_VLAN_PROPAGATION_CLONE;
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_REPLACE;
+ }
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_DISABLE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx,
+ fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, dir, table[2];
+
+ *pbmp = 0;
+ aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+
+ addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3);
+ /* get vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ dir = 0x3 & (table[1] >> 4);
+ if (!dir)
+ {
+ return SW_EMPTY;
+ }
+
+ entry->o_vid = table[0] & 0xfff;
+ *pbmp = (table[1] >> 6) & 0x7f;
+
+ if (3 == dir)
+ {
+ entry->bi_dir = A_TRUE;
+ entry->forward_dir = A_TRUE;
+ entry->reverse_dir = A_TRUE;
+ }
+ else if (1 == dir)
+ {
+ entry->bi_dir = A_FALSE;
+ entry->forward_dir = A_TRUE;
+ entry->reverse_dir = A_FALSE;
+ }
+ else
+ {
+ entry->bi_dir = A_FALSE;
+ entry->forward_dir = A_FALSE;
+ entry->reverse_dir = A_TRUE;
+ }
+
+ entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL;
+ entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL;
+ entry->s_vid_enable = (table[1] >> 14) & 0x1UL;
+ entry->c_vid_enable = (table[1] >> 15) & 0x1UL;
+
+ if (A_TRUE == entry->s_vid_enable)
+ {
+ entry->s_vid = (table[0] >> 12) & 0xfff;
+ }
+
+ if (A_TRUE == entry->c_vid_enable)
+ {
+ entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp,
+ fal_vlan_trans_entry_t entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, table[2] = { 0 };
+
+ addr = ISIS_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+ if (0 != pbmp)
+ {
+ table[0] = entry.o_vid & 0xfff;
+ table[0] |= ((entry.s_vid & 0xfff) << 12);
+ table[0] |= ((entry.c_vid & 0xff) << 24);
+ table[1] = (entry.c_vid >> 8) & 0xf;
+
+ if (A_TRUE == entry.bi_dir)
+ {
+ table[1] |= (0x3 << 4);
+ }
+
+ if (A_TRUE == entry.forward_dir)
+ {
+ table[1] |= (0x1 << 4);
+ }
+
+ if (A_TRUE == entry.reverse_dir)
+ {
+ table[1] |= (0x1 << 5);
+ }
+
+ table[1] |= (pbmp << 6);
+ table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13);
+ table[1] |= ((0x1UL & entry.s_vid_enable) << 14);
+ table[1] |= ((0x1UL & entry.c_vid_enable) << 15);
+ table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16);
+ }
+
+ /* set vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry,
+ fal_vlan_trans_entry_t * local)
+{
+ aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t));
+
+ if ((A_TRUE == local->bi_dir)
+ || ((A_TRUE == local->forward_dir)
+ && (A_TRUE == local->reverse_dir)))
+ {
+ local->bi_dir = A_TRUE;
+ local->forward_dir = A_TRUE;
+ local->reverse_dir = A_TRUE;
+ }
+
+ if (A_FALSE == local->s_vid_enable)
+ {
+ local->s_vid = 0;
+ }
+
+ if (A_FALSE == local->c_vid_enable)
+ {
+ local->c_vid = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ entry_idx = idx;
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ return SW_ALREADY_EXIST;
+ }
+ entry_idx = idx;
+ break;
+ }
+ else
+ {
+ t_pbmp = 0;
+ }
+ }
+
+ if (ISIS_MAX_VLAN_TRANS != entry_idx)
+ {
+ t_pbmp |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = ISIS_MAX_VLAN_TRANS;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ entry_idx = idx;
+ break;
+ }
+ }
+ }
+
+ if (ISIS_MAX_VLAN_TRANS != entry_idx)
+ {
+ t_pbmp &= (~(0x1 << port_id));
+ }
+ else
+ {
+ return SW_NOT_FOUND;
+ }
+
+ return _isis_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISIS_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isis_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ return SW_OK;
+ }
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator,
+ fal_vlan_trans_entry_t * entry)
+{
+ a_uint32_t index;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_t;
+ fal_pbmp_t pbmp_t;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (ISIS_MAX_VLAN_TRANS < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < ISIS_MAX_VLAN_TRANS; index++)
+ {
+ rv = _isis_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+
+ if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+ {
+ aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t));
+ break;
+ }
+ }
+
+ if (ISIS_MAX_VLAN_TRANS == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_QINQ_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_STAG_MODE == mode)
+ {
+ stag = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (stag)
+ {
+ *mode = FAL_QINQ_STAG_MODE;
+ }
+ else
+ {
+ *mode = FAL_QINQ_CTAG_MODE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_CORE_PORT == role)
+ {
+ core = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (core)
+ {
+ *role = FAL_QINQ_CORE_PORT;
+ }
+ else
+ {
+ *role = FAL_QINQ_EDGE_PORT;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id,
+ EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+
+}
+
+static sw_error_t
+_isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id,
+ EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_force_default_vid_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_force_default_vid_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_force_portvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_force_portvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nestvlan_tpid_set(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_nestvlan_tpid_get(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_invlan_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_invlan_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_tls_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_tls_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_pri_propagation_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_pri_propagation_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_default_svid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_default_svid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_default_cvid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_default_cvid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_propagation_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_propagation_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_trans_add(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_trans_del(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_trans_get(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qinq_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qinq_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_qinq_role_set(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_qinq_role_get(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isis_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv =_isis_port_route_defv_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_portvlan_init(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_init;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t));
+
+ for (i = 0; i < ISIS_MAX_VLAN_TRANS; i++)
+ {
+ rv = _isis_vlan_trans_write(dev_id, i, 0, entry_init);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = isis_port_1qmode_get;
+ p_api->port_1qmode_set = isis_port_1qmode_set;
+ p_api->port_egvlanmode_get = isis_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = isis_port_egvlanmode_set;
+ p_api->portvlan_member_add = isis_portvlan_member_add;
+ p_api->portvlan_member_del = isis_portvlan_member_del;
+ p_api->portvlan_member_update = isis_portvlan_member_update;
+ p_api->portvlan_member_get = isis_portvlan_member_get;
+ p_api->port_force_default_vid_set = isis_port_force_default_vid_set;
+ p_api->port_force_default_vid_get = isis_port_force_default_vid_get;
+ p_api->port_force_portvlan_set = isis_port_force_portvlan_set;
+ p_api->port_force_portvlan_get = isis_port_force_portvlan_get;
+ p_api->nestvlan_tpid_set = isis_nestvlan_tpid_set;
+ p_api->nestvlan_tpid_get = isis_nestvlan_tpid_get;
+ p_api->port_invlan_mode_set = isis_port_invlan_mode_set;
+ p_api->port_invlan_mode_get = isis_port_invlan_mode_get;
+ p_api->port_tls_set = isis_port_tls_set;
+ p_api->port_tls_get = isis_port_tls_get;
+ p_api->port_pri_propagation_set = isis_port_pri_propagation_set;
+ p_api->port_pri_propagation_get = isis_port_pri_propagation_get;
+ p_api->port_default_svid_set = isis_port_default_svid_set;
+ p_api->port_default_svid_get = isis_port_default_svid_get;
+ p_api->port_default_cvid_set = isis_port_default_cvid_set;
+ p_api->port_default_cvid_get = isis_port_default_cvid_get;
+ p_api->port_vlan_propagation_set = isis_port_vlan_propagation_set;
+ p_api->port_vlan_propagation_get = isis_port_vlan_propagation_get;
+ p_api->port_vlan_trans_add = isis_port_vlan_trans_add;
+ p_api->port_vlan_trans_del = isis_port_vlan_trans_del;
+ p_api->port_vlan_trans_get = isis_port_vlan_trans_get;
+ p_api->qinq_mode_set = isis_qinq_mode_set;
+ p_api->qinq_mode_get = isis_qinq_mode_get;
+ p_api->port_qinq_role_set = isis_port_qinq_role_set;
+ p_api->port_qinq_role_get = isis_port_qinq_role_get;
+ p_api->port_vlan_trans_iterate = isis_port_vlan_trans_iterate;
+ p_api->port_mac_vlan_xlt_set = isis_port_mac_vlan_xlt_set;
+ p_api->port_mac_vlan_xlt_get = isis_port_mac_vlan_xlt_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isis/isis_qos.c b/src/hsl/isis/isis_qos.c
new file mode 100644
index 0000000..548a3bf
--- /dev/null
+++ b/src/hsl/isis/isis_qos.c
@@ -0,0 +1,1240 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_qos ISIS_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_qos.h"
+#include "isis_reg.h"
+
+#define ISIS_QOS_QUEUE_TX_BUFFER_MAX 60
+#define ISIS_QOS_PORT_TX_BUFFER_MAX 252
+#define ISIS_QOS_PORT_RX_BUFFER_MAX 60
+
+//#define ISIS_MIN_QOS_MODE_PRI 0
+#define ISIS_MAX_QOS_MODE_PRI 3
+#define ISIS_MAX_PRI 7
+#define ISIS_MAX_QUEUE 3
+#define ISIS_MAX_EH_QUEUE 5
+
+static sw_error_t
+_isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+ if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+ {
+ if (ISIS_MAX_EH_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+ else
+ {
+ if (ISIS_MAX_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t data, val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_QOS_QUEUE_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ val = *number / 4;
+ *number = val << 2;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0xf << (queue_id << 2)));
+ data |= (val << (queue_id << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t data, val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (data >> (queue_id << 2)) & 0xf;
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_QOS_PORT_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_QOS_PORT_RX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAX_QOS_MODE_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ a_uint32_t entry, f_val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *pri = f_val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t reg, val, w[6] = { 0 };
+ a_int32_t i, _index;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SCH_SP_MODE == mode)
+ {
+ val = 0;
+ _index = -1;
+ }
+ else if (FAL_SCH_WRR_MODE == mode)
+ {
+ val = 3;
+ _index = 5;
+ }
+ else if (FAL_SCH_MIX_MODE == mode)
+ {
+ val = 1;
+ _index = 4;
+ }
+ else if (FAL_SCH_MIX_PLUS_MODE == mode)
+ {
+ val = 2;
+ _index = 3;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (i = _index; i >= 0; i--)
+ {
+ if (weight[i] > 0x1f)
+ {
+ return SW_BAD_PARAM;
+ }
+ w[i] = weight[i];
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t val, sch, w[6], i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+ if (0 == sch)
+ {
+ *mode = FAL_SCH_SP_MODE;
+ }
+ else if (1 == sch)
+ {
+ *mode = FAL_SCH_MIX_MODE;
+ }
+ else if (2 == sch)
+ {
+ *mode = FAL_SCH_MIX_PLUS_MODE;
+ }
+ else
+ {
+ *mode = FAL_SCH_WRR_MODE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ weight[i] = w[i];
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAX_PRI < spri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = spri;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *spri = val & 0x7;
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISIS_MAX_PRI < cpri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = cpri;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *cpri = val & 0x7;
+ return rv;
+}
+
+static sw_error_t
+_isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t addr, data;
+ a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+ rv = _isis_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = base[port_id] + ((queue_id / 4) << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0xff << ((queue_id % 4) << 3)));
+ data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3));
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t addr, data;
+ a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+ rv = _isis_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = base[port_id] + ((queue_id / 4) << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf;
+ *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7;
+ return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ If enable tx buffer on one port that means this port will have fixed
+ number buffers when transmitting packets. Otherwise they will
+ share the whole buffers with other ports in device.
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is 4, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for queue is 4 to 60.
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ * @details Comments:
+ The step of buffer number in Shiva is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_mode_set(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_mode_get(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ If the priority of a mode is more small then the priority is more high.
+ Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ * @details Comments:
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+ the max value supported by ISIS is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_default_spri_set(dev_id, port_id, spri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_default_spri_get(dev_id, port_id, spri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_default_cpri_set(dev_id, port_id, cpri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_port_default_cpri_get(dev_id, port_id, cpri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_qos_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->qos_queue_tx_buf_status_set = isis_qos_queue_tx_buf_status_set;
+ p_api->qos_queue_tx_buf_status_get = isis_qos_queue_tx_buf_status_get;
+ p_api->qos_port_tx_buf_status_set = isis_qos_port_tx_buf_status_set;
+ p_api->qos_port_tx_buf_status_get = isis_qos_port_tx_buf_status_get;
+ p_api->qos_queue_tx_buf_nr_set = isis_qos_queue_tx_buf_nr_set;
+ p_api->qos_queue_tx_buf_nr_get = isis_qos_queue_tx_buf_nr_get;
+ p_api->qos_port_tx_buf_nr_set = isis_qos_port_tx_buf_nr_set;
+ p_api->qos_port_tx_buf_nr_get = isis_qos_port_tx_buf_nr_get;
+ p_api->qos_port_rx_buf_nr_set = isis_qos_port_rx_buf_nr_set;
+ p_api->qos_port_rx_buf_nr_get = isis_qos_port_rx_buf_nr_get;
+ p_api->qos_port_mode_set = isis_qos_port_mode_set;
+ p_api->qos_port_mode_get = isis_qos_port_mode_get;
+ p_api->qos_port_mode_pri_set = isis_qos_port_mode_pri_set;
+ p_api->qos_port_mode_pri_get = isis_qos_port_mode_pri_get;
+ p_api->qos_port_sch_mode_set = isis_qos_port_sch_mode_set;
+ p_api->qos_port_sch_mode_get = isis_qos_port_sch_mode_get;
+ p_api->qos_port_default_spri_set = isis_qos_port_default_spri_set;
+ p_api->qos_port_default_spri_get = isis_qos_port_default_spri_get;
+ p_api->qos_port_default_cpri_set = isis_qos_port_default_cpri_set;
+ p_api->qos_port_default_cpri_get = isis_qos_port_default_cpri_get;
+ p_api->qos_queue_remark_table_set = isis_qos_queue_remark_table_set;
+ p_api->qos_queue_remark_table_get = isis_qos_queue_remark_table_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isis/isis_rate.c b/src/hsl/isis/isis_rate.c
new file mode 100644
index 0000000..e9a3ede
--- /dev/null
+++ b/src/hsl/isis/isis_rate.c
@@ -0,0 +1,1540 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_rate ISIS_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_rate.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_POLICER_ID 31
+#define ISIS_MAX_QUEUE 3
+#define ISIS_MAX_EH_QUEUE 5
+
+#define ACL_POLICER_CNT_SEL_ADDR 0x09f0
+#define ACL_POLICER_CNT_MODE_ADDR 0x09f4
+#define ACL_POLICER_CNT_RST_ADDR 0x09f8
+
+static sw_error_t
+_isis_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+ if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+ {
+ if (ISIS_MAX_EH_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+ else
+ {
+ if (ISIS_MAX_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ return SW_OK;
+}
+
+static void
+_isis_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_int32_t i;
+ a_uint32_t data[8] =
+ {
+ 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+ 512 * 1024
+ };
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isis_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] =
+ {
+ 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+ 512 * 1024
+ };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+ a_int32_t i;
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isis_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_int32_t i;
+ a_uint32_t data[8] =
+ {
+ 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+ 8 * 1024 * 1024, 32 * 1024 * 1024
+ };
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isis_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] =
+ {
+ 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+ 8 * 1024 * 1024, 32 * 1024 * 1024
+ };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+ a_int32_t i;
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isis_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isis_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag)
+{
+ *hw_flag = 0;
+
+ if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 1);
+ }
+
+ if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag)
+ {
+ *hw_flag |= (0x1 << 2);
+ }
+
+ if (FAL_INGRESS_POLICING_BROAD & sw_flag)
+ {
+ *hw_flag |= (0x1 << 3);
+ }
+
+ if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag)
+ {
+ *hw_flag |= (0x1 << 4);
+ }
+
+ if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 5);
+ }
+
+ if (FAL_INGRESS_POLICING_UNI & sw_flag)
+ {
+ *hw_flag |= (0x1 << 6);
+ }
+
+ if (FAL_INGRESS_POLICING_MUL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 7);
+ }
+}
+
+static void
+_isis_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag)
+{
+ *sw_flag = 0;
+
+ if (hw_flag & 0x2)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL;
+ }
+
+ if (hw_flag & 0x4)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT;
+ }
+
+ if (hw_flag & 0x8)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_BROAD;
+ }
+
+ if (hw_flag & 0x10)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI;
+ }
+
+ if (hw_flag & 0x20)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL;
+ }
+
+ if (hw_flag & 0x40)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNI;
+ }
+
+ if (hw_flag & 0x80)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_MUL;
+ }
+}
+
+static void
+_isis_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw)
+{
+ if (FAL_RATE_MI_100US == sw)
+ {
+ *hw = 0;
+ }
+ else if (FAL_RATE_MI_1MS == sw)
+ {
+ *hw = 1;
+ }
+ else if (FAL_RATE_MI_10MS == sw)
+ {
+ *hw = 2;
+ }
+ else if (FAL_RATE_MI_100MS)
+ {
+ *hw = 3;
+ }
+ else
+ {
+ *hw = 0;
+ }
+}
+
+static void
+_isis_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw)
+{
+ if (0 == hw)
+ {
+ *sw = FAL_RATE_MI_100US;
+ }
+ else if (1 == hw)
+ {
+ *sw = FAL_RATE_MI_1MS;
+ }
+ else if (2 == hw)
+ {
+ *sw = FAL_RATE_MI_10MS;
+ }
+ else
+ {
+ *sw = FAL_RATE_MI_100MS;
+ }
+}
+
+static sw_error_t
+_isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data[0] = 0x18000000;
+ if (FAL_BYTE_BASED == policer->meter_unit)
+ {
+ if (A_TRUE == policer->c_enable)
+ {
+ cir = policer->cir >> 5;
+ policer->cir = cir << 5;
+ _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+ _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ }
+
+ if (A_TRUE == policer->e_enable)
+ {
+ eir = policer->eir >> 5;
+ policer->eir = eir << 5;
+ _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+ _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]);
+ }
+ else if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ if (A_TRUE == policer->c_enable)
+ {
+ cir = (policer->cir * 2) / 125;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+ _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ }
+
+ if (A_TRUE == policer->c_enable)
+ {
+ eir = (policer->eir * 2) / 125;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+ _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+
+ if (A_TRUE == policer->combine_mode)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]);
+ }
+
+ if (A_TRUE == policer->deficit_en)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->color_mode)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->couple_flag)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]);
+ }
+
+ _isis_rate_ts_parse(policer->c_meter_interval, &tmp);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]);
+
+ _isis_rate_ts_parse(policer->e_meter_interval, &tmp);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]);
+
+ _isis_rate_flag_parse(policer->c_rate_flag, &tmp);
+ data[2] = (tmp << 8) & 0xff00;
+
+ _isis_rate_flag_parse(policer->e_rate_flag, &tmp);
+ data[2] |= (tmp & 0xff);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id,
+ (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id,
+ (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]);
+
+ policer->c_enable = A_TRUE;
+ if (0x7fff == cir)
+ {
+ policer->c_enable = A_FALSE;
+ cir = 0;
+ }
+
+ policer->e_enable = A_TRUE;
+ if (0x7fff == eir)
+ {
+ policer->e_enable = A_FALSE;
+ eir = 0;
+ }
+
+ if (unit)
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+ }
+ else
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ policer->cir = cir << 5;
+ policer->eir = eir << 5;
+ _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode,
+ data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en,
+ data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag,
+ data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode,
+ data[1]);
+
+ ts = (data[2] >> 8) & 0xff;
+ _isis_rate_flag_reparse(ts, &(policer->c_rate_flag));
+
+ ts = data[2] & 0xff;
+ _isis_rate_flag_reparse(ts, &(policer->e_rate_flag));
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]);
+ _isis_rate_ts_reparse(ts, &(policer->c_meter_interval));
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]);
+ _isis_rate_ts_reparse(ts, &(policer->e_meter_interval));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == enable)
+ {
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ cir = 0x7fff;
+ eir = 0x7fff;
+ }
+ else
+ {
+ if (FAL_BYTE_BASED == shaper->meter_unit)
+ {
+ cir = shaper->cir >> 5;
+ shaper->cir = cir << 5;
+
+ eir = shaper->eir >> 5;
+ shaper->eir = eir << 5;
+
+ _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+ _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+ _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+ data = 0;
+ }
+ else if (FAL_FRAME_BASED == shaper->meter_unit)
+ {
+ cir = (shaper->cir * 2) / 125;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (shaper->eir * 2) / 125;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+ _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+ _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (!data)
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if ((0x7fff == cir) && (0x7fff == eir))
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ *enable = A_TRUE;
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ shaper->meter_unit = FAL_FRAME_BASED;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+ _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+ }
+ else
+ {
+ shaper->meter_unit = FAL_BYTE_BASED;
+ shaper->cir = cir << 5;
+ shaper->eir = eir << 5;
+ _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+ _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_rate_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ cir = 0x7fff;
+ eir = 0x7fff;
+ }
+ else
+ {
+ if (FAL_BYTE_BASED == shaper->meter_unit)
+ {
+ cir = shaper->cir >> 5;
+ shaper->cir = cir << 5;
+
+ eir = shaper->eir >> 5;
+ shaper->eir = eir << 5;
+
+ _isis_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+ _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isis_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+ _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+ unit = 0;
+ }
+ else if (FAL_FRAME_BASED == shaper->meter_unit)
+ {
+ cir = (shaper->cir * 2) / 125;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (shaper->eir * 2) / 125;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isis_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+ _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isis_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+ _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+ unit = 1;
+ }
+
+ data = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (4 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_rate_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (4 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if ((0x7fff == cir) && (0x7fff == eir))
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ *enable = A_TRUE;
+ if (data)
+ {
+ shaper->meter_unit = FAL_FRAME_BASED;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isis_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+ _isis_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+ }
+ else
+ {
+ shaper->meter_unit = FAL_BYTE_BASED;
+ shaper->cir = cir << 5;
+ shaper->eir = eir << 5;
+ _isis_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+ _isis_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_POLICER_ID < policer_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == policer->counter_mode)
+ {
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ data[0] = 0x1;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ACL_POLICER_CNT_MODE_ADDR;
+ if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ data[0] = 0x0;
+ }
+ else
+ {
+ data[0] = 0x1;
+ }
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ACL_POLICER_CNT_RST_ADDR;
+ data[0] = 0x1;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data[0] = 0x0;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ return rv;
+ }
+
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ data[0] = 0x0;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_BYTE_BASED == policer->meter_unit)
+ {
+ cir = policer->cir >> 5;
+ policer->cir = cir << 5;
+
+ eir = policer->eir >> 5;
+ policer->eir = eir << 5;
+
+ _isis_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+ _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+
+ _isis_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+ _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]);
+ }
+ else if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ cir = (policer->cir * 2) / 125;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (policer->eir * 2) / 125;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isis_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+ _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+
+ _isis_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+ _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+
+ if (A_TRUE == policer->deficit_en)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->color_mode)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->couple_flag)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]);
+ }
+
+ _isis_rate_ts_parse(policer->meter_interval, &ts);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISIS_MAX_POLICER_ID < policer_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(policer, sizeof (policer));
+
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data[0])
+ {
+ policer->counter_mode = A_TRUE;
+
+ addr = ACL_POLICER_CNT_MODE_ADDR;
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data[0])
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ }
+ else
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ policer->counter_low = data[0];
+ policer->counter_high = data[1];
+
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]);
+ if (unit)
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isis_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ _isis_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+ }
+ else
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ policer->cir = cir << 5;
+ policer->eir = eir << 5;
+ _isis_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ _isis_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]);
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]);
+ _isis_rate_ts_reparse(ts, &(policer->meter_interval));
+
+ return SW_OK;
+}
+
+sw_error_t
+_isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ a_uint32_t val = number;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (val>255)
+ return SW_BAD_PARAM;
+
+ HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+sw_error_t
+_isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv = SW_OK;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+
+ HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ *number = val;
+
+ return rv;
+}
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_policer_set(dev_id, port_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_policer_get(dev_id, port_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress shaper parameters is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_acl_policer_set(dev_id, policer_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_acl_policer_get(dev_id, policer_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isis_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_add_rate_byte_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isis_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_rate_port_add_rate_byte_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_rate_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->rate_port_policer_set = isis_rate_port_policer_set;
+ p_api->rate_port_policer_get = isis_rate_port_policer_get;
+ p_api->rate_port_shaper_set = isis_rate_port_shaper_set;
+ p_api->rate_port_shaper_get = isis_rate_port_shaper_get;
+ p_api->rate_queue_shaper_set = isis_rate_queue_shaper_set;
+ p_api->rate_queue_shaper_get = isis_rate_queue_shaper_get;
+ p_api->rate_acl_policer_set = isis_rate_acl_policer_set;
+ p_api->rate_acl_policer_get = isis_rate_acl_policer_get;
+ p_api->rate_port_add_rate_byte_set = isis_rate_port_add_rate_byte_set;
+ p_api->rate_port_add_rate_byte_get = isis_rate_port_add_rate_byte_get;
+
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_reg_access.c b/src/hsl/isis/isis_reg_access.c
new file mode 100644
index 0000000..899d879
--- /dev/null
+++ b/src/hsl/isis/isis_reg_access.c
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "isis_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+#if defined(REG_ACCESS_SPEEDUP)
+static a_uint32_t mdio_base_addr = 0xffffffff;
+#endif
+
+
+
+
+int
+isis_reg_config_header (a_uint8_t *header, a_uint8_t wr_flag,
+ a_uint32_t reg_addr, a_uint8_t cmd_len,
+ a_uint8_t *val, a_uint32_t seq_num)
+{
+ athrs_header_t athrs_header;
+ athrs_header_regcmd_t reg_cmd;
+ a_uint16_t head_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN;
+ a_uint8_t buf[ISIS_HEADER_CMD_LEN+ISIS_HEADER_LEN+ISIS_HEADER_MAX_DATA_LEN] = { 0 };
+ a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN + ISIS_HEADER_LEN;
+
+ aos_mem_set(&athrs_header, 0, sizeof(athrs_header));
+ aos_mem_set(®_cmd, 0, sizeof(reg_cmd));
+ aos_mem_set(buf, 0, sizeof(buf));
+
+ /*fill atheros header*/
+ athrs_header.version = 2;
+ athrs_header.priority = 0;
+ athrs_header.type = 1;/*READ_WRITE_REG*/
+ athrs_header.broadcast = 0;
+ athrs_header.from_cpu = 1;
+ athrs_header.port_num = 0;
+
+ /*fill in 4 byte type atheros header witch specific header type
+ must config reg 0x98*/
+ buf[head_offset] = (ATHRS_HEADER_4BYTE_VAL & 0xff00)>>8;
+ buf[head_offset+1] = ATHRS_HEADER_4BYTE_VAL & 0xff;
+
+ buf[head_offset+2] = athrs_header.type;
+ buf[head_offset+2] |= athrs_header.priority << 3;
+ buf[head_offset+2] |= athrs_header.version << 6;
+ buf[head_offset+3] = athrs_header.port_num;
+ buf[head_offset+3] |= athrs_header.from_cpu << 7;
+
+ /*fill reg cmd*/
+ if(cmd_len > ISIS_HEADER_MAX_DATA_LEN)
+ cmd_len = ISIS_HEADER_MAX_DATA_LEN;//maximum data length is16 bytes
+ reg_cmd.reg_addr = reg_addr&0x7fffc; /*bit 0:18, lower 2 bits must be 0*/
+ reg_cmd.cmd_len = cmd_len;
+ reg_cmd.cmd = wr_flag;
+ reg_cmd.check_code = 5;
+ reg_cmd.seq_num = seq_num;
+
+ /*bit[0:18], reg addr*/
+ buf[0] = reg_cmd.reg_addr & 0xff;
+ buf[1] = (reg_cmd.reg_addr & 0xff00) >> 8;
+ buf[2] = (reg_cmd.reg_addr & 0x70000) >> 16;
+ /*bit[19:23], cmd data length*/
+ buf[2] |= reg_cmd.cmd_len << 3;
+ /*bit[28], cmd type, read/write*/
+ buf[3] = reg_cmd.cmd << 4;
+ /*bit[29:31], check code, must be 3'b101*/
+ buf[3] |= reg_cmd.check_code << 5;
+ /*bit[32:63], sequence num*/
+ buf[4] = (reg_cmd.seq_num & 0xff);
+ buf[5] = (reg_cmd.seq_num & 0xff00) >> 8;
+ buf[6] = (reg_cmd.seq_num & 0xff0000) >> 16;
+ buf[7] = (reg_cmd.seq_num & 0xff000000) >> 24;
+
+ if(!wr_flag)//write
+ {
+ aos_mem_copy(buf+ ISIS_HEADER_CMD_LEN , val, ISIS_HEADER_DATA_LEN);
+ if (cmd_len >4 )
+ aos_mem_copy(buf+ data2_offset , val + ISIS_HEADER_DATA_LEN, cmd_len - ISIS_HEADER_DATA_LEN);
+ }
+
+ aos_mem_copy(header, buf, sizeof(buf));
+ return 0;
+}
+
+
+sw_error_t isis_reg_parser_header_skb(a_uint8_t *header_buf, athrs_cmd_resp_t *cmd_resp)
+{
+ a_uint16_t data2_offset = ISIS_HEADER_CMD_LEN + ISIS_HEADER_DATA_LEN + ISIS_HEADER_LEN;
+ aos_mem_set(cmd_resp, 0, sizeof(cmd_resp));
+ cmd_resp->len = header_buf[2] >> 3;
+ if (cmd_resp->len > ISIS_HEADER_MAX_DATA_LEN)
+ return SW_BAD_LEN;
+
+ cmd_resp->seq = 0;
+ cmd_resp->seq = header_buf[4];
+ cmd_resp->seq |= header_buf[5] << 8;
+ cmd_resp->seq |= header_buf[6] << 16;
+ cmd_resp->seq |= header_buf[7] << 24;
+
+ aos_mem_copy (cmd_resp->data, (header_buf + ISIS_HEADER_CMD_LEN), ISIS_HEADER_DATA_LEN);
+ if (cmd_resp->len > 4)
+ aos_mem_copy ((cmd_resp->data+ISIS_HEADER_DATA_LEN), (header_buf + data2_offset), cmd_resp->len-4);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+ if (phy_val != mdio_base_addr)
+ {
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ mdio_base_addr = phy_val;
+ }
+#else
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+ if (phy_val != mdio_base_addr)
+ {
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ mdio_base_addr = phy_val;
+ }
+#else
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in higher address, we should write the lower 16-bit register then the */
+ /* higher one */
+
+ /* write register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ unsigned long flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _isis_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+isis_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ unsigned long flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _isis_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+isis_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ return SW_OK;
+}
+
+sw_error_t
+isis_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(isis_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+ SW_RTN_ON_ERROR(isis_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->phy_get = isis_phy_get;
+ p_api->phy_set = isis_phy_set;
+ p_api->reg_get = isis_reg_get;
+ p_api->reg_set = isis_reg_set;
+ p_api->reg_field_get = isis_reg_field_get;
+ p_api->reg_field_set = isis_reg_field_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+isis_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
+
diff --git a/src/hsl/isis/isis_sec.c b/src/hsl/isis/isis_sec.c
new file mode 100644
index 0000000..3d80e89
--- /dev/null
+++ b/src/hsl/isis/isis_sec.c
@@ -0,0 +1,778 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_sec ISIS_SEC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_sec.h"
+#include "isis_reg.h"
+
+#define NORM_CTRL0_ADDR 0x0200
+#define NORM_CTRL1_ADDR 0x0204
+#define NORM_CTRL2_ADDR 0x0208
+#define NORM_CTRL3_ADDR 0x0c00
+
+static sw_error_t
+_isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ fal_fwd_cmd_t cmd;
+ a_bool_t enable;
+ a_uint32_t addr, offset, len, reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ cmd = *((fal_fwd_cmd_t *) value);
+ enable = *((a_bool_t *) value);
+ val = *((a_uint32_t *) value);
+
+ len = 1;
+ switch (item)
+ {
+ case FAL_NORM_MAC_RESV_VID_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 0;
+ goto cmd_chk;
+
+ case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 20;
+ goto cmd_chk;
+
+ case FAL_NORM_IP_INVALID_VER_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_IP_SAME_ADDR_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 2;
+ goto cmd_chk;
+ break;
+
+ case FAL_NROM_IP_TTL_CHANGE_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 11;
+ goto sts_chk;
+
+ case FAL_NROM_IP_TTL_VALUE:
+ addr = NORM_CTRL3_ADDR;
+ offset = 12;
+ len = 8;
+ goto set_reg;
+
+ case FAL_NROM_IP4_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 3;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 4;
+ len = 2;
+ goto s_cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_DF_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 7;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 8;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 24;
+ len = 8;
+ goto set_reg;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 9;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 10;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_SIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 11;
+ len = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_DIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 12;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 13;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 19;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_DF_CLEAR_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 9;
+ goto sts_chk;
+
+ case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 10;
+ goto sts_chk;
+
+ case FAL_NROM_IP6_INVALID_DIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 16;
+ goto cmd_chk;
+
+ case FAL_NROM_IP6_INVALID_SIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 17;
+ goto cmd_chk;
+
+ case FAL_NROM_IP6_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 18;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_BLAT_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 14;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 15;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_MIN_HDR_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 12;
+ len = 4;
+ goto set_reg;
+
+ case FAL_NROM_TCP_INVALID_SYN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 16;
+ goto cmd_chk;
+ break;
+
+ case FAL_NROM_TCP_SU_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 17;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 18;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SAP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 19;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_XMAS_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 20;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_NULL_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 21;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 22;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SF_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 23;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SAR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 24;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_RST_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 25;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 26;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 27;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_FA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 28;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_PA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 29;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_UA_BLOCK_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 0;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 2;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 3;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_BLAT_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 4;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_INVALID_LEN_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 5;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 6;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 7;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 8;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 9;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP6_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 10;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 0;
+ len = 14;
+ goto set_reg;
+
+ case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 16;
+ len = 14;
+ goto set_reg;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+
+sts_chk:
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ goto set_reg;
+
+s_cmd_chk:
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ val = 3;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ goto set_reg;
+
+cmd_chk:
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+set_reg:
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ a_uint32_t addr, offset, len, reg, val;
+ a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ len = 1;
+ switch (item)
+ {
+ case FAL_NORM_MAC_RESV_VID_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 0;
+ break;
+
+ case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 20;
+ break;
+
+ case FAL_NORM_IP_INVALID_VER_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 1;
+ break;
+
+ case FAL_NROM_IP_SAME_ADDR_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 2;
+ break;
+
+ case FAL_NROM_IP_TTL_CHANGE_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 11;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP_TTL_VALUE:
+ addr = NORM_CTRL3_ADDR;
+ offset = 12;
+ len = 8;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 2;
+ break;
+
+ case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 4;
+ len = 2;
+ scmd_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_DF_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 7;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 8;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 24;
+ len = 8;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 9;
+ break;
+
+ case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 10;
+ break;
+
+ case FAL_NROM_IP4_INVALID_SIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 11;
+ len = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_DIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 12;
+ break;
+
+ case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 13;
+ break;
+
+ case FAL_NROM_IP4_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 19;
+ break;
+
+ case FAL_NROM_IP4_DF_CLEAR_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 9;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 10;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP6_INVALID_DIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 16;
+ break;
+
+ case FAL_NROM_IP6_INVALID_SIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 17;
+ break;
+
+ case FAL_NROM_IP6_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 18;
+ break;
+
+ case FAL_NROM_TCP_BLAT_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 14;
+ break;
+
+ case FAL_NROM_TCP_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 15;
+ break;
+
+ case FAL_NROM_TCP_MIN_HDR_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 12;
+ len = 4;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_TCP_INVALID_SYN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 16;
+ break;
+
+ case FAL_NROM_TCP_SU_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 17;
+ break;
+
+ case FAL_NROM_TCP_SP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 18;
+ break;
+
+ case FAL_NROM_TCP_SAP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 19;
+ break;
+
+ case FAL_NROM_TCP_XMAS_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 20;
+ break;
+
+ case FAL_NROM_TCP_NULL_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 21;
+ break;
+
+ case FAL_NROM_TCP_SR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 22;
+ break;
+
+ case FAL_NROM_TCP_SF_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 23;
+ break;
+
+ case FAL_NROM_TCP_SAR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 24;
+ break;
+
+ case FAL_NROM_TCP_RST_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 25;
+ break;
+
+ case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 26;
+ break;
+
+ case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 27;
+ break;
+
+ case FAL_NROM_TCP_FA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 28;
+ break;
+
+ case FAL_NROM_TCP_PA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 29;
+ break;
+
+ case FAL_NROM_TCP_UA_BLOCK_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 0;
+ break;
+
+ case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 1;
+ break;
+
+ case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 2;
+ break;
+
+ case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 3;
+ break;
+
+ case FAL_NROM_UDP_BLAT_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 4;
+ break;
+
+ case FAL_NROM_UDP_INVALID_LEN_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 5;
+ break;
+
+ case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 6;
+ break;
+
+ case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 7;
+ break;
+
+ case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 8;
+ break;
+
+ case FAL_NROM_ICMP4_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 9;
+ break;
+
+ case FAL_NROM_ICMP6_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 10;
+ break;
+
+ case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 0;
+ len = 14;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 16;
+ len = 14;
+ val_chk = 1;
+ break;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
+
+ if (val_chk)
+ {
+ *((a_uint32_t *) value) = val;
+ }
+ else if (status_chk)
+ {
+ if (val)
+ {
+ *((a_bool_t *) value) = A_TRUE;
+ }
+ else
+ {
+ *((a_bool_t *) value) = A_FALSE;
+ }
+ }
+ else if (scmd_chk)
+ {
+ if (2 == val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
+ }
+ else if (3 == val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+ }
+ else
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+ }
+ }
+ else
+ {
+ if (val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+ }
+ else
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+ }
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_sec_norm_item_set(dev_id, item, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_sec_norm_item_get(dev_id, item, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_sec_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->sec_norm_item_set = isis_sec_norm_item_set;
+ p_api->sec_norm_item_get = isis_sec_norm_item_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isis/isis_stp.c b/src/hsl/isis/isis_stp.c
new file mode 100644
index 0000000..b6f7510
--- /dev/null
+++ b/src/hsl/isis/isis_stp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_stp ISIS_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_stp.h"
+#include "isis_reg.h"
+
+#define ISIS_PORT_DISABLED 0
+#define ISIS_STP_BLOCKING 1
+#define ISIS_STP_LISTENING 2
+#define ISIS_STP_LEARNING 3
+#define ISIS_STP_FARWARDING 4
+
+static sw_error_t
+_isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ switch (state)
+ {
+ case FAL_STP_BLOKING:
+ val = ISIS_STP_BLOCKING;
+ break;
+ case FAL_STP_LISTENING:
+ val = ISIS_STP_LISTENING;
+ break;
+ case FAL_STP_LEARNING:
+ val = ISIS_STP_LEARNING;
+ break;
+ case FAL_STP_FARWARDING:
+ val = ISIS_STP_FARWARDING;
+ break;
+ case FAL_STP_DISABLED:
+ val = ISIS_PORT_DISABLED;
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ switch (val)
+ {
+ case ISIS_STP_BLOCKING:
+ *state = FAL_STP_BLOKING;
+ break;
+ case ISIS_STP_LISTENING:
+ *state = FAL_STP_LISTENING;
+ break;
+ case ISIS_STP_LEARNING:
+ *state = FAL_STP_LEARNING;
+ break;
+ case ISIS_STP_FARWARDING:
+ *state = FAL_STP_FARWARDING;
+ break;
+ case ISIS_PORT_DISABLED:
+ *state = FAL_STP_DISABLED;
+ break;
+ default:
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_stp_port_state_set(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_stp_port_state_get(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_stp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->stp_port_state_set = isis_stp_port_state_set;
+ p_api->stp_port_state_get = isis_stp_port_state_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_trunk.c b/src/hsl/isis/isis_trunk.c
new file mode 100644
index 0000000..d3fbc5c
--- /dev/null
+++ b/src/hsl/isis/isis_trunk.c
@@ -0,0 +1,681 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup isis_trunk ISIS_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_trunk.h"
+#include "isis_reg.h"
+
+#define ISIS_MAX_TRUNK_ID 3
+
+/*feature on/off for manipulating dp within trunk group*/
+#define ISIS_TRUNK_MANIPULATE_DP_ON 1
+#define ISIS_TRUNK_MANIPULATE_HEADER_LEN 12
+#define MAC_LEN 6
+#define HASH_SIZE 4
+
+enum isis_trunk_reg_id
+{
+ ISIS_TRUNK_HASH_EN = 0, /*0x270*/
+ ISIS_TRUNK_CTRL_0, /*0x700*/
+ ISIS_TRUNK_CTRL_1, /*0x704*/
+ ISIS_TRUNK_CTRL_2, /*0x708*/
+ ISIS_TRUNK_REG_MAX
+};
+
+static a_uint32_t isis_trunk_regs[ISIS_TRUNK_REG_MAX] =
+{
+ 0xf, 0x0, 0x0, 0x0
+};
+
+static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] =
+{
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 }
+};
+
+static sw_error_t
+_isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+ a_uint32_t i, reg, cnt = 0, data0 = 0, data1 = 0;
+
+ if (ISIS_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data0 = (0x1 << 7) | member;
+
+ for (i = 0; i < 7; i++)
+ {
+ if (member & (0x1 << i))
+ {
+ if (4 <= cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data1 |= (i << (cnt << 2));
+ data1 |= (1 << (3 + (cnt << 2)));
+ cnt++;
+ }
+ }
+ }
+ else if (A_FALSE == enable)
+ {
+
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* set trunk port member bitmap info */
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= (~(0xff << (trunk_id << 3)));
+ reg |= (data0 << (trunk_id << 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isis_trunk_regs[ISIS_TRUNK_CTRL_0] = reg;
+
+ /* set trunk port member id info */
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= (~(0xffff << ((trunk_id % 2) << 4)));
+ reg |= (data1 << ((trunk_id % 2) << 4));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ if (ISIS_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (trunk_id << 3)) & 0xff;
+ if (0x80 & data)
+ {
+ *enable = A_TRUE;
+ *member = data & 0x7f;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *member = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ if (ISIS_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg = isis_trunk_regs[ISIS_TRUNK_CTRL_0];
+
+ data = (reg >> (trunk_id << 3)) & 0xff;
+ if (0x80 & data)
+ {
+ *enable = A_TRUE;
+ *member = data & 0x7f;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *member = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isis_trunk_regs[ISIS_TRUNK_HASH_EN] = data;
+
+ return rv;
+}
+
+static sw_error_t
+_isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *hash_mode = 0;
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+ }
+
+ return SW_OK;
+}
+
+#define BYTE_B2R(x, mask) ((x) ^ (mask))
+#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4))
+
+static sw_error_t
+_isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < HASH_SIZE; i++)
+ {
+ memcpy(sa_hash[i], addr->uc, MAC_LEN);
+ sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ memcpy(addr->uc, sa_hash[0], MAC_LEN);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data = 0;
+
+ reg = isis_trunk_regs[ISIS_TRUNK_HASH_EN];
+
+ *hash_mode = 0;
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp,
+ a_uint32_t * trunk_id, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_bool_t enable;
+ a_uint32_t i;
+
+ for (i = 0; i <= ISIS_MAX_TRUNK_ID; i++)
+ {
+ rv = _isis_trunk_group_sw_get(dev_id, i, &enable, member);
+ SW_RTN_ON_ERROR(rv);
+ if (enable && (*member & expect_dp))
+ {
+ *trunk_id = i;
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+ a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp)
+{
+#define BIT2_MASK 0x03
+#define TRUNK_MEM_EN_MASK 0x8
+#define TRUNK_MEM_PT_MASK 0x7
+#define TRUNK_HASH_DP_SEL 4
+ sw_error_t rv;
+ a_uint32_t i, hash_mode, reg, data1 = 0;
+ a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/
+ a_uint8_t xor_dp = 0;
+
+ rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!hash_mode)
+ {
+ return SW_DISABLE;
+ }
+
+ *hash_dp = 0;
+
+ if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA))
+ {
+ for (i = 0; i < MAC_LEN; i++)
+ {
+ da_xor ^= (header[i] & BIT2_MASK) ^
+ ((header[i] >> 2) & BIT2_MASK) ^
+ ((header[i] >> 4) & BIT2_MASK) ^
+ ((header[i] >> 6) & BIT2_MASK);
+ }
+ *hash_dp = da_xor;
+ }
+ if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA))
+ {
+ for (i = 6; i < 2 * MAC_LEN; i++)
+ {
+ sa_xor ^= (header[i] & BIT2_MASK) ^
+ ((header[i] >> 2) & BIT2_MASK) ^
+ ((header[i] >> 4) & BIT2_MASK) ^
+ ((header[i] >> 6) & BIT2_MASK);
+ }
+ *hash_dp = (*hash_dp) ^ sa_xor;
+ }
+
+ /*dp translation*/
+#if 0
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#else /*sw*/
+ reg = isis_trunk_regs[ISIS_TRUNK_CTRL_1 + (trunk_id >> 1)];
+#endif
+
+ for (i = 0; i < TRUNK_HASH_DP_SEL; i++)
+ {
+ xor_dp = BYTE_B2R(*hash_dp, i);
+ data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2))));
+ if (data1 & TRUNK_MEM_EN_MASK)
+ {
+ *hash_dp = data1 & TRUNK_MEM_PT_MASK;
+ *hash_dp = 0x01 << (*hash_dp); /*bmp*/
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isis_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+ a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member)
+{
+ sw_error_t rv;
+ a_uint32_t i, hash_mode;
+ a_uint8_t hash_dp;
+ a_uint8_t ori_sa[MAC_LEN];
+
+ rv = _isis_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA))
+ {
+ return SW_DISABLE;
+ }
+
+ memcpy(ori_sa, &header[MAC_LEN], MAC_LEN);
+
+ for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++)
+ {
+ memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN);
+ rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+ FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+ SW_RTN_ON_ERROR(rv);
+ if (expect_dp == hash_dp)
+ {
+ // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i);
+ return SW_OK;
+ }
+ }
+
+ /*should never here*/
+ memcpy(&header[MAC_LEN], ori_sa, MAC_LEN);
+ return SW_FAIL;
+}
+
+static sw_error_t
+_isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member)
+{
+ sw_error_t rv;
+ a_uint8_t expect_dp, hash_dp; /*bitmap*/
+ a_uint32_t i, trunk_id;
+ fal_pbmp_t member;
+
+ if (!ISIS_TRUNK_MANIPULATE_DP_ON)
+ {
+ return SW_OK; /*feature not enabled*/
+ }
+
+ if (!header || len < ISIS_TRUNK_MANIPULATE_HEADER_LEN)
+ {
+ return SW_BAD_VALUE;
+ }
+
+#if 0 /*de-comment this to ignore broadcast packets*/
+ const a_uint8_t bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ if (!memcmp(header, bc_mac, MAC_LEN)) /*not for broadcast*/
+ {
+ return SW_OK;
+ }
+#endif
+
+ /*expect_dp within trunk group*/
+ expect_dp = dp_member & 0x7f;
+ for (i = 0; i < 7; i++)
+ {
+ if (expect_dp & (0x01 << i))
+ {
+ rv = _isis_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member);
+ if (rv != SW_OK)
+ {
+ expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/
+ }
+ }
+ }
+
+ if (BYTE_B1C(expect_dp) != 1) /*supports 1 dp only*/
+ {
+ return SW_OK; /*ignore none-dp or multi-dp*/
+ }
+
+ rv = _isis_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member);
+ SW_RTN_ON_ERROR(rv);
+
+ member &= 0x7f;
+ if (BYTE_B1C(member) == 1) /*trunk group w/ one port*/
+ {
+ return SW_OK;
+ }
+
+ rv = _isis_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+ FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+ SW_RTN_ON_ERROR(rv);
+
+ // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member);
+ if (expect_dp == hash_dp)
+ {
+ return SW_OK;
+ }
+
+ rv = _isis_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member);
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_group_set(dev_id, trunk_id, enable, member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_group_get(dev_id, trunk_id, enable, member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @details Comments:
+ hash mode is listed below
+ FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_hash_mode_set(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_hash_mode_get(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_manipulate_sa_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[out] addr manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_manipulate_sa_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief manipulate destination port within a trunk group
+ * @details Comments:
+ * supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA;
+ * FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design
+ * @param[in] dev_id device id
+ * @param[in-out] header packet header, accept format: [DA:6B][SA:6B]
+ * @param[in] len length of packet header, should be 12 in current design (6B DA + 6B SA)
+ * @param[in] dp_member expect destination port members, bitmap format
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_trunk_manipulate_dp(dev_id, header, len, dp_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+sw_error_t
+isis_trunk_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->trunk_group_set = isis_trunk_group_set;
+ p_api->trunk_group_get = isis_trunk_group_get;
+ p_api->trunk_hash_mode_set = isis_trunk_hash_mode_set;
+ p_api->trunk_hash_mode_get = isis_trunk_hash_mode_get;
+ p_api->trunk_manipulate_sa_set = isis_trunk_manipulate_sa_set;
+ p_api->trunk_manipulate_sa_get = isis_trunk_manipulate_sa_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isis/isis_vlan.c b/src/hsl/isis/isis_vlan.c
new file mode 100644
index 0000000..a5af347
--- /dev/null
+++ b/src/hsl/isis/isis_vlan.c
@@ -0,0 +1,900 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isis_vlan ISIS_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isis_vlan.h"
+#include "isis_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+#define VLAN_NEXT_ENTRY 5
+#define VLAN_FIND_ENTRY 6
+
+static void
+_isis_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+ a_uint32_t i, data, tmp;
+
+ aos_mem_zero(vlan_entry, sizeof (fal_vlan_t));
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]);
+ vlan_entry->vid = data & 0xfff;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->fid = vlan_entry->vid;
+ }
+ else
+ {
+ vlan_entry->fid = FAL_SVL_FID;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->learn_dis = A_TRUE;
+ }
+ else
+ {
+ vlan_entry->learn_dis = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->vid_pri_en = A_TRUE;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+ vlan_entry->vid_pri = data & 0xff;
+ }
+ else
+ {
+ vlan_entry->vid_pri_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+ for (i = 0; i < 7; i++)
+ {
+ tmp = (data >> (i << 1)) & 0x3UL;
+ if (0 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->unmodify_ports |= (0x1UL << i);
+ }
+ else if (1 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->untagged_ports |= (0x1UL << i);
+ }
+ else if (2 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->tagged_ports |= (0x1UL << i);
+ }
+ }
+
+ return;
+}
+
+static sw_error_t
+_isis_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t i, tag, untag, unmodify, member = 0;
+
+ if (vlan_entry->vid > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+
+ if (FAL_SVL_FID == vlan_entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+ }
+ else if (vlan_entry->vid == vlan_entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (A_TRUE == vlan_entry->learn_dis)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ }
+
+ for (i = 0; i < 7; i++)
+ {
+ if ((vlan_entry->mem_ports >> i) & 0x1UL)
+ {
+ tag = (vlan_entry->tagged_ports >> i) & 0x1UL;
+ untag = (vlan_entry->untagged_ports >> i) & 0x1UL;
+ unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL;
+
+ if ((0 == (tag + untag + unmodify))
+ || (1 < (tag + untag + unmodify)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (tag)
+ {
+ member |= (2 << (i << 1));
+ }
+ else if (untag)
+ {
+ member |= (1 << (i << 1));
+ }
+ }
+ else
+ {
+ member |= (3 << (i << 1));
+ }
+ }
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]);
+
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri,
+ reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ {
+ printk("%s BUSY\n", __FUNCTION__);
+ return SW_BUSY;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ vt_busy = 1;
+ i = 0x1000;
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (!val)
+ {
+ if (VLAN_FIND_ENTRY == op)
+ return SW_NOT_FOUND;
+
+ if (VLAN_NEXT_ENTRY == op)
+ return SW_NO_MORE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_up_to_sw(dev_id, reg);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_sw_to_hw(dev_id, vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+
+ rv = _isis_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id)
+ {
+ rv = _isis_vlan_hwentry_get(dev_id, 0, reg);
+
+ if (SW_OK == rv)
+ {
+ _isis_vlan_hw_to_sw(reg, p_vlan);
+ return SW_OK;
+ }
+ else
+ {
+ vlan_id = 0;
+ }
+ }
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_vlan_hw_to_sw(reg, p_vlan);
+
+ if (0 == p_vlan->vid)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isis_vlan_hw_to_sw(reg, p_vlan);
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ reg = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_FLUSH);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((MAX_VLAN_ID >= fid) && (vlan_id != fid))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SVL_FID == fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ }
+
+ rv = _isis_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+ if (data)
+ {
+ *fid = vlan_id;
+ }
+ else
+ {
+ *fid = FAL_SVL_FID;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_isis_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, a_uint32_t port_info)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+ data &= (~(0x3 << (port_id << 1)));
+ data |= ((port_info & 0x3) << (port_id << 1));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+
+ rv = _isis_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+ a_uint32_t info = 0;
+
+ if (FAL_EG_UNMODIFIED == port_info)
+ {
+ info = 0;
+ }
+ else if (FAL_EG_TAGGED == port_info)
+ {
+ info = 0x2;
+ }
+ else if (FAL_EG_UNTAGGED == port_info)
+ {
+ info = 0x1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t info = 0x3;
+
+ rv = _isis_vlan_member_update(dev_id, vlan_id, port_id, info);
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isis_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isis_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isis_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+ if (data)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+ return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_flush(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_fid_set(dev_id, vlan_id, fid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_fid_get(dev_id, vlan_id, fid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_member_del(dev_id, vlan_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_learning_state_set(dev_id, vlan_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_vlan_learning_state_get(dev_id, vlan_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isis_vlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = isis_vlan_entry_append;
+ p_api->vlan_creat = isis_vlan_create;
+ p_api->vlan_delete = isis_vlan_delete;
+ p_api->vlan_next = isis_vlan_next;
+ p_api->vlan_find = isis_vlan_find;
+ p_api->vlan_flush = isis_vlan_flush;
+ p_api->vlan_fid_set = isis_vlan_fid_set;
+ p_api->vlan_fid_get = isis_vlan_fid_get;
+ p_api->vlan_member_add = isis_vlan_member_add;
+ p_api->vlan_member_del = isis_vlan_member_del;
+ p_api->vlan_learning_state_set = isis_vlan_learning_state_set;
+ p_api->vlan_learning_state_get = isis_vlan_learning_state_get;
+
+
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/Makefile b/src/hsl/isisc/Makefile
new file mode 100644
index 0000000..2cb25ec
--- /dev/null
+++ b/src/hsl/isisc/Makefile
@@ -0,0 +1,119 @@
+LOC_DIR=src/hsl/isisc
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=isisc_reg_access.c isisc_init.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += isisc_acl.c isisc_acl_parse.c isisc_multicast_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += isisc_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += isisc_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += isisc_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += isisc_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += isisc_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += isisc_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += isisc_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += isisc_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += isisc_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += isisc_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += isisc_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += isisc_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += isisc_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ SRC_LIST += isisc_reduced_acl.c
+endif
+
+ifeq (TRUE, $(IN_COSMAP))
+ SRC_LIST += isisc_cosmap.c
+endif
+
+ifeq (TRUE, $(IN_IP))
+ SRC_LIST += isisc_ip.c
+endif
+
+ifeq (TRUE, $(IN_NAT))
+ SRC_LIST += isisc_nat.c
+endif
+
+ifeq (TRUE, $(IN_NAT_HELPER))
+ SRC_LIST += nat_helper_dt.c
+ SRC_LIST += nat_helper_hsl.c
+# SRC_LIST += nat_ipt_helper.c
+ SRC_LIST += napt_helper.c
+ SRC_LIST += host_helper.c
+ SRC_LIST += nat_helper.c
+ SRC_LIST += napt_acl.c
+ SRC_LIST += napt_procfs.c
+endif
+
+ifeq (TRUE, $(IN_TRUNK))
+ SRC_LIST += isisc_trunk.c
+endif
+
+ifeq (TRUE, $(IN_SEC))
+ SRC_LIST += isisc_sec.c
+endif
+
+ifeq (TRUE, $(IN_INTERFACECONTROL))
+ SRC_LIST += isisc_interface_ctrl.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=isisc_reg_access.c isisc_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring ISISC, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/hsl/isisc/isisc_acl.c b/src/hsl/isisc/isisc_acl.c
new file mode 100644
index 0000000..a2dc30b
--- /dev/null
+++ b/src/hsl/isisc/isisc_acl.c
@@ -0,0 +1,1983 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_acl ISISC_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#include "isisc_acl_prv.h"
+
+//#define ISISC_ACL_DEBUG
+//#define ISISC_SW_ENTRY
+#define ISISC_HW_ENTRY
+
+static isisc_acl_list_t *sw_list_ent[SW_MAX_NR_DEV];
+static isisc_acl_rule_t *sw_rule_ent[SW_MAX_NR_DEV];
+
+static isisc_acl_rule_t *sw_rule_tmp[SW_MAX_NR_DEV];
+static isisc_acl_rule_t *hw_rule_tmp[SW_MAX_NR_DEV];
+#ifdef ISISC_SW_ENTRY
+static a_uint8_t *sw_filter_mem = NULL;
+#endif
+
+static sw_error_t
+_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag);
+
+static sw_error_t
+_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx,
+ a_uint32_t ports);
+
+static sw_error_t
+_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op);
+
+static sw_error_t
+_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op);
+
+static sw_error_t
+_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable);
+
+static void
+_isisc_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+ isisc_acl_list_t *sw_list;
+
+ aos_printk("\ndev_id=%d list control infomation:", dev_id);
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_list = &(sw_list_ent[dev_id][i]);
+ if (ENT_USED & sw_list->status)
+ {
+ aos_printk
+ ("\nlist_id=%02d list_pri=%02d rule_nr=%02d [pts_map]:0x%02x idx=%02d ",
+ sw_list->list_id, sw_list->list_pri, sw_list->rule_nr,
+ sw_list->bind_pts, i);
+ }
+ }
+ aos_printk("\n");
+}
+
+static void
+_isisc_acl_sw_rule_dump(char *info, isisc_acl_rule_t * sw_rule)
+{
+#ifdef ISISC_ACL_DEBUG
+ a_uint32_t flt_idx, i;
+
+ aos_printk("\n%s", info);
+ for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++)
+ {
+ aos_printk("\n%d software filter:", flt_idx);
+ aos_printk("\nact:");
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < 5; i++)
+ {
+ aos_printk("%08x ", sw_rule[flt_idx].filter.msk[i]);
+ }
+
+ aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d]",
+ sw_rule[flt_idx].status,
+ sw_rule[flt_idx].list_id, sw_rule[flt_idx].rule_id);
+
+ aos_printk("\n\n");
+ }
+#else
+ return;
+#endif
+}
+
+static isisc_acl_list_t *
+_isisc_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ if ((ENT_USED & sw_list_ent[dev_id][i].status)
+ && (list_id == sw_list_ent[dev_id][i].list_id))
+ {
+ return &(sw_list_ent[dev_id][i]);
+ }
+ }
+ return NULL;
+}
+
+static sw_error_t
+_isisc_filter_valid_set(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flag)
+{
+#ifdef ISISC_SW_ENTRY
+ hw_filter_t filter;
+
+ _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+ filter.msk[4] &= 0xfffffff8;
+ filter.msk[4] |= (flag & 0x7);
+
+ _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+#ifdef ISISC_HW_ENTRY
+ hw_filter_t filter;
+
+ filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+ filter.msk[4] &= 0xfffffff8;
+ filter.msk[4] |= (flag & 0x7);
+
+ _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+#else
+ sw_error_t rv;
+ a_uint32_t addr, data = 0;
+
+ /* read filter mask at first */
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter mask and modify it */
+ addr = ISISC_RULE_FUNC_ADDR + 20;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= 0xfffffff8;
+ data |= (flag & 0x7);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* write back filter mask */
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 8) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isisc_filter_ports_bind(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t ports)
+{
+#ifdef ISISC_SW_ENTRY
+ hw_filter_t filter;
+
+ _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+
+ filter.vlu[4] &= 0xffffff80;
+ filter.vlu[4] |= (ports & 0x7f);
+
+ _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+#ifdef ISISC_HW_ENTRY
+ hw_filter_t filter;
+
+ filter = sw_rule_ent[dev_id][flt_idx].filter;
+
+ filter.vlu[4] &= 0xffffff80;
+ filter.vlu[4] |= (ports & 0x7f);
+
+ _isisc_filter_down_to_hw(dev_id, &filter, flt_idx);
+
+ return SW_OK;
+#else
+ sw_error_t rv;
+ a_uint32_t addr, data;
+
+ /* read filter value at first */
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter value and modify it */
+ addr = ISISC_RULE_FUNC_ADDR + 20;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= 0xffffff80;
+ data |= (ports & 0x7f);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* write back filter value */
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+#endif
+#endif
+}
+
+static sw_error_t
+_isisc_filter_write(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op)
+{
+ a_uint32_t i, addr, data, idx = 6;
+ sw_error_t rv;
+
+ if (ISISC_FILTER_ACT_OP == op)
+ {
+ idx = 4;
+ }
+
+ for (i = 1; i < idx; i++)
+ {
+ addr = ISISC_RULE_FUNC_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(reg[i - 1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_filter_read(a_uint32_t dev_id, a_uint32_t reg[], a_uint32_t flt_idx,
+ a_uint32_t op)
+{
+ a_uint32_t i, addr, data, idx = 6;
+ sw_error_t rv;
+
+ addr = ISISC_RULE_FUNC_ADDR;
+ data = (flt_idx & 0x7f) | (op << 8) | (0x1 << 10) | (0x1 << 31);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISISC_FILTER_ACT_OP == op)
+ {
+ idx = 4;
+ }
+
+ for (i = 1; i < idx; i++)
+ {
+ addr = ISISC_RULE_FUNC_ADDR + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(reg[i - 1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_filter_down_to_hw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx)
+{
+#ifdef ISISC_SW_ENTRY
+ a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+ aos_mem_copy(tbl, filter, sizeof (hw_filter_t));
+#else
+#ifdef ISISC_HW_ENTRY
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->act[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#else
+ sw_error_t rv;
+
+ rv = _isisc_filter_write(dev_id, &(filter->act[0]), flt_idx,
+ ISISC_FILTER_ACT_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_filter_write(dev_id, &(filter->vlu[0]), flt_idx,
+ ISISC_FILTER_VLU_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_filter_write(dev_id, &(filter->msk[0]), flt_idx,
+ ISISC_FILTER_MSK_OP);
+ SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_filter_up_to_sw(a_uint32_t dev_id, hw_filter_t * filter,
+ a_uint32_t flt_idx)
+{
+#ifdef ISISC_SW_ENTRY
+ a_uint8_t *tbl = sw_filter_mem + sizeof (hw_filter_t) * flt_idx;
+
+ aos_mem_copy(filter, tbl, sizeof (hw_filter_t));
+#else
+#ifdef ISISC_HW_ENTRY
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = ISISC_FILTER_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISISC_FILTER_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ base = ISISC_FILTER_ACT_ADDR + (flt_idx << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(filter->act[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#else
+ sw_error_t rv;
+
+ rv = _isisc_filter_read(dev_id, &(filter->vlu[0]), flt_idx,
+ ISISC_FILTER_VLU_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_filter_read(dev_id, &(filter->msk[0]), flt_idx,
+ ISISC_FILTER_MSK_OP);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_filter_read(dev_id, &(filter->act[0]), flt_idx,
+ ISISC_FILTER_ACT_OP);
+ SW_RTN_ON_ERROR(rv);
+#endif
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_insert(a_uint32_t dev_id, a_uint32_t * src_idx,
+ a_uint32_t * dst_idx, isisc_acl_rule_t * src_rule,
+ isisc_acl_rule_t * dst_rule)
+{
+ a_uint32_t i, data, rule_id, list_id, list_pri;
+
+ rule_id = 0;
+ list_id = src_rule[*src_idx].list_id;
+ list_pri = src_rule[*src_idx].list_pri;
+
+ for (i = *src_idx; i < ISISC_MAX_FILTER; i++)
+ {
+ if (!(ENT_USED & src_rule[i].status))
+ {
+ continue; // was: break;
+ }
+
+ if (src_rule[i].list_id != list_id)
+ {
+ break;
+ }
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+ src_rule[i].filter.msk[4]);
+ if (!data)
+ {
+ continue;
+ }
+
+ if (ISISC_MAX_FILTER <= *dst_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (ENT_USED & dst_rule[*dst_idx].status)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_VALID, data,
+ src_rule[i].filter.msk[4]);
+ if ((FLT_START == data) && (*dst_idx % 2))
+ {
+ if (*src_idx != i)
+ {
+ dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id - 1;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ }
+
+ (*dst_idx)++;
+ if (ISISC_MAX_FILTER <= *dst_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (ENT_USED & dst_rule[*dst_idx].status)
+ {
+ return SW_NO_RESOURCE;
+ }
+ }
+
+ aos_mem_copy(&(dst_rule[*dst_idx].filter), &(src_rule[i].filter),
+ sizeof (hw_filter_t));
+ dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ if (ENT_DEACTIVE & src_rule[i].status)
+ {
+ dst_rule[*dst_idx].status |= ENT_DEACTIVE;
+ }
+ (*dst_idx)++;
+
+ if ((FLT_END == data) && (*dst_idx % 2))
+ {
+ if (ISISC_MAX_FILTER > *dst_idx)
+ {
+ dst_rule[*dst_idx].src_flt_dis = src_rule[i].src_flt_dis;
+ dst_rule[*dst_idx].list_id = list_id;
+ dst_rule[*dst_idx].list_pri = list_pri;
+ dst_rule[*dst_idx].rule_id = rule_id;
+ dst_rule[*dst_idx].status |= ENT_USED;
+ (*dst_idx)++;
+ }
+ }
+
+ if ((FLT_END == data) || (FLT_STARTEND == data))
+ {
+ rule_id++;
+ }
+ }
+
+ *src_idx = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_alloc(a_uint32_t dev_id, isisc_acl_list_t * sw_list,
+ a_uint32_t filter_nr)
+{
+ a_uint32_t free_flt_nr, load_idx, begin_idx, start_idx, end_idx, i;
+ a_uint32_t largest_nr, largest_idx;
+ sw_error_t rv;
+
+ /* calculate the proper location, [start_idx, end_idx) */
+ start_idx = 0;
+ end_idx = ISISC_MAX_FILTER;
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ if (sw_rule_ent[dev_id][i].list_pri < sw_list->list_pri)
+ {
+ start_idx = i + 1;
+ }
+ else if (sw_rule_ent[dev_id][i].list_pri > sw_list->list_pri)
+ {
+ end_idx = i;
+ break;
+ }
+ }
+ }
+
+ /* find the larget free filters block */
+ largest_nr = 0;
+ largest_idx = 0;
+ free_flt_nr = 0;
+ begin_idx = start_idx;
+ for (i = start_idx; i < end_idx; i++)
+ {
+ if (!(ENT_USED & sw_rule_ent[dev_id][i].status))
+ {
+ free_flt_nr++;
+ }
+ else
+ {
+ if (free_flt_nr > largest_nr)
+ {
+ largest_nr = free_flt_nr;
+ largest_idx = begin_idx;
+ }
+ free_flt_nr = 0;
+ begin_idx = i + 1;
+ }
+ }
+
+ if (free_flt_nr > largest_nr)
+ {
+ largest_nr = free_flt_nr;
+ largest_idx = begin_idx;
+ }
+
+ if ((!largest_nr) || ((largest_nr + 1) < filter_nr))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ aos_mem_copy(&(sw_rule_tmp[dev_id][i]), &(sw_rule_ent[dev_id][i]),
+ sizeof (isisc_acl_rule_t));
+ }
+ }
+
+ begin_idx = 0;
+ load_idx = largest_idx;
+ rv = _isisc_acl_list_insert(dev_id, &begin_idx, &load_idx,
+ hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+ return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_reorder(a_uint32_t dev_id, isisc_acl_list_t * sw_list)
+{
+ a_uint32_t i, src_idx, dst_idx;
+ sw_error_t rv;
+
+ dst_idx = 0;
+ for (i = 0; i < ISISC_MAX_FILTER;)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ if (sw_rule_ent[dev_id][i].list_pri <= sw_list->list_pri)
+ {
+ rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx,
+ sw_rule_ent[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ break;
+ }
+ }
+ else
+ {
+ i++;
+ }
+ }
+
+ src_idx = 0;
+ rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx, hw_rule_tmp[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ for (; i < ISISC_MAX_FILTER;)
+ {
+ if (ENT_USED & sw_rule_ent[dev_id][i].status)
+ {
+ rv = _isisc_acl_list_insert(dev_id, &i, &dst_idx,
+ sw_rule_ent[dev_id],
+ sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ i++;
+ }
+ }
+
+ return SW_OK;
+}
+
+static void
+_isisc_acl_rule_sync(a_uint32_t dev_id, a_uint32_t flt_idx, a_uint32_t flt_nr)
+{
+ a_uint32_t i, data;
+
+ for (i = flt_idx; i < (flt_idx + flt_nr); i++)
+ {
+ if (aos_mem_cmp
+ (&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+ sizeof (isisc_acl_rule_t)))
+ {
+ SW_GET_FIELD_BY_REG(MAC_RUL_M4, RULE_TYP, data,
+ sw_rule_tmp[dev_id][i].filter.msk[4]);
+ if (data)
+ {
+ _isisc_filter_down_to_hw(dev_id,
+ &(sw_rule_tmp[dev_id][i].filter), i);
+ }
+ else
+ {
+ _isisc_filter_valid_set(dev_id, i, 0);
+ }
+
+ aos_mem_copy(&(sw_rule_ent[dev_id][i]), &(sw_rule_tmp[dev_id][i]),
+ sizeof (isisc_acl_rule_t));
+ _isisc_acl_rule_src_filter_sts_set(dev_id, i,
+ !sw_rule_tmp[dev_id][i].src_flt_dis);
+ }
+ }
+}
+
+static sw_error_t
+_isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+ a_uint32_t i, loc = ISISC_MAX_FILTER;
+ isisc_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((ISISC_MAX_LIST_ID < list_id) || (ISISC_MAX_LIST_PRI < list_pri))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_list = &(sw_list_ent[dev_id][i]);
+ if (ENT_USED & sw_list->status)
+ {
+ if (list_id == sw_list->list_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+ else
+ {
+ loc = i;
+ }
+ }
+
+ if (ISISC_MAX_FILTER == loc)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ sw_list = &(sw_list_ent[dev_id][loc]);
+ aos_mem_zero(sw_list, sizeof (isisc_acl_list_t));
+ sw_list->list_id = list_id;
+ sw_list->list_pri = list_pri;
+ sw_list->status |= ENT_USED;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ isisc_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (0 != sw_list->bind_pts)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (0 != sw_list->rule_nr)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(sw_list, sizeof (isisc_acl_list_t));
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ isisc_acl_list_t *sw_list;
+ isisc_acl_rule_t *sw_rule;
+ a_uint32_t i, free_flt_nr, old_flt_nr, old_flt_idx, new_flt_nr, bind_pts;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if ((0 == rule_nr) || (NULL == rule))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (rule_id != sw_list->rule_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ old_flt_idx = 0;
+ old_flt_nr = 0;
+ free_flt_nr = 0;
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ if (sw_rule->list_id == sw_list->list_id)
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][old_flt_nr]), sw_rule,
+ sizeof (isisc_acl_rule_t));
+ if (!old_flt_nr)
+ {
+ old_flt_idx = i;
+ }
+ old_flt_nr++;
+ }
+ }
+ else
+ {
+ free_flt_nr++;
+ }
+ }
+
+ if (!free_flt_nr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ /* parse rule entry and alloc rule resource */
+ new_flt_nr = old_flt_nr;
+ for (i = 0; i < rule_nr; i++)
+ {
+ rv = _isisc_acl_rule_sw_to_hw(dev_id, &rule[i], hw_rule_tmp[dev_id],
+ &new_flt_nr);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if (free_flt_nr < (new_flt_nr - old_flt_nr))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = old_flt_nr; i < new_flt_nr; i++)
+ {
+ hw_rule_tmp[dev_id][i].status |= ENT_USED;
+ hw_rule_tmp[dev_id][i].list_id = sw_list->list_id;
+ hw_rule_tmp[dev_id][i].list_pri = sw_list->list_pri;
+ bind_pts = sw_list->bind_pts;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, bind_pts,
+ (hw_rule_tmp[dev_id][i].filter.vlu[4]));
+ }
+
+ for (i = 0; i < old_flt_nr; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][old_flt_idx + i]);
+ sw_rule->status &= (~ENT_USED);
+ sw_rule->status |= (ENT_TMP);
+ }
+
+ rv = _isisc_acl_rule_alloc(dev_id, sw_list, new_flt_nr);
+ if (SW_OK != rv)
+ {
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+ rv = _isisc_acl_rule_reorder(dev_id, sw_list);
+ }
+
+ for (i = 0; i < old_flt_nr; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i + old_flt_idx]);
+ sw_rule->status |= (ENT_USED);
+ sw_rule->status &= (~ENT_TMP);
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_acl_rule_sync(dev_id, 0, ISISC_MAX_FILTER);
+ sw_list->rule_nr += rule_nr;
+
+ _isisc_acl_sw_rule_dump("sw rule after add", sw_rule_ent[dev_id]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ isisc_acl_rule_t *sw_rule;
+ isisc_acl_list_t *sw_list;
+ a_uint32_t i, flt_idx = 0, src_idx, dst_idx, del_nr = 0, flt_nr = 0;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->rule_nr < (rule_id + rule_nr))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+ aos_mem_zero(sw_rule_tmp[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if ((ENT_USED & sw_rule->status) && (sw_rule->list_id == list_id))
+ {
+ if (!flt_nr)
+ {
+ flt_idx = i;
+ }
+
+ if ((sw_rule->rule_id >= rule_id)
+ && (sw_rule->rule_id < (rule_id + rule_nr)))
+ {
+ del_nr++;
+ }
+ else
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][flt_idx + flt_nr]), sw_rule,
+ sizeof (isisc_acl_rule_t));
+ }
+ flt_nr++;
+ }
+ }
+
+ if (!del_nr)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ _isisc_acl_sw_rule_dump("hw rule before del", hw_rule_tmp[dev_id]);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ sw_rule = &(hw_rule_tmp[dev_id][flt_idx + i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ break;
+ }
+ }
+
+ if (i != flt_nr)
+ {
+ src_idx = flt_idx + i;
+ dst_idx = flt_idx;
+ rv = _isisc_acl_list_insert(dev_id, &src_idx, &dst_idx,
+ hw_rule_tmp[dev_id], sw_rule_tmp[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ _isisc_acl_rule_sync(dev_id, flt_idx, flt_nr);
+ sw_list->rule_nr -= rule_nr;
+
+ _isisc_acl_sw_rule_dump("sw rule after del", sw_rule_ent[dev_id]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ isisc_acl_rule_t *sw_rule;
+ a_uint32_t flt_nr = 0, i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(hw_rule_tmp[dev_id],
+ ISISC_HW_RULE_TMP_CNT * sizeof (isisc_acl_rule_t));
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+ if (ENT_USED & sw_rule->status)
+ {
+ if ((sw_rule->list_id == list_id) && (sw_rule->rule_id == rule_id))
+ {
+ aos_mem_copy(&(hw_rule_tmp[dev_id][flt_nr]), sw_rule,
+ sizeof (isisc_acl_rule_t));
+ flt_nr++;
+ }
+ }
+ }
+
+ if (!flt_nr)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+ rv = _isisc_acl_rule_hw_to_sw(dev_id, rule, hw_rule_tmp[dev_id], 0, flt_nr);
+ return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_bind(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t ports)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ isisc_acl_rule_t *sw_rule;
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id)
+ && (!(ENT_DEACTIVE & sw_rule->status)))
+ {
+ rv = _isisc_filter_ports_bind(dev_id, i, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+ (sw_rule->filter.vlu[4]));
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t ports;
+ isisc_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->bind_pts & (0x1 << obj_idx))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ ports = (sw_list->bind_pts) | (0x1 << obj_idx);
+ rv = _isisc_acl_rule_bind(dev_id, list_id, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ sw_list->bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t ports;
+ isisc_acl_list_t *sw_list;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < list_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (!(sw_list->bind_pts & (0x1 << obj_idx)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ ports = (sw_list->bind_pts) & (~(0x1UL << obj_idx));
+ rv = _isisc_acl_rule_bind(dev_id, list_id, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ sw_list->bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, ACL_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_UDF_MAX_OFFSET < offset)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_UDF_MAX_OFFSET < length)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ switch (udf_type)
+ {
+ case FAL_ACL_UDF_TYPE_L2:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L2_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L3_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L4:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL0, L4_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L2_SNAP:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L2S_LENGTH, length, reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3_PLUS:
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_OFFSET, offset, reg);
+ SW_SET_REG_BY_FIELD(WIN_RULE_CTL1, L3P_LENGTH, length, reg);
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((FAL_ACL_UDF_TYPE_L2_SNAP == udf_type)
+ || (FAL_ACL_UDF_TYPE_L3_PLUS == udf_type))
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, WIN_RULE_CTL0, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ switch (udf_type)
+ {
+ case FAL_ACL_UDF_TYPE_L2:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L2_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L3_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L4:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL0, L4_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L2_SNAP:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L2S_LENGTH, (*length), reg);
+ break;
+ case FAL_ACL_UDF_TYPE_L3_PLUS:
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_OFFSET, (*offset), reg);
+ SW_GET_FIELD_BY_REG(WIN_RULE_CTL1, L3P_LENGTH, (*length), reg);
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr, a_bool_t active)
+{
+ sw_error_t rv;
+ a_uint32_t i, ports;
+ isisc_acl_list_t *sw_list;
+ isisc_acl_rule_t *sw_rule;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_list = _isisc_acl_list_loc(dev_id, list_id);
+ if (NULL == sw_list)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (sw_list->rule_nr < (rule_id + rule_nr))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == active)
+ {
+ ports = (sw_list->bind_pts);
+ }
+ else
+ {
+ ports = 0;
+ }
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[dev_id][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id)
+ && (rule_id <= sw_rule->rule_id)
+ && ((rule_id + rule_nr) > sw_rule->rule_id))
+ {
+ rv = _isisc_filter_ports_bind(dev_id, i, ports);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, SRC_PT, ports,
+ (sw_rule->filter.vlu[4]));
+
+ if (A_TRUE == active)
+ {
+ sw_rule->status &= (~ENT_DEACTIVE);
+ }
+ else
+ {
+ sw_rule->status |= (ENT_DEACTIVE);
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, regIdx;
+ isisc_acl_rule_t *sw_rule;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_rule = &sw_rule_ent[dev_id][rule_id];
+ if (!(ENT_USED & sw_rule->status))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ regIdx = rule_id >> 5;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ reg |= (0x1 << (rule_id & 0x1F));
+ sw_rule->src_flt_dis = 0;
+ }
+ else if (A_FALSE == enable)
+ {
+ reg &= ~(0x1 << (rule_id & 0x1F));
+ sw_rule->src_flt_dis = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, regIdx;
+ isisc_acl_rule_t *sw_rule;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_rule = &sw_rule_ent[dev_id][rule_id];
+ if (!(ENT_USED & sw_rule->status))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ regIdx = rule_id >> 5;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_FWD_SRC_FILTER_CTL0, regIdx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (reg & (0x1 << (rule_id & 0x1F)))
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+
+HSL_LOCAL sw_error_t
+isisc_acl_list_dump(a_uint32_t dev_id)
+{
+ _isisc_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+isisc_acl_rule_dump(a_uint32_t dev_id)
+{
+ a_uint32_t flt_idx, i;
+ sw_error_t rv;
+ hw_filter_t filter;
+
+ aos_printk("\nisisc_acl_rule_dump:\n");
+
+ for (flt_idx = 0; flt_idx < ISISC_MAX_FILTER; flt_idx++)
+ {
+ aos_mem_zero(&filter, sizeof (hw_filter_t));
+
+ rv = _isisc_filter_up_to_sw(dev_id, &filter, flt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\n%d filter dump:", flt_idx);
+
+ aos_printk("\nhardware content:");
+ aos_printk("\nact:");
+ for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", filter.msk[i]);
+ }
+
+ aos_printk("\nsoftware content:");
+ aos_printk("\nact:");
+ for (i = 0; i < (sizeof (filter.act) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.act[i]);
+ }
+
+ aos_printk("\nvlu:");
+ for (i = 0; i < (sizeof (filter.vlu) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.vlu[i]);
+ }
+
+ aos_printk("\nmsk:");
+ for (i = 0; i < (sizeof (filter.msk) / sizeof (a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", sw_rule_ent[dev_id][flt_idx].filter.msk[i]);
+ }
+
+ aos_printk("\nctl:status[%02d] list_id[%02d] rule_id[%02d] src_flt_dis[%02d]",
+ sw_rule_ent[dev_id][flt_idx].status,
+ sw_rule_ent[dev_id][flt_idx].list_id,
+ sw_rule_ent[dev_id][flt_idx].rule_id,
+ sw_rule_ent[dev_id][flt_idx].src_flt_dis);
+
+ aos_printk("\n\n");
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_acl_reset(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_zero(sw_list_ent[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_list_t));
+
+ aos_mem_zero(sw_rule_ent[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+ return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details Comments:
+ * If the value of list_pri is more small then the priority is more high,
+ * that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t list_pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_list_creat(dev_id, list_id, list_pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_list_destroy(dev_id, list_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_query(dev_id, list_id, rule_id, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL a_uint32_t
+isisc_acl_rule_get_offset(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t rule_id)
+{
+ a_uint32_t i, pos=0;
+ isisc_acl_rule_t *sw_rule;
+
+ for (i = 0; i < ISISC_MAX_FILTER; i++)
+ {
+ sw_rule = &(sw_rule_ent[0][i]);
+
+ if ((ENT_USED & sw_rule->status)
+ && (list_id == sw_rule->list_id) && (sw_rule->rule_id == rule_id)
+ && (!(ENT_DEACTIVE & sw_rule->status)))
+ {
+ pos = i;
+ break;
+
+ }
+ }
+
+ return pos;
+}
+
+
+HSL_LOCAL sw_error_t
+isisc_acl_rule_sync_multi_portmap(a_uint32_t dev_id, a_uint32_t pos, a_uint32_t *act)
+{
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_LIST_ID < pos)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ sw_rule_ent[dev_id][pos].filter.act[1] = act[1];
+ sw_rule_ent[dev_id][pos].filter.act[2] = act[2];
+
+ sw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+ sw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+ hw_rule_tmp[dev_id][pos].filter.act[1] = act[1];
+ hw_rule_tmp[dev_id][pos].filter.act[2] = act[2];
+
+
+ return SW_OK;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[in] offset udf offset
+ * @param[in] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_port_udf_profile_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t offset,
+ a_uint32_t length)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_port_udf_profile_set(dev_id, port_id, udf_type, offset,
+ length);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user define fields profile on a particular port
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] udf_type udf type
+ * @param[out] offset udf offset
+ * @param[out] length udf length
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_port_udf_profile_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_acl_udf_type_t udf_type, a_uint32_t * offset,
+ a_uint32_t * length)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_port_udf_profile_get(dev_id, port_id, udf_type, offset,
+ length);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Active one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_active(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_TRUE);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Deactive one or more rules in an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] rule_nr rule number of this deactive operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_deactive(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_active(dev_id, list_id, rule_id, rule_nr, A_FALSE);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief enable acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_src_filter_sts_set(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_src_filter_sts_set(dev_id, rule_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get the status of acl forward source filter of one rule.
+ * @param[in] dev_id device id
+ * @param[in] rule_id first rule id of this deactive operation in list
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_acl_rule_src_filter_sts_get(a_uint32_t dev_id,
+ a_uint32_t rule_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_acl_rule_src_filter_sts_get(dev_id, rule_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+
+sw_error_t
+isisc_acl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ sw_list_ent[dev_id] =
+ (isisc_acl_list_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+ sizeof (isisc_acl_list_t));
+ if (NULL == sw_list_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_list_ent[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_list_t));
+
+ sw_rule_ent[dev_id] =
+ (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+ sizeof (isisc_acl_rule_t));
+ if (NULL == sw_rule_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_rule_ent[dev_id],
+ ISISC_MAX_FILTER * sizeof (isisc_acl_rule_t));
+
+ hw_rule_tmp[dev_id] =
+ (isisc_acl_rule_t *) aos_mem_alloc(ISISC_HW_RULE_TMP_CNT *
+ sizeof (isisc_acl_rule_t));
+ if (NULL == hw_rule_tmp[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ sw_rule_tmp[dev_id] =
+ (isisc_acl_rule_t *) aos_mem_alloc(ISISC_MAX_FILTER *
+ sizeof (isisc_acl_rule_t));
+ if (NULL == sw_rule_tmp[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+#ifdef ISISC_SW_ENTRY
+ sw_filter_mem = aos_mem_alloc(ISISC_MAX_FILTER * sizeof (hw_filter_t));
+ if (NULL == sw_filter_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(sw_filter_mem, ISISC_MAX_FILTER * sizeof (hw_filter_t));
+#endif
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->acl_list_creat = isisc_acl_list_creat;
+ p_api->acl_list_destroy = isisc_acl_list_destroy;
+ p_api->acl_list_bind = isisc_acl_list_bind;
+ p_api->acl_list_unbind = isisc_acl_list_unbind;
+ p_api->acl_rule_add = isisc_acl_rule_add;
+ p_api->acl_rule_delete = isisc_acl_rule_delete;
+ p_api->acl_rule_query = isisc_acl_rule_query;
+ p_api->acl_status_set = isisc_acl_status_set;
+ p_api->acl_status_get = isisc_acl_status_get;
+ p_api->acl_list_dump = isisc_acl_list_dump;
+ p_api->acl_rule_dump = isisc_acl_rule_dump;
+ p_api->acl_port_udf_profile_set = isisc_acl_port_udf_profile_set;
+ p_api->acl_port_udf_profile_get = isisc_acl_port_udf_profile_get;
+ p_api->acl_rule_active = isisc_acl_rule_active;
+ p_api->acl_rule_deactive = isisc_acl_rule_deactive;
+ p_api->acl_rule_src_filter_sts_set = isisc_acl_rule_src_filter_sts_set;
+ p_api->acl_rule_src_filter_sts_get = isisc_acl_rule_src_filter_sts_get;
+ p_api->acl_rule_get_offset = isisc_acl_rule_get_offset;
+ p_api->acl_rule_sync_multi_portmap = isisc_acl_rule_sync_multi_portmap;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_acl_parse.c b/src/hsl/isisc/isisc_acl_parse.c
new file mode 100644
index 0000000..396678d
--- /dev/null
+++ b/src/hsl/isisc/isisc_acl_parse.c
@@ -0,0 +1,2440 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "isisc_acl.h"
+#include "isisc_reg.h"
+#include "isisc_acl_prv.h"
+
+#define DAH 0x1
+#define SAH 0x2
+#define TAG 0x4
+#define STAG 0x8
+#define CTAG 0x10
+
+typedef sw_error_t(*parse_func_t) (fal_acl_rule_t * sw,
+ hw_filter_t * hw_filter_snap,
+ a_bool_t * b_care);
+
+static a_bool_t
+_isisc_acl_zero_addr(const fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+ return A_TRUE;
+}
+
+static a_bool_t
+_isisc_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu)
+{
+ if (FAL_ACL_FIELD_MASK == op)
+ {
+ if (0 == mask)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_RANGE == op)
+ {
+ if ((0 == val) && (chkvlu == mask))
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_LE == op)
+ {
+ if (chkvlu == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_GE == op)
+ {
+ if (0 == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_NE == op)
+ {
+ return A_TRUE;
+ }
+
+ return A_TRUE;
+}
+
+static sw_error_t
+_isisc_acl_rule_bmac_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_MAC_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_SET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_SET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_SET(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_SET(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_SET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+
+ FIELD_SET(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_SET(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ FIELD_SET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_SET(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ if (0x0 != sw->tagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tagged_val &= sw->tagged_mask;
+ FIELD_SET(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+ FIELD_SET(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ if (0x0 != sw->up_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->up_val &= sw->up_mask;
+ FIELD_SET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+ FIELD_SET(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+ }
+
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+ && (FAL_ACL_FIELD_LE != sw->vid_op)
+ && (FAL_ACL_FIELD_GE != sw->vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->vid_op)
+ {
+ sw->vid_val &= sw->vid_mask;
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ FIELD_SET(MAC_RUL_M4, VIDMSK, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->vid_op)
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, 0);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, sw->vid_val);
+ }
+ else
+ {
+ FIELD_SET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_SET(MAC_RUL_M3, VLANIDM, 0xfff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ if (0x0 != sw->cfi_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->cfi_val &= sw->cfi_mask;
+ FIELD_SET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+ FIELD_SET(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ehmac_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+ a_bool_t da_h = A_FALSE, sa_h = A_FALSE;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_EHMAC_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->dest_mac_mask.uc[i])
+ {
+ da_h = A_TRUE;
+ break;
+ }
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->src_mac_mask.uc[i])
+ {
+ sa_h = A_TRUE;
+ break;
+ }
+ }
+ }
+
+ /* if sa_h and da_h both are true need't process mac address fileds */
+ if ((A_TRUE == da_h) && ((A_TRUE == sa_h)))
+ {
+ da_h = A_FALSE;
+ sa_h = A_FALSE;
+ }
+
+ if (A_TRUE == da_h)
+ {
+ FIELD_SET(EHMAC_RUL_V3, DA_EN, 1);
+
+ if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_SET(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ }
+ }
+
+ if (A_TRUE == sa_h)
+ {
+ if (A_TRUE != _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V0, DAV_BYTE5, sw->src_mac_val.uc[5]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_SET(EHMAC_RUL_V1, DAV_BYTE1, sw->src_mac_val.uc[1]);
+
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M0, DAM_BYTE5, sw->src_mac_mask.uc[5]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_SET(EHMAC_RUL_M1, DAM_BYTE1, sw->src_mac_mask.uc[1]);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ FIELD_SET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_SET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+ FIELD_SET(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_SET(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ FIELD_SET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_SET(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ }
+
+ /* Process Stag Fields */
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+ {
+ if (0x0 != sw->stagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stagged_val &= sw->stagged_mask;
+ FIELD_SET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+ FIELD_SET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+ }
+
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_LE != sw->stag_vid_op)
+ && (FAL_ACL_FIELD_GE != sw->stag_vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+ sw->stag_vid_mask, 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->stag_vid_op)
+ {
+ sw->stag_vid_val &= sw->stag_vid_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+ FIELD_SET(EHMAC_RUL_V3, SVIDMSK, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->stag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->stag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, 0);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_val);
+
+ }
+ else
+ {
+ FIELD_SET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_VIDM, 0xfff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+ {
+ if (0x0 != sw->stag_pri_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stag_pri_val &= sw->stag_pri_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+ {
+ if (0x0 != sw->stag_dei_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->stag_dei_val &= sw->stag_dei_mask;
+ FIELD_SET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+ FIELD_SET(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+ }
+
+ /* Process Ctag Fields */
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+ {
+ if (0x0 != sw->ctagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctagged_val &= sw->ctagged_mask;
+ FIELD_SET(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+ FIELD_SET(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+ }
+
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_LE != sw->ctag_vid_op)
+ && (FAL_ACL_FIELD_GE != sw->ctag_vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+ sw->ctag_vid_mask, 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 0);
+ if (FAL_ACL_FIELD_MASK == sw->ctag_vid_op)
+ {
+ sw->ctag_vid_val &= sw->ctag_vid_mask;
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+ FIELD_SET(EHMAC_RUL_M4, CVIDMSK, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->ctag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_mask >> 8));
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->ctag_vid_op)
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, 0);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, 0);
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, (sw->ctag_vid_val >> 8));
+
+ }
+ else
+ {
+ FIELD_SET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_SET(EHMAC_RUL_V3, CTAG_VIDHV, (sw->ctag_vid_val >> 8));
+ FIELD_SET(EHMAC_RUL_M2, CTAG_VIDLM, 0xff);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_VIDHM, 0xf);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+ {
+ if (0x0 != sw->ctag_pri_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctag_pri_val &= sw->ctag_pri_mask;
+ FIELD_SET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+ {
+ if (0x0 != sw->ctag_cfi_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ctag_cfi_val &= sw->ctag_cfi_mask;
+ FIELD_SET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+ FIELD_SET(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static void
+_isisc_acl_rule_mac_preparse(fal_acl_rule_t * sw, a_bool_t * b_mac,
+ a_bool_t * eh_mac)
+{
+ a_uint32_t bm = 0, i, tmp;
+
+ *b_mac = A_FALSE;
+ *eh_mac = A_FALSE;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->dest_mac_mask.uc[i])
+ {
+ bm |= DAH;
+ break;
+ }
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ for (i = 0; i < 3; i++)
+ {
+ if (sw->src_mac_mask.uc[i])
+ {
+ bm |= SAH;
+ break;
+ }
+ }
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ tmp |= ((sw->tagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ tmp |= ((sw->up_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ tmp |= ((sw->cfi_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= TAG;
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+ {
+ tmp |= ((sw->stagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+ {
+ tmp |= ((sw->stag_pri_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+ {
+ tmp |= ((sw->stag_dei_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+ {
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->stag_vid_op, sw->stag_vid_val,
+ sw->stag_vid_mask, 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= STAG;
+ }
+
+ tmp = 0;
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+ {
+ tmp |= ((sw->ctagged_mask & 0x1) << 16);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+ {
+ tmp |= ((sw->ctag_pri_mask & 0x7) << 13);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+ {
+ tmp |= ((sw->ctag_cfi_mask & 0x1) << 12);
+ }
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+ {
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->ctag_vid_op, sw->ctag_vid_val,
+ sw->ctag_vid_mask, 0xfff))
+ {
+ tmp |= 0xfff;
+ }
+ }
+ if (tmp)
+ {
+ bm |= CTAG;
+ }
+
+ if ((bm & CTAG) || (bm & STAG))
+ {
+ *eh_mac = A_TRUE;
+ }
+
+ if ((bm & TAG) || ((bm & DAH) && (bm & SAH)))
+ {
+ *b_mac = A_TRUE;
+ }
+}
+
+static sw_error_t
+_isisc_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_IP4_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ FIELD_SET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+ FIELD_SET(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ FIELD_SET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+ FIELD_SET(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+ {
+ if (0x0 != sw->src_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->src_ip4_val &= sw->src_ip4_mask;
+ hw->vlu[1] = sw->src_ip4_val;
+ hw->msk[1] = sw->src_ip4_mask;
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+ {
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->dest_ip4_val &= sw->dest_ip4_mask;
+ hw->vlu[0] = sw->dest_ip4_val;
+ hw->msk[0] = sw->dest_ip4_mask;
+ }
+
+ if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, 0);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP4_RUL_M3, IP4SPORTM, 0xffff);
+ }
+ }
+
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ FIELD_SET(IP4_RUL_M3, IP4DPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, 0);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP4_RUL_M2, IP4DPORTM, 0xffff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ {
+ if (0x0 != sw->icmp_type_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+ sw->icmp_type_val &= sw->icmp_type_mask;
+ FIELD_SET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+ FIELD_SET(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+ {
+ if (0x0 != sw->icmp_code_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP4_RUL_V3, ICMP_EN, 1);
+
+ sw->icmp_code_val &= sw->icmp_code_mask;
+ FIELD_SET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+ FIELD_SET(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+ {
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tcp_flag_val &= sw->tcp_flag_mask;
+ FIELD_SET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+ FIELD_SET(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_RIPV1))
+ {
+ if (0x0 != sw->ripv1_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ripv1_val &= sw->ripv1_mask;
+ FIELD_SET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+ FIELD_SET(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV4))
+ {
+ if (0x0 != sw->dhcpv4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dhcpv4_val &= sw->dhcpv4_mask;
+ FIELD_SET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+ FIELD_SET(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_IP6R1_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_IP6R2_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_IP6R3_FILTER);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+ {
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip6_lable_val &= sw->ip6_lable_mask;
+ FIELD_SET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+ FIELD_SET(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+ FIELD_SET(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16));
+ FIELD_SET(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16));
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ FIELD_SET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+ FIELD_SET(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ FIELD_SET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+ FIELD_SET(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+ }
+
+ if ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ && ((FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ || (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isisc_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM_EN, 1);
+
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, 0);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val);
+
+ }
+ else
+ {
+ FIELD_SET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_SET(IP6_RUL3_M3, IP6SPORTM, 0xffff);
+ }
+ }
+
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _isisc_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 0);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ FIELD_SET(IP6_RUL3_M3, IP6DPORTM_EN, 1);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, 0);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val);
+ }
+ else
+ {
+ FIELD_SET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_SET(IP6_RUL3_M2, IP6DPORTM, 0xffff);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ {
+ if (0x0 != sw->icmp_type_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+ sw->icmp_type_val &= sw->icmp_type_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+ FIELD_SET(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+ {
+ if (0x0 != sw->icmp_code_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ FIELD_SET(IP6_RUL3_V3, ICMP6_EN, 1);
+
+ sw->icmp_code_val &= sw->icmp_code_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+ FIELD_SET(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+ {
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tcp_flag_val &= sw->tcp_flag_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+ FIELD_SET(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_DHCPV6))
+ {
+ if (0x0 != sw->dhcpv6_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dhcpv6_val &= sw->dhcpv6_mask;
+ FIELD_SET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+ FIELD_SET(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_udf_parse(fal_acl_rule_t * sw,
+ hw_filter_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+
+ FIELD_SET(MAC_RUL_M4, RULE_TYP, ISISC_UDF_FILTER);
+
+ if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+ {
+ if (FAL_ACL_RULE_UDF == sw->rule_type)
+ {
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+ *b_care = A_TRUE;
+ }
+ return SW_OK;
+ }
+
+ if (ISISC_MAX_UDF_LENGTH < sw->udf_len)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *b_care = A_TRUE;
+ for (i = 0; i < sw->udf_len; i++)
+ {
+ hw->vlu[3 - i / 4] |=
+ ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+ hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * (i % 4)));
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ FIELD_SET(MAC_RUL_V4, RULE_INV, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ hw_filter_t * hw)
+{
+ fal_pbmp_t des_pts;
+
+ aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+ /* FAL_ACL_ACTION_PERMIT need't process */
+
+ /* we should ignore any other action flags when DENY bit is settd. */
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x7);
+ return SW_OK;
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU)))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x3);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+ {
+ FIELD_SET(ACL_RSLT2, FWD_CMD, 0x1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+ {
+ FIELD_SET(ACL_RSLT2, MIRR_EN, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ FIELD_SET(ACL_RSLT2, DES_PORT_EN, 1);
+
+ des_pts = (sw->ports >> 3) & 0xf;
+ FIELD_SET(ACL_RSLT2, DES_PORT1, des_pts);
+
+ des_pts = sw->ports & 0x7;
+ FIELD_SET(ACL_RSLT1, DES_PORT0, des_pts);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+ {
+ FIELD_SET(ACL_RSLT1, PRI_QU_EN, 1);
+ FIELD_SET(ACL_RSLT1, PRI_QU, sw->queue);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+ {
+ FIELD_SET(ACL_RSLT1, DSCPV, sw->dscp);
+ FIELD_SET(ACL_RSLT1, DSCP_REMAP, 1);
+ }
+
+ FIELD_SET(ACL_RSLT0, STAGVID, sw->stag_vid);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+ {
+ FIELD_SET(ACL_RSLT1, TRANS_SVID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+ {
+ FIELD_SET(ACL_RSLT0, STAGPRI, sw->stag_pri);
+ FIELD_SET(ACL_RSLT1, STAG_PRI_REMAP, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+ {
+ FIELD_SET(ACL_RSLT0, STAGDEI, sw->stag_dei);
+ FIELD_SET(ACL_RSLT1, STAG_DEI_CHG, 1);
+ }
+
+ FIELD_SET(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+ {
+ FIELD_SET(ACL_RSLT1, TRANS_CVID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+ {
+ FIELD_SET(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+ FIELD_SET(ACL_RSLT1, CTAG_PRI_REMAP, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+ {
+ FIELD_SET(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+ FIELD_SET(ACL_RSLT1, CTAG_CFI_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+ {
+ FIELD_SET(ACL_RSLT1, LOOK_VID_CHG, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICER_EN))
+ {
+ FIELD_SET(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+ FIELD_SET(ACL_RSLT2, POLICER_EN, 1);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_ARP_EN))
+ {
+ FIELD_SET(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+ FIELD_SET(ACL_RSLT1, ARP_PTR_EN, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_WCMP_EN))
+ {
+ FIELD_SET(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+ FIELD_SET(ACL_RSLT1, WCMP_EN, 1);
+ FIELD_SET(ACL_RSLT1, ARP_PTR_EN, 1);
+ }
+
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x0);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+ {
+ if (FAL_ACL_POLICY_ROUTE == sw->policy_fwd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ else if (FAL_ACL_POLICY_SNAT == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x1);
+ }
+ else if (FAL_ACL_POLICY_DNAT == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x2);
+ }
+ else if (FAL_ACL_POLICY_RESERVE == sw->policy_fwd)
+ {
+ FIELD_SET(ACL_RSLT1, FORCE_L3_MODE, 0x3);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+ {
+ FIELD_SET(ACL_RSLT2, EG_BYPASS, 1);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+ {
+ FIELD_SET(ACL_RSLT2, TRIGGER_INTR, 1);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_bmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en;
+
+ /* destnation mac address */
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_GET(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5]);
+ FIELD_GET(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0]);
+ FIELD_GET(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1]);
+
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_GET(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ FIELD_GET(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0]);
+ FIELD_GET(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1]);
+ if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ /* source mac address */
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2]);
+ FIELD_GET(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_GET(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_GET(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2]);
+ FIELD_GET(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_GET(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_GET(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+ if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ /* ethernet type */
+ FIELD_GET(MAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_GET(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet tagged */
+ FIELD_GET(MAC_RUL_M4, TAGGEDV, sw->tagged_val);
+ FIELD_GET(MAC_RUL_M4, TAGGEDM, sw->tagged_mask);
+ if (0x0 != sw->tagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+ }
+
+ /* vlan priority */
+ FIELD_GET(MAC_RUL_V3, VLANPRIV, sw->up_val);
+ FIELD_GET(MAC_RUL_M3, VLANPRIM, sw->up_mask);
+ if (0x0 != sw->up_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+ }
+
+ /* vlanid */
+ FIELD_GET(MAC_RUL_V3, VLANIDV, sw->vid_val);
+ FIELD_GET(MAC_RUL_M3, VLANIDM, sw->vid_mask);
+ FIELD_GET(MAC_RUL_M4, VIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+ (a_uint32_t) sw->vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+ }
+
+ /* vlan cfi */
+ FIELD_GET(MAC_RUL_V3, VLANCFIV, sw->cfi_val);
+ FIELD_GET(MAC_RUL_M3, VLANCFIM, sw->cfi_mask);
+ if (0x0 != sw->cfi_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ehmac_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i, mask_en, data;
+
+ FIELD_GET(EHMAC_RUL_V3, DA_EN, data);
+ if (data)
+ {
+ for (i = 2; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+ sw->dest_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ sw->dest_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+ sw->dest_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+ }
+
+ if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5]);
+
+ FIELD_GET(EHMAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5]);
+
+ if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+ }
+ else
+ {
+ for (i = 2; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] = ((hw->vlu[0]) >> ((5 - i) << 3)) & 0xff;
+ sw->src_mac_mask.uc[i] = ((hw->msk[0]) >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ sw->src_mac_val.uc[i] = ((hw->vlu[1]) >> ((1 - i) << 3)) & 0xff;
+ sw->src_mac_mask.uc[i] = ((hw->msk[1]) >> ((1 - i) << 3)) & 0xff;
+ }
+
+ if (A_FALSE == _isisc_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ FIELD_GET(EHMAC_RUL_V2, SAV_BYTE3, sw->dest_mac_val.uc[3]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE4, sw->dest_mac_val.uc[4]);
+ FIELD_GET(EHMAC_RUL_V1, SAV_BYTE5, sw->dest_mac_val.uc[5]);
+
+ FIELD_GET(EHMAC_RUL_M2, SAM_BYTE3, sw->dest_mac_mask.uc[3]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE4, sw->dest_mac_mask.uc[4]);
+ FIELD_GET(EHMAC_RUL_M1, SAM_BYTE5, sw->dest_mac_mask.uc[5]);
+ if (A_FALSE == _isisc_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+ }
+
+ /* ethernet type */
+ FIELD_GET(EHMAC_RUL_V3, ETHTYPV, sw->ethtype_val);
+ FIELD_GET(EHMAC_RUL_M3, ETHTYPM, sw->ethtype_mask);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet stagged */
+ FIELD_GET(EHMAC_RUL_V3, STAGGEDV, sw->stagged_val);
+ FIELD_GET(EHMAC_RUL_V3, STAGGEDM, sw->stagged_mask);
+ if (0x0 != sw->stagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+ }
+
+ /* stag vid */
+ FIELD_GET(EHMAC_RUL_V2, STAG_VIDV, sw->stag_vid_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_VIDM, sw->stag_vid_mask);
+ FIELD_GET(EHMAC_RUL_V3, SVIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->stag_vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->stag_vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->stag_vid_op, (a_uint32_t) sw->stag_vid_val,
+ (a_uint32_t) sw->stag_vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+ }
+
+ /* stag priority */
+ FIELD_GET(EHMAC_RUL_V2, STAG_PRIV, sw->stag_pri_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_PRIM, sw->stag_pri_mask);
+ if (0x0 != sw->stag_pri_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+ }
+
+ /* stag dei */
+ FIELD_GET(EHMAC_RUL_V2, STAG_DEIV, sw->stag_dei_val);
+ FIELD_GET(EHMAC_RUL_M2, STAG_DEIM, sw->stag_dei_mask);
+ if (0x0 != sw->stag_dei_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+ }
+
+ /* packet ctagged */
+ FIELD_GET(EHMAC_RUL_M4, CTAGGEDV, sw->ctagged_val);
+ FIELD_GET(EHMAC_RUL_M4, CTAGGEDM, sw->ctagged_mask);
+ if (0x0 != sw->ctagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+ }
+
+ /* ctag vid */
+ FIELD_GET(EHMAC_RUL_V2, CTAG_VIDLV, sw->ctag_vid_val);
+ FIELD_GET(EHMAC_RUL_V3, CTAG_VIDHV, data);
+ sw->ctag_vid_val |= (data << 8);
+ FIELD_GET(EHMAC_RUL_M2, CTAG_VIDLM, sw->ctag_vid_mask);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_VIDHM, data);
+ sw->ctag_vid_mask |= (data << 8);
+
+ FIELD_GET(EHMAC_RUL_M4, CVIDMSK, mask_en);
+ if (mask_en)
+ {
+ sw->ctag_vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->ctag_vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->ctag_vid_op, (a_uint32_t) sw->ctag_vid_val,
+ (a_uint32_t) sw->ctag_vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+ }
+
+ /* ctag priority */
+ FIELD_GET(EHMAC_RUL_V3, CTAG_PRIV, sw->ctag_pri_val);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_PRIM, sw->ctag_pri_mask);
+ if (0x0 != sw->ctag_pri_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+ }
+
+ /* ctag dei */
+ FIELD_GET(EHMAC_RUL_V3, CTAG_CFIV, sw->ctag_cfi_val);
+ FIELD_GET(EHMAC_RUL_M3, CTAG_CFIM, sw->ctag_cfi_mask);
+ if (0x0 != sw->ctag_cfi_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip4_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en, icmp_en;
+
+ sw->dest_ip4_val = hw->vlu[0];
+ sw->dest_ip4_mask = hw->msk[0];
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+
+ sw->src_ip4_val = hw->vlu[1];
+ sw->src_ip4_mask = hw->msk[1];
+ if (0x0 != sw->src_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val);
+ FIELD_GET(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val);
+ FIELD_GET(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ FIELD_GET(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val);
+ FIELD_GET(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask);
+ FIELD_GET(IP4_RUL_M3, IP4DPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ FIELD_GET(IP4_RUL_V3, ICMP_EN, icmp_en);
+ if (icmp_en)
+ {
+ FIELD_GET(IP4_RUL_V3, IP4ICMPTYPV, sw->icmp_type_val);
+ FIELD_GET(IP4_RUL_M3, IP4ICMPTYPM, sw->icmp_type_mask);
+ if (0x0 != sw->icmp_type_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4ICMPCODEV, sw->icmp_code_val);
+ FIELD_GET(IP4_RUL_M3, IP4ICMPCODEM, sw->icmp_code_mask);
+ if (0x0 != sw->icmp_code_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+ }
+ }
+ else
+ {
+ FIELD_GET(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val);
+ FIELD_GET(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask);
+ FIELD_GET(IP4_RUL_M3, IP4SPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4TCPFLAGV, sw->tcp_flag_val);
+ FIELD_GET(IP4_RUL_M3, IP4TCPFLAGM, sw->tcp_flag_mask);
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4RIPV, sw->ripv1_val);
+ FIELD_GET(IP4_RUL_M3, IP4RIPM, sw->ripv1_mask);
+ if (0x0 != sw->ripv1_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_RIPV1);
+ }
+
+ FIELD_GET(IP4_RUL_V3, IP4DHCPV, sw->dhcpv4_val);
+ FIELD_GET(IP4_RUL_M3, IP4DHCPM, sw->dhcpv4_mask);
+ if (0x0 != sw->dhcpv4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV4);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t mask_en, icmp6_en, tmp;
+
+ FIELD_GET(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val);
+ FIELD_GET(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ FIELD_GET(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val);
+ FIELD_GET(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ FIELD_GET(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val);
+ FIELD_GET(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask);
+ FIELD_GET(IP6_RUL3_M3, IP6DPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, ICMP6_EN, icmp6_en);
+ if (icmp6_en)
+ {
+ FIELD_GET(IP6_RUL3_V3, IP6ICMPTYPV, sw->icmp_type_val);
+ FIELD_GET(IP6_RUL3_M3, IP6ICMPTYPM, sw->icmp_type_mask);
+ if (0x0 != sw->icmp_type_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6ICMPCODEV, sw->icmp_code_val);
+ FIELD_GET(IP6_RUL3_M3, IP6ICMPCODEM, sw->icmp_code_mask);
+ if (0x0 != sw->icmp_code_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+ }
+ }
+ else
+ {
+ FIELD_GET(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val);
+ FIELD_GET(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask);
+ FIELD_GET(IP6_RUL3_M3, IP6SPORTM_EN, mask_en);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _isisc_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ }
+
+ FIELD_GET(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val);
+ FIELD_GET(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask);
+
+ FIELD_GET(IP6_RUL3_V2, IP6LABEL2V, tmp);
+ sw->ip6_lable_val |= (tmp << 16);
+ FIELD_GET(IP6_RUL3_M2, IP6LABEL2M, tmp);
+ sw->ip6_lable_mask |= (tmp << 16);
+
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6TCPFLAGV, sw->tcp_flag_val);
+ FIELD_GET(IP6_RUL3_M3, IP6TCPFLAGM, sw->tcp_flag_mask);
+ if (0x0 != sw->tcp_flag_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+ }
+
+ FIELD_GET(IP6_RUL3_V3, IP6DHCPV, sw->dhcpv6_val);
+ FIELD_GET(IP6_RUL3_M3, IP6DHCPM, sw->dhcpv6_mask);
+ if (0x0 != sw->dhcpv6_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_DHCPV6);
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, mask_en);
+ if (mask_en)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_udf_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t i;
+
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+ /* for ISIS UDF type, length and offset no meanging in rules, just set default value */
+ sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+ sw->udf_len = 16;
+ sw->udf_offset = 0;
+
+ for (i = 0; i < ISISC_MAX_UDF_LENGTH; i++)
+ {
+ sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ }
+
+ FIELD_GET(MAC_RUL_V4, RULE_INV, i);
+ if (i)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_acl_rule_action_reparse(fal_acl_rule_t * sw, const hw_filter_t * hw)
+{
+ a_uint32_t data;
+
+ sw->action_flg = 0;
+
+ FIELD_GET(ACL_RSLT2, DES_PORT_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+ FIELD_GET(ACL_RSLT1, DES_PORT0, sw->ports);
+ FIELD_GET(ACL_RSLT2, DES_PORT1, data);
+ sw->ports |= (data << 3);
+ }
+
+ FIELD_GET(ACL_RSLT2, FWD_CMD, data);
+ if (0x7 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_DENY);
+ }
+ else if (0x3 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+ }
+ else if (0x1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+ }
+ else
+ {
+ /* need't set permit action */
+ }
+
+ FIELD_GET(ACL_RSLT2, MIRR_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+ }
+
+ FIELD_GET(ACL_RSLT1, PRI_QU_EN, data);
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+ FIELD_GET(ACL_RSLT1, PRI_QU, sw->queue);
+ }
+
+ FIELD_GET(ACL_RSLT1, DSCP_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+ FIELD_GET(ACL_RSLT1, DSCPV, sw->dscp);
+ }
+
+ FIELD_GET(ACL_RSLT0, STAGVID, sw->stag_vid);
+
+ FIELD_GET(ACL_RSLT1, TRANS_SVID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+ }
+
+ FIELD_GET(ACL_RSLT1, STAG_PRI_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+ FIELD_GET(ACL_RSLT0, STAGPRI, sw->stag_pri);
+ }
+
+ FIELD_GET(ACL_RSLT1, STAG_DEI_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+ FIELD_GET(ACL_RSLT0, STAGDEI, sw->stag_dei);
+ }
+
+ FIELD_GET(ACL_RSLT0, CTAGVID, sw->ctag_vid);
+
+ FIELD_GET(ACL_RSLT1, TRANS_CVID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+ }
+
+ FIELD_GET(ACL_RSLT1, CTAG_PRI_REMAP, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+ FIELD_GET(ACL_RSLT0, CTAGPRI, sw->ctag_pri);
+ }
+
+ FIELD_GET(ACL_RSLT1, CTAG_CFI_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+ FIELD_GET(ACL_RSLT0, CTAGCFI, sw->ctag_cfi);
+ }
+
+ FIELD_GET(ACL_RSLT1, LOOK_VID_CHG, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+ }
+
+ FIELD_GET(ACL_RSLT2, POLICER_EN, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICER_EN);
+ FIELD_GET(ACL_RSLT2, POLICER_PTR, sw->policer_ptr);
+ }
+
+ FIELD_GET(ACL_RSLT1, ARP_PTR_EN, data);
+ if (data)
+ {
+ FIELD_GET(ACL_RSLT1, WCMP_EN, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_WCMP_EN);
+ FIELD_GET(ACL_RSLT1, ARP_PTR, sw->wcmp_ptr);
+ }
+ else
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_ARP_EN);
+ FIELD_GET(ACL_RSLT1, ARP_PTR, sw->arp_ptr);
+ }
+ }
+
+ FIELD_GET(ACL_RSLT1, FORCE_L3_MODE, data);
+ if ((0 != data) && (3 != data))
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+ if (0x1 == data)
+ {
+ sw->policy_fwd = FAL_ACL_POLICY_SNAT;
+ }
+ else
+ {
+ sw->policy_fwd = FAL_ACL_POLICY_DNAT;
+ }
+ }
+
+ FIELD_GET(ACL_RSLT2, EG_BYPASS, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+ }
+
+ FIELD_GET(ACL_RSLT2, TRIGGER_INTR, data);
+ if (data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ isisc_acl_rule_t * hw_rule_snap, a_uint32_t * idx)
+{
+ sw_error_t rv;
+ a_uint32_t tmp_idx, i, b_rule[7] = { 0 };
+ parse_func_t ptr[7] = { NULL };
+ a_bool_t b_care, b_mac, eh_mac;
+
+ rv = _isisc_acl_action_parse(dev_id, sw, &(hw_rule_snap[*idx].filter));
+ SW_RTN_ON_ERROR(rv);
+
+ ptr[0] = _isisc_acl_rule_udf_parse;
+ _isisc_acl_rule_mac_preparse(sw, &b_mac, &eh_mac);
+
+ /* ehmac rule must be parsed bofore mac rule.
+ it's important for reparse process */
+ if (A_TRUE == eh_mac)
+ {
+ ptr[1] = _isisc_acl_rule_ehmac_parse;
+ }
+
+ if (A_TRUE == b_mac)
+ {
+ ptr[2] = _isisc_acl_rule_bmac_parse;
+ }
+
+ if ((A_FALSE == b_mac) && (A_FALSE == eh_mac))
+ {
+ ptr[2] = _isisc_acl_rule_bmac_parse;
+ }
+
+ if (FAL_ACL_RULE_MAC == sw->rule_type)
+ {
+ }
+ else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ ptr[3] = _isisc_acl_rule_ip4_parse;
+ }
+ else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ ptr[4] = _isisc_acl_rule_ip6r1_parse;
+ ptr[5] = _isisc_acl_rule_ip6r2_parse;
+ ptr[6] = _isisc_acl_rule_ip6r3_parse;
+ }
+ else if (FAL_ACL_RULE_UDF == sw->rule_type)
+ {
+ ptr[1] = NULL;
+ ptr[2] = NULL;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ tmp_idx = *idx;
+ for (i = 0; i < 7; i++)
+ {
+ if (ptr[i])
+ {
+ if (ISISC_HW_RULE_TMP_CNT <= tmp_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ rv = ptr[i] (sw, &(hw_rule_snap[tmp_idx].filter), &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_rule[i] = 1;
+ }
+ }
+ }
+
+ if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ if ((!b_rule[4]) && (!b_rule[5]) && (!b_rule[6]))
+ {
+ tmp_idx++;
+ }
+ }
+
+ if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ if (!b_rule[3])
+ {
+ tmp_idx++;
+ }
+ }
+
+ if (tmp_idx == *idx)
+ {
+ /* set type start & end */
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ (*idx)++;
+ }
+ else
+ {
+ if (1 == (tmp_idx - *idx))
+ {
+ if (FAL_ACL_COMBINED_START == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else if (FAL_ACL_COMBINED_CONTINUE == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else if (FAL_ACL_COMBINED_END == sw->combined)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_STARTEND,
+ (hw_rule_snap[*idx].filter.msk[4]));
+ }
+ }
+ else
+ {
+ for (i = *idx; i < tmp_idx; i++)
+ {
+ if (i == *idx)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_START,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ else if (i == (tmp_idx - 1))
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_END,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_M4, RULE_VALID, FLT_CONTINUE,
+ (hw_rule_snap[i].filter.msk[4]));
+ }
+ aos_mem_copy(&(hw_rule_snap[i].filter.act[0]),
+ &(hw_rule_snap[*idx].filter.act[0]),
+ sizeof (hw_rule_snap[*idx].filter.act));
+ }
+ }
+ *idx = tmp_idx;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ isisc_acl_rule_t * hw_rule_snap, a_uint32_t idx,
+ a_uint32_t ent_nr)
+{
+ a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+ sw_error_t rv;
+ a_uint32_t i, flt_typ;
+ hw_filter_t *hw;
+
+ rv = _isisc_acl_rule_action_reparse(sw, &(hw_rule_snap[idx].filter));
+ SW_RTN_ON_ERROR(rv);
+
+ sw->rule_type = FAL_ACL_RULE_UDF;
+ for (i = 0; i < ent_nr; i++)
+ {
+ hw = &(hw_rule_snap[idx + i].filter);
+ FIELD_GET(MAC_RUL_M4, RULE_TYP, flt_typ);
+
+ if (ISISC_UDF_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_udf_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (ISISC_MAC_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_bmac_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_mac = A_TRUE;
+ }
+ else if (ISISC_EHMAC_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_ehmac_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_mac = A_TRUE;
+ }
+ else if (ISISC_IP4_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_ip4_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip4 = A_TRUE;
+ }
+ else if (ISISC_IP6R1_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_ip6r1_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (ISISC_IP6R2_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_ip6r2_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (ISISC_IP6R3_FILTER == flt_typ)
+ {
+ rv = _isisc_acl_rule_ip6r3_reparse(sw, hw);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else
+ {
+ /* ignore fill gap filters */
+ }
+ }
+
+ if (A_TRUE == b_mac)
+ {
+ sw->rule_type = FAL_ACL_RULE_MAC;
+ }
+
+ if (A_TRUE == b_ip4)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP4;
+ }
+
+ if (A_TRUE == b_ip6)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP6;
+ }
+
+ return SW_OK;
+}
diff --git a/src/hsl/isisc/isisc_acl_prv.h b/src/hsl/isisc/isisc_acl_prv.h
new file mode 100644
index 0000000..c107970
--- /dev/null
+++ b/src/hsl/isisc/isisc_acl_prv.h
@@ -0,0 +1,97 @@
+
+
+typedef struct
+{
+ a_uint8_t status;
+ a_uint8_t list_id;
+ a_uint8_t list_pri;
+ a_uint8_t rule_nr;
+ fal_pbmp_t bind_pts;
+} isisc_acl_list_t;
+
+
+typedef struct
+{
+ a_uint32_t vlu[5];
+ a_uint32_t msk[5];
+ a_uint32_t act[3];
+} hw_filter_t;
+
+
+typedef struct
+{
+ a_uint8_t status;
+ a_uint8_t list_id;
+ a_uint8_t list_pri;
+ a_uint8_t rule_id;
+ hw_filter_t filter;
+ a_uint32_t src_flt_dis; /* src filter disabled */
+} isisc_acl_rule_t;
+
+
+#define ENT_USED 0x1
+#define ENT_TMP 0x2
+#define ENT_DEACTIVE 0x4
+
+#define FLT_START 0x0
+#define FLT_CONTINUE 0x1
+#define FLT_END 0x2
+#define FLT_STARTEND 0x3
+
+
+#define ISISC_MAC_FILTER 1
+#define ISISC_IP4_FILTER 2
+#define ISISC_IP6R1_FILTER 3
+#define ISISC_IP6R2_FILTER 4
+#define ISISC_IP6R3_FILTER 5
+#define ISISC_UDF_FILTER 6
+#define ISISC_EHMAC_FILTER 7
+
+
+#define ISISC_MAX_UDF_OFFSET 31
+#define ISISC_MAX_UDF_LENGTH 16
+
+
+#define ISISC_FILTER_VLU_OP 0x0
+#define ISISC_FILTER_MSK_OP 0x1
+#define ISISC_FILTER_ACT_OP 0x2
+
+
+
+//#define ISISC_MAX_FILTER 8
+#define ISISC_MAX_FILTER 96
+#define ISISC_RULE_FUNC_ADDR 0x0400
+#define ISISC_HW_RULE_TMP_CNT (ISISC_MAX_FILTER + 4)
+
+#define ISISC_MAX_LIST_ID 255
+#define ISISC_MAX_LIST_PRI 255
+
+#define ISISC_UDF_MAX_LENGTH 15
+#define ISISC_UDF_MAX_OFFSET 31
+
+#define WIN_RULE_CTL0_ADDR 0x218
+#define WIN_RULE_CTL1_ADDR 0x234
+
+
+#define ISISC_FILTER_VLU_ADDR 0x58000
+#define ISISC_FILTER_MSK_ADDR 0x59000
+#define ISISC_FILTER_ACT_ADDR 0x5a000
+
+
+#define FIELD_SET(reg, field, val) \
+ SW_REG_SET_BY_FIELD_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+#define FIELD_GET(reg, field, val) \
+ SW_FIELD_GET_BY_REG_U32(hw->vlu[reg], val, reg##_##field##_BOFFSET, \
+ reg##_##field##_BLEN)
+
+
+sw_error_t
+_isisc_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t * idx);
+
+
+sw_error_t
+_isisc_acl_rule_hw_to_sw(a_uint32_t dev_id, fal_acl_rule_t * sw, isisc_acl_rule_t * hw_filter_snap, a_uint32_t idx, a_uint32_t ent_nr);
+
+
diff --git a/src/hsl/isisc/isisc_cosmap.c b/src/hsl/isisc/isisc_cosmap.c
new file mode 100644
index 0000000..4cf0fe8
--- /dev/null
+++ b/src/hsl/isisc/isisc_cosmap.c
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_cosmap ISISC_COSMAP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_cosmap.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_DSCP 63
+#define ISISC_MAX_UP 7
+#define ISISC_MAX_PRI 7
+#define ISISC_MAX_DP 1
+#define ISISC_MAX_QUEUE 3
+#define ISISC_MAX_EH_QUEUE 5
+
+#define ISISC_DSCP_TO_PRI 0
+#define ISISC_DSCP_TO_DP 1
+#define ISISC_UP_TO_PRI 2
+#define ISISC_UP_TO_DP 3
+
+#define ISISC_EGRESS_REAMRK_ADDR 0x5ae00
+#define ISISC_EGRESS_REAMRK_NUM 16
+
+static sw_error_t
+_isisc_cosmap_dscp_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode,
+ a_uint32_t dscp, a_uint32_t val)
+{
+ sw_error_t rv;
+ a_uint32_t index, data;
+
+ if (ISISC_MAX_DSCP < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ index = dscp >> 3;
+ HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISISC_DSCP_TO_PRI == mode)
+ {
+ if (ISISC_MAX_PRI < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x7 << ((dscp & 0x7) << 2)));
+ data |= (val << ((dscp & 0x7) << 2));
+ }
+ else
+ {
+ if (ISISC_MAX_DP < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x1 << (((dscp & 0x7) << 2) + 3)));
+ data |= (val << (((dscp & 0x7) << 2) + 3));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_dscp_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode,
+ a_uint32_t dscp, a_uint32_t * val)
+{
+ sw_error_t rv;
+ a_uint32_t index, data;
+
+ if (ISISC_MAX_DSCP < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ index = dscp >> 3;
+ HSL_REG_ENTRY_GET(rv, dev_id, DSCP_TO_PRI, index, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (data >> ((dscp & 0x7) << 2)) & 0xf;
+ if (ISISC_DSCP_TO_PRI == mode)
+ {
+ *val = data & 0x7;
+ }
+ else
+ {
+ *val = (data & 0x8) >> 3;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_up_to_pri_dp_set(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+ a_uint32_t val)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISISC_MAX_UP < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISISC_UP_TO_PRI == mode)
+ {
+ if (ISISC_MAX_PRI < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x7 << (up << 2)));
+ data |= (val << (up << 2));
+ }
+ else
+ {
+ if (ISISC_MAX_DP < val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data &= (~(0x1 << ((up << 2) + 3)));
+ data |= (val << ((up << 2) + 3));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_up_to_pri_dp_get(a_uint32_t dev_id, a_uint32_t mode, a_uint32_t up,
+ a_uint32_t * val)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISISC_MAX_UP < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, UP_TO_PRI, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (data >> (up << 2)) & 0xf;
+
+ if (ISISC_UP_TO_PRI == mode)
+ {
+ *val = (data & 0x7);
+ }
+ else
+ {
+ *val = (data & 0x8) >> 3;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_QUEUE < queue))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x3 << (pri << 2)));
+ data |= (queue << (pri << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISISC_MAX_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_QUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = (data >> (pri << 2)) & 0x3;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if ((ISISC_MAX_PRI < pri) || (ISISC_MAX_EH_QUEUE < queue))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x7 << (pri << 2)));
+ data |= (queue << (pri << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (ISISC_MAX_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_TO_EHQUEUE, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = (data >> (pri << 2)) & 0x7;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ if (ISISC_EGRESS_REAMRK_NUM <= tbl_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = (tbl->y_up & 0x7)
+ | ((tbl->g_up & 0x7) << 4)
+ | ((tbl->y_dscp & 0x3f) << 8)
+ | ((tbl->g_dscp & 0x3f) << 16)
+ | ((tbl->remark_dscp & 0x1) << 23)
+ | ((tbl->remark_up & 0x1) << 22);
+
+ addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ if (ISISC_EGRESS_REAMRK_NUM <= tbl_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(tbl, sizeof (fal_egress_remark_table_t));
+
+ addr = ISISC_EGRESS_REAMRK_ADDR + (tbl_id << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data & (0x1 << 23))
+ {
+ tbl->remark_dscp = A_TRUE;
+ tbl->y_dscp = (data >> 8) & 0x3f;
+ tbl->g_dscp = (data >> 16) & 0x3f;
+ }
+
+ if (data & (0x1 << 22))
+ {
+ tbl->remark_up = A_TRUE;
+ tbl->y_up = data & 0x7;
+ tbl->g_up = (data >> 4) & 0x7;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_pri_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_PRI, dscp, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_pri_get(a_uint32_t dev_id, a_uint32_t dscp,
+ a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_PRI, dscp, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_dp_set(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_dscp_to_pri_dp_set(dev_id, ISISC_DSCP_TO_DP, dscp, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dscp to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_dscp_to_dp_get(a_uint32_t dev_id, a_uint32_t dscp, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_dscp_to_pri_dp_get(dev_id, ISISC_DSCP_TO_DP, dscp, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_pri_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_PRI, up, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal priority mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[out] pri internal priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_pri_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_PRI, up, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_dp_set(a_uint32_t dev_id, a_uint32_t up, a_uint32_t dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_up_to_pri_dp_set(dev_id, ISISC_UP_TO_DP, up, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dot1p to internal drop precedence mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] up dot1p
+ * @param[in] dp internal drop precedence
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_up_to_dp_get(a_uint32_t dev_id, a_uint32_t up, a_uint32_t * dp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_up_to_pri_dp_get(dev_id, ISISC_UP_TO_DP, up, dp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_queue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_pri_to_queue_set(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 1/2/3/4 which have four egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_queue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_pri_to_queue_get(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_ehqueue_set(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_pri_to_ehqueue_set(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get internal priority to queue mapping on one particular device.
+ * @details Comments:
+ * This function is for port 0/5/6 which have six egress queues
+ * @param[in] dev_id device id
+ * @param[in] pri internal priority
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_pri_to_ehqueue_get(a_uint32_t dev_id, a_uint32_t pri,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_pri_to_ehqueue_get(dev_id, pri, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[in] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_egress_remark_set(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_egress_remark_set(dev_id, tbl_id, tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remap table on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] tbl_id CoS remap table id
+ * @param[out] tbl CoS remap table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cosmap_egress_remark_get(a_uint32_t dev_id, a_uint32_t tbl_id,
+ fal_egress_remark_table_t * tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cosmap_egress_remark_get(dev_id, tbl_id, tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_cosmap_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->cosmap_dscp_to_pri_set = isisc_cosmap_dscp_to_pri_set;
+ p_api->cosmap_dscp_to_pri_get = isisc_cosmap_dscp_to_pri_get;
+ p_api->cosmap_dscp_to_dp_set = isisc_cosmap_dscp_to_dp_set;
+ p_api->cosmap_dscp_to_dp_get = isisc_cosmap_dscp_to_dp_get;
+ p_api->cosmap_up_to_pri_set = isisc_cosmap_up_to_pri_set;
+ p_api->cosmap_up_to_pri_get = isisc_cosmap_up_to_pri_get;
+ p_api->cosmap_up_to_dp_set = isisc_cosmap_up_to_dp_set;
+ p_api->cosmap_up_to_dp_get = isisc_cosmap_up_to_dp_get;
+ p_api->cosmap_pri_to_queue_set = isisc_cosmap_pri_to_queue_set;
+ p_api->cosmap_pri_to_queue_get = isisc_cosmap_pri_to_queue_get;
+ p_api->cosmap_pri_to_ehqueue_set = isisc_cosmap_pri_to_ehqueue_set;
+ p_api->cosmap_pri_to_ehqueue_get = isisc_cosmap_pri_to_ehqueue_get;
+ p_api->cosmap_egress_remark_set = isisc_cosmap_egress_remark_set;
+ p_api->cosmap_egress_remark_get = isisc_cosmap_egress_remark_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_fdb.c b/src/hsl/isisc/isisc_fdb.c
new file mode 100644
index 0000000..858928c
--- /dev/null
+++ b/src/hsl/isisc/isisc_fdb.c
@@ -0,0 +1,2272 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_fdb ISISC_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_fdb.h"
+#include "isisc_reg.h"
+#include "isisc_fdb_prv.h"
+
+static sw_error_t
+_isisc_wl_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17C_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static a_bool_t
+_isisc_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+_isisc_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE2, addr.uc[2], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE3, addr.uc[3], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+_isisc_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+ sw_error_t rv;
+
+ if (A_TRUE == entry->white_list_en)
+ {
+ rv = _isisc_wl_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, WL_EN, 1, reg[2]);
+ }
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISISC_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg[1]);
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, SA_DROP_EN, 1, reg[1]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, MIRROR_EN, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 1, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, CROSS_PT, 0, reg[1]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI, (entry->da_queue & 0x7),
+ reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_PRI_EN, 0, reg[1]);
+ }
+
+ _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ return SW_OK;
+}
+
+static void
+_isisc_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_SVL_EN, data, reg[1]);
+ if (data)
+ {
+ entry->fid = FAL_SVL_FID;
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_VID, data, reg[2]);
+ entry->fid = data;
+ }
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, SA_DROP_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, MIRROR_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI_EN, data, reg[1]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, AT_PRI, data, reg[1]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x7;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, CROSS_PT, data, reg[1]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, data, reg[1]);
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 2; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+ }
+
+ entry->white_list_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, WL_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->white_list_en = A_TRUE;
+ }
+
+ return;
+}
+
+static sw_error_t
+_isisc_atu_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (®[3]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_atu_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (®[3]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 2000;
+ a_uint32_t entry;
+ a_uint32_t hwop = op;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+ }
+
+ if (0 == i)
+ {
+ return SW_BUSY;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_BUSY, 1, entry);
+
+ if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 1, entry);
+ }
+
+ if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, FLUSH_ST_EN, 0, entry);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_FUNC, hwop, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 2000;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_BUSY, busy, entry);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC3, AT_FULL_VIO, full_vio, entry);
+
+ if (full_vio)
+ {
+ /* must clear AT_FULL_VOI bit */
+ entry = 0x1000;
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ARL_LOAD_ENTRY == hwop)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == hwop)
+ || (ARL_FLUSH_PORT_UNICAST == hwop))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_get(a_uint32_t dev_id, fal_fdb_op_t * option, fal_fdb_entry_t * entry,
+ a_uint32_t hwop)
+{
+ sw_error_t rv;
+ a_uint32_t i, port = 0, status, reg[4] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == option->port_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_EN, 1, reg[3]);
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map,
+ HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ status = 0;
+ for (i = 0; i < SW_MAX_NR_PORT; i++)
+ {
+ if ((entry->port.map) & (0x1UL << i))
+ {
+ if (status)
+ {
+ return SW_BAD_PARAM;
+ }
+ port = i;
+ status = 1;
+ }
+ }
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port, reg[3]);
+ }
+
+ if (A_TRUE == option->fid_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+ }
+
+ if (A_TRUE == option->multicast_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+ }
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISISC_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, entry->fid, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ARL_FIRST_ENTRY != hwop)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 0xf, reg[2]);
+ }
+
+ _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ rv = _isisc_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_atu_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_atu_hw_to_sw(reg, entry);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+ if ((A_TRUE == _isisc_fdb_is_zeroaddr(entry->addr))
+ && (0 == status))
+ {
+ if (ARL_NEXT_ENTRY == hwop)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+ else
+ {
+ return SW_OK;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[4] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC3, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+ }
+ else
+ {
+ rv = _isisc_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0, reg2 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ _isisc_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ if (FAL_SVL_FID == entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg2);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg1);
+ }
+ else if (ISISC_MAX_FID >= entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, (entry->fid), reg2);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg1);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0, (a_uint8_t *) (®2),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_fdb_op_t option;
+
+ aos_mem_zero(&option, sizeof (fal_fdb_op_t));
+ rv = _isisc_fdb_get(dev_id, &option, entry, ARL_FIND_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = _isisc_fdb_get(dev_id, option, entry, ARL_NEXT_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ rv = _isisc_fdb_get(dev_id, option, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+ a_uint32_t reg[4] = { 0 };
+
+ if (A_TRUE == option->port_en)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == option->fid_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_VID_EN, 1, reg[3]);
+ }
+
+ if (A_TRUE == option->multicast_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_MULTI_EN, 1, reg[3]);
+ }
+
+ if (FAL_SVL_FID == fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, 0, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 1, reg[1]);
+ }
+ else if (ISISC_MAX_FID >= fid)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_VID, fid, reg[2]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_SVL_EN, 0, reg[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, AT_PORT_NUM, old_port, reg[3]);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC3, NEW_PORT_NUM, new_port, reg[3]);
+
+ rv = _isisc_atu_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_fdb_commit(dev_id, ARL_TRANSFER_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ data = smode;
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, ARL_INI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ *smode = data;
+
+ return rv;
+}
+
+
+
+static sw_error_t
+_isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((65535 * 7 < *time) || (7 > *time))
+ {
+ return SW_BAD_PARAM;
+ }
+ data = *time / 7;
+ *time = data * 7;
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 7;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_LIMIT_EN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, SA_LEARN_CNT, data, reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISISC_MAX_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 1,
+ reg);
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, 0,
+ reg);
+ SW_SET_REG_BY_FIELD(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_LIMIT_EN, data,
+ reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(GLOBAL_LEARN_LIMIT_CTL, GOL_SA_LEARN_CNT, data,
+ reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_LEARN_LIMIT_CTL, 0,
+ GOL_SA_LEARN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+#define ISISC_RESV_ADDR_NUM 32
+#define RESV_ADDR_TBL0_ADDR 0x3c000
+#define RESV_ADDR_TBL1_ADDR 0x3c004
+#define RESV_ADDR_TBL2_ADDR 0x3c008
+
+static void
+_isisc_resv_addr_parse(const a_uint32_t reg[], fal_mac_addr_t * addr)
+{
+ a_uint32_t i;
+
+ for (i = 2; i < 6; i++)
+ {
+ addr->uc[i] = (reg[0] >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ addr->uc[i] = (reg[1] >> ((1 - i) << 3)) & 0xff;
+ }
+}
+
+static sw_error_t
+_isisc_resv_atu_sw_to_hw(a_uint32_t dev_id, fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ port = entry->port.map;
+ }
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_DES_PORT, port, reg[1]);
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, 1, reg[1]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, 1, reg[1]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 1, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_LEAKY_EN, 0, reg[1]);
+ }
+
+ if (A_TRUE != entry->static_en)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL2, RESV_STATUS, 1, reg[2]);
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_MIRROR_EN, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_CROSS_PT, 1, reg[1]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI_EN, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(RESV_ADDR_TBL1, RESV_PRI, (entry->da_queue & 0x7),
+ reg[1]);
+ }
+
+ _isisc_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ return SW_OK;
+}
+
+static void
+_isisc_resv_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->fid = FAL_SVL_FID;
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_COPY_TO_CPU, data, reg[1]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_REDRCT_TO_CPU, data, reg[1]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_LEAKY_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_TRUE;
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_MIRROR_EN, data, reg[1]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI_EN, data, reg[1]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_PRI, data, reg[1]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x7;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_CROSS_PT, data, reg[1]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL1, RESV_DES_PORT, data, reg[1]);
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ _isisc_resv_addr_parse(reg, &(entry->addr));
+ return;
+}
+
+static sw_error_t
+_isisc_fdb_resv_commit(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op,
+ a_uint32_t * empty)
+{
+ a_uint32_t index, addr, data, tbl[3] = { 0 };
+ sw_error_t rv;
+ fal_mac_addr_t mac_tmp;
+
+ *empty = ISISC_RESV_ADDR_NUM;
+ for (index = 0; index < ISISC_RESV_ADDR_NUM; index++)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+ if (data)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_resv_addr_parse(tbl, &mac_tmp);
+ if (!aos_mem_cmp
+ ((void *) &(entry->addr), (void *) &mac_tmp,
+ sizeof (fal_mac_addr_t)))
+ {
+ if (ARL_PURGE_ENTRY == op)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ tbl[2] = 0;
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])),
+ sizeof (a_uint32_t));
+ return rv;
+ }
+ else if (ARL_LOAD_ENTRY == op)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ else if (ARL_FIND_ENTRY == op)
+ {
+ _isisc_resv_atu_hw_to_sw(tbl, entry);
+ return SW_OK;
+ }
+ }
+ }
+ else
+ {
+ *empty = index;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, empty, addr, tbl[3] = { 0 };
+
+ rv = _isisc_resv_atu_sw_to_hw(dev_id, entry, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_LOAD_ENTRY, &empty);
+ if (SW_ALREADY_EXIST == rv)
+ {
+ return rv;
+ }
+
+ if (ISISC_RESV_ADDR_NUM == empty)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < 3; i++)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty;
+
+ rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_PURGE_ENTRY, &empty);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty;
+
+ rv = _isisc_fdb_resv_commit(dev_id, entry, ARL_FIND_ENTRY, &empty);
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ a_uint32_t index, addr, data, tbl[3] = { 0 };
+ sw_error_t rv;
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (ISISC_RESV_ADDR_NUM < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < ISISC_RESV_ADDR_NUM; index++)
+ {
+ addr = RESV_ADDR_TBL2_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(RESV_ADDR_TBL2, RESV_STATUS, data, tbl[2]);
+ if (data)
+ {
+ addr = RESV_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = RESV_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_resv_atu_hw_to_sw(tbl, entry);
+ break;
+ }
+ }
+
+ if (ISISC_RESV_ADDR_NUM == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0x7;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_STATUS, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ SA_LEARN_STATUS, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_fdb_port_update(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ fal_fdb_entry_t entry;
+ fal_fdb_op_t option;
+ a_uint32_t reg, port;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SVL_FID < fid)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(&option, sizeof(fal_fdb_op_t));
+ aos_mem_copy(&(entry.addr), addr, sizeof(fal_mac_addr_t));
+ entry.fid = fid & 0xffff;
+ rv = _isisc_fdb_get(dev_id, &option, &entry, ARL_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+ if (op)
+ {
+ port |= (0x1 << port_id);
+ }
+ else
+ {
+ port &= (~(0x1 << port_id));
+ }
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, DES_PORT, port, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ rv = _isisc_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+ return rv;
+}
+
+sw_error_t
+inter_isisc_fdb_flush(a_uint32_t dev_id, a_uint32_t flag)
+{
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ return _isisc_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get next Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option next operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_extend_next(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_extend_next(dev_id, option, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from a particular device
+ * @param[in] dev_id device id
+ * @param[in] option first operation options
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_extend_first(dev_id, option, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Transfer fdb entries port information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port source port id
+ * @param[in] new_port destination port id
+ * @param[in] fid filter database id
+ * @param[in] option transfer operation options
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
+ a_uint32_t fid, fal_fdb_op_t * option)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_transfer(dev_id, old_port, new_port, fid, option);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_learn_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_learn_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_age_ctrl_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_age_ctrl_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief set arl search mode as ivl or svl when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[in] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_vlan_ivl_svl_set(a_uint32_t dev_id, fal_fdb_smode smode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_vlan_ivl_svl_set(dev_id, smode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get arl search mode when vlan invalid.
+ * @param[in] dev_id device id
+ * @param[out] smode INVALID_VLAN_IVL or INVALID_VLAN_SVL
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_vlan_ivl_svl_get(a_uint32_t dev_id, fal_fdb_smode* smode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_vlan_ivl_svl_get(dev_id, smode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_fdb_learn_limit_set(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_fdb_learn_limit_get(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_fdb_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_fdb_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_limit_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_learn_limit_set(dev_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count limit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_limit_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_learn_limit_get(dev_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_exceed_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_learn_exceed_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning count exceed command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_learn_exceed_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_learn_exceed_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a particular reserve Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_add(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_resv_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_del(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_resv_del(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular reserve Fdb entry through mac address
+ * @param[in] dev_id device id
+ * @param[in] entry reserve fdb entry
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_resv_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all reserve fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator reserve fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry reserve fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_resv_iterate(a_uint32_t dev_id, a_uint32_t * iterator,
+ fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_resv_iterate(dev_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_static_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_learn_static_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of fdb entries which learned by hardware on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_learn_static_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_learn_static_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port to an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_add(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 1);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a port from an exsiting entry
+ * @param[in] dev_id device id
+ * @param[in] fid filtering database id
+ * @param[in] addr MAC address
+ * @param[in] port_id port id
+ * @return SW_OK or error code, If entry not exist will return error.
+ */
+HSL_LOCAL sw_error_t
+isisc_fdb_port_del(a_uint32_t dev_id, a_uint32_t fid, fal_mac_addr_t * addr, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_fdb_port_update(dev_id, fid, addr, port_id, 0);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = isisc_fdb_add;
+ p_api->fdb_del_all = isisc_fdb_del_all;
+ p_api->fdb_del_by_port = isisc_fdb_del_by_port;
+ p_api->fdb_del_by_mac = isisc_fdb_del_by_mac;
+ p_api->fdb_extend_first = isisc_fdb_extend_first;
+ p_api->fdb_extend_next = isisc_fdb_extend_next;
+ p_api->fdb_find = isisc_fdb_find;
+ p_api->port_learn_set = isisc_fdb_port_learn_set;
+ p_api->port_learn_get = isisc_fdb_port_learn_get;
+ p_api->age_ctrl_set = isisc_fdb_age_ctrl_set;
+ p_api->age_ctrl_get = isisc_fdb_age_ctrl_get;
+ p_api->age_time_set = isisc_fdb_age_time_set;
+ p_api->age_time_get = isisc_fdb_age_time_get;
+ p_api->fdb_extend_next = isisc_fdb_extend_next;
+ p_api->fdb_extend_first = isisc_fdb_extend_first;
+ p_api->fdb_transfer = isisc_fdb_transfer;
+ p_api->port_fdb_learn_limit_set = isisc_port_fdb_learn_limit_set;
+ p_api->port_fdb_learn_limit_get = isisc_port_fdb_learn_limit_get;
+ p_api->port_fdb_learn_exceed_cmd_set = isisc_port_fdb_learn_exceed_cmd_set;
+ p_api->port_fdb_learn_exceed_cmd_get = isisc_port_fdb_learn_exceed_cmd_get;
+ p_api->fdb_learn_limit_set = isisc_fdb_learn_limit_set;
+ p_api->fdb_learn_limit_get = isisc_fdb_learn_limit_get;
+ p_api->fdb_learn_exceed_cmd_set = isisc_fdb_learn_exceed_cmd_set;
+ p_api->fdb_learn_exceed_cmd_get = isisc_fdb_learn_exceed_cmd_get;
+ p_api->fdb_resv_add = isisc_fdb_resv_add;
+ p_api->fdb_resv_del = isisc_fdb_resv_del;
+ p_api->fdb_resv_find = isisc_fdb_resv_find;
+ p_api->fdb_resv_iterate = isisc_fdb_resv_iterate;
+ p_api->fdb_port_learn_static_set = isisc_fdb_port_learn_static_set;
+ p_api->fdb_port_learn_static_get = isisc_fdb_port_learn_static_get;
+ p_api->fdb_port_add = isisc_fdb_port_add;
+ p_api->fdb_port_del = isisc_fdb_port_del;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_igmp.c b/src/hsl/isisc/isisc_igmp.c
new file mode 100644
index 0000000..b7545a2
--- /dev/null
+++ b/src/hsl/isisc/isisc_igmp.c
@@ -0,0 +1,1134 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_igmp ISISC_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_igmp.h"
+#include "isisc_reg.h"
+
+#define LEAVE_EN_OFFSET 2
+#define JOIN_EN_OFFSET 1
+#define IGMP_MLD_EN_OFFSET 0
+
+#define ISISC_MAX_PORT_LEARN_LIMIT_CNT 1024
+
+extern sw_error_t
+isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+extern sw_error_t
+isisc_igmp_sg_entry_show(a_uint32_t dev_id);
+
+static sw_error_t
+_isisc_port_igmp_property_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << ((port_id << 3) + item));
+ reg |= (val << ((port_id << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+ reg |= (val << (((port_id - 4) << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_property_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+ }
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+ {
+ return SW_BAD_PARAM;
+ }
+ val = pts;
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *pts = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0xe;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 1, entry);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, queue, entry);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI_EN, 0, entry);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_CTL, IGMP_PRI, 0, entry);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI_EN, data, entry);
+ if (data)
+ {
+ *enable = A_TRUE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_CTL, IGMP_PRI, data, entry);
+ *queue = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *queue = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (ISISC_MAX_PORT_LEARN_LIMIT_CNT < cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, cnt, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_LIMIT_EN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(PORT_LEARN_LIMIT_CTL, IGMP_JOIN_CNT, data, reg);
+ *enable = A_TRUE;
+ *cnt = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *cnt = data;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LEARN_LIMIT_CTL, port_id,
+ IGMP_JOIN_LIMIT_DROP_EN, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_set(dev_id, port_id, enable,
+ IGMP_MLD_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_get(dev_id, port_id, enable,
+ IGMP_MLD_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, JOIN_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, JOIN_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp leave feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_set(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_property_get(dev_id, port_id, enable, LEAVE_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_rp_set(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_rp_get(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_creat_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_creat_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * static status hardware will not age out multicast entry which leardned by hardware,
+ * otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_static_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_static_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_leaky_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_leaky_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details Comments:
+ * After enabling igmp join/leave feature on a particular port hardware will dynamic
+ * creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_v3_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_v3_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable,
+ a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_queue_set(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable,
+ a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_igmp_mld_entry_queue_get(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_limit_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_mld_learn_limit_set(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count limit on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] cnt limit count
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_limit_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t * cnt)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_mld_learn_limit_get(dev_id, port_id, enable, cnt);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_exceed_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_mld_learn_exceed_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IGMP hardware learning count exceed command on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_igmp_mld_learn_exceed_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_igmp_mld_learn_exceed_cmd_get(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_igmp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_igmps_status_set = isisc_port_igmps_status_set;
+ p_api->port_igmps_status_get = isisc_port_igmps_status_get;
+ p_api->igmp_mld_cmd_set = isisc_igmp_mld_cmd_set;
+ p_api->igmp_mld_cmd_get = isisc_igmp_mld_cmd_get;
+ p_api->port_igmp_join_set = isisc_port_igmp_mld_join_set;
+ p_api->port_igmp_join_get = isisc_port_igmp_mld_join_get;
+ p_api->port_igmp_leave_set = isisc_port_igmp_mld_leave_set;
+ p_api->port_igmp_leave_get = isisc_port_igmp_mld_leave_get;
+ p_api->igmp_rp_set = isisc_igmp_mld_rp_set;
+ p_api->igmp_rp_get = isisc_igmp_mld_rp_get;
+ p_api->igmp_entry_creat_set = isisc_igmp_mld_entry_creat_set;
+ p_api->igmp_entry_creat_get = isisc_igmp_mld_entry_creat_get;
+ p_api->igmp_entry_static_set = isisc_igmp_mld_entry_static_set;
+ p_api->igmp_entry_static_get = isisc_igmp_mld_entry_static_get;
+ p_api->igmp_entry_leaky_set = isisc_igmp_mld_entry_leaky_set;
+ p_api->igmp_entry_leaky_get = isisc_igmp_mld_entry_leaky_get;
+ p_api->igmp_entry_v3_set = isisc_igmp_mld_entry_v3_set;
+ p_api->igmp_entry_v3_get = isisc_igmp_mld_entry_v3_get;
+ p_api->igmp_entry_queue_set = isisc_igmp_mld_entry_queue_set;
+ p_api->igmp_entry_queue_get = isisc_igmp_mld_entry_queue_get;
+ p_api->port_igmp_mld_learn_limit_set = isisc_port_igmp_mld_learn_limit_set;
+ p_api->port_igmp_mld_learn_limit_get = isisc_port_igmp_mld_learn_limit_get;
+ p_api->port_igmp_mld_learn_exceed_cmd_set = isisc_port_igmp_mld_learn_exceed_cmd_set;
+ p_api->port_igmp_mld_learn_exceed_cmd_get = isisc_port_igmp_mld_learn_exceed_cmd_get;
+ p_api->igmp_sg_entry_set = isisc_igmp_sg_entry_set;
+ p_api->igmp_sg_entry_clear = isisc_igmp_sg_entry_clear;
+ p_api->igmp_sg_entry_show = isisc_igmp_sg_entry_show;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_init.c b/src/hsl/isisc/isisc_init.c
new file mode 100644
index 0000000..b989416
--- /dev/null
+++ b/src/hsl/isisc/isisc_init.c
@@ -0,0 +1,313 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_init ISISC_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mib.h"
+#include "isisc_port_ctrl.h"
+#include "isisc_portvlan.h"
+#include "isisc_vlan.h"
+#include "isisc_fdb.h"
+#include "isisc_qos.h"
+#include "isisc_mirror.h"
+#include "isisc_stp.h"
+#include "isisc_rate.h"
+#include "isisc_misc.h"
+#include "isisc_leaky.h"
+#include "isisc_igmp.h"
+#include "isisc_acl.h"
+#include "isisc_led.h"
+#include "isisc_cosmap.h"
+#include "isisc_ip.h"
+#include "isisc_nat.h"
+#if defined(IN_NAT_HELPER)
+#include "isisc_nat_helper.h"
+#endif
+#include "isisc_sec.h"
+#include "isisc_trunk.h"
+#include "isisc_interface_ctrl.h"
+#include "isisc_reg_access.h"
+#include "isisc_reg.h"
+#include "isisc_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * isisc_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For isis there are five internal PHY devices and seven MAC devices.
+ MAC0 always connect to external MAC device.
+ PHY4 can connect to MAC5 or external MAC device.
+ MAC6 always connect to external devices.
+ MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+isisc_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ /* for port property set, SSDK should not generate some limitations */
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ /* Only port0/port6 without PHY device */
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != pdev->nr_ports - 1))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port but exclude wan port in some cases */
+ /* but which port is wan port, we are no meaning */
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ /* which port is wan port, we are no meaning but port0 is
+ always CPU port */
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+isisc_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ return SW_OK;
+}
+
+#endif
+
+static sw_error_t
+isisc_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+ a_uint32_t entry;
+ sw_error_t rv;
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17C_DEVICE_ID == entry)
+ {
+ pdev->nr_ports = 7;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 6;
+ pdev->cpu_mode = cpu_mode;
+ }
+ else
+ {
+ pdev->nr_ports = 6;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 6;
+ pdev->cpu_mode = cpu_mode;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = isisc_hw_init(dev_id, isisc_cfg[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ ISISC_ACL_RESET(rv, dev_id);
+ ISISC_IP_RESET(rv, dev_id);
+ ISISC_NAT_RESET(rv, dev_id);
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_cleanup(a_uint32_t dev_id)
+{
+ if (isisc_cfg[dev_id])
+ {
+#if defined(IN_NAT_HELPER)
+ sw_error_t rv;
+ ISISC_NAT_HELPER_CLEANUP(rv, dev_id);
+#endif
+
+ aos_mem_free(isisc_cfg[dev_id]);
+ isisc_cfg[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ * This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ * This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+isisc_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == isisc_cfg[dev_id])
+ {
+ isisc_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == isisc_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(isisc_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(isisc_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(isisc_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ sw_error_t rv;
+
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(isisc_portproperty_init(dev_id, cfg->cpu_mode));
+
+ ISISC_MIB_INIT(rv, dev_id);
+ ISISC_PORT_CTRL_INIT(rv, dev_id);
+ ISISC_PORTVLAN_INIT(rv, dev_id);
+ ISISC_VLAN_INIT(rv, dev_id);
+ ISISC_FDB_INIT(rv, dev_id);
+ ISISC_QOS_INIT(rv, dev_id);
+ ISISC_STP_INIT(rv, dev_id);
+ ISISC_MIRR_INIT(rv, dev_id);
+ ISISC_RATE_INIT(rv, dev_id);
+ ISISC_MISC_INIT(rv, dev_id);
+ ISISC_LEAKY_INIT(rv, dev_id);
+ ISISC_IGMP_INIT(rv, dev_id);
+ ISISC_ACL_INIT(rv, dev_id);
+ ISISC_LED_INIT(rv, dev_id);
+ ISISC_COSMAP_INIT(rv, dev_id);
+ ISISC_IP_INIT(rv, dev_id);
+ ISISC_NAT_INIT(rv, dev_id);
+ ISISC_TRUNK_INIT(rv, dev_id);
+ ISISC_SEC_INIT(rv, dev_id);
+ ISISC_INTERFACE_CTRL_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = isisc_reset;
+ p_api->dev_clean = isisc_cleanup;
+ }
+
+ SW_RTN_ON_ERROR(isisc_hw_init(dev_id, cfg));
+#if defined(IN_NAT_HELPER)
+ ISISC_NAT_HELPER_INIT(rv, dev_id);
+#endif
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_interface_ctrl.c b/src/hsl/isisc/isisc_interface_ctrl.c
new file mode 100644
index 0000000..5b00bdb
--- /dev/null
+++ b/src/hsl/isisc/isisc_interface_ctrl.c
@@ -0,0 +1,2116 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_interface_ctrl ISISC_INTERFACE_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_interface_ctrl.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAC_0 0
+#define ISISC_MAC_5 5
+#define ISISC_MAC_6 6
+
+#define ISISC_PHY_MODE_PHY_ID 4
+#define ISISC_LPI_PORT1_OFFSET 4
+#define ISISC_LPI_BIT_STEP 2
+
+/* we need to do more about MAC5/PHY4 connection... */
+#if 0
+static sw_error_t
+_isisc_port_mac5_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, rgmii, gmii_mac, gmii_phy, mii_mac, mii_phy, sgmii;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, rgmii, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, gmii_mac, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, gmii_phy, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, mii_mac, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, mii_phy, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, sgmii, reg);
+
+ if (rgmii || gmii_mac || gmii_phy || mii_mac || mii_phy || sgmii)
+ {
+ *inter_mode = A_FALSE;
+ }
+ else
+ {
+ *inter_mode = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_phy4_internal_mode(a_uint32_t dev_id, a_bool_t * inter_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, rgmii, gmii, mii;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_GMII_EN, gmii, reg);
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_MII_EN, mii, reg);
+
+ if (rgmii || gmii || mii)
+ {
+ *inter_mode = A_FALSE;
+ }
+ else
+ {
+ *inter_mode = A_TRUE;
+ }
+
+ return SW_OK;
+}
+#endif
+
+static sw_error_t
+_isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, offset, device_id, rev_id, reverse = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+ if (S17C_DEVICE_ID != device_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+ if (S17_REVISION_A == rev_id)
+ {
+ reverse = 0;
+ }
+ else
+ {
+ reverse = 1;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ field = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ field = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (reverse)
+ {
+ field = (~field) & 0x1UL;
+ }
+
+ offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET;
+ reg &= (~(0x1UL << offset));
+ reg |= (field << offset);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, offset, device_id, rev_id, reverse = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MASK_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, DEVICE_ID, device_id, reg);
+ if (S17C_DEVICE_ID != device_id)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_GET_FIELD_BY_REG(MASK_CTL, REV_ID, rev_id, reg);
+ if (S17_REVISION_A == rev_id)
+ {
+ reverse = 0;
+ }
+ else
+ {
+ reverse = 1;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, EEE_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ offset = (port_id - 1) * ISISC_LPI_BIT_STEP + ISISC_LPI_PORT1_OFFSET;
+ field = (reg >> offset) & 0x1;
+
+ if (reverse)
+ {
+ field = (~field) & 0x1UL;
+ }
+
+ if (field)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_rgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (A_TRUE == config->txclk_delay_cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, config->txclk_delay_sel, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ }
+
+ if (A_TRUE == config->rxclk_delay_cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, config->rxclk_delay_sel, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ }
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, field, reg);
+ if (field)
+ {
+ config->txclk_delay_cmd = A_TRUE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, field, reg);
+ config->txclk_delay_sel = field;
+ }
+ else
+ {
+ config->txclk_delay_cmd = A_FALSE;
+ config->txclk_delay_sel = 0;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, field, reg);
+ if (field)
+ {
+ config->rxclk_delay_cmd = A_TRUE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, field, reg);
+ config->rxclk_delay_sel = field;
+ }
+ else
+ {
+ config->rxclk_delay_cmd = A_FALSE;
+ config->rxclk_delay_sel = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg,field;
+
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MAC06_EXCH_EN, field, reg);
+ if (field)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (config->master_mode == config->slave_mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == config->master_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 1, reg);
+ }
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (A_TRUE == config->clock_inverse)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SEL, 0, reg);
+ }
+
+ if (A_TRUE == config->pipe_rxclk_sel)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, 0, reg);
+ }
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field, reg);
+ if (field)
+ {
+ config->master_mode = A_TRUE;
+ }
+ else
+ {
+ config->master_mode = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field, reg);
+ if (field)
+ {
+ config->slave_mode = A_TRUE;
+ }
+ else
+ {
+ config->slave_mode = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SEL, field, reg);
+ if (field)
+ {
+ config->clock_inverse = A_TRUE;
+ }
+ else
+ {
+ config->clock_inverse = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_PIPE_RXCLK_SEL, field, reg);
+ if (field)
+ {
+ config->pipe_rxclk_sel = A_TRUE;
+ }
+ else
+ {
+ config->pipe_rxclk_sel = A_FALSE;
+ }
+
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_gmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+ }
+ else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, config->rxclk_select, reg);
+
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_gmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_gmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field, reg);
+ if (field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, config->rxclk_select, reg);
+ }
+ else if (FAL_INTERFACE_CLOCK_MAC_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, config->txclk_select, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, config->rxclk_select, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_mii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_mii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field, reg);
+ if (field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, field, reg);
+ config->txclk_select = field;
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, field, reg);
+ config->rxclk_select = field;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_sgmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+
+ if (A_TRUE == config->force_speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, 0, reg);
+ }
+
+ if (A_TRUE == config->prbs_enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, 0, reg);
+ }
+
+ if (A_TRUE == config->rem_phy_lpbk)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, 0, reg);
+ }
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+ /* TX/RX clock setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* SGMII control register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg);
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == config->clock_mode)
+ {
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 2, reg);
+ }
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_sgmii_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_sgmii_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ /* nothing to do */
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ /* nothing to do */
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, field, reg);
+ if (field)
+ {
+ config->auto_neg = A_TRUE;
+ }
+ else
+ {
+ config->auto_neg = A_FALSE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(SGMII_CTRL, MODE_CTRL_25M, field, reg);
+ if (1 == field)
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_PHY_MODE;
+ }
+ else
+ {
+ config->clock_mode = FAL_INTERFACE_CLOCK_MAC_MODE;
+ }
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_PRBS_BERT_EN, field, reg);
+ if (1 == field)
+ {
+ config->prbs_enable = A_TRUE;
+ }
+ else
+ {
+ config->prbs_enable = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_REM_PHY_LPBK_EN, field, reg);
+ if (1 == field)
+ {
+ config->rem_phy_lpbk = A_TRUE;
+ }
+ else
+ {
+ config->rem_phy_lpbk = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_fiber_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT6_PAD_CTRL, port_id, MAC6_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* only support one SGMII interface, so we need to disable another SGMII */
+ field = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT0_PAD_CTRL, port_id, MAC0_SGMII_EN,
+ (a_uint8_t *) (&field), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* SGMII global settings, for all SGMII interfaces, now we fix all the values */
+ /* TX/RX clock setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_RX_SEL, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_CLK125M_TX_SEL, 0, reg);
+
+ if (A_TRUE == config->fx100_enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, SGMII_FX100_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* SGMII control register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, MODE_CTRL_25M, 0, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_FIBER_MODE, 3, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_PLL, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_RX, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_TX, 1, reg);
+ SW_SET_REG_BY_FIELD(SGMII_CTRL, SGMII_EN_SD, 1, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* Power on strip register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(POWER_STRIP, SERDES_AN_EN, 0, reg);
+ }
+ HSL_REG_ENTRY_SET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* Port status register setting */
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ /* setting port status default configuration */
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 1, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg);
+ if (A_TRUE == config->auto_neg)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_fiber_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_fiber_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ /* nothing to do */
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ /* nothing to do */
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, POWER_STRIP, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(POWER_STRIP, SERDES_AN_EN, field, reg);
+ if (field)
+ {
+ config->auto_neg = A_TRUE;
+ }
+ else
+ {
+ config->auto_neg = A_FALSE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, SGMII_FX100_EN, field, reg);
+
+ if (field)
+ {
+ config->fx100_enable = A_TRUE;
+ }
+ else
+ {
+ config->fx100_enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_default_mode_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_SGMII_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_MASTER_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, RMII_SLAVE_EN, 0, reg);
+
+ /* hardware suggestions: restore to defatult settings */
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_TXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_RGMII_RXCLK_DELAY_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_PHY_MII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_GMII_RXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_TXCLK_SEL, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT0_PAD_CTRL, MAC0_MAC_MII_RXCLK_SEL, 0, reg);
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_MODE_RGMII == config->mac_mode)
+ {
+ rv = _isisc_port_rgmii_mode_set(dev_id, port_id, &(config->config.rgmii));
+ }
+ else if (FAL_MAC_MODE_GMII == config->mac_mode)
+ {
+ rv = _isisc_port_gmii_mode_set(dev_id, port_id, &(config->config.gmii));
+ }
+ else if (FAL_MAC_MODE_MII == config->mac_mode)
+ {
+ rv = _isisc_port_mii_mode_set(dev_id, port_id, &(config->config.mii));
+ }
+ else if (FAL_MAC_MODE_SGMII == config->mac_mode)
+ {
+ rv = _isisc_port_sgmii_mode_set(dev_id, port_id, &(config->config.sgmii));
+ }
+ else if (FAL_MAC_MODE_FIBER == config->mac_mode)
+ {
+ rv = _isisc_port_fiber_mode_set(dev_id, port_id, &(config->config.fiber));
+ }
+ else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+ {
+ rv = _isisc_port_default_mode_set(dev_id, port_id);
+ }
+ else if (FAL_MAC_MODE_RMII == config->mac_mode)
+ {
+ rv = _isisc_port_rmii_mode_set(dev_id, port_id, &(config->config.rmii));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field, field2;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAC_0 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_5 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else if (ISISC_MAC_6 == port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(config, sizeof(fal_interface_mac_mode_t));
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_RGMII_EN, field, reg);
+ if (field)
+ {
+ config->mac_mode = FAL_MAC_MODE_RGMII;
+ rv = _isisc_port_rgmii_mode_get(dev_id, port_id, &(config->config.rgmii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_MASTER_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, RMII_SLAVE_EN, field2, reg);
+ if (field || field2)
+ {
+ config->mac_mode = FAL_MAC_MODE_RMII;
+ rv = _isisc_port_rmii_mode_get(dev_id, port_id, &(config->config.rmii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_GMII_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_GMII_EN, field2, reg);
+ if (field || field2)
+ {
+ config->mac_mode = FAL_MAC_MODE_GMII;
+ rv = _isisc_port_gmii_mode_get(dev_id, port_id, &(config->config.gmii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_MII_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_PHY_MII_EN, field2, reg);
+ if (field || field2)
+ {
+ config->mac_mode = FAL_MAC_MODE_MII;
+ rv = _isisc_port_mii_mode_get(dev_id, port_id, &(config->config.mii));
+ return rv;
+ }
+
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_SGMII_EN, field, reg);
+ SW_GET_FIELD_BY_REG(PORT0_PAD_CTRL, MAC0_MAC_SGMII_FORCE_SPEED, field2, reg);
+
+ if (field)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(SGMII_CTRL, SGMII_FIBER_MODE, field, reg);
+ if (3 == field)
+ {
+ config->mac_mode = FAL_MAC_MODE_FIBER;
+ rv = _isisc_port_fiber_mode_get(dev_id, port_id, &(config->config.fiber));
+ }
+ else
+ {
+ config->mac_mode = FAL_MAC_MODE_SGMII;
+ rv = _isisc_port_sgmii_mode_get(dev_id, port_id, &(config->config.sgmii));
+ if (field2)
+ config->config.sgmii.force_speed = A_TRUE;
+ else
+ config->config.sgmii.force_speed = A_FALSE;
+ }
+ return rv;
+ }
+
+ config->mac_mode = FAL_MAC_MODE_DEFAULT;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ a_uint16_t data;
+ a_uint32_t reg, rgmii_mode, tx_delay = 2;;
+ a_bool_t tx_delay_cmd, rx_delay_cmd;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ /* only PHY4 support mode setting */
+ if (ISISC_PHY_MODE_PHY_ID != phy_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_MODE_RGMII == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 1, reg);
+ rgmii_mode = 1;
+ /* PHY TX delay */
+ if (A_TRUE == config->txclk_delay_cmd)
+ {
+ tx_delay_cmd = A_TRUE;
+ tx_delay = config->txclk_delay_sel;
+ }
+ else
+ {
+ tx_delay_cmd = A_FALSE;
+ }
+
+ /* PHY RX delay */
+ if (A_TRUE == config->rxclk_delay_cmd)
+ {
+ rx_delay_cmd = A_TRUE;
+ }
+ else
+ {
+ rx_delay_cmd = A_FALSE;
+ }
+ }
+ else if (FAL_MAC_MODE_DEFAULT == config->mac_mode)
+ {
+ SW_SET_REG_BY_FIELD(PORT6_PAD_CTRL, PHY4_RGMII_EN, 0, reg);
+ rgmii_mode = 0;
+ tx_delay_cmd = A_FALSE;
+ rx_delay_cmd = A_FALSE;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RGMII mode, debug register18 bit3 */
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 18);
+ data &= 0xfff7UL;
+ data |= ((rgmii_mode & 0x1) << 3);
+ rv = f1_phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 18, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY TX delay command, debug regigster5 bit8 */
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5);
+ if (A_TRUE == tx_delay_cmd)
+ {
+ data |= 0x0100UL;
+ }
+ else
+ {
+ data &= 0xfeffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 5, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY TX delay select, debug register11 bit-6 */
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11);
+ data &= 0xff9fUL;
+ data |= ((tx_delay & 0x3UL) << 5);
+ if (A_TRUE == tx_delay_cmd)
+ {
+ data |= 0x0100UL;
+ }
+ else
+ {
+ data &= 0xfeffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 11, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RX delay command, debug regigster0 bit15 */
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0);
+ if (A_TRUE == rx_delay_cmd)
+ {
+ data |= 0x8000UL;
+ }
+ else
+ {
+ data &= 0x7fffUL;
+ }
+ rv = f1_phy_debug_write(dev_id, ISISC_PHY_MODE_PHY_ID, 0, data);
+ SW_RTN_ON_ERROR(rv);
+
+ /* PHY RX delay select, now hardware not support */
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+ a_uint16_t data;
+ a_uint32_t reg, rgmii, gmii, mii;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ /* only one PHY device support this */
+ if (ISISC_PHY_MODE_PHY_ID != phy_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(config, sizeof(fal_phy_config_t));
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT6_PAD_CTRL, PHY4_RGMII_EN, rgmii, reg);
+
+ if (rgmii)
+ {
+ config->mac_mode = FAL_MAC_MODE_RGMII;
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 5);
+ if (data & 0x0100)
+ {
+ config->txclk_delay_cmd = A_TRUE;
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 11);
+ config->txclk_delay_sel = (data >> 5) & 0x3UL;
+ }
+ else
+ {
+ config->txclk_delay_cmd = A_FALSE;
+ }
+
+ data = f1_phy_debug_read(dev_id, ISISC_PHY_MODE_PHY_ID, 0);
+ if (data & 0x8000)
+ {
+ config->rxclk_delay_cmd = A_TRUE;
+ }
+ else
+ {
+ config->rxclk_delay_cmd = A_FALSE;
+ }
+ }
+ else
+ {
+ config->mac_mode = FAL_MAC_MODE_DEFAULT;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (Fx100BASE_MODE == config->link_mode)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, LINK_CTRL, Fx100BASE_MODE, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == config->overshoot)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, OVERSHOOT_MODE, 0, reg);
+ }
+
+ if (A_TRUE == config->loopback)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_MODE, 0, reg);
+ }
+
+ if (A_TRUE == config->fd_mode)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, FD_MODE, 0, reg);
+ }
+
+ if (A_TRUE == config->col_test)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, COL_TEST, 0, reg);
+ }
+
+ if (FX100_SERDS_MODE == config->sgmii_fiber_mode)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, SGMII_FIBER, FX100_SERDS_MODE, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == config->crs_ctrl)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_CTRL, 0, reg);
+ }
+
+ if (A_TRUE == config->loopback_ctrl)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, LOOPBACK_TEST, 0, reg);
+ }
+
+ if (A_TRUE == config->crs_col_100_ctrl)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, CRS_COL_100_CTRL, 0, reg);
+ }
+
+ if (A_TRUE == config->loop_en)
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 1, reg);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(FX100_CTRL, FX100_LOOP_EN, 0, reg);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FX100_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, LINK_CTRL, field, reg);
+ if (field == Fx100BASE_MODE)
+ {
+ config->link_mode = Fx100BASE_MODE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, OVERSHOOT_MODE, field, reg);
+ if (A_TRUE == field)
+ {
+ config->overshoot = A_TRUE;
+ }
+ else
+ {
+ config->overshoot = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_MODE, field, reg);
+ if (A_TRUE == field)
+ {
+ config->loopback = A_TRUE;
+ }
+ else
+ {
+ config->loopback = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, FD_MODE, field, reg);
+ config->fd_mode =field;
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, COL_TEST, field, reg);
+ if (A_TRUE == field)
+ {
+ config->col_test = A_TRUE;
+ }
+ else
+ {
+ config->col_test = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, SGMII_FIBER, field, reg);
+ if (FX100_SERDS_MODE == field)
+ {
+ config->sgmii_fiber_mode = FX100_SERDS_MODE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_CTRL, field, reg);
+ if (A_TRUE == field)
+ {
+ config->crs_ctrl = A_TRUE;
+ }
+ else
+ {
+ config->crs_ctrl = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, LOOPBACK_TEST, field, reg);
+ if (A_TRUE == field)
+ {
+ config->loopback_ctrl = A_TRUE;
+ }
+ else
+ {
+ config->loopback_ctrl = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, CRS_COL_100_CTRL, field, reg);
+ if (A_TRUE == field)
+ {
+ config->crs_col_100_ctrl = A_TRUE;
+ }
+ else
+ {
+ config->crs_col_100_ctrl = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_LOOP_EN, field, reg);
+ if (A_TRUE == field)
+ {
+ config->loop_en = A_TRUE;
+ }
+ else
+ {
+ config->loop_en = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, FX100_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(FX100_CTRL, FX100_STATUS, field, reg);
+
+ *status = field;
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_3az_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_3az_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.3az status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_3az_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_3az_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_mode_set(dev_id, port_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface mode on a particular MAC device.
+ * @param[in] dev_id device id
+ * @param[in] mca_id MAC device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_mode_get(a_uint32_t dev_id, fal_port_t port_id, fal_mac_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_mode_get(dev_id, port_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[in] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_phy_mode_set(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_phy_mode_set(dev_id, phy_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get interface phy mode on a particular PHY device.
+ * @param[in] dev_id device id
+ * @param[in] phy_id PHY device ID
+ * @param[out] config interface configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_phy_mode_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_phy_config_t * config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_phy_mode_get(dev_id, phy_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[in] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_ctrl_set(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_fx100_ctrl_set(dev_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get fx100 control configuration.
+ * @param[in] dev_id device id
+ * @param[out] config fx100 control configuration
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_ctrl_get(a_uint32_t dev_id, fal_fx100_ctrl_config_t* config)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_fx100_ctrl_get(dev_id, config);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get fx100 status.
+ * @param[in] dev_id device id
+ * @param[out] the value of fx100 status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_fx100_status_get(a_uint32_t dev_id, a_uint32_t* status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_fx100_status_get(dev_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac06_exch_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac06_exch_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac0 and mac6 exchange status.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac06_exch_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac06_exch_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_interface_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_3az_status_set = isisc_port_3az_status_set;
+ p_api->port_3az_status_get = isisc_port_3az_status_get;
+ p_api->interface_mac_mode_set = isisc_interface_mac_mode_set;
+ p_api->interface_mac_mode_get = isisc_interface_mac_mode_get;
+ p_api->interface_phy_mode_set = isisc_interface_phy_mode_set;
+ p_api->interface_phy_mode_get = isisc_interface_phy_mode_get;
+ p_api->interface_fx100_ctrl_set = isisc_interface_fx100_ctrl_set;
+ p_api->interface_fx100_ctrl_get = isisc_interface_fx100_ctrl_get;
+ p_api->interface_fx100_status_get = isisc_interface_fx100_status_get;
+ p_api->interface_mac06_exch_set = isisc_interface_mac06_exch_set;
+ p_api->interface_mac06_exch_get = isisc_interface_mac06_exch_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_ip.c b/src/hsl/isisc/isisc_ip.c
new file mode 100644
index 0000000..8b80c13
--- /dev/null
+++ b/src/hsl/isisc/isisc_ip.c
@@ -0,0 +1,2538 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_ip ISISC_IP
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_ip.h"
+#include "isisc_reg.h"
+
+#define ISISC_HOST_ENTRY_DATA0_ADDR 0x0e80
+#define ISISC_HOST_ENTRY_DATA1_ADDR 0x0e84
+#define ISISC_HOST_ENTRY_DATA2_ADDR 0x0e88
+#define ISISC_HOST_ENTRY_DATA3_ADDR 0x0e8c
+#define ISISC_HOST_ENTRY_DATA4_ADDR 0x0e90
+#define ISISC_HOST_ENTRY_DATA5_ADDR 0x0e94
+#define ISISC_HOST_ENTRY_DATA6_ADDR 0x0e98
+#define ISISC_HOST_ENTRY_DATA7_ADDR 0x0e58
+
+#define ISISC_HOST_ENTRY_REG_NUM 8
+
+#define ISISC_HOST_ENTRY_FLUSH 1
+#define ISISC_HOST_ENTRY_ADD 2
+#define ISISC_HOST_ENTRY_DEL 3
+#define ISISC_HOST_ENTRY_NEXT 4
+#define ISISC_HOST_ENTRY_SEARCH 5
+
+#define ISISC_ENTRY_ARP 3
+
+#define ISISC_INTF_MAC_ADDR_NUM 8
+#define ISISC_INTF_MAC_TBL0_ADDR 0x5a900
+#define ISISC_INTF_MAC_TBL1_ADDR 0x5a904
+#define ISISC_INTF_MAC_TBL2_ADDR 0x5a908
+#define ISISC_INTF_MAC_EDIT0_ADDR 0x02000
+#define ISISC_INTF_MAC_EDIT1_ADDR 0x02004
+#define ISISC_INTF_MAC_EDIT2_ADDR 0x02008
+
+#define ISISC_IP6_BASE_ADDR 0x0470
+
+#define ISISC_HOST_ENTRY_NUM 128
+
+#define ISISC_IP_COUTER_ADDR 0x2b000
+
+static a_uint32_t isisc_mac_snap[SW_MAX_NR_DEV] = { 0 };
+static fal_intf_mac_entry_t isisc_intf_snap[SW_MAX_NR_DEV][ISISC_INTF_MAC_ADDR_NUM];
+
+static void
+_isisc_ip_pt_learn_save(a_uint32_t dev_id, a_uint32_t * status)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ return;
+ }
+
+ *status = (data & 0x7f7f);
+
+ data &= 0xffff8080;
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return;
+}
+
+static void
+_isisc_ip_pt_learn_restore(a_uint32_t dev_id, a_uint32_t status)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ return;
+ }
+
+ data &= 0xffff8080;
+ data |= (status & 0x7f7f);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return;
+}
+
+static sw_error_t
+_isisc_ip_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17C_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static sw_error_t
+_isisc_ip_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+ a_uint32_t counter[2])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ addr = ISISC_IP_COUTER_ADDR + (cnt_id << 3);
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(counter[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr += 4;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+ a_uint32_t busy = 1, i = 0x100, entry, j, try_num;
+ a_uint32_t learn_status = 0;
+ sw_error_t rv;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+ }
+
+ if (i == 0)
+ {
+ return SW_BUSY;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* hardware requirements, we should disable ARP learn at first */
+ /* and maybe we should try several times... */
+ _isisc_ip_pt_learn_save(dev_id, &learn_status);
+ if (learn_status)
+ {
+ try_num = 10;
+ }
+ else
+ {
+ try_num = 1;
+ }
+
+ for (j = 0; j < try_num; j++)
+ {
+ busy = 1;
+ i = 0x1000;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ _isisc_ip_pt_learn_restore(dev_id, learn_status);
+ return rv;
+ }
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+ }
+
+ if (i == 0)
+ {
+ _isisc_ip_pt_learn_restore(dev_id, learn_status);
+ return SW_BUSY;
+ }
+
+ /* hardware requirement, we should read again... */
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ _isisc_ip_pt_learn_restore(dev_id, learn_status);
+ return rv;
+ }
+
+ /* operation success...... */
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+ if (busy)
+ {
+ _isisc_ip_pt_learn_restore(dev_id, learn_status);
+ return SW_OK;
+ }
+ }
+
+ _isisc_ip_pt_learn_restore(dev_id, learn_status);
+ if (ISISC_HOST_ENTRY_NEXT == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if (ISISC_HOST_ENTRY_SEARCH == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else if (ISISC_HOST_ENTRY_DEL == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+}
+
+static sw_error_t
+_isisc_ip_intf_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+ a_uint32_t * hw_intf)
+{
+ sw_error_t rv;
+ a_uint32_t addr, lvid, hvid, tbl[3], i;
+ a_uint32_t sw_intf = entry->intf_id;
+ a_uint32_t vid_offset;
+
+ for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isisc_mac_snap[dev_id] & (0x1 << i))
+ {
+ addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 8;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, hvid, tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, lvid, tbl[2]);
+ hvid |= ((lvid & 0xff) << 4);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl[1]);
+
+ if ((lvid <= sw_intf) && (hvid >= sw_intf))
+ {
+ vid_offset = entry->expect_vid ? (entry->expect_vid - lvid) : (sw_intf - lvid);
+ *hw_intf = (vid_offset << 3) | i;
+ return SW_OK;
+ }
+ }
+ }
+
+ return SW_BAD_PARAM;
+}
+
+static sw_error_t
+_isisc_ip_intf_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_intf,
+ a_uint32_t * sw_intf)
+{
+ sw_error_t rv;
+ a_uint32_t addr, lvid, tbl, i;
+
+ i = hw_intf & 0x7;
+
+ addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + 4;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&tbl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, lvid, tbl);
+ *sw_intf = lvid + (hw_intf >> 3);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (255 < ((*time + 5) / 6))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = ((*time + 5) / 6);
+ *time = data * 6;
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 6;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_sw_to_hw(a_uint32_t dev_id, fal_host_entry_t * entry,
+ a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 0, reg[6]);
+ }
+
+ if (FAL_IP_IP6_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip6_addr.ul[3];
+ reg[1] = entry->ip6_addr.ul[2];
+ reg[2] = entry->ip6_addr.ul[1];
+ reg[3] = entry->ip6_addr.ul[0];
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+ rv = _isisc_ip_intf_sw_to_hw(dev_id, entry/*was:->intf_id*/, &data);
+
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+
+#if 0
+ if (A_TRUE != hsl_port_prop_check(dev_id, entry->port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+#endif
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+ if (FAL_IP_CPU_ADDR & entry->flags)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, CPU_ADDR, 1, reg[5]);
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+
+ if ((A_TRUE == entry->mirror_en) && (FAL_MAC_FRWRD != entry->action))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+ }
+
+ if (FAL_MAC_DROP == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, 7, reg[5]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 1, reg[6]);
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 2, reg[6]);
+ }
+ else
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 0, reg[6]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, ACTION, 3, reg[6]);
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[2];
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, IP_VER, data, reg[6]);
+ if (data)
+ {
+ entry->ip6_addr.ul[0] = reg[3];
+ entry->ip6_addr.ul[1] = reg[2];
+ entry->ip6_addr.ul[2] = reg[1];
+ entry->ip6_addr.ul[3] = reg[0];
+ entry->flags |= FAL_IP_IP6_ADDR;
+ }
+ else
+ {
+ entry->ip4_addr = reg[0];
+ entry->flags |= FAL_IP_IP4_ADDR;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR2, entry->mac_addr.uc[2], reg[4]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR3, entry->mac_addr.uc[3], reg[4]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR4, entry->mac_addr.uc[4], reg[4]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY4, MAC_ADDR5, entry->mac_addr.uc[5], reg[4]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR0, entry->mac_addr.uc[0], reg[5]);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY5, MAC_ADDR1, entry->mac_addr.uc[1], reg[5]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY5, INTF_ID, data, reg[5]);
+ rv = _isisc_ip_intf_hw_to_sw(dev_id, data, &(entry->intf_id));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY5, CPU_ADDR, data, reg[5]);
+ if (data)
+ {
+ entry->flags |= FAL_IP_CPU_ADDR;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_EN, data, reg[6]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, CNT_IDX, entry->counter_id, reg[6]);
+
+ rv = _isisc_ip_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->packet = cnt[0];
+ entry->byte = cnt[1];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_EN, data, reg[6]);
+ if (data)
+ {
+ entry->pppoe_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, PPPOE_IDX, data, reg[6]);
+ entry->pppoe_id = data;
+ }
+ else
+ {
+ entry->pppoe_en = A_FALSE;
+ }
+
+ if (7 == entry->port_id)
+ {
+ entry->port_id = 0;
+ entry->action = FAL_MAC_DROP;
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(HOST_ENTRY6, ACTION, data, reg[6]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+ {
+ if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+ {
+ addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+ }
+ else
+ {
+ addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_host_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+ {
+ if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+ {
+ addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+ }
+ else
+ {
+ addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ }
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, op = ISISC_HOST_ENTRY_FLUSH;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_IP_ENTRY_ID_EN & del_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_IP_ENTRY_IPADDR_EN & del_mode)
+ {
+ op = ISISC_HOST_ENTRY_DEL;
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ }
+
+ if (FAL_IP_IP6_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip6_addr.ul[3];
+ reg[1] = entry->ip6_addr.ul[2];
+ reg[2] = entry->ip6_addr.ul[1];
+ reg[3] = entry->ip6_addr.ul[0];
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+ }
+ }
+
+ if (FAL_IP_ENTRY_INTF_EN & del_mode)
+ {
+ rv = _isisc_ip_intf_sw_to_hw(dev_id, entry->intf_id, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+ }
+
+ if (FAL_IP_ENTRY_PORT_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+ }
+
+ if (FAL_IP_ENTRY_STATUS_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+ }
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, op);
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_IP_ENTRY_IPADDR_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ reg[0] = entry->ip4_addr;
+ }
+ else
+ {
+ reg[0] = entry->ip6_addr.ul[3];
+ reg[1] = entry->ip6_addr.ul[2];
+ reg[2] = entry->ip6_addr.ul[1];
+ reg[3] = entry->ip6_addr.ul[0];
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, IP_VER, 1, reg[6]);
+ }
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP,
+ ISISC_HOST_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+ rv = _isisc_host_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(entry->status))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (®[7]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t idx, data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = ISISC_HOST_ENTRY_NUM - 1;
+ }
+ else
+ {
+ if ((ISISC_HOST_ENTRY_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id;
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+ if (FAL_IP_ENTRY_INTF_EN & next_mode)
+ {
+ rv = _isisc_ip_intf_sw_to_hw(dev_id, entry->intf_id, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_VID, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, INTF_ID, data, reg[5]);
+ }
+
+ if (FAL_IP_ENTRY_PORT_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SP, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY5, SRC_PORT, entry->port_id, reg[5]);
+ }
+
+ if (FAL_IP_ENTRY_STATUS_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, AGE_FLAG, entry->status, reg[6]);
+ }
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(entry, sizeof (fal_host_entry_t));
+
+ rv = _isisc_host_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(entry->status))
+ {
+ return SW_NO_MORE;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x7f;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ rv = _isisc_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ tbl[0] = reg[0];
+ tbl[1] = reg[1];
+ tbl[2] = reg[2];
+ tbl[3] = reg[3];
+ tbl[6] = (reg[6] >> 15) << 15;
+ rv = _isisc_host_down_to_hw(dev_id, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 0, reg[6]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_EN, 1, reg[6]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, CNT_IDX, cnt_id, reg[6]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg[7] = 0x0;
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x7f;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_up_to_sw(dev_id, reg);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 0, reg[6]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_EN, 1, reg[6]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY6, PPPOE_IDX, pppoe_id, reg[6]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ tbl[0] = reg[0];
+ tbl[1] = reg[1];
+ tbl[2] = reg[2];
+ tbl[3] = reg[3];
+ tbl[6] = (reg[6] >> 15) << 15;
+ rv = _isisc_host_down_to_hw(dev_id, tbl);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ reg[7] = 0x0;
+ rv = _isisc_host_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_ARP_LEARN_REQ & flags)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ data &= (~(0x1 << port_id));
+ }
+
+ if (FAL_ARP_LEARN_ACK & flags)
+ {
+ data |= (0x1 << (8 + port_id));
+ }
+ else
+ {
+ data &= (~(0x1 << (8 + port_id)));
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *flags = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL2, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data & (0x1 << port_id))
+ {
+ *flags |= FAL_ARP_LEARN_REQ;
+ }
+
+ if (data & (8 + (0x1 << port_id)))
+ {
+ *flags |= FAL_ARP_LEARN_ACK;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_ARP_LEARN_ALL == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_ARP_LEARN_LOCAL == mode)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ARP_LEARN_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *mode = FAL_ARP_LEARN_ALL;
+ }
+ else
+ {
+ *mode = FAL_ARP_LEARN_LOCAL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NO_SOURCE_GUARD < mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = 0;
+ if (FAL_MAC_IP_GUARD == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_IP_PORT_GUARD == mode)
+ {
+ data = 2;
+ }
+ else if (FAL_MAC_IP_VLAN_GUARD == mode)
+ {
+ data = 3;
+ }
+ else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+ {
+ data = 4;
+ }
+ reg &= (~(0x7 << (port_id * 3)));
+ reg |= ((data & 0x7) << (port_id * 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ if (FAL_NO_SOURCE_GUARD == mode)
+ {
+ data = 0;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, SP_CHECK_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (port_id * 3)) & 0x7;
+
+ *mode = FAL_NO_SOURCE_GUARD;
+ if (1 == data)
+ {
+ *mode = FAL_MAC_IP_GUARD;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_GUARD;
+ }
+ else if (3 == data)
+ {
+ *mode = FAL_MAC_IP_VLAN_GUARD;
+ }
+ else if (4 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ data = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, IP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+ else if (1 == data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NO_SOURCE_GUARD < mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = 0;
+ if (FAL_MAC_IP_GUARD == mode)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_IP_PORT_GUARD == mode)
+ {
+ data = 2;
+ }
+ else if (FAL_MAC_IP_VLAN_GUARD == mode)
+ {
+ data = 3;
+ }
+ else if (FAL_MAC_IP_PORT_VLAN_GUARD == mode)
+ {
+ data = 4;
+ }
+ reg &= (~(0x7 << (port_id * 3)));
+ reg |= ((data & 0x7) << (port_id * 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_PTCTRL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (port_id * 3)) & 0x7;
+
+ *mode = FAL_NO_SOURCE_GUARD;
+ if (1 == data)
+ {
+ *mode = FAL_MAC_IP_GUARD;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_GUARD;
+ }
+ else if (3 == data)
+ {
+ *mode = FAL_MAC_IP_VLAN_GUARD;
+ }
+ else if (4 == data)
+ {
+ *mode = FAL_MAC_IP_PORT_VLAN_GUARD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ data = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_NOT_FOUND,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+ else if (1 == data)
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, L3_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ROUTER_CTRL, 0, ROUTER_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, found = 0, addr, tbl[3] = { 0 };
+ fal_intf_mac_entry_t * intf_entry = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isisc_mac_snap[dev_id] & (0x1 << i))
+ {
+ intf_entry = &(isisc_intf_snap[dev_id][i]);
+ if ((entry->vid_low == intf_entry->vid_low)
+ && (entry->vid_high == intf_entry->vid_high))
+ {
+ /* all same, return OK directly */
+ if (!aos_mem_cmp(intf_entry, entry, sizeof(fal_intf_mac_entry_t)))
+ {
+ return SW_OK;
+ }
+ else
+ {
+ /* update entry */
+ found = 1;
+ break;
+ }
+ }
+ else
+ {
+ /* entry VID cross border, not support */
+ if ((entry->vid_low >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* entry VID cross border, not support */
+ if ((entry->vid_high >= intf_entry->vid_low) && (entry->vid_low <= intf_entry->vid_high))
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+ }
+ }
+
+ if (!found)
+ {
+ for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (!(isisc_mac_snap[dev_id] & (0x1 << i)))
+ {
+ intf_entry = &(isisc_intf_snap[dev_id][i]);
+ break;
+ }
+ }
+ }
+
+ if (ISISC_INTF_MAC_ADDR_NUM == i)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if ((A_FALSE == entry->ip4_route) && (A_FALSE == entry->ip6_route))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (512 <= (entry->vid_high - entry->vid_low))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+ tbl[0]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+ tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+ tbl[1]);
+
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY1, VID_HIGH0, (entry->vid_high & 0xf),
+ tbl[1]);
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, VID_HIGH1, (entry->vid_high >> 4),
+ tbl[2]);
+
+ if (A_TRUE == entry->ip4_route)
+ {
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP4_ROUTE, 1, tbl[2]);
+ }
+
+ if (A_TRUE == entry->ip6_route)
+ {
+ SW_SET_REG_BY_FIELD(INTF_ADDR_ENTRY2, IP6_ROUTE, 1, tbl[2]);
+ }
+
+ for (j = 0; j < 2; j++)
+ {
+ addr = ISISC_INTF_MAC_EDIT0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ for (j = 0; j < 3; j++)
+ {
+ addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ isisc_mac_snap[dev_id] |= (0x1 << i);
+ *intf_entry = *entry;
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t addr, tbl[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(FAL_IP_ENTRY_ID_EN & del_mode))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (ISISC_INTF_MAC_ADDR_NUM <= entry->entry_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* clear valid bits */
+ addr = ISISC_INTF_MAC_TBL2_ADDR + (entry->entry_id << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_mac_snap[dev_id] &= (~(0x1 << entry->entry_id));
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, idx, addr, tbl[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISISC_INTF_MAC_ADDR_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id + 1;
+ }
+ }
+
+ for (i = idx; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+ {
+ if (isisc_mac_snap[dev_id] & (0x1 << i))
+ {
+ break;
+ }
+ }
+
+ if (ISISC_INTF_MAC_ADDR_NUM == i)
+ {
+ return SW_NO_MORE;
+ }
+
+ for (j = 0; j < 3; j++)
+ {
+ addr = ISISC_INTF_MAC_TBL0_ADDR + (i << 4) + (j << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[j])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ aos_mem_zero(entry, sizeof (fal_intf_mac_entry_t));
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR2, entry->mac_addr.uc[2],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR3, entry->mac_addr.uc[3],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR4, entry->mac_addr.uc[4],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY0, MAC_ADDR5, entry->mac_addr.uc[5],
+ tbl[0]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR0, entry->mac_addr.uc[0],
+ tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, MAC_ADDR1, entry->mac_addr.uc[1],
+ tbl[1]);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_LOW, entry->vid_low, tbl[1]);
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY1, VID_HIGH0, j, tbl[1]);
+ entry->vid_high = j & 0xf;
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, VID_HIGH1, j, tbl[2]);
+ entry->vid_high |= ((j & 0xff) << 4);
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP4_ROUTE, j, tbl[2]);
+ if (j)
+ {
+ entry->ip4_route = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(INTF_ADDR_ENTRY2, IP6_ROUTE, j, tbl[2]);
+ if (j)
+ {
+ entry->ip6_route = A_TRUE;
+ }
+
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+#define ISISC_WCMP_ENTRY_MAX_ID 3
+#define ISISC_WCMP_HASH_MAX_NUM 16
+#define ISISC_IP_ENTRY_MAX_ID 127
+
+#define ISISC_WCMP_HASH_TBL_ADDR 0x0e10
+#define ISISC_WCMP_NHOP_TBL_ADDR 0x0e20
+
+static sw_error_t
+_isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+ a_uint32_t i, j, addr, data;
+ a_uint8_t idx, ptr[4] = { 0 }, pos[16] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_WCMP_HASH_MAX_NUM < wcmp->nh_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < wcmp->nh_nr; i++)
+ {
+ if (ISISC_IP_ENTRY_MAX_ID < wcmp->nh_id[i])
+ {
+ return SW_BAD_PARAM;
+ }
+
+ idx = 4;
+ for (j = 0; j < 4; j++)
+ {
+ if (ptr[j] & 0x80)
+ {
+ if ((ptr[j] & 0x7f) == wcmp->nh_id[i])
+ {
+ idx = j;
+ break;
+ }
+ }
+ else
+ {
+ idx = j;
+ }
+ }
+
+ if (4 == idx)
+ {
+ return SW_BAD_PARAM;
+ }
+ else
+ {
+ ptr[idx] = (wcmp->nh_id[i] & 0x7f) | 0x80;
+ pos[i] = idx;
+ }
+ }
+
+ data = 0;
+ for (j = 0; j < 4; j++)
+ {
+ data |= (ptr[j] << (j << 3));
+ }
+
+ addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 0;
+ for (j = 0; j < 16; j++)
+ {
+ data |= (pos[j] << (j << 1));
+ }
+
+ addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, data;
+ a_uint8_t ptr[4] = { 0 }, pos[16] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (ISISC_WCMP_ENTRY_MAX_ID < wcmp_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ wcmp->nh_nr = ISISC_WCMP_HASH_MAX_NUM;
+
+ addr = ISISC_WCMP_NHOP_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 4; i++)
+ {
+ ptr[i] = (data >> (i << 3)) & 0x7f;
+ }
+
+ addr = ISISC_WCMP_HASH_TBL_ADDR + (wcmp_id << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 16; i++)
+ {
+ pos[i] = (data >> (i << 1)) & 0x3;
+ }
+
+ for (i = 0; i < 16; i++)
+ {
+ wcmp->nh_id[i] = ptr[pos[i]];
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_WCMP_HASH_KEY_SIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SIP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_DIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DIP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_SPORT & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_SP, 0, data);
+ }
+
+ if (FAL_WCMP_HASH_KEY_DPORT & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ROUTER_CTRL, WCMP_HAHS_DP, 0, data);
+ }
+
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data, field;
+
+ *hash_mode = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_CTRL, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SIP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_SIP;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DIP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_SP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_SPORT;
+ }
+
+ SW_GET_FIELD_BY_REG(ROUTER_CTRL, WCMP_HAHS_DP, field, data);
+ if (field)
+ {
+ *hash_mode |= FAL_WCMP_HASH_KEY_DPORT;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_ip_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_ip_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_host_entry_commit(dev_id, ISISC_ENTRY_ARP, ISISC_HOST_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_mac_snap[dev_id] = 0;
+ for (i = 0; i < ISISC_INTF_MAC_ADDR_NUM; i++)
+ {
+ addr = ISISC_INTF_MAC_TBL2_ADDR + (i << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Add one host entry to one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry added related interface entry and ip6 base address
+ must be set at first.
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_add(a_uint32_t dev_id, fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_add(dev_id, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For del_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_del(dev_id, del_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For get_mode please refer IP entry operation flags.
+ * @param[in] dev_id device id
+ * @param[in] get_mode get operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_get(dev_id, get_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one host entry from one particular device.
+ * @details Comments:
+ * For ISIS the intf_id parameter in host_entry means vlan id.
+ Before host entry deleted related interface entry and ip6 base address
+ must be set atfirst.
+ For next_mode please refer IP entry operation flags.
+ For get the first entry please set entry id as FAL_NEXT_ENTRY_FIRST_ID
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] host_entry host entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_host_entry_t * host_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_next(dev_id, next_mode, host_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one pppoe session entry to one host entry on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id host entry id
+ * @param[in] pppoe_id pppoe session entry id
+ * @param[in] enable A_TRUE means bind, A_FALSE means unbind
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_host_pppoe_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t pppoe_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_host_pppoe_bind(dev_id, entry_id, pppoe_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_pt_arp_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t flags)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_pt_arp_learn_set(dev_id, port_id, flags);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] flags arp type FAL_ARP_LEARN_REQ and/or FAL_ARP_LEARN_ACK
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_pt_arp_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * flags)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_pt_arp_learn_get(dev_id, port_id, flags);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_learn_set(a_uint32_t dev_id, fal_arp_learn_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_arp_learn_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets type to learn on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode learning mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_learn_get(a_uint32_t dev_id, fal_arp_learn_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_arp_learn_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_source_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_source_guard_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ip packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_source_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_source_guard_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source ip packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when ip source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_unk_source_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source ip packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_unk_source_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_guard_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_arp_guard_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets source guarding mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode source guarding mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_arp_guard_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_source_guard_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_arp_guard_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unkonw source arp packets forwarding command on one particular device.
+ * @details Comments:
+ * This settin is no meaning when arp source guard not enable
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_unk_source_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_arp_unk_source_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unkonw source arp packets forwarding command on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_unk_source_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_arp_unk_source_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_route_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_route_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP unicast routing status on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_route_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_route_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one interface entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_add(a_uint32_t dev_id, fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_intf_entry_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operation mode
+ * @param[in] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_intf_entry_del(dev_id, del_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next one interface entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operation mode
+ * @param[out] entry interface entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_intf_entry_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_intf_mac_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_intf_entry_next(dev_id, next_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP host entry aging time on one particular device.
+ * @details Comments:
+ * This operation will set dynamic entry aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param[in] time aging time
+ * @param[out] time actual aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP host entry aging time on one particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_age_time_get(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP WCMP table one particular device.
+ * @details Comments:
+ * Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[in] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_entry_set(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_wcmp_entry_set(dev_id, wcmp_id, wcmp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP WCMP table one particular device.
+ * @details Comments:
+ * Hardware only support 0 - 15 hash values and 4 different host tables.
+ * @param[in] dev_id device id
+ * @param[in] wcmp_id wcmp entry id
+ * @param[out] wcmp wcmp entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_entry_get(a_uint32_t dev_id, a_uint32_t wcmp_id, fal_ip_wcmp_t * wcmp)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_wcmp_entry_get(dev_id, wcmp_id, wcmp);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[in] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_wcmp_hash_mode_set(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP WCMP hash key mode.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ip_wcmp_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ip_wcmp_hash_mode_get(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_ip_init(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = isisc_ip_reset(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->ip_host_add = isisc_ip_host_add;
+ p_api->ip_host_del = isisc_ip_host_del;
+ p_api->ip_host_get = isisc_ip_host_get;
+ p_api->ip_host_next = isisc_ip_host_next;
+ p_api->ip_host_counter_bind = isisc_ip_host_counter_bind;
+ p_api->ip_host_pppoe_bind = isisc_ip_host_pppoe_bind;
+ p_api->ip_pt_arp_learn_set = isisc_ip_pt_arp_learn_set;
+ p_api->ip_pt_arp_learn_get = isisc_ip_pt_arp_learn_get;
+ p_api->ip_arp_learn_set = isisc_ip_arp_learn_set;
+ p_api->ip_arp_learn_get = isisc_ip_arp_learn_get;
+ p_api->ip_source_guard_set = isisc_ip_source_guard_set;
+ p_api->ip_source_guard_get = isisc_ip_source_guard_get;
+ p_api->ip_unk_source_cmd_set = isisc_ip_unk_source_cmd_set;
+ p_api->ip_unk_source_cmd_get = isisc_ip_unk_source_cmd_get;
+ p_api->ip_arp_guard_set = isisc_ip_arp_guard_set;
+ p_api->ip_arp_guard_get = isisc_ip_arp_guard_get;
+ p_api->arp_unk_source_cmd_set = isisc_arp_unk_source_cmd_set;
+ p_api->arp_unk_source_cmd_get = isisc_arp_unk_source_cmd_get;
+ p_api->ip_route_status_set = isisc_ip_route_status_set;
+ p_api->ip_route_status_get = isisc_ip_route_status_get;
+ p_api->ip_intf_entry_add = isisc_ip_intf_entry_add;
+ p_api->ip_intf_entry_del = isisc_ip_intf_entry_del;
+ p_api->ip_intf_entry_next = isisc_ip_intf_entry_next;
+ p_api->ip_age_time_set = isisc_ip_age_time_set;
+ p_api->ip_age_time_get = isisc_ip_age_time_get;
+ p_api->ip_wcmp_hash_mode_set = isisc_ip_wcmp_hash_mode_set;
+ p_api->ip_wcmp_hash_mode_get = isisc_ip_wcmp_hash_mode_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_leaky.c b/src/hsl/isisc/isisc_leaky.c
new file mode 100644
index 0000000..a94bfc9
--- /dev/null
+++ b/src/hsl/isisc/isisc_leaky.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_leaky ISISC_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_leaky.h"
+#include "isisc_reg.h"
+
+static sw_error_t
+_isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_uc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_uc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_arp_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_arp_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_uc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_uc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_mc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_mc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_leaky_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->uc_leaky_mode_set = isisc_uc_leaky_mode_set;
+ p_api->uc_leaky_mode_get = isisc_uc_leaky_mode_get;
+ p_api->mc_leaky_mode_set = isisc_mc_leaky_mode_set;
+ p_api->mc_leaky_mode_get = isisc_mc_leaky_mode_get;
+ p_api->port_arp_leaky_set = isisc_port_arp_leaky_set;
+ p_api->port_arp_leaky_get = isisc_port_arp_leaky_get;
+ p_api->port_uc_leaky_set = isisc_port_uc_leaky_set;
+ p_api->port_uc_leaky_get = isisc_port_uc_leaky_get;
+ p_api->port_mc_leaky_set = isisc_port_mc_leaky_set;
+ p_api->port_mc_leaky_get = isisc_port_mc_leaky_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_led.c b/src/hsl/isisc/isisc_led.c
new file mode 100644
index 0000000..4b1929f
--- /dev/null
+++ b/src/hsl/isisc/isisc_led.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_led ISISC_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "isisc_led.h"
+#include "isisc_reg.h"
+
+#define MAX_LED_PATTERN_ID 2
+#define LED_PATTERN_ADDR 0x50
+
+static sw_error_t
+_isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, mode;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ mode = 0;
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ mode = 1;
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ mode = 2;
+ }
+ else if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ mode = 3;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+ }
+ else if (LED_BLINK_TXRX == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ reg &= 0xffff;
+ reg |= (data << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= data;
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ if (0 == id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+ }
+ else if (1 == id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L2_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L2_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L2_MODE, mode, data);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, tmp;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((LED_WAN_PORT_GROUP != group) && (LED_LAN_PORT_GROUP != group))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+ addr = LED_PATTERN_ADDR + (id << 2);
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ data = (reg >> 16) & 0xffff;
+ }
+ else
+ {
+ data = reg & 0xffff;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_OFF;
+ }
+ else if (1 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_BLINK;
+ }
+ else if (2 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_ON;
+ }
+ else
+ {
+ pattern->mode = LED_PATTERN_MAP_EN;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->freq = LED_BLINK_2HZ;
+ }
+ else if (1 == tmp)
+ {
+ pattern->freq = LED_BLINK_4HZ;
+ }
+ else if (2 == tmp)
+ {
+ pattern->freq = LED_BLINK_8HZ;
+ }
+ else
+ {
+ pattern->freq = LED_BLINK_TXRX;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+isisc_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_led_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->led_ctrl_pattern_set = isisc_led_ctrl_pattern_set;
+ p_api->led_ctrl_pattern_get = isisc_led_ctrl_pattern_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_mib.c b/src/hsl/isisc/isisc_mib.c
new file mode 100644
index 0000000..6cf8e1a
--- /dev/null
+++ b/src/hsl/isisc/isisc_mib.c
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_mib ISISC_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mib.h"
+#include "isisc_reg.h"
+
+
+#define MIB_FLUSH_ALL_PORTS 0x1
+#define MIB_FLUSH_ONE_PORT 0x2
+#define MIB_AUTOCAST_ALL_PORTS 0x3
+
+static sw_error_t
+_isisc_mib_op_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t mib_busy = 1, i = 0x1000, val;
+ sw_error_t rv;
+
+ while (mib_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+ (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FUNC, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
+ SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, MIB_FUNC, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ mib_busy = 1;
+ i = 0x1000;
+ while (mib_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_BUSY,
+ (a_uint8_t *) (&mib_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXUNICAST, port_id,
+ (a_uint8_t *) (&val), sizeof
+ (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxUniCast = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNICAST, port_id,
+ (a_uint8_t *) (&val), sizeof
+ (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUniCast = val;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MOD_ENABLE, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_CPU_KEEP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ if (port_id>7)
+ return SW_BAD_PARAM;
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_FLUSH_PORT,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ rv = _isisc_mib_op_commit( dev_id, MIB_FLUSH_ONE_PORT);
+
+ return rv;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mib_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mib_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_mib_port_flush_counters(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mib_port_flush_counters(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib cpu keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_cpukeep_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mib_cpukeep_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib keep bit on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mib_cpukeep_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mib_cpukeep_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = isisc_get_mib_info;
+ p_api->mib_status_set = isisc_mib_status_set;
+ p_api->mib_status_get = isisc_mib_status_get;
+ p_api->mib_port_flush_counters = isisc_mib_port_flush_counters;
+ p_api->mib_cpukeep_set = isisc_mib_cpukeep_set;
+ p_api->mib_cpukeep_get = isisc_mib_cpukeep_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_mirror.c b/src/hsl/isisc/isisc_mirror.c
new file mode 100644
index 0000000..01f77e2
--- /dev/null
+++ b/src/hsl/isisc/isisc_mirror.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_mirror ISISC_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_mirror.h"
+#include "isisc_reg.h"
+
+static sw_error_t
+_isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *port_id = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_analysis_port_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_analysis_port_get(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_port_in_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_port_in_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_port_eg_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_mirr_port_eg_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_mirr_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->mirr_analysis_port_set = isisc_mirr_analysis_port_set;
+ p_api->mirr_analysis_port_get = isisc_mirr_analysis_port_get;
+ p_api->mirr_port_in_set = isisc_mirr_port_in_set;
+ p_api->mirr_port_in_get = isisc_mirr_port_in_get;
+ p_api->mirr_port_eg_set = isisc_mirr_port_eg_set;
+ p_api->mirr_port_eg_get = isisc_mirr_port_eg_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_misc.c b/src/hsl/isisc/isisc_misc.c
new file mode 100644
index 0000000..439dd23
--- /dev/null
+++ b/src/hsl/isisc/isisc_misc.c
@@ -0,0 +1,2163 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_misc ISISC_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_misc.h"
+#include "isisc_reg.h"
+#include "f1_phy.h"
+
+#define ISISC_MAX_FRMAE_SIZE 9216
+
+#define ARP_REQ_EN_OFFSET 6
+#define ARP_ACK_EN_OFFSET 5
+#define DHCP_EN_OFFSET 4
+#define EAPOL_EN_OFFSET 3
+
+#define ISISC_SWITCH_INT_PHY_INT 0x8000
+
+
+static sw_error_t
+_isisc_port_misc_property_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << ((port_id << 3) + item));
+ reg |= (val << ((port_id << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= ~(0x1UL << (((port_id - 4) << 3) + item));
+ reg |= (val << (((port_id - 4) << 3) + item));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ }
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_misc_property_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, a_uint32_t item)
+{
+ sw_error_t rv;
+ a_uint32_t reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (3 >= port_id)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> ((port_id << 3) + item)) & 0x1UL;
+ }
+ else
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, FRAME_ACK_CTL1, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (reg >> (((port_id - 4) << 3) + item)) & 0x1UL;
+ }
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_FRMAE_SIZE < size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = size;
+ HSL_REG_FIELD_SET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MAX_SIZE, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *size = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL1, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, CPU_VID_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PKT_CTRL, 0, RTD_PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FRAME_ACK_CTL1, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (0 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+#define ISISC_MAX_PPPOE_SESSION 16
+#define ISISC_MAX_SESSION_ID 0xffff
+
+static sw_error_t
+_isisc_pppoe_session_add(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id, entry_idx = ISISC_MAX_PPPOE_SESSION;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((A_FALSE == session_tbl->multi_session)
+ && (A_TRUE == session_tbl->uni_session))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((A_FALSE == session_tbl->multi_session)
+ && (A_FALSE == session_tbl->uni_session))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (!valid)
+ {
+ entry_idx = i;
+ }
+ else if (id == session_tbl->session_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+
+ if (ISISC_MAX_PPPOE_SESSION == entry_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+#if 0
+ if (A_TRUE == session_tbl->uni_session)
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 2, reg);
+ }
+ else
+#endif
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+ }
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_tbl->session_id,
+ reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ session_tbl->entry_id = entry_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_pppoe_session_del(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_pppoe_session_get(a_uint32_t dev_id, fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_tbl->session_id > ISISC_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < ISISC_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (((1 == valid) || (2 == valid)) && (id == session_tbl->session_id))
+ {
+ if (1 == valid)
+ {
+ session_tbl->multi_session = A_TRUE;
+ session_tbl->uni_session = A_FALSE;
+ }
+ else
+ {
+ session_tbl->multi_session = A_TRUE;
+ session_tbl->uni_session = A_TRUE;
+ }
+
+ session_tbl->entry_id = i;
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (ISISC_MAX_PPPOE_SESSION <= index)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAX_SESSION_ID < id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg = 0;
+ SW_SET_REG_BY_FIELD(PPPOE_EDIT, EDIT_ID, id, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+ a_uint32_t reg, tmp;
+
+ if (ISISC_MAX_PPPOE_SESSION <= index)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_EDIT, index, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ tmp = 0;
+ SW_GET_FIELD_BY_REG(PPPOE_EDIT, EDIT_ID, tmp, reg);
+ *id = tmp;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (intr_mask & FAL_SWITCH_INTR_LINK_STATUS)
+ {
+ reg |= ISISC_SWITCH_INT_PHY_INT;
+ }
+ else
+ {
+ reg &= (~ISISC_SWITCH_INT_PHY_INT);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ *intr_mask = 0;
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_MASK1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (reg & ISISC_SWITCH_INT_PHY_INT)
+ {
+ *intr_mask |= FAL_SWITCH_INTR_LINK_STATUS;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ *intr_status = 0;
+ HSL_REG_ENTRY_GET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (reg & ISISC_SWITCH_INT_PHY_INT)
+ {
+ *intr_status |= FAL_SWITCH_INTR_LINK_STATUS;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ reg = 0;
+ if (intr_status & FAL_SWITCH_INTR_LINK_STATUS)
+ {
+ reg |= ISISC_SWITCH_INT_PHY_INT;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GBL_INT_STATUS1, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_mask_set(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_mask_get(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_link_intr_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_intr_status_get(dev_id, phy_id, intr_mask_flag);
+ return rv;
+}
+
+static sw_error_t
+_isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ data &= (~((a_uint32_t) 0x1 << port_id));
+ }
+ else if (A_TRUE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+
+static sw_error_t
+_isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_MASK1, 0, LINK_CHG_INT_M,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ *port_bitmap = reg;
+
+ return rv;
+
+}
+
+static sw_error_t
+_isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ HSL_REG_FIELD_SET(rv, dev_id, GBL_INT_STATUS1, 0, LINK_CHG_INT_S,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_frame_max_size_set(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_frame_max_size_get(a_uint32_t dev_id, a_uint32_t * size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_frame_max_size_get(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_unk_uc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_unk_uc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_unk_mc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_unk_mc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_bc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_bc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cpu_port_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_port_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cpu_port_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_set(dev_id, port_id, enable, DHCP_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_get(dev_id, port_id, enable, DHCP_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling arp packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_arp_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_arp_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling eapol packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_eapol_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_eapol_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_add(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_session_add(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_del(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_session_del(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * The entry only for pppoe/ppp header remove.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_table_get(a_uint32_t dev_id,
+ fal_pppoe_session_t * session_tbl)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_session_get(dev_id, session_tbl);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set a pppoe session id entry to a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[in] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_id_set(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_session_id_set(dev_id, index, id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session id entry from a particular device.
+ * The entry only for pppoe/ppp header add.
+ * @param[in] dev_id device id
+ * @param[out] session_tbl pppoe session table
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_pppoe_session_id_get(a_uint32_t dev_id, a_uint32_t index,
+ a_uint32_t * id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_pppoe_session_id_get(dev_id, index, id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_set(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_get(dev_id, port_id, enable, EAPOL_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ripv1_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_ripv1_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_ripv1_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_req_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_set(dev_id, port_id, enable,
+ ARP_REQ_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp req packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_req_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_get(dev_id, port_id, enable,
+ ARP_REQ_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_ack_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_set(dev_id, port_id, enable,
+ ARP_ACK_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp ack packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_arp_ack_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_misc_property_get(dev_id, port_id, enable,
+ ARP_ACK_EN_OFFSET);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_set(a_uint32_t dev_id, a_uint32_t intr_mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_intr_mask_set(dev_id, intr_mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt mask on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_mask mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_get(a_uint32_t dev_id, a_uint32_t * intr_mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_intr_mask_get(dev_id, intr_mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_get(a_uint32_t dev_id, a_uint32_t * intr_status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_intr_status_get(dev_id, intr_status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Clear switch interrupt status on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] intr_status status
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_clear(a_uint32_t dev_id, a_uint32_t intr_status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_intr_status_clear(dev_id, intr_status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_mask_set(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t intr_mask_flag)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_link_intr_mask_set(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_mask_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_link_intr_mask_get(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link interrupt status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] intr_mask_flag interrupt mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_port_link_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t * intr_mask_flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_link_intr_status_get(dev_id, port_id, intr_mask_flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable ports intr mask enabled
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_mac_linkchg_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ FAL_API_LOCK;
+ rv = _isisc_intr_mask_mac_linkchg_set(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac link change interrupt mask on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port interrupt mask or not
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_mask_mac_linkchg_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _isisc_intr_mask_mac_linkchg_get(dev_id, port_id, enable);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] ports bitmap which generates interrupt
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_mac_linkchg_get(a_uint32_t dev_id, fal_pbmp_t* port_bitmap)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _isisc_intr_status_mac_linkchg_get(dev_id, port_bitmap);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_vid_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cpu_vid_en_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu vid enable status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_cpu_vid_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_cpu_vid_en_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rtd_pppoe_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rtd_pppoe_en_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get RM_RTD_PPPOE_EN status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rtd_pppoe_en_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rtd_pppoe_en_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Clear link change interrupt status for all ports.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_intr_status_mac_linkchg_clear(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ FAL_API_LOCK;
+ rv = _isisc_intr_status_mac_linkchg_clear(dev_id);
+ FAL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_misc_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->frame_max_size_set = isisc_frame_max_size_set;
+ p_api->frame_max_size_get = isisc_frame_max_size_get;
+ p_api->port_unk_uc_filter_set = isisc_port_unk_uc_filter_set;
+ p_api->port_unk_uc_filter_get = isisc_port_unk_uc_filter_get;
+ p_api->port_unk_mc_filter_set = isisc_port_unk_mc_filter_set;
+ p_api->port_unk_mc_filter_get = isisc_port_unk_mc_filter_get;
+ p_api->port_bc_filter_set = isisc_port_bc_filter_set;
+ p_api->port_bc_filter_get = isisc_port_bc_filter_get;
+ p_api->cpu_port_status_set = isisc_cpu_port_status_set;
+ p_api->cpu_port_status_get = isisc_cpu_port_status_get;
+ p_api->pppoe_cmd_set = isisc_pppoe_cmd_set;
+ p_api->pppoe_cmd_get = isisc_pppoe_cmd_get;
+ p_api->pppoe_status_set = isisc_pppoe_status_set;
+ p_api->pppoe_status_get = isisc_pppoe_status_get;
+ p_api->port_dhcp_set = isisc_port_dhcp_set;
+ p_api->port_dhcp_get = isisc_port_dhcp_get;
+ p_api->arp_cmd_set = isisc_arp_cmd_set;
+ p_api->arp_cmd_get = isisc_arp_cmd_get;
+ p_api->eapol_cmd_set = isisc_eapol_cmd_set;
+ p_api->eapol_cmd_get = isisc_eapol_cmd_get;
+ p_api->pppoe_session_table_add = isisc_pppoe_session_table_add;
+ p_api->pppoe_session_table_del = isisc_pppoe_session_table_del;
+ p_api->pppoe_session_table_get = isisc_pppoe_session_table_get;
+ p_api->pppoe_session_id_set = isisc_pppoe_session_id_set;
+ p_api->pppoe_session_id_get = isisc_pppoe_session_id_get;
+ p_api->eapol_status_set = isisc_eapol_status_set;
+ p_api->eapol_status_get = isisc_eapol_status_get;
+ p_api->ripv1_status_set = isisc_ripv1_status_set;
+ p_api->ripv1_status_get = isisc_ripv1_status_get;
+ p_api->port_arp_req_status_set = isisc_port_arp_req_status_set;
+ p_api->port_arp_req_status_get = isisc_port_arp_req_status_get;
+ p_api->port_arp_ack_status_set = isisc_port_arp_ack_status_set;
+ p_api->port_arp_ack_status_get = isisc_port_arp_ack_status_get;
+ p_api->intr_mask_set = isisc_intr_mask_set;
+ p_api->intr_mask_get = isisc_intr_mask_get;
+ p_api->intr_status_get = isisc_intr_status_get;
+ p_api->intr_status_clear = isisc_intr_status_clear;
+ p_api->intr_port_link_mask_set = isisc_intr_port_link_mask_set;
+ p_api->intr_port_link_mask_get = isisc_intr_port_link_mask_get;
+ p_api->intr_port_link_status_get = isisc_intr_port_link_status_get;
+ p_api->intr_mask_mac_linkchg_set = isisc_intr_mask_mac_linkchg_set;
+ p_api->intr_mask_mac_linkchg_get = isisc_intr_mask_mac_linkchg_get;
+ p_api->intr_status_mac_linkchg_get = isisc_intr_status_mac_linkchg_get;
+ p_api->cpu_vid_en_set = isisc_cpu_vid_en_set;
+ p_api->cpu_vid_en_get = isisc_cpu_vid_en_get;
+ p_api->rtd_pppoe_en_set = isisc_rtd_pppoe_en_set;
+ p_api->rtd_pppoe_en_get = isisc_rtd_pppoe_en_get;
+ p_api->intr_status_mac_linkchg_clear = isisc_intr_status_mac_linkchg_clear;
+
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isisc/isisc_multicast_acl.c b/src/hsl/isisc/isisc_multicast_acl.c
new file mode 100644
index 0000000..88bc707
--- /dev/null
+++ b/src/hsl/isisc/isisc_multicast_acl.c
@@ -0,0 +1,1004 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "fal_nat.h"
+#include "fal_ip.h"
+#include "hsl_api.h"
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_igmp.h"
+#include "isisc_reg.h"
+#include "isisc_acl.h"
+#include "fal_multi.h"
+#include "hsl_shared_api.h"
+#include "sal/os/aos_lock.h"
+
+#if 0
+/**
+ * I/F prototype for complete igmpv3 & mldv2 support
+ */
+
+/*supports 32 entries*/
+#define FAL_IGMP_SG_ENTRY_MAX 32
+
+typedef enum
+{
+ FAL_ADDR_IPV4 = 0,
+ FAL_ADDR_IPV6
+} fal_addr_type_t;
+
+typedef struct
+{
+ fal_addr_type_t type;
+ union
+ {
+ fal_ip4_addr_t ip4_addr;
+ fal_ip6_addr_t ip6_addr;
+ } u;
+} fal_igmp_sg_addr_t;
+
+typedef struct
+{
+ fal_igmp_sg_addr_t source;
+ fal_igmp_sg_addr_t group;
+ fal_pbmp_t port_map;
+} fal_igmp_sg_entry_t;
+
+/**
+ * @brief set PortMap of IGMP sg entry.
+ * search entry according to source/group address,
+ * update PortMap if SG entry is found, otherwise create a new sg entry.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+/**
+ * @brief clear PortMap of IGMP sg entry.
+ * search entry according to source/group address,
+ * update PortMap if SG entry is found, delete the entry in case PortMap was 0.
+ * SW_NOT_FOUND will be returned in case search failed.
+ * @param[in] dev_id device id
+ * @param[in-out] entry SG entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry);
+
+#define MULTI_DEBUG_
+#ifdef MULTI_DEBUG_
+#define MULTI_DEBUG(x...) aos_printk(x)
+#else
+#define MULTI_DEBUG(x...)
+#endif
+
+#define FAL_ACL_LIST_MULTICAST 55
+#define FAL_MULTICAST_PRI 5
+
+#define MULT_ACTION_SET 1
+#define MULT_ACTION_CLEAR 1
+
+static a_uint32_t rule_nr=1;
+
+typedef struct
+{
+ a_uint8_t index; //MAX is 32
+ fal_igmp_sg_entry_t entry; //Stores the specific ACL rule info
+} multi_acl_info_t;
+#endif
+
+static a_uint32_t mul_rule_nr=1;
+
+void
+isisc_multicast_init(a_uint32_t dev_id);
+
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry);
+
+static multi_acl_info_t multi_acl_info[FAL_IGMP_SG_ENTRY_MAX];
+static multi_acl_info_t multi_acl_group[FAL_IGMP_SG_ENTRY_MAX];
+
+static int ip6_addr_is_null(fal_ip6_addr_t *ip6)
+{
+ if (NULL == ip6)
+ {
+ aos_printk("Invalid ip6 address\n");
+ return -1;
+ }
+ if(0 == ip6->ul[0] && 0 == ip6->ul[1] && 0 == ip6->ul[2] && 0 == ip6->ul[3])
+ return 1;
+ else
+ return 0;
+}
+static int multi_source_is_null(fal_igmp_sg_addr_t *s)
+{
+ if (NULL == s)
+ {
+ aos_printk("Invalid source address\n");
+ return -1;
+ }
+ if(0 == s->type && 0==s->u.ip4_addr)
+ return 1;
+ if(1 == s->type && 1 == ip6_addr_is_null(&(s->u.ip6_addr)))
+ return 1;
+
+ return 0;
+}
+
+HSL_LOCAL int iterate_multicast_acl_rule(int list_id, int start_n)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t rule_id;
+ sw_error_t ret;
+ fal_acl_rule_t rule= {0};
+
+ if(start_n>=FAL_IGMP_SG_ENTRY_MAX)
+ {
+ return -1;
+ }
+
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ ret = ACL_RULE_QUERY(dev_id, list_id, rule_id, &rule);
+
+ if (ret==SW_NOT_FOUND )
+ break;//NOT found in ACL rule
+
+ multi_acl_info[rule_id+start_n].index = rule_id; // consider here... index is NOT related start_n
+ //MULTI_DEBUG("normal query1: rule dest_ip4_val=%x, src ip4=%x, dst_ip6=%x, ports=%x\n",
+ //rule.dest_ip4_val, rule.src_ip4_val, rule.dest_ip6_val.ul[0], rule.ports);
+
+ if(rule.dest_ip4_val !=0 && ip6_addr_is_null(&rule.dest_ip6_val)) //only ip4
+ {
+ multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV4;
+ multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV4;
+ multi_acl_info[rule_id+start_n].entry.group.u.ip4_addr = rule.dest_ip4_val;
+ multi_acl_info[rule_id+start_n].entry.source.u.ip4_addr = rule.src_ip4_val;
+ multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+ }
+ else if(rule.dest_ip4_val ==0 && !ip6_addr_is_null(&rule.dest_ip6_val)) //only ip6
+ {
+ multi_acl_info[rule_id+start_n].entry.group.type = FAL_ADDR_IPV6;
+ multi_acl_info[rule_id+start_n].entry.source.type = FAL_ADDR_IPV6;
+ memcpy(&(multi_acl_info[rule_id+start_n].entry.group.u.ip6_addr), &(rule.dest_ip6_val), sizeof(rule.dest_ip6_val));
+ memcpy(&(multi_acl_info[rule_id+start_n].entry.source.u.ip6_addr), &(rule.src_ip6_val), sizeof(rule.src_ip6_val));
+ multi_acl_info[rule_id+start_n].entry.port_map= rule.ports;
+ }
+ }
+
+ return rule_id+start_n;
+}
+/*
+** Iterate the total 32 multicast ACL entries.
+ After the function completes:
+ 1. Stores all multicast related ACL rules in multi_acl_info[32]
+ 2. return the number of multicast related ACL rules
+*/
+HSL_LOCAL a_uint32_t isisc_multicast_acl_query(void)
+{
+ int start_n;
+ int total_n;
+ //a_uint32_t i;
+
+ start_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST, 0);
+ if(-1 == start_n)
+ aos_printk("ACL rule1 is FULL\n");
+ total_n = iterate_multicast_acl_rule(FAL_ACL_LIST_MULTICAST+1, start_n);
+ if(-1 == total_n)
+ aos_printk("ACL rule2 is FULL\n");
+
+ MULTI_DEBUG("KKK, the total ACL rule number is %d, (G,S) number=%d\n", total_n, start_n);
+ /*
+ for(i=0;i<total_n;i++)
+ MULTI_DEBUG("KKK, indx=%d, multi_acl_info[%d].entry=[%d][%x]\n", multi_acl_info[i].index,i,
+ multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip4_addr );
+ */
+
+ return total_n;
+}
+
+HSL_LOCAL a_uint32_t isisc_multicast_acl_total_n(a_uint32_t list_id)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t ret;
+ a_uint32_t rule_id;
+ fal_acl_rule_t rule= {0};
+
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ ret = ACL_RULE_QUERY(dev_id, list_id,
+ rule_id, &rule);
+ if(ret==SW_NOT_FOUND)
+ return rule_id;
+
+ }
+ return 0;
+}
+
+HSL_LOCAL a_uint32_t isisc_acl_multigroup_cmp(fal_igmp_sg_addr_t *group, fal_acl_rule_t* rule)
+{
+ if(group->type == FAL_ADDR_IPV4)
+ return memcmp(&group->u.ip4_addr, &rule->dest_ip4_val, sizeof(rule->dest_ip4_val));
+ else if(group->type == FAL_ADDR_IPV6)
+ return memcmp(group->u.ip6_addr.ul, rule->dest_ip6_val.ul, sizeof(rule->dest_ip6_val));
+
+ return -1;
+}
+
+
+#define ISISC_FILTER_ACT_ADDR 0x5a000
+#define ISISC_FILTER_MSK_ADDR 0x59000
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set_all(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+ a_uint32_t i, base, addr;
+ a_uint32_t dev_id=0;
+ a_uint32_t msk_valid=0;
+ sw_error_t rv;
+
+ /* 2'b00:start; 2'b01:continue; 2'b10:end; 2'b11:start&end*/
+ for(i=pos; i<pos+4; i++)
+ {
+ base = ISISC_FILTER_MSK_ADDR +(i<<5);
+ addr = base+(4<<2); //fifth byte
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&msk_valid),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+ if ((((msk_valid>>6)&0x3) == 0x3) || (((msk_valid>>6)&0x3) == 0x2))
+ {
+ rv = multi_portmap_aclreg_set(i, entry);
+ break;
+ }
+ else if ((((msk_valid>>6)&0x3)) == 0x0 || (((msk_valid>>6)&0x3) == 0x1))
+ {
+ rv = multi_portmap_aclreg_set(i, entry);
+ continue;
+ }
+ else
+ {
+ aos_printk("The rule valid bit:6 7 is wrong!!!");
+ break;
+ }
+ }
+ return rv;
+}
+HSL_LOCAL sw_error_t multi_portmap_aclreg_set(a_uint32_t pos, fal_igmp_sg_entry_t * entry)
+{
+ a_uint32_t i, base, addr;
+ a_uint32_t dev_id=0;
+ sw_error_t rv;
+ a_uint32_t act[3]= {0};
+ fal_pbmp_t pm;
+
+ pm = entry->port_map;
+
+ base = ISISC_FILTER_ACT_ADDR + (pos << 4);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[i]),
+ sizeof (a_uint32_t));
+ //MULTI_DEBUG("2:Get register value 0x%x =%x\n", addr, act[i]);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ act[1] &= ~(0x7<<29); // clear the high 3 bits
+ act[1] |= (pm&0x7)<<29; //the low 3 bits of pm means redirect port 0,1,2
+
+ /* New modification: update acl ACTION register from DENY to redirect */
+ if((act[2]>>6)&0x7 == 0x7 ) //DENY mode
+ {
+ if(pm)
+ {
+ act[2] &= ~(0x7<<6);//clear DENY bits
+ act[2] |= (0x1<<4); //DES_PORT_EN set 1, enable
+ }
+ }
+ else if((act[2]>>4)&0x1 == 0x1) //redirect mode
+ {
+ if(pm==0)
+ {
+ act[2] &= ~(0x1<<4);//clear redirect bits
+ act[2] |= (0x7<<6); //set to DENY
+ }
+ }
+
+ act[2] &= ~0xf; //clear the low 4 bits of port 3,4,5,6
+ act[2] |= (pm>>3)&0xf;
+
+ addr = base + (1<<2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[1]), sizeof (a_uint32_t));
+ addr = base + (2<<2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&act[2]), sizeof (a_uint32_t));
+ MULTI_DEBUG("pos=%d, before sync portmap, the new act=%x %x\n", pos, act[1],act[2]);
+ if((rv = ACL_RULE_SYNC_MULTI_PORTMAP(dev_id, pos, act)) < 0)
+ aos_printk("Sync multicast portmap error\n");
+ return rv;
+}
+
+HSL_LOCAL int multi_get_dp()
+{
+ a_uint32_t addr;
+ a_uint32_t dev_id=0;
+ sw_error_t rv;
+ int val=0;
+
+ addr = 0x624;//GLOBAL_FW_CTRL1
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ val = (val>>24)&0x7f; //30:24, IGMP_JOIN_LEAVE_DP
+
+ return val;
+}
+static int old_bind_p=-1;
+HSL_LOCAL int multi_acl_bind()
+{
+ int bind_p;
+ int i;
+
+ bind_p = multi_get_dp();
+ if(bind_p == old_bind_p)
+ return 0;
+ old_bind_p = bind_p;
+
+ for(i=0; i<6; i++)
+ {
+ ACL_LIST_UNBIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_UNBIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+
+ if(bind_p==0)
+ {
+ for(i=0; i<6; i++)
+ {
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+ }
+ else
+ {
+ for(i=0; i<6; i++)
+ if((bind_p>>i) &0x1)
+ {
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ ACL_LIST_BIND(0, FAL_ACL_LIST_MULTICAST+1, FAL_ACL_DIREC_IN, FAL_ACL_BIND_PORT, i);
+ }
+ else
+ continue;
+ }
+}
+/*
+** Only update the related portmap from the privious input.
+*/
+HSL_LOCAL sw_error_t isisc_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+ a_uint32_t dev_id=0;
+ //a_uint32_t list_pos;
+ a_uint32_t rule_pos;
+ a_uint32_t list_pri;
+ sw_error_t rv;
+
+ //if(entry->port_map < 1 || acl_index<0)
+ if(acl_index<0)
+ aos_printk("Something is wrong...\n");
+
+ if(list_id == FAL_ACL_LIST_MULTICAST) //Update all matched group based acl_rule->source
+ list_pri=FAL_MULTICAST_PRI;
+ else if(list_id == FAL_ACL_LIST_MULTICAST+1) //only update the specific (G,*)entry
+ list_pri=FAL_MULTICAST_PRI+1;
+
+
+ //list_pos = isisc_acl_rule_get_pos(dev_id, list_id, list_pri);
+ rule_pos = ACL_RULE_GET_OFFSET(dev_id, list_id, multi_acl_group[acl_index].index);
+ if(MULT_ACTION_SET == action)
+ {
+ multi_acl_group[acl_index].entry.port_map |= entry->port_map;
+ if(entry->port_map == 0)
+ {
+ multi_acl_group[acl_index].entry.port_map = 0;
+ }
+ }
+ else if(MULT_ACTION_CLEAR == action)
+ multi_acl_group[acl_index].entry.port_map &= ~(entry->port_map);
+
+ rv = multi_portmap_aclreg_set_all(rule_pos, &multi_acl_group[acl_index].entry);
+
+ multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+ return rv;
+}
+
+HSL_LOCAL sw_error_t sw_multicast_acl_update( int list_id, int acl_index, fal_igmp_sg_entry_t * entry, int action)
+{
+ a_uint32_t dev_id=0;
+ a_uint32_t rule_pos;
+ a_uint32_t list_pri;
+
+ if(list_id == FAL_ACL_LIST_MULTICAST) //Update all matched group based acl_rule->source
+ list_pri=FAL_MULTICAST_PRI;
+ else if(list_id == FAL_ACL_LIST_MULTICAST+1) //only update the specific (G,*)entry
+ list_pri=FAL_MULTICAST_PRI+1;
+
+ rule_pos = ACL_RULE_GET_OFFSET(dev_id, list_id, multi_acl_group[acl_index].index);
+
+ MULTI_DEBUG("SW update: rule_pos=%d, index=%d, old portmap=%x\n",
+ rule_pos, acl_index, multi_acl_group[acl_index].entry.port_map);
+ if(MULT_ACTION_SET == action)
+ entry->port_map |= multi_acl_group[acl_index].entry.port_map;
+ else if(MULT_ACTION_CLEAR == action)
+ entry->port_map &= ~multi_acl_group[acl_index].entry.port_map;
+
+ return SW_OK;
+}
+
+
+HSL_LOCAL sw_error_t isisc_multicast_acl_del(int list_id, int index)
+{
+ sw_error_t rv;
+ int rule_id;
+
+ rule_id = multi_acl_group[index].index;
+
+ rv = ACL_RULE_DEL(0, list_id, rule_id, 1);
+ multi_acl_bind(); //Here need extra bind since IGMP join/leave would happen
+}
+
+/*
+** Add new acl rule with parameters: DIP, SIP, redirect port.
+*/
+HSL_LOCAL sw_error_t isisc_multicast_acl_add(int list_id, fal_igmp_sg_entry_t * entry)
+{
+ sw_error_t val;
+ a_uint32_t pos;
+ fal_acl_rule_t acl= {0};
+
+ /* IPv4 multicast */
+ if( entry->group.type == FAL_ADDR_IPV4 )
+ {
+ MULTI_DEBUG("KKK1, group[%d][%x], source[%d][%x]\n",entry->group.type,
+ entry->group.u.ip4_addr, entry->source.type, entry->source.u.ip4_addr);
+
+ acl.rule_type = FAL_ACL_RULE_IP4;
+
+ if(entry->group.u.ip4_addr!= 0)
+ {
+ acl.dest_ip4_val = entry->group.u.ip4_addr;
+ acl.dest_ip4_mask = 0xffffffff;//e->ip.dmsk.s_addr;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+ if(entry->source.u.ip4_addr!= 0)
+ {
+ acl.src_ip4_val = entry->source.u.ip4_addr;
+ acl.src_ip4_mask = 0xffffffff;//e->ip.smsk.s_addr;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+ if( entry->port_map==0 )
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+ else
+ //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+ /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+ if( entry->port_map )
+ {
+ FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+ acl.ports = entry->port_map;
+ }
+ }
+ else if( entry->group.type == FAL_ADDR_IPV6 )
+ {
+ MULTI_DEBUG("KKK2, group[%d][%x], source[%d][%x], pm=%x\n",entry->group.type,
+ entry->group.u.ip6_addr.ul[0], entry->source.type, entry->source.u.ip6_addr.ul[0], entry->port_map);
+
+ acl.rule_type = FAL_ACL_RULE_IP6;
+
+ if(!ip6_addr_is_null(&(entry->group.u.ip6_addr)))
+ {
+ memcpy(&acl.dest_ip6_val, &(entry->group.u.ip6_addr), sizeof(entry->group.u.ip6_addr));
+ acl.dest_ip6_mask.ul[0] = 0xffffffff;
+ acl.dest_ip6_mask.ul[1] = 0xffffffff;
+ acl.dest_ip6_mask.ul[2] = 0xffffffff;
+ acl.dest_ip6_mask.ul[3] = 0xffffffff;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ if(!ip6_addr_is_null(&(entry->source.u.ip6_addr)))
+ {
+ memcpy(&acl.src_ip6_val, &(entry->source.u.ip6_addr), sizeof(entry->source.u.ip6_addr));
+ acl.src_ip6_mask.ul[0] = 0xffffffff;
+ acl.src_ip6_mask.ul[1] = 0xffffffff;
+ acl.src_ip6_mask.ul[2] = 0xffffffff;
+ acl.src_ip6_mask.ul[3] = 0xffffffff;
+ FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+
+ if( entry->port_map==0 )
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_DENY);
+ else
+ //FAL_FIELD_FLG_SET(acl.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ FAL_ACTION_FLG_SET ( acl.action_flg, FAL_ACL_ACTION_PERMIT );
+
+ /* Be careful, _isisc_acl_action_parse() will block FAL_ACL_ACTION_DENY action, So we change it. */
+ if( entry->port_map )
+ {
+ FAL_ACTION_FLG_SET(acl.action_flg, FAL_ACL_ACTION_REDPT);
+ acl.ports = entry->port_map;
+ }
+ }
+
+ pos = isisc_multicast_acl_total_n(list_id);
+
+ MULTI_DEBUG("In isisc_multicast_acl_add, list_id=%d, rule_id=%d\n", list_id, pos);
+ val = ACL_RULE_ADD(0, list_id, pos, mul_rule_nr, &acl);
+
+ multi_acl_bind();
+
+ return val;
+}
+
+
+HSL_LOCAL int iterate_multicast_acl_group(a_uint32_t number, fal_igmp_sg_entry_t * entry)
+{
+ int count=0;
+ int i;
+
+ if (number == 0)
+ return 0; //no any ACL rules based the query
+
+ for(i=0; i<number; i++)
+ {
+
+ /*MULTI_DEBUG("2:iterate_multicast_acl_group, index=%d, multi_acl_info[%d].entry=type[%d]-addr[%x], pm=%x, new entry=type[%d]-addr[%x], pm=%x\n",
+ multi_acl_info[i].index,i, multi_acl_info[i].entry.group.type, multi_acl_info[i].entry.group.u.ip6_addr.ul[0], multi_acl_info[i].entry.port_map,
+ entry->group.type, entry->group.u.ip6_addr.ul[0], entry->port_map);*/
+
+ if(0 == memcmp(&(multi_acl_info[i].entry.group), &(entry->group), sizeof(entry->group)))
+ {
+ memcpy(&multi_acl_group[count], &multi_acl_info[i], sizeof(multi_acl_info[i]));
+ count++;//return the real number of multi_acl_group[]
+ MULTI_DEBUG("in iterate_multicast_acl_group, count=%d, i=%d\n", count, i);
+ }
+ }
+
+ return count;
+}
+
+HSL_LOCAL int mult_acl_has_entry(fal_igmp_sg_addr_t * group, fal_igmp_sg_addr_t *source)
+{
+ int rule_id;
+ int ret = 0;
+#if 0
+ if(source != NULL)
+ {
+ MULTI_DEBUG("new group[%d]= %x %x %x %x, new source[%d]=%x %x %x %x\n",
+ group->type, group->u.ip6_addr.ul[0], group->u.ip6_addr.ul[1], group->u.ip6_addr.ul[2], group->u.ip6_addr.ul[3],
+ source->type, source->u.ip6_addr.ul[0], source->u.ip6_addr.ul[1], source->u.ip6_addr.ul[2], source->u.ip6_addr.ul[3]);
+
+ MULTI_DEBUG("old group[%d]= %x %x %x %x, old source[%d]=%x %x %x %x\n",
+ multi_acl_group[0].entry.group.type, multi_acl_group[0].entry.group.u.ip6_addr.ul[0],
+ multi_acl_group[0].entry.group.u.ip6_addr.ul[1], multi_acl_group[0].entry.group.u.ip6_addr.ul[2], multi_acl_group[0].entry.group.u.ip6_addr.ul[3],
+ multi_acl_group[0].entry.source.type, multi_acl_group[0].entry.source.u.ip6_addr.ul[0],
+ multi_acl_group[0].entry.source.u.ip6_addr.ul[1], multi_acl_group[0].entry.source.u.ip6_addr.ul[2], multi_acl_group[0].entry.source.u.ip6_addr.ul[3]);
+ }
+#endif
+ if(source == NULL)
+ {
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+ (multi_source_is_null(&multi_acl_group[rule_id].entry.source)))
+ {
+ MULTI_DEBUG("Source=0:Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+ ret = rule_id+1; // ensure the return value is the actually number of entry
+ break;
+ }
+ }
+ }
+ else
+ {
+ for(rule_id=0; rule_id<FAL_IGMP_SG_ENTRY_MAX; rule_id++)
+ {
+ if( (0==memcmp(&multi_acl_group[rule_id].entry.group, group, sizeof(fal_igmp_sg_addr_t))) &&
+ (0==memcmp(&multi_acl_group[rule_id].entry.source, source, sizeof(fal_igmp_sg_addr_t))))
+ {
+ MULTI_DEBUG("Orignal ACL rule have this entry! rule id= %d\n", rule_id);
+ ret = rule_id+1; // ensure the return value is the actually number of entry
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+HSL_LOCAL int portmap_null(int index, fal_pbmp_t portmap)
+{
+ int val;
+ if (index<0)
+ aos_printk("portmap_null, index error\n");
+
+ val = multi_acl_group[index].entry.port_map&(~portmap);
+
+ if( 0 == (val&0xff) )
+ return 1;
+ else
+ return 0;
+}
+
+HSL_LOCAL int portmap_valid(fal_igmp_sg_entry_t *g_source, fal_igmp_sg_entry_t *g_star)
+{
+ /* return 0 means the portmap is Not valid
+ return 1 means the protmap is valid
+ */
+ /* MULTI_DEBUG("portmap_valid:g_source portmap=%x, source=%x,group=%x, g_star portmap=%x, source=%x, group=%x\n",
+ g_source->port_map, g_source->source.u.ip4_addr, g_source->group.u.ip4_addr,
+ g_star->port_map, g_star->source.u.ip4_addr,g_star->group.u.ip4_addr);*/
+
+ if(multi_source_is_null(&(g_star->source)))
+ {
+ if((g_source->port_map|g_star->port_map) == g_star->port_map)
+ {
+ return 0;
+ }
+ }
+
+ return 1;
+}
+
+
+HSL_LOCAL int portmap_clear_type(int count, int index, fal_pbmp_t portmap)
+{
+ if(count>=0 && index<count) //new_index must >0; this means there're (G,*) and (G,S)
+ {
+ //if the new clear portmap will cause (G,S)=(G,*), Delete the (G,S)
+ if((multi_acl_group[index].entry.port_map & (~portmap)) == multi_acl_group[count].entry.port_map)
+ return 1; //delete
+
+
+ //The following means there must be at least one bit clear wrong. Clear the (G,*) portmap.
+ if( ((multi_acl_group[index].entry.port_map & (~portmap)) & (multi_acl_group[count].entry.port_map))
+ != (multi_acl_group[count].entry.port_map))
+ return 0;
+
+ return 2; //Normal update
+ }
+ ;
+}
+sw_error_t isisc_igmp_sg_entry_set(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ HSL_API_LOCK;
+ int number, count;
+ int new_index=0;
+ int tmp_index=0;
+ sw_error_t rv;
+ int action = MULT_ACTION_SET;
+ fal_igmp_sg_entry_t tmp_entry[1]= {};
+ int i=0;
+
+ (void)isisc_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ MULTI_DEBUG("Before query: group=%x, source=%x, portmap=%x\n", entry->group.u.ip4_addr, entry->source.u.ip4_addr, entry->port_map);
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isisc_multicast_acl_query();
+ //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+ count = iterate_multicast_acl_group(number, entry);
+ //new_index-1 is the found entry index in multi_acl_group[], the real index is [new_index-1], 0 means no entry
+ new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+ MULTI_DEBUG("Start entry set: number=%d, count=%d, new_index=%d, pm=%x\n", number, count, new_index, entry->port_map);
+ if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S)
+ {
+ MULTI_DEBUG("the new entry is (G,S)\n");
+ if(count>0 && 0 == portmap_valid(entry, &(multi_acl_group[count-1].entry))) //specfic group entry exist,(G,S) or (G,*)
+ {
+ //return SW_NO_CHANGE; // The new portmap is Not valid
+ MULTI_DEBUG("KKK, modified 1 !!!\n");
+ }
+
+ if(0 == new_index) //new entry, need add
+ {
+#if 0
+ /*The method:
+ 1. predict if the portmap should be modified.
+ 2. add new acl rule with new portmap value.
+ */
+ if((tmp_index = mult_acl_has_entry(&entry->group, NULL))>0) // (G, *) entry exist
+ {
+ /*Here the update should new (G, S) OR orignal (G,*) portmap,
+ be careful, entry's portmap value will be modified, so I use tmp_entry.
+ */
+ memcpy(tmp_entry, entry, sizeof(fal_igmp_sg_entry_t));
+ MULTI_DEBUG("Here, (G,*) exist! tmp_index=%d\n", tmp_index);
+ sw_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, tmp_index-1, tmp_entry, action);
+
+ isisc_multicast_acl_add(FAL_ACL_LIST_MULTICAST, tmp_entry);
+ return SW_OK;
+ }
+#endif
+ isisc_multicast_acl_add(FAL_ACL_LIST_MULTICAST, entry);
+ MULTI_DEBUG("Here, need add (G, S), portmap=%x\n", entry->port_map);
+ return SW_OK;
+ }
+ else
+ {
+ //Here update Just: the old exist entry portmap OR the new entry portmap
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ return SW_OK;
+ }
+ } //end of memcmp
+ else // new entry is (G, *)
+ {
+ if(0 == new_index) //new entry, need add
+ {
+ isisc_multicast_acl_add(FAL_ACL_LIST_MULTICAST+1, entry);
+ rv = SW_OK;
+ }
+ else if(new_index > 0) // (G, *) entry exist?
+ {
+ //Update exist (G, *) portmap with new portmap
+ MULTI_DEBUG("(G,*) exist, before update, new_index=%d\n", new_index );
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+ rv = SW_OK;
+ }
+
+ if(new_index>0&&count>1) //(G,S*) and (G,*) exist, new entry is (G,*)
+ {
+ for(i=count-2; i>=0; i--)
+ {
+ if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+ continue;
+
+ if(0 == portmap_valid(&(multi_acl_group[i].entry), &(multi_acl_group[count-1].entry)))
+ {
+ MULTI_DEBUG("1:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+ i, multi_acl_group[i].entry.port_map, multi_acl_group[count-1].entry.port_map);
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("1:Start update all (G,S),i=%d, gstar portmap=%x\n", i, multi_acl_group[count-1].entry.port_map);
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+ else if(new_index==0&&count>0) //only exist (G,S*) orignally
+ {
+ for(i=count-1; i>=0; i--)
+ {
+ if(multi_acl_group[i].entry.port_map==0) //This ACL rule should be done nothing, DENY rule
+ continue;
+
+ if(0 == portmap_valid(&(multi_acl_group[i].entry), entry))
+ {
+ MULTI_DEBUG("2:portmap is not valid, should delete, i=%d, source portmap=%x, gstar pm=%x\n",
+ i, multi_acl_group[i].entry.port_map, entry->port_map);
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("2:Start update all (G,S),i=%d, portmap=%x\n", i, entry->port_map);
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+ }
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t isisc_igmp_sg_entry_clear(a_uint32_t dev_id, fal_igmp_sg_entry_t * entry)
+{
+ HSL_API_LOCK;
+ a_uint32_t number, count;
+ int new_index=0;
+ sw_error_t rv;
+ int action= MULT_ACTION_CLEAR;
+ int i=0;
+ int pm_type;
+
+ (void)isisc_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isisc_multicast_acl_query();
+ //count the total specific multicast group ACL rules, stores in multi_acl_group[]; count <=number
+ count = iterate_multicast_acl_group(number, entry);
+ //new_index-1 is the found entry index in multi_acl_group[]
+ new_index = mult_acl_has_entry(&entry->group, &entry->source);
+
+ MULTI_DEBUG("Start entry clear: number=%d, count=%d, new_index=%d\n", number, count, new_index);
+ if(0 == new_index) //new entry, the user command is wrong
+ {
+ return SW_NO_SUCH;
+ }
+
+ if( 0==multi_source_is_null(&entry->source) ) // new entry is (G, S)
+ {
+ if (portmap_null(new_index-1, entry->port_map))
+ {
+ MULTI_DEBUG("KKK entry clear, new(G,S), with null portmap. \n");
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+ return SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("KKK entry clear, new(G,S), with NOT null portmap. \n");
+ /* If (G,*) doesn't exist, [count-1] is the last specfic group, maybe(G,*) */
+ if(0 == multi_source_is_null(&(multi_acl_group[count-1].entry.source)))
+ {
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ }
+ else //(G,*) exist
+ {
+ pm_type = portmap_clear_type(count-1, new_index-1, entry->port_map);
+ if(pm_type == 0)
+ return SW_NO_CHANGE;
+ else if(pm_type == 1)
+ {
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, new_index-1);
+ return SW_NO_MORE;
+ }
+ else
+ {
+ //normal update; consider here...wangson
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, new_index-1, entry, action);
+ }
+ }
+ }
+ return SW_OK;
+ }
+ else //clear entry is (G,*)
+ {
+ MULTI_DEBUG("Here, new_index[%d]>=0, new portmap to clear is %x\n", new_index, entry->port_map);
+ if (portmap_null(new_index-1, entry->port_map))
+ {
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST+1, new_index-1);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ MULTI_DEBUG("Update (G,*)!, new_index=%d, pm=%x\n", new_index, entry->port_map);
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST+1, new_index-1, entry, action);
+ }
+ MULTI_DEBUG("KKK, ready clear (G, S*), count=%d\n", count);
+#if 0
+ if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+ {
+ //count must >=2
+ for(i=count-2; i>=0; i--)
+ {
+ if(portmap_null(i, entry->port_map))
+ {
+ MULTI_DEBUG("portmap_null, i=%d\n", i);
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ rv = SW_NO_MORE;
+ }
+ else
+ {
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+ }
+#else
+ if(count>1) // (G, S*) entry exist, if count=1 here, only exist(G,*)entry
+ {
+ //count must >=2
+ for(i=count-2; i>=0; i--)
+ {
+ //PortMap of entry (S,G) == (*,G) portmap after clear?
+ if((multi_acl_group[new_index-1].entry.port_map&(~(entry->port_map))) ==
+ multi_acl_group[i].entry.port_map)
+ isisc_multicast_acl_del(FAL_ACL_LIST_MULTICAST, i);
+ else
+ //Update all (G,S) entry portmap with new(G, *) portmap
+ isisc_multicast_acl_update(FAL_ACL_LIST_MULTICAST, i, entry, action);
+ rv = SW_OK;
+ }
+ }
+#endif
+ }
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+static void
+print_ip4addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip4_addr_t ip4;
+
+ ip4 = *((fal_ip4_addr_t *) buf);
+ aos_printk("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+ }
+ aos_printk("%d", (ip4 & 0xff));
+}
+static void
+print_ip6addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip6_addr_t ip6;
+
+ ip6 = *(fal_ip6_addr_t *) buf;
+ aos_printk("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ aos_printk("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+ }
+ aos_printk("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+sw_error_t isisc_igmp_sg_entry_show(a_uint32_t dev_id)
+{
+ HSL_API_LOCK;
+ a_uint32_t number;
+ int i;
+
+ (void)isisc_multicast_init(0);
+ aos_mem_zero(multi_acl_info, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ aos_mem_zero(multi_acl_group, FAL_IGMP_SG_ENTRY_MAX * sizeof (multi_acl_info_t));
+ //number is the total multicast ACL rules amount, stores in multi_acl_info[];
+ number = isisc_multicast_acl_query();
+
+ for(i=0; i<number; i++)
+ {
+ if(0 == multi_acl_info[i].entry.group.type) //ipv4
+ {
+ aos_printk("\n[%d]:", i);
+ print_ip4addr(" [Group IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip4_addr), sizeof (fal_ip4_addr_t));
+ print_ip4addr(" [Source IPv4 addr]:", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip4_addr), sizeof (fal_ip4_addr_t));
+ aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+ }
+ else if(1 == multi_acl_info[i].entry.group.type) //ipv6
+ {
+ aos_printk("\n[%d]:", i);
+ print_ip6addr(" [Group IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.group.u.ip6_addr), sizeof (fal_ip6_addr_t));
+ print_ip6addr(" [Source IPv6 addr]: ", (a_uint32_t *)&(multi_acl_info[i].entry.source.u.ip6_addr), sizeof (fal_ip6_addr_t));
+ aos_printk(" [Portmap]: 0x%x ", multi_acl_info[i].entry.port_map);
+ }
+
+ }
+ aos_printk("\n\nTotal %d multicast ACL rules.\n", number);
+ HSL_API_UNLOCK;
+
+ return SW_OK;
+}
+
+void
+isisc_multicast_init(a_uint32_t dev_id)
+{
+ sw_error_t val;
+
+ ACL_STATUS_SET(0, 1);
+
+ val = ACL_LIST_CREATE(0, FAL_ACL_LIST_MULTICAST, FAL_MULTICAST_PRI);
+ if(val !=SW_OK && val != SW_ALREADY_EXIST)
+ aos_printk("Multicast 1 acl list create error, val=%d\n", val);
+
+ val = ACL_LIST_CREATE(0, FAL_ACL_LIST_MULTICAST+1, FAL_MULTICAST_PRI+1);
+ if(val !=SW_OK && val != SW_ALREADY_EXIST)
+ aos_printk("Multicast 2 acl list create error, val=%d\n", val);
+
+}
+
diff --git a/src/hsl/isisc/isisc_nat.c b/src/hsl/isisc/isisc_nat.c
new file mode 100644
index 0000000..7335665
--- /dev/null
+++ b/src/hsl/isisc/isisc_nat.c
@@ -0,0 +1,2417 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_ip ISISC_NAT
+ * @{
+ */
+
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_nat.h"
+#include "isisc_reg.h"
+
+#define ISISC_HOST_ENTRY_DATA0_ADDR 0x0e80
+#define ISISC_HOST_ENTRY_DATA1_ADDR 0x0e84
+#define ISISC_HOST_ENTRY_DATA2_ADDR 0x0e88
+#define ISISC_HOST_ENTRY_DATA3_ADDR 0x0e8c
+#define ISISC_HOST_ENTRY_DATA4_ADDR 0x0e90
+#define ISISC_HOST_ENTRY_DATA5_ADDR 0x0e94
+#define ISISC_HOST_ENTRY_DATA6_ADDR 0x0e98
+#define ISISC_HOST_ENTRY_DATA7_ADDR 0x0e58
+
+#define ISISC_HOST_ENTRY_REG_NUM 8
+
+#define ISISC_NAT_ENTRY_FLUSH 1
+#define ISISC_NAT_ENTRY_ADD 2
+#define ISISC_NAT_ENTRY_DEL 3
+#define ISISC_NAT_ENTRY_NEXT 4
+#define ISISC_NAT_ENTRY_SEARCH 5
+
+#define ISISC_ENTRY_NAPT 0
+#define ISISC_ENTRY_NAT 2
+#define ISISC_ENTRY_ARP 3
+
+#define ISISC_PUB_ADDR_NUM 16
+#define ISISC_PUB_ADDR_TBL0_ADDR 0x5aa00
+#define ISISC_PUB_ADDR_TBL1_ADDR 0x5aa04
+#define ISISC_PUB_ADDR_EDIT0_ADDR 0x02100
+#define ISISC_PUB_ADDR_EDIT1_ADDR 0x02104
+#define ISISC_PUB_ADDR_OFFLOAD_ADDR 0x2f000
+#define ISISC_PUB_ADDR_VALID_ADDR 0x2f040
+
+#define ISISC_NAT_ENTRY_NUM 32
+#define ISISC_NAPT_ENTRY_NUM 1024
+
+#define ISISC_NAT_COUTER_ADDR 0x2b000
+
+#define ISISC_NAT_PORT_NUM 255
+
+static a_uint32_t isisc_nat_snap[SW_MAX_NR_DEV] = { 0 };
+
+static sw_error_t
+_isisc_nat_feature_check(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, DEVICE_ID,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (S17C_DEVICE_ID == entry)
+ {
+ return SW_OK;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+}
+
+static sw_error_t
+_isisc_ip_prvaddr_sw_to_hw(a_uint32_t dev_id, fal_ip4_addr_t sw_addr,
+ a_uint32_t * hw_addr)
+{
+ /*
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data) {
+ *hw_addr = (sw_addr & 0xff) | (((sw_addr >> 16) & 0xf) << 8);
+ } else {
+ *hw_addr = sw_addr & 0xfff;
+ }
+ */
+ *hw_addr = sw_addr;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_ip_prvaddr_hw_to_sw(a_uint32_t dev_id, a_uint32_t hw_addr,
+ fal_ip4_addr_t * sw_addr)
+{
+ /*
+ sw_error_t rv;
+ a_uint32_t data, addr;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&addr), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data) {
+ *sw_addr = ((addr & 0xff) << 8) | (((addr >> 8) & 0xfff) << 8)
+ | (hw_addr & 0xff) | (((hw_addr >> 8) & 0xf) << 16);
+ } else {
+ *sw_addr = (addr << 12) | (hw_addr & 0xfff);
+ }
+ */
+ *sw_addr = hw_addr;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_counter_get(a_uint32_t dev_id, a_uint32_t cnt_id,
+ a_uint32_t counter[4])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ addr = ISISC_NAT_COUTER_ADDR + (cnt_id << 4);
+ for (i = 0; i < 4; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(counter[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr += 4;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_entry_commit(a_uint32_t dev_id, a_uint32_t entry_type, a_uint32_t op)
+{
+ a_uint32_t busy = 1, i = 0x100, entry;
+ sw_error_t rv;
+
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+ }
+
+ if (i == 0)
+ {
+ return SW_BUSY;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_SEL, entry_type, entry);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, op, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 0x1000;
+ while (busy && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_BUSY, busy, entry);
+#if 1
+ if(ISISC_NAT_ENTRY_SEARCH == op && busy) break;
+#endif
+ }
+
+ if (i == 0)
+ {
+ return SW_BUSY;
+ }
+
+ /* hardware requirement, we should delay... */
+ if ((ISISC_NAT_ENTRY_FLUSH == op) && (ISISC_ENTRY_NAPT == entry_type))
+ {
+ aos_mdelay(10);
+ }
+
+ /* hardware requirement, we should read again... */
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, busy, entry);
+ if (!busy)
+ {
+ if (ISISC_NAT_ENTRY_NEXT == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if (ISISC_NAT_ENTRY_SEARCH == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_sw_to_hw(a_uint32_t dev_id, fal_nat_entry_t * entry, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg[0] = entry->trans_addr;
+
+ if (FAL_NAT_ENTRY_PORT_CHECK & entry->flags)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_RANGE, entry->port_range, reg[1]);
+ if (ISISC_NAT_PORT_NUM < entry->port_range)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PORT_NUM, entry->port_num, reg[1]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY3, PORT_EN, 0, reg[3]);
+ }
+
+ rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, PRV_IPADDR1, (data >> 8), reg[2]);
+
+ if (FAL_MAC_FRWRD == entry->action)
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 0, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 3, reg[2]);
+ }
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 2, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, ACTION, 1, reg[2]);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_PROTOCOL_ANY & entry->flags)
+ {
+ data = 3;
+ }
+ else if ((FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ && (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags))
+ {
+ data = 2;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, HASH_KEY, entry->slct_idx, reg[2]);
+
+ SW_SET_REG_BY_FIELD(NAT_ENTRY3, ENTRY_VALID, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[], fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[4];
+
+ entry->trans_addr = reg[0];
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY3, PORT_EN, data, reg[3]);
+ if (data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PORT_CHECK;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_RANGE, data, reg[1]);
+ entry->port_range = data;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PORT_NUM, data, reg[1]);
+ entry->port_num = data;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY1, PRV_IPADDR0, data, reg[1]);
+ entry->src_addr = data;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, PRV_IPADDR1, data, reg[2]);
+ data = (entry->src_addr & 0xff) | (data << 8);
+
+ rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, ACTION, data, reg[2]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_EN, data, reg[2]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, CNT_IDX, entry->counter_id, reg[2]);
+
+ rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->ingress_packet = cnt[0];
+ entry->ingress_byte = cnt[1];
+ entry->egress_packet = cnt[2];
+ entry->egress_byte = cnt[3];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY3, PRO_TYP, data, reg[3]);
+ if (3 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_ANY;
+ }
+ else if (2 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (1 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (0 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ }
+
+ SW_GET_FIELD_BY_REG(NAT_ENTRY2, HASH_KEY, data, reg[2]);
+ entry->slct_idx = data;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_sw_to_hw(a_uint32_t dev_id, fal_napt_entry_t * entry,
+ a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ reg[0] = entry->dst_addr;
+
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+ rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+
+ if (!(FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags))
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+ if (FAL_MAC_FRWRD == entry->action)
+ {
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 0, reg[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 3, reg[3]);
+ }
+ }
+ else if (FAL_MAC_CPY_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 2, reg[3]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->action)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, ACTION, 1, reg[3]);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+ }
+
+ data = 2;
+ if (FAL_NAT_ENTRY_PROTOCOL_TCP & entry->flags)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_UDP & entry->flags)
+ {
+ data = 1;
+ }
+ else if (FAL_NAT_ENTRY_PROTOCOL_PPTP & entry->flags)
+ {
+ data = 3;
+ }
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_hw_to_sw(a_uint32_t dev_id, a_uint32_t reg[],
+ fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, cnt[4];
+
+ entry->dst_addr = reg[0];
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY1, DST_PORT, entry->dst_port, reg[1]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY1, SRC_PORT, entry->src_port, reg[1]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_PORT, entry->trans_port, reg[2]);
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, SRC_IPADDR0, data, reg[2]);
+ entry->src_addr = data;
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, SRC_IPADDR1, data, reg[3]);
+ data = (entry->src_addr & 0xfff) | (data << 12);
+ rv = _isisc_ip_prvaddr_hw_to_sw(dev_id, data, &(entry->src_addr));
+ SW_RTN_ON_ERROR(rv);
+
+ entry->flags |= FAL_NAT_ENTRY_TRANS_IPADDR_INDEX;
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, ACTION, data, reg[3]);
+ entry->action = FAL_MAC_FRWRD;
+ if (0 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+ else if (2 == data)
+ {
+ entry->action = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (1 == data)
+ {
+ entry->action = FAL_MAC_RDT_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_EN, data, reg[3]);
+ if (data)
+ {
+ entry->counter_en = A_TRUE;
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, CNT_IDX, entry->counter_id, reg[3]);
+
+ rv = _isisc_nat_counter_get(dev_id, entry->counter_id, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ entry->ingress_packet = cnt[0];
+ entry->ingress_byte = cnt[1];
+ entry->egress_packet = cnt[2];
+ entry->egress_byte = cnt[3];
+ }
+ else
+ {
+ entry->counter_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY3, PROT_TYP, data, reg[3]);
+ if (0 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_TCP;
+ }
+ else if (1 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_UDP;
+ }
+ else if (3 == data)
+ {
+ entry->flags |= FAL_NAT_ENTRY_PROTOCOL_PPTP;
+ }
+
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+ {
+ if((ISISC_HOST_ENTRY_REG_NUM - 1) == i)
+ {
+ addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+ }
+ else
+ {
+ addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+ a_uint32_t i, addr;
+
+ for (i = 0; i < ISISC_HOST_ENTRY_REG_NUM; i++)
+ {
+ if((ISISC_HOST_ENTRY_REG_NUM -1) == i)
+ {
+ addr = ISISC_HOST_ENTRY_DATA7_ADDR;
+ }
+ else
+ {
+ addr = ISISC_HOST_ENTRY_DATA0_ADDR + (i << 2);
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®[i]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < ISISC_NAT_ENTRY_NUM; i++)
+ {
+ if (!(isisc_nat_snap[dev_id] & (0x1 << i)))
+ {
+ break;
+ }
+ }
+
+ if (ISISC_NAT_ENTRY_NUM == i)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ entry->entry_id = i;
+
+ rv = _isisc_nat_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_nat_snap[dev_id] |= (0x1 << i);
+ entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, ENTRY_FUNC, ISISC_NAT_ENTRY_DEL, reg[7]);
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_nat_snap[dev_id] &= (~(0x1 << entry->entry_id));
+ }
+ else
+ {
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_nat_snap[dev_id] = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_nat_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (!(isisc_nat_snap[dev_id] & (0x1 << entry->entry_id)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_hw_to_sw(dev_id, reg, entry);
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ a_uint32_t i, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == nat_entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISISC_NAT_ENTRY_NUM - 1) == nat_entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = nat_entry->entry_id + 1;
+ }
+ }
+
+ for (i = idx; i < ISISC_NAT_ENTRY_NUM; i++)
+ {
+ if (isisc_nat_snap[dev_id] & (0x1 << i))
+ {
+ break;
+ }
+ }
+
+ if (ISISC_NAT_ENTRY_NUM == i)
+ {
+ return SW_NO_MORE;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, i, reg[7]);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+
+ rv = _isisc_nat_hw_to_sw(dev_id, reg, nat_entry);
+ SW_RTN_ON_ERROR(rv);
+
+ nat_entry->entry_id = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(isisc_nat_snap[dev_id] & (0x1 << entry_id)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry_id, reg[7]);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 0, reg[2]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_EN, 1, reg[2]);
+ SW_SET_REG_BY_FIELD(NAT_ENTRY2, CNT_IDX, cnt_id, reg[2]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* needn't set TBL_IDX, keep hardware register value */
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ /* needn't set TBL_IDX, keep hardware register value */
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAT_ENTRY_ID_EN & del_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_NAT_ENTRY_KEY_EN & del_mode)
+ {
+ rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+ }
+ else
+ {
+ if (FAL_NAT_ENTRY_PUBLIC_IP_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, entry->trans_addr, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_SOURCE_IP_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+ rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+ }
+
+ if (FAL_NAT_ENTRY_AGE_EN & del_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, entry->status, reg[4]);
+ }
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH);
+ return rv;
+ }
+}
+
+static sw_error_t
+_isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode, fal_napt_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t found, age, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#if 0
+ if (FAL_NAT_ENTRY_ID_EN != get_mode)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+#else
+ rv = _isisc_napt_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_SEARCH);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, found, reg[7]);
+ SW_GET_FIELD_BY_REG(NAPT_ENTRY4, AGE_FLAG, age, reg[4]);
+ if (found && age)
+ {
+ found = 1;
+ }
+ else
+ {
+ found = 0;
+ }
+
+ rv = _isisc_napt_hw_to_sw(dev_id, reg, entry);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!found)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ a_uint32_t data, idx, reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 };
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == napt_entry->entry_id)
+ {
+ idx = ISISC_NAPT_ENTRY_NUM - 1;
+ }
+ else
+ {
+ if ((ISISC_NAPT_ENTRY_NUM - 1) == napt_entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = napt_entry->entry_id;
+ }
+ }
+
+ if (FAL_NAT_ENTRY_PUBLIC_IP_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_PIP, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, TRANS_IPADDR, napt_entry->trans_addr, reg[2]);
+ }
+
+ if (FAL_NAT_ENTRY_SOURCE_IP_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_SIP, 1, reg[7]);
+ rv = _isisc_ip_prvaddr_sw_to_hw(dev_id, napt_entry->src_addr, &data);
+ SW_RTN_ON_ERROR(rv);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY2, SRC_IPADDR0, (data & 0xfff), reg[2]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, SRC_IPADDR1, (data >> 12), reg[3]);
+ }
+
+ if (FAL_NAT_ENTRY_AGE_EN & next_mode)
+ {
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, SPEC_STATUS, 1, reg[7]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY4, AGE_FLAG, napt_entry->status, reg[4]);
+ }
+
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, idx, reg[7]);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(napt_entry, sizeof (fal_nat_entry_t));
+
+ rv = _isisc_napt_hw_to_sw(dev_id, reg, napt_entry);
+ SW_RTN_ON_ERROR(rv);
+
+#if 0
+ a_uint32_t temp=0, complete=0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&temp),
+ sizeof (a_uint32_t));
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_STAUS, complete, temp);
+
+ if (!complete)
+ {
+ return SW_NO_MORE;
+ }
+#endif
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, napt_entry->entry_id, reg[7]);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[ISISC_HOST_ENTRY_REG_NUM] = { 0 }, tbl_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl_idx = (entry_id - 1) & 0x3ff;
+ SW_SET_REG_BY_FIELD(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_NEXT);
+ if (SW_OK != rv)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ rv = _isisc_nat_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HOST_ENTRY7, TBL_IDX, tbl_idx, reg[7]);
+ if (entry_id != tbl_idx)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 0, reg[3]);
+ }
+ else if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_EN, 1, reg[3]);
+ SW_SET_REG_BY_FIELD(NAPT_ENTRY3, CNT_IDX, cnt_id, reg[3]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_DEL);
+ SW_RTN_ON_ERROR(rv);
+
+ reg[4] = 0x0;
+ rv = _isisc_nat_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_ADD);
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NAPT_FULL_CONE == mode)
+ {
+ data = 0;
+ }
+ else if (FAL_NAPT_STRICT_CONE == mode)
+ {
+ data = 1;
+ }
+ else if ((FAL_NAPT_PORT_STRICT == mode)
+ || (FAL_NAPT_SYNMETRIC == mode))
+ {
+ data = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAPT_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *mode = FAL_NAPT_FULL_CONE;
+ }
+ else if (1 == data)
+ {
+ *mode = FAL_NAPT_STRICT_CONE;
+ }
+ else
+ {
+ *mode = FAL_NAPT_PORT_STRICT;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if ((FAL_NAT_HASH_KEY_PORT & mode)
+ && (FAL_NAT_HASH_KEY_IPADDR & mode))
+ {
+ data = 2;
+ }
+ else if (FAL_NAT_HASH_KEY_PORT & mode)
+ {
+ data = 0;
+ }
+ else if (FAL_NAT_HASH_KEY_IPADDR & mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, NAT_CTRL, 0, NAT_HASH_MODE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *mode = 0;
+ if (0 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_PORT;
+ }
+ else if (1 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_IPADDR;
+ }
+ else if (2 == data)
+ {
+ *mode = FAL_NAT_HASH_KEY_PORT;
+ *mode |= FAL_NAT_HASH_KEY_IPADDR;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ data = addr;
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_ADDR, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ *addr = data;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ data = mask;
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+#if 0
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ data = (((addr >> 20) & 0xfff) << 8) | ((addr >> 8) & 0xff);
+ }
+ else
+ {
+ data = (addr >> 12) & 0xfffff;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+#endif
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+#if 0
+ sw_error_t rv;
+ a_uint32_t data, tmp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, BASEADDR_SEL,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_CTL, 0, IP4_BASEADDR,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (tmp)
+ {
+ *addr = ((data & 0xff) << 8) | (((data >> 8) & 0xfff) << 20);
+ }
+ else
+ {
+ *addr = (data & 0xfffff) << 12;
+ }
+#endif
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRVIP_MASK, 0, IP4_BASEMASK,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *mask = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_commit(a_uint32_t dev_id, fal_nat_pub_addr_t * entry,
+ a_uint32_t op, a_uint32_t * empty)
+{
+ a_uint32_t index, addr, data, tbl[2] = { 0 };
+ sw_error_t rv;
+
+ *empty = ISISC_PUB_ADDR_NUM;
+ for (index = 0; index < ISISC_PUB_ADDR_NUM; index++)
+ {
+ addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+ if (data)
+ {
+ addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp
+ ((void *) &(entry->pub_addr), (void *) &(tbl[0]),
+ sizeof (fal_ip4_addr_t)))
+ {
+ if (ISISC_NAT_ENTRY_DEL == op)
+ {
+ addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+ tbl[1] = 0;
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])),
+ sizeof (a_uint32_t));
+ *empty = index;
+ return rv;
+ }
+ else if (ISISC_NAT_ENTRY_ADD == op)
+ {
+ entry->entry_id = index;
+ return SW_ALREADY_EXIST;
+ }
+ }
+ }
+ else
+ {
+ *empty = index;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, empty, addr, data, tbl[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ tbl[0] = entry->pub_addr;
+ tbl[1] = 1;
+
+ rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_ADD, &empty);
+ if (SW_ALREADY_EXIST == rv)
+ {
+ return rv;
+ }
+
+ if (ISISC_PUB_ADDR_NUM == empty)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ for (i = 0; i < 1; i++)
+ {
+ addr = ISISC_PUB_ADDR_EDIT0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ addr = ISISC_PUB_ADDR_OFFLOAD_ADDR + (empty << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISISC_PUB_ADDR_VALID_ADDR;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data |= (0x1 << empty);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < 2; i++)
+ {
+ addr = ISISC_PUB_ADDR_TBL0_ADDR + (empty << 4) + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ entry->entry_id = empty;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t empty, addr, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_pub_addr_commit(dev_id, entry, ISISC_NAT_ENTRY_DEL, &empty);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ISISC_PUB_ADDR_VALID_ADDR;
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x1 << empty));
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t data, addr, idx, index, tbl[2];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == entry->entry_id)
+ {
+ idx = 0;
+ }
+ else
+ {
+ if ((ISISC_PUB_ADDR_NUM - 1) == entry->entry_id)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ idx = entry->entry_id + 1;
+ }
+ }
+
+ for (index = idx; index < ISISC_PUB_ADDR_NUM; index++)
+ {
+ addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PUB_ADDR1, ADDR_VALID, data, tbl[1]);
+ if (data)
+ {
+ break;
+ }
+ }
+
+ if (ISISC_PUB_ADDR_NUM == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ addr = ISISC_PUB_ADDR_TBL0_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ entry->entry_id = index;
+ entry->pub_addr = tbl[0];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_DROP == cmd)
+ {
+ data = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FORWARD_CTL0, 0, NAT_NOT_FOUND_DROP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_DROP;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_nat_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t index, addr, data = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_nat_feature_check(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_nat_snap[dev_id] = 0;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAT, ISISC_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HOST_ENTRY7, 0, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_nat_entry_commit(dev_id, ISISC_ENTRY_NAPT, ISISC_NAT_ENTRY_FLUSH);
+ SW_RTN_ON_ERROR(rv);
+
+ for (index = 0; index < ISISC_PUB_ADDR_NUM; index++)
+ {
+ addr = ISISC_PUB_ADDR_TBL1_ADDR + (index << 4);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Add one NAT entry to one particular device.
+ * @details Comments:
+ Before NAT entry added ip4 private base address must be set
+ at first.
+ In parameter nat_entry entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_add(a_uint32_t dev_id, fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_add(dev_id, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAT entry delete operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_del(dev_id, del_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAT entry get operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_get(dev_id, get_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAT entry next operation mode
+ * @param[in] nat_entry NAT entry parameter
+ * @param[out] nat_entry NAT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_entry_t * nat_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_next(dev_id, next_mode, nat_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id, a_uint32_t cnt_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one NAPT entry to one particular device.
+ * @details Comments:
+ Before NAPT entry added related ip4 private base address must be set
+ at first.
+ In parameter napt_entry related entry flags must be set
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_add(a_uint32_t dev_id, fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_add(dev_id, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode NAPT entry delete operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_del(dev_id, del_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get one NAPT entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] get_mode NAPT entry get operation mode
+ * @param[in] nat_entry NAPT entry parameter
+ * @param[out] nat_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_get(a_uint32_t dev_id, a_uint32_t get_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_get(dev_id, get_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next NAPT entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode NAPT entry next operation mode
+ * @param[in] napt_entry NAPT entry parameter
+ * @param[out] napt_entry NAPT entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_napt_entry_t * napt_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_next(dev_id, next_mode, napt_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind one counter entry to one NAPT entry to one particular device.
+ * @param[in] dev_id device id
+ * @param[in] entry_id NAPT entry id
+ * @param[in] cnt_id counter entry id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_counter_bind(a_uint32_t dev_id, a_uint32_t entry_id,
+ a_uint32_t cnt_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_counter_bind(dev_id, entry_id, cnt_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_hash_mode_set(a_uint32_t dev_id, a_uint32_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_hash_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get NAT hash mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAT hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_hash_mode_get(a_uint32_t dev_id, a_uint32_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_hash_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_mode_set(a_uint32_t dev_id, fal_napt_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working mode of NAPT engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mode NAPT mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_napt_mode_get(a_uint32_t dev_id, fal_napt_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_napt_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @details Comments:
+ Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_prv_base_addr_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_prv_base_addr_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[in] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_mask_set(a_uint32_t dev_id, fal_ip4_addr_t mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_prv_base_mask_set(dev_id, mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] mask private base mask
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_base_mask_get(a_uint32_t dev_id, fal_ip4_addr_t * mask)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_prv_base_mask_get(dev_id, mask);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set IP4 private base address on a particular device
+ * @details Comments:
+ Only 20bits is meaning which 20bits is determined by private address mode.
+ * @param[in] dev_id device id
+ * @param[in] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_psr_prv_base_addr_set(a_uint32_t dev_id, fal_ip4_addr_t addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_psr_prv_base_addr_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address on a particular device
+ * @param[in] dev_id device id
+ * @param[out] addr private base address
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_psr_prv_base_addr_get(a_uint32_t dev_id, fal_ip4_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_psr_prv_base_addr_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set IP4 private base address mode on a particular device
+ * @details Comments:
+ If map_en equal true means bits31-20 bits15-8 are base address
+ else bits31-12 are base address.
+ * @param[in] dev_id device id
+ * @param[in] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_addr_mode_set(a_uint32_t dev_id, a_bool_t map_en)
+{
+ sw_error_t rv = SW_OK;
+
+ HSL_API_LOCK;
+ /*rv = _isisc_nat_prv_addr_mode_set(dev_id, map_en);*/
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get IP4 private base address mode on a particular device
+ * @param[in] dev_id device id
+ * @param[out] map_en private base mapping mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_prv_addr_mode_get(a_uint32_t dev_id, a_bool_t * map_en)
+{
+ sw_error_t rv = SW_OK;
+
+ HSL_API_LOCK;
+ /*rv = _isisc_nat_prv_addr_mode_get(dev_id, map_en);*/
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one public address entry to one particular device.
+ * @details Comments:
+ Hardware entry id will be returned.
+ * @param[in] dev_id device id
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_add(a_uint32_t dev_id, fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_pub_addr_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one public address entry from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] del_mode delete operaton mode
+ * @param[in] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_del(a_uint32_t dev_id, a_uint32_t del_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_pub_addr_del(dev_id, del_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next public address entries from one particular device.
+ * @param[in] dev_id device id
+ * @param[in] next_mode next operaton mode
+ * @param[out] entry public address entry parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_pub_addr_next(a_uint32_t dev_id, a_uint32_t next_mode,
+ fal_nat_pub_addr_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_pub_addr_next(dev_id, next_mode, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_unk_session_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_unk_session_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for those packets miss NAT entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nat_unk_session_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nat_unk_session_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_nat_init(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = isisc_nat_reset(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->nat_add = isisc_nat_add;
+ p_api->nat_del = isisc_nat_del;
+ p_api->nat_get = isisc_nat_get;
+ p_api->nat_next = isisc_nat_next;
+ p_api->nat_counter_bind = isisc_nat_counter_bind;
+ p_api->napt_add = isisc_napt_add;
+ p_api->napt_del = isisc_napt_del;
+ p_api->napt_get = isisc_napt_get;
+ p_api->napt_next = isisc_napt_next;
+ p_api->napt_counter_bind = isisc_napt_counter_bind;
+ p_api->nat_status_set = isisc_nat_status_set;
+ p_api->nat_status_get = isisc_nat_status_get;
+ p_api->nat_hash_mode_set = isisc_nat_hash_mode_set;
+ p_api->nat_hash_mode_get = isisc_nat_hash_mode_get;
+ p_api->napt_status_set = isisc_napt_status_set;
+ p_api->napt_status_get = isisc_napt_status_get;
+ p_api->napt_mode_set = isisc_napt_mode_set;
+ p_api->napt_mode_get = isisc_napt_mode_get;
+ p_api->nat_pub_addr_add = isisc_nat_pub_addr_add;
+ p_api->nat_pub_addr_del = isisc_nat_pub_addr_del;
+ p_api->nat_pub_addr_next = isisc_nat_pub_addr_next;
+ p_api->nat_unk_session_cmd_set = isisc_nat_unk_session_cmd_set;
+ p_api->nat_unk_session_cmd_get = isisc_nat_unk_session_cmd_get;
+ p_api->nat_prv_base_addr_set = isisc_nat_prv_base_addr_set;
+ p_api->nat_prv_base_addr_get = isisc_nat_prv_base_addr_get;
+ p_api->nat_prv_base_mask_set = isisc_nat_prv_base_mask_set;
+ p_api->nat_prv_base_mask_get = isisc_nat_prv_base_mask_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isisc/isisc_port_ctrl.c b/src/hsl/isisc/isisc_port_ctrl.c
new file mode 100644
index 0000000..4eeb29f
--- /dev/null
+++ b/src/hsl/isisc/isisc_port_ctrl.c
@@ -0,0 +1,2154 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_port_ctrl ISISC_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_port_ctrl.h"
+#include "isisc_reg.h"
+#include "f1_phy.h"
+
+static a_bool_t
+_isisc_port_phy_connected(a_uint32_t dev_id, fal_port_t port_id)
+{
+ if ((0 == port_id) || (6 == port_id))
+ {
+ return A_FALSE;
+ }
+ else
+ {
+ return A_TRUE;
+ }
+}
+
+static sw_error_t
+_isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id, reg_save, reg_val, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ if (FAL_HALF_DUPLEX == duplex)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
+ }
+ reg_save = reg_val;
+ }
+ else
+ {
+ /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ reg_save = reg_val;
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_duplex(dev_id, phy_id, duplex);
+ SW_RTN_ON_ERROR(rv);
+
+ /* If MAC not in sync with PHY mode, the behavior is undefine.
+ You must be careful... */
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+ if (!force)
+ {
+ if (FAL_HALF_DUPLEX == duplex)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_save);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_save);
+ }
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, field, reg);
+ if (field)
+ {
+ *pduplex = FAL_FULL_DUPLEX;
+ }
+ else
+ {
+ *pduplex = FAL_HALF_DUPLEX;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id, reg_save, reg_val, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_SPEED_1000 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
+ }
+ reg_save = reg_val;
+
+ }
+ else
+ {
+ /* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ reg_save = reg_val;
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_speed(dev_id, phy_id, speed);
+ SW_RTN_ON_ERROR(rv);
+
+ /* If MAC not in sync with PHY mode, the behavior is undefine.
+ You must be careful... */
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg_save);
+ if (!force)
+ {
+ if (FAL_SPEED_10 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_save);
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_save);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_save);
+ }
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, field, reg);
+ if (0 == field)
+ {
+ *pspeed = FAL_SPEED_10;
+ }
+ else if (1 == field)
+ {
+ *pspeed = FAL_SPEED_100;
+ }
+ else if (2 == field)
+ {
+ *pspeed = FAL_SPEED_1000;
+ }
+ else
+ {
+ *pspeed = FAL_SPEED_BUTT;
+ rv = SW_READ_ERROR;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ a_uint32_t phy_id;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f1_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f1_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t rx, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+
+ if (1 == rx)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ /* for those ports without PHY, it can't sync flow control status */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ return SW_DISABLE;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (0 == force)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f1_phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_NO_HEADER_EN == mode)
+ {
+ val = 0;
+ }
+ else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+ {
+ val = 1;
+ }
+ else if (FAL_ALL_TYPE_FRAME_EN == mode)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, RXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *mode = FAL_ONLY_MANAGE_FRAME_EN;
+ }
+ else if (2 == val)
+ {
+ *mode = FAL_ALL_TYPE_FRAME_EN;
+ }
+ else
+ {
+ *mode = FAL_NO_HEADER_EN;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_NO_HEADER_EN == mode)
+ {
+ val = 0;
+ }
+ else if (FAL_ONLY_MANAGE_FRAME_EN == mode)
+ {
+ val = 1;
+ }
+ else if (FAL_ALL_TYPE_FRAME_EN == mode)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, TXHDR_MODE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *mode = FAL_ONLY_MANAGE_FRAME_EN;
+ }
+ else if (2 == val)
+ {
+ *mode = FAL_ALL_TYPE_FRAME_EN;
+ }
+ else
+ {
+ *mode = FAL_NO_HEADER_EN;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ a_uint32_t reg;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (0xffff < type)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 1, reg);
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, type, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_LEN, 0, reg);
+ SW_SET_REG_BY_FIELD(HEADER_CTL, TYPE_VAL, 0, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ a_uint32_t data, reg;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, HEADER_CTL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_LEN, data, reg);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(HEADER_CTL, TYPE_VAL, data, reg);
+ *enable = A_TRUE;
+ *type = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *type = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, force, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg);
+ if (force)
+ {
+ /* link isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TXMAC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, force, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, force, reg);
+ if (force)
+ {
+ /* link isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RXMAC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, reg, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, reg, force;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* for those ports without PHY device we set MAC register */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ }
+ else
+ {
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ }
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, RX_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ /* for those ports without PHY, it can't sync link status */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ return SW_DISABLE;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, LINK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* for those ports without PHY device supposed always link up */
+ if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
+ {
+ *status = A_TRUE;
+ }
+ else
+ {
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == f1_phy_get_link_status(dev_id, phy_id))
+ {
+ *status = A_TRUE;
+ }
+ else
+ {
+ *status = A_FALSE;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HDR_CTL, port_id, LOOPBACK_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control(rx/tx/bp) status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_flowctrl_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_flowctrl_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_rxhdr_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_rxhdr_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txhdr_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_txhdr_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txhdr_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_header_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_txhdr_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_header_type_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t type)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_header_type_set(dev_id, enable, type);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header type value on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] type header type value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_header_type_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * type)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_header_type_get(dev_id, enable, type);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_txmac_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of txmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_txmac_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_rxmac_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of rxmac on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxmac_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_rxmac_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_txfc_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of tx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_txfc_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_rxfc_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of rx flow control on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_rxfc_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_bp_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of back pressure on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_bp_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_bp_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_link_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_forcemode_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_link_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get link status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status link status up (A_TRUE) or down (A_FALSE)
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_link_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_link_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_loopback_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_port_mac_loopback_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac loop back on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_loopback_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_mac_loopback_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = isisc_port_duplex_get;
+ p_api->port_duplex_set = isisc_port_duplex_set;
+ p_api->port_speed_get = isisc_port_speed_get;
+ p_api->port_speed_set = isisc_port_speed_set;
+ p_api->port_autoneg_status_get = isisc_port_autoneg_status_get;
+ p_api->port_autoneg_enable = isisc_port_autoneg_enable;
+ p_api->port_autoneg_restart = isisc_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = isisc_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = isisc_port_autoneg_adv_set;
+ p_api->port_flowctrl_set = isisc_port_flowctrl_set;
+ p_api->port_flowctrl_get = isisc_port_flowctrl_get;
+ p_api->port_flowctrl_forcemode_set = isisc_port_flowctrl_forcemode_set;
+ p_api->port_flowctrl_forcemode_get = isisc_port_flowctrl_forcemode_get;
+ p_api->port_powersave_set = isisc_port_powersave_set;
+ p_api->port_powersave_get = isisc_port_powersave_get;
+ p_api->port_hibernate_set = isisc_port_hibernate_set;
+ p_api->port_hibernate_get = isisc_port_hibernate_get;
+ p_api->port_cdt = isisc_port_cdt;
+ p_api->port_rxhdr_mode_set = isisc_port_rxhdr_mode_set;
+ p_api->port_rxhdr_mode_get = isisc_port_rxhdr_mode_get;
+ p_api->port_txhdr_mode_set = isisc_port_txhdr_mode_set;
+ p_api->port_txhdr_mode_get = isisc_port_txhdr_mode_get;
+ p_api->header_type_set = isisc_header_type_set;
+ p_api->header_type_get = isisc_header_type_get;
+ p_api->port_txmac_status_set = isisc_port_txmac_status_set;
+ p_api->port_txmac_status_get = isisc_port_txmac_status_get;
+ p_api->port_rxmac_status_set = isisc_port_rxmac_status_set;
+ p_api->port_rxmac_status_get = isisc_port_rxmac_status_get;
+ p_api->port_txfc_status_set = isisc_port_txfc_status_set;
+ p_api->port_txfc_status_get = isisc_port_txfc_status_get;
+ p_api->port_rxfc_status_set = isisc_port_rxfc_status_set;
+ p_api->port_rxfc_status_get = isisc_port_rxfc_status_get;
+ p_api->port_bp_status_set = isisc_port_bp_status_set;
+ p_api->port_bp_status_get = isisc_port_bp_status_get;
+ p_api->port_link_forcemode_set = isisc_port_link_forcemode_set;
+ p_api->port_link_forcemode_get = isisc_port_link_forcemode_get;
+ p_api->port_link_status_get = isisc_port_link_status_get;
+ p_api->port_mac_loopback_set=isisc_port_mac_loopback_set;
+ p_api->port_mac_loopback_get=isisc_port_mac_loopback_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_portvlan.c b/src/hsl/isisc/isisc_portvlan.c
new file mode 100644
index 0000000..2061ab6
--- /dev/null
+++ b/src/hsl/isisc/isisc_portvlan.c
@@ -0,0 +1,2240 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_port_vlan ISISC_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_portvlan.h"
+#include "isisc_reg.h"
+
+#define MAX_VLAN_ID 4095
+#define ISISC_MAX_VLAN_TRANS 64
+#define ISISC_VLAN_TRANS_ADDR 0x5ac00
+
+
+static sw_error_t
+_isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (port_id % 2)
+ {
+ reg &= 0xffff;
+ reg |= ((data & 0xfff) << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= (data & 0xfff);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_DEFV, (port_id / 2),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t data, regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_1Q_DISABLE == port_1qmode)
+ {
+ data = 1;
+ }
+ else
+ {
+ data = 0;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, VLAN_DIS,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t data, regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3, 3 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((FAL_EG_MODE_BUTT <= port_egvlanmode)
+ || (FAL_EG_HYBRID == port_egvlanmode))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ROUTER_EG, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0x3 << (port_id << 2)));
+ data |= (regval[port_egvlanmode] << (port_id << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ROUTER_EG, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED, FAL_EG_UNTOUCHED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = tpid;
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tpid = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_INVLAN_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val[mode]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+ FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(mode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (regval >= 3)
+ {
+ return SW_FAIL;
+ }
+ *mode = retval[regval & 0x3];
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ TLS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (vid > MAX_VLAN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_SVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (vid > MAX_VLAN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ DEF_CVID, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+ {
+ p = 0;
+ c = 0;
+ }
+ else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+ {
+ p = 1;
+ c = 1;
+ }
+ else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+ {
+ p = 1;
+ c = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_VLAN1, PROPAGATION_EN, p, reg);
+ SW_SET_REG_BY_FIELD(PORT_VLAN1, CLONE, c, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_VLAN1, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_VLAN1, PROPAGATION_EN, p, reg);
+ SW_GET_FIELD_BY_REG(PORT_VLAN1, CLONE, c, reg);
+
+ if (p)
+ {
+ if (c)
+ {
+ *mode = FAL_VLAN_PROPAGATION_CLONE;
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_REPLACE;
+ }
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_DISABLE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx,
+ fal_pbmp_t * pbmp, fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, dir, table[2];
+
+ *pbmp = 0;
+ aos_mem_zero(entry, sizeof (fal_vlan_trans_entry_t));
+
+ addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3);
+ /* get vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ dir = 0x3 & (table[1] >> 4);
+ if (!dir)
+ {
+ return SW_EMPTY;
+ }
+
+ entry->o_vid = table[0] & 0xfff;
+ *pbmp = (table[1] >> 6) & 0x7f;
+
+ if (3 == dir)
+ {
+ entry->bi_dir = A_TRUE;
+ entry->forward_dir = A_TRUE;
+ entry->reverse_dir = A_TRUE;
+ }
+ else if (1 == dir)
+ {
+ entry->bi_dir = A_FALSE;
+ entry->forward_dir = A_TRUE;
+ entry->reverse_dir = A_FALSE;
+ }
+ else
+ {
+ entry->bi_dir = A_FALSE;
+ entry->forward_dir = A_FALSE;
+ entry->reverse_dir = A_TRUE;
+ }
+
+ entry->o_vid_is_cvid = (table[1] >> 13) & 0x1UL;
+ entry->one_2_one_vlan = (table[1] >> 16) & 0x1UL;
+ entry->s_vid_enable = (table[1] >> 14) & 0x1UL;
+ entry->c_vid_enable = (table[1] >> 15) & 0x1UL;
+
+ if (A_TRUE == entry->s_vid_enable)
+ {
+ entry->s_vid = (table[0] >> 12) & 0xfff;
+ }
+
+ if (A_TRUE == entry->c_vid_enable)
+ {
+ entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp,
+ fal_vlan_trans_entry_t entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, table[2] = { 0 };
+
+ addr = ISISC_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+ if (0 != pbmp)
+ {
+ table[0] = entry.o_vid & 0xfff;
+ table[0] |= ((entry.s_vid & 0xfff) << 12);
+ table[0] |= ((entry.c_vid & 0xff) << 24);
+ table[1] = (entry.c_vid >> 8) & 0xf;
+
+ if (A_TRUE == entry.bi_dir)
+ {
+ table[1] |= (0x3 << 4);
+ }
+
+ if (A_TRUE == entry.forward_dir)
+ {
+ table[1] |= (0x1 << 4);
+ }
+
+ if (A_TRUE == entry.reverse_dir)
+ {
+ table[1] |= (0x1 << 5);
+ }
+
+ table[1] |= (pbmp << 6);
+ table[1] |= ((0x1UL & entry.o_vid_is_cvid) << 13);
+ table[1] |= ((0x1UL & entry.s_vid_enable) << 14);
+ table[1] |= ((0x1UL & entry.c_vid_enable) << 15);
+ table[1] |= ((0x1UL & entry.one_2_one_vlan) << 16);
+ }
+
+ /* set vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_convert(fal_vlan_trans_entry_t * entry,
+ fal_vlan_trans_entry_t * local)
+{
+ aos_mem_copy(local, entry, sizeof (fal_vlan_trans_entry_t));
+
+ if ((A_TRUE == local->bi_dir)
+ || ((A_TRUE == local->forward_dir)
+ && (A_TRUE == local->reverse_dir)))
+ {
+ local->bi_dir = A_TRUE;
+ local->forward_dir = A_TRUE;
+ local->reverse_dir = A_TRUE;
+ }
+
+ if (A_FALSE == local->s_vid_enable)
+ {
+ local->s_vid = 0;
+ }
+
+ if (A_FALSE == local->c_vid_enable)
+ {
+ local->c_vid = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ entry_idx = idx;
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&local, &temp, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ return SW_ALREADY_EXIST;
+ }
+ entry_idx = idx;
+ break;
+ }
+ else
+ {
+ t_pbmp = 0;
+ }
+ }
+
+ if (ISISC_MAX_VLAN_TRANS != entry_idx)
+ {
+ t_pbmp |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = ISISC_MAX_VLAN_TRANS;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ entry_idx = idx;
+ break;
+ }
+ }
+ }
+
+ if (ISISC_MAX_VLAN_TRANS != entry_idx)
+ {
+ t_pbmp &= (~(0x1 << port_id));
+ }
+ else
+ {
+ return SW_NOT_FOUND;
+ }
+
+ return _isisc_vlan_trans_write(dev_id, entry_idx, t_pbmp, local);
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx;
+ fal_vlan_trans_entry_t temp, local;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_port_vlan_trans_convert(entry, &local);
+ SW_RTN_ON_ERROR(rv);
+
+ for (idx = 0; idx < ISISC_MAX_VLAN_TRANS; idx++)
+ {
+ rv = _isisc_vlan_trans_read(dev_id, idx, &t_pbmp, &temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&temp, &local, sizeof (fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ return SW_OK;
+ }
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator,
+ fal_vlan_trans_entry_t * entry)
+{
+ a_uint32_t index;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_t;
+ fal_pbmp_t pbmp_t;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (ISISC_MAX_VLAN_TRANS < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < ISISC_MAX_VLAN_TRANS; index++)
+ {
+ rv = _isisc_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+
+ if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+ {
+ aos_mem_copy(entry, &entry_t, sizeof (fal_vlan_trans_entry_t));
+ break;
+ }
+ }
+
+ if (ISISC_MAX_VLAN_TRANS == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_QINQ_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_STAG_MODE == mode)
+ {
+ stag = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ STAG_MODE, (a_uint8_t *) (&stag), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (stag)
+ {
+ *mode = FAL_QINQ_STAG_MODE;
+ }
+ else
+ {
+ *mode = FAL_QINQ_CTAG_MODE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_CORE_PORT == role)
+ {
+ core = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_port_route_defv_set(dev_id, port_id);
+ return rv;
+}
+
+static sw_error_t
+_isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN1, port_id,
+ COREP_EN, (a_uint8_t *) (&core), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (core)
+ {
+ *role = FAL_QINQ_CORE_PORT;
+ }
+ else
+ {
+ *role = FAL_QINQ_EDGE_PORT;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id,
+ EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+
+}
+
+static sw_error_t
+_isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id,
+ EG_MAC_BASE_VLAN_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_netisolate_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = enable;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+ NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_netisolate_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+ NET_ISO, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *enable = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = enable;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TRANS, 0,
+ EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TRANS, 0,
+ EG_FLTR_BYPASS_EN, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *enable = val;
+ return SW_OK;
+}
+
+
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_force_default_vid_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_force_default_vid_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_force_portvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_force_portvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nestvlan_tpid_set(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t * tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_nestvlan_tpid_get(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_invlan_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_invlan_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_tls_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_tls_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_tls_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_tls_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_pri_propagation_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_pri_propagation_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_default_svid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_default_svid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_default_cvid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_default_cvid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_propagation_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_propagation_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_trans_add(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_trans_del(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_trans_get(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator,
+ fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qinq_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qinq_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_qinq_role_set(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_qinq_role_get(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_vlan_xlt_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_mac_vlan_xlt_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get MAC_VLAN_XLT status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_port_mac_vlan_xlt_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_port_mac_vlan_xlt_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_port_route_defv_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv =_isisc_port_route_defv_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set NET_ISOLATE_EN
+ * @param[in] dev_id device id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_netisolate_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_netisolate_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get NET_ISOLATE_EN status
+ * @param[in] dev_id device id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_netisolate_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_netisolate_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_eg_trans_filter_bypass_en_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress translation filter bypass enable
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_eg_trans_filter_bypass_en_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+
+sw_error_t
+isisc_portvlan_init(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_init;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_set(&entry_init, 0, sizeof (fal_vlan_trans_entry_t));
+
+ for (i = 0; i < ISISC_MAX_VLAN_TRANS; i++)
+ {
+ rv = _isisc_vlan_trans_write(dev_id, i, 0, entry_init);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = isisc_port_1qmode_get;
+ p_api->port_1qmode_set = isisc_port_1qmode_set;
+ p_api->port_egvlanmode_get = isisc_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = isisc_port_egvlanmode_set;
+ p_api->portvlan_member_add = isisc_portvlan_member_add;
+ p_api->portvlan_member_del = isisc_portvlan_member_del;
+ p_api->portvlan_member_update = isisc_portvlan_member_update;
+ p_api->portvlan_member_get = isisc_portvlan_member_get;
+ p_api->port_force_default_vid_set = isisc_port_force_default_vid_set;
+ p_api->port_force_default_vid_get = isisc_port_force_default_vid_get;
+ p_api->port_force_portvlan_set = isisc_port_force_portvlan_set;
+ p_api->port_force_portvlan_get = isisc_port_force_portvlan_get;
+ p_api->nestvlan_tpid_set = isisc_nestvlan_tpid_set;
+ p_api->nestvlan_tpid_get = isisc_nestvlan_tpid_get;
+ p_api->port_invlan_mode_set = isisc_port_invlan_mode_set;
+ p_api->port_invlan_mode_get = isisc_port_invlan_mode_get;
+ p_api->port_tls_set = isisc_port_tls_set;
+ p_api->port_tls_get = isisc_port_tls_get;
+ p_api->port_pri_propagation_set = isisc_port_pri_propagation_set;
+ p_api->port_pri_propagation_get = isisc_port_pri_propagation_get;
+ p_api->port_default_svid_set = isisc_port_default_svid_set;
+ p_api->port_default_svid_get = isisc_port_default_svid_get;
+ p_api->port_default_cvid_set = isisc_port_default_cvid_set;
+ p_api->port_default_cvid_get = isisc_port_default_cvid_get;
+ p_api->port_vlan_propagation_set = isisc_port_vlan_propagation_set;
+ p_api->port_vlan_propagation_get = isisc_port_vlan_propagation_get;
+ p_api->port_vlan_trans_add = isisc_port_vlan_trans_add;
+ p_api->port_vlan_trans_del = isisc_port_vlan_trans_del;
+ p_api->port_vlan_trans_get = isisc_port_vlan_trans_get;
+ p_api->qinq_mode_set = isisc_qinq_mode_set;
+ p_api->qinq_mode_get = isisc_qinq_mode_get;
+ p_api->port_qinq_role_set = isisc_port_qinq_role_set;
+ p_api->port_qinq_role_get = isisc_port_qinq_role_get;
+ p_api->port_vlan_trans_iterate = isisc_port_vlan_trans_iterate;
+ p_api->port_mac_vlan_xlt_set = isisc_port_mac_vlan_xlt_set;
+ p_api->port_mac_vlan_xlt_get = isisc_port_mac_vlan_xlt_get;
+ p_api->netisolate_set = isisc_netisolate_set;
+ p_api->netisolate_get = isisc_netisolate_get;
+ p_api->eg_trans_filter_bypass_en_set = isisc_eg_trans_filter_bypass_en_set;
+ p_api->eg_trans_filter_bypass_en_get = isisc_eg_trans_filter_bypass_en_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isisc/isisc_qos.c b/src/hsl/isisc/isisc_qos.c
new file mode 100644
index 0000000..bfb5fd6
--- /dev/null
+++ b/src/hsl/isisc/isisc_qos.c
@@ -0,0 +1,1535 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_qos ISISC_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_qos.h"
+#include "isisc_reg.h"
+
+#define ISISC_QOS_QUEUE_TX_BUFFER_MAX 120
+#define ISISC_QOS_PORT_TX_BUFFER_MAX 504
+#define ISISC_QOS_PORT_RX_BUFFER_MAX 120
+
+#define ISISC_QOS_HOL_STEP 8
+#define ISISC_QOS_HOL_MOD 3
+
+//#define ISISC_MIN_QOS_MODE_PRI 0
+#define ISISC_MAX_QOS_MODE_PRI 3
+#define ISISC_MAX_PRI 7
+#define ISISC_MAX_QUEUE 3
+#define ISISC_MAX_EH_QUEUE 5
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+
+
+static sw_error_t
+_isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_RED_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+
+
+static sw_error_t
+_isisc_qos_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+ if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+ {
+ if (ISISC_MAX_EH_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+ else
+ {
+ if (ISISC_MAX_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t data, val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_QOS_QUEUE_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ val = *number / ISISC_QOS_HOL_STEP;
+ *number = val << ISISC_QOS_HOL_MOD;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0xf << (queue_id << 2)));
+ data |= (val << (queue_id << 2));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t data, val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_HOL_CTL0, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = (data >> (queue_id << 2)) & 0xf;
+ *number = val << ISISC_QOS_HOL_MOD;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_QOS_PORT_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / ISISC_QOS_HOL_STEP;
+ *number = val << ISISC_QOS_HOL_MOD;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL0, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << ISISC_QOS_HOL_MOD;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_QOS_PORT_RX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / ISISC_QOS_HOL_STEP;
+ *number = val << ISISC_QOS_HOL_MOD;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_HOL_CTL1, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << ISISC_QOS_HOL_MOD;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAX_QOS_MODE_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ a_uint32_t entry, f_val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *pri = f_val;
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t reg, val, w[6] = { 0 };
+ a_int32_t i, _index;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SCH_SP_MODE == mode)
+ {
+ val = 0;
+ _index = -1;
+ }
+ else if (FAL_SCH_WRR_MODE == mode)
+ {
+ val = 3;
+ _index = 5;
+ }
+ else if (FAL_SCH_MIX_MODE == mode)
+ {
+ val = 1;
+ _index = 4;
+ }
+ else if (FAL_SCH_MIX_PLUS_MODE == mode)
+ {
+ val = 2;
+ _index = 3;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (i = _index; i >= 0; i--)
+ {
+ if (weight[i] > 0x1f)
+ {
+ return SW_BAD_PARAM;
+ }
+ w[i] = weight[i];
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q5_W, w[5], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q4_W, w[4], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t val, sch, w[6], i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q5_W, w[5], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q4_W, w[4], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+ if (0 == sch)
+ {
+ *mode = FAL_SCH_SP_MODE;
+ }
+ else if (1 == sch)
+ {
+ *mode = FAL_SCH_MIX_MODE;
+ }
+ else if (2 == sch)
+ {
+ *mode = FAL_SCH_MIX_PLUS_MODE;
+ }
+ else
+ {
+ *mode = FAL_SCH_WRR_MODE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ weight[i] = w[i];
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAX_PRI < spri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = spri;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *spri = val & 0x7;
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (ISISC_MAX_PRI < cpri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = cpri;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ *cpri = val & 0x7;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_FORCE_SPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = enable ? 1 : 0;
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_VLAN0, port_id,
+ ING_FORCE_CPRI, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t addr, data;
+ a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+ rv = _isisc_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = base[port_id] + ((queue_id / 4) << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data &= (~(0xff << ((queue_id % 4) << 3)));
+ data |= (((enable << 7 ) | (tbl_id & 0xf)) << ((queue_id % 4) << 3));
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+_isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t addr, data;
+ a_uint32_t base[7] = {0x0c40, 0x0c48, 0x0c4c, 0x0c50, 0x0c54, 0x0c58, 0x0c60};
+
+ rv = _isisc_qos_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = base[port_id] + ((queue_id / 4) << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tbl_id = (data >> ((queue_id % 4) << 3)) & 0xf;
+ *enable = ((data >> ((queue_id % 4) << 3)) & 0x80) >> 7;
+ return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ If enable tx buffer on one port that means this port will have fixed
+ number buffers when transmitting packets. Otherwise they will
+ share the whole buffers with other ports in device.
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_red_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_red_en_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port red on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_red_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_red_en_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is 4, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for queue is 4 to 60.
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ The step of buffer number in Garuda is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ * @details Comments:
+ The step of buffer number in Shiva is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_mode_set(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_mode_get(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ If the priority of a mode is more small then the priority is more high.
+ Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ * @details Comments:
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+ the max value supported by ISIS is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t spri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_default_spri_set(dev_id, port_id, spri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default stag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] spri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * spri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_default_spri_get(dev_id, port_id, spri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t cpri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_default_cpri_set(dev_id, port_id, cpri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default ctag priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cpri vlan priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * cpri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_default_cpri_get(dev_id, port_id, cpri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_force_spri_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port force stag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_force_spri_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_force_cpri_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port force ctag priority enable flag one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_port_force_cpri_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] tbl_id CoS remark table id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_remark_table_set(dev_id, port_id, queue_id, tbl_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress queue based CoS remark on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] tbl_id CoS remark table id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_qos_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->qos_queue_tx_buf_status_set = isisc_qos_queue_tx_buf_status_set;
+ p_api->qos_queue_tx_buf_status_get = isisc_qos_queue_tx_buf_status_get;
+ p_api->qos_port_tx_buf_status_set = isisc_qos_port_tx_buf_status_set;
+ p_api->qos_port_tx_buf_status_get = isisc_qos_port_tx_buf_status_get;
+ p_api->qos_port_red_en_set = isisc_qos_port_red_en_set;
+ p_api->qos_port_red_en_get = isisc_qos_port_red_en_get;
+ p_api->qos_queue_tx_buf_nr_set = isisc_qos_queue_tx_buf_nr_set;
+ p_api->qos_queue_tx_buf_nr_get = isisc_qos_queue_tx_buf_nr_get;
+ p_api->qos_port_tx_buf_nr_set = isisc_qos_port_tx_buf_nr_set;
+ p_api->qos_port_tx_buf_nr_get = isisc_qos_port_tx_buf_nr_get;
+ p_api->qos_port_rx_buf_nr_set = isisc_qos_port_rx_buf_nr_set;
+ p_api->qos_port_rx_buf_nr_get = isisc_qos_port_rx_buf_nr_get;
+ p_api->qos_port_mode_set = isisc_qos_port_mode_set;
+ p_api->qos_port_mode_get = isisc_qos_port_mode_get;
+ p_api->qos_port_mode_pri_set = isisc_qos_port_mode_pri_set;
+ p_api->qos_port_mode_pri_get = isisc_qos_port_mode_pri_get;
+ p_api->qos_port_sch_mode_set = isisc_qos_port_sch_mode_set;
+ p_api->qos_port_sch_mode_get = isisc_qos_port_sch_mode_get;
+ p_api->qos_port_default_spri_set = isisc_qos_port_default_spri_set;
+ p_api->qos_port_default_spri_get = isisc_qos_port_default_spri_get;
+ p_api->qos_port_default_cpri_set = isisc_qos_port_default_cpri_set;
+ p_api->qos_port_default_cpri_get = isisc_qos_port_default_cpri_get;
+ p_api->qos_port_force_spri_status_set = isisc_qos_port_force_spri_status_set;
+ p_api->qos_port_force_spri_status_get = isisc_qos_port_force_spri_status_get;
+ p_api->qos_port_force_cpri_status_set = isisc_qos_port_force_cpri_status_set;
+ p_api->qos_port_force_cpri_status_get = isisc_qos_port_force_cpri_status_get;
+ p_api->qos_queue_remark_table_set = isisc_qos_queue_remark_table_set;
+ p_api->qos_queue_remark_table_get = isisc_qos_queue_remark_table_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isisc/isisc_rate.c b/src/hsl/isisc/isisc_rate.c
new file mode 100644
index 0000000..5ab7270
--- /dev/null
+++ b/src/hsl/isisc/isisc_rate.c
@@ -0,0 +1,1651 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_rate ISISC_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_rate.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_POLICER_ID 31
+#define ISISC_MAX_QUEUE 3
+#define ISISC_MAX_EH_QUEUE 5
+
+#define ACL_POLICER_CNT_SEL_ADDR 0x09f0
+#define ACL_POLICER_CNT_MODE_ADDR 0x09f4
+#define ACL_POLICER_CNT_RST_ADDR 0x09f8
+
+static sw_error_t
+_isisc_rate_port_queue_check(fal_port_t port_id, fal_queue_t queue_id)
+{
+ if ((0 == port_id) || (5 == port_id) || (6 == port_id))
+ {
+ if (ISISC_MAX_EH_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+ else
+ {
+ if (ISISC_MAX_QUEUE < queue_id)
+ {
+ return SW_BAD_PARAM;
+ }
+ }
+
+ return SW_OK;
+}
+
+static void
+_isisc_egress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_int32_t i;
+ a_uint32_t data[8] =
+ {
+ 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+ 512 * 1024
+ };
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isisc_egress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] =
+ {
+ 0, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024, 32 * 1024, 128 * 1024,
+ 512 * 1024
+ };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_egress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+ a_int32_t i;
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isisc_egress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] = { 0, 2, 4, 16, 64, 256, 512, 1024 };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_ingress_bs_byte_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_int32_t i;
+ a_uint32_t data[8] =
+ {
+ 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+ 8 * 1024 * 1024, 32 * 1024 * 1024
+ };
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isisc_ingress_bs_byte_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] =
+ {
+ 0, 4 * 1024, 32 * 1024, 128 * 1024, 512 * 1024, 2 * 1024 * 1024,
+ 8 * 1024 * 1024, 32 * 1024 * 1024
+ };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_ingress_bs_frame_sw_to_hw(a_uint32_t sw_bs, a_uint32_t * hw_bs)
+{
+ a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+ a_int32_t i;
+
+ for (i = 7; i >= 0; i--)
+ {
+ if (sw_bs >= data[i])
+ {
+ *hw_bs = i;
+ break;
+ }
+ }
+}
+
+static void
+_isisc_ingress_bs_frame_hw_to_sw(a_uint32_t hw_bs, a_uint32_t * sw_bs)
+{
+ a_uint32_t data[8] = { 0, 4, 16, 64, 256, 1024, 4096, 16384 };
+
+ *sw_bs = data[hw_bs & 0x7];
+}
+
+static void
+_isisc_rate_flag_parse(a_uint32_t sw_flag, a_uint32_t * hw_flag)
+{
+ *hw_flag = 0;
+
+ if (FAL_INGRESS_POLICING_TCP_CTRL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 1);
+ }
+
+ if (FAL_INGRESS_POLICING_MANAGEMENT & sw_flag)
+ {
+ *hw_flag |= (0x1 << 2);
+ }
+
+ if (FAL_INGRESS_POLICING_BROAD & sw_flag)
+ {
+ *hw_flag |= (0x1 << 3);
+ }
+
+ if (FAL_INGRESS_POLICING_UNK_UNI & sw_flag)
+ {
+ *hw_flag |= (0x1 << 4);
+ }
+
+ if (FAL_INGRESS_POLICING_UNK_MUL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 5);
+ }
+
+ if (FAL_INGRESS_POLICING_UNI & sw_flag)
+ {
+ *hw_flag |= (0x1 << 6);
+ }
+
+ if (FAL_INGRESS_POLICING_MUL & sw_flag)
+ {
+ *hw_flag |= (0x1 << 7);
+ }
+}
+
+static void
+_isisc_rate_flag_reparse(a_uint32_t hw_flag, a_uint32_t * sw_flag)
+{
+ *sw_flag = 0;
+
+ if (hw_flag & 0x2)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_TCP_CTRL;
+ }
+
+ if (hw_flag & 0x4)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_MANAGEMENT;
+ }
+
+ if (hw_flag & 0x8)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_BROAD;
+ }
+
+ if (hw_flag & 0x10)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNK_UNI;
+ }
+
+ if (hw_flag & 0x20)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNK_MUL;
+ }
+
+ if (hw_flag & 0x40)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_UNI;
+ }
+
+ if (hw_flag & 0x80)
+ {
+ *sw_flag |= FAL_INGRESS_POLICING_MUL;
+ }
+}
+
+static void
+_isisc_rate_ts_parse(fal_rate_mt_t sw, a_uint32_t * hw)
+{
+ if (FAL_RATE_MI_100US == sw)
+ {
+ *hw = 0;
+ }
+ else if (FAL_RATE_MI_1MS == sw)
+ {
+ *hw = 1;
+ }
+ else if (FAL_RATE_MI_10MS == sw)
+ {
+ *hw = 2;
+ }
+ else if (FAL_RATE_MI_100MS)
+ {
+ *hw = 3;
+ }
+ else
+ {
+ *hw = 0;
+ }
+}
+
+static void
+_isisc_rate_ts_reparse(a_uint32_t hw, fal_rate_mt_t * sw)
+{
+ if (0 == hw)
+ {
+ *sw = FAL_RATE_MI_100US;
+ }
+ else if (1 == hw)
+ {
+ *sw = FAL_RATE_MI_1MS;
+ }
+ else if (2 == hw)
+ {
+ *sw = FAL_RATE_MI_10MS;
+ }
+ else
+ {
+ *sw = FAL_RATE_MI_100MS;
+ }
+}
+
+static sw_error_t
+_isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t cir = 0x7fff, eir = 0x7fff, cbs = 0, ebs = 0, tmp, data[3] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data[0] = 0x18000000;
+ if (FAL_BYTE_BASED == policer->meter_unit)
+ {
+ if (A_TRUE == policer->c_enable)
+ {
+ cir = policer->cir >> 5;
+ policer->cir = cir << 5;
+ _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+ _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ }
+
+ if (A_TRUE == policer->e_enable)
+ {
+ eir = policer->eir >> 5;
+ policer->eir = eir << 5;
+ _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+ _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 0, data[1]);
+ }
+ else if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ if (A_TRUE == policer->c_enable)
+ {
+ cir = (policer->cir * 2) / 125;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+ _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ }
+
+ if (A_TRUE == policer->c_enable)
+ {
+ eir = (policer->eir * 2) / 125;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+ _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_UNIT, 1, data[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+
+ if (A_TRUE == policer->combine_mode)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, RATE_MODE, 1, data[0]);
+ }
+
+ if (A_TRUE == policer->deficit_en)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_BORROW, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->color_mode)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CM, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->couple_flag)
+ {
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, INGRESS_CF, 1, data[1]);
+ }
+
+ _isisc_rate_ts_parse(policer->c_meter_interval, &tmp);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER0, C_ING_TS, tmp, data[0]);
+
+ _isisc_rate_ts_parse(policer->e_meter_interval, &tmp);
+ SW_SET_REG_BY_FIELD(INGRESS_POLICER1, E_ING_TS, tmp, data[1]);
+
+ _isisc_rate_flag_parse(policer->c_rate_flag, &tmp);
+ data[2] = (tmp << 8) & 0xff00;
+
+ _isisc_rate_flag_parse(policer->e_rate_flag, &tmp);
+ data[2] |= (tmp & 0xff);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER0, port_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER1, port_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, INGRESS_POLICER2, port_id,
+ (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t unit, ts, cir, eir, cbs, ebs, data[3];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER0, port_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER1, port_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, INGRESS_POLICER2, port_id,
+ (a_uint8_t *) (&data[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CIR, cir, data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, INGRESS_CBS, cbs, data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EIR, eir, data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_EBS, ebs, data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_UNIT, unit, data[1]);
+
+ policer->c_enable = A_TRUE;
+ if (0x7fff == cir)
+ {
+ policer->c_enable = A_FALSE;
+ cir = 0;
+ }
+
+ policer->e_enable = A_TRUE;
+ if (0x7fff == eir)
+ {
+ policer->e_enable = A_FALSE;
+ eir = 0;
+ }
+
+ if (unit)
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+ }
+ else
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ policer->cir = cir << 5;
+ policer->eir = eir << 5;
+ _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, RATE_MODE, policer->combine_mode,
+ data[0]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_BORROW, policer->deficit_en,
+ data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CF, policer->couple_flag,
+ data[1]);
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, INGRESS_CM, policer->color_mode,
+ data[1]);
+
+ ts = (data[2] >> 8) & 0xff;
+ _isisc_rate_flag_reparse(ts, &(policer->c_rate_flag));
+
+ ts = data[2] & 0xff;
+ _isisc_rate_flag_reparse(ts, &(policer->e_rate_flag));
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER0, C_ING_TS, ts, data[0]);
+ _isisc_rate_ts_reparse(ts, &(policer->c_meter_interval));
+
+ SW_GET_FIELD_BY_REG(INGRESS_POLICER1, E_ING_TS, ts, data[1]);
+ _isisc_rate_ts_reparse(ts, &(policer->e_meter_interval));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == enable)
+ {
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ cir = 0x7fff;
+ eir = 0x7fff;
+ }
+ else
+ {
+ if (FAL_BYTE_BASED == shaper->meter_unit)
+ {
+ cir = shaper->cir >> 5;
+ shaper->cir = cir << 5;
+
+ eir = shaper->eir >> 5;
+ shaper->eir = eir << 5;
+
+ _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+ _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+ _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+ data = 0;
+ }
+ else if (FAL_FRAME_BASED == shaper->meter_unit)
+ {
+ cir = (shaper->cir * 2) / 125;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (shaper->eir * 2) / 125;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+ _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+ _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (!data)
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if ((0x7fff == cir) && (0x7fff == eir))
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ *enable = A_TRUE;
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ shaper->meter_unit = FAL_FRAME_BASED;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+ _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+ }
+ else
+ {
+ shaper->meter_unit = FAL_BYTE_BASED;
+ shaper->cir = cir << 5;
+ shaper->eir = eir << 5;
+ _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+ _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t unit = 0, data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_rate_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ cir = 0x7fff;
+ eir = 0x7fff;
+ }
+ else
+ {
+ if (FAL_BYTE_BASED == shaper->meter_unit)
+ {
+ cir = shaper->cir >> 5;
+ shaper->cir = cir << 5;
+
+ eir = shaper->eir >> 5;
+ shaper->eir = eir << 5;
+
+ _isisc_egress_bs_byte_sw_to_hw(shaper->cbs, &cbs);
+ _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isisc_egress_bs_byte_sw_to_hw(shaper->ebs, &ebs);
+ _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+
+ unit = 0;
+ }
+ else if (FAL_FRAME_BASED == shaper->meter_unit)
+ {
+ cir = (shaper->cir * 2) / 125;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (shaper->eir * 2) / 125;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isisc_egress_bs_frame_sw_to_hw(shaper->cbs, &cbs);
+ _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+
+ _isisc_egress_bs_frame_sw_to_hw(shaper->ebs, &ebs);
+ _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+
+ unit = 1;
+ }
+
+ data = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (4 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+ (a_uint8_t *) (&unit), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+ a_uint32_t data, cir, eir, cbs = 0, ebs = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_rate_port_queue_check(port_id, queue_id);
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mem_zero(shaper, sizeof (fal_egress_shaper_t));
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_PT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data)
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q0_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q0_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q0_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q0_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER0, port_id, EG_Q1_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER3, port_id, EG_Q1_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q1_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q1_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q2_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q2_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q2_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q2_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER1, port_id, EG_Q3_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER4, port_id, EG_Q3_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER6, port_id, EG_Q3_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q3_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (4 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q4_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q4_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q4_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER2, port_id, EG_Q5_CIR,
+ (a_uint8_t *) (&cir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER5, port_id, EG_Q5_EIR,
+ (a_uint8_t *) (&eir), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_CBS,
+ (a_uint8_t *) (&cbs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_EBS,
+ (a_uint8_t *) (&ebs), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, EG_SHAPER7, port_id, EG_Q5_UNIT,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if ((0x7fff == cir) && (0x7fff == eir))
+ {
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ *enable = A_TRUE;
+ if (data)
+ {
+ shaper->meter_unit = FAL_FRAME_BASED;
+ shaper->cir = cir / 2 * 125 + cir % 2 * 63;
+ shaper->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isisc_egress_bs_frame_hw_to_sw(cbs, &(shaper->cbs));
+ _isisc_egress_bs_frame_hw_to_sw(ebs, &(shaper->ebs));
+ }
+ else
+ {
+ shaper->meter_unit = FAL_BYTE_BASED;
+ shaper->cir = cir << 5;
+ shaper->eir = eir << 5;
+ _isisc_egress_bs_byte_hw_to_sw(cbs, &(shaper->cbs));
+ _isisc_egress_bs_byte_hw_to_sw(ebs, &(shaper->ebs));
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t ts, cir, eir, cbs = 0, ebs = 0, addr, data[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_POLICER_ID < policer_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == policer->counter_mode)
+ {
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ data[0] = 0x1;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ACL_POLICER_CNT_MODE_ADDR;
+ if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ data[0] = 0x0;
+ }
+ else
+ {
+ data[0] = 0x1;
+ }
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = ACL_POLICER_CNT_RST_ADDR;
+ data[0] = 0x1;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data[0] = 0x0;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ return rv;
+ }
+
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ data[0] = 0x0;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_BYTE_BASED == policer->meter_unit)
+ {
+ cir = policer->cir >> 5;
+ policer->cir = cir << 5;
+
+ eir = policer->eir >> 5;
+ policer->eir = eir << 5;
+
+ _isisc_ingress_bs_byte_sw_to_hw(policer->cbs, &cbs);
+ _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+
+ _isisc_ingress_bs_byte_sw_to_hw(policer->ebs, &ebs);
+ _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 0, data[1]);
+ }
+ else if (FAL_FRAME_BASED == policer->meter_unit)
+ {
+ cir = (policer->cir * 2) / 125;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+
+ eir = (policer->eir * 2) / 125;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+
+ _isisc_ingress_bs_frame_sw_to_hw(policer->cbs, &cbs);
+ _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+
+ _isisc_ingress_bs_frame_sw_to_hw(policer->ebs, &ebs);
+ _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_UNIT, 1, data[1]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CIR, cir, data[0]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EIR, eir, data[1]);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+
+ if (A_TRUE == policer->deficit_en)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_BORROW, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->color_mode)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CM, 1, data[1]);
+ }
+
+ if (A_TRUE == policer->couple_flag)
+ {
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_CF, 1, data[1]);
+ }
+
+ _isisc_rate_ts_parse(policer->meter_interval, &ts);
+ SW_SET_REG_BY_FIELD(ACL_POLICER1, ACL_TS, ts, data[1]);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ACL_POLICER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+ a_uint32_t unit, ts, cir, eir, cbs, ebs, addr, data[2];
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (ISISC_MAX_POLICER_ID < policer_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(policer, sizeof (policer));
+
+ addr = ACL_POLICER_CNT_SEL_ADDR;
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data[0])
+ {
+ policer->counter_mode = A_TRUE;
+
+ addr = ACL_POLICER_CNT_MODE_ADDR;
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, addr, 1, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (data[0])
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ }
+ else
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_COUNTER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ policer->counter_low = data[0];
+ policer->counter_high = data[1];
+
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER0, policer_id,
+ (a_uint8_t *) (&data[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ACL_POLICER1, policer_id,
+ (a_uint8_t *) (&data[1]), sizeof (a_uint32_t));
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CIR, cir, data[0]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER0, ACL_CBS, cbs, data[0]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EIR, eir, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_EBS, ebs, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_UNIT, unit, data[1]);
+ if (unit)
+ {
+ policer->meter_unit = FAL_FRAME_BASED;
+ policer->cir = cir / 2 * 125 + cir % 2 * 63;
+ policer->eir = eir / 2 * 125 + eir % 2 * 63;
+ _isisc_ingress_bs_frame_hw_to_sw(cbs, &(policer->cbs));
+ _isisc_ingress_bs_frame_hw_to_sw(ebs, &(policer->ebs));
+
+ }
+ else
+ {
+ policer->meter_unit = FAL_BYTE_BASED;
+ policer->cir = cir << 5;
+ policer->eir = eir << 5;
+ _isisc_ingress_bs_byte_hw_to_sw(cbs, &(policer->cbs));
+ _isisc_ingress_bs_byte_hw_to_sw(ebs, &(policer->ebs));
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CF, policer->couple_flag, data[1]);
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_CM, policer->color_mode, data[1]);
+
+ SW_GET_FIELD_BY_REG(ACL_POLICER1, ACL_TS, ts, data[1]);
+ _isisc_rate_ts_reparse(ts, &(policer->meter_interval));
+
+ return SW_OK;
+}
+
+sw_error_t
+_isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ a_uint32_t val = number;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (val>255)
+ return SW_BAD_PARAM;
+
+ HSL_REG_FIELD_SET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+sw_error_t
+_isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv = SW_OK;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+
+ HSL_REG_FIELD_GET(rv, dev_id, INGRESS_POLICER0, port_id, ADD_RATE_BYTE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ *number = val;
+
+ return rv;
+}
+
+sw_error_t
+_isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+
+ if (A_TRUE == enable)
+ {
+ val |= (0x1<<(16+port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ val &= ~(0x1<<(16+port_id));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, QM_CTRL_REG, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+sw_error_t
+_isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTRL_REG, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (val&(0x1<<(16+port_id)))
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return rv;
+}
+
+
+
+/**
+ * @brief Set port ingress policer parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_policer_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_policer_set(dev_id, port_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress policer parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress policer input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] policer port ingress policer parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_policer_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_policer_get(dev_id, port_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_shaper_set(dev_id, port_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress shaper parameters is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable, fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_shaper_get(dev_id, port_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set queue egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_queue_shaper_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_queue_shaper_set(dev_id, port_id, queue_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress shaper parameters on one particular port.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress shaper parameters is meaningless.
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] shaper port egress shaper parameter
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_queue_shaper_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_bool_t * enable,
+ fal_egress_shaper_t * shaper)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_queue_shaper_get(dev_id, port_id, queue_id, enable, shaper);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ACL ingress policer parameters.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_acl_policer_set(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_acl_policer_set(dev_id, policer_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ACL ingress policer parameters.
+ * @details Comments:
+ The granularity of speed is 32kbps or 62.5fps.
+ Because of hardware granularity function will return actual speed in hardware.
+ * @param[in] dev_id device id
+ * @param[in] policer_id ACL policer id
+ * @param[in] policer ACL ingress policer parameters
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_acl_policer_get(a_uint32_t dev_id, a_uint32_t policer_id,
+ fal_acl_policer_t * policer)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_acl_policer_get(dev_id, policer_id, policer);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_rate_port_add_rate_byte_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_add_rate_byte_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+HSL_LOCAL sw_error_t
+isisc_rate_port_add_rate_byte_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t *number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_add_rate_byte_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of port global flow control when global threshold is reached.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_gol_flow_en_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_gol_flow_en_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief get status of port global flow control when global threshold is reached.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_rate_port_gol_flow_en_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t* enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_rate_port_gol_flow_en_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+
+sw_error_t
+isisc_rate_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->rate_port_policer_set = isisc_rate_port_policer_set;
+ p_api->rate_port_policer_get = isisc_rate_port_policer_get;
+ p_api->rate_port_shaper_set = isisc_rate_port_shaper_set;
+ p_api->rate_port_shaper_get = isisc_rate_port_shaper_get;
+ p_api->rate_queue_shaper_set = isisc_rate_queue_shaper_set;
+ p_api->rate_queue_shaper_get = isisc_rate_queue_shaper_get;
+ p_api->rate_acl_policer_set = isisc_rate_acl_policer_set;
+ p_api->rate_acl_policer_get = isisc_rate_acl_policer_get;
+ p_api->rate_port_gol_flow_en_set = isisc_rate_port_gol_flow_en_set;
+ p_api->rate_port_gol_flow_en_get = isisc_rate_port_gol_flow_en_get;
+ p_api->rate_port_add_rate_byte_set=isisc_rate_port_add_rate_byte_set;
+ p_api->rate_port_add_rate_byte_get=isisc_rate_port_add_rate_byte_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_reg_access.c b/src/hsl/isisc/isisc_reg_access.c
new file mode 100644
index 0000000..ee696d2
--- /dev/null
+++ b/src/hsl/isisc/isisc_reg_access.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "isisc_reg_access.h"
+
+#if 0
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <linux/mm.h>
+#endif
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+#if defined(REG_ACCESS_SPEEDUP)
+static a_uint32_t mdio_base_addr = 0xffffffff;
+#endif
+
+static sw_error_t
+_isisc_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+#if 0
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+ if (phy_val != mdio_base_addr)
+ {
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ mdio_base_addr = phy_val;
+ }
+#else
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+#else
+ reg_val = qca_ar8216_mii_read(reg_addr);
+#endif
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+#if 0
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+#if defined(REG_ACCESS_SPEEDUP)
+ if (phy_val != mdio_base_addr)
+ {
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ mdio_base_addr = phy_val;
+ }
+#else
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in higher address, we should write the lower 16-bit register then the */
+ /* higher one */
+
+ /* write register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+#else
+ qca_ar8216_mii_write(reg_addr, reg_val);
+#endif
+ return SW_OK;
+}
+
+sw_error_t
+isisc_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ unsigned long flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _isisc_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+isisc_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ unsigned long flags;
+
+ struct file *filp;
+ // mm_segment_t fs;
+ a_uint32_t rt_value = 0;
+ a_uint32_t write_flag = 0;
+ char s[20]= {0};
+ a_uint32_t tmp_val = *((a_uint32_t *) value);
+
+ /*get MODULE_EN reg rsv */
+ SW_RTN_ON_ERROR(isisc_reg_get(dev_id, 0x30,(void *)&rt_value,4));
+ write_flag = (rt_value>>15) & 0x1;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _isisc_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+#if 0
+ if(write_flag)
+ {
+ filp = filp_open("/tmp/asic_output", O_RDWR|O_APPEND, 0644);
+ if(IS_ERR(filp))
+ {
+ printk("open error...\n");
+ return;
+ }
+
+ fs=get_fs();
+
+ set_fs(KERNEL_DS);
+ sprintf(s,"%08x %08x\n",reg_addr,tmp_val);
+ filp->f_op->write(filp, s, strlen(s),&filp->f_pos);
+
+ set_fs(fs);
+
+ filp_close(filp,NULL);
+ }
+#endif
+
+ return rv;
+}
+
+sw_error_t
+isisc_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+
+ if(32 == field_len)
+ {
+ *((a_uint32_t *) value) = reg_val;
+ }
+ else
+ {
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ }
+ return SW_OK;
+}
+
+sw_error_t
+isisc_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(isisc_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ if(32 == field_len)
+ {
+ reg_val = field_val;
+ }
+ else
+ {
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+ }
+
+
+ SW_RTN_ON_ERROR(isisc_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->phy_get = isisc_phy_get;
+ p_api->phy_set = isisc_phy_set;
+ p_api->reg_get = isisc_reg_get;
+ p_api->reg_set = isisc_reg_set;
+ p_api->reg_field_get = isisc_reg_field_get;
+ p_api->reg_field_set = isisc_reg_field_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+isisc_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
+
diff --git a/src/hsl/isisc/isisc_sec.c b/src/hsl/isisc/isisc_sec.c
new file mode 100644
index 0000000..fec6be9
--- /dev/null
+++ b/src/hsl/isisc/isisc_sec.c
@@ -0,0 +1,778 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_sec ISISC_SEC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_sec.h"
+#include "isisc_reg.h"
+
+#define NORM_CTRL0_ADDR 0x0200
+#define NORM_CTRL1_ADDR 0x0204
+#define NORM_CTRL2_ADDR 0x0208
+#define NORM_CTRL3_ADDR 0x0c00
+
+static sw_error_t
+_isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ fal_fwd_cmd_t cmd;
+ a_bool_t enable;
+ a_uint32_t addr, offset, len, reg, val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ cmd = *((fal_fwd_cmd_t *) value);
+ enable = *((a_bool_t *) value);
+ val = *((a_uint32_t *) value);
+
+ len = 1;
+ switch (item)
+ {
+ case FAL_NORM_MAC_RESV_VID_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 0;
+ goto cmd_chk;
+
+ case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 20;
+ goto cmd_chk;
+
+ case FAL_NORM_IP_INVALID_VER_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_IP_SAME_ADDR_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 2;
+ goto cmd_chk;
+ break;
+
+ case FAL_NROM_IP_TTL_CHANGE_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 11;
+ goto sts_chk;
+
+ case FAL_NROM_IP_TTL_VALUE:
+ addr = NORM_CTRL3_ADDR;
+ offset = 12;
+ len = 8;
+ goto set_reg;
+
+ case FAL_NROM_IP4_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 3;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 4;
+ len = 2;
+ goto s_cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_DF_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 7;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 8;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 24;
+ len = 8;
+ goto set_reg;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 9;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 10;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_SIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 11;
+ len = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_DIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 12;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 13;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 19;
+ goto cmd_chk;
+
+ case FAL_NROM_IP4_DF_CLEAR_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 9;
+ goto sts_chk;
+
+ case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 10;
+ goto sts_chk;
+
+ case FAL_NROM_IP6_INVALID_DIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 16;
+ goto cmd_chk;
+
+ case FAL_NROM_IP6_INVALID_SIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 17;
+ goto cmd_chk;
+
+ case FAL_NROM_IP6_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 18;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_BLAT_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 14;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 15;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_MIN_HDR_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 12;
+ len = 4;
+ goto set_reg;
+
+ case FAL_NROM_TCP_INVALID_SYN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 16;
+ goto cmd_chk;
+ break;
+
+ case FAL_NROM_TCP_SU_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 17;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 18;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SAP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 19;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_XMAS_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 20;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_NULL_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 21;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 22;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SF_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 23;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SAR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 24;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_RST_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 25;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 26;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 27;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_FA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 28;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_PA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 29;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_UA_BLOCK_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 0;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 1;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 2;
+ goto cmd_chk;
+
+ case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 3;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_BLAT_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 4;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_INVALID_LEN_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 5;
+ goto cmd_chk;
+
+ case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 6;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 7;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 8;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 9;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP6_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 10;
+ goto cmd_chk;
+
+ case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 0;
+ len = 14;
+ goto set_reg;
+
+ case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 16;
+ len = 14;
+ goto set_reg;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+
+sts_chk:
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ goto set_reg;
+
+s_cmd_chk:
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ val = 3;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 2;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ goto set_reg;
+
+cmd_chk:
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+set_reg:
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_REG_SET_BY_FIELD_U32(reg, val, offset, len);
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+ a_uint32_t addr, offset, len, reg, val;
+ a_uint32_t status_chk = 0, val_chk = 0, scmd_chk = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ len = 1;
+ switch (item)
+ {
+ case FAL_NORM_MAC_RESV_VID_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 0;
+ break;
+
+ case FAL_NORM_MAC_INVALID_SRC_ADDR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 20;
+ break;
+
+ case FAL_NORM_IP_INVALID_VER_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 1;
+ break;
+
+ case FAL_NROM_IP_SAME_ADDR_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 2;
+ break;
+
+ case FAL_NROM_IP_TTL_CHANGE_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 11;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP_TTL_VALUE:
+ addr = NORM_CTRL3_ADDR;
+ offset = 12;
+ len = 8;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 3;
+ break;
+
+ case FAL_NROM_IP4_HDR_OPTIONS_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 4;
+ len = 2;
+ scmd_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_DF_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 7;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 8;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 24;
+ len = 8;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 9;
+ break;
+
+ case FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 10;
+ break;
+
+ case FAL_NROM_IP4_INVALID_SIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 11;
+ len = 1;
+ break;
+
+ case FAL_NROM_IP4_INVALID_DIP_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 12;
+ break;
+
+ case FAL_NROM_IP4_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 13;
+ break;
+
+ case FAL_NROM_IP4_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 19;
+ break;
+
+ case FAL_NROM_IP4_DF_CLEAR_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 9;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP4_IPID_RANDOM_STATUS:
+ addr = NORM_CTRL3_ADDR;
+ offset = 10;
+ status_chk = 1;
+ break;
+
+ case FAL_NROM_IP6_INVALID_DIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 16;
+ break;
+
+ case FAL_NROM_IP6_INVALID_SIP_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 17;
+ break;
+
+ case FAL_NROM_IP6_INVALID_PL_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 18;
+ break;
+
+ case FAL_NROM_TCP_BLAT_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 14;
+ break;
+
+ case FAL_NROM_TCP_INVALID_HL_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 15;
+ break;
+
+ case FAL_NROM_TCP_MIN_HDR_SIZE:
+ addr = NORM_CTRL1_ADDR;
+ offset = 12;
+ len = 4;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_TCP_INVALID_SYN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 16;
+ break;
+
+ case FAL_NROM_TCP_SU_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 17;
+ break;
+
+ case FAL_NROM_TCP_SP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 18;
+ break;
+
+ case FAL_NROM_TCP_SAP_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 19;
+ break;
+
+ case FAL_NROM_TCP_XMAS_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 20;
+ break;
+
+ case FAL_NROM_TCP_NULL_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 21;
+ break;
+
+ case FAL_NROM_TCP_SR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 22;
+ break;
+
+ case FAL_NROM_TCP_SF_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 23;
+ break;
+
+ case FAL_NROM_TCP_SAR_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 24;
+ break;
+
+ case FAL_NROM_TCP_RST_SCAN_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 25;
+ break;
+
+ case FAL_NROM_TCP_SYN_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 26;
+ break;
+
+ case FAL_NROM_TCP_RST_WITH_DATA_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 27;
+ break;
+
+ case FAL_NROM_TCP_FA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 28;
+ break;
+
+ case FAL_NROM_TCP_PA_BLOCK_CMD:
+ addr = NORM_CTRL0_ADDR;
+ offset = 29;
+ break;
+
+ case FAL_NROM_TCP_UA_BLOCK_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 0;
+ break;
+
+ case FAL_NROM_TCP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 1;
+ break;
+
+ case FAL_NROM_TCP_INVALID_URGPTR_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 2;
+ break;
+
+ case FAL_NROM_TCP_INVALID_OPTIONS_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 3;
+ break;
+
+ case FAL_NROM_UDP_BLAT_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 4;
+ break;
+
+ case FAL_NROM_UDP_INVALID_LEN_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 5;
+ break;
+
+ case FAL_NROM_UDP_INVALID_CHKSUM_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 6;
+ break;
+
+ case FAL_NROM_ICMP4_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 7;
+ break;
+
+ case FAL_NROM_ICMP6_PING_PL_EXCEED_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 8;
+ break;
+
+ case FAL_NROM_ICMP4_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 9;
+ break;
+
+ case FAL_NROM_ICMP6_PING_FRAG_CMD:
+ addr = NORM_CTRL1_ADDR;
+ offset = 10;
+ break;
+
+ case FAL_NROM_ICMP4_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 0;
+ len = 14;
+ val_chk = 1;
+ break;
+
+ case FAL_NROM_ICMP6_PING_MAX_PL_VALUE:
+ addr = NORM_CTRL2_ADDR;
+ offset = 16;
+ len = 14;
+ val_chk = 1;
+ break;
+
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_FIELD_GET_BY_REG_U32(reg, val, offset, len);
+
+ if (val_chk)
+ {
+ *((a_uint32_t *) value) = val;
+ }
+ else if (status_chk)
+ {
+ if (val)
+ {
+ *((a_bool_t *) value) = A_TRUE;
+ }
+ else
+ {
+ *((a_bool_t *) value) = A_FALSE;
+ }
+ }
+ else if (scmd_chk)
+ {
+ if (2 == val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_RDT_TO_CPU;
+ }
+ else if (3 == val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+ }
+ else
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+ }
+ }
+ else
+ {
+ if (val)
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_DROP;
+ }
+ else
+ {
+ *((fal_fwd_cmd_t *) value) = FAL_MAC_FRWRD;
+ }
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[in] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_sec_norm_item_set(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_sec_norm_item_set(dev_id, item, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get normalization particular item types value.
+ * @details Comments:
+ * This operation will set normalization item values on a particular device.
+ * The prototye of value based on the item type.
+ * @param[in] dev_id device id
+ * @param[in] item normalizaton item type
+ * @param[out] value normalizaton item value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_sec_norm_item_get(a_uint32_t dev_id, fal_norm_item_t item, void *value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_sec_norm_item_get(dev_id, item, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_sec_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->sec_norm_item_set = isisc_sec_norm_item_set;
+ p_api->sec_norm_item_get = isisc_sec_norm_item_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
diff --git a/src/hsl/isisc/isisc_stp.c b/src/hsl/isisc/isisc_stp.c
new file mode 100644
index 0000000..e59bfd2
--- /dev/null
+++ b/src/hsl/isisc/isisc_stp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_stp ISISC_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_stp.h"
+#include "isisc_reg.h"
+
+#define ISISC_PORT_DISABLED 0
+#define ISISC_STP_BLOCKING 1
+#define ISISC_STP_LISTENING 2
+#define ISISC_STP_LEARNING 3
+#define ISISC_STP_FARWARDING 4
+
+static sw_error_t
+_isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ switch (state)
+ {
+ case FAL_STP_BLOKING:
+ val = ISISC_STP_BLOCKING;
+ break;
+ case FAL_STP_LISTENING:
+ val = ISISC_STP_LISTENING;
+ break;
+ case FAL_STP_LEARNING:
+ val = ISISC_STP_LEARNING;
+ break;
+ case FAL_STP_FARWARDING:
+ val = ISISC_STP_FARWARDING;
+ break;
+ case FAL_STP_DISABLED:
+ val = ISISC_PORT_DISABLED;
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_LOOKUP_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ switch (val)
+ {
+ case ISISC_STP_BLOCKING:
+ *state = FAL_STP_BLOKING;
+ break;
+ case ISISC_STP_LISTENING:
+ *state = FAL_STP_LISTENING;
+ break;
+ case ISISC_STP_LEARNING:
+ *state = FAL_STP_LEARNING;
+ break;
+ case ISISC_STP_FARWARDING:
+ *state = FAL_STP_FARWARDING;
+ break;
+ case ISISC_PORT_DISABLED:
+ *state = FAL_STP_DISABLED;
+ break;
+ default:
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_stp_port_state_set(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ Garuda only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_stp_port_state_get(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_stp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->stp_port_state_set = isisc_stp_port_state_set;
+ p_api->stp_port_state_get = isisc_stp_port_state_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_trunk.c b/src/hsl/isisc/isisc_trunk.c
new file mode 100644
index 0000000..23197dc
--- /dev/null
+++ b/src/hsl/isisc/isisc_trunk.c
@@ -0,0 +1,681 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+/**
+ * @defgroup isisc_trunk ISISC_TRUNK
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_trunk.h"
+#include "isisc_reg.h"
+
+#define ISISC_MAX_TRUNK_ID 3
+
+/*feature on/off for manipulating dp within trunk group*/
+#define ISISC_TRUNK_MANIPULATE_DP_ON 1
+#define ISISC_TRUNK_MANIPULATE_HEADER_LEN 12
+#define MAC_LEN 6
+#define HASH_SIZE 4
+
+enum isisc_trunk_reg_id
+{
+ ISISC_TRUNK_HASH_EN = 0, /*0x270*/
+ ISISC_TRUNK_CTRL_0, /*0x700*/
+ ISISC_TRUNK_CTRL_1, /*0x704*/
+ ISISC_TRUNK_CTRL_2, /*0x708*/
+ ISISC_TRUNK_REG_MAX
+};
+
+static a_uint32_t isisc_trunk_regs[ISISC_TRUNK_REG_MAX] =
+{
+ 0xf, 0x0, 0x0, 0x0
+};
+
+static a_uint8_t sa_hash[HASH_SIZE][MAC_LEN] =
+{
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 },
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 }
+};
+
+static sw_error_t
+_isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+ a_uint32_t i, reg, cnt = 0, data0 = 0, data1 = 0;
+
+ if (ISISC_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data0 = (0x1 << 7) | member;
+
+ for (i = 0; i < 7; i++)
+ {
+ if (member & (0x1 << i))
+ {
+ if (4 <= cnt)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data1 |= (i << (cnt << 2));
+ data1 |= (1 << (3 + (cnt << 2)));
+ cnt++;
+ }
+ }
+ }
+ else if (A_FALSE == enable)
+ {
+
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* set trunk port member bitmap info */
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= (~(0xff << (trunk_id << 3)));
+ reg |= (data0 << (trunk_id << 3));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_trunk_regs[ISISC_TRUNK_CTRL_0] = reg;
+
+ /* set trunk port member id info */
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ reg &= (~(0xffff << ((trunk_id % 2) << 4)));
+ reg |= (data1 << ((trunk_id % 2) << 4));
+
+ HSL_REG_ENTRY_SET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)] = reg;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ if (ISISC_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = (reg >> (trunk_id << 3)) & 0xff;
+ if (0x80 & data)
+ {
+ *enable = A_TRUE;
+ *member = data & 0x7f;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *member = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_group_sw_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg;
+
+ if (ISISC_MAX_TRUNK_ID < trunk_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_0];
+
+ data = (reg >> (trunk_id << 3)) & 0xff;
+ if (0x80 & data)
+ {
+ *enable = A_TRUE;
+ *member = data & 0x7f;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *member = 0;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t data = 0;
+
+ if (FAL_TRUNK_HASH_KEY_DA & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DA_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_SA & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SA_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_DIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, DIP_EN, 1, data);
+ }
+
+ if (FAL_TRUNK_HASH_KEY_SIP & hash_mode)
+ {
+ SW_SET_REG_BY_FIELD(TRUNK_HASH_MODE, SIP_EN, 1, data);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, TRUNK_HASH_MODE, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ isisc_trunk_regs[ISISC_TRUNK_HASH_EN] = data;
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data = 0;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, TRUNK_HASH_MODE, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *hash_mode = 0;
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+ }
+
+ return SW_OK;
+}
+
+#define BYTE_B2R(x, mask) ((x) ^ (mask))
+#define BYTE_B1C(x) ((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0x0f)+((((((x&0x55)+((x&0xaa)>>1))&0x33)+((((x&0x55)+((x&0xaa)>>1))&0xcc)>>2))&0xf0)>>4))
+
+static sw_error_t
+_isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < HASH_SIZE; i++)
+ {
+ memcpy(sa_hash[i], addr->uc, MAC_LEN);
+ sa_hash[i][MAC_LEN - 1] = BYTE_B2R(sa_hash[i][MAC_LEN - 1], i);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ memcpy(addr->uc, sa_hash[0], MAC_LEN);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_hash_mode_sw_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data = 0;
+
+ reg = isisc_trunk_regs[ISISC_TRUNK_HASH_EN];
+
+ *hash_mode = 0;
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SA_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SA;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, DIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_DIP;
+ }
+
+ SW_GET_FIELD_BY_REG(TRUNK_HASH_MODE, SIP_EN, data, reg);
+ if (data)
+ {
+ *hash_mode |= FAL_TRUNK_HASH_KEY_SIP;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_trunk_id_member_get(a_uint32_t dev_id, a_uint8_t expect_dp,
+ a_uint32_t * trunk_id, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+ a_bool_t enable;
+ a_uint32_t i;
+
+ for (i = 0; i <= ISISC_MAX_TRUNK_ID; i++)
+ {
+ rv = _isisc_trunk_group_sw_get(dev_id, i, &enable, member);
+ SW_RTN_ON_ERROR(rv);
+ if (enable && (*member & expect_dp))
+ {
+ *trunk_id = i;
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_trunk_hash_dp_get(a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+ a_uint32_t trunk_id, a_uint32_t mode, a_uint8_t * hash_dp)
+{
+#define BIT2_MASK 0x03
+#define TRUNK_MEM_EN_MASK 0x8
+#define TRUNK_MEM_PT_MASK 0x7
+#define TRUNK_HASH_DP_SEL 4
+ sw_error_t rv;
+ a_uint32_t i, hash_mode, reg, data1 = 0;
+ a_uint32_t da_xor = 0, sa_xor = 0; /*consider da-hash & sa-hash (TBD: dip-hash & sip-hash)*/
+ a_uint8_t xor_dp = 0;
+
+ rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!hash_mode)
+ {
+ return SW_DISABLE;
+ }
+
+ *hash_dp = 0;
+
+ if ((mode & FAL_TRUNK_HASH_KEY_DA) && (hash_mode & FAL_TRUNK_HASH_KEY_DA))
+ {
+ for (i = 0; i < MAC_LEN; i++)
+ {
+ da_xor ^= (header[i] & BIT2_MASK) ^
+ ((header[i] >> 2) & BIT2_MASK) ^
+ ((header[i] >> 4) & BIT2_MASK) ^
+ ((header[i] >> 6) & BIT2_MASK);
+ }
+ *hash_dp = da_xor;
+ }
+ if ((mode & FAL_TRUNK_HASH_KEY_SA) && (hash_mode & FAL_TRUNK_HASH_KEY_SA))
+ {
+ for (i = 6; i < 2 * MAC_LEN; i++)
+ {
+ sa_xor ^= (header[i] & BIT2_MASK) ^
+ ((header[i] >> 2) & BIT2_MASK) ^
+ ((header[i] >> 4) & BIT2_MASK) ^
+ ((header[i] >> 6) & BIT2_MASK);
+ }
+ *hash_dp = (*hash_dp) ^ sa_xor;
+ }
+
+ /*dp translation*/
+#if 0
+ HSL_REG_ENTRY_GET(rv, dev_id, GOL_TRUNK_CTL1, (trunk_id >> 1),
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#else /*sw*/
+ reg = isisc_trunk_regs[ISISC_TRUNK_CTRL_1 + (trunk_id >> 1)];
+#endif
+
+ for (i = 0; i < TRUNK_HASH_DP_SEL; i++)
+ {
+ xor_dp = BYTE_B2R(*hash_dp, i);
+ data1 = (0x0f & (reg >> (((trunk_id % 2) << 4) + (xor_dp << 2))));
+ if (data1 & TRUNK_MEM_EN_MASK)
+ {
+ *hash_dp = data1 & TRUNK_MEM_PT_MASK;
+ *hash_dp = 0x01 << (*hash_dp); /*bmp*/
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_isisc_trunk_sa_spoofing( a_uint32_t dev_id, a_uint8_t * header, a_uint32_t len,
+ a_uint8_t expect_dp, a_uint32_t trunk_id, fal_pbmp_t member)
+{
+ sw_error_t rv;
+ a_uint32_t i, hash_mode;
+ a_uint8_t hash_dp;
+ a_uint8_t ori_sa[MAC_LEN];
+
+ rv = _isisc_trunk_hash_mode_sw_get(dev_id, &hash_mode);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(hash_mode & FAL_TRUNK_HASH_KEY_SA))
+ {
+ return SW_DISABLE;
+ }
+
+ memcpy(ori_sa, &header[MAC_LEN], MAC_LEN);
+
+ for (i = 0; i < HASH_SIZE/*not HASH_SIZE, for RAD only*/; i++)
+ {
+ memcpy(&header[MAC_LEN], sa_hash[i], MAC_LEN);
+ rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+ FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+ SW_RTN_ON_ERROR(rv);
+ if (expect_dp == hash_dp)
+ {
+ // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, sa_id = %d\n", expect_dp, hash_dp, i);
+ return SW_OK;
+ }
+ }
+
+ /*should never here*/
+ memcpy(&header[MAC_LEN], ori_sa, MAC_LEN);
+ return SW_FAIL;
+}
+
+static sw_error_t
+_isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member)
+{
+ sw_error_t rv;
+ a_uint8_t expect_dp, hash_dp; /*bitmap*/
+ a_uint32_t i, trunk_id;
+ fal_pbmp_t member;
+
+ if (!ISISC_TRUNK_MANIPULATE_DP_ON)
+ {
+ return SW_OK; /*feature not enabled*/
+ }
+
+ if (!header || len < ISISC_TRUNK_MANIPULATE_HEADER_LEN)
+ {
+ return SW_BAD_VALUE;
+ }
+
+#if 0 /*de-comment this to ignore broadcast packets*/
+ const a_uint8_t bc_mac[MAC_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+ if (!memcmp(header, bc_mac, MAC_LEN)) /*not for broadcast*/
+ {
+ return SW_OK;
+ }
+#endif
+
+ /*expect_dp within trunk group*/
+ expect_dp = dp_member & 0x7f;
+ for (i = 0; i < 7; i++)
+ {
+ if (expect_dp & (0x01 << i))
+ {
+ rv = _isisc_trunk_id_member_get(dev_id, (0x01 << i), &trunk_id, &member);
+ if (rv != SW_OK)
+ {
+ expect_dp &= ~(0x01 << i); /*not the dp doesn't belong to trunk*/
+ }
+ }
+ }
+
+ if (BYTE_B1C(expect_dp) != 1) /*supports 1 dp only*/
+ {
+ return SW_OK; /*ignore none-dp or multi-dp*/
+ }
+
+ rv = _isisc_trunk_id_member_get(dev_id, expect_dp, &trunk_id, &member);
+ SW_RTN_ON_ERROR(rv);
+
+ member &= 0x7f;
+ if (BYTE_B1C(member) == 1) /*trunk group w/ one port*/
+ {
+ return SW_OK;
+ }
+
+ rv = _isisc_trunk_hash_dp_get(dev_id, header, len, trunk_id,
+ FAL_TRUNK_HASH_KEY_DA | FAL_TRUNK_HASH_KEY_SA, &hash_dp);
+ SW_RTN_ON_ERROR(rv);
+
+ // printk("expect_dp = 0x%x, hash_dp(DA+SA) = 0x%x, member = 0x%x\n", expect_dp, hash_dp, member);
+ if (expect_dp == hash_dp)
+ {
+ return SW_OK;
+ }
+
+ rv = _isisc_trunk_sa_spoofing(dev_id, header, len, expect_dp, trunk_id, member);
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+
+/**
+ * @brief Set particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[in] enable trunk group status, enable or disable
+ * @param[in] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_group_set(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t enable, fal_pbmp_t member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_group_set(dev_id, trunk_id, enable, member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular trunk group information on particular device.
+ * @param[in] dev_id device id
+ * @param[in] trunk_id trunk group id
+ * @param[out] enable trunk group status, enable or disable
+ * @param[out] member port member information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_group_get(a_uint32_t dev_id, a_uint32_t trunk_id,
+ a_bool_t * enable, fal_pbmp_t * member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_group_get(dev_id, trunk_id, enable, member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk hash mode on particular device.
+ * @details Comments:
+ hash mode is listed below
+ FAL_TRUNK_HASH_KEY_DA, FAL_TRUNK_HASH_KEY_SA, FAL_TRUNK_HASH_KEY_DIP and FAL_TRUNK_HASH_KEY_SIP
+ * @param[in] dev_id device id
+ * @param[in] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_hash_mode_set(a_uint32_t dev_id, a_uint32_t hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_hash_mode_set(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk hash mode on particular device.
+ * @param[in] dev_id device id
+ * @param[out] hash_mode trunk hash mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_hash_mode_get(a_uint32_t dev_id, a_uint32_t * hash_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_hash_mode_get(dev_id, hash_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[in] addr manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_sa_set(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_manipulate_sa_set(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get trunk manipulate SA on particular device.
+ * @param[in] dev_id device id
+ * @param[out] addr manipulate SA
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_sa_get(a_uint32_t dev_id, fal_mac_addr_t * addr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_manipulate_sa_get(dev_id, addr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief manipulate destination port within a trunk group
+ * @details Comments:
+ * supporting hash mode include: FAL_TRUNK_HASH_KEY_DA & FAL_TRUNK_HASH_KEY_SA;
+ * FAL_TRUNK_HASH_KEY_DIP & FAL_TRUNK_HASH_KEY_SIP are NOT covered in current design
+ * @param[in] dev_id device id
+ * @param[in-out] header packet header, accept format: [DA:6B][SA:6B]
+ * @param[in] len length of packet header, should be 12 in current design (6B DA + 6B SA)
+ * @param[in] dp_member expect destination port members, bitmap format
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_trunk_manipulate_dp(a_uint32_t dev_id, a_uint8_t * header,
+ a_uint32_t len, fal_pbmp_t dp_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_trunk_manipulate_dp(dev_id, header, len, dp_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+sw_error_t
+isisc_trunk_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->trunk_group_set = isisc_trunk_group_set;
+ p_api->trunk_group_get = isisc_trunk_group_get;
+ p_api->trunk_hash_mode_set = isisc_trunk_hash_mode_set;
+ p_api->trunk_hash_mode_get = isisc_trunk_hash_mode_get;
+ p_api->trunk_manipulate_sa_set = isisc_trunk_manipulate_sa_set;
+ p_api->trunk_manipulate_sa_get = isisc_trunk_manipulate_sa_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/isisc/isisc_vlan.c b/src/hsl/isisc/isisc_vlan.c
new file mode 100644
index 0000000..7a71ba1
--- /dev/null
+++ b/src/hsl/isisc/isisc_vlan.c
@@ -0,0 +1,897 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup isisc_vlan ISISC_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "isisc_vlan.h"
+#include "isisc_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+#define VLAN_NEXT_ENTRY 5
+#define VLAN_FIND_ENTRY 6
+
+static void
+_isisc_vlan_hw_to_sw(a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+ a_uint32_t i, data, tmp;
+
+ aos_mem_zero(vlan_entry, sizeof (fal_vlan_t));
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VLAN_ID, data, reg[1]);
+ vlan_entry->vid = data & 0xfff;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->fid = vlan_entry->vid;
+ }
+ else
+ {
+ vlan_entry->fid = FAL_SVL_FID;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->learn_dis = A_TRUE;
+ }
+ else
+ {
+ vlan_entry->learn_dis = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->vid_pri_en = A_TRUE;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+ vlan_entry->vid_pri = data & 0xff;
+ }
+ else
+ {
+ vlan_entry->vid_pri_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+ for (i = 0; i < 7; i++)
+ {
+ tmp = (data >> (i << 1)) & 0x3UL;
+ if (0 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->unmodify_ports |= (0x1UL << i);
+ }
+ else if (1 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->untagged_ports |= (0x1UL << i);
+ }
+ else if (2 == tmp)
+ {
+ vlan_entry->mem_ports |= (0x1UL << i);
+ vlan_entry->tagged_ports |= (0x1UL << i);
+ }
+ }
+
+ return;
+}
+
+static sw_error_t
+_isisc_vlan_sw_to_hw(a_uint32_t dev_id, const fal_vlan_t * vlan_entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t i, tag, untag, unmodify, member = 0;
+
+ if (vlan_entry->vid > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+
+ if (FAL_SVL_FID == vlan_entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+ }
+ else if (vlan_entry->vid == vlan_entry->fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (A_TRUE == vlan_entry->learn_dis)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ }
+
+ for (i = 0; i < 7; i++)
+ {
+ if ((vlan_entry->mem_ports >> i) & 0x1UL)
+ {
+ tag = (vlan_entry->tagged_ports >> i) & 0x1UL;
+ untag = (vlan_entry->untagged_ports >> i) & 0x1UL;
+ unmodify = (vlan_entry->unmodify_ports >> i) & 0x1UL;
+
+ if ((0 == (tag + untag + unmodify))
+ || (1 < (tag + untag + unmodify)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (tag)
+ {
+ member |= (2 << (i << 1));
+ }
+ else if (untag)
+ {
+ member |= (1 << (i << 1));
+ }
+ }
+ else
+ {
+ member |= (3 << (i << 1));
+ }
+ }
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, member, reg[0]);
+
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri,
+ reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_entry->vid, reg[1]);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_down_to_hw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_up_to_sw(a_uint32_t dev_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ vt_busy = 1;
+ i = 0x1000;
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_VALID,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (!val)
+ {
+ if (VLAN_FIND_ENTRY == op)
+ return SW_NOT_FOUND;
+
+ if (VLAN_NEXT_ENTRY == op)
+ return SW_NO_MORE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_hwentry_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t reg[])
+{
+ sw_error_t rv;
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_up_to_sw(dev_id, reg);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_sw_to_hw(dev_id, vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_VALID, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, 0x3fff, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+
+ rv = _isisc_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_NEXT_ENTRY_FIRST_ID == vlan_id)
+ {
+ rv = _isisc_vlan_hwentry_get(dev_id, 0, reg);
+
+ if (SW_OK == rv)
+ {
+ _isisc_vlan_hw_to_sw(reg, p_vlan);
+ return SW_OK;
+ }
+ else
+ {
+ vlan_id = 0;
+ }
+ }
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VLAN_ID, vlan_id, reg[1]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_up_to_sw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_vlan_hw_to_sw(reg, p_vlan);
+
+ if (0 == p_vlan->vid)
+ {
+ return SW_NO_MORE;
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ _isisc_vlan_hw_to_sw(reg, p_vlan);
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ reg = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VLAN_ID,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_FLUSH);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((MAX_VLAN_ID < fid) && (FAL_SVL_FID != fid))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((MAX_VLAN_ID >= fid) && (vlan_id != fid))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SVL_FID == fid)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 0, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, IVL_EN, 1, reg[0]);
+ }
+
+ rv = _isisc_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, IVL_EN, data, reg[0]);
+ if (data)
+ {
+ *fid = vlan_id;
+ }
+ else
+ {
+ *fid = FAL_SVL_FID;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_isisc_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, a_uint32_t port_info)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+ data &= (~(0x3 << (port_id << 1)));
+ data |= ((port_info & 0x3) << (port_id << 1));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VID_MEM, data, reg[0]);
+
+ rv = _isisc_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+ a_uint32_t info = 0;
+
+ if (FAL_EG_UNMODIFIED == port_info)
+ {
+ info = 0;
+ }
+ else if (FAL_EG_TAGGED == port_info)
+ {
+ info = 0x2;
+ }
+ else if (FAL_EG_UNTAGGED == port_info)
+ {
+ info = 0x1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t info = 0x3;
+
+ rv = _isisc_vlan_member_update(dev_id, vlan_id, port_id, info);
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 0, reg[0]);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, LEARN_DIS, 1, reg[0]);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = _isisc_vlan_down_to_hw(dev_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _isisc_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ if (SW_FULL == rv)
+ {
+ rv = SW_OK;
+ }
+ return rv;
+}
+
+static sw_error_t
+_isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data, reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _isisc_vlan_hwentry_get(dev_id, vlan_id, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, LEARN_DIS, data, reg[0]);
+ if (data)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+ return SW_OK;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_flush(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_fid_set(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t fid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_fid_set(dev_id, vlan_id, fid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FID of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] fid FDB id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_fid_get(a_uint32_t dev_id, a_uint32_t vlan_id, a_uint32_t * fid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_fid_get(dev_id, vlan_id, fid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a port member to a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @param[in] port_info port tag information
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_member_add(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_port_t port_id, fal_pt_1q_egmode_t port_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_member_add(dev_id, vlan_id, port_id, port_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Del a port member from a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_member_del(a_uint32_t dev_id, a_uint32_t vlan_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_member_del(dev_id, vlan_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_learning_state_set(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_learning_state_set(dev_id, vlan_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get FDB learning status of a paticular vlan entry on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_vlan_learning_state_get(a_uint32_t dev_id, a_uint32_t vlan_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_vlan_learning_state_get(dev_id, vlan_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+isisc_vlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = isisc_vlan_entry_append;
+ p_api->vlan_creat = isisc_vlan_create;
+ p_api->vlan_delete = isisc_vlan_delete;
+ p_api->vlan_next = isisc_vlan_next;
+ p_api->vlan_find = isisc_vlan_find;
+ p_api->vlan_flush = isisc_vlan_flush;
+ p_api->vlan_fid_set = isisc_vlan_fid_set;
+ p_api->vlan_fid_get = isisc_vlan_fid_get;
+ p_api->vlan_member_add = isisc_vlan_member_add;
+ p_api->vlan_member_del = isisc_vlan_member_del;
+ p_api->vlan_learning_state_set = isisc_vlan_learning_state_set;
+ p_api->vlan_learning_state_get = isisc_vlan_learning_state_get;
+
+
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/phy/Makefile b/src/hsl/phy/Makefile
new file mode 100644
index 0000000..e69afdb
--- /dev/null
+++ b/src/hsl/phy/Makefile
@@ -0,0 +1,46 @@
+LOC_DIR=src/hsl/phy
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+ifeq (ATHENA, $(CHIP_TYPE))
+ SRC_LIST = f2_phy.c
+endif
+
+ifeq (GARUDA, $(CHIP_TYPE))
+ SRC_LIST = f1_phy.c
+endif
+
+ifeq (SHIVA, $(CHIP_TYPE))
+ SRC_LIST = f2_phy.c
+endif
+
+ifeq (HORUS, $(CHIP_TYPE))
+ SRC_LIST = f2_phy.c
+endif
+
+ifeq (ISIS, $(CHIP_TYPE))
+ SRC_LIST = f1_phy.c
+endif
+
+ifeq (ISISC, $(CHIP_TYPE))
+ SRC_LIST = f1_phy.c
+endif
+
+ifeq (ALL_CHIP, $(CHIP_TYPE))
+ SRC_LIST = f1_phy.c f2_phy.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=
+ endif
+ endif
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/hsl/phy/f1_phy.c b/src/hsl/phy/f1_phy.c
new file mode 100644
index 0000000..be527c2
--- /dev/null
+++ b/src/hsl/phy/f1_phy.c
@@ -0,0 +1,1234 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "f1_phy.h"
+#include "aos_timer.h"
+
+static a_uint16_t
+_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg)
+{
+ sw_error_t rv;
+ a_uint16_t val;
+
+ HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val);
+ if (SW_OK != rv)
+ return 0xFFFF;
+
+ return val;
+}
+
+static void
+_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint32_t reg,
+ a_uint16_t val)
+{
+ sw_error_t rv;
+
+ HSL_PHY_SET(rv, dev_id, phy_addr, reg, val);
+}
+
+#define f1_phy_reg_read _phy_reg_read
+#define f1_phy_reg_write _phy_reg_write
+
+/******************************************************************************
+*
+* f1_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+f1_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+ a_uint16_t reg_val)
+{
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id);
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, reg_val);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+f1_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, reg_id);
+ return f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* f1_phy_mmd_write - PHY MMD register write
+*
+* PHY MMD register write
+*/
+sw_error_t
+f1_phy_mmd_write(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t mmd_num,
+ a_uint16_t reg_id,
+ a_uint16_t reg_val)
+{
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num);
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id);
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num);
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_val);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_mmd_read - PHY MMD register read
+*
+* PHY MMD register read
+*/
+a_uint16_t
+f1_phy_mmd_read(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t mmd_num,
+ a_uint16_t reg_id)
+{
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, mmd_num);
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_DATA_REG, reg_id);
+ f1_phy_reg_write(dev_id, phy_id, F1_MMD_CTRL_REG, 0x4000|mmd_num);
+
+ return f1_phy_reg_read(dev_id, phy_id, F1_MMD_DATA_REG);
+}
+
+
+/******************************************************************************
+*
+* f1_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f1_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+ a_uint16_t phy_data;
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29);
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+ if(enable == A_TRUE)
+ {
+ phy_data |= 0x8000;
+ }
+ else
+ {
+ phy_data &= ~0x8000;
+ }
+
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f1_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+ a_uint16_t phy_data;
+ *enable = A_FALSE;
+
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0x29);
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+ if(phy_data & 0x8000)
+ *enable = A_TRUE;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+f1_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+ a_uint16_t phy_data;
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb);
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+ if(enable == A_TRUE)
+ {
+ phy_data |= 0x8000;
+ }
+ else
+ {
+ phy_data &= ~0x8000;
+ }
+
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_DATA, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+f1_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+ a_uint16_t phy_data;
+ *enable = A_FALSE;
+
+ f1_phy_reg_write(dev_id, phy_id, F1_DEBUG_PORT_ADDRESS, 0xb);
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_DEBUG_PORT_DATA);
+
+ if(phy_data & 0x8000)
+ *enable = A_TRUE;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+#ifdef ISISC
+#define RUN_CDT 0x8000
+#define CABLE_LENGTH_UNIT 0x0400
+sw_error_t f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id);
+a_bool_t f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id);
+a_bool_t f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id);
+
+static inline fal_cable_status_t
+_fal_cdt_status_mapping(a_uint16_t status)
+{
+ fal_cable_status_t status_mapping = FAL_CABLE_STATUS_INVALID;
+
+ if (0 == status)
+ status_mapping = FAL_CABLE_STATUS_INVALID;
+ else if (1 == status)
+ status_mapping = FAL_CABLE_STATUS_NORMAL;
+ else if (2 == status)
+ status_mapping = FAL_CABLE_STATUS_OPENED;
+ else if (3 == status)
+ status_mapping = FAL_CABLE_STATUS_SHORT;
+
+ return status_mapping;
+}
+
+static sw_error_t
+f1_phy_cdt_start(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t status = 0;
+ a_uint16_t ii = 100;
+
+ /* RUN CDT */
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, RUN_CDT|CABLE_LENGTH_UNIT);
+ do
+ {
+ aos_mdelay(30);
+ status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL);
+ }
+ while ((status & RUN_CDT) && (--ii));
+
+ return SW_OK;
+}
+
+sw_error_t
+f1_phy_cdt_get(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_cdt_t *port_cdt)
+{
+ a_uint16_t status = 0;
+ a_uint16_t cable_delta_time = 0;
+ a_uint16_t org_debug_value = 0;
+ int ii = 100;
+ a_bool_t link_st = A_FALSE;
+ a_uint16_t reg806e = 0;
+ int i;
+
+ if((!port_cdt) || (phy_id > 4))
+ {
+ return SW_FAIL;
+ }
+
+ /*disable clock gating*/
+ org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f);
+ f1_phy_debug_write(dev_id, phy_id, 0x3f, 0);
+
+ f1_phy_cdt_start(dev_id, phy_id);
+
+ /* Get cable status */
+ status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064);
+
+ /* Workaround for cable lenth less than 20M */
+ port_cdt->pair_c_status = (status >> 4) & 0x3;
+ /* Get Cable Length value */
+ cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067);
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ port_cdt->pair_c_len = (cable_delta_time * 824) /1000;
+ if ((1 == port_cdt->pair_c_status) &&
+ (port_cdt->pair_c_len > 0) && (port_cdt->pair_c_len <= 20))
+ {
+ reg806e = f1_phy_mmd_read(dev_id, phy_id, 3, 0x806e);
+ f1_phy_mmd_write(dev_id, phy_id, 3, 0x806e, reg806e & (~0x8000));
+
+ f1_phy_reset(dev_id, phy_id);
+ f1_phy_reset_done(dev_id, phy_id);
+ do
+ {
+ link_st = f1_phy_get_link_status(dev_id, phy_id);
+ aos_mdelay(100);
+ } while ((A_FALSE == link_st) && (--ii));
+
+ f1_phy_cdt_start(dev_id, phy_id);
+ /* Get cable status */
+ status = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8064);
+ }
+
+ for (i=0;i<4;i++)
+ {
+ switch(i)
+ {
+ case 0:
+ port_cdt->pair_a_status = (status >> 12) & 0x3;
+ /* Get Cable Length value */
+ cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8065);
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ port_cdt->pair_a_len = (cable_delta_time * 824) /1000;
+
+ break;
+ case 1:
+ port_cdt->pair_b_status = (status >> 8) & 0x3;
+ /* Get Cable Length value */
+ cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8066);
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ port_cdt->pair_b_len = (cable_delta_time * 824) /1000;
+ break;
+ case 2:
+ port_cdt->pair_c_status = (status >> 4) & 0x3;
+ /* Get Cable Length value */
+ cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8067);
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ port_cdt->pair_c_len = (cable_delta_time * 824) /1000;
+ break;
+ case 3:
+ port_cdt->pair_d_status = status & 0x3;
+ /* Get Cable Length value */
+ cable_delta_time = f1_phy_mmd_read(dev_id, phy_id, 3, 0x8068);
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ port_cdt->pair_d_len = (cable_delta_time * 824) /1000;
+ break;
+ default:
+ break;
+ }
+ }
+
+ /*restore debug port value*/
+ f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value);
+
+ return SW_OK;
+}
+
+sw_error_t
+f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ fal_port_cdt_t f1_port_cdt;
+
+ if((mdi_pair >= 4) || (phy_id > 4))
+ {
+ //There are only 4 mdi pairs in 1000BASE-T
+ return SW_BAD_PARAM;
+ }
+
+ f1_phy_cdt_get(dev_id, phy_id, &f1_port_cdt);
+
+ switch(mdi_pair)
+ {
+ case 0:
+ *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_a_status);
+ /* Get Cable Length value */
+ *cable_len = f1_port_cdt.pair_a_len;
+ break;
+ case 1:
+ *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_b_status);
+ /* Get Cable Length value */
+ *cable_len = f1_port_cdt.pair_b_len;
+ break;
+ case 2:
+ *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_c_status);
+ /* Get Cable Length value */
+ *cable_len = f1_port_cdt.pair_c_len;
+ break;
+ case 3:
+ *cable_status = _fal_cdt_status_mapping(f1_port_cdt.pair_d_status);
+ /* Get Cable Length value */
+ *cable_len = f1_port_cdt.pair_d_len;
+ break;
+ default:
+ break;
+ }
+
+ return SW_OK;
+}
+#else
+sw_error_t
+f1_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ a_uint16_t status = 0;
+ a_uint16_t ii = 100;
+
+ if(!cable_status || !cable_len)
+ {
+ return SW_FAIL;
+ }
+
+ if(mdi_pair >= 4)
+ {
+ //There are only 4 mdi pairs in 1000BASE-T
+ return SW_BAD_PARAM;
+ }
+
+ a_uint16_t org_debug_value = f1_phy_debug_read(dev_id, phy_id, 0x3f);
+
+ /*disable clock gating*/
+ f1_phy_debug_write(dev_id, phy_id, 0x3f, 0);
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001);
+
+ do
+ {
+ aos_mdelay(30);
+ status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_CONTROL);
+ }
+ while ((status & 0x0001) && (--ii));
+
+ status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CDT_STATUS);
+
+ *cable_status = (status&0x300) >> 8;
+ if ( (*cable_status == 1) || (*cable_status == 2))
+ {
+ if ( mdi_pair == 1 || mdi_pair == 3 )
+ {
+ /*Reverse the mdi status for channel 1 and channel 3*/
+ *cable_status = (~(*cable_status)) & 0x3;
+ }
+ }
+
+ /* the actual cable length equals to CableDeltaTime * 0.824*/
+ a_uint16_t cable_delta_time = status & 0xff;
+ *cable_len = (cable_delta_time * 824) /1000;
+
+ /*restore debug port value*/
+ f1_phy_debug_write(dev_id, phy_id, 0x3f, org_debug_value);
+ //f1_phy_reg_write(dev_id, phy_id, 0x00, 0x9000);//Reset the PHY if necessary
+
+ return SW_OK;
+}
+#endif
+
+/******************************************************************************
+*
+* f1_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f1_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+ aos_mdelay(10);
+ }
+ while ((!F1_RESET_DONE(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_autoneg_done
+*
+* f1_autoneg_done
+*/
+a_bool_t
+f1_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+ aos_mdelay(10);
+ }
+ while ((!F1_AUTONEG_DONE(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f1_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+ aos_mdelay(10);
+ }
+ while ((!F1_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f1_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t
+f1_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+ phy_data | F1_CTRL_SOFTWARE_RESET);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_off - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f1_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+ phy_data | F1_CTRL_POWER_DOWN);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_on - power on the phy after speed changed
+*
+* Power on the phy
+*/
+sw_error_t
+f1_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+ phy_data & ~F1_CTRL_POWER_DOWN);
+
+ aos_mdelay(200);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f1_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * ability)
+{
+ a_uint16_t phy_data;
+
+ *ability = 0;
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+
+ if (phy_data & F1_STATUS_AUTONEG_CAPS)
+ *ability |= FAL_PHY_AUTONEG_CAPS;
+
+ if (phy_data & F1_STATUS_100T2_HD_CAPS)
+ *ability |= FAL_PHY_100T2_HD_CAPS;
+
+ if (phy_data & F1_STATUS_100T2_FD_CAPS)
+ *ability |= FAL_PHY_100T2_FD_CAPS;
+
+ if (phy_data & F1_STATUS_10T_HD_CAPS)
+ *ability |= FAL_PHY_10T_HD_CAPS;
+
+ if (phy_data & F1_STATUS_10T_FD_CAPS)
+ *ability |= FAL_PHY_10T_FD_CAPS;
+
+ if (phy_data & F1_STATUS_100X_HD_CAPS)
+ *ability |= FAL_PHY_100X_HD_CAPS;
+
+ if (phy_data & F1_STATUS_100X_FD_CAPS)
+ *ability |= FAL_PHY_100X_FD_CAPS;
+
+ if (phy_data & F1_STATUS_100T4_CAPS)
+ *ability |= FAL_PHY_100T4_CAPS;
+
+ if (phy_data & F1_STATUS_EXTENDED_STATUS)
+ {
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_EXTENDED_STATUS);
+
+ if (phy_data & F1_STATUS_1000T_FD_CAPS)
+ {
+ *ability |= FAL_PHY_1000T_FD_CAPS;
+ }
+
+ if (phy_data & F1_STATUS_1000X_FD_CAPS)
+ {
+ *ability |= FAL_PHY_1000X_FD_CAPS;
+ }
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f1_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * ability)
+{
+ a_uint16_t phy_data;
+
+ *ability = 0;
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_LINK_PARTNER_ABILITY);
+
+ if (phy_data & F1_LINK_10BASETX_HALF_DUPLEX)
+ *ability |= FAL_PHY_PART_10T_HD;
+
+ if (phy_data & F1_LINK_10BASETX_FULL_DUPLEX)
+ *ability |= FAL_PHY_PART_10T_FD;
+
+ if (phy_data & F1_LINK_100BASETX_HALF_DUPLEX)
+ *ability |= FAL_PHY_PART_100TX_HD;
+
+ if (phy_data & F1_LINK_100BASETX_FULL_DUPLEX)
+ *ability |= FAL_PHY_PART_100TX_FD;
+
+ if (phy_data & F1_LINK_NPAGE)
+ {
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_STATUS);
+
+ if (phy_data & F1_LINK_1000BASETX_FULL_DUPLEX)
+ *ability |= FAL_PHY_PART_1000T_FD;
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+* A_TRUE --> link is alive
+* A_FALSE --> link is down
+*/
+a_bool_t
+f1_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+
+ if (phy_data & F1_STATUS_LINK_PASS)
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f1_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f1_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t autoneg)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT);
+ phy_data &= ~F1_ADVERTISE_MEGA_ALL;
+ phy_data &= ~(F1_ADVERTISE_PAUSE | F1_ADVERTISE_ASYM_PAUSE);
+
+ if (autoneg & FAL_PHY_ADV_100TX_FD)
+ phy_data |= F1_ADVERTISE_100FULL;
+
+ if (autoneg & FAL_PHY_ADV_100TX_HD)
+ phy_data |= F1_ADVERTISE_100HALF;
+
+ if (autoneg & FAL_PHY_ADV_10T_FD)
+ phy_data |= F1_ADVERTISE_10FULL;
+
+ if (autoneg & FAL_PHY_ADV_10T_HD)
+ phy_data |= F1_ADVERTISE_10HALF;
+
+ if (autoneg & FAL_PHY_ADV_PAUSE)
+ phy_data |= F1_ADVERTISE_PAUSE;
+
+ if (autoneg & FAL_PHY_ADV_ASY_PAUSE)
+ phy_data |= F1_ADVERTISE_ASYM_PAUSE;
+
+ f1_phy_reg_write(dev_id, phy_id, F1_AUTONEG_ADVERT, phy_data);
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL);
+ phy_data &= ~F1_ADVERTISE_1000FULL;
+ phy_data &= ~F1_ADVERTISE_1000HALF;
+
+ if (autoneg & FAL_PHY_ADV_1000T_FD)
+ phy_data |= F1_ADVERTISE_1000FULL;
+
+ f1_phy_reg_write(dev_id, phy_id, F1_1000BASET_CONTROL, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f1_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * autoneg)
+{
+ a_uint16_t phy_data = 0;
+
+ *autoneg = 0;
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_AUTONEG_ADVERT);
+
+ if (phy_data & F1_ADVERTISE_100FULL)
+ *autoneg |= FAL_PHY_ADV_100TX_FD;
+
+ if (phy_data & F1_ADVERTISE_100HALF)
+ *autoneg |= FAL_PHY_ADV_100TX_HD;
+
+ if (phy_data & F1_ADVERTISE_10FULL)
+ *autoneg |= FAL_PHY_ADV_10T_FD;
+
+ if (phy_data & F1_ADVERTISE_10HALF)
+ *autoneg |= FAL_PHY_ADV_10T_HD;
+
+ if (phy_data & F1_ADVERTISE_PAUSE)
+ *autoneg |= FAL_PHY_ADV_PAUSE;
+
+ if (phy_data & F1_ADVERTISE_ASYM_PAUSE)
+ *autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_1000BASET_CONTROL);
+
+ if (phy_data & F1_ADVERTISE_1000FULL)
+ *autoneg |= FAL_PHY_ADV_1000T_FD;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+a_bool_t
+f1_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+ if (phy_data & F1_CTRL_AUTONEGOTIATION_ENABLE)
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f1_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t
+f1_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+ phy_data |= F1_CTRL_AUTONEGOTIATION_ENABLE;
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+ phy_data | F1_CTRL_RESTART_AUTONEGOTIATION);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f1_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_CONTROL);
+
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL,
+ phy_data | F1_CTRL_AUTONEGOTIATION_ENABLE);
+
+ return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f1_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+
+sw_error_t
+f1_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t * speed)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+
+ switch (phy_data & F1_STATUS_SPEED_MASK)
+ {
+ case F1_STATUS_SPEED_1000MBS:
+ *speed = FAL_SPEED_1000;
+ break;
+ case F1_STATUS_SPEED_100MBS:
+ *speed = FAL_SPEED_100;
+ break;
+ case F1_STATUS_SPEED_10MBS:
+ *speed = FAL_SPEED_10;
+ break;
+ default:
+ return SW_READ_ERROR;
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t speed)
+{
+ a_uint16_t phy_data = 0;
+ a_uint16_t phy_status = 0;
+
+ a_uint32_t autoneg, oldneg;
+ fal_port_duplex_t old_duplex;
+
+ if (FAL_SPEED_1000 == speed)
+ {
+ phy_data |= F1_CTRL_SPEED_1000;
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ phy_data |= F1_CTRL_SPEED_100;
+ }
+ else if (FAL_SPEED_10 == speed)
+ {
+ phy_data |= F1_CTRL_SPEED_10;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE;
+
+ (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+ oldneg = autoneg;
+ autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL;
+
+ (void)f1_phy_get_duplex(dev_id, phy_id, &old_duplex);
+
+ if (old_duplex == FAL_FULL_DUPLEX)
+ {
+ phy_data |= F1_CTRL_FULL_DUPLEX;
+
+ if (FAL_SPEED_1000 == speed)
+ {
+ autoneg |= FAL_PHY_ADV_1000T_FD;
+ }
+ else if (FAL_SPEED_100 == speed)
+ {
+ autoneg |= FAL_PHY_ADV_100TX_FD;
+ }
+ else
+ {
+ autoneg |= FAL_PHY_ADV_10T_FD;
+ }
+ }
+ else if (old_duplex == FAL_HALF_DUPLEX)
+ {
+ phy_data &= ~F1_CTRL_FULL_DUPLEX;
+
+ if (FAL_SPEED_100 == speed)
+ {
+ autoneg |= FAL_PHY_ADV_100TX_HD;
+ }
+ else
+ {
+ autoneg |= FAL_PHY_ADV_10T_HD;
+ }
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+
+ (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+ (void)f1_phy_restart_autoneg(dev_id, phy_id);
+ if(f1_phy_get_link_status(dev_id, phy_id))
+ {
+ do
+ {
+ phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+ }
+ while(!F1_AUTONEG_DONE(phy_status));
+ }
+
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data);
+ (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+ return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* f1_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t * duplex)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_SPEC_STATUS);
+
+ //read duplex
+ if (phy_data & F1_STATUS_FULL_DUPLEX)
+ *duplex = FAL_FULL_DUPLEX;
+ else
+ *duplex = FAL_HALF_DUPLEX;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*/
+sw_error_t
+f1_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t duplex)
+{
+ a_uint16_t phy_data = 0;
+ a_uint16_t phy_status = 0;
+
+ fal_port_speed_t old_speed;
+ a_uint32_t oldneg, autoneg;
+
+ if (A_TRUE == f1_phy_autoneg_status(dev_id, phy_id))
+ phy_data &= ~F1_CTRL_AUTONEGOTIATION_ENABLE;
+
+ (void)f1_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+ oldneg = autoneg;
+ autoneg &= ~FAL_PHY_ADV_GE_SPEED_ALL;
+ (void)f1_phy_get_speed(dev_id, phy_id, &old_speed);
+
+ if (FAL_SPEED_1000 == old_speed)
+ {
+ phy_data |= F1_CTRL_SPEED_1000;
+ }
+ else if (FAL_SPEED_100 == old_speed)
+ {
+ phy_data |= F1_CTRL_SPEED_100;
+ }
+ else if (FAL_SPEED_10 == old_speed)
+ {
+ phy_data |= F1_CTRL_SPEED_10;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+
+ if (duplex == FAL_FULL_DUPLEX)
+ {
+ phy_data |= F1_CTRL_FULL_DUPLEX;
+
+ if (FAL_SPEED_1000 == old_speed)
+ {
+ autoneg = FAL_PHY_ADV_1000T_FD;
+ }
+ else if (FAL_SPEED_100 == old_speed)
+ {
+ autoneg = FAL_PHY_ADV_100TX_FD;
+ }
+ else
+ {
+ autoneg = FAL_PHY_ADV_10T_FD;
+ }
+ }
+ else if (duplex == FAL_HALF_DUPLEX)
+ {
+ phy_data &= ~F1_CTRL_FULL_DUPLEX;
+
+ if (FAL_SPEED_100 == old_speed)
+ {
+ autoneg = FAL_PHY_ADV_100TX_HD;
+ }
+ else
+ {
+ autoneg = FAL_PHY_ADV_10T_HD;
+ }
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ (void)f1_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+ (void)f1_phy_restart_autoneg(dev_id, phy_id);
+ if(f1_phy_get_link_status(dev_id, phy_id))
+ {
+ do
+ {
+ phy_status = f1_phy_reg_read(dev_id, phy_id, F1_PHY_STATUS);
+ }
+ while(!F1_AUTONEG_DONE(phy_status));
+ }
+
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_CONTROL, phy_data);
+ (void)f1_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_get_phy_id - get the phy id
+*
+*/
+static sw_error_t
+f1_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+ *org_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID1);
+ *rev_id = f1_phy_reg_read(dev_id, phy_id, F1_PHY_ID2);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_mask_set - Set interrupt mask with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_mask_set(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t intr_mask_flag)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK);
+
+ if (FAL_PHY_INTR_STATUS_UP_CHANGE & intr_mask_flag)
+ {
+ phy_data |= F1_INTR_STATUS_UP_CHANGE;
+ }
+ else
+ {
+ phy_data &= (~F1_INTR_STATUS_UP_CHANGE);
+ }
+
+ if (FAL_PHY_INTR_STATUS_DOWN_CHANGE & intr_mask_flag)
+ {
+ phy_data |= F1_INTR_STATUS_DOWN_CHANGE;
+ }
+ else
+ {
+ phy_data &= (~F1_INTR_STATUS_DOWN_CHANGE);
+ }
+
+ if (FAL_PHY_INTR_SPEED_CHANGE & intr_mask_flag)
+ {
+ phy_data |= F1_INTR_SPEED_CHANGE;
+ }
+ else
+ {
+ phy_data &= (~F1_INTR_SPEED_CHANGE);
+ }
+
+ if (FAL_PHY_INTR_DUPLEX_CHANGE & intr_mask_flag)
+ {
+ phy_data |= F1_INTR_DUPLEX_CHANGE;
+ }
+ else
+ {
+ phy_data &= (~F1_INTR_DUPLEX_CHANGE);
+ }
+
+ f1_phy_reg_write(dev_id, phy_id, F1_PHY_INTR_MASK, phy_data);
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_mask_get - Get interrupt mask with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_mask_get(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * intr_mask_flag)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_MASK);
+
+ *intr_mask_flag = 0;
+ if (F1_INTR_STATUS_UP_CHANGE & phy_data)
+ {
+ *intr_mask_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+ }
+
+ if (F1_INTR_STATUS_DOWN_CHANGE & phy_data)
+ {
+ *intr_mask_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+ }
+
+ if (F1_INTR_SPEED_CHANGE & phy_data)
+ {
+ *intr_mask_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+ }
+
+ if (F1_INTR_DUPLEX_CHANGE & phy_data)
+ {
+ *intr_mask_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_intr_status_get - Get interrupt status with the
+* specified device.
+*/
+sw_error_t
+f1_phy_intr_status_get(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * intr_status_flag)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f1_phy_reg_read(dev_id, phy_id, F1_PHY_INTR_STATUS);
+
+ *intr_status_flag = 0;
+ if (F1_INTR_STATUS_UP_CHANGE & phy_data)
+ {
+ *intr_status_flag |= FAL_PHY_INTR_STATUS_UP_CHANGE;
+ }
+
+ if (F1_INTR_STATUS_DOWN_CHANGE & phy_data)
+ {
+ *intr_status_flag |= FAL_PHY_INTR_STATUS_DOWN_CHANGE;
+ }
+
+ if (F1_INTR_SPEED_CHANGE & phy_data)
+ {
+ *intr_status_flag |= FAL_PHY_INTR_SPEED_CHANGE;
+ }
+
+ if (F1_INTR_DUPLEX_CHANGE & phy_data)
+ {
+ *intr_status_flag |= FAL_PHY_INTR_DUPLEX_CHANGE;
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f1_phy_init -
+*
+*/
+a_bool_t
+f1_phy_init(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t org_id, a_uint16_t rev_id)
+{
+ a_uint16_t org_tmp, rev_tmp;
+
+ (void)f1_phy_get_phy_id(dev_id, phy_id, &org_tmp, &rev_tmp);
+ if ((org_id == org_tmp) && (rev_id == rev_tmp))
+ return A_TRUE;
+ else
+ return A_FALSE;
+}
diff --git a/src/hsl/phy/f2_phy.c b/src/hsl/phy/f2_phy.c
new file mode 100644
index 0000000..c7d2fde
--- /dev/null
+++ b/src/hsl/phy/f2_phy.c
@@ -0,0 +1,833 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "fal_port_ctrl.h"
+#include "hsl_api.h"
+#include "hsl.h"
+#include "f2_phy.h"
+
+static a_uint16_t
+_phy_reg_read(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg)
+{
+ sw_error_t rv;
+ a_uint16_t val;
+
+ HSL_PHY_GET(rv, dev_id, phy_addr, reg, &val);
+ if (SW_OK != rv)
+ return 0xFFFF;
+
+ return val;
+}
+
+
+static void
+_phy_reg_write(a_uint32_t dev_id, a_uint32_t phy_addr, a_uint8_t reg,
+ a_uint16_t val)
+{
+ sw_error_t rv;
+
+ HSL_PHY_SET(rv, dev_id, phy_addr, reg, val);
+}
+
+#define f2_phy_reg_read _phy_reg_read
+#define f2_phy_reg_write _phy_reg_write
+
+/******************************************************************************
+*
+* f2_phy_debug_write - debug port write
+*
+* debug port write
+*/
+sw_error_t
+f2_phy_debug_write(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id,
+ a_uint16_t reg_val)
+{
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id);
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, reg_val);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_debug_read - debug port read
+*
+* debug port read
+*/
+a_uint16_t
+f2_phy_debug_read(a_uint32_t dev_id, a_uint32_t phy_id, a_uint16_t reg_id)
+{
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, reg_id);
+ return f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+}
+
+/******************************************************************************
+*
+* f2_phy_set_powersave - set power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f2_phy_set_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+ a_uint16_t phy_data;
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29);
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+ if(enable == A_TRUE)
+ {
+ phy_data |= 0x8000;
+ }
+ else
+ {
+ phy_data &= ~0x8000;
+ }
+
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_powersave - get power saving status
+*
+* set power saving status
+*/
+sw_error_t
+f2_phy_get_powersave(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+ a_uint16_t phy_data;
+ *enable = A_FALSE;
+
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0x29);
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+ if(phy_data & 0x8000)
+ *enable = A_TRUE;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_hibernate - set hibernate status
+*
+* set hibernate status
+*/
+sw_error_t
+f2_phy_set_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t enable)
+{
+ a_uint16_t phy_data;
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb);
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+ if(enable == A_TRUE)
+ {
+ phy_data |= 0x8000;
+ }
+ else
+ {
+ phy_data &= ~0x8000;
+ }
+
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_DATA, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_hibernate - get hibernate status
+*
+* get hibernate status
+*/
+sw_error_t
+f2_phy_get_hibernate(a_uint32_t dev_id, a_uint32_t phy_id, a_bool_t *enable)
+{
+ a_uint16_t phy_data;
+ *enable = A_FALSE;
+
+ f2_phy_reg_write(dev_id, phy_id, F2_DEBUG_PORT_ADDRESS, 0xb);
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_DEBUG_PORT_DATA);
+
+ if(phy_data & 0x8000)
+ *enable = A_TRUE;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_cdt - cable diagnostic test
+*
+* cable diagnostic test
+*/
+sw_error_t
+f2_phy_cdt(a_uint32_t dev_id, a_uint32_t phy_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ a_uint16_t status = 0;
+ a_uint16_t ii = 100;
+
+ if(!cable_status || !cable_len)
+ {
+ return SW_FAIL;
+ }
+
+ if(mdi_pair >= 2)
+ {
+ //There are only 4 mdi pairs in 1000BASE-T
+ return SW_BAD_PARAM;
+ }
+
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CDT_CONTROL, (mdi_pair << 8) | 0x0001);
+
+ do
+ {
+ aos_mdelay(30);
+ status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_CONTROL);
+ }
+ while ((status & 0x0001) && (--ii));
+
+ status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CDT_STATUS);
+ *cable_status = (status & 0x300) >> 8;//(00:normal 01:short 10:opened 11:invalid)
+
+ /*the actual cable length equals to CableDeltaTime * 0.824*/
+ a_uint16_t cable_delta_time = status & 0xff;
+ *cable_len = (cable_delta_time * 824) /1000;
+
+ /*workaround*/
+ if(*cable_len <= 2 && *cable_status == 1)
+ *cable_status = 2;
+
+ //f2_phy_reg_write(dev_id, phy_id, 0x00, 0x9000); //Reset the PHY if necessary
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_reset_done - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f2_phy_reset_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+ aos_mdelay(10);
+ }
+ while ((!F2_RESET_DONE(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_autoneg_done
+*
+* f2_autoneg_done
+*/
+a_bool_t
+f2_autoneg_done(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+ aos_mdelay(10);
+ }
+ while ((!F2_AUTONEG_DONE(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_phy_Speed_Duplex_Resolved
+ - reset the phy
+*
+* reset the phy
+*/
+a_bool_t
+f2_phy_speed_duplex_resolved(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ a_uint16_t ii = 200;
+
+ do
+ {
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+ aos_mdelay(10);
+ }
+ while ((!F2_SPEED_DUPLEX_RESOVLED(phy_data)) && --ii);
+
+ if (ii == 0)
+ return A_FALSE;
+
+ return A_TRUE;
+}
+
+/******************************************************************************
+*
+* f2_phy_reset - reset the phy
+*
+* reset the phy
+*/
+sw_error_t
+f2_phy_reset(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+ phy_data | F2_CTRL_SOFTWARE_RESET);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_off - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f2_phy_poweroff(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+ phy_data | F2_CTRL_POWER_DOWN);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_on - power on the phy after speed changed
+*
+* Power on the phy
+*/
+sw_error_t
+f2_phy_poweron(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+ phy_data & ~F2_CTRL_POWER_DOWN);
+
+ aos_mdelay(200);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f2_phy_get_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t * ability)
+{
+ a_uint16_t phy_data;
+
+ *ability = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+
+ if (phy_data & F2_STATUS_AUTONEG_CAPS)
+ *ability |= FAL_PHY_AUTONEG_CAPS;
+
+ if (phy_data & F2_STATUS_100T2_HD_CAPS)
+ *ability |= FAL_PHY_100T2_HD_CAPS;
+
+ if (phy_data & F2_STATUS_100T2_FD_CAPS)
+ *ability |= FAL_PHY_100T2_FD_CAPS;
+
+ if (phy_data & F2_STATUS_10T_HD_CAPS)
+ *ability |= FAL_PHY_10T_HD_CAPS;
+
+ if (phy_data & F2_STATUS_10T_FD_CAPS)
+ *ability |= FAL_PHY_10T_FD_CAPS;
+
+ if (phy_data & F2_STATUS_100X_HD_CAPS)
+ *ability |= FAL_PHY_100X_HD_CAPS;
+
+ if (phy_data & F2_STATUS_100X_FD_CAPS)
+ *ability |= FAL_PHY_100X_FD_CAPS;
+
+ if (phy_data & F2_STATUS_100T4_CAPS)
+ *ability |= FAL_PHY_100T4_CAPS;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_ability - get the phy ability
+*
+*
+*/
+sw_error_t
+f2_phy_get_partner_ability(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint16_t * ability)
+{
+ a_uint16_t phy_data;
+
+ *ability = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_LINK_PARTNER_ABILITY);
+
+ if (phy_data & F2_LINK_10BASETX_HALF_DUPLEX)
+ *ability |= FAL_PHY_PART_10T_HD;
+
+ if (phy_data & F2_LINK_10BASETX_FULL_DUPLEX)
+ *ability |= FAL_PHY_PART_10T_FD;
+
+ if (phy_data & F2_LINK_100BASETX_HALF_DUPLEX)
+ *ability |= FAL_PHY_PART_100TX_HD;
+
+ if (phy_data & F2_LINK_100BASETX_FULL_DUPLEX)
+ *ability |= FAL_PHY_PART_100TX_FD;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_status - test to see if the specified phy link is alive
+*
+* RETURNS:
+* A_TRUE --> link is alive
+* A_FALSE --> link is down
+*/
+a_bool_t
+f2_phy_get_link_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+
+ if (phy_data & F2_STATUS_LINK_STATUS_UP)
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f2_set_autoneg_adv - set the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f2_phy_set_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t autoneg)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT);
+ phy_data &= ~F2_ADVERTISE_ALL;
+ phy_data &= ~(F2_ADVERTISE_PAUSE | F2_ADVERTISE_ASYM_PAUSE);
+
+ if (autoneg & FAL_PHY_ADV_100TX_FD)
+ phy_data |= F2_ADVERTISE_100FULL;
+
+ if (autoneg & FAL_PHY_ADV_100TX_HD)
+ phy_data |= F2_ADVERTISE_100HALF;
+
+ if (autoneg & FAL_PHY_ADV_10T_FD)
+ phy_data |= F2_ADVERTISE_10FULL;
+
+ if (autoneg & FAL_PHY_ADV_10T_HD)
+ phy_data |= F2_ADVERTISE_10HALF;
+
+ if (autoneg & FAL_PHY_ADV_PAUSE)
+ phy_data |= F2_ADVERTISE_PAUSE;
+
+ if (autoneg & FAL_PHY_ADV_ASY_PAUSE)
+ phy_data |= F2_ADVERTISE_ASYM_PAUSE;
+
+ f2_phy_reg_write(dev_id, phy_id, F2_AUTONEG_ADVERT, phy_data);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_get_autoneg_adv - get the phy autoneg Advertisement
+*
+*/
+sw_error_t
+f2_phy_get_autoneg_adv(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_uint32_t * autoneg)
+{
+ a_uint16_t phy_data = 0;
+
+ *autoneg = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_AUTONEG_ADVERT);
+
+ if (phy_data & F2_ADVERTISE_100FULL)
+ *autoneg |= FAL_PHY_ADV_100TX_FD;
+
+ if (phy_data & F2_ADVERTISE_100HALF)
+ *autoneg |= FAL_PHY_ADV_100TX_HD;
+
+ if (phy_data & F2_ADVERTISE_10FULL)
+ *autoneg |= FAL_PHY_ADV_10T_FD;
+
+ if (phy_data & F2_ADVERTISE_10HALF)
+ *autoneg |= FAL_PHY_ADV_10T_HD;
+
+ if (phy_data & F2_ADVERTISE_PAUSE)
+ *autoneg |= FAL_PHY_ADV_PAUSE;
+
+ if (phy_data & F2_ADVERTISE_ASYM_PAUSE)
+ *autoneg |= FAL_PHY_ADV_ASY_PAUSE;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+a_bool_t
+f2_phy_autoneg_status(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+ if (phy_data & F2_CTRL_AUTONEGOTIATION_ENABLE)
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+/******************************************************************************
+*
+* f2_restart_autoneg - restart the phy autoneg
+*
+*/
+sw_error_t
+f2_phy_restart_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+ phy_data |= F2_CTRL_AUTONEGOTIATION_ENABLE;
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+ phy_data | F2_CTRL_RESTART_AUTONEGOTIATION);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_enable_autonego - power off the phy to change its speed
+*
+* Power off the phy
+*/
+sw_error_t
+f2_phy_enable_autoneg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data = 0;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_CONTROL);
+
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL,
+ phy_data | F2_CTRL_AUTONEGOTIATION_ENABLE);
+
+ return SW_OK;
+}
+
+
+/******************************************************************************
+*
+* f2_phy_get_speed - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+* AG7100_PHY_SPEED_1000T;
+*/
+
+sw_error_t
+f2_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t * speed)
+{
+ a_uint16_t phy_data;
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+
+ //read speed
+ switch (phy_data & F2_STATUS_SPEED_MASK)
+ {
+ case F2_STATUS_SPEED_1000MBS:
+ *speed = FAL_SPEED_1000;
+ break;
+ case F2_STATUS_SPEED_100MBS:
+ *speed = FAL_SPEED_100;
+ break;
+ case F2_STATUS_SPEED_10MBS:
+ *speed = FAL_SPEED_10;
+ break;
+ default:
+ return SW_READ_ERROR;
+ }
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_speed - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+* AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_set_speed(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_speed_t speed)
+{
+ a_uint16_t phy_data = 0;
+ a_uint16_t phy_status = 0;
+ a_uint32_t autoneg, oldneg;
+ fal_port_duplex_t old_duplex;
+
+ phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE;
+
+ (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+ oldneg = autoneg;
+ autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL;
+
+ (void)f2_phy_get_duplex(dev_id, phy_id, &old_duplex);
+
+ if (old_duplex == FAL_FULL_DUPLEX)
+ {
+ phy_data |= F2_CTRL_FULL_DUPLEX;
+
+ if (speed == FAL_SPEED_100)
+ autoneg |= FAL_PHY_ADV_100TX_FD;
+ else
+ autoneg |= FAL_PHY_ADV_10T_FD;
+ }
+ else if (old_duplex == FAL_HALF_DUPLEX)
+ {
+ phy_data &= ~F2_CTRL_FULL_DUPLEX;
+
+ if (speed == FAL_SPEED_100)
+ autoneg |= FAL_PHY_ADV_100TX_HD;
+ else
+ autoneg |= FAL_PHY_ADV_10T_HD;
+ }
+ else
+ return SW_FAIL;
+
+ (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+ (void)f2_phy_restart_autoneg(dev_id, phy_id);
+
+ if(f2_phy_get_link_status(dev_id, phy_id))
+ {
+ do
+ {
+ phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+ }
+ while(!F2_AUTONEG_DONE(phy_status));
+ }
+
+ if (speed == FAL_SPEED_100)
+ phy_data |= F2_CTRL_SPEED_100;
+ else if (speed == FAL_SPEED_10)
+ phy_data |= F2_CTRL_SPEED_10;
+ else
+ return SW_BAD_PARAM;
+
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data);
+ (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+ return SW_OK;
+
+}
+
+/******************************************************************************
+*
+* f2_phy_get_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+* AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_get_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t * duplex)
+{
+ a_uint16_t phy_data;
+
+#if 0
+ //a_uint16_t ii = 200;
+ a_uint16_t ii = 2;
+
+ if (phy_id >= F2_PHY_MAX)
+ return SW_BAD_PARAM;
+
+ do
+ {
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+ aos_mdelay(10);
+ }
+ while ((!(phy_data & F2_STATUS_RESOVLED)) && --ii);
+
+ //read time out
+ if (ii == 0)
+ return SW_DISABLE;
+#endif
+
+ phy_data = f2_phy_reg_read(dev_id, phy_id, F2_PHY_SPEC_STATUS);
+
+ //read duplex
+ if (phy_data & F2_STATUS_FULL_DUPLEX)
+ *duplex = FAL_FULL_DUPLEX;
+ else
+ *duplex = FAL_HALF_DUPLEX;
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_set_duplex - Determines the speed of phy ports associated with the
+* specified device.
+*
+* RETURNS:
+* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
+* AG7100_PHY_SPEED_1000T;
+*/
+sw_error_t
+f2_phy_set_duplex(a_uint32_t dev_id, a_uint32_t phy_id,
+ fal_port_duplex_t duplex)
+{
+ a_uint16_t phy_data = 0;
+ a_uint16_t phy_status = 0;
+
+ fal_port_speed_t old_speed;
+ a_uint32_t autoneg, oldneg;
+
+ if (f2_phy_autoneg_status(dev_id, phy_id))
+ phy_data &= ~F2_CTRL_AUTONEGOTIATION_ENABLE;
+
+ (void)f2_phy_get_autoneg_adv(dev_id, phy_id, &autoneg);
+ oldneg = autoneg;
+ autoneg &= ~FAL_PHY_ADV_FE_SPEED_ALL;
+
+ (void)f2_phy_get_speed(dev_id, phy_id, &old_speed);
+
+ if (old_speed == FAL_SPEED_100)
+ phy_data |= F2_CTRL_SPEED_100;
+ else if (old_speed == FAL_SPEED_10)
+ phy_data |= F2_CTRL_SPEED_10;
+ else
+ return SW_FAIL;
+
+ if (duplex == FAL_FULL_DUPLEX)
+ {
+ phy_data |= F2_CTRL_FULL_DUPLEX;
+
+ if (old_speed == FAL_SPEED_100)
+ autoneg = FAL_PHY_ADV_100TX_FD;
+ else
+ autoneg = FAL_PHY_ADV_10T_FD;
+ }
+ else if (duplex == FAL_HALF_DUPLEX)
+ {
+ phy_data &= ~F2_CTRL_FULL_DUPLEX;
+
+ if (old_speed == FAL_SPEED_100)
+ autoneg = FAL_PHY_ADV_100TX_HD;
+ else
+ autoneg = FAL_PHY_ADV_10T_HD;
+ }
+ else
+ return SW_BAD_PARAM;
+
+ (void)f2_phy_set_autoneg_adv(dev_id, phy_id, autoneg);
+ (void)f2_phy_restart_autoneg(dev_id, phy_id);
+
+ if(f2_phy_get_link_status(dev_id, phy_id))
+ {
+ do
+ {
+ phy_status = f2_phy_reg_read(dev_id, phy_id, F2_PHY_STATUS);
+ }
+ while(!F2_AUTONEG_DONE(phy_status));
+ }
+
+ f2_phy_reg_write(dev_id, phy_id, F2_PHY_CONTROL, phy_data);
+ (void)f2_phy_set_autoneg_adv(dev_id, phy_id, oldneg);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_get_phy_id - get the phy id
+*
+*/
+static sw_error_t
+f2_phy_get_phy_id(a_uint32_t dev_id, int phy_id,
+ a_uint16_t * org_id, a_uint16_t * rev_id)
+{
+ *org_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID1);
+ *rev_id = f2_phy_reg_read(dev_id, phy_id, F2_PHY_ID2);
+
+ return SW_OK;
+}
+
+/******************************************************************************
+*
+* f2_phy_init -
+*
+*/
+a_bool_t
+f2_phy_init(a_uint32_t dev_id, int phy_id,
+ a_uint16_t org_id, a_uint16_t rev_id)
+{
+ a_uint16_t org_tmp, rev_tmp;
+
+ (void)f2_phy_get_phy_id(dev_id, phy_id, &org_tmp, &rev_tmp);
+ if ((org_id == org_tmp) && (rev_id == rev_tmp))
+ return A_TRUE;
+ else
+ return A_FALSE;
+}
diff --git a/src/hsl/shiva/Makefile b/src/hsl/shiva/Makefile
new file mode 100644
index 0000000..20042ef
--- /dev/null
+++ b/src/hsl/shiva/Makefile
@@ -0,0 +1,84 @@
+LOC_DIR=src/hsl/shiva
+LIB=HSL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=shiva_reg_access.c shiva_init.c
+
+ifeq (TRUE, $(IN_ACL))
+ SRC_LIST += shiva_acl.c
+endif
+
+ifeq (TRUE, $(IN_FDB))
+ SRC_LIST += shiva_fdb.c
+endif
+
+ifeq (TRUE, $(IN_IGMP))
+ SRC_LIST += shiva_igmp.c
+endif
+
+ifeq (TRUE, $(IN_LEAKY))
+ SRC_LIST += shiva_leaky.c
+endif
+
+ifeq (TRUE, $(IN_LED))
+ SRC_LIST += shiva_led.c
+endif
+
+ifeq (TRUE, $(IN_MIB))
+ SRC_LIST += shiva_mib.c
+endif
+
+ifeq (TRUE, $(IN_MIRROR))
+ SRC_LIST += shiva_mirror.c
+endif
+
+ifeq (TRUE, $(IN_MISC))
+ SRC_LIST += shiva_misc.c
+endif
+
+ifeq (TRUE, $(IN_PORTCONTROL))
+ SRC_LIST += shiva_port_ctrl.c
+endif
+
+ifeq (TRUE, $(IN_PORTVLAN))
+ SRC_LIST += shiva_portvlan.c
+endif
+
+ifeq (TRUE, $(IN_QOS))
+ SRC_LIST += shiva_qos.c
+endif
+
+ifeq (TRUE, $(IN_RATE))
+ SRC_LIST += shiva_rate.c
+endif
+
+ifeq (TRUE, $(IN_STP))
+ SRC_LIST += shiva_stp.c
+endif
+
+ifeq (TRUE, $(IN_VLAN))
+ SRC_LIST += shiva_vlan.c
+endif
+
+ifeq (TRUE, $(IN_REDUCED_ACL))
+ SRC_LIST += shiva_reduced_acl.c
+endif
+
+ifeq (linux, $(OS))
+ ifeq (KSLIB, $(MODULE_TYPE))
+ ifneq (TRUE, $(KERNEL_MODE))
+ SRC_LIST=shiva_reg_access.c shiva_init.c
+ endif
+ endif
+endif
+
+ifeq (, $(findstring SHIVA, $(SUPPORT_CHIP)))
+ SRC_LIST=
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/hsl/shiva/shiva_acl.c b/src/hsl/shiva/shiva_acl.c
new file mode 100644
index 0000000..e86104f
--- /dev/null
+++ b/src/hsl/shiva/shiva_acl.c
@@ -0,0 +1,3162 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_acl SHIVA_ACL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_acl.h"
+#include "shiva_acl.h"
+#include "shiva_reg.h"
+
+//#define SHIVA_ACL_DEBUG
+//#define SHIVA_SW_ENTRY
+//#define SHIVA_ENTRY_DUMP
+
+typedef struct
+{
+ a_uint32_t list_id;
+ a_uint32_t list_pri;
+ a_uint32_t addr;
+ a_uint32_t size;
+ a_uint32_t status;
+ fal_pbmp_t bind_pts;
+} shiva_acl_list_t;
+
+typedef struct
+{
+ a_uint32_t slct[6];
+ a_uint32_t vlu[5];
+ a_uint32_t msk[5];
+ a_uint32_t typ;
+ a_uint32_t len;
+ a_uint32_t act[3];
+} shiva_acl_hw_rule_t;
+
+static shiva_acl_list_t *list_ent[SW_MAX_NR_DEV];
+static shiva_acl_hw_rule_t *hw_rule_ent;
+
+static a_uint32_t filter[SW_MAX_NR_DEV];
+static a_uint32_t filter_snap[SW_MAX_NR_DEV];
+
+#define SHIVA_MAX_LIST 32
+#define SHIVA_MAX_RULE 32
+
+#define ENT_FREE 0x1
+#define ENT_USED 0x2
+
+#define SHIVA_RULE_VLU_ADDR 0x58400
+#define SHIVA_RULE_MSK_ADDR 0x58c00
+#define SHIVA_RULE_LEN_ADDR 0x58818
+#define SHIVA_RULE_TYP_ADDR 0x5881c
+#define SHIVA_RULE_ACT_ADDR 0x58000
+#define SHIVA_RULE_SLCT_ADDR 0x58800
+
+#define SHIVA_MAC_FILTER 1
+#define SHIVA_IP4_FILTER 2
+#define SHIVA_IP6R1_FILTER 3
+#define SHIVA_IP6R2_FILTER 4
+#define SHIVA_IP6R3_FILTER 5
+#define SHIVA_UDF_FILTER 6
+
+#ifdef SHIVA_SW_ENTRY
+static char *flt_vlu_mem = NULL;
+static char *flt_msk_mem = NULL;
+static char *flt_typ_mem = NULL;
+static char *flt_len_mem = NULL;
+static char *act_mem = NULL;
+static char *slct_mem = NULL;
+#endif
+
+static a_bool_t _shiva_acl_zero_addr(const fal_mac_addr_t addr);
+
+static a_bool_t
+_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu);
+
+static sw_error_t
+_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx);
+
+static sw_error_t
+_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx[], a_uint32_t * flt_nr);
+
+static sw_error_t
+_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care);
+
+static sw_error_t
+_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw);
+
+static sw_error_t
+_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx);
+
+static void
+_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx);
+
+static void
+_shiva_acl_filter_snap(a_uint32_t dev_id);
+
+static void
+_shiva_acl_filter_commit(a_uint32_t dev_id);
+
+static sw_error_t
+_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t act_idx);
+
+static sw_error_t
+_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx);
+
+static sw_error_t
+_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx);
+
+static sw_error_t
+_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t act_idx);
+
+static sw_error_t
+_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx);
+
+static sw_error_t
+_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+ const shiva_acl_hw_rule_t * hw_rule_ent,
+ a_uint32_t rule_nr);
+
+static sw_error_t
+_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t * ent_idx, a_uint32_t rule_idx);
+
+static sw_error_t
+_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_uint32_t * idx);
+
+static sw_error_t
+_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw,
+ a_uint32_t ent_idx, a_uint32_t ent_nr);
+
+static sw_error_t
+_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+ a_uint32_t dst_slct_idx, a_uint32_t size);
+
+static sw_error_t
+_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+ a_uint32_t size);
+
+static sw_error_t
+_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+ a_uint32_t flag);
+
+static sw_error_t
+_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t list_id);
+
+static sw_error_t
+_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports);
+
+#ifdef SHIVA_ACL_DEBUG
+static void
+_shiva_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+
+ aos_printk("\ndev_id=%d list control infomation", dev_id);
+ for (i = 0; i < SHIVA_MAX_LIST; i++)
+ {
+ if (ENT_USED == list_ent[dev_id][i].status)
+ {
+ aos_printk("\nlist_id=%d list_pri=%d addr=%d size=%d idx=%d ",
+ list_ent[dev_id][i].list_id,
+ list_ent[dev_id][i].list_pri,
+ list_ent[dev_id][i].addr, list_ent[dev_id][i].size, i);
+ }
+ }
+ aos_printk("\n");
+}
+#else
+#define _shiva_acl_list_dump(dev_id)
+#endif
+
+static a_bool_t
+_shiva_acl_zero_addr(const fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+ return A_TRUE;
+}
+
+static a_bool_t
+_shiva_acl_field_care(fal_acl_field_op_t op, a_uint32_t val, a_uint32_t mask,
+ a_uint32_t chkvlu)
+{
+ if (FAL_ACL_FIELD_MASK == op)
+ {
+ if (0 == mask)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_RANGE == op)
+ {
+ if ((0 == val) && (chkvlu == mask))
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_LE == op)
+ {
+ if (chkvlu == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_GE == op)
+ {
+ if (0 == val)
+ return A_FALSE;
+ }
+ else if (FAL_ACL_FIELD_NE == op)
+ {
+ return A_TRUE;
+ }
+
+ return A_TRUE;
+}
+
+static sw_error_t
+_shiva_acl_list_loc(a_uint32_t dev_id, a_uint32_t list_id, a_uint32_t * idx)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < SHIVA_MAX_LIST; i++)
+ {
+ if ((ENT_USED == list_ent[dev_id][i].status)
+ && (list_id == list_ent[dev_id][i].list_id))
+ {
+ *idx = i;
+ return SW_OK;
+ }
+ }
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_acl_filter_map_get(const shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx[], a_uint32_t * flt_nr)
+{
+ a_uint32_t flt_en, idx, i = 0;
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR0_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT1, ADDR0, idx, (rule->slct[1]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR1_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT2, ADDR1, idx, (rule->slct[2]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR2_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT3, ADDR2, idx, (rule->slct[3]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ SW_GET_FIELD_BY_REG(RUL_SLCT0, ADDR3_EN, flt_en, (rule->slct[0]));
+ if (flt_en)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT4, ADDR3, idx, (rule->slct[4]));
+ flt_idx[i] = idx;
+ i++;
+ }
+
+ *flt_nr = i;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_mac_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i, len = 14;
+
+ *b_care = A_FALSE;
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_MAC_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ if (A_TRUE != _shiva_acl_zero_addr(sw->dest_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->dest_mac_val.uc[i] &= sw->dest_mac_mask.uc[i];
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+ hw->vlu[1]);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+ hw->msk[0]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+ hw->msk[1]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ if (A_TRUE != _shiva_acl_zero_addr(sw->src_mac_mask))
+ {
+ *b_care = A_TRUE;
+ }
+
+ for (i = 0; i < 6; i++)
+ {
+ sw->src_mac_val.uc[i] &= sw->src_mac_mask.uc[i];
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+ hw->vlu[2]);
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+ hw->msk[1]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ if (0x0 != sw->ethtype_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ethtype_val &= sw->ethtype_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ if (0x0 != sw->tagged_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->tagged_val &= sw->tagged_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ if (0x0 != sw->up_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->up_val &= sw->up_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->vid_op)
+ && (FAL_ACL_FIELD_RANGE != sw->vid_op)
+ && (FAL_ACL_FIELD_LE != sw->vid_op)
+ && (FAL_ACL_FIELD_GE != sw->vid_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->vid_op, sw->vid_val, sw->vid_mask,
+ 0xfff))
+ {
+ *b_care = A_TRUE;
+ }
+
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 0, hw->vlu[4]);
+ if (FAL_ACL_FIELD_MASK == sw->vid_op)
+ {
+ sw->vid_val &= sw->vid_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_V4, VIDMSK, 1, hw->vlu[4]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->vid_op)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->vid_op)
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, 0, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, sw->vid_val, hw->msk[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANIDM, 0xfff, hw->msk[3]);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ if (0x0 != sw->cfi_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->cfi_val &= sw->cfi_mask;
+ SW_SET_REG_BY_FIELD(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]);
+ }
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip4_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t len = 34;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP4_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask,
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_SIP))
+ {
+ if (0x0 != sw->src_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->src_ip4_val &= sw->src_ip4_mask;
+ hw->vlu[1] = sw->src_ip4_val;
+ hw->msk[1] = sw->src_ip4_mask;
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP4_DIP))
+ {
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ *b_care = A_TRUE;
+ }
+ sw->dest_ip4_val &= sw->dest_ip4_mask;
+ hw->vlu[0] = sw->dest_ip4_val;
+ hw->msk[0] = sw->dest_ip4_mask;
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+ len = 38;
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, 0, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_val,
+ hw->msk[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4SPORTM, 0xffff, hw->msk[3]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+ len = 38;
+
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M3, IP4DPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, 0, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_val,
+ hw->msk[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP4_RUL_M2, IP4DPORTM, 0xffff, hw->msk[2]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i, len = 54;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R1_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_DIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->dest_ip6_val.ul[3 - i] &= sw->dest_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->dest_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->dest_ip6_mask.ul[3 - i];
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i, len = 54;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R2_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_SIP))
+ {
+ for (i = 0; i < 4; i++)
+ {
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->src_ip6_val.ul[3 - i] &= sw->src_ip6_mask.ul[3 - i];
+ hw->vlu[i] = sw->src_ip6_val.ul[3 - i];
+ hw->msk[i] = sw->src_ip6_mask.ul[3 - i];
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t len = 54;
+
+ *b_care = A_FALSE;
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_IP6R3_FILTER, hw->typ);
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+ {
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip6_lable_val &= sw->ip6_lable_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val,
+ hw->vlu[1]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+ hw->msk[1]);
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6LABEL2V, (sw->ip6_lable_val >> 16),
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6LABEL2M, (sw->ip6_lable_mask >> 16),
+ hw->msk[2]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ if (0x0 != sw->ip_proto_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_proto_val &= sw->ip_proto_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val,
+ hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask,
+ hw->msk[0]);
+ }
+
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ *b_care = A_TRUE;
+ }
+
+ sw->ip_dscp_val &= sw->ip_dscp_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask,
+ hw->msk[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->src_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->src_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _shiva_acl_field_care(sw->src_l4port_op, sw->src_l4port_val,
+ sw->src_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->src_l4port_val = 0;
+ sw->src_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+ len = 58;
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->src_l4port_op)
+ {
+ sw->src_l4port_val &= sw->src_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->src_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, 0, hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_val,
+ hw->msk[3]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val,
+ hw->vlu[3]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6SPORTM, 0xffff, hw->msk[3]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+ if (FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ if ((FAL_ACL_FIELD_MASK != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_RANGE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_LE != sw->dest_l4port_op)
+ && (FAL_ACL_FIELD_GE != sw->dest_l4port_op))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_FALSE ==
+ _shiva_acl_field_care(sw->dest_l4port_op, sw->dest_l4port_val,
+ sw->dest_l4port_mask, 0xffff))
+ {
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ sw->dest_l4port_val = 0;
+ sw->dest_l4port_mask = 0xffff;
+ }
+ }
+ *b_care = A_TRUE;
+ len = 58;
+
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 0, hw->msk[3]);
+ if (FAL_ACL_FIELD_MASK == sw->dest_l4port_op)
+ {
+ sw->dest_l4port_val &= sw->dest_l4port_mask;
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M3, IP6DPORTM_EN, 1, hw->msk[3]);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ }
+ else if (FAL_ACL_FIELD_LE == sw->dest_l4port_op)
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, 0, hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_val,
+ hw->msk[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_SET_REG_BY_FIELD(IP6_RUL3_M2, IP6DPORTM, 0xffff, hw->msk[2]);
+ }
+ }
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ return SW_OK;
+}
+
+#define SHIVA_MAX_UDF_OFFSET 127
+#define SHIVA_MAX_UDF_LENGTH 16
+
+static sw_error_t
+_shiva_acl_rule_udf_parse(fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_bool_t * b_care)
+{
+ a_uint32_t i, len = 0;
+
+ if (FAL_ACL_UDF_TYPE_BUTT <= sw->udf_type)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (SHIVA_MAX_UDF_OFFSET < sw->udf_offset)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (sw->udf_offset % 2)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (SHIVA_MAX_UDF_LENGTH < sw->udf_len)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(&(hw->vlu[0]), sizeof (hw->vlu));
+ aos_mem_zero(&(hw->msk[0]), sizeof (hw->msk));
+ aos_mem_zero(&(hw->typ), sizeof (hw->typ));
+ aos_mem_zero(&(hw->len), sizeof (hw->len));
+
+ *b_care = A_FALSE;
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT7, RULE_TYP, SHIVA_UDF_FILTER, hw->typ);
+
+ if (!FAL_FIELD_FLG_TST(sw->field_flg, FAL_ACL_FIELD_UDF))
+ {
+ return SW_OK;
+ }
+
+ *b_care = A_TRUE;
+ if (FAL_ACL_UDF_TYPE_L2 == sw->udf_type)
+ {
+ SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 0, hw->vlu[4]);
+ len = sw->udf_offset + sw->udf_len;
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_TYP, 1, hw->vlu[4]);
+ len = 14 + sw->udf_offset + sw->udf_len;
+ }
+ SW_SET_REG_BY_FIELD(RUL_SLCT6, RULE_LEN, len, hw->len);
+
+ SW_SET_REG_BY_FIELD(UDF_RUL_V4, LAYER_OFFSET, sw->udf_offset, hw->vlu[4]);
+
+ for (i = 0; i < sw->udf_len; i++)
+ {
+ hw->vlu[3 - i / 4] |= ((sw->udf_mask[i] & sw->udf_val[i]) << (24 - 8 * (i % 4)));
+ hw->msk[3 - i / 4] |= ((sw->udf_mask[i]) << (24 - 8 * i));
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_parse(a_uint32_t dev_id, const fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw)
+{
+ aos_mem_zero(&(hw->act[0]), sizeof (hw->act));
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ && (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ /* FAL_ACL_ACTION_PERMIT need't process */
+
+ /* we should ignore any other action flags when DENY bit is settd. */
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_DENY))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, 0, hw->act[1]);
+ return SW_OK;
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_RDTCPU))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT2, RDTCPU, 1, hw->act[2]);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_CPYCPU))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT2, CPYCPU, 1, hw->act[2]);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MIRROR))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, MIRR_EN, 1, hw->act[1]);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, DES_PORT_EN, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_UP))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_DOT1P, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, DOT1P, sw->up, hw->act[1]);
+ }
+
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, REMARK_PRI_QU, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, PRI_QU, sw->queue, hw->act[1]);
+ }
+
+ if ((FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ || (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN)))
+ {
+
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, CHG_VID_EN, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, VID, sw->vid, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 1, hw->act[1]);
+ if (FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, STAG_CHG_EN, 0, hw->act[1]);
+
+ if (!FAL_ACTION_FLG_TST(sw->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, VID_MEM_EN, 1, hw->act[1]);
+ SW_SET_REG_BY_FIELD(ACL_RSLT1, PORT_MEM, sw->ports, hw->act[1]);
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_mac_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+
+ /* destnation mac address */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE2, sw->dest_mac_val.uc[2],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE3, sw->dest_mac_val.uc[3],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE4, sw->dest_mac_val.uc[4],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V0, DAV_BYTE5, sw->dest_mac_val.uc[5],
+ hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE0, sw->dest_mac_val.uc[0],
+ hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, DAV_BYTE1, sw->dest_mac_val.uc[1],
+ hw->vlu[1]);
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE2, sw->dest_mac_mask.uc[2],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE3, sw->dest_mac_mask.uc[3],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE4, sw->dest_mac_mask.uc[4],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M0, DAM_BYTE5, sw->dest_mac_mask.uc[5],
+ hw->msk[0]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE0, sw->dest_mac_mask.uc[0],
+ hw->msk[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, DAM_BYTE1, sw->dest_mac_mask.uc[1],
+ hw->msk[1]);
+ if (A_FALSE == _shiva_acl_zero_addr(sw->dest_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ /* source mac address */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE0, sw->src_mac_val.uc[0],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE1, sw->src_mac_val.uc[1],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE2, sw->src_mac_val.uc[2],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V2, SAV_BYTE3, sw->src_mac_val.uc[3],
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE4, sw->src_mac_val.uc[4],
+ hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V1, SAV_BYTE5, sw->src_mac_val.uc[5],
+ hw->vlu[1]);
+
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE0, sw->src_mac_mask.uc[0],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE1, sw->src_mac_mask.uc[1],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE2, sw->src_mac_mask.uc[2],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M2, SAM_BYTE3, sw->src_mac_mask.uc[3],
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE4, sw->src_mac_mask.uc[4],
+ hw->msk[1]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M1, SAM_BYTE5, sw->src_mac_mask.uc[5],
+ hw->msk[1]);
+ if (A_FALSE == _shiva_acl_zero_addr(sw->src_mac_mask))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ /* ethernet type */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, ETHTYPV, sw->ethtype_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, ETHTYPM, sw->ethtype_mask, hw->msk[3]);
+ if (0x0 != sw->ethtype_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* packet tagged */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDV, sw->tagged_val, hw->vlu[4]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V4, TAGGEDM, sw->tagged_mask, hw->vlu[4]);
+ if (0x0 != sw->tagged_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+ }
+
+ /* vlan priority */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANPRIV, sw->up_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANPRIM, sw->up_mask, hw->msk[3]);
+ if (0x0 != sw->up_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_UP);
+ }
+
+ /* vlanid */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANIDV, sw->vid_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANIDM, sw->vid_mask, hw->msk[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_V4, VIDMSK, mask_en, hw->vlu[4]);
+ if (mask_en)
+ {
+ sw->vid_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->vid_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->vid_op, (a_uint32_t) sw->vid_val,
+ (a_uint32_t) sw->vid_mask, 0xfff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_VID);
+ }
+
+ /* vlan cfi */
+ SW_GET_FIELD_BY_REG(MAC_RUL_V3, VLANCFIV, sw->cfi_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(MAC_RUL_M3, VLANCFIM, sw->cfi_mask, hw->msk[3]);
+ if (0x0 != sw->cfi_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_MAC_CFI);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip4_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+
+ sw->dest_ip4_val = hw->vlu[0];
+ sw->dest_ip4_mask = hw->msk[0];
+ if (0x0 != sw->dest_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+
+ sw->src_ip4_val = hw->vlu[1];
+ sw->src_ip4_mask = hw->msk[1];
+ if (0x0 != sw->src_ip4_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4PROTV, sw->ip_proto_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4PROTM, sw->ip_proto_mask, hw->msk[2]);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DSCPV, sw->ip_dscp_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DSCPM, sw->ip_dscp_mask, hw->msk[2]);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V2, IP4DPORTV, sw->dest_l4port_val, hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M2, IP4DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4DPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP4_RUL_V3, IP4SPORTV, sw->src_l4port_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM, sw->src_l4port_mask, hw->msk[3]);
+ SW_GET_FIELD_BY_REG(IP4_RUL_M3, IP4SPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r1_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->dest_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->dest_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->dest_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r2_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 4; i++)
+ {
+ sw->src_ip6_val.ul[i] = hw->vlu[3 - i];
+ sw->src_ip6_mask.ul[i] = hw->msk[3 - i];
+ if (0x0 != sw->src_ip6_mask.ul[i])
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_ip6r3_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t mask_en;
+ a_uint32_t tmp;
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6PROTV, sw->ip_proto_val, hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6PROTM, sw->ip_proto_mask, hw->msk[0]);
+ if (0x0 != sw->ip_proto_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V0, IP6DSCPV, sw->ip_dscp_val, hw->vlu[0]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M0, IP6DSCPM, sw->ip_dscp_mask, hw->msk[0]);
+ if (0x0 != sw->ip_dscp_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6DPORTV, sw->dest_l4port_val,
+ hw->vlu[2]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6DPORTM, sw->dest_l4port_mask,
+ hw->msk[2]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6DPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->dest_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->dest_l4port_op,
+ (a_uint32_t) sw->dest_l4port_val,
+ (a_uint32_t) sw->dest_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->dest_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V3, IP6SPORTV, sw->src_l4port_val, hw->vlu[3]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM, sw->src_l4port_mask,
+ hw->msk[3]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M3, IP6SPORTM_EN, mask_en, hw->msk[3]);
+ if (mask_en)
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_MASK;
+ }
+ else
+ {
+ sw->src_l4port_op = FAL_ACL_FIELD_RANGE;
+ }
+
+ if (A_TRUE ==
+ _shiva_acl_field_care(sw->src_l4port_op,
+ (a_uint32_t) sw->src_l4port_val,
+ (a_uint32_t) sw->src_l4port_mask, 0xffff))
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+ else if (FAL_ACL_FIELD_RANGE == sw->src_l4port_op)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V1, IP6LABEL1V, sw->ip6_lable_val, hw->vlu[1]);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M1, IP6LABEL1M, sw->ip6_lable_mask,
+ hw->msk[1]);
+
+ SW_GET_FIELD_BY_REG(IP6_RUL3_V2, IP6LABEL2V, tmp, hw->vlu[2]);
+ sw->ip6_lable_val |= (tmp << 16);
+ SW_GET_FIELD_BY_REG(IP6_RUL3_M2, IP6LABEL2M, tmp, hw->msk[2]);
+ sw->ip6_lable_mask |= (tmp << 16);
+
+ if (0x0 != sw->ip6_lable_mask)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_udf_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t i, tmp;
+
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+
+ SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_OFFSET, tmp, hw->vlu[4]);
+ sw->udf_offset = tmp;
+
+ SW_GET_FIELD_BY_REG(UDF_RUL_V4, LAYER_TYP, tmp, hw->vlu[4]);
+ if (tmp)
+ {
+ sw->udf_type = FAL_ACL_UDF_TYPE_L3;
+ sw->udf_len = hw->len - sw->udf_offset - 14;
+ }
+ else
+ {
+ sw->udf_type = FAL_ACL_UDF_TYPE_L2;
+ sw->udf_len = hw->len - sw->udf_offset;
+ }
+
+ if (SHIVA_MAX_UDF_LENGTH < sw->udf_len)
+ {
+ return SW_READ_ERROR;
+ }
+
+ for (i = 0; i < sw->udf_len; i++)
+ {
+ sw->udf_val[i] = ((hw->vlu[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ sw->udf_mask[i] = ((hw->msk[3 - i / 4]) >> (24 - 8 * (i % 4))) & 0xff;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_action_reparse(fal_acl_rule_t * sw,
+ const shiva_acl_hw_rule_t * hw)
+{
+ a_uint32_t data;
+
+ sw->match_cnt = hw->act[0];
+
+ sw->action_flg = 0;
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, DES_PORT_EN, data, (hw->act[1]));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1]));
+ sw->ports = data;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REDPT);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT2, RDTCPU, data, (hw->act[2]));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_RDTCPU);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT2, CPYCPU, data, (hw->act[2]));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_CPYCPU);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, MIRR_EN, data, (hw->act[1]));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MIRROR);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_DOT1P, data, (hw->act[1]));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, DOT1P, data, (hw->act[1]));
+ sw->up = data & 0x7;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_UP);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, REMARK_PRI_QU, data, (hw->act[1]));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, PRI_QU, data, (hw->act[1]));
+ sw->queue = data & 0x3;
+
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, CHG_VID_EN, data, (hw->act[1]));
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, STAG_CHG_EN, data, (hw->act[1]));
+ if (1 == data)
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_NEST_VLAN);
+ }
+ else
+ {
+ FAL_ACTION_FLG_SET(sw->action_flg, FAL_ACL_ACTION_MODIFY_VLAN);
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, PORT_MEM, data, (hw->act[1]));
+ sw->ports = data;
+ }
+ }
+
+ SW_GET_FIELD_BY_REG(ACL_RSLT1, VID, data, (hw->act[1]));
+ sw->vid = data & 0xfff;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_alloc(a_uint32_t dev_id, a_uint32_t * idx)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < SHIVA_MAX_RULE; i++)
+ {
+ if (0 == (filter_snap[dev_id] & (0x1UL << i)))
+ {
+ filter_snap[dev_id] |= (0x1UL << i);
+ *idx = i;
+ return SW_OK;
+ }
+ }
+ return SW_NO_RESOURCE;
+}
+
+static void
+_shiva_acl_filter_free(a_uint32_t dev_id, a_uint32_t idx)
+{
+ filter_snap[dev_id] &= (~(0x1UL << idx));
+}
+
+static void
+_shiva_acl_filter_snap(a_uint32_t dev_id)
+{
+ filter_snap[dev_id] = filter[dev_id];
+ return;
+}
+
+static void
+_shiva_acl_filter_commit(a_uint32_t dev_id)
+{
+ filter[dev_id] = filter_snap[dev_id];
+ return;
+}
+
+static sw_error_t
+_shiva_acl_slct_update(shiva_acl_hw_rule_t * hw, a_uint32_t offset,
+ a_uint32_t flt_idx)
+{
+ switch (offset)
+ {
+ case 0:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR0_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT1, ADDR0, flt_idx, hw->slct[1]);
+ break;
+
+ case 1:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR1_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT2, ADDR1, flt_idx, hw->slct[2]);
+ break;
+
+ case 2:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR2_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT3, ADDR2, flt_idx, hw->slct[3]);
+ break;
+
+ case 3:
+ SW_SET_REG_BY_FIELD(RUL_SLCT0, ADDR3_EN, 1, hw->slct[0]);
+ SW_SET_REG_BY_FIELD(RUL_SLCT4, ADDR3, flt_idx, hw->slct[4]);
+ break;
+
+ default:
+ return SW_FAIL;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = flt_vlu_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->vlu[0]), sizeof(rule->vlu));
+
+ memaddr = flt_msk_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->msk[0]), sizeof(rule->vlu));
+
+ memaddr = flt_typ_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->typ), sizeof(rule->typ));
+
+ memaddr = flt_len_mem + (flt_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->len), sizeof(rule->len));
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* set filter value */
+ base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter mask */
+ base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter type */
+ addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set filter length */
+ addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_filter_write flt_idx = %d type = %d len = %d\n",
+ flt_idx, rule->typ, rule->len);
+ for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->vlu[j]);
+ }
+ aos_printk("\n");
+ for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->msk[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t act_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = act_mem + (act_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->act[0]), sizeof(rule->act));
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* set rule action */
+ base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+ for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_action_write act_idx = %d\n", act_idx);
+ for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->act[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_slct_write(a_uint32_t dev_id, const shiva_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = slct_mem + (slct_idx << 5);
+ aos_mem_copy(memaddr, (char *) &(rule->slct[0]), sizeof(rule->slct));
+
+#else
+ sw_error_t rv;
+ a_uint32_t base, addr;
+ a_uint32_t i;
+
+ base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* set filter address and source ports bitmap*/
+ for (i = 1; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set filter enable */
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_slct_write slct_idx = %d\n", slct_idx);
+ for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->slct[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_filter_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t flt_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = flt_vlu_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->vlu[0]), memaddr, 20);
+
+ memaddr = flt_msk_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->msk[0]), memaddr, 20);
+
+ memaddr = flt_typ_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->typ), memaddr, 4);
+
+ memaddr = flt_len_mem + (flt_idx << 5);
+ aos_mem_copy((char *) &(rule->len), memaddr, 4);
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* get filter value */
+ base = SHIVA_RULE_VLU_ADDR + (flt_idx << 5);
+ for (i = 0; i < (sizeof(rule->vlu) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get filter mask */
+ base = SHIVA_RULE_MSK_ADDR + (flt_idx << 5);
+ for (i = 0; i < (sizeof(rule->msk) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get filter type */
+ addr = SHIVA_RULE_TYP_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->typ)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* get filter length */
+ addr = SHIVA_RULE_LEN_ADDR + (flt_idx << 5);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->len)), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_filter_read flt_idx = %d type = %d len = %d \n",
+ flt_idx, rule->typ, rule->len);
+ for (j = 0; j < (sizeof(rule->vlu) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->vlu[j]);
+ }
+ aos_printk("\n");
+ for (j = 0; j < (sizeof(rule->msk) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->msk[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_action_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t act_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = act_mem + (act_idx << 5);
+ aos_mem_copy((char *) &(rule->act[0]), memaddr, sizeof(rule->act));
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* get rule action */
+ base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+ for (i = 0; i < (sizeof(rule->act) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->act[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_action_read act_idx = %d ", act_idx);
+ for (j = 0; j < (sizeof(rule->act) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->act[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_slct_read(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t slct_idx)
+{
+#ifdef SHIVA_SW_ENTRY
+ char *memaddr;
+
+ memaddr = slct_mem + (slct_idx << 5);
+ aos_mem_copy((char *) &(rule->slct[0]), memaddr, sizeof(rule->slct));
+
+#else
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* get filter address and enable and source ports bitmap */
+ for (i = 0; i < (sizeof(rule->slct) / sizeof(a_uint32_t)); i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(rule->slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+#endif
+
+#ifdef SHIVA_ENTRY_DUMP
+ a_uint32_t j;
+ aos_printk("\n_shiva_acl_slct_read slct_idx = %d\n", slct_idx);
+ for (j = 0; j < (sizeof(rule->slct) / sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule->slct[j]);
+ }
+#endif
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_set(a_uint32_t dev_id, a_uint32_t base_addr,
+ const shiva_acl_hw_rule_t * rule, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ a_uint32_t ent_idx, tmp_ent_idx;
+ a_uint32_t i, flt_nr, flt_idx[4];
+ a_uint32_t act_idx, slct_idx;
+
+ act_idx = base_addr;
+ slct_idx = base_addr;
+ ent_idx = 0;
+ for (i = 0; i < rule_nr; i++)
+ {
+ tmp_ent_idx = ent_idx;
+
+ rv = _shiva_acl_filter_map_get(&rule[ent_idx], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!flt_nr)
+ {
+ return SW_FAIL;
+ }
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _shiva_acl_filter_write(dev_id, &(rule[ent_idx]), flt_idx[i]);
+ ent_idx++;
+ }
+
+ rv = _shiva_acl_action_write(dev_id, &(rule[tmp_ent_idx]), act_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_slct_write(dev_id, &(rule[tmp_ent_idx]), slct_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ act_idx++;
+ slct_idx++;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_get(a_uint32_t dev_id, shiva_acl_hw_rule_t * rule,
+ a_uint32_t * ent_idx, a_uint32_t rule_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, tmp_idx, flt_nr, flt_idx[4];
+
+ tmp_idx = *ent_idx;
+
+ rv = _shiva_acl_slct_read(dev_id, &rule[tmp_idx], rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_action_read(dev_id, &rule[tmp_idx], rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_filter_map_get(&rule[tmp_idx], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _shiva_acl_filter_read(dev_id, &rule[tmp_idx], flt_idx[i]);
+ SW_RTN_ON_ERROR(rv);
+
+ tmp_idx++;
+ }
+
+ *ent_idx = tmp_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_sw_to_hw(a_uint32_t dev_id, fal_acl_rule_t * sw,
+ shiva_acl_hw_rule_t * hw, a_uint32_t * idx)
+{
+ sw_error_t rv;
+ a_bool_t b_care;
+ a_bool_t b_valid = A_FALSE;
+ a_uint32_t tmp_idx;
+
+ tmp_idx = *idx;
+ if (FAL_ACL_RULE_MAC == sw->rule_type)
+ {
+ rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ tmp_idx++;
+ }
+ else if (FAL_ACL_RULE_IP4 == sw->rule_type)
+ {
+ rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _shiva_acl_rule_ip4_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ tmp_idx++;
+ }
+ else if (FAL_ACL_RULE_IP6 == sw->rule_type)
+ {
+ rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _shiva_acl_rule_mac_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ }
+
+ rv = _shiva_acl_rule_ip6r1_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_valid = A_TRUE;
+ }
+
+ rv = _shiva_acl_rule_ip6r2_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if (A_TRUE == b_care)
+ {
+ tmp_idx++;
+ b_valid = A_TRUE;
+ }
+
+ rv = _shiva_acl_rule_ip6r3_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ if ((A_TRUE == b_care) || (A_FALSE == b_valid))
+ {
+ tmp_idx++;
+ }
+ else
+ {
+ hw[tmp_idx - 1].len = hw[tmp_idx].len;
+ }
+ }
+ else if (FAL_ACL_RULE_UDF == sw->rule_type)
+ {
+ FAL_FIELD_FLG_SET(sw->field_flg, FAL_ACL_FIELD_UDF);
+ rv = _shiva_acl_rule_udf_parse(sw, &hw[tmp_idx], &b_care);
+ SW_RTN_ON_ERROR(rv);
+ tmp_idx++;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _shiva_acl_action_parse(dev_id, sw, &(hw_rule_ent[*idx]));
+ SW_RTN_ON_ERROR(rv);
+
+ *idx = tmp_idx;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_hw_to_sw(fal_acl_rule_t * sw, const shiva_acl_hw_rule_t * hw,
+ a_uint32_t ent_idx, a_uint32_t ent_nr)
+{
+ sw_error_t rv;
+ a_uint32_t i, flt_typ;
+ a_bool_t b_mac = A_FALSE, b_ip4 = A_FALSE, b_ip6 = A_FALSE;
+
+ rv = _shiva_acl_rule_action_reparse(sw, &hw[ent_idx]);
+ SW_RTN_ON_ERROR(rv);
+
+ sw->rule_type = FAL_ACL_RULE_UDF;
+ for (i = 0; i < ent_nr; i++)
+ {
+ SW_GET_FIELD_BY_REG(RUL_SLCT7, RULE_TYP, flt_typ, hw[ent_idx + i].typ);
+
+ if (SHIVA_UDF_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_udf_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ }
+ else if (SHIVA_MAC_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_mac_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_mac = A_TRUE;
+ }
+ else if (SHIVA_IP4_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_ip4_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip4 = A_TRUE;
+ }
+ else if (SHIVA_IP6R1_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_ip6r1_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (SHIVA_IP6R2_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_ip6r2_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else if (SHIVA_IP6R3_FILTER == flt_typ)
+ {
+ rv = _shiva_acl_rule_ip6r3_reparse(sw, &hw[ent_idx + i]);
+ SW_RTN_ON_ERROR(rv);
+ b_ip6 = A_TRUE;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ if (A_TRUE == b_mac)
+ {
+ sw->rule_type = FAL_ACL_RULE_MAC;
+ }
+
+ if (A_TRUE == b_ip4)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP4;
+ }
+
+ if (A_TRUE == b_ip6)
+ {
+ sw->rule_type = FAL_ACL_RULE_IP6;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_copy(a_uint32_t dev_id, a_uint32_t src_slct_idx,
+ a_uint32_t dst_slct_idx, a_uint32_t size)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+ a_int32_t step, src_idx, dst_idx;
+ shiva_acl_hw_rule_t rule;
+
+ if (dst_slct_idx <= src_slct_idx)
+ {
+ src_idx = src_slct_idx & 0x7fffffff;
+ dst_idx = dst_slct_idx & 0x7fffffff;
+ step = 1;
+ }
+ else
+ {
+ src_idx = (src_slct_idx + size - 1) & 0x7fffffff;
+ dst_idx = (dst_slct_idx + size - 1) & 0x7fffffff;
+ step = -1;
+ }
+
+ aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+ for (i = 0; i < size; i++)
+ {
+ rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) dst_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_action_read(dev_id, &rule, (a_uint32_t) src_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_action_write(dev_id, &rule, (a_uint32_t) dst_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_slct_read(dev_id, &rule, (a_uint32_t) src_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_slct_write(dev_id, &rule, (a_uint32_t) dst_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_rule_invalid(dev_id, (a_uint32_t) src_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ src_idx += step;
+ dst_idx += step;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_invalid(a_uint32_t dev_id, a_uint32_t rule_idx,
+ a_uint32_t size)
+{
+ sw_error_t rv;
+ a_uint32_t base, flag, i;
+
+ flag = 0;
+ for (i = 0; i < size; i++)
+ {
+ base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_valid(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t size,
+ a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t base, i;
+
+ for (i = 0; i < size; i++)
+ {
+ base = SHIVA_RULE_SLCT_ADDR + ((rule_idx + i) << 5);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&flag), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_addr_update(a_uint32_t dev_id, a_uint32_t old_addr,
+ a_uint32_t new_addr, a_uint32_t list_id)
+{
+ sw_error_t rv;
+ a_uint32_t idx;
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (old_addr != list_ent[dev_id][idx].addr)
+ {
+ return SW_FAIL;
+ }
+
+ list_ent[dev_id][idx].addr = new_addr;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_bind(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t ports)
+{
+ sw_error_t rv;
+ shiva_acl_hw_rule_t rule;
+
+ aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+
+ rv = _shiva_acl_slct_read(dev_id, &rule, rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_rule_invalid(dev_id, rule_idx, 1);
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, ports, rule.slct[5]);
+
+ rv = _shiva_acl_slct_write(dev_id, &rule, rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_rule_valid(dev_id, rule_idx, 1, rule.slct[0]);
+ return rv;
+}
+
+static sw_error_t
+_shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri)
+{
+ a_uint32_t i, loc = SHIVA_MAX_LIST;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ for (i = 0; i < SHIVA_MAX_LIST; i++)
+ {
+ if ((ENT_USED == list_ent[dev_id][i].status)
+ && (list_id == list_ent[dev_id][i].list_id))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ if (ENT_FREE == list_ent[dev_id][i].status)
+ {
+ loc = i;
+ }
+ }
+
+ if (SHIVA_MAX_LIST == loc)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ aos_mem_zero(&(list_ent[dev_id][loc]), sizeof (shiva_acl_list_t));
+ list_ent[dev_id][loc].list_id = list_id;
+ list_ent[dev_id][loc].list_pri = list_pri;
+ list_ent[dev_id][loc].status = ENT_USED;
+ _shiva_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ a_uint32_t list_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ for (list_idx = 0; list_idx < SHIVA_MAX_LIST; list_idx++)
+ {
+ if ((ENT_USED == list_ent[dev_id][list_idx].status)
+ && (list_id == list_ent[dev_id][list_idx].list_id))
+ {
+ break;
+ }
+ }
+
+ if (list_idx >= SHIVA_MAX_LIST)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ if (0 != list_ent[dev_id][list_idx].bind_pts)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (0 != list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ aos_mem_zero(&(list_ent[dev_id][list_idx]), sizeof (shiva_acl_list_t));
+ list_ent[dev_id][list_idx].status = ENT_FREE;
+ _shiva_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ a_uint32_t hsl_f_rsc, list_new_size, list_addr;
+ a_uint32_t list_pri, list_idx, load_addr, bind_pts;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((0 == rule_nr) || (NULL == rule))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_acl_free_rsc_get(dev_id, &hsl_f_rsc);
+ SW_RTN_ON_ERROR(rv);
+ if (hsl_f_rsc < rule_nr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (rule_id != list_ent[dev_id][list_idx].size)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ bind_pts = list_ent[dev_id][list_idx].bind_pts;
+
+ _shiva_acl_filter_snap(dev_id);
+
+ /* parse rule entry and alloc rule resource */
+ {
+ a_uint32_t i, j;
+ a_uint32_t ent_idx, tmp_ent_idx, flt_idx;
+
+ aos_mem_zero(hw_rule_ent,
+ SHIVA_MAX_RULE * sizeof (shiva_acl_hw_rule_t));
+
+ ent_idx = 0;
+ for (i = 0; i < rule_nr; i++)
+ {
+ tmp_ent_idx = ent_idx;
+ rv = _shiva_acl_rule_sw_to_hw(dev_id, &rule[i],
+ &hw_rule_ent[ent_idx], &ent_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (4 < (ent_idx - tmp_ent_idx))
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (j = tmp_ent_idx; j < ent_idx; j++)
+ {
+ rv = _shiva_acl_filter_alloc(dev_id, &flt_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_slct_update(&hw_rule_ent[tmp_ent_idx],
+ j - tmp_ent_idx, flt_idx);
+ SW_RTN_ON_ERROR(rv);
+ }
+ SW_SET_REG_BY_FIELD(RUL_SLCT5, SRC_PT, bind_pts,
+ hw_rule_ent[tmp_ent_idx].slct[5]);
+ }
+ }
+
+ /* alloc hardware select entry resource */
+ if (0 == list_ent[dev_id][list_idx].size)
+ {
+ list_new_size = rule_nr;
+ list_pri = list_ent[dev_id][list_idx].list_pri;
+
+ rv = hsl_acl_blk_alloc(dev_id, list_pri, list_new_size, list_id,
+ &list_addr);
+ SW_RTN_ON_ERROR(rv);
+
+ load_addr = list_addr;
+ }
+ else
+ {
+ list_new_size = list_ent[dev_id][list_idx].size + rule_nr;
+ list_addr = list_ent[dev_id][list_idx].addr;
+
+ rv = hsl_acl_blk_resize(dev_id, list_addr, list_new_size);
+ SW_RTN_ON_ERROR(rv);
+
+ /* must be careful resize opration maybe change list base address */
+ list_addr = list_ent[dev_id][list_idx].addr;
+ load_addr = list_ent[dev_id][list_idx].size + list_addr;
+ }
+
+ /* load acl rule to hardware */
+ rv = _shiva_acl_rule_set(dev_id, load_addr, hw_rule_ent, rule_nr);
+ if (SW_OK != rv)
+ {
+ (void) hsl_acl_blk_resize(dev_id, list_addr,
+ list_ent[dev_id][list_idx].size);
+ return rv;
+ }
+
+ /* update software list control information */
+ list_ent[dev_id][list_idx].size = list_new_size;
+ list_ent[dev_id][list_idx].addr = list_addr;
+
+ /* update hardware acl rule resource information */
+ _shiva_acl_filter_commit(dev_id);
+ _shiva_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+ a_uint32_t flt_idx[4];
+ a_uint32_t i, j, flt_nr;
+ a_uint32_t list_idx, addr, size, rule_idx, cnt;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == rule_nr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((rule_id + rule_nr) > list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ _shiva_acl_filter_snap(dev_id);
+
+ /* free hardware filter resource */
+ addr = list_ent[dev_id][list_idx].addr + rule_id;
+ for (i = 0; i < rule_nr; i++)
+ {
+ rv = _shiva_acl_slct_read(dev_id, &hw_rule_ent[0], i + addr);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_filter_map_get(&hw_rule_ent[0], flt_idx, &flt_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ for (j = 0; j < flt_nr; j++)
+ {
+ _shiva_acl_filter_free(dev_id, flt_idx[j]);
+ }
+ }
+
+ cnt = list_ent[dev_id][list_idx].size - (rule_id + rule_nr);
+ rule_idx = list_ent[dev_id][list_idx].addr + (rule_id + rule_nr);
+ rv = _shiva_acl_rule_copy(dev_id, rule_idx, rule_idx - rule_nr, cnt);
+ SW_RTN_ON_ERROR(rv);
+
+ addr = list_ent[dev_id][list_idx].addr;
+ size = list_ent[dev_id][list_idx].size;
+ rv = hsl_acl_blk_resize(dev_id, addr, size - rule_nr);
+ SW_RTN_ON_ERROR(rv);
+
+ list_ent[dev_id][list_idx].size -= rule_nr;
+ _shiva_acl_filter_commit(dev_id);
+ _shiva_acl_list_dump(dev_id);
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+ a_uint32_t list_idx, ent_idx, tmp_ent_idx, rule_idx;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (rule_id >= list_ent[dev_id][list_idx].size)
+ {
+ return SW_NOT_FOUND;
+ }
+
+ aos_mem_zero(rule, sizeof (fal_acl_rule_t));
+
+ ent_idx = 0;
+ tmp_ent_idx = 0;
+ rule_idx = list_ent[dev_id][list_idx].addr + rule_id;
+ rv = _shiva_acl_rule_get(dev_id, hw_rule_ent, &tmp_ent_idx, rule_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = _shiva_acl_rule_hw_to_sw(rule, hw_rule_ent, ent_idx,
+ tmp_ent_idx - ent_idx);
+ return rv;
+}
+
+static sw_error_t
+_shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, list_idx, rule_idx, base, ports;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx))
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ base = list_ent[dev_id][list_idx].addr;
+ ports = list_ent[dev_id][list_idx].bind_pts | (0x1 << obj_idx);
+ for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+ {
+ rule_idx = base + i;
+ rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ list_ent[dev_id][list_idx].bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+ a_uint32_t i, list_idx, rule_idx, base, ports;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_ACL_DIREC_IN != direc)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_ACL_BIND_PORT != obj_t)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ rv = _shiva_acl_list_loc(dev_id, list_id, &list_idx);
+ SW_RTN_ON_ERROR(rv);
+
+ if (!(list_ent[dev_id][list_idx].bind_pts & (0x1 << obj_idx)))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ base = list_ent[dev_id][list_idx].addr;
+ ports = list_ent[dev_id][list_idx].bind_pts & (~(0x1UL << obj_idx));
+ for (i = 0; i < list_ent[dev_id][list_idx].size; i++)
+ {
+ rule_idx = base + i;
+ rv = _shiva_acl_rule_bind(dev_id, rule_idx, ports);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ list_ent[dev_id][list_idx].bind_pts = ports;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ACL_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ACL_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+shiva_acl_list_dump(a_uint32_t dev_id)
+{
+ a_uint32_t idx;
+
+ aos_printk("\nshiva_acl_list_dump:\n");
+ for (idx = 0; idx < SHIVA_MAX_LIST; idx++)
+ {
+ if (ENT_USED == list_ent[dev_id][idx].status)
+ {
+ aos_printk
+ ("\n[id]:%02d [pri]:%02d [size]:%02d [addr]:%02d [pts_map]:0x%02x",
+ list_ent[dev_id][idx].list_id, list_ent[dev_id][idx].list_pri,
+ list_ent[dev_id][idx].size, list_ent[dev_id][idx].addr,
+ list_ent[dev_id][idx].bind_pts);
+ }
+ }
+ aos_printk("\n");
+
+ return SW_OK;
+}
+
+HSL_LOCAL sw_error_t
+shiva_acl_rule_dump(a_uint32_t dev_id)
+{
+ a_uint32_t slt_idx, flt_nr, i, j;
+ a_uint32_t flt_idx[4];
+ sw_error_t rv;
+ shiva_acl_hw_rule_t rule;
+
+ aos_printk("\nshiva_acl_rule_dump:\n");
+
+ aos_printk("\nfilter_bitmap:0x%x", filter[dev_id]);
+ for (slt_idx = 0; slt_idx < SHIVA_MAX_RULE; slt_idx++)
+ {
+ aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+
+ rv = _shiva_acl_slct_read(dev_id, &rule, slt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ rv = _shiva_acl_filter_map_get(&rule, flt_idx, &flt_nr);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\nslct_idx=%d ", slt_idx);
+ for (i = 0; i < flt_nr; i++)
+ {
+ aos_printk("flt%d_idx=%d ", i, flt_idx[i]);
+ }
+
+ aos_printk("\nslt:");
+ for (i = 0; i < (sizeof(rule.slct)/sizeof(a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", rule.slct[i]);
+ }
+
+ if (flt_nr)
+ {
+ rv = _shiva_acl_action_read(dev_id, &rule, slt_idx);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\nact:");
+ for (i = 0; i < (sizeof(rule.act)/sizeof(a_uint32_t)); i++)
+ {
+ aos_printk("%08x ", rule.act[i]);
+ }
+
+ for (i = 0; i < flt_nr; i++)
+ {
+ rv = _shiva_acl_filter_read(dev_id, &rule, flt_idx[i]);
+ if (SW_OK != rv)
+ {
+ continue;
+ }
+
+ aos_printk("\ntyp:%08x length:%08x", rule.typ, rule.len);
+ aos_printk("\nvlu:");
+ for (j = 0; j < (sizeof(rule.vlu)/sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule.vlu[j]);
+ }
+
+ aos_printk("\nmsk:");
+ for (j = 0; j < (sizeof(rule.msk)/sizeof(a_uint32_t)); j++)
+ {
+ aos_printk("%08x ", rule.msk[j]);
+ }
+ aos_printk("\n");
+ }
+ }
+ aos_printk("\n");
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+ a_uint32_t i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_zero(hw_rule_ent,
+ (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t));
+
+ aos_mem_zero(list_ent[dev_id],
+ SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+
+ for (i = 0; i < SHIVA_MAX_LIST; i++)
+ {
+ list_ent[dev_id][i].status = ENT_FREE;
+ }
+
+ filter[dev_id] = 0;
+ filter_snap[dev_id] = 0;
+
+ rv = hsl_acl_pool_destroy(dev_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+/**
+ * @brief Creat an acl list
+ * @details Comments:
+ * If the priority of a list is more small then the priority is more high,
+ * that means the list could be first matched.
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] list_pri acl list priority
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_creat(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t list_pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_list_creat(dev_id, list_id, list_pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Destroy an acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_destroy(a_uint32_t dev_id, a_uint32_t list_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_list_destroy(dev_id, list_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add one rule or more rules to an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this adding operation in list
+ * @param[in] rule_nr rule number of this adding operation
+ * @param[in] rule rules content of this adding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_add(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr,
+ fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_rule_add(dev_id, list_id, rule_id, rule_nr, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete one rule or more rules from an existing acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[in] rule_nr rule number of this deleteing operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_delete(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, a_uint32_t rule_nr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_rule_delete(dev_id, list_id, rule_id, rule_nr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Query one particular rule in a particular acl list
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] rule_id first rule id of this deleteing operation in list
+ * @param[out] rule rule content of this operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_rule_query(a_uint32_t dev_id, a_uint32_t list_id,
+ a_uint32_t rule_id, fal_acl_rule_t * rule)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_rule_query(dev_id, list_id, rule_id, rule);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Bind an acl list to a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this binding operation
+ * @param[in] obj_t object type of this binding operation
+ * @param[in] obj_idx object index of this binding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_bind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_list_bind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Unbind an acl list from a particular object
+ * @details Comments:
+ * If obj_t equals FAL_ACL_BIND_PORT then obj_idx means port id
+ * @param[in] dev_id device id
+ * @param[in] list_id acl list id
+ * @param[in] direc direction of this unbinding operation
+ * @param[in] obj_t object type of this unbinding operation
+ * @param[in] obj_idx object index of this unbinding operation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_list_unbind(a_uint32_t dev_id, a_uint32_t list_id,
+ fal_acl_direc_t direc, fal_acl_bind_obj_t obj_t,
+ a_uint32_t obj_idx)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_list_unbind(dev_id, list_id, direc, obj_t, obj_idx);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get working status of ACL engine on a particular device
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_acl_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_acl_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_acl_init(a_uint32_t dev_id)
+{
+ static a_bool_t b_hw_rule = A_FALSE;
+ hsl_acl_func_t *acl_func;
+ shiva_acl_hw_rule_t rule;
+ sw_error_t rv;
+ a_uint32_t i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == b_hw_rule)
+ {
+ hw_rule_ent = (shiva_acl_hw_rule_t *)
+ aos_mem_alloc((SHIVA_MAX_RULE +
+ 3) * sizeof (shiva_acl_hw_rule_t));
+ if (NULL == hw_rule_ent)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(hw_rule_ent,
+ (SHIVA_MAX_RULE + 3) * sizeof (shiva_acl_hw_rule_t));
+ b_hw_rule = A_TRUE;
+ }
+
+ list_ent[dev_id] = (shiva_acl_list_t *)
+ aos_mem_alloc(SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+ if (NULL == list_ent[dev_id])
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(list_ent[dev_id],
+ SHIVA_MAX_LIST * sizeof (shiva_acl_list_t));
+
+ for (i = 0; i < SHIVA_MAX_LIST; i++)
+ {
+ list_ent[dev_id][i].status = ENT_FREE;
+ }
+
+ filter[dev_id] = 0;
+ filter_snap[dev_id] = 0;
+
+ rv = hsl_acl_pool_creat(dev_id, SHIVA_MAX_LIST, SHIVA_MAX_RULE);
+ SW_RTN_ON_ERROR(rv);
+
+ acl_func = hsl_acl_ptr_get(dev_id);
+ SW_RTN_ON_NULL(acl_func);
+
+ acl_func->acl_rule_copy = _shiva_acl_rule_copy;
+ acl_func->acl_rule_invalid = _shiva_acl_rule_invalid;
+ acl_func->acl_addr_update = _shiva_acl_addr_update;
+
+ /* zero acl hardware memory */
+ aos_mem_zero(&rule, sizeof (shiva_acl_hw_rule_t));
+ for (i = 0; i < SHIVA_MAX_RULE; i++)
+ {
+ rv = _shiva_acl_slct_write(dev_id, &rule, i);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+#ifdef SHIVA_SW_ENTRY
+ flt_vlu_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+ if (NULL == flt_vlu_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_vlu_mem, SHIVA_MAX_RULE * 32);
+
+ flt_msk_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+ if (NULL == flt_msk_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_msk_mem, SHIVA_MAX_RULE * 32);
+
+ flt_typ_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4);
+ if (NULL == flt_typ_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_typ_mem, SHIVA_MAX_RULE * 4);
+
+ flt_len_mem = aos_mem_alloc(SHIVA_MAX_RULE * 4);
+ if (NULL == flt_len_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(flt_len_mem, SHIVA_MAX_RULE * 4);
+
+ act_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+ if (NULL == act_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(act_mem, SHIVA_MAX_RULE * 32);
+
+ slct_mem = aos_mem_alloc(SHIVA_MAX_RULE * 32);
+ if (NULL == slct_mem)
+ {
+ return SW_NO_RESOURCE;
+ }
+ aos_mem_zero(slct_mem, SHIVA_MAX_RULE * 32);
+#endif
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->acl_list_creat = shiva_acl_list_creat;
+ p_api->acl_list_destroy = shiva_acl_list_destroy;
+ p_api->acl_list_bind = shiva_acl_list_bind;
+ p_api->acl_list_unbind = shiva_acl_list_unbind;
+ p_api->acl_rule_add = shiva_acl_rule_add;
+ p_api->acl_rule_delete = shiva_acl_rule_delete;
+ p_api->acl_rule_query = shiva_acl_rule_query;
+ p_api->acl_status_set = shiva_acl_status_set;
+ p_api->acl_status_get = shiva_acl_status_get;
+ p_api->acl_list_dump = shiva_acl_list_dump;
+ p_api->acl_rule_dump = shiva_acl_rule_dump;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_fdb.c b/src/hsl/shiva/shiva_fdb.c
new file mode 100644
index 0000000..55b9ab3
--- /dev/null
+++ b/src/hsl/shiva/shiva_fdb.c
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_fdb SHIVA_FDB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_fdb.h"
+#include "shiva_reg.h"
+
+#define ARL_FLUSH_ALL 1
+#define ARL_LOAD_ENTRY 2
+#define ARL_PURGE_ENTRY 3
+#define ARL_FLUSH_ALL_UNLOCK 4
+#define ARL_FLUSH_PORT_UNICAST 5
+#define ARL_NEXT_ENTRY 6
+#define ARL_FIND_ENTRY 7
+
+#define ARL_FIRST_ENTRY 1001
+#define ARL_FLUSH_PORT_NO_STATIC 1002
+#define ARL_FLUSH_PORT_AND_STATIC 1003
+
+static a_bool_t
+shiva_fdb_is_zeroaddr(fal_mac_addr_t addr)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < 6; i++)
+ {
+ if (addr.uc[i])
+ {
+ return A_FALSE;
+ }
+ }
+
+ return A_TRUE;
+}
+
+static void
+shiva_fdb_fill_addr(fal_mac_addr_t addr, a_uint32_t * reg0, a_uint32_t * reg1)
+{
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE0, addr.uc[0], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE1, addr.uc[1], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE2, addr.uc[2], *reg1);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC1, AT_ADDR_BYTE3, addr.uc[3], *reg1);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE4, addr.uc[4], *reg0);
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_ADDR_BYTE5, addr.uc[5], *reg0);
+
+ return;
+}
+
+static sw_error_t
+shiva_atu_sw_to_hw(a_uint32_t dev_id, const fal_fdb_entry_t * entry,
+ a_uint32_t reg[])
+{
+ a_uint32_t port;
+
+ if (A_FALSE == entry->portmap_en)
+ {
+ if (A_TRUE !=
+ hsl_port_prop_check(dev_id, entry->port.id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = 0x1UL << entry->port.id;
+ }
+ else
+ {
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, entry->port.map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ port = entry->port.map;
+ }
+
+ if (FAL_MAC_CPY_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, COPY_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == entry->dacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->dacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (FAL_MAC_DROP == entry->sacmd)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, SA_DROP_EN, 1, reg[2]);
+ }
+ else if (FAL_MAC_FRWRD != entry->sacmd)
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ if (A_TRUE == entry->leaky_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 1, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, LEAKY_EN, 0, reg[2]);
+ }
+
+ if (A_TRUE == entry->static_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 15, reg[2]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_STATUS, 7, reg[2]);
+ }
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, MIRROR_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->clone_en)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CLONE_EN, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->cross_pt_state)
+ {
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, CROSS_PT, 1, reg[2]);
+ }
+
+ if (A_TRUE == entry->da_pri_en)
+ {
+ hsl_dev_t *p_dev;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI_EN, 1, reg[2]);
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+
+ if (entry->da_queue > (p_dev->nr_queue - 1))
+ return SW_BAD_PARAM;
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, AT_PRI, entry->da_queue, reg[2]);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC2, DES_PORT, port, reg[2]);
+ shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+
+ return SW_OK;
+}
+
+static void
+shiva_atu_hw_to_sw(const a_uint32_t reg[], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, COPY_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, REDRCT_TO_CPU, data, reg[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, SA_DROP_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, LEAKY_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, data, reg[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, MIRROR_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->clone_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CLONE_EN, data, reg[2]);
+ if (1 == data)
+ {
+ entry->clone_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI_EN, data, reg[2]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_PRI, data, reg[2]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x3;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, CROSS_PT, data, reg[2]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, DES_PORT, data, reg[2]);
+
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 0; i < 4; i++)
+ {
+ entry->addr.uc[i] = (reg[1] >> ((3 - i) << 3)) & 0xff;
+ }
+
+ for (i = 4; i < 6; i++)
+ {
+ entry->addr.uc[i] = (reg[0] >> ((7 - i) << 3)) & 0xff;
+ }
+
+ return;
+}
+
+static sw_error_t
+shiva_fdb_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t busy = 1;
+ a_uint32_t full_vio;
+ a_uint32_t i = 1000;
+ a_uint32_t entry;
+ a_uint32_t hwop = op;
+
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_BUSY;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_BUSY, 1, entry);
+
+ if (ARL_FLUSH_PORT_AND_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 1, entry);
+ }
+
+ if (ARL_FLUSH_PORT_NO_STATIC == hwop)
+ {
+ hwop = ARL_FLUSH_PORT_UNICAST;
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, FLUSH_ST_EN, 0, entry);
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_FUNC, hwop, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ busy = 1;
+ i = 1000;
+ while (busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_BUSY,
+ (a_uint8_t *) (&busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_FAIL;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0, AT_FULL_VIO,
+ (a_uint8_t *) (&full_vio), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (full_vio)
+ {
+ /* must clear AT_FULL_VOI bit */
+ entry = 0x1000;
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (ARL_LOAD_ENTRY == hwop)
+ {
+ return SW_FULL;
+ }
+ else if ((ARL_PURGE_ENTRY == hwop)
+ || (ARL_FLUSH_PORT_UNICAST == hwop))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+shiva_atu_get(a_uint32_t dev_id, fal_fdb_entry_t * entry, a_uint32_t op)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0 };
+ a_uint32_t status = 0;
+ a_uint32_t hwop = op;
+
+ if ((ARL_NEXT_ENTRY == op)
+ || (ARL_FIND_ENTRY == op))
+ {
+ shiva_fdb_fill_addr(entry->addr, ®[0], ®[1]);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ /* set status not zero */
+ if (ARL_NEXT_ENTRY == op)
+ {
+ reg[2] = 0xf0000;
+ }
+
+ if (ARL_FIRST_ENTRY == op)
+ {
+ hwop = ARL_NEXT_ENTRY;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_fdb_commit(dev_id, hwop);
+ SW_RTN_ON_ERROR(rv);
+
+ /* get hardware enrety */
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(ADDR_TABLE_FUNC2, AT_STATUS, status, reg[2]);
+
+ shiva_atu_hw_to_sw(reg, entry);
+
+ /* If hardware return back with address and status all zero,
+ that means no other next valid entry in fdb table */
+ if ((A_TRUE == shiva_fdb_is_zeroaddr(entry->addr))
+ && (0 == status))
+ {
+ if (ARL_NEXT_ENTRY == op)
+ {
+ return SW_NO_MORE;
+ }
+ else if ((ARL_FIND_ENTRY == op)
+ || (ARL_FIRST_ENTRY == op))
+ {
+ return SW_NOT_FOUND;
+ }
+ else
+ {
+ return SW_FAIL;
+ }
+ }
+ else
+ {
+ return SW_OK;
+ }
+}
+
+static sw_error_t
+_shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[3] = { 0, 0, 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = shiva_atu_sw_to_hw(dev_id, entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC2, 0,
+ (a_uint8_t *) (®[2]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®[1]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®[0]),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_fdb_commit(dev_id, ARL_LOAD_ENTRY);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL);
+ }
+ else
+ {
+ rv = shiva_fdb_commit(dev_id, ARL_FLUSH_ALL_UNLOCK);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_SET_REG_BY_FIELD(ADDR_TABLE_FUNC0, AT_PORT_NUM, port_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_FDB_DEL_STATIC & flag)
+ {
+ rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_AND_STATIC);
+ }
+ else
+ {
+ rv = shiva_fdb_commit(dev_id, ARL_FLUSH_PORT_NO_STATIC);
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg0 = 0, reg1 = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ shiva_fdb_fill_addr(entry->addr, ®0, ®1);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC1, 0, (a_uint8_t *) (®1),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, ADDR_TABLE_FUNC0, 0, (a_uint8_t *) (®0),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_fdb_commit(dev_id, ARL_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = shiva_atu_get(dev_id, entry, ARL_FIRST_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ rv = shiva_atu_get(dev_id, entry, ARL_FIND_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEARN_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((65535 * 7 < *time) || (7 > *time))
+ {
+ return SW_BAD_PARAM;
+ }
+ data = *time / 7;
+ *time = data * 7;
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, AGE_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *time = data * 7;
+ return SW_OK;
+}
+
+static void
+_shiva_fdb_hw_to_sw(a_uint32_t tbl[3], fal_fdb_entry_t * entry)
+{
+ a_uint32_t i, data;
+
+ aos_mem_zero(entry, sizeof (fal_fdb_entry_t));
+
+ entry->dacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_CPYCPU_EN, data, tbl[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_CPY_TO_CPU;
+ }
+
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_RDTCPU_EN, data, tbl[2]);
+ if (1 == data)
+ {
+ entry->dacmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ entry->leaky_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_LEANKY_EN, data, tbl[2]);
+ if (1 == data)
+ {
+ entry->leaky_en = A_TRUE;
+ }
+
+ entry->static_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]);
+ if (0xf == data)
+ {
+ entry->static_en = A_TRUE;
+ }
+
+ entry->clone_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MACCLONE_EN, data, tbl[1]);
+ if (1 == data)
+ {
+ entry->clone_en = A_TRUE;
+ }
+
+ entry->sacmd = FAL_MAC_FRWRD;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_SADROP_EN, data, tbl[1]);
+ if (1 == data)
+ {
+ entry->sacmd = FAL_MAC_DROP;
+ }
+
+ entry->mirror_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_MIRROR_EN, data, tbl[1]);
+ if (1 == data)
+ {
+ entry->mirror_en = A_TRUE;
+ }
+
+ entry->da_pri_en = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY_EN, data, tbl[1]);
+ if (1 == data)
+ {
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_PRIORITY, data, tbl[1]);
+ entry->da_pri_en = A_TRUE;
+ entry->da_queue = data & 0x3;
+ }
+
+ entry->cross_pt_state = A_FALSE;
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_CROSS_STATE, data, tbl[1]);
+ if (1 == data)
+ {
+ entry->cross_pt_state = A_TRUE;
+ }
+
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC1, FDB_DES_PORT, data, tbl[1]);
+ entry->portmap_en = A_TRUE;
+ entry->port.map = data;
+
+ for (i = 2; i < 6; i++)
+ {
+ entry->addr.uc[i] = (tbl[0] >> ((5 - i) << 3)) & 0xff;
+ }
+
+ for (i = 0; i < 2; i++)
+ {
+ entry->addr.uc[i] = (tbl[1] >> ((1 - i) << 3)) & 0xff;
+ }
+}
+
+#define SHIVA_FDB_ENTRY_NUM 1024
+#define SHIVA_FDB_ENTRY_ADDR0 0x30000
+#define SHIVA_FDB_ENTRY_ADDR1 0x30004
+#define SHIVA_FDB_ENTRY_ADDR2 0x30008
+
+static sw_error_t
+_shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ a_uint32_t index, addr, data, tbl[3] = { 0 };
+ sw_error_t rv;
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (SHIVA_FDB_ENTRY_NUM == *iterator)
+ {
+ return SW_NO_MORE;
+ }
+
+ if (SHIVA_FDB_ENTRY_NUM < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < SHIVA_FDB_ENTRY_NUM; index++)
+ {
+ addr = SHIVA_FDB_ENTRY_ADDR2 + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[2])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(FDB_TABLE_FUNC2, FDB_STATUS, data, tbl[2]);
+ if (data)
+ {
+ addr = SHIVA_FDB_ENTRY_ADDR0 + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[0])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ addr = SHIVA_FDB_ENTRY_ADDR1 + (index << 4);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(tbl[1])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ _shiva_fdb_hw_to_sw(tbl, entry);
+ break;
+ }
+ }
+
+ if (SHIVA_FDB_ENTRY_NUM == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+/**
+ * @brief Add a Fdb entry
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_add(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete all Fdb entries
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_all(a_uint32_t dev_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_del_all(dev_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete Fdb entries on a particular port
+ * @details Comments:
+ * If set FAL_FDB_DEL_STATIC bit in flag which means delete all fdb
+ * entries otherwise only delete dynamic entries.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] flag delete operation option
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_by_port(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_del_by_port(dev_id, port_id, flag);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a particular Fdb entry through mac address
+ * @details Comments:
+ * Only addr field in entry is meaning. For IVL learning vid or fid field
+ * also is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_del_by_mac(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_del_by_mac(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get first Fdb entry from particular device
+ * @param[in] dev_id device id
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_first(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_first(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a particular Fdb entry from device through mac address.
+ * @details Comments:
+ For input parameter only addr field in entry is meaning.
+ * @param[in] dev_id device id
+ * @param[in] entry fdb entry
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_find(dev_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address learning status on a particular port.
+ * @details Comments:
+ * This operation will enable or disable dynamic address learning
+ * feature on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_port_learn_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address learning status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_port_learn_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging status on particular device.
+ * @details Comments:
+ * This operation will enable or disable dynamic address aging
+ * feature on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_age_ctrl_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging status on particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable enable or disable
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_age_ctrl_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dynamic address aging time on a particular device.
+ * @details Comments:
+ * This operation will set dynamic address aging time on a particular device.
+ * The unit of time is second. Because different device has differnet
+ * hardware granularity function will return actual time in hardware.
+ * @param[in] dev_id device id
+ * @param time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_age_time_set(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dynamic address aging time on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] time aging time
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_age_time_get(a_uint32_t dev_id, a_uint32_t *time)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_age_time_get(dev_id, time);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all fdb entries on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] iterator fdb entry index if it's zero means get the first entry
+ * @param[out] iterator next valid fdb entry index
+ * @param[out] entry fdb entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_fdb_iterate(a_uint32_t dev_id, a_uint32_t * iterator, fal_fdb_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_fdb_iterate(dev_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_fdb_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->fdb_add = shiva_fdb_add;
+ p_api->fdb_del_all = shiva_fdb_del_all;
+ p_api->fdb_del_by_port = shiva_fdb_del_by_port;
+ p_api->fdb_del_by_mac = shiva_fdb_del_by_mac;
+ p_api->fdb_first = shiva_fdb_first;
+ p_api->fdb_find = shiva_fdb_find;
+ p_api->port_learn_set = shiva_fdb_port_learn_set;
+ p_api->port_learn_get = shiva_fdb_port_learn_get;
+ p_api->age_ctrl_set = shiva_fdb_age_ctrl_set;
+ p_api->age_ctrl_get = shiva_fdb_age_ctrl_get;
+ p_api->age_time_set = shiva_fdb_age_time_set;
+ p_api->age_time_get = shiva_fdb_age_time_get;
+ p_api->fdb_iterate = shiva_fdb_iterate;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_igmp.c b/src/hsl/shiva/shiva_igmp.c
new file mode 100644
index 0000000..66c1245
--- /dev/null
+++ b/src/hsl/shiva/shiva_igmp.c
@@ -0,0 +1,971 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_igmp SHIVA_IGMP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_igmp.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, IGMP_MLD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_COPY_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, JOIN_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, LEAVE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_mports_validity_check(dev_id, pts))
+ {
+ return SW_BAD_PARAM;
+ }
+ val = pts;
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, IGMP_DP,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *pts = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_CREAT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 0xf;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0xe;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_STATIC,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0xf == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_JOIN_LEAKY,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, IGMP_V3_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry;
+ hsl_dev_t *p_dev;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 1, entry);
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (queue >= p_dev->nr_queue)
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, queue, entry);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI_EN, 0, entry);
+ SW_SET_REG_BY_FIELD(QM_CTL, IGMP_PRI, 0, entry);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t entry, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, QM_CTL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI_EN, data, entry);
+ if (data)
+ {
+ *enable = A_TRUE;
+ SW_GET_FIELD_BY_REG(QM_CTL, IGMP_PRI, data, entry);
+ *queue = data;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ *queue = 0;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set igmp/mld packets snooping status on a particular port.
+ * @details Comments:
+ * After enabling igmp/mld snooping feature on a particular port all kinds
+ * igmp/mld packets received on this port would be acknowledged by hardware.
+ * Particular forwarding decision could be setted by fal_igmp_mld_cmd_set.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmps_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmps_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets snooping status on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmps_status_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmps_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld packets forwarding command on a particular device.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * This operation will take effect only after enabling igmp/mld snooping
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld join packets hardware acknowledgement status on particular port.
+ * @details Comments:
+ * After enabling igmp/mld join feature on a particular port hardware will
+ * dynamic learning or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_join_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmp_mld_join_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld join packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_join_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmp_mld_join_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @details Comments:
+ * After enabling igmp leave feature on a particular port hardware will dynamic
+ * deleting or changing multicast entry.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_leave_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmp_mld_leave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld leave packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_igmp_mld_leave_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_igmp_mld_leave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmp/mld router ports on a particular device.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port igmp/mld
+ * join/leave packets received on this port will be forwarded to router ports.
+ * @param[in] dev_id device id
+ * @param[in] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_rp_set(a_uint32_t dev_id, fal_pbmp_t pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_rp_set(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmp/mld router ports on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] pts dedicates ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_rp_get(a_uint32_t dev_id, fal_pbmp_t * pts)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_rp_get(dev_id, pts);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * entry creat hardware will dynamic creat and delete multicast entry,
+ * otherwise hardware only can change destination ports of existing muticast entry.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_creat_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_creat_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the status of creating multicast entry during igmp/mld join/leave procedure.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_creat_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_creat_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the static status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * static status hardware will not age out multicast entry which leardned by hardware,
+ * otherwise hardware will age out multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_static_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_static_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the static status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_static_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_static_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the leaky status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set leaky flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set leaky flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_leaky_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_leaky_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the leaky status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_leaky_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_leaky_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @details Comments:
+ * After enabling igmp join/leave feature on a particular port hardware will dynamic
+ * creating or changing multicast entry after receiving igmpv3/mldv2 packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_v3_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_v3_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get igmpv3/mldv2 packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_v3_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_v3_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set the queue status of multicast entry which learned by hardware.
+ * @details Comments:
+ * After enabling igmp/mld join/leave feature on a particular port if enable
+ * leaky status hardware will set queue flag of multicast entry which leardned by hardware,
+ * otherwise hardware will not set queue flag of multicast entry which leardned by hardware.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_queue_set(a_uint32_t dev_id, a_bool_t enable, a_uint32_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_queue_set(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get the queue status of multicast entry which learned by hardware.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_igmp_mld_entry_queue_get(a_uint32_t dev_id, a_bool_t * enable, a_uint32_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_igmp_mld_entry_queue_get(dev_id, enable, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_igmp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_igmps_status_set = shiva_port_igmps_status_set;
+ p_api->port_igmps_status_get = shiva_port_igmps_status_get;
+ p_api->igmp_mld_cmd_set = shiva_igmp_mld_cmd_set;
+ p_api->igmp_mld_cmd_get = shiva_igmp_mld_cmd_get;
+ p_api->port_igmp_join_set = shiva_port_igmp_mld_join_set;
+ p_api->port_igmp_join_get = shiva_port_igmp_mld_join_get;
+ p_api->port_igmp_leave_set = shiva_port_igmp_mld_leave_set;
+ p_api->port_igmp_leave_get = shiva_port_igmp_mld_leave_get;
+ p_api->igmp_rp_set = shiva_igmp_mld_rp_set;
+ p_api->igmp_rp_get = shiva_igmp_mld_rp_get;
+ p_api->igmp_entry_creat_set = shiva_igmp_mld_entry_creat_set;
+ p_api->igmp_entry_creat_get = shiva_igmp_mld_entry_creat_get;
+ p_api->igmp_entry_static_set = shiva_igmp_mld_entry_static_set;
+ p_api->igmp_entry_static_get = shiva_igmp_mld_entry_static_get;
+ p_api->igmp_entry_leaky_set = shiva_igmp_mld_entry_leaky_set;
+ p_api->igmp_entry_leaky_get = shiva_igmp_mld_entry_leaky_get;
+ p_api->igmp_entry_v3_set = shiva_igmp_mld_entry_v3_set;
+ p_api->igmp_entry_v3_get = shiva_igmp_mld_entry_v3_get;
+ p_api->igmp_entry_queue_set = shiva_igmp_mld_entry_queue_set;
+ p_api->igmp_entry_queue_get = shiva_igmp_mld_entry_queue_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_init.c b/src/hsl/shiva/shiva_init.c
new file mode 100644
index 0000000..85deb87
--- /dev/null
+++ b/src/hsl/shiva/shiva_init.c
@@ -0,0 +1,437 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_init SHIVA_INIT
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mib.h"
+#include "shiva_port_ctrl.h"
+#include "shiva_portvlan.h"
+#include "shiva_vlan.h"
+#include "shiva_fdb.h"
+#include "shiva_qos.h"
+#include "shiva_mirror.h"
+#include "shiva_stp.h"
+#include "shiva_rate.h"
+#include "shiva_misc.h"
+#include "shiva_leaky.h"
+#include "shiva_igmp.h"
+#include "shiva_acl.h"
+#include "shiva_led.h"
+#include "shiva_reg_access.h"
+#include "shiva_reg.h"
+#include "shiva_init.h"
+#include "f1_phy.h"
+
+static ssdk_init_cfg * shiva_cfg[SW_MAX_NR_DEV] = { 0 };
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+/* For SHIVA there are five internal PHY devices and seven MAC devices.
+ MAC0 always connect to external MAC device.
+ PHY4 can connect to MAC5 or external MAC device.
+ MAC6 always connect to external devices.
+ MAC1..MAC4 connect to internal PHY0..PHY3.
+*/
+static sw_error_t
+shiva_portproperty_init(a_uint32_t dev_id, hsl_init_mode mode)
+{
+ hsl_port_prop_t p_type;
+ hsl_dev_t *pdev = NULL;
+ fal_port_t port_id;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ hsl_port_prop_portmap_set(dev_id, port_id);
+
+ for (p_type = HSL_PP_PHY; p_type < HSL_PP_BUTT; p_type++)
+ {
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ continue;
+ }
+
+ switch (p_type)
+ {
+ case HSL_PP_PHY:
+ if (HSL_CPU_1 != mode)
+ {
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != (pdev->nr_ports -1))
+ && (port_id != (pdev->nr_ports -2)))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ else
+ {
+ if ((port_id != pdev->cpu_port_nr)
+ && (port_id != pdev->nr_ports - 1))
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ }
+ }
+ break;
+
+ case HSL_PP_INCL_CPU:
+ /* include cpu port but exclude wan port in some cases */
+ if (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+
+ break;
+
+ case HSL_PP_EXCL_CPU:
+ /* exclude cpu port and wan port in some cases */
+ if ((port_id != pdev->cpu_port_nr)
+ && (!((HSL_CPU_2 == mode) && (port_id == (pdev->nr_ports - 2)))))
+ SW_RTN_ON_ERROR(hsl_port_prop_set(dev_id, port_id, p_type));
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ if (HSL_NO_CPU == mode)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id + 1));
+ }
+ else
+ {
+ if (port_id != pdev->cpu_port_nr)
+ {
+ SW_RTN_ON_ERROR(hsl_port_prop_set_phyid
+ (dev_id, port_id, port_id - 1));
+ }
+ }
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+shiva_hw_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ hsl_dev_t *pdev = NULL;
+ a_uint32_t port_id;
+ a_uint32_t data;
+ sw_error_t rv;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (NULL == pdev)
+ {
+ return SW_NOT_INITIALIZED;
+ }
+
+ for (port_id = 0; port_id < pdev->nr_ports; port_id++)
+ {
+ if (port_id == pdev->cpu_port_nr)
+ {
+ continue;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 1, data);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+shiva_bist_test(a_uint32_t dev_id)
+{
+ a_uint32_t entry, data, i;
+ sw_error_t rv;
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ONE_ERR, data, entry);
+ if (!data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_ADDR, data, entry);
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_EN, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_RCV, RCV_ADDR, data, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_RCV, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+ else
+ {
+ return SW_OK;
+ }
+
+ entry = 0;
+ SW_SET_REG_BY_FIELD(BIST_CTRL, BIST_BUSY, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN2, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN1, 1, entry);
+ SW_SET_REG_BY_FIELD(BIST_CTRL, PTN_EN0, 1, entry);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ data = 1;
+ i = 0x1000;
+ while (data && --i)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, BIST_CTRL, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(BIST_CTRL, BIST_BUSY, data, entry);
+ aos_udelay(5);
+ }
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ SW_GET_FIELD_BY_REG(BIST_CTRL, ERR_CNT, data, entry);
+ if (data)
+ {
+ return SW_INIT_ERROR;
+ }
+
+ return SW_OK;
+}
+#endif
+
+static sw_error_t
+shiva_dev_init(a_uint32_t dev_id, hsl_init_mode cpu_mode)
+{
+ hsl_dev_t *pdev = NULL;
+
+ pdev = hsl_dev_ptr_get(dev_id);
+ if (pdev == NULL)
+ return SW_NOT_INITIALIZED;
+
+ pdev->nr_ports = 7;
+ pdev->nr_phy = 5;
+ pdev->cpu_port_nr = 0;
+ pdev->nr_vlans = 4096;
+ pdev->hw_vlan_query = A_TRUE;
+ pdev->nr_queue = 4;
+ pdev->cpu_mode = cpu_mode;
+
+ return SW_OK;
+}
+
+
+static sw_error_t
+_shiva_reset(a_uint32_t dev_id)
+{
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_hw_init(dev_id, shiva_cfg[dev_id]);
+ SW_RTN_ON_ERROR(rv);
+
+ SHIVA_ACL_RESET(rv, dev_id);
+#endif
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_cleanup(a_uint32_t dev_id)
+{
+ if (shiva_cfg[dev_id])
+ {
+ aos_mem_free(shiva_cfg[dev_id]);
+ shiva_cfg[dev_id] = NULL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief reset hsl layer.
+ * @details Comments:
+ * This operation will reset hsl layer
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_reset(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_reset(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Init hsl layer.
+ * @details Comments:
+ * This operation will init hsl layer and hsl layer
+ * @param[in] dev_id device id
+ * @param[in] cfg configuration for initialization
+ * @return SW_OK or error code
+ */
+sw_error_t
+shiva_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (NULL == shiva_cfg[dev_id])
+ {
+ shiva_cfg[dev_id] = aos_mem_alloc(sizeof (ssdk_init_cfg));
+ }
+
+ if (NULL == shiva_cfg[dev_id])
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+ aos_mem_copy(shiva_cfg[dev_id], cfg, sizeof (ssdk_init_cfg));
+
+ SW_RTN_ON_ERROR(shiva_reg_access_init(dev_id, cfg->reg_mode));
+
+ SW_RTN_ON_ERROR(shiva_dev_init(dev_id, cfg->cpu_mode));
+
+#if !(defined(KERNEL_MODULE) && defined(USER_MODE))
+ {
+ a_uint32_t i, entry;
+ sw_error_t rv;
+
+ if(HSL_MDIO == cfg->reg_mode)
+ {
+ SW_RTN_ON_ERROR(shiva_bist_test(dev_id));
+
+ entry = 0x1;
+ HSL_REG_FIELD_SET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ i = 0x10;
+ do
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, MASK_CTL, 0, SOFT_RST,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ aos_mdelay(10);
+ }
+ while (entry && --i);
+
+ if (0 == i)
+ {
+ return SW_INIT_ERROR;
+ }
+ }
+ SW_RTN_ON_ERROR(hsl_port_prop_init());
+ SW_RTN_ON_ERROR(hsl_port_prop_init_by_dev(dev_id));
+ SW_RTN_ON_ERROR(shiva_portproperty_init(dev_id, cfg->cpu_mode));
+
+ SHIVA_MIB_INIT(rv, dev_id);
+ SHIVA_PORT_CTRL_INIT(rv, dev_id);
+ SHIVA_PORTVLAN_INIT(rv, dev_id);
+ SHIVA_VLAN_INIT(rv, dev_id);
+ SHIVA_FDB_INIT(rv, dev_id);
+ SHIVA_QOS_INIT(rv, dev_id);
+ SHIVA_STP_INIT(rv, dev_id);
+ SHIVA_MIRR_INIT(rv, dev_id);
+ SHIVA_RATE_INIT(rv, dev_id);
+ SHIVA_MISC_INIT(rv, dev_id);
+ SHIVA_LEAKY_INIT(rv, dev_id);
+ SHIVA_IGMP_INIT(rv, dev_id);
+ SHIVA_ACL_INIT(rv, dev_id);
+ SHIVA_LED_INIT(rv, dev_id);
+
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->dev_reset = shiva_reset;
+ p_api->dev_clean = shiva_cleanup;
+ }
+
+ SW_RTN_ON_ERROR(shiva_hw_init(dev_id, cfg));
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_leaky.c b/src/hsl/shiva/shiva_leaky.c
new file mode 100644
index 0000000..11a3b3e
--- /dev/null
+++ b/src/hsl/shiva/shiva_leaky.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_leaky SHIVA_LEAKY
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_leaky.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_UNI_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_LEAKY_PORT_CTRL == ctrl_mode)
+ {
+ data = 0;
+ }
+ else if (FAL_LEAKY_FDB_CTRL == ctrl_mode)
+ {
+ data = 1;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, ARL_MUL_LEAKY,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *ctrl_mode = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ *ctrl_mode = FAL_LEAKY_PORT_CTRL;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ARP_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, UNI_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, MUL_LEAKY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set unicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_uc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_uc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_uc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_uc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Set multicast packets leaky control mode on a particular device.
+* @param[in] dev_id device id
+* @param[in] ctrl_mode leaky control mode
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_mc_leaky_mode_set(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mc_leaky_mode_set(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky control mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] ctrl_mode leaky control mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mc_leaky_mode_get(a_uint32_t dev_id,
+ fal_leaky_ctrl_mode_t *ctrl_mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mc_leaky_mode_get(dev_id, ctrl_mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_arp_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_arp_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_arp_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_arp_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_uc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_uc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get unicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_uc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_uc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_mc_leaky_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_mc_leaky_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get multicast packets leaky status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_mc_leaky_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_mc_leaky_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_leaky_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->uc_leaky_mode_set = shiva_uc_leaky_mode_set;
+ p_api->uc_leaky_mode_get = shiva_uc_leaky_mode_get;
+ p_api->mc_leaky_mode_set = shiva_mc_leaky_mode_set;
+ p_api->mc_leaky_mode_get = shiva_mc_leaky_mode_get;
+ p_api->port_arp_leaky_set = shiva_port_arp_leaky_set;
+ p_api->port_arp_leaky_get = shiva_port_arp_leaky_get;
+ p_api->port_uc_leaky_set = shiva_port_uc_leaky_set;
+ p_api->port_uc_leaky_get = shiva_port_uc_leaky_get;
+ p_api->port_mc_leaky_set = shiva_port_mc_leaky_set;
+ p_api->port_mc_leaky_get = shiva_port_mc_leaky_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_led.c b/src/hsl/shiva/shiva_led.c
new file mode 100644
index 0000000..3c8cdb2
--- /dev/null
+++ b/src/hsl/shiva/shiva_led.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_led SHIVA_LED
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "shiva_led.h"
+#include "shiva_reg.h"
+
+#define MAX_LED_PATTERN_ID 1
+#define LED_PATTERN_ADDR 0xB0
+
+static sw_error_t
+_shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, mode;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (group >= LED_GROUP_BUTT)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (LED_MAC_PORT_GROUP == group)
+ {
+ addr = LED_PATTERN_ADDR + 8;
+ }
+ else
+ {
+ addr = LED_PATTERN_ADDR + (id << 2);
+ }
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ mode = 0;
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ mode = 1;
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ mode = 2;
+ }
+ else if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ mode = 3;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(LED_CTRL, PATTERN_EN, mode, data);
+
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FULL_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, HALF_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, POWERON_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, GE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, FE_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, ETH_LIGHT_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, COL_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, RX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, TX_BLINK_EN, 1, data);
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 1, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, LINKUP_OVER_EN, 0, data);
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 0, data);
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 1, data);
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 2, data);
+ }
+ else if (LED_BLINK_TXRX == pattern->freq)
+ {
+ SW_SET_REG_BY_FIELD(LED_CTRL, BLINK_FREQ, 3, data);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ reg &= 0xffff;
+ reg |= (data << 16);
+ }
+ else
+ {
+ reg &= 0xffff0000;
+ reg |= data;
+ }
+
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ return SW_OK;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_LAN_PORT_GROUP == group)
+ {
+ if (id)
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L1_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L1_MODE, mode, data);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P3L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P2L0_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, P1L0_MODE, mode, data);
+ }
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(LED_PATTERN, M6_MODE, mode, data);
+ SW_SET_REG_BY_FIELD(LED_PATTERN, M5_MODE, mode, data);
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, LED_PATTERN, 0,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ a_uint32_t data = 0, reg, tmp;
+ a_uint32_t addr;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (group >= LED_GROUP_BUTT)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (id > MAX_LED_PATTERN_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((LED_MAC_PORT_GROUP == group) && (0 != id))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ aos_mem_zero(pattern, sizeof(led_ctrl_pattern_t));
+
+ if (LED_MAC_PORT_GROUP == group)
+ {
+ addr = LED_PATTERN_ADDR + 8;
+ }
+ else
+ {
+ addr = LED_PATTERN_ADDR + (id << 2);
+ }
+
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (LED_WAN_PORT_GROUP == group)
+ {
+ data = (reg >> 16) & 0xffff;
+ }
+ else
+ {
+ data = reg & 0xffff;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, PATTERN_EN, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_OFF;
+ }
+ else if (1 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_BLINK;
+ }
+ else if (2 == tmp)
+ {
+ pattern->mode = LED_ALWAYS_ON;
+ }
+ else
+ {
+ pattern->mode = LED_PATTERN_MAP_EN;
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FULL_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, HALF_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, POWERON_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, GE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, FE_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, ETH_LIGHT_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, COL_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, RX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, TX_BLINK_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, LINKUP_OVER_EN, tmp, data);
+ if (1 == tmp)
+ {
+ pattern->map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ SW_GET_FIELD_BY_REG(LED_CTRL, BLINK_FREQ, tmp, data);
+ if (0 == tmp)
+ {
+ pattern->freq = LED_BLINK_2HZ;
+ }
+ else if (1 == tmp)
+ {
+ pattern->freq = LED_BLINK_4HZ;
+ }
+ else if (2 == tmp)
+ {
+ pattern->freq = LED_BLINK_8HZ;
+ }
+ else
+ {
+ pattern->freq = LED_BLINK_TXRX;
+ }
+
+ return SW_OK;
+}
+
+/**
+* @brief Set led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[in] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_led_ctrl_pattern_set(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_led_ctrl_pattern_set(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+* @brief Get led control pattern on a particular device.
+* @param[in] dev_id device id
+* @param[in] group pattern group, lan or wan
+* @param[in] id pattern id
+* @param[out] pattern led control pattern
+* @return SW_OK or error code
+*/
+HSL_LOCAL sw_error_t
+shiva_led_ctrl_pattern_get(a_uint32_t dev_id, led_pattern_group_t group,
+ led_pattern_id_t id, led_ctrl_pattern_t * pattern)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_led_ctrl_pattern_get(dev_id, group, id, pattern);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_led_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->led_ctrl_pattern_set = shiva_led_ctrl_pattern_set;
+ p_api->led_ctrl_pattern_get = shiva_led_ctrl_pattern_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_mib.c b/src/hsl/shiva/shiva_mib.c
new file mode 100644
index 0000000..b1adf83
--- /dev/null
+++ b/src/hsl/shiva/shiva_mib.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_mib SHIVA_MIB
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mib.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ a_uint32_t val;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_OUT_OF_RANGE;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBROAD, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXPAUSE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMULTI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFCSERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFcsErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXALLIGNERR, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxAllignErr = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXRUNT, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxRunt = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXFRAGMENT, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxFragment = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Rx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXTOOLONG, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxTooLong = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXGOODBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxGoodByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXBADBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxBadByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_RXOVERFLOW, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->RxOverFlow = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_FILTERED, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Filtered = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBROAD, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxBroad = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXPAUSE, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxPause = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTI, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMulti = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXUNDERRUN, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxUnderRun = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX64BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx64Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX128BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx128Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX256BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx256Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX512BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx512Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1024BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1024Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TX1518BYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->Tx1518Byte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMAXBYTE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMaxByte = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXOVERSIZE, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxOverSize = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_LO, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_lo = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXBYTE_HI, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxByte_hi = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXCOLLISION, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxCollision = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXABORTCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxAbortCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXMULTICOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxMultiCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXSINGALCOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxSingalCol = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXEXCDEFER, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxExcDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXDEFER, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxDefer = val;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, MIB_TXLATECOL, port_id,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ mib_info->TxLateCol = val;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, MIB_FUNC, 0, MIB_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Get mib infomation on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mib_info mib infomation
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_get_mib_info(a_uint32_t dev_id, fal_port_t port_id,
+ fal_mib_info_t * mib_info)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_get_mib_info(dev_id, port_id, mib_info);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mib_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mib_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mib status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mib_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mib_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_mib_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->get_mib_info = shiva_get_mib_info;
+ p_api->mib_status_set = shiva_mib_status_set;
+ p_api->mib_status_get = shiva_mib_status_get;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_mirror.c b/src/hsl/shiva/shiva_mirror.c
new file mode 100644
index 0000000..3ad1aff
--- /dev/null
+++ b/src/hsl/shiva/shiva_mirror.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_mirror SHIVA_MIRROR
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_mirror.h"
+#include "shiva_reg.h"
+
+static sw_error_t
+_shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = port_id;
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, MIRROR_PORT_NUM,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *port_id = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, ING_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_MIRROR_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @details Comments:
+ * The analysis port works for both ingress and egress mirror.
+ * @brief Set mirror analyzer port on particular a device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_analysis_port_set(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_analysis_port_set(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mirror analysis port on particular a device.
+ * @param[in] dev_id device id
+ * @param[out] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_analysis_port_get(a_uint32_t dev_id, fal_port_t * port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_analysis_port_get(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_in_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_port_in_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress mirror status on particular a port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_in_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_port_in_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_eg_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_port_eg_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get egress mirror status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_mirr_port_eg_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_mirr_port_eg_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_mirr_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->mirr_analysis_port_set = shiva_mirr_analysis_port_set;
+ p_api->mirr_analysis_port_get = shiva_mirr_analysis_port_get;
+ p_api->mirr_port_in_set = shiva_mirr_port_in_set;
+ p_api->mirr_port_in_get = shiva_mirr_port_in_get;
+ p_api->mirr_port_eg_set = shiva_mirr_port_eg_set;
+ p_api->mirr_port_eg_get = shiva_mirr_port_eg_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_misc.c b/src/hsl/shiva/shiva_misc.c
new file mode 100644
index 0000000..076b8fb
--- /dev/null
+++ b/src/hsl/shiva/shiva_misc.c
@@ -0,0 +1,1736 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_misc SHIVA_MISC
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_misc.h"
+#include "shiva_reg.h"
+
+#define SHIVA_MAX_FRMAE_SIZE 9216
+
+static sw_error_t
+_shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (SHIVA_MAX_FRMAE_SIZE < size)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ data = size;
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, GLOBAL_CTL, 0, MAX_FRAME_SIZE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *size = data;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 0, data);
+ }
+ else if (FAL_MAC_DROP == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 1, data);
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ SW_SET_REG_BY_FIELD(PORT_CTL, PORT_LOCK_EN, 1, data);
+ SW_SET_REG_BY_FIELD(PORT_CTL, LOCK_DROP_EN, 0, data);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+ a_uint32_t port_lock_en, port_drop_en;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_CTL, port_id, (a_uint8_t *) (&data),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_CTL, PORT_LOCK_EN, port_lock_en, data);
+ SW_GET_FIELD_BY_REG(PORT_CTL, LOCK_DROP_EN, port_drop_en, data);
+
+ if (1 == port_lock_en)
+ {
+ if (1 == port_drop_en)
+ {
+ *action = FAL_MAC_DROP;
+ }
+ else
+ {
+ *action = FAL_MAC_RDT_TO_CPU;
+ }
+ }
+ else
+ {
+ *action = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, UNI_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, MUL_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ data &= (~((a_uint32_t)0x1 << port_id));
+ }
+ else if (A_FALSE == enable)
+ {
+ data |= (0x1 << port_id);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t reg, field;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, FLOOD_MASK, 0, BC_FLOOD_DP,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ field = reg & (0x1 << port_id);
+ if (field)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, CPU_PORT, 0, CPU_PORT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_FRWRD == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_RDT_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_FRWRD;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, PPPOE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, DHCP_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, ARP_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_MAC_CPY_TO_CPU == cmd)
+ {
+ val = 0;
+ }
+ else if (FAL_MAC_RDT_TO_CPU == cmd)
+ {
+ val = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, EAPOL_CMD,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *cmd = FAL_MAC_CPY_TO_CPU;
+ }
+ else
+ {
+ *cmd = FAL_MAC_RDT_TO_CPU;
+ }
+
+ return SW_OK;
+}
+
+#define SHIVA_MAX_PPPOE_SESSION 16
+#define SHIVA_MAX_SESSION_ID 0xffff
+
+static sw_error_t
+_shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, cmd, id, entry_idx = 0xffff;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_id > SHIVA_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (!valid)
+ {
+ entry_idx = i;
+ }
+ else if (id == session_id)
+ {
+ return SW_ALREADY_EXIST;
+ }
+ }
+
+ if (0xffff == entry_idx)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 1, reg);
+ if (A_TRUE == strip_hdr)
+ {
+ cmd = 1;
+ }
+ else if (A_FALSE == strip_hdr)
+ {
+ cmd = 0;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, cmd, reg);
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, session_id, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, entry_idx,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_id > SHIVA_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (valid && (id == session_id))
+ {
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, ENTRY_VALID, 0, reg);
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, STRIP_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PPPOE_SESSION, SEESION_ID, 0, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+ sw_error_t rv;
+ a_uint32_t reg, i, valid, cmd, id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (session_id > SHIVA_MAX_SESSION_ID)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (i = 0; i < SHIVA_MAX_PPPOE_SESSION; i++)
+ {
+ HSL_REG_ENTRY_GET(rv, dev_id, PPPOE_SESSION, i,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, ENTRY_VALID, valid, reg);
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, SEESION_ID, id, reg);
+
+ if (valid && (id == session_id))
+ {
+ SW_GET_FIELD_BY_REG(PPPOE_SESSION, STRIP_EN, cmd, reg);
+ if (cmd)
+ {
+ *strip_hdr = A_TRUE;
+ }
+ else
+ {
+ *strip_hdr = A_FALSE;
+ }
+ return SW_OK;
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EAPOL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, 0, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QM_CTL, 0, RIP_CPY_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t data, intr;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE == enable)
+ {
+ if (FAL_LOOP_CHECK_1MS == time)
+ {
+ data = 1;
+ }
+ else if (FAL_LOOP_CHECK_10MS == time)
+ {
+ data = 2;
+ }
+ else if (FAL_LOOP_CHECK_100MS == time)
+ {
+ data = 3;
+ }
+ else if (FAL_LOOP_CHECK_500MS == time)
+ {
+ data = 4;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ intr = 1;
+ }
+ else
+ {
+ data = 0;
+ intr = 0;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, GLOBAL_INT_MASK, 0, GLBM_LOOP_CHECK,
+ (a_uint8_t *) (&intr), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0, LOOP_CHK_TIME,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *enable = A_TRUE;
+ *time = FAL_LOOP_CHECK_1MS;
+ if (0 == data)
+ {
+ *enable = A_FALSE;
+ }
+ else if (2 == data)
+ {
+ *time = FAL_LOOP_CHECK_10MS;
+ }
+ else if (3 == data)
+ {
+ *time = FAL_LOOP_CHECK_100MS;
+ }
+ else if (4 == data)
+ {
+ *time = FAL_LOOP_CHECK_500MS;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg, data;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, LOOP_CHECK, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(LOOP_CHECK, NEW_PORT, data, reg);
+ *new_port_id = data;
+
+ SW_GET_FIELD_BY_REG(LOOP_CHECK, OLD_PORT, data, reg);
+ *old_port_id = data;
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_arp_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_arp_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max frame size which device can received on a particular device.
+ * @details Comments:
+ * The granularity of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[in] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_frame_max_size_set(a_uint32_t dev_id, a_uint32_t size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_frame_max_size_set(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max frame size which device can received on a particular device.
+ * @details Comments:
+ * The unit of packets size is byte.
+ * @param[in] dev_id device id
+ * @param[out] size packet size
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_frame_max_size_get(a_uint32_t dev_id, a_uint32_t *size)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_frame_max_size_get(dev_id, size);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set forwarding command for packets which source address is unknown on a particular port.
+ * @details Comments:
+ * Particular device may only support parts of forwarding commands.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_sa_cmd_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_sa_cmd_set(dev_id, port_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get forwarding command for packets which source address is unknown on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_sa_cmd_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_fwd_cmd_t * action)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_sa_cmd_get(dev_id, port_id, action);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown unicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown unicast packets filter on one port then unknown
+ * unicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_uc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_uc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flooding status of unknown unicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_uc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_uc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of unknown multicast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_mc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_mc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of unknown multicast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_unk_mc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_unk_mc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flooding status of broadcast packets on a particular port.
+ * @details Comments:
+ * If enable unknown multicast packets filter on one port then unknown
+ * multicast packets can't flood out from this port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_bc_filter_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_bc_filter_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/** @brief Get flooding status of broadcast packets on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_bc_filter_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_bc_filter_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cpu_port_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cpu_port_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cpu port status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cpu_port_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cpu_port_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling pppoe packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set pppoe packets hardware acknowledgement status on particular device.
+ * @details comments:
+ * Particular device may only support parts of pppoe packets.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get pppoe packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_status_get(a_uint32_t dev_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set dhcp packets hardware acknowledgement status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_dhcp_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_dhcp_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get dhcp packets hardware acknowledgement status on particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_dhcp_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_dhcp_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set arp packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling arp packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_arp_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get arp packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_arp_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_arp_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets forwarding command on a particular device.
+ * @details comments:
+ * Particular device may only support parts of forwarding commands.
+ * Ihis operation will take effect only after enabling eapol packets
+ * hardware acknowledgement
+ * @param[in] dev_id device id
+ * @param[in] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_cmd_set(a_uint32_t dev_id, fal_fwd_cmd_t cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_eapol_cmd_set(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets forwarding command on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] cmd forwarding command
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_cmd_get(a_uint32_t dev_id, fal_fwd_cmd_t * cmd)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_eapol_cmd_get(dev_id, cmd);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a pppoe session entry to a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[in] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_add(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t strip_hdr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_session_add(dev_id, session_id, strip_hdr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_del(a_uint32_t dev_id, a_uint32_t session_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_session_del(dev_id, session_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a pppoe session entry from a particular device.
+ * @param[in] dev_id device id
+ * @param[in] session_id pppoe session id
+ * @param[out] strip_hdr strip or not strip pppoe header
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_pppoe_session_get(a_uint32_t dev_id, a_uint32_t session_id, a_bool_t * strip_hdr)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_pppoe_session_get(dev_id, session_id, strip_hdr);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_status_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_eapol_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get eapol packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_eapol_status_get(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_eapol_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_ripv1_status_set(a_uint32_t dev_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_ripv1_status_set(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get rip v1 packets hardware acknowledgement status on a particular port.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_ripv1_status_get(a_uint32_t dev_id, a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_ripv1_status_get(dev_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set loopback checking status on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_status_set(a_uint32_t dev_id, fal_loop_check_time_t time, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_loop_check_status_set(dev_id, time, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get loopback checking status on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_status_get(a_uint32_t dev_id, fal_loop_check_time_t * time, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_loop_check_status_get(dev_id, time, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get loopback checking information on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] old_port_id
+ * @param[in] new_port_id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_loop_check_info_get(a_uint32_t dev_id, a_uint32_t * old_port_id, a_uint32_t * new_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_loop_check_info_get(dev_id, old_port_id, new_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_misc_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->arp_status_set = shiva_arp_status_set;
+ p_api->arp_status_get = shiva_arp_status_get;
+ p_api->frame_max_size_set = shiva_frame_max_size_set;
+ p_api->frame_max_size_get = shiva_frame_max_size_get;
+ p_api->port_unk_sa_cmd_set = shiva_port_unk_sa_cmd_set;
+ p_api->port_unk_sa_cmd_get = shiva_port_unk_sa_cmd_get;
+ p_api->port_unk_uc_filter_set = shiva_port_unk_uc_filter_set;
+ p_api->port_unk_uc_filter_get = shiva_port_unk_uc_filter_get;
+ p_api->port_unk_mc_filter_set = shiva_port_unk_mc_filter_set;
+ p_api->port_unk_mc_filter_get = shiva_port_unk_mc_filter_get;
+ p_api->port_bc_filter_set = shiva_port_bc_filter_set;
+ p_api->port_bc_filter_get = shiva_port_bc_filter_get;
+ p_api->cpu_port_status_set = shiva_cpu_port_status_set;
+ p_api->cpu_port_status_get = shiva_cpu_port_status_get;
+ p_api->pppoe_cmd_set = shiva_pppoe_cmd_set;
+ p_api->pppoe_cmd_get = shiva_pppoe_cmd_get;
+ p_api->pppoe_status_set = shiva_pppoe_status_set;
+ p_api->pppoe_status_get = shiva_pppoe_status_get;
+ p_api->port_dhcp_set = shiva_port_dhcp_set;
+ p_api->port_dhcp_get = shiva_port_dhcp_get;
+ p_api->arp_cmd_set = shiva_arp_cmd_set;
+ p_api->arp_cmd_get = shiva_arp_cmd_get;
+ p_api->eapol_cmd_set = shiva_eapol_cmd_set;
+ p_api->eapol_cmd_get = shiva_eapol_cmd_get;
+ p_api->pppoe_session_add = shiva_pppoe_session_add;
+ p_api->pppoe_session_del = shiva_pppoe_session_del;
+ p_api->pppoe_session_get = shiva_pppoe_session_get;
+ p_api->eapol_status_set = shiva_eapol_status_set;
+ p_api->eapol_status_get = shiva_eapol_status_get;
+ p_api->ripv1_status_set = shiva_ripv1_status_set;
+ p_api->ripv1_status_get = shiva_ripv1_status_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_port_ctrl.c b/src/hsl/shiva/shiva_port_ctrl.c
new file mode 100644
index 0000000..5f6a8d3
--- /dev/null
+++ b/src/hsl/shiva/shiva_port_ctrl.c
@@ -0,0 +1,984 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_port_ctrl SHIVA_PORT_CONTROL
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_port_ctrl.h"
+#include "shiva_reg.h"
+#include "f2_phy.h"
+
+static sw_error_t
+_shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+ a_uint32_t reg_save = 0;
+ a_uint32_t reg_val = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DUPLEX_BUTT <= duplex)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ //save reg value
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ reg_save = reg_val;
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, 0, reg_val);
+
+ //set mac be config by sw and turn off RX TX MAC_EN
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_val), sizeof (a_uint32_t));
+
+ rv = f2_phy_set_duplex(dev_id, phy_id, duplex);
+
+ //retore reg value
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®_save), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_duplex(dev_id, phy_id, pduplex);
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_SPEED_100 < speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = f2_phy_set_speed(dev_id, phy_id, speed);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_speed(dev_id, phy_id, pspeed);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ a_uint32_t phy_id;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *status = f2_phy_autoneg_status(dev_id, phy_id);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_enable_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_restart_autoneg(dev_id, phy_id);
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ *autoadv = 0;
+ rv = f2_phy_get_autoneg_adv(dev_id, phy_id, autoadv);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, HEAD_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val, force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force)
+ {
+ /* flow control isn't in force mode so can't set */
+ return SW_DISABLE;
+ }
+
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t tx, rx, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, RX_FLOW_EN, rx, reg);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, TX_FLOW_EN, tx, reg);
+
+ if (1 == rx)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (force != (a_uint32_t) enable)
+ {
+ return SW_OK;
+ }
+
+ if (A_TRUE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, 0, reg);
+ SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, 0, reg);
+ }
+ else if (A_FALSE == enable)
+ {
+ SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, 0, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t force, reg;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, force, reg);
+ if (0 == force)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_powersave(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_set_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_get_hibernate(dev_id, phy_id, enable);
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+ a_uint32_t phy_id = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_PHY))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = f2_phy_cdt(dev_id, phy_id, mdi_pair, cable_status, cable_len);
+
+ return rv;
+}
+
+/**
+ * @brief Set duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_duplex_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t duplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_duplex_set(dev_id, port_id, duplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get duplex mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] duplex duplex mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_duplex_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_duplex_t * pduplex)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_duplex_get(dev_id, port_id, pduplex);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_speed_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t speed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_speed_set(dev_id, port_id, speed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get speed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed port speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_speed_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_port_speed_t * pspeed)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_speed_get(dev_id, port_id, pspeed);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] status A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * status)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_autoneg_status_get(dev_id, port_id, status);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Enable auto negotiation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_enable(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_autoneg_enable(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Restart auto negotiation procedule on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_restart(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_autoneg_restart(dev_id, port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set auto negotiation advtisement ability on a particular port.
+ * @details Comments:
+ * auto negotiation advtisement ability is defined by macro such as
+ * FAL_PHY_ADV_10T_HD, FAL_PHY_ADV_PAUSE...
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_adv_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_autoneg_adv_set(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get auto negotiation advtisement ability on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] autoadv auto negotiation advtisement ability bit map
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_autoneg_adv_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * autoadv)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_autoneg_adv_get(dev_id, port_id, autoadv);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hdr_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_hdr_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get status of Atheros header packets parsed on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hdr_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_hdr_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_flowctrl_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_flowctrl_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_forcemode_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_flowctrl_forcemode_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get flow control force mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_flowctrl_forcemode_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_flowctrl_forcemode_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_powersave_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_powersave_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get powersaving status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_powersave_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_powersave_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hibernate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_hibernate_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get hibernate status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_hibernate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t *enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_hibernate_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Run cable diagnostic test on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mdi_pair mdi pair id
+ * @param[out] cable_status cable status
+ * @param[out] cable_len cable len
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_cdt(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
+ fal_cable_status_t *cable_status, a_uint32_t *cable_len)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_cdt(dev_id, port_id, mdi_pair, cable_status, cable_len);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_port_ctrl_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_duplex_get = shiva_port_duplex_get;
+ p_api->port_duplex_set = shiva_port_duplex_set;
+ p_api->port_speed_get = shiva_port_speed_get;
+ p_api->port_speed_set = shiva_port_speed_set;
+ p_api->port_autoneg_status_get = shiva_port_autoneg_status_get;
+ p_api->port_autoneg_enable = shiva_port_autoneg_enable;
+ p_api->port_autoneg_restart = shiva_port_autoneg_restart;
+ p_api->port_autoneg_adv_get = shiva_port_autoneg_adv_get;
+ p_api->port_autoneg_adv_set = shiva_port_autoneg_adv_set;
+ p_api->port_hdr_status_set = shiva_port_hdr_status_set;
+ p_api->port_hdr_status_get = shiva_port_hdr_status_get;
+ p_api->port_flowctrl_set = shiva_port_flowctrl_set;
+ p_api->port_flowctrl_get = shiva_port_flowctrl_get;
+ p_api->port_flowctrl_forcemode_set = shiva_port_flowctrl_forcemode_set;
+ p_api->port_flowctrl_forcemode_get = shiva_port_flowctrl_forcemode_get;
+ p_api->port_powersave_set = shiva_port_powersave_set;
+ p_api->port_powersave_get = shiva_port_powersave_get;
+ p_api->port_hibernate_set = shiva_port_hibernate_set;
+ p_api->port_hibernate_get = shiva_port_hibernate_get;
+ p_api->port_cdt = shiva_port_cdt;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_portvlan.c b/src/hsl/shiva/shiva_portvlan.c
new file mode 100644
index 0000000..49c1de1
--- /dev/null
+++ b/src/hsl/shiva/shiva_portvlan.c
@@ -0,0 +1,1849 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_port_vlan SHIVA_PORT_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_portvlan.h"
+#include "shiva_reg.h"
+
+#define MAX_VLAN_ID 4095
+#define SHIVA_MAX_VLAN_TRANS 16
+#define SHIVA_VLAN_TRANS_ADDR 0x59000
+
+static sw_error_t
+_shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_1Q_MODE_BUTT] = { 0, 3, 2, 1 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_1Q_MODE_BUTT <= port_1qmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val[port_1qmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1qmode_t retval[4] = { FAL_1Q_DISABLE, FAL_1Q_FALLBACK,
+ FAL_1Q_CHECK, FAL_1Q_SECURE
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_1qmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, DOT1Q_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_1qmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+static sw_error_t
+_shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_EG_MODE_BUTT] = { 0, 1, 2, 3};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_EG_MODE_BUTT <= port_egvlanmode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val[port_egvlanmode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_1q_egmode_t retval[4] = { FAL_EG_UNMODIFIED, FAL_EG_UNTAGGED,
+ FAL_EG_TAGGED, FAL_EG_HYBRID
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(pport_egvlanmode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, EG_VLAN_MODE,
+ (a_uint8_t *) (®val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *pport_egvlanmode = retval[regval & 0x3];
+
+ return SW_OK;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval |= (0x1UL << mem_port_id);
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, mem_port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ regval &= (~(0x1UL << mem_port_id));
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ return rv;
+
+}
+
+static sw_error_t
+_shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_FALSE ==
+ hsl_mports_prop_check(dev_id, mem_port_map, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) (&mem_port_map),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *mem_port_map = 0;
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PORT_VID_MEM, (a_uint8_t *) mem_port_map,
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ FORCE_DEF_VID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ FORCE_PVLAN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ val = tpid;
+ HSL_REG_FIELD_SET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, SERVICE_TAG, 0,
+ TAG_VALUE, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *tpid = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval[FAL_INVLAN_MODE_BUTT] = { 0, 1, 2};
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_INVLAN_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val[mode]),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t regval = 0;
+ fal_pt_invlan_mode_t retval[FAL_INVLAN_MODE_BUTT] = { FAL_INVLAN_ADMIT_ALL,
+ FAL_INVLAN_ADMIT_TAGGED, FAL_INVLAN_ADMIT_UNTAGGED
+ };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_FALSE == hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(mode);
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id, IN_VLAN_MODE,
+ (a_uint8_t *) (®val),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (regval >= 3)
+ {
+ return SW_FAIL;
+ }
+ *mode = retval[regval & 0x3];
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ TLS_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ TLS_EN, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ PRI_PROPAGATION, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((0 == vid) || (vid > MAX_VLAN_ID))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ DEF_SVID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ DEF_SVID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((0 == vid) || (vid > MAX_VLAN_ID))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = vid;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ DEF_CVID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ DEF_CVID, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+
+ *vid = val & 0xfff;
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_VLAN_PROPAGATION_DISABLE == mode)
+ {
+ p = 0;
+ c = 0;
+ }
+ else if (FAL_VLAN_PROPAGATION_CLONE == mode)
+ {
+ p = 1;
+ c = 1;
+ }
+ else if (FAL_VLAN_PROPAGATION_REPLACE == mode)
+ {
+ p = 1;
+ c = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(PORT_DOT1AD, PROPAGATION_EN, p, reg);
+ SW_SET_REG_BY_FIELD(PORT_DOT1AD, CLONE, c, reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT_DOT1AD, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t reg, p, c;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT_DOT1AD, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(PORT_DOT1AD, PROPAGATION_EN, p, reg);
+ SW_GET_FIELD_BY_REG(PORT_DOT1AD, CLONE, c, reg);
+
+ if (p)
+ {
+ if (c)
+ {
+ *mode = FAL_VLAN_PROPAGATION_CLONE;
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_REPLACE;
+ }
+ }
+ else
+ {
+ *mode = FAL_VLAN_PROPAGATION_DISABLE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_trans_read(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t * pbmp, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, table[2];
+
+ addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+ /* get vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ if (0x1 & (table[1] >> 4))
+ {
+ entry->o_vid = table[0] & 0xfff;
+ entry->s_vid = (table[0] >> 12) & 0xfff;
+ entry->c_vid = ((table[0] >> 24) & 0xff) | ((table[1] & 0xf) << 8);
+ entry->bi_dir = (~(table[1] >> 5)) & 0x1;
+ *pbmp = (table[1] >> 6) & 0x7f;
+ return SW_OK;
+ }
+ else
+ {
+ return SW_EMPTY;
+ }
+}
+
+static sw_error_t
+_shiva_vlan_trans_write(a_uint32_t dev_id, a_uint32_t entry_idx, fal_pbmp_t pbmp, fal_vlan_trans_entry_t entry)
+{
+ sw_error_t rv;
+ a_uint32_t i, addr, table[2] = {0};
+
+ addr = SHIVA_VLAN_TRANS_ADDR + (entry_idx << 3);
+
+ if (0 != pbmp)
+ {
+ table[0] = entry.o_vid & 0xfff;
+ table[0] |= ((entry.s_vid & 0xfff) << 12);
+ table[0] |= ((entry.c_vid & 0xff) << 24);
+ table[1] = (entry.c_vid >> 8) & 0xf;
+ table[1] |= (0x1 << 4);
+ table[1] |= (((~(entry.bi_dir))& 0x1) << 5);
+ table[1] |= (pbmp << 6);
+ }
+
+ /* set vlan trans table */
+ for (i = 0; i < 2; i++)
+ {
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr + (i << 2), sizeof (a_uint32_t),
+ (a_uint8_t *) (&(table[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = 0xffff, old_idx = 0xffff;
+ fal_vlan_trans_entry_t entry_temp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+ {
+ aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+ rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+ if (SW_EMPTY == rv)
+ {
+ entry_idx = idx;
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (!aos_mem_cmp(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t)))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ return SW_ALREADY_EXIST;
+ }
+ old_idx = idx;
+ break;
+ }
+ }
+
+ if (0xffff != old_idx)
+ {
+ t_pbmp |= (0x1 << port_id);
+ entry_idx = old_idx;
+ }
+ else if (0xffff != entry_idx)
+ {
+ t_pbmp = (0x1 << port_id);
+ aos_mem_copy(&entry_temp, entry, sizeof(fal_vlan_trans_entry_t));
+ }
+ else
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp);
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx, entry_idx = 0xffff;
+ fal_vlan_trans_entry_t entry_temp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+ {
+ aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+ rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if ((entry->o_vid == entry_temp.o_vid)
+ && (entry->bi_dir == entry_temp.bi_dir))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ entry_idx = idx;
+ break;
+ }
+ }
+ }
+
+ if (0xffff != entry_idx)
+ {
+ t_pbmp &= (~(0x1 << port_id));
+ }
+ else
+ {
+ return SW_NOT_FOUND;
+ }
+
+ return _shiva_vlan_trans_write(dev_id, entry_idx, t_pbmp, entry_temp);
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+ fal_pbmp_t t_pbmp;
+ a_uint32_t idx;
+ fal_vlan_trans_entry_t entry_temp;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (idx = 0; idx < SHIVA_MAX_VLAN_TRANS; idx++)
+ {
+ aos_mem_set(&entry_temp, 0, sizeof(fal_vlan_trans_entry_t));
+ rv = _shiva_vlan_trans_read(dev_id, idx, &t_pbmp, &entry_temp);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+ if ((entry->o_vid == entry_temp.o_vid)
+ && (entry->bi_dir == entry_temp.bi_dir))
+ {
+ if (SW_IS_PBMP_MEMBER(t_pbmp, port_id))
+ {
+ aos_mem_copy(entry, &entry_temp, sizeof(fal_vlan_trans_entry_t));
+ return SW_OK;
+ }
+ }
+ }
+
+ return SW_NOT_FOUND;
+}
+
+static sw_error_t
+_shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+ a_uint32_t index;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_t;
+ fal_pbmp_t pbmp_t;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((NULL == iterator) || (NULL == entry))
+ {
+ return SW_BAD_PTR;
+ }
+
+ if (SHIVA_MAX_VLAN_TRANS == *iterator)
+ {
+ return SW_NO_MORE;
+ }
+
+ if (SHIVA_MAX_VLAN_TRANS < *iterator)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ for (index = *iterator; index < SHIVA_MAX_VLAN_TRANS; index++)
+ {
+ rv = _shiva_vlan_trans_read(dev_id, index, &pbmp_t, &entry_t);
+ if (SW_EMPTY == rv)
+ {
+ continue;
+ }
+
+ if (SW_IS_PBMP_MEMBER(pbmp_t, port_id))
+ {
+ aos_mem_copy(entry, &entry_t, sizeof(fal_vlan_trans_entry_t));
+ break;
+ }
+ }
+
+ if (SHIVA_MAX_VLAN_TRANS == index)
+ {
+ return SW_NO_MORE;
+ }
+
+ *iterator = index + 1;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_QINQ_MODE_BUTT <= mode)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_STAG_MODE == mode)
+ {
+ stag = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ STAG_MODE, (a_uint8_t *) (&stag),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+ a_uint32_t stag = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_FIELD_GET(rv, dev_id, ADDR_TABLE_CTL, 0,
+ STAG_MODE, (a_uint8_t *) (&stag),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (stag)
+ {
+ *mode = FAL_QINQ_STAG_MODE;
+ }
+ else
+ {
+ *mode = FAL_QINQ_CTAG_MODE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_PORT_ROLE_BUTT <= role)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QINQ_CORE_PORT == role)
+ {
+ core = 1;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ COREP_EN, (a_uint8_t *) (&core),
+ sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+ a_uint32_t core = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_BASE_VLAN, port_id,
+ COREP_EN, (a_uint8_t *) (&core),
+ sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (core)
+ {
+ *role = FAL_QINQ_CORE_PORT;
+ }
+ else
+ {
+ *role = FAL_QINQ_EDGE_PORT;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_1qmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t port_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_1qmode_set(dev_id, port_id, port_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get 802.1q work mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_1qmode 802.1q work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_1qmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1qmode_t * pport_1qmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_1qmode_get(dev_id, port_id, pport_1qmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_egvlanmode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t port_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_egvlanmode_set(dev_id, port_id, port_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get packets transmitted out vlan tagged mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] port_egvlanmode packets transmitted out vlan tagged mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_egvlanmode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_1q_egmode_t * pport_egvlanmode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_egvlanmode_get(dev_id, port_id, pport_egvlanmode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_add(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_portvlan_member_add(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_id port member
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_del(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t mem_port_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_portvlan_member_del(dev_id, port_id, mem_port_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_update(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_portvlan_member_update(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get member of port based vlan on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mem_port_map port members
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_portvlan_member_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pbmp_t * mem_port_map)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_portvlan_member_get(dev_id, port_id, mem_port_map);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_default_vid_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_force_default_vid_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force default vlan id status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_default_vid_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_force_default_vid_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_portvlan_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_force_portvlan_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get force port based vlan status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_force_portvlan_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_force_portvlan_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_nestvlan_tpid_set(a_uint32_t dev_id, a_uint32_t tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_nestvlan_tpid_set(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get nest vlan tpid on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] tpid tag protocol identification
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_nestvlan_tpid_get(a_uint32_t dev_id, a_uint32_t *tpid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_nestvlan_tpid_get(dev_id, tpid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_invlan_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_invlan_mode_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get ingress vlan mode mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode ingress vlan mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_invlan_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_pt_invlan_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_invlan_mode_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_tls_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_tls_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get tls status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_tls_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_tls_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_pri_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_pri_propagation_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_pri_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_pri_propagation_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_svid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_default_svid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default s-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid s-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_svid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_default_svid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_cvid_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_default_cvid_set(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default c-vid on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] vid c-vid
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_default_cvid_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * vid)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_default_cvid_get(dev_id, port_id, vid);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_propagation_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_propagation_set(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get vlan propagation status on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] mode vlan propagation mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_propagation_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_vlan_propagation_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_propagation_get(dev_id, port_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Add a vlan translation entry to a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_add(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_trans_add(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_del(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_trans_del(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get a vlan translation entry from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_get(a_uint32_t dev_id, fal_port_t port_id, fal_vlan_trans_entry_t *entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_trans_get(dev_id, port_id, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Iterate all vlan translation entries from a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] iterator translation entry index if it's zero means get the first entry
+ * @param[out] iterator next valid translation entry index
+ * @param[out] entry vlan translation entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_vlan_trans_iterate(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * iterator, fal_vlan_trans_entry_t * entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_vlan_trans_iterate(dev_id, port_id, iterator, entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[in] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qinq_mode_set(a_uint32_t dev_id, fal_qinq_mode_t mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qinq_mode_set(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get switch qinq work mode on a particular device.
+ * @param[in] dev_id device id
+ * @param[out] mode qinq work mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qinq_mode_get(a_uint32_t dev_id, fal_qinq_mode_t * mode)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qinq_mode_get(dev_id, mode);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_qinq_role_set(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_qinq_role_set(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get qinq role on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] role port role
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_port_qinq_role_get(a_uint32_t dev_id, fal_port_t port_id, fal_qinq_port_role_t * role)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_port_qinq_role_get(dev_id, port_id, role);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_portvlan_init(a_uint32_t dev_id)
+{
+ a_uint32_t i;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry_init;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ aos_mem_set(&entry_init, 0, sizeof(fal_vlan_trans_entry_t));
+ entry_init.bi_dir = A_TRUE;
+
+ for (i = 0; i < SHIVA_MAX_VLAN_TRANS; i++)
+ {
+ rv = _shiva_vlan_trans_write(dev_id, i, 0, entry_init);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL (p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->port_1qmode_get = shiva_port_1qmode_get;
+ p_api->port_1qmode_set = shiva_port_1qmode_set;
+ p_api->port_egvlanmode_get = shiva_port_egvlanmode_get;
+ p_api->port_egvlanmode_set = shiva_port_egvlanmode_set;
+ p_api->portvlan_member_add = shiva_portvlan_member_add;
+ p_api->portvlan_member_del = shiva_portvlan_member_del;
+ p_api->portvlan_member_update = shiva_portvlan_member_update;
+ p_api->portvlan_member_get = shiva_portvlan_member_get;
+ p_api->port_force_default_vid_set = shiva_port_force_default_vid_set;
+ p_api->port_force_default_vid_get = shiva_port_force_default_vid_get;
+ p_api->port_force_portvlan_set = shiva_port_force_portvlan_set;
+ p_api->port_force_portvlan_get = shiva_port_force_portvlan_get;
+ p_api->nestvlan_tpid_set = shiva_nestvlan_tpid_set;
+ p_api->nestvlan_tpid_get = shiva_nestvlan_tpid_get;
+ p_api->port_invlan_mode_set = shiva_port_invlan_mode_set;
+ p_api->port_invlan_mode_get = shiva_port_invlan_mode_get;
+ p_api->port_tls_set = shiva_port_tls_set;
+ p_api->port_tls_get = shiva_port_tls_get;
+ p_api->port_pri_propagation_set = shiva_port_pri_propagation_set;
+ p_api->port_pri_propagation_get = shiva_port_pri_propagation_get;
+ p_api->port_default_svid_set = shiva_port_default_svid_set;
+ p_api->port_default_svid_get = shiva_port_default_svid_get;
+ p_api->port_default_cvid_set = shiva_port_default_cvid_set;
+ p_api->port_default_cvid_get = shiva_port_default_cvid_get;
+ p_api->port_vlan_propagation_set = shiva_port_vlan_propagation_set;
+ p_api->port_vlan_propagation_get = shiva_port_vlan_propagation_get;
+ p_api->port_vlan_trans_add = shiva_port_vlan_trans_add;
+ p_api->port_vlan_trans_del = shiva_port_vlan_trans_del;
+ p_api->port_vlan_trans_get = shiva_port_vlan_trans_get;
+ p_api->qinq_mode_set = shiva_qinq_mode_set;
+ p_api->qinq_mode_get = shiva_qinq_mode_get;
+ p_api->port_qinq_role_set = shiva_port_qinq_role_set;
+ p_api->port_qinq_role_get = shiva_port_qinq_role_get;
+ p_api->port_vlan_trans_iterate = shiva_port_vlan_trans_iterate;
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_qos.c b/src/hsl/shiva/shiva_qos.c
new file mode 100644
index 0000000..edc9105
--- /dev/null
+++ b/src/hsl/shiva/shiva_qos.c
@@ -0,0 +1,1274 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_qos SHIVA_QOS
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_qos.h"
+#include "shiva_reg.h"
+
+#define SHIVA_QOS_QUEUE_TX_BUFFER_MAX 60
+#define SHIVA_QOS_PORT_TX_BUFFER_MAX 252
+#define SHIVA_QOS_PORT_RX_BUFFER_MAX 60
+
+//#define SHIVA_MIN_QOS_MODE_PRI 0
+#define SHIVA_MAX_QOS_MODE_PRI 3
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (SHIVA_QOS_QUEUE_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE0_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE1_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE2_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, QUEUE3_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (SHIVA_QOS_PORT_TX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_DESC_NR,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (SHIVA_QOS_PORT_RX_BUFFER_MAX < *number)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = *number / 4;
+ *number = val << 2;
+ HSL_REG_FIELD_SET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ a_uint32_t val = 0;
+ sw_error_t rv;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, QUEUE_CTL, port_id, PORT_IN_DESC_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *number = val << 2;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, TAG_PRI_MAPPING_OFFSET, 2,
+ (a_uint16_t) (up << 1), (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+ hsl_dev_t *p_dev = NULL;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_NULL(p_dev = hsl_dev_ptr_get(dev_id));
+ if (p_dev->nr_queue <= queue)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp >> 4) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ val = queue;
+ HSL_REG_FIELD_GEN_SET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t offsetaddr;
+ a_uint16_t fieldoffset;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_DSCP_MAX < dscp)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ offsetaddr = (dscp / 16) << 2;
+ fieldoffset = (dscp & 0xf) << 1;
+
+ HSL_REG_FIELD_GEN_GET(rv, dev_id, (IP_PRI_MAPPING_OFFSET + offsetaddr),
+ 2, fieldoffset, (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *queue = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ val = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, DA_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, VLAN_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, IP_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, PRI_CTL, port_id, PORT_PRI_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (SHIVA_MAX_QOS_MODE_PRI < pri)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, DA_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, VLAN_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, IP_PRI_SEL, pri, val);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_SET_REG_BY_FIELD(PRI_CTL, PORT_PRI_SEL, pri, val);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_ENTRY_SET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&val),
+ sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+ a_uint32_t entry, f_val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, PRI_CTL, port_id, (a_uint8_t *) (&entry),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (FAL_QOS_DA_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, DA_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_UP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, VLAN_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_DSCP_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, IP_PRI_SEL, f_val, entry);
+ }
+ else if (FAL_QOS_PORT_MODE == mode)
+ {
+ SW_GET_FIELD_BY_REG(PRI_CTL, PORT_PRI_SEL, f_val, entry);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ *pri = f_val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_DOT1P_MAX < up)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ val = up;
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_DOT1AD, port_id, ING_PRI,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ *up = val;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t reg, val, w[4] = {0};
+ a_int32_t i, _index;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SCH_SP_MODE == mode)
+ {
+ val = 0;
+ _index = -1;
+ }
+ else if (FAL_SCH_WRR_MODE == mode)
+ {
+ val = 3;
+ _index = 3;
+ }
+ else if (FAL_SCH_MIX_MODE == mode)
+ {
+ val = 1;
+ _index = 2;
+ }
+ else if (FAL_SCH_MIX_PLUS_MODE == mode)
+ {
+ val = 2;
+ _index = 1;
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ for (i = _index; i >= 0; i--)
+ {
+ if (weight[i] > 0x1f)
+ {
+ return SW_BAD_PARAM;
+ }
+ w[i] = weight[i];
+ }
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (®),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_SET_REG_BY_FIELD(WRR_CTRL, SCH_MODE, val, reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q3_W, w[3], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q2_W, w[2], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q1_W, w[1], reg);
+ SW_SET_REG_BY_FIELD(WRR_CTRL, Q0_W, w[0], reg);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, WRR_CTRL, port_id,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+ a_uint32_t val, sch, w[4], i;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, WRR_CTRL, port_id, (a_uint32_t *) (&val),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ SW_GET_FIELD_BY_REG(WRR_CTRL, SCH_MODE, sch, val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q3_W, w[3], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q2_W, w[2], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q1_W, w[1], val);
+ SW_GET_FIELD_BY_REG(WRR_CTRL, Q0_W, w[0], val);
+
+ if (0 == sch)
+ {
+ *mode = FAL_SCH_SP_MODE;
+ }
+ else if (1 == sch)
+ {
+ *mode = FAL_SCH_MIX_MODE;
+ }
+ else if (2 == sch)
+ {
+ *mode = FAL_SCH_MIX_PLUS_MODE;
+ }
+ else
+ {
+ *mode = FAL_SCH_WRR_MODE;
+ }
+
+ for (i = 0; i < 4; i++)
+ {
+ weight[i] = w[i];
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting queue on one particular port.
+ * @details Comments:
+ * If enable queue tx buffer on one port that means each queue of this port
+ * will have fixed number buffers when transmitting packets. Otherwise they
+ * share the whole buffers with other queues in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_queue_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting queue on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_queue_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set buffer aggsinment status of transmitting port on one particular port.
+ * @details Comments:
+ If enable tx buffer on one port that means this port will have fixed
+ number buffers when transmitting packets. Otherwise they will
+ share the whole buffers with other ports in device.
+ * function will return actual buffer numbers in hardware.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_status_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_tx_buf_status_set(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get buffer aggsinment status of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_status_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_tx_buf_status_get(dev_id, port_id, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting queue on one particular port.
+ * @details Comments:
+ The step of buffer number in SHIVA is 4, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for queue is 4 to 60.
+ * share the whole buffers with other ports in device.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_queue_tx_buf_nr_set(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting queue on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_queue_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_queue_tx_buf_nr_get(dev_id, port_id, queue_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of transmitting port on one particular port.
+ * @details Comments:
+ The step of buffer number in SHIVA is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for transmitting port is 4 to 124.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_tx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of transmitting port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_tx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_tx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set max occupied buffer number of receiving port on one particular port.
+ * @details Comments:
+ The step of buffer number in SHIVA is four, function will return actual
+ buffer numbers in hardware.
+ The buffer number range for receiving port is 4 to 60.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_rx_buf_nr_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_rx_buf_nr_set(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get max occupied buffer number of receiving port on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] number buffer number
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_rx_buf_nr_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * number)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_rx_buf_nr_get(dev_id, port_id, number);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_up_queue_set(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cosmap_up_queue_set(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get user priority to mapping on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dot1p 802.1p
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_up_queue_get(a_uint32_t dev_id, a_uint32_t up,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cosmap_up_queue_get(dev_id, up, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[in] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_dscp_queue_set(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cosmap_dscp_queue_set(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get cos map dscp_2_queue item on one particular device.
+ * @param[in] dev_id device id
+ * @param[in] dscp dscp
+ * @param[out] queue queue id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_cosmap_dscp_queue_get(a_uint32_t dev_id, a_uint32_t dscp,
+ fal_queue_t * queue)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_cosmap_dscp_queue_get(dev_id, dscp, queue);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_mode_set(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port qos mode on a particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] enable A_TRUE of A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_mode_get(dev_id, port_id, mode, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set priority of one particular qos mode on one particular port.
+ * @details Comments:
+ If the priority of a mode is more small then the priority is more high.
+ Differnet mode should have differnet priority.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[in] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_mode_pri_set(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get priority of one particular qos mode on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] mode qos mode
+ * @param[out] pri priority of one particular qos mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_qos_mode_t mode, a_uint32_t * pri)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_mode_pri_get(dev_id, port_id, mode, pri);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_default_up_set(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get default user priority on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] up 802.1p
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * up)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_default_up_get(dev_id, port_id, up);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set traffic scheduling mode on particular one port.
+ * @details Comments:
+ * When scheduling mode is sp the weight is meaningless usually it's zero
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] fal_sch_mode_t traffic scheduling mode
+ * @param[in] weight[] weight value for each queue when in wrr mode,
+ the max value supported by SHIVA is 0x1f.
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t mode, const a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_sch_mode_set(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get traffic scheduling mode on particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] fal_sch_mode_t traffic scheduling mode
+ * @param[out] weight weight value for wrr mode
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
+ fal_sch_mode_t * mode, a_uint32_t weight[])
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_qos_port_sch_mode_get(dev_id, port_id, mode, weight);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_qos_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->qos_queue_tx_buf_status_set = shiva_qos_queue_tx_buf_status_set;
+ p_api->qos_queue_tx_buf_status_get = shiva_qos_queue_tx_buf_status_get;
+ p_api->qos_port_tx_buf_status_set = shiva_qos_port_tx_buf_status_set;
+ p_api->qos_port_tx_buf_status_get = shiva_qos_port_tx_buf_status_get;
+ p_api->qos_queue_tx_buf_nr_set = shiva_qos_queue_tx_buf_nr_set;
+ p_api->qos_queue_tx_buf_nr_get = shiva_qos_queue_tx_buf_nr_get;
+ p_api->qos_port_tx_buf_nr_set = shiva_qos_port_tx_buf_nr_set;
+ p_api->qos_port_tx_buf_nr_get = shiva_qos_port_tx_buf_nr_get;
+ p_api->qos_port_rx_buf_nr_set = shiva_qos_port_rx_buf_nr_set;
+ p_api->qos_port_rx_buf_nr_get = shiva_qos_port_rx_buf_nr_get;
+ p_api->cosmap_up_queue_set = shiva_cosmap_up_queue_set;
+ p_api->cosmap_up_queue_get = shiva_cosmap_up_queue_get;
+ p_api->cosmap_dscp_queue_set = shiva_cosmap_dscp_queue_set;
+ p_api->cosmap_dscp_queue_get = shiva_cosmap_dscp_queue_get;
+ p_api->qos_port_mode_set = shiva_qos_port_mode_set;
+ p_api->qos_port_mode_get = shiva_qos_port_mode_get;
+ p_api->qos_port_mode_pri_set = shiva_qos_port_mode_pri_set;
+ p_api->qos_port_mode_pri_get = shiva_qos_port_mode_pri_get;
+ p_api->qos_port_default_up_set = shiva_qos_port_default_up_set;
+ p_api->qos_port_default_up_get = shiva_qos_port_default_up_get;
+ p_api->qos_port_sch_mode_set = shiva_qos_port_sch_mode_set;
+ p_api->qos_port_sch_mode_get = shiva_qos_port_sch_mode_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_rate.c b/src/hsl/shiva/shiva_rate.c
new file mode 100644
index 0000000..5d2abd8
--- /dev/null
+++ b/src/hsl/shiva/shiva_rate.c
@@ -0,0 +1,838 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_rate SHIVA_RATE
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_rate.h"
+#include "shiva_reg.h"
+
+#define SHIVA_STORM_MIN_RATE_PPS 1000
+#define SHIVA_STORM_MAX_RATE_PPS (1024 * 1000)
+
+static sw_error_t
+shiva_stormrate_sw_to_hw(a_uint32_t swrate, a_uint32_t * hwrate)
+{
+ a_uint32_t shrnr = 0;
+ a_uint32_t tmp = swrate / 1000;
+
+ if ((SHIVA_STORM_MIN_RATE_PPS > swrate)
+ || (SHIVA_STORM_MAX_RATE_PPS < swrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ while ((tmp != 0) && (shrnr < 12))
+ {
+ tmp = tmp >> 1;
+ shrnr++;
+ }
+
+ if (12 == shrnr)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *hwrate = shrnr;
+ return SW_OK;
+}
+
+static sw_error_t
+shiva_stormrate_hw_to_sw(a_uint32_t hwrate, a_uint32_t * swrate)
+{
+ if (0 == hwrate)
+ {
+ hwrate = 1;
+ }
+
+ if ((1 > hwrate) || (11 < hwrate))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ *swrate = (1 << (hwrate - 1)) * 1000;
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t portrl;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_TRUE == enable)
+ {
+ if (1 == portrl)
+ {
+ /* already enable port egress rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+ val = *speed >> 5;
+ *speed = val << 5;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0x7fff;
+ *speed = 0;
+ if (1 == portrl)
+ {
+ /* already enable port egress rate limit */
+ return SW_OK;
+ }
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == val)
+ {
+ /* already enable port egress rate limit */
+ *speed = 0;
+ *enable = A_FALSE;
+
+ return SW_OK;
+ }
+
+ if (0 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (1 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (2 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else if (3 == queue_id)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff == val)
+ {
+ *enable = A_FALSE;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+ a_uint32_t portrl;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&portrl), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (A_FALSE == enable)
+ {
+ *speed = 0;
+
+ /* if port egress rate limit current enable then disable */
+ if (1 == portrl)
+ {
+ val = 0;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ val = 0x7fff;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ rv = SW_OK;
+ }
+ else
+ {
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ /* not enable egress port rate limit */
+ if (0 == portrl)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q0_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue0 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT1, port_id, EG_Q1_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue1 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q2_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue2 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff != val)
+ {
+ /* already enable egress queue3 rate limit, queue and port
+ egress rate limit can't coexist */
+ return SW_NOT_SUPPORTED;
+ }
+
+ val = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ val = *speed >> 5;
+ *speed = val << 5;
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, EG_RATE_EN,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == val)
+ {
+ *speed = 0;
+ *enable = A_FALSE;
+ return SW_OK;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT2, port_id, EG_Q3_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ *enable = A_TRUE;
+ *speed = val << 5;
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ if ((0x7ffe << 5) < *speed)
+ {
+ return SW_BAD_PARAM;
+ }
+ val = *speed >> 5;
+ *speed = val << 5;
+ }
+ else if (A_FALSE == enable)
+ {
+ val = 0x7fff;
+ *speed = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, RATE_LIMIT0, port_id, ING_RATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0x7fff == val)
+ {
+ *enable = A_FALSE;
+ *speed = 0;
+ }
+ else
+ {
+ *enable = A_TRUE;
+ *speed = val << 5;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE == enable)
+ {
+ data = 1;
+ }
+ else if (A_FALSE == enable)
+ {
+ data = 0;
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ if (0 == data)
+ {
+ data = 1;
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (FAL_UNICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, UNI_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_MULTICAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, MUL_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else if (FAL_BROADCAST_STORM == storm_type)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, BRO_EN,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ }
+ else
+ {
+ return SW_BAD_PARAM;
+ }
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (1 == data)
+ {
+ data = 1;
+ *enable = A_TRUE;
+ }
+ else
+ {
+ *enable = A_FALSE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ rv = shiva_stormrate_sw_to_hw(*rate_in_pps, &data);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_FIELD_SET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_stormrate_hw_to_sw(data, rate_in_pps);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ a_uint32_t data;
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, STORM_CTL, port_id, RATE,
+ (a_uint8_t *) (&data), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_stormrate_hw_to_sw(data, rate_in_pps);
+ return rv;
+}
+
+/**
+ * @brief Set queue egress rate limit status on one particular port and queue.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable queue egress rate limit input parameter speed is meaningless.
+ Egress queue rate limit can't coexist with port egress rate limit.
+ The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_queue_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_queue_egrl_set(dev_id, port_id, queue_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get queue egress rate limit status on one particular port and queue.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] queue_id queue id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_queue_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_queue_t queue_id, a_uint32_t * speed,
+ a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_queue_egrl_get(dev_id, port_id, queue_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port egress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port egress rate limit input parameter speed is meaningless.
+ Egress port rate limit can't coexist with queue egress rate limit.
+ The step of speed is 32kbps.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_egrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_port_egrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port egress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_egrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_port_egrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set port ingress rate limit status on one particular port.
+ * @details Comments:
+ The granularity of speed is bps.
+ Because of hardware granularity function will return actual speed in hardware.
+ When disable port ingress rate limit input parameter speed is meaningless.
+ The step of speed is 32kbps.
+ * When disable port ingress rate limit input parameter speed is meaningless.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed rate limit speed
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_inrl_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_port_inrl_set(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port ingress rate limit status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed rate limit speed
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_rate_port_inrl_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * speed, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_rate_port_inrl_get(dev_id, port_id, speed, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set particular type storm control status on one particular port.
+ * @details Comments:
+ * When enable one particular packets type storm control this type packets
+ * speed will be calculated in storm control.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[in] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_frame_set(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_storm_ctrl_frame_set(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get particular type storm control status on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[in] frame_type packets type which causes storm
+ * @param[out] enable A_TRUE or A_FALSE
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_frame_get(a_uint32_t dev_id, fal_port_t port_id,
+ fal_storm_type_t storm_type, a_bool_t * enable)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_storm_ctrl_frame_get(dev_id, port_id, storm_type, enable);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Set storm control speed on one particular port.
+ * @details Comments:
+ Because of hardware granularity function will return actual speed in hardware.
+ The step of speed is kpps.
+ The speed range is from 1k to 1M
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_rate_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_storm_ctrl_rate_set(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get storm control speed on one particular port.
+ * @param[in] dev_id device id
+ * @param[in] port_id port id
+ * @param[out] speed storm control speed
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_storm_ctrl_rate_get(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t * rate_in_pps)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_storm_ctrl_rate_get(dev_id, port_id, rate_in_pps);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_rate_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->rate_queue_egrl_set = shiva_rate_queue_egrl_set;
+ p_api->rate_queue_egrl_get = shiva_rate_queue_egrl_get;
+ p_api->rate_port_egrl_set = shiva_rate_port_egrl_set;
+ p_api->rate_port_egrl_get = shiva_rate_port_egrl_get;
+ p_api->rate_port_inrl_set = shiva_rate_port_inrl_set;
+ p_api->rate_port_inrl_get = shiva_rate_port_inrl_get;
+ p_api->storm_ctrl_frame_set = shiva_storm_ctrl_frame_set;
+ p_api->storm_ctrl_frame_get = shiva_storm_ctrl_frame_get;
+ p_api->storm_ctrl_rate_set = shiva_storm_ctrl_rate_set;
+ p_api->storm_ctrl_rate_get = shiva_storm_ctrl_rate_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_reduced_acl.c b/src/hsl/shiva/shiva_reduced_acl.c
new file mode 100644
index 0000000..20deeb7
--- /dev/null
+++ b/src/hsl/shiva/shiva_reduced_acl.c
@@ -0,0 +1,164 @@
+#include "sw.h"
+#include "shiva_reduced_acl.h"
+#include "hsl.h"
+
+#define SHIVA_RULE_VLU_ADDR 0x58400
+#define SHIVA_RULE_MSK_ADDR 0x58c00
+#define SHIVA_RULE_LEN_ADDR 0x58818
+#define SHIVA_RULE_ACT_ADDR 0x58000
+#define SHIVA_RULE_SLCT_ADDR 0x58800
+
+sw_error_t
+shiva_acl_rule_write(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* set rule value */
+ base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set rule mask */
+ base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_action_write(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act[3])
+{
+ sw_error_t rv;
+ a_uint32_t base, addr, i;
+
+ /* set rule action */
+ base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_slct_write(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8])
+{
+ sw_error_t rv;
+ a_uint32_t base, addr;
+ a_uint32_t i;
+
+ base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* set rule address */
+ for (i = 1; i < 7; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* set rule enable */
+ HSL_REG_ENTRY_GEN_SET(rv, dev_id, base, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[0])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_rule_read(a_uint32_t dev_id, a_uint32_t rule_idx, a_uint32_t vlu[8],
+ a_uint32_t msk[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ /* get rule value */
+ base = SHIVA_RULE_VLU_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(vlu[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ /* get rule mask */
+ base = SHIVA_RULE_MSK_ADDR + (rule_idx << 5);
+ for (i = 0; i < 5; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(msk[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_action_read(a_uint32_t dev_id, a_uint32_t act_idx,
+ a_uint32_t act[3])
+{
+ sw_error_t rv;
+ a_uint32_t base, addr, i;
+
+ /* get rule action */
+ base = SHIVA_RULE_ACT_ADDR + (act_idx << 5);
+ for (i = 0; i < 3; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(act[i])), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_acl_slct_read(a_uint32_t dev_id, a_uint32_t slct_idx,
+ a_uint32_t slct[8])
+{
+ sw_error_t rv;
+ a_uint32_t i, base, addr;
+
+ base = SHIVA_RULE_SLCT_ADDR + (slct_idx << 5);
+
+ /* get filter address and enable */
+ for (i = 0; i < 7; i++)
+ {
+ addr = base + (i << 2);
+ HSL_REG_ENTRY_GEN_GET(rv, dev_id, addr, sizeof (a_uint32_t),
+ (a_uint8_t *) (&(slct[i])),
+ sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return SW_OK;
+}
diff --git a/src/hsl/shiva/shiva_reg_access.c b/src/hsl/shiva/shiva_reg_access.c
new file mode 100644
index 0000000..2587688
--- /dev/null
+++ b/src/hsl/shiva/shiva_reg_access.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "sd.h"
+#include "shiva_reg_access.h"
+
+static hsl_access_mode reg_mode;
+
+#if defined(API_LOCK)
+static aos_lock_t mdio_lock;
+#define MDIO_LOCKER_INIT aos_lock_init(&mdio_lock)
+#define MDIO_LOCKER_LOCK aos_lock(&mdio_lock)
+#define MDIO_LOCKER_UNLOCK aos_unlock(&mdio_lock)
+#else
+#define MDIO_LOCKER_INIT
+#define MDIO_LOCKER_LOCK
+#define MDIO_LOCKER_UNLOCK
+#endif
+
+static sw_error_t
+_shiva_mdio_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val, tmp_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as MIBs, since it is read/clear, we should */
+ /* read the lower 16-bit register then the higher one */
+
+ /* read register in lower address */
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val = tmp_val;
+
+ /* read register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ rv = sd_reg_mdio_get(dev_id, phy_addr, phy_reg, &tmp_val);
+ SW_RTN_ON_ERROR(rv);
+ reg_val |= (((a_uint32_t)tmp_val) << 16);
+
+ aos_mem_copy(value, ®_val, sizeof (a_uint32_t));
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_mdio_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ a_uint32_t reg_word_addr;
+ a_uint32_t phy_addr, reg_val;
+ a_uint16_t phy_val;
+ a_uint8_t phy_reg;
+ sw_error_t rv;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ aos_mem_copy(®_val, value, sizeof (a_uint32_t));
+
+ /* change reg_addr to 16-bit word address, 32-bit aligned */
+ reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+ /* configure register high address */
+ phy_addr = 0x18;
+ phy_reg = 0x0;
+ phy_val = (a_uint16_t) ((reg_word_addr >> 8) & 0x3ff); /* bit16-8 of reg address */
+
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* For some registers such as ARL and VLAN, since they include BUSY bit */
+ /* in lower address, we should write the higher 16-bit register then the */
+ /* lower one */
+
+ /* write register in higher address */
+ reg_word_addr++;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) ((reg_val >> 16) & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ /* write register in lower address */
+ reg_word_addr--;
+ phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+ phy_reg = (a_uint8_t) (reg_word_addr & 0x1f); /* bit4-0 of reg address */
+ phy_val = (a_uint16_t) (reg_val & 0xffff);
+ rv = sd_reg_mdio_set(dev_id, phy_addr, phy_reg, phy_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_phy_get(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t * value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_get(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+shiva_phy_set(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t value)
+{
+ sw_error_t rv;
+
+ MDIO_LOCKER_LOCK;
+ rv = sd_reg_mdio_set(dev_id, phy_addr, reg, value);
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+shiva_reg_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _shiva_mdio_reg_get(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_get(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+shiva_reg_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t value[],
+ a_uint32_t value_len)
+{
+ sw_error_t rv;
+ a_uint32_t flags;
+
+ MDIO_LOCKER_LOCK;
+ if (HSL_MDIO == reg_mode)
+ {
+ aos_irq_save(flags);
+ rv = _shiva_mdio_reg_set(dev_id, reg_addr, value, value_len);
+ aos_irq_restore(flags);
+ }
+ else
+ {
+ rv = sd_reg_hdr_set(dev_id, reg_addr, value, value_len);
+ }
+ MDIO_LOCKER_UNLOCK;
+
+ return rv;
+}
+
+sw_error_t
+shiva_reg_field_get(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val = 0;
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ *((a_uint32_t *) value) = SW_REG_2_FIELD(reg_val, bit_offset, field_len);
+ return SW_OK;
+}
+
+sw_error_t
+shiva_reg_field_set(a_uint32_t dev_id, a_uint32_t reg_addr,
+ a_uint32_t bit_offset, a_uint32_t field_len,
+ const a_uint8_t value[], a_uint32_t value_len)
+{
+ a_uint32_t reg_val;
+ a_uint32_t field_val = *((a_uint32_t *) value);
+
+ if ((bit_offset >= 32 || (field_len > 32)) || (field_len == 0))
+ return SW_OUT_OF_RANGE;
+
+ if (value_len != sizeof (a_uint32_t))
+ return SW_BAD_LEN;
+
+ SW_RTN_ON_ERROR(shiva_reg_get(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ SW_REG_SET_BY_FIELD_U32(reg_val, field_val, bit_offset, field_len);
+
+ SW_RTN_ON_ERROR(shiva_reg_set(dev_id, reg_addr, (a_uint8_t *) & reg_val, sizeof (a_uint32_t)));
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_reg_access_init(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ hsl_api_t *p_api;
+
+ MDIO_LOCKER_INIT;
+ reg_mode = mode;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+ p_api->phy_get = shiva_phy_get;
+ p_api->phy_set = shiva_phy_set;
+ p_api->reg_get = shiva_reg_get;
+ p_api->reg_set = shiva_reg_set;
+ p_api->reg_field_get = shiva_reg_field_get;
+ p_api->reg_field_set = shiva_reg_field_set;
+ p_api->dev_access_set= shiva_access_mode_set;
+
+ return SW_OK;
+}
+
+sw_error_t
+shiva_access_mode_set(a_uint32_t dev_id, hsl_access_mode mode)
+{
+ reg_mode = mode;
+ return SW_OK;
+
+}
+
diff --git a/src/hsl/shiva/shiva_stp.c b/src/hsl/shiva/shiva_stp.c
new file mode 100644
index 0000000..06128b4
--- /dev/null
+++ b/src/hsl/shiva/shiva_stp.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_stp SHIVA_STP
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_stp.h"
+#include "shiva_reg.h"
+
+#define SHIVA_PORT_DISABLED 0
+#define SHIVA_STP_BLOCKING 1
+#define SHIVA_STP_LISTENING 2
+#define SHIVA_STP_LEARNING 3
+#define SHIVA_STP_FARWARDING 4
+
+static sw_error_t
+_shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ switch (state)
+ {
+ case FAL_STP_BLOKING:
+ val = SHIVA_STP_BLOCKING;
+ break;
+ case FAL_STP_LISTENING:
+ val = SHIVA_STP_LISTENING;
+ break;
+ case FAL_STP_LEARNING:
+ val = SHIVA_STP_LEARNING;
+ break;
+ case FAL_STP_FARWARDING:
+ val = SHIVA_STP_FARWARDING;
+ break;
+ case FAL_STP_DISABLED:
+ val = SHIVA_PORT_DISABLED;
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_SET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ return rv;
+}
+
+static sw_error_t
+_shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+ a_uint32_t val;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (FAL_SINGLE_STP_ID != st_id)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_EXCL_CPU))
+ {
+ return SW_BAD_PARAM;
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_CTL, port_id, PORT_STATE,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ switch (val)
+ {
+ case SHIVA_STP_BLOCKING:
+ *state = FAL_STP_BLOKING;
+ break;
+ case SHIVA_STP_LISTENING:
+ *state = FAL_STP_LISTENING;
+ break;
+ case SHIVA_STP_LEARNING:
+ *state = FAL_STP_LEARNING;
+ break;
+ case SHIVA_STP_FARWARDING:
+ *state = FAL_STP_FARWARDING;
+ break;
+ case SHIVA_PORT_DISABLED:
+ *state = FAL_STP_DISABLED;
+ break;
+ default:
+ return SW_FAIL;
+ }
+
+ return SW_OK;
+}
+
+/**
+ * @brief Set port stp state on a particular spanning tree and port.
+ * @details Comments:
+ SHIVA only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[in] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_stp_port_state_set(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_stp_port_state_set(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get port stp state on a particular spanning tree and port.
+ * @details Comments:
+ SHIVA only support single spanning tree so st_id should be
+ FAL_SINGLE_STP_ID that is zero.
+ * @param[in] dev_id device id
+ * @param[in] st_id spanning tree id
+ * @param[in] port_id port id
+ * @param[out] state port state for spanning tree
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_stp_port_state_get(a_uint32_t dev_id, a_uint32_t st_id,
+ fal_port_t port_id, fal_stp_state_t * state)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_stp_port_state_get(dev_id, st_id, port_id, state);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_stp_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ {
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->stp_port_state_set = shiva_stp_port_state_set;
+ p_api->stp_port_state_get = shiva_stp_port_state_get;
+ }
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/hsl/shiva/shiva_vlan.c b/src/hsl/shiva/shiva_vlan.c
new file mode 100644
index 0000000..47753de
--- /dev/null
+++ b/src/hsl/shiva/shiva_vlan.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+/**
+ * @defgroup shiva_vlan SHIVA_VLAN
+ * @{
+ */
+#include "sw.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "hsl_port_prop.h"
+#include "shiva_vlan.h"
+#include "shiva_reg.h"
+
+#define MAX_VLAN_ID 4095
+
+#define VLAN_FLUSH 1
+#define VLAN_LOAD_ENTRY 2
+#define VLAN_PURGE_ENTRY 3
+#define VLAN_REMOVE_PORT 4
+#define VLAN_NEXT_ENTRY 5
+#define VLAN_FIND_ENTRY 6
+
+static void
+shiva_vlan_hw_to_sw(const a_uint32_t reg[], fal_vlan_t * vlan_entry)
+{
+ a_uint32_t data;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI_EN, data, reg[0]);
+ if (1 == data)
+ {
+ vlan_entry->vid_pri_en = A_TRUE;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VT_PRI, data, reg[0]);
+ vlan_entry->vid_pri = data & 0xff;
+ }
+ else
+ {
+ vlan_entry->vid_pri_en = A_FALSE;
+ }
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC0, VLAN_ID, data, reg[0]);
+ vlan_entry->vid = data & 0xffff;
+
+ SW_GET_FIELD_BY_REG(VLAN_TABLE_FUNC1, VID_MEM, data, reg[1]);
+ vlan_entry->mem_ports = data;
+
+ return;
+}
+
+static sw_error_t
+shiva_vlan_sw_to_hw(const fal_vlan_t * vlan_entry, a_uint32_t reg[])
+{
+ if (A_TRUE == vlan_entry->vid_pri_en)
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 1, reg[0]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI, vlan_entry->vid_pri, reg[0]);
+ }
+ else
+ {
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_PRI_EN, 0, reg[0]);
+ }
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_entry->vid, reg[0]);
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, reg[1]);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VID_MEM, vlan_entry->mem_ports, reg[1]);
+
+ if (0 != vlan_entry->u_ports)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+shiva_vlan_commit(a_uint32_t dev_id, a_uint32_t op)
+{
+ a_uint32_t vt_busy = 1, i = 0x1000, vt_full, val;
+ sw_error_t rv;
+
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_BUSY;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_FUNC, op, val);
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VT_BUSY, 1, val);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ vt_busy = 1;
+ i = 0x1000;
+ while (vt_busy && --i)
+ {
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_BUSY,
+ (a_uint8_t *) (&vt_busy), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ aos_udelay(5);
+ }
+
+ if (i == 0)
+ return SW_FAIL;
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VT_FULL_VIO,
+ (a_uint8_t *) (&vt_full), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (vt_full)
+ {
+ val = 0x10;
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+ if (VLAN_LOAD_ENTRY == op)
+ {
+ return SW_FULL;
+ }
+ else if (VLAN_PURGE_ENTRY == op)
+ {
+ return SW_NOT_FOUND;
+ }
+ }
+
+ HSL_REG_FIELD_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VT_VALID,
+ (a_uint8_t *) (&val), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ if (!val)
+ {
+ if (VLAN_FIND_ENTRY == op)
+ return SW_NOT_FOUND;
+
+ if (VLAN_NEXT_ENTRY == op)
+ return SW_NO_MORE;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_entry->vid == 0) || (vlan_entry->vid > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, vlan_entry->mem_ports, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ rv = shiva_vlan_sw_to_hw(vlan_entry, reg);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t entry = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ /* set default value for VLAN_TABLE_FUNC0, all 0 except vid */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ /* set default value for VLAN_TABLE_FUNC1, all 0 */
+ entry = 0;
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC1, VT_VALID, 1, entry);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (&entry), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if (vlan_id > MAX_VLAN_ID)
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_NEXT_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ shiva_vlan_hw_to_sw(reg, p_vlan);
+
+ if (0 == p_vlan->vid)
+ return SW_NO_MORE;
+ else
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+ a_uint32_t reg[2] = { 0 };
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ aos_mem_zero(p_vlan, sizeof (fal_vlan_t));
+
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg[0]);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®[0]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ HSL_REG_ENTRY_GET(rv, dev_id, VLAN_TABLE_FUNC1, 0,
+ (a_uint8_t *) (®[1]), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ shiva_vlan_hw_to_sw(reg, p_vlan);
+
+ return SW_OK;
+}
+
+static sw_error_t
+_shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+ a_uint32_t reg = 0;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ if (A_FALSE == hsl_mports_prop_check(dev_id, member, HSL_PP_INCL_CPU))
+ return SW_BAD_PARAM;
+
+ if (u_member != 0)
+ return SW_BAD_PARAM;
+
+ /* get vlan entry first */
+ SW_SET_REG_BY_FIELD(VLAN_TABLE_FUNC0, VLAN_ID, vlan_id, reg);
+ HSL_REG_ENTRY_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_FIND_ENTRY);
+ SW_RTN_ON_ERROR(rv);
+
+ /* set vlan member for VLAN_TABLE_FUNC1 */
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC1, 0, VID_MEM,
+ (a_uint8_t *) (&member), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_LOAD_ENTRY);
+ /* when update port member through LOAD opration, hardware will
+ return VT_FULL_VIO, we should ignore it */
+ if (SW_FULL == rv)
+ rv = SW_OK;
+
+ return rv;
+}
+
+static sw_error_t
+_shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_DEV_ID_CHECK(dev_id);
+
+ if ((vlan_id == 0) || (vlan_id > MAX_VLAN_ID))
+ return SW_OUT_OF_RANGE;
+
+ reg = (a_int32_t) vlan_id;
+ HSL_REG_FIELD_SET(rv, dev_id, VLAN_TABLE_FUNC0, 0, VLAN_ID,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ SW_RTN_ON_ERROR(rv);
+
+ rv = shiva_vlan_commit(dev_id, VLAN_PURGE_ENTRY);
+ return rv;
+}
+
+static sw_error_t
+_shiva_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_DEV_ID_CHECK(dev_id);
+ rv = shiva_vlan_commit(dev_id, VLAN_FLUSH);
+ return rv;
+}
+
+/**
+ * @brief Append a vlan entry on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_entry vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_entry_append(a_uint32_t dev_id, const fal_vlan_t * vlan_entry)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_entry_append(dev_id, vlan_entry);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Creat a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * After this operation the member ports of the created vlan entry are null.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_create(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_create(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Next a vlan entry through vlan id on a paticular device.
+ * @details Comments:
+ * If the value of vid is zero this operation will get the first entry.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_next(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_next(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Find a vlan entry through vlan id on paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[out] p_vlan vlan entry
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_find(a_uint32_t dev_id, a_uint32_t vlan_id, fal_vlan_t * p_vlan)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_find(dev_id, vlan_id, p_vlan);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Update a vlan entry member port through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @param[in] member member ports
+ * @param[in] u_member tagged or untagged infomation for member ports
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_member_update(a_uint32_t dev_id, a_uint32_t vlan_id,
+ fal_pbmp_t member, fal_pbmp_t u_member)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_member_update(dev_id, vlan_id, member, u_member);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Delete a vlan entry through vlan id on a paticular device.
+ * @param[in] dev_id device id
+ * @param[in] vlan_id vlan id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_delete(a_uint32_t dev_id, a_uint32_t vlan_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_delete(dev_id, vlan_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Flush all vlan entries on a paticular device.
+ * @param[in] dev_id device id
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+shiva_vlan_flush(a_uint32_t dev_id)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _shiva_vlan_flush(dev_id);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+shiva_vlan_init(a_uint32_t dev_id)
+{
+ HSL_DEV_ID_CHECK(dev_id);
+
+#ifndef HSL_STANDALONG
+ hsl_api_t *p_api;
+
+ SW_RTN_ON_NULL(p_api = hsl_api_ptr_get(dev_id));
+
+ p_api->vlan_entry_append = shiva_vlan_entry_append;
+ p_api->vlan_creat = shiva_vlan_create;
+ p_api->vlan_member_update = shiva_vlan_member_update;
+ p_api->vlan_delete = shiva_vlan_delete;
+ p_api->vlan_next = shiva_vlan_next;
+ p_api->vlan_find = shiva_vlan_find;
+ p_api->vlan_flush = shiva_vlan_flush;
+
+#endif
+
+ return SW_OK;
+}
+
+/**
+ * @}
+ */
+
diff --git a/src/init/Makefile b/src/init/Makefile
new file mode 100644
index 0000000..8edc72b
--- /dev/null
+++ b/src/init/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/init
+LIB=INIT
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
new file mode 100644
index 0000000..5f9d430
--- /dev/null
+++ b/src/init/ssdk_init.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "ssdk_init.h"
+#include "fal_init.h"
+#include "hsl.h"
+#include "hsl_dev.h"
+#include "ssdk_init.h"
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#define IPQ806X_MDIO_BUS_NAME "mdio-gpio"
+#define IPQ806X_MDIO_BUS_NUM 0
+#define IPQ806X_MDIO_BUS_MAX 1
+
+static struct mii_bus *miibus = NULL;
+
+sw_error_t
+ssdk_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+ sw_error_t rv;
+
+#if (defined(KERNEL_MODULE) && defined(USER_MODE))
+ rv = hsl_dev_init(dev_id, cfg);
+#else
+#ifdef HSL_STANDALONG
+ rv = hsl_dev_init(dev_id, cfg);
+#else
+ rv = fal_init(dev_id, cfg);
+#endif
+#endif
+
+ return rv;
+}
+
+sw_error_t
+ssdk_reduced_init(a_uint32_t dev_id, hsl_init_mode cpu_mode,
+ hsl_access_mode reg_mode)
+{
+ sw_error_t rv;
+
+#if (defined(KERNEL_MODULE) && defined(USER_MODE))
+ rv = hsl_dev_reduced_init(dev_id, cpu_mode, reg_mode);
+#else
+#ifdef HSL_STANDALONG
+ rv = hsl_dev_reduced_init(dev_id, cpu_mode, reg_mode);
+#else
+ rv = fal_reduced_init(dev_id, cpu_mode, reg_mode);
+#endif
+#endif
+
+ return rv;
+}
+
+sw_error_t
+ssdk_cleanup(void)
+{
+ sw_error_t rv;
+
+#if (defined(KERNEL_MODULE) && defined(USER_MODE))
+ rv = hsl_dev_cleanup();
+#else
+#ifdef HSL_STANDALONG
+ rv = hsl_dev_cleanup();
+#else
+ rv = fal_cleanup();
+#endif
+#endif
+
+ return rv;
+}
+
+sw_error_t
+ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode)
+{
+ sw_error_t rv;
+
+ rv = hsl_access_mode_set(dev_id, reg_mode);
+ return rv;
+}
+
+static inline void
+split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2, uint16_t *page)
+{
+ regaddr >>= 1;
+ *r1 = regaddr & 0x1e;
+
+ regaddr >>= 5;
+ *r2 = regaddr & 0x7;
+
+ regaddr >>= 3;
+ *page = regaddr & 0x3ff;
+}
+
+uint32_t
+qca_ar8216_mii_read(int reg)
+{
+ struct mii_bus *bus = miibus;
+ uint16_t r1, r2, page;
+ uint16_t lo, hi;
+
+ split_addr((uint32_t) reg, &r1, &r2, &page);
+
+ mutex_lock(&bus->mdio_lock);
+
+ bus->write(bus, 0x18, 0, page);
+ usleep_range(1000, 2000); /* wait for the page switch to propagate */
+ lo = bus->read(bus, 0x10 | r2, r1);
+ hi = bus->read(bus, 0x10 | r2, r1 + 1);
+
+ mutex_unlock(&bus->mdio_lock);
+
+ return (hi << 16) | lo;
+}
+
+void
+qca_ar8216_mii_write(int reg, uint32_t val)
+{
+ struct mii_bus *bus = miibus;
+ uint16_t r1, r2, r3;
+ uint16_t lo, hi;
+
+ split_addr((u32) reg, &r1, &r2, &r3);
+ lo = val & 0xffff;
+ hi = (u16) (val >> 16);
+
+ mutex_lock(&bus->mdio_lock);
+
+ bus->write(bus, 0x18, 0, r3);
+ usleep_range(1000, 2000); /* wait for the page switch to propagate */
+ bus->write(bus, 0x10 | r2, r1, lo);
+ bus->write(bus, 0x10 | r2, r1 + 1, hi);
+
+ mutex_unlock(&bus->mdio_lock);
+}
+
+static sw_error_t qca_ar8216_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t* data)
+
+{
+ struct mii_bus *bus = miibus;
+
+ mutex_lock(&bus->mdio_lock);
+ *data = bus->read(bus, phy_addr, reg);
+ mutex_unlock(&bus->mdio_lock);
+
+ return 0;
+}
+
+static sw_error_t qca_ar8216_phy_write(a_uint32_t dev_id, a_uint32_t phy_addr,
+ a_uint32_t reg, a_uint16_t data)
+{
+ struct mii_bus *bus = miibus;
+
+ mutex_lock(&bus->mdio_lock);
+ bus->write(bus, phy_addr, reg, data);
+ mutex_unlock(&bus->mdio_lock);
+
+ return 0;
+}
+
+static int miibus_get()
+{
+ struct device *miidev;
+ uint8_t busid[MII_BUS_ID_SIZE];
+ snprintf(busid, MII_BUS_ID_SIZE, "%s.%d", IPQ806X_MDIO_BUS_NAME, IPQ806X_MDIO_BUS_NUM);
+
+ miidev = bus_find_device_by_name(&platform_bus_type, NULL, busid);
+ if (!miidev) {
+ printk("cannot get mii bus\n");
+ return 1;
+ }
+
+ miibus = dev_get_drvdata(miidev);
+ if(!miidev){
+ printk("mdio bus '%s' get FAIL\n", busid);
+ return 1;
+ }
+
+ return 0;
+
+}
+
+static int __init
+regi_init(void)
+{
+ int phy_addr;
+ ssdk_init_cfg cfg;
+ int rv = 0;
+
+ miibus_get();
+ garuda_init_spec_cfg chip_spec_cfg;
+
+ memset(&cfg, 0, sizeof(ssdk_init_cfg));
+ memset(&chip_spec_cfg, 0, sizeof(garuda_init_spec_cfg));
+
+ cfg.cpu_mode = HSL_CPU_1;
+ cfg.reg_mode = HSL_MDIO;
+ cfg.nl_prot = 30;
+
+ #ifdef QCA_SWITCH_S17
+ cfg.chip_type = CHIP_ISIS;
+ #else
+ cfg.chip_type = CHIP_ISISC;
+ #endif
+
+ cfg.chip_spec_cfg = &chip_spec_cfg;
+ cfg.reg_func.mdio_set = qca_ar8216_phy_write; // parameters
+ cfg.reg_func.mdio_get = qca_ar8216_phy_read;
+
+
+ rv = ssdk_init(0, &cfg);
+ if (rv == 0)
+ printk("qca-ssdk module init succeeded!\n");
+ else
+ printk("qca-ssdk module init failed! (code: %d)\n", rv);
+
+ return rv;
+
+}
+
+static void __exit
+regi_exit(void)
+{
+ sw_error_t rv=ssdk_cleanup();
+
+ if (rv == 0)
+ printk("qca-ssdk module exit done!\n");
+ else
+ printk("qca-ssdk module exit failed! (code: %d)\n", rv);
+}
+
+module_init(regi_init);
+module_exit(regi_exit);
+
+MODULE_DESCRIPTION("QCA SSDK Driver");
+MODULE_AUTHOR("Qualcomm Atheros Inc");
+MODULE_LICENSE("Dual BSD/GPL");
+
diff --git a/src/sal/Makefile b/src/sal/Makefile
new file mode 100644
index 0000000..805ae0f
--- /dev/null
+++ b/src/sal/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/sal/sd/Makefile b/src/sal/sd/Makefile
new file mode 100644
index 0000000..74c50e2
--- /dev/null
+++ b/src/sal/sd/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal/sd
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/sal/sd/linux/Makefile b/src/sal/sd/linux/Makefile
new file mode 100644
index 0000000..a038efc
--- /dev/null
+++ b/src/sal/sd/linux/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/sal/sd/linux
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/sal/sd/linux/uk_interface/Makefile b/src/sal/sd/linux/uk_interface/Makefile
new file mode 100644
index 0000000..a4bac32
--- /dev/null
+++ b/src/sal/sd/linux/uk_interface/Makefile
@@ -0,0 +1,34 @@
+LOC_DIR=src/sal/sd/linux/uk_interface
+LIB=SAL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=
+
+ifeq (TRUE, $(UK_IF))
+ifeq (KSLIB, $(MODULE_TYPE))
+ ifeq (TRUE, $(UK_NETLINK))
+ SRC_LIST=sw_api_ks_netlink.c
+ endif
+
+ ifeq (TRUE, $(UK_IOCTL))
+ SRC_LIST=sw_api_ks_ioctl.c
+ endif
+endif
+
+ifeq (USLIB, $(MODULE_TYPE))
+ ifeq (TRUE, $(UK_NETLINK))
+ SRC_LIST=sw_api_us_netlink.c
+ endif
+
+ ifeq (TRUE, $(UK_IOCTL))
+ SRC_LIST=sw_api_us_ioctl.c
+ endif
+endif
+endif
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
\ No newline at end of file
diff --git a/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c b/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c
new file mode 100644
index 0000000..50eefc1
--- /dev/null
+++ b/src/sal/sd/linux/uk_interface/sw_api_ks_ioctl.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "sw_api.h"
+
+#ifdef KVER26 /*Linux Kernel 2.6 */
+#define __USER __user
+#else /*Linux Kernel 2.4 */
+#include <asm/uaccess.h>
+#define __USER
+#endif /*KVER26 */
+
+#ifdef KVER34
+#include <generated/autoconf.h>
+#include <linux/fs.h>
+#include <linux/export.h>
+#else
+#include <net/sock.h>
+#endif
+
+#include <linux/skbuff.h>
+#include <linux/miscdevice.h>
+#include "api_access.h"
+#include "sw_api_ks.h"
+#ifdef KVER32
+#include <asm/uaccess.h>
+#include <linux/module.h>
+#endif
+
+static int
+switch_open(struct inode * inode,struct file * file);
+
+static int
+switch_close(struct inode * inode, struct file * file);
+
+
+#ifdef KVER32 //for linux3.2
+static long
+switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg);
+#else
+static long
+switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg);
+#endif
+
+static a_uint32_t *cmd_buf = NULL;
+
+static aos_lock_t api_ioctl_lock;
+
+static struct file_operations switch_device_fops =
+{
+ .owner = THIS_MODULE,
+ .read = NULL,
+ .write = NULL,
+ .poll = NULL,
+ .unlocked_ioctl= switch_ioctl,
+ .open = switch_open,
+ .release = switch_close
+};
+
+static struct miscdevice switch_device =
+{
+ MISC_DYNAMIC_MINOR,
+ "switch_ssdk",
+ &switch_device_fops
+};
+
+static sw_error_t
+input_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+ a_uint32_t i = 0, buf_head = nr_param;
+
+ for (i = 0; i < nr_param; i++)
+ {
+ if (p->param_type & SW_PARAM_PTR)
+ {
+ cmd_buf[i] = (a_uint32_t) & cmd_buf[buf_head];
+ buf_head += (p->data_size + 3) / 4;
+
+ if (buf_head > (SW_MAX_API_BUF / 4))
+ return SW_NO_RESOURCE;
+
+ if (p->param_type & SW_PARAM_IN)
+ {
+ if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2], ((p->data_size + 3) >> 2) << 2))
+ return SW_NO_RESOURCE;
+ }
+ }
+ else
+ {
+ cmd_buf[i] = args[i + 2];
+ }
+ p++;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+output_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+ a_uint32_t i =0;
+
+ for (i = 0; i < nr_param; i++)
+ {
+ if (p->param_type & SW_PARAM_OUT)
+ {
+ if (copy_to_user
+ ((void __USER *) args[i + 2], (a_uint32_t *) cmd_buf[i], ((p->data_size + 3) >> 2) << 2))
+ return SW_NO_RESOURCE;
+ }
+ p++;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+sw_api_cmd(a_uint32_t * args)
+{
+ a_uint32_t *p = cmd_buf, api_id = args[0], nr_param = 0;
+ sw_error_t(*func) (a_uint32_t, ...);
+ sw_api_param_t *pp;
+ sw_api_func_t *fp;
+ sw_error_t rv;
+ sw_api_t sw_api;
+
+ sw_api.api_id = api_id;
+ rv = sw_api_get(&sw_api);
+ SW_OUT_ON_ERROR(rv);
+
+ fp = sw_api.api_fp;
+ pp = sw_api.api_pp;
+ nr_param = sw_api.api_nr;
+
+ rv = input_parser(pp, nr_param, args);
+ SW_OUT_ON_ERROR(rv);
+ func = fp->func;
+
+ switch (nr_param)
+ {
+ case 1:
+ rv = (func) (p[0]);
+ break;
+ case 2:
+ rv = (func) (p[0], p[1]);
+ break;
+ case 3:
+ rv = (func) (p[0], p[1], p[2]);
+ break;
+ case 4:
+ rv = (func) (p[0], p[1], p[2], p[3]);
+ break;
+ case 5:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+ break;
+ case 6:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+ break;
+ case 7:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+ break;
+ case 8:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+ break;
+ case 9:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+ break;
+ case 10:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+ p[6], p[7], p[8], p[9]);
+ break;
+ default:
+ rv = SW_OUT_OF_RANGE;
+ }
+
+ SW_OUT_ON_ERROR(rv);
+ rv = output_parser(pp, nr_param, args);
+
+out:
+ return rv;
+}
+
+static int
+switch_open(struct inode * inode,struct file * file)
+{
+ return SW_OK;
+}
+
+static int
+switch_close(struct inode * inode, struct file * file)
+{
+ return SW_OK;
+}
+
+#ifdef KVER32
+static long
+switch_ioctl(struct file * file, unsigned int cmd, unsigned long arg)
+#else
+static long
+switch_ioctl(struct inode *inode, struct file * file, unsigned int cmd, unsigned long arg)
+#endif
+{
+ a_uint32_t args[SW_MAX_API_PARAM], rtn;
+ sw_error_t rv = SW_NO_RESOURCE;
+
+ if (copy_from_user(args, (int __user *)arg, sizeof (args)))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ aos_lock(&api_ioctl_lock);
+ rv = sw_api_cmd(args);
+ aos_unlock(&api_ioctl_lock);
+
+ /* return API result to user */
+ rtn = (a_uint32_t) rv;
+ if (copy_to_user
+ ((void __USER *) args[1], (a_uint32_t *) &rtn, sizeof (a_uint32_t)))
+ {
+ rv = SW_NO_RESOURCE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+ if (!cmd_buf)
+ {
+ if((cmd_buf = (a_uint32_t *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL)
+ {
+ return SW_OUT_OF_MEM;
+ }
+
+#if defined UK_MINOR_DEV
+ switch_device.minor = UK_MINOR_DEV;
+#else
+ switch_device.minor = nl_prot;
+#endif
+
+ if (misc_register(&switch_device))
+ {
+ return SW_INIT_ERROR;
+ }
+
+ aos_lock_init(&api_ioctl_lock);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+ if (cmd_buf)
+ {
+ aos_mem_free(cmd_buf);
+ cmd_buf = NULL;
+
+ misc_deregister(&switch_device);
+ }
+
+ return SW_OK;
+}
+
diff --git a/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c b/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c
new file mode 100644
index 0000000..37af244
--- /dev/null
+++ b/src/sal/sd/linux/uk_interface/sw_api_ks_netlink.c
@@ -0,0 +1,760 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "sw_api.h"
+
+#ifdef KVER26 /*Linux Kernel 2.6 */
+#define __USER __user
+#else /*Linux Kernel 2.4 */
+#include <asm/uaccess.h>
+#define __USER
+#define CLONE_KERNEL (CLONE_FS | CLONE_FILES | CLONE_SIGHAND)
+#define for_each_process(p) for_each_task(p)
+#endif /*KVER26 */
+#include <net/sock.h>
+#include <linux/skbuff.h>
+#include <linux/netlink.h>
+#include <linux/version.h>
+#include "api_access.h"
+#include "sw_api_ks.h"
+
+#if 0
+#define dprintk(args...) aos_printk(args)
+#else
+#define dprintk(args...)
+#endif
+
+/*configurable value for max creating request of kernel thread*/
+#define PID_THREADS_MAX 32
+
+#define RSV_PID_LOC_0 (0)
+#define RSV_PID_LOC_1 (1)
+
+#define PID_TAB_MAX PID_THREADS_MAX
+#define PID_TAB_NOT_FOUND PID_TAB_MAX+1
+
+static pid_t pid_parents[PID_TAB_MAX] = {0};
+static pid_t pid_childs[PID_TAB_MAX] = {0};
+static wait_queue_head_t pid_child_wait[PID_TAB_MAX];
+static struct semaphore pid_tab_sem;
+
+static a_uint32_t *cmd_buf = NULL;
+static struct semaphore api_sem;
+static struct sock *ssdk_nl_sk = NULL;
+static struct sk_buff * skb_array[PID_TAB_MAX] = {0};
+
+static sw_error_t
+input_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+ a_uint32_t i = 0, buf_head = nr_param;
+
+ for (i = 0; i < nr_param; i++)
+ {
+ if (p->param_type & SW_PARAM_PTR)
+ {
+ cmd_buf[i] = (a_uint32_t) & cmd_buf[buf_head];
+ buf_head += (p->data_size + 3) / 4;
+
+ if (buf_head > (SW_MAX_API_BUF / 4))
+ return SW_NO_RESOURCE;
+
+ if (p->param_type & SW_PARAM_IN)
+ {
+ if (copy_from_user((a_uint8_t*)(cmd_buf[i]), (void __USER *)args[i + 2], ((p->data_size + 3) >> 2) << 2))
+ return SW_NO_RESOURCE;
+ }
+ }
+ else
+ {
+ cmd_buf[i] = args[i + 2];
+ }
+ p++;
+ }
+ return SW_OK;
+}
+
+static sw_error_t
+output_parser(sw_api_param_t *p, a_uint32_t nr_param, a_uint32_t *args)
+{
+ a_uint32_t i =0;
+
+ for (i = 0; i < nr_param; i++)
+ {
+ if (p->param_type & SW_PARAM_OUT)
+ {
+ if (copy_to_user
+ ((void __USER *) args[i + 2], (a_uint32_t *) cmd_buf[i], ((p->data_size + 3) >> 2) << 2))
+ return SW_NO_RESOURCE;
+ }
+ p++;
+ }
+
+ return SW_OK;
+}
+
+static sw_error_t
+sw_api_cmd(a_uint32_t * args)
+{
+ a_uint32_t *p = cmd_buf, api_id = args[0], nr_param = 0;
+ sw_error_t(*func) (a_uint32_t, ...);
+ sw_api_param_t *pp;
+ sw_api_func_t *fp;
+ sw_error_t rv;
+ sw_api_t sw_api;
+
+ down(&api_sem);
+
+ sw_api.api_id = api_id;
+ rv = sw_api_get(&sw_api);
+ SW_OUT_ON_ERROR(rv);
+
+ fp = sw_api.api_fp;
+ pp = sw_api.api_pp;
+ nr_param = sw_api.api_nr;
+
+ rv = input_parser(pp, nr_param, args);
+ SW_OUT_ON_ERROR(rv);
+ func = fp->func;
+
+ switch (nr_param)
+ {
+ case 1:
+ rv = (func) (p[0]);
+ break;
+ case 2:
+ rv = (func) (p[0], p[1]);
+ break;
+ case 3:
+ rv = (func) (p[0], p[1], p[2]);
+ break;
+ case 4:
+ rv = (func) (p[0], p[1], p[2], p[3]);
+ break;
+ case 5:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+ break;
+ case 6:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+ break;
+ case 7:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+ break;
+ case 8:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+ break;
+ case 9:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+ break;
+ case 10:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+ p[6], p[7], p[8], p[9]);
+ break;
+ default:
+ rv = SW_OUT_OF_RANGE;
+ }
+
+ SW_OUT_ON_ERROR(rv);
+ rv = output_parser(pp, nr_param, args);
+
+out:
+ up(&api_sem);
+ return rv;
+}
+
+static inline int pid_find(pid_t pid, pid_t pids[])
+{
+ a_uint32_t i, loc = PID_TAB_NOT_FOUND;
+
+ for(i = 0; i< PID_TAB_MAX; i++)
+ {
+ if(pids[i] == pid)
+ {
+ loc = i;
+ break;
+ }
+ }
+ return loc;
+}
+
+static inline a_bool_t pid_exit(pid_t parent_pid)
+{
+ struct task_struct *p;
+ a_bool_t rtn = A_TRUE;
+
+ for_each_process(p)
+ {
+ if(parent_pid == p->pid)
+ {
+ rtn = A_FALSE;
+ break;
+ }
+ }
+
+ return rtn;
+}
+
+static inline void pid_free(a_uint32_t loc)
+{
+ if (down_interruptible(&pid_tab_sem))
+ return;
+
+ pid_childs[loc] = 0;
+ pid_parents[loc] = 0;
+
+ up(&pid_tab_sem);
+}
+
+static inline a_bool_t pid_full(void)
+{
+ return (pid_find(0, pid_parents) == PID_TAB_NOT_FOUND)?A_TRUE:A_FALSE;
+}
+
+static a_uint32_t pid_find_save (pid_t parent_pid, pid_t child_pid)
+{
+ a_uint32_t loc = PID_TAB_NOT_FOUND;
+
+ if(!parent_pid && !child_pid)
+ {
+ dprintk("child and father can't both zero\n");
+ return loc;
+ }
+
+ if (down_interruptible(&pid_tab_sem))
+ return loc;
+
+ if(!parent_pid)
+ {
+ /*find locate by child_pid*/
+ loc = pid_find(child_pid, pid_childs);
+
+ }
+ else
+ {
+ /*find locate by parent_pid*/
+ loc = pid_find(parent_pid, pid_parents);
+
+ if(child_pid)
+ {
+ loc = pid_find(0, pid_parents);
+
+ if(loc != PID_TAB_NOT_FOUND)
+ {
+ pid_childs[loc] = child_pid;
+ pid_parents[loc] = parent_pid;
+ }
+ }
+ }
+
+ up(&pid_tab_sem);
+ return loc;
+}
+
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)
+static void
+sw_api_excep_ack(struct sock *sk, pid_t pid)
+{
+ sw_error_t rv = SW_NO_RESOURCE;
+ a_uint32_t args[SW_MAX_API_PARAM], rtn;
+ struct sk_buff *skb, *skb_first = NULL;
+ struct nlmsghdr *nlh = NULL;
+
+ while(1)
+ {
+#ifdef KVER26
+ skb = skb_dequeue(&sk->sk_receive_queue);
+#else
+ skb = skb_dequeue(&sk->receive_queue);
+#endif
+ if (!skb)
+ {
+ dprintk("pid error: skb = null\n");
+ return;
+ }
+
+ nlh = (struct nlmsghdr *)skb->data;
+ if (!nlh)
+ {
+ dprintk("pid error: nlh = null\n");
+ return;
+ }
+
+ if(nlh->nlmsg_pid == pid)
+ {
+ break;
+ }
+
+ if(!skb_first)
+ {
+ skb_first = skb;
+ }
+ else if (skb_first == skb)
+ {
+ dprintk("can't found my skb???\n");
+ return;
+ }
+
+#ifdef KVER26
+ skb_queue_tail(&sk->sk_receive_queue, skb);
+#else
+ skb_queue_tail(&sk->receive_queue, skb);
+#endif
+ }
+
+ aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+ /* return API result to user */
+ rtn = (a_uint32_t) rv;
+ if (copy_to_user
+ ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+ {
+ rv = SW_NO_RESOURCE;
+ }
+
+ NETLINK_CB(skb).pid = 0;
+ NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid;
+#ifdef KVER26
+ NETLINK_CB(skb).dst_group = 0;
+#else
+ NETLINK_CB(skb).dst_groups = 0;
+#endif
+
+ netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT);
+}
+
+static void
+sw_api_exec(struct sock *sk, pid_t pid)
+{
+ sw_error_t rv = SW_NO_RESOURCE;
+ a_uint32_t args[SW_MAX_API_PARAM], rtn;
+ struct sk_buff *skb, *skb_first = NULL;
+ struct nlmsghdr *nlh = NULL;
+
+ while(1)
+ {
+#ifdef KVER26
+ skb = skb_dequeue(&sk->sk_receive_queue);
+#else
+ skb = skb_dequeue(&sk->receive_queue);
+#endif
+ if (!skb)
+ {
+ dprintk("pid error: skb = null\n");
+ return;
+ }
+
+ nlh = (struct nlmsghdr *)skb->data;
+ if (!nlh)
+ {
+ dprintk("pid error: nlh = null\n");
+ return;
+ }
+
+ if(nlh->nlmsg_pid == pid)
+ {
+ break;
+ }
+
+ if(!skb_first)
+ {
+ skb_first = skb;
+ }
+ else if (skb_first == skb)
+ {
+ dprintk("can't found my skb???\n");
+ return;
+ }
+
+#ifdef KVER26
+ skb_queue_tail(&sk->sk_receive_queue, skb);
+#else
+ skb_queue_tail(&sk->receive_queue, skb);
+#endif
+ }
+
+ aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+
+ rv = sw_api_cmd(args);
+ /* return API result to user */
+ rtn = (a_uint32_t) rv;
+ if (copy_to_user
+ ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+ {
+ rv = SW_NO_RESOURCE;
+ }
+
+ NETLINK_CB(skb).pid = 0;
+ NETLINK_CB(skb).dst_pid = nlh->nlmsg_pid;
+#ifdef KVER26
+ NETLINK_CB(skb).dst_group = 0;
+#else
+ NETLINK_CB(skb).dst_groups = 0;
+#endif
+
+ netlink_unicast(sk, skb, nlh->nlmsg_pid, MSG_DONTWAIT);
+}
+
+
+static int sw_api_thread(void *sk)
+{
+ a_uint32_t loc, i;
+ pid_t parent_pid = 0, child_pid = current->pid;
+
+ while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND)
+ schedule_timeout(1*HZ);
+
+ parent_pid = pid_parents[loc];
+ dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc);
+
+ if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc))
+ {
+ for(i=0; ; i++)
+ {
+ if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ)))
+ {
+ if(pid_exit(parent_pid) == A_FALSE)
+ continue;
+
+ pid_free(loc);
+ dprintk("thread child[%d] exit!\n", child_pid);
+ return 0;
+ }
+
+ sw_api_exec(sk, parent_pid);
+ }
+ }
+ else
+ {
+ sw_api_exec(sk, parent_pid);
+ pid_free(loc);
+ }
+
+ return 0;
+}
+
+static void
+sw_api_netlink(struct sock *sk, int len)
+{
+ pid_t parent_pid = current->pid, child_pid = 0;
+ a_uint32_t loc = pid_find_save (parent_pid, child_pid);
+
+ if(loc == PID_TAB_NOT_FOUND)
+ {
+ if(pid_full())
+ {
+ dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid);
+ sw_api_excep_ack(sk, parent_pid);
+ return;
+ }
+#if 1
+ struct task_struct *p;
+ p = kthread_create(sw_api_thread, (void *)ssdk_nl_sk, "netlink_child");
+ if (IS_ERR(p))
+ {
+ dprintk("thread can't be created for netlink\n");
+ return;
+ }
+ child_pid = p->pid;
+#else
+ if ((child_pid = kernel_thread(sw_api_thread, ssdk_nl_sk, CLONE_KERNEL)) < 0)
+ {
+ dprintk("thread can't be created for netlink\n");
+ return;
+ }
+#endif
+ dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc);
+ pid_find_save(parent_pid, child_pid);
+ wake_up_process(p);
+ }
+ else
+ {
+ dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc);
+ wake_up(&pid_child_wait[loc]);
+ }
+
+ return;
+
+}
+
+#else
+
+static void
+sw_api_excep_ack_26_22(struct sk_buff *skb)
+{
+ sw_error_t rv = SW_NO_RESOURCE;
+ a_uint32_t args[SW_MAX_API_PARAM], rtn, size, dst_pid;
+ struct nlmsghdr *nlh = NULL;
+ struct sk_buff *rep;
+
+ nlh = (struct nlmsghdr *)skb->data;
+ if (!nlh)
+ {
+ dprintk("pid error: nlh = null\n");
+ return;
+ }
+ dst_pid = nlh->nlmsg_pid;
+
+ aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+ /* return API result to user */
+ rtn = (a_uint32_t) rv;
+ if (copy_to_user
+ ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+ {
+ rv = SW_NO_RESOURCE;
+ }
+
+ size = NLMSG_SPACE(0);
+ rep = alloc_skb(size, GFP_ATOMIC);
+ if (!rep)
+ {
+ dprintk("reply socket buffer allocation error... \n");
+ return;
+ }
+ nlh = nlmsg_put(rep, 0, 0, 0, 0, 0);
+
+ NETLINK_CB(rep).pid = 0;
+ NETLINK_CB(rep).dst_group = 0;
+ netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT);
+}
+
+static void
+sw_api_exec_26_22(pid_t parent_pid)
+{
+ sw_error_t rv = SW_NO_RESOURCE;
+ a_uint32_t loc, args[SW_MAX_API_PARAM], rtn, skblen, nlmsglen, size, dst_pid;
+ struct nlmsghdr *nlh = NULL;
+ struct sk_buff *skb;
+ struct sk_buff *rep;
+
+ loc = pid_find(parent_pid, pid_parents);
+ if (PID_TAB_NOT_FOUND == loc)
+ {
+ dprintk("parent PID not found - (%d)\n", parent_pid);
+ return;
+ }
+
+ skb = skb_array[loc];
+ if (!skb)
+ {
+ dprintk("skb null pointer error\n");
+ return;
+ }
+
+ skblen = skb->len;
+ if (skb->len < sizeof(nlh))
+ {
+ dprintk("skb len error - (%d)\n", skb->len);
+ SW_OUT_ON_ERROR(SW_ABORTED);
+ }
+
+ nlh = (struct nlmsghdr *)skb->data;
+ if (!nlh)
+ {
+ dprintk("pid error: nlh = null\n");
+ SW_OUT_ON_ERROR(SW_ABORTED);
+ }
+
+ nlmsglen = nlh->nlmsg_len;
+ if (nlmsglen < sizeof(*nlh) || skblen < nlmsglen)
+ {
+ dprintk("nlmsglen error - (%d)\n", nlmsglen);
+ SW_OUT_ON_ERROR(SW_ABORTED);
+ }
+ dst_pid = nlh->nlmsg_pid;
+
+ aos_mem_copy(args, NLMSG_DATA(nlh), SW_MAX_PAYLOAD);
+ rv = sw_api_cmd(args);
+
+ /* return API result to user */
+ rtn = (a_uint32_t) rv;
+ if (copy_to_user
+ ((void __USER *) args[1], (a_uint32_t *) & rtn, sizeof (a_uint32_t)))
+ {
+ rv = SW_NO_RESOURCE;
+ }
+
+ size = NLMSG_SPACE(0);
+ rep = alloc_skb(size, GFP_ATOMIC);
+ if (!rep)
+ {
+ dprintk("reply socket buffer allocation error... \n");
+ SW_OUT_ON_ERROR(SW_ABORTED);
+ }
+ nlh = nlmsg_put(rep, 0, 0, 0, 0, 0);
+
+ NETLINK_CB(rep).pid = 0;
+ NETLINK_CB(rep).dst_group = 0;
+ netlink_unicast(ssdk_nl_sk, rep, dst_pid, MSG_DONTWAIT);
+
+out:
+ skb_array[loc] = NULL;
+ kfree_skb(skb);
+}
+
+static int
+sw_api_thread_26_22(void * data)
+{
+ a_uint32_t loc, i;
+ pid_t parent_pid = 0, child_pid = current->pid;
+
+ while ((loc = pid_find_save(parent_pid, child_pid)) == PID_TAB_NOT_FOUND)
+ schedule_timeout(1*HZ);
+
+ parent_pid = pid_parents[loc];
+ dprintk("thread child [%d] find parent [%d] at %d \n", child_pid, parent_pid, loc);
+
+ if ((RSV_PID_LOC_0 == loc) || (RSV_PID_LOC_1 == loc))
+ {
+ for(i=0; ; i++)
+ {
+ if(i && !sleep_on_timeout(&pid_child_wait[loc], (5*HZ)))
+ {
+ if(pid_exit(parent_pid) == A_FALSE)
+ continue;
+
+ pid_free(loc);
+ dprintk("thread child[%d] exit!\n", child_pid);
+ return 0;
+ }
+
+ sw_api_exec_26_22(parent_pid);
+ }
+ }
+ else
+ {
+ sw_api_exec_26_22(parent_pid);
+ pid_free(loc);
+ }
+
+ return 0;
+}
+
+static void
+sw_api_netlink_26_22(struct sk_buff *skb)
+{
+ pid_t parent_pid = current->pid, child_pid = 0;
+ a_uint32_t loc = pid_find_save (parent_pid, child_pid);
+
+ if(loc == PID_TAB_NOT_FOUND)
+ {
+ if(pid_full())
+ {
+ dprintk("###threads exceed the max [%d] for pid [%d]!###\n", PID_TAB_MAX, parent_pid);
+ sw_api_excep_ack_26_22(skb);
+ return;
+ }
+
+ loc = pid_find_save(parent_pid, 0xffffffff);
+
+#if 1
+ struct task_struct *p;
+ p = kthread_create(sw_api_thread_26_22, (void *)ssdk_nl_sk, "netlink_child");
+ if (IS_ERR(p))
+ {
+ dprintk("thread can't be created for netlink\n");
+ return;
+ }
+
+ skb_array[loc] = skb_get(skb);
+ child_pid = p->pid;
+ pid_childs[loc] = child_pid;
+ wake_up_process(p);
+#else
+ if ((child_pid = kernel_thread(sw_api_thread_26_22, NULL, CLONE_KERNEL)) < 0)
+ {
+ dprintk("thread can't be created for netlink\n");
+ return;
+ }
+#endif
+ dprintk("[%d] create child [%d] at %d\n", parent_pid, child_pid, loc);
+ }
+ else
+ {
+ dprintk("[%d] wake up child [%d] at %d\n", parent_pid, pid_childs[loc], loc);
+ skb_array[loc] = skb_get(skb);
+ wake_up(&pid_child_wait[loc]);
+ }
+
+ return;
+}
+#endif
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+ a_uint32_t i, protocol;
+
+ if (!cmd_buf)
+ {
+ if((cmd_buf = (a_uint32_t *) aos_mem_alloc(SW_MAX_API_BUF)) == NULL)
+ return SW_OUT_OF_MEM;
+ }
+
+ if (!ssdk_nl_sk)
+ {
+#if defined UK_NL_PROT
+ protocol = UK_NL_PROT;
+#else
+ protocol = nl_prot;
+#endif
+
+#ifdef KVER26
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ ssdk_nl_sk = netlink_kernel_create(&init_net, protocol, 0, sw_api_netlink_26_22, NULL, THIS_MODULE);
+#else
+ ssdk_nl_sk = netlink_kernel_create(protocol, 0, sw_api_netlink, THIS_MODULE);
+#endif
+#else
+ ssdk_nl_sk = netlink_kernel_create(protocol, sw_api_netlink);
+#endif
+ if (!ssdk_nl_sk)
+ {
+ dprintk("netlink_kernel_create fail at nl_prot:[%d]\n", protocol);
+ return SW_NO_RESOURCE;
+ }
+ else
+ {
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
+ dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (>2.6.22)\n", protocol);
+#else
+ dprintk("netlink_kernel_create succeeded at nl_prot: [%d] (<2.6.22)\n", protocol);
+#endif
+ }
+ }
+
+ init_MUTEX(&pid_tab_sem);
+ init_MUTEX(&api_sem);
+
+ for(i = 0; i < PID_TAB_MAX; i++)
+ {
+ init_waitqueue_head(&pid_child_wait[i]);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+ if (cmd_buf)
+ {
+ aos_mem_free(cmd_buf);
+ cmd_buf = NULL;
+ }
+
+ if (ssdk_nl_sk)
+ {
+#ifdef KVER26
+ sock_release(ssdk_nl_sk->sk_socket);
+#else
+ sock_release(ssdk_nl_sk->socket);
+#endif
+ ssdk_nl_sk = NULL;
+ }
+
+ return SW_OK;
+}
+
diff --git a/src/sal/sd/linux/uk_interface/sw_api_us_ioctl.c b/src/sal/sd/linux/uk_interface/sw_api_us_ioctl.c
new file mode 100644
index 0000000..0aa2c29
--- /dev/null
+++ b/src/sal/sd/linux/uk_interface/sw_api_us_ioctl.c
@@ -0,0 +1,53 @@
+#include <sys/ioctl.h>
+#include <net/if.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/stat.h>
+#include <sys/sysmacros.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include "sw.h"
+#include "sw_api.h"
+#include "sw_api_us.h"
+
+#define MISC_CHR_DEV 10
+static int glb_socket_fd = 0;
+
+sw_error_t
+sw_uk_if(a_uint32_t arg_val[SW_MAX_API_PARAM])
+{
+ ioctl(glb_socket_fd, SIOCDEVPRIVATE, arg_val);
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+ if (!glb_socket_fd)
+ {
+ /* even mknod fail we not quit, perhaps the device node exist already */
+#if defined UK_MINOR_DEV
+ mknod("/dev/switch_ssdk", S_IFCHR, makedev(MISC_CHR_DEV, UK_MINOR_DEV));
+#else
+ mknod("/dev/switch_ssdk", S_IFCHR, makedev(MISC_CHR_DEV, nl_prot));
+#endif
+ if ((glb_socket_fd = open("/dev/switch_ssdk", O_RDWR)) < 0)
+ {
+ return SW_INIT_ERROR;
+ }
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+ close(glb_socket_fd);
+ glb_socket_fd = 0;
+#if 0
+ remove("/dev/switch_ssdk");
+#endif
+ return SW_OK;
+}
+
diff --git a/src/sal/sd/linux/uk_interface/sw_api_us_netlink.c b/src/sal/sd/linux/uk_interface/sw_api_us_netlink.c
new file mode 100644
index 0000000..ae8c9b9
--- /dev/null
+++ b/src/sal/sd/linux/uk_interface/sw_api_us_netlink.c
@@ -0,0 +1,214 @@
+#include <sys/socket.h>
+#include <linux/types.h>
+#include <linux/netlink.h>
+#include "sw.h"
+#include "sw_api.h"
+#include "sw_api_us.h"
+
+#define SSDK_SOCK_SEND_TRY_NUM 1000
+#define SSDK_SOCK_RCV_TRY_NUM 1000
+#define SSDK_SOCK_FD_NUM 16
+typedef struct
+{
+ a_uint32_t ssdk_sock_pid;
+ a_int32_t ssdk_sock_fd;
+} ssdk_sock_t;
+ssdk_sock_t ssdk_sock[SSDK_SOCK_FD_NUM];
+
+static a_uint32_t ssdk_sock_prot = 0;
+static struct nlmsghdr *nl_hdr = NULL;
+#if defined(API_LOCK)
+static aos_lock_t ssdk_sock_lock;
+#define SOCK_LOCKER_INIT aos_lock_init(&ssdk_sock_lock)
+#define SOCK_LOCKER_LOCK aos_lock(&ssdk_sock_lock)
+#define SOCK_LOCKER_UNLOCK aos_unlock(&ssdk_sock_lock)
+#else
+#define SOCK_LOCKER_INIT
+#define SOCK_LOCKER_LOCK
+#define SOCK_LOCKER_UNLOCK
+#endif
+
+static ssdk_sock_t *
+ssdk_sock_alloc(a_uint32_t pid)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < SSDK_SOCK_FD_NUM; i++)
+ {
+ if (!ssdk_sock[i].ssdk_sock_pid)
+ {
+ return &ssdk_sock[i];
+ }
+ else
+ {
+ if (0 != kill(ssdk_sock[i].ssdk_sock_pid, 0))
+ {
+ return &ssdk_sock[i];
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static ssdk_sock_t *
+ssdk_sock_find(a_uint32_t pid)
+{
+ a_uint32_t i;
+
+ for (i = 0; i < SSDK_SOCK_FD_NUM; i++)
+ {
+ if (ssdk_sock[i].ssdk_sock_pid == pid)
+ {
+ return &ssdk_sock[i];
+ }
+ }
+
+ return NULL;
+}
+
+sw_error_t
+sw_uk_if(a_uint32_t arg_val[SW_MAX_API_PARAM])
+{
+ struct sockaddr_nl src_addr;
+ struct sockaddr_nl dest_addr;
+ struct msghdr msg;
+ struct iovec iov;
+ struct nlmsghdr *nlh;
+ ssdk_sock_t * sock;
+ a_int32_t sock_fd;
+ a_uint32_t curr_pid;
+ sw_error_t rv = SW_OK;
+ a_uint32_t i, j, flag;
+
+ curr_pid = getpid();
+
+ SOCK_LOCKER_LOCK;
+ sock = ssdk_sock_find(curr_pid);
+ if (!sock)
+ {
+ sock = ssdk_sock_alloc(curr_pid);
+ if (!sock)
+ {
+ SW_OUT_ON_ERROR(SW_NO_RESOURCE);
+ }
+
+ sock_fd = socket(PF_NETLINK, SOCK_RAW, ssdk_sock_prot);
+ aos_mem_set(&src_addr, 0, sizeof(src_addr));
+ src_addr.nl_family = AF_NETLINK;
+ src_addr.nl_pid = curr_pid;
+ src_addr.nl_groups = 0;
+ bind(sock_fd, (struct sockaddr*)&src_addr, sizeof(src_addr));
+
+ sock->ssdk_sock_fd = sock_fd;
+ sock->ssdk_sock_pid = curr_pid;
+ }
+ else
+ {
+ sock_fd = sock->ssdk_sock_fd;
+ }
+
+ aos_mem_set(&dest_addr, 0, sizeof(dest_addr));
+ dest_addr.nl_family = AF_NETLINK;
+ dest_addr.nl_pid = 0;
+ dest_addr.nl_groups = 0;
+
+ nlh = nl_hdr;
+ aos_mem_set(nlh, 0, NLMSG_SPACE(SW_MAX_PAYLOAD));
+ nlh->nlmsg_len = NLMSG_SPACE(SW_MAX_PAYLOAD);
+ nlh->nlmsg_pid = curr_pid;
+ nlh->nlmsg_flags = 0;
+ aos_mem_copy(NLMSG_DATA(nlh), arg_val, SW_MAX_PAYLOAD);
+
+ iov.iov_base = (void *)nlh;
+ iov.iov_len = nlh->nlmsg_len;
+
+ aos_mem_set(&msg, 0, sizeof(msg));
+ msg.msg_name = (void *)&dest_addr;
+ msg.msg_namelen = sizeof(dest_addr);
+ msg.msg_iov = &iov;
+ msg.msg_iovlen = 1;
+
+ for (i = 0; i < SSDK_SOCK_SEND_TRY_NUM; i++)
+ {
+ if (0 < sendmsg(sock_fd, &msg, MSG_DONTWAIT))
+ {
+ break;
+ }
+ }
+
+ if (SSDK_SOCK_SEND_TRY_NUM <= i)
+ {
+ SW_OUT_ON_ERROR(SW_TIMEOUT);
+ }
+
+ flag = 0;
+ aos_mem_set(nlh, 0, NLMSG_SPACE(SW_MAX_PAYLOAD));
+ for (i = 0; i < SSDK_SOCK_RCV_TRY_NUM; i++)
+ {
+ for (j = 0; j < 1000; j++)
+ {
+ if (0 < recvmsg(sock_fd, &msg, MSG_DONTWAIT))
+ {
+ flag = 1;
+ break;
+ }
+ }
+
+ if (flag)
+ {
+ break;
+ }
+ else
+ {
+ aos_mdelay(10);
+ }
+ }
+
+ if (SSDK_SOCK_RCV_TRY_NUM <= i)
+ {
+ SW_OUT_ON_ERROR(SW_TIMEOUT);
+ }
+
+out:
+ SOCK_LOCKER_UNLOCK;
+ return rv;
+}
+
+sw_error_t
+sw_uk_init(a_uint32_t nl_prot)
+{
+ if (!nl_hdr)
+ {
+ nl_hdr = (struct nlmsghdr *)aos_mem_alloc(NLMSG_SPACE(SW_MAX_PAYLOAD));
+ }
+
+ if (!nl_hdr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+#if defined UK_NL_PROT
+ ssdk_sock_prot = UK_NL_PROT;
+#else
+ ssdk_sock_prot = nl_prot;
+#endif
+ SOCK_LOCKER_INIT;
+ aos_mem_zero(ssdk_sock, sizeof(ssdk_sock_t) * SSDK_SOCK_FD_NUM);
+ return SW_OK;
+}
+
+sw_error_t
+sw_uk_cleanup(void)
+{
+ aos_mem_zero(ssdk_sock, sizeof(ssdk_sock_t) * SSDK_SOCK_FD_NUM);
+
+ if (nl_hdr)
+ {
+ aos_mem_free(nl_hdr);
+ nl_hdr = NULL;
+ }
+
+ return SW_OK;
+}
+
diff --git a/src/sal/sd/sd.c b/src/sal/sd/sd.c
new file mode 100644
index 0000000..598adde
--- /dev/null
+++ b/src/sal/sd/sd.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+#include "sw.h"
+#include "ssdk_init.h"
+#include "sd.h"
+#include "sw_api.h"
+#include "sw_api_us.h"
+
+mdio_reg_set ssdk_mdio_set = NULL;
+mdio_reg_get ssdk_mdio_get = NULL;
+hdr_reg_set ssdk_hdr_reg_set = NULL;
+hdr_reg_get ssdk_hdr_reg_get = NULL;
+
+sw_error_t
+sd_reg_mdio_set(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg,
+ a_uint16_t data)
+{
+ sw_error_t rv = SW_OK;
+
+ if (NULL != ssdk_mdio_set)
+ {
+ rv = ssdk_mdio_set(dev_id, phy, reg, data);
+ }
+ else
+ {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+ {
+ a_uint32_t args[SW_MAX_API_PARAM];
+
+ args[0] = SW_API_PHY_SET;
+ args[1] = (a_uint32_t) & rv;
+ args[2] = dev_id;
+ args[3] = phy;
+ args[4] = reg;
+ args[5] = data;
+ if (SW_OK != sw_uk_if(args))
+ {
+ return SW_FAIL;
+ }
+ }
+#else
+ return SW_NOT_SUPPORTED;
+#endif
+ }
+
+ return rv;
+}
+
+sw_error_t
+sd_reg_mdio_get(a_uint32_t dev_id, a_uint32_t phy, a_uint32_t reg, a_uint16_t * data)
+{
+ sw_error_t rv = SW_OK;
+
+ if (NULL != ssdk_mdio_get)
+ {
+ rv = ssdk_mdio_get(dev_id, phy, reg, data);
+ }
+ else
+ {
+#if ((!defined(KERNEL_MODULE)) && defined(UK_IF))
+ {
+ a_uint32_t args[SW_MAX_API_PARAM];
+ a_uint32_t tmp;
+
+ args[0] = SW_API_PHY_GET;
+ args[1] = (a_uint32_t) & rv;
+ args[2] = dev_id;
+ args[3] = phy;
+ args[4] = reg;
+ args[5] = (a_uint32_t) & tmp;
+ if (SW_OK != sw_uk_if(args))
+ {
+ return SW_FAIL;
+ }
+ *data = *((a_uint16_t *)&tmp);
+ }
+#else
+ return SW_NOT_SUPPORTED;
+#endif
+ }
+
+ return rv;
+}
+
+sw_error_t
+sd_reg_hdr_set(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+ sw_error_t rv;
+
+ if (NULL != ssdk_hdr_reg_set)
+ {
+ rv = ssdk_hdr_reg_set(dev_id, reg_addr, reg_data, len);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ return rv;
+}
+
+sw_error_t
+sd_reg_hdr_get(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
+{
+ sw_error_t rv;
+
+ if (NULL != ssdk_hdr_reg_get)
+ {
+ rv = ssdk_hdr_reg_get(dev_id, reg_addr, reg_data, len);
+ }
+ else
+ {
+ return SW_NOT_SUPPORTED;
+ }
+
+ return rv;
+}
+
+sw_error_t
+sd_init(a_uint32_t dev_id, ssdk_init_cfg * cfg)
+{
+ if (NULL != cfg->reg_func.mdio_set)
+ {
+ ssdk_mdio_set = cfg->reg_func.mdio_set;
+ }
+
+ if (NULL != cfg->reg_func.mdio_get)
+ {
+ ssdk_mdio_get = cfg->reg_func.mdio_get;
+ }
+
+ if (NULL != cfg->reg_func.header_reg_set)
+ {
+ ssdk_hdr_reg_set = cfg->reg_func.header_reg_set;
+ }
+
+ if (NULL != cfg->reg_func.header_reg_get)
+ {
+ ssdk_hdr_reg_get = cfg->reg_func.header_reg_get;
+ }
+
+ return SW_OK;
+}
+
diff --git a/src/shell/Makefile b/src/shell/Makefile
new file mode 100644
index 0000000..a8ec731
--- /dev/null
+++ b/src/shell/Makefile
@@ -0,0 +1,24 @@
+LOC_DIR=src/shell
+LIB=SHELL
+
+include $(PRJ_PATH)/make/config.mk
+include $(PRJ_PATH)/make/components.mk
+
+SRC_LIST=$(wildcard *.c)
+ifeq (,$(findstring SHELL, $(COMPONENTS)))
+all: dep obj
+else
+all: dep obj lib
+endif
+
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+ifeq (TRUE, $(API_LOCK))
+ PT_LIB=-lpthread
+else
+ PT_LIB=
+endif
+
+lib:
+ $(CC) $(CFLAGS) $(OBJ_FILE) $(BIN_DIR)/$(US_MOD)_$(RUNMODE).a -o $(DST_DIR)/$(SHELLOBJ) $(PT_LIB)
diff --git a/src/shell/shell.c b/src/shell/shell.c
new file mode 100644
index 0000000..af099dc
--- /dev/null
+++ b/src/shell/shell.c
@@ -0,0 +1,798 @@
+#include <stdio.h>
+#include <stdarg.h>
+#include <pthread.h>
+#include "shell.h"
+#include "shell_io.h"
+#include "shell_sw.h"
+#include "shell_lib.h"
+#include "shell_config.h"
+#include "api_access.h"
+
+a_uint32_t *ioctl_buf;
+ssdk_init_cfg init_cfg = def_init_cfg;
+
+static a_uint32_t *ioctl_argp;
+static FILE * out_fd;
+static char *err_info[] =
+{
+ "Operation succeeded", /*SW_OK*/
+ "Operation failed", /*SW_FAIL*/
+ "Illegal value ", /*SW_BAD_VALUE*/
+ "Value is out of range ", /*SW_OUT_OF_RANGE*/
+ "Illegal parameter(s) ", /*SW_BAD_PARAM*/
+ "Illegal pointer value ", /*SW_BAD_PTR*/
+ "Wrong length", /*SW_BAD_LEN*/
+ "Wrong state of state machine ", /*SW_BAD_STATE*/
+ "Read operation failed ", /*SW_READ_ERROR*/
+ "Write operation failed ", /*SW_WRITE_ERROR*/
+ "Fail in creating an entry ", /*SW_CREATE_ERROR*/
+ "Fail in deleteing an entry ", /*SW_DELETE_ERROR*/
+ "Entry not found ", /*SW_NOT_FOUND*/
+ "The parameter(s) is the same ", /*SW_NO_CHANGE*/
+ "No more entry found ", /*SW_NO_MORE*/
+ "No such entry ", /*SW_NO_SUCH*/
+ "Tried to create existing entry ", /*SW_ALREADY_EXIST*/
+ "Table is full ", /*SW_FULL*/
+ "Table is empty ", /*SW_EMPTY*/
+ "This request is not support ", /*SW_NOT_SUPPORTED*/
+ "This request is not implemented", /*SW_NOT_IMPLEMENTED*/
+ "The item is not initialized ", /*SW_NOT_INITIALIZED*/
+ "Operation is still running", /*SW_BUSY*/
+ "Operation Time Out ", /*SW_TIMEOUT*/
+ "Operation is disabled ", /*SW_DISABLE*/
+ "Resource not available (memory ...)", /*SW_NO_RESOURCE*/
+ "Error occured while INIT process", /*SW_INIT_ERROR*/
+ "The other side is not ready yet", /*SW_NOT_READY */
+ "Cpu memory allocation failed. ", /*SW_OUT_OF_MEM */
+ "Operation has been aborted. ", /*SW_ABORTED*/
+} ;
+
+void
+cmd_print_error(sw_error_t rtn)
+{
+ dprintf("\n%s\n\n", err_info[abs(rtn)]);
+}
+
+void
+cmd_print(char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ if(out_fd)
+ vfprintf(out_fd, fmt, args);
+ else
+ vfprintf(stdout, fmt, args);
+ va_end(args);
+}
+
+static sw_error_t
+cmd_input_parser(a_uint32_t *arg_val, a_uint32_t arg_index, sw_api_param_t *pp)
+{
+ a_int16_t i;
+ a_uint32_t *pbuf;
+ a_uint16_t rtn_size = 1;
+ sw_api_param_t *pptmp;
+
+ pbuf = ioctl_buf + rtn_size; /*reserve for return value */
+
+ for (i = 0; i < arg_index; i++)
+ {
+ pptmp = pp + i;
+ if (pptmp->param_type & SW_PARAM_PTR)
+ {
+ pbuf += (pptmp->data_size + 3) / 4;
+ }
+ }
+ if ((pbuf - ioctl_buf + (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4))
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ *arg_val = (a_uint32_t) pbuf;
+
+ return SW_OK;
+}
+
+static sw_error_t
+cmd_api_func(sw_api_func_t *fp, a_uint32_t nr_param, a_uint32_t * args)
+{
+ a_uint32_t *p = &args[2];
+ sw_error_t rv;
+ sw_error_t(*func) ();
+
+ func = fp->func;
+
+ switch (nr_param)
+ {
+ case 0:
+ rv = (func) ();
+ break;
+ case 1:
+ rv = (func) (p[0]);
+ break;
+ case 2:
+ rv = (func) (p[0], p[1]);
+ break;
+ case 3:
+ rv = (func) (p[0], p[1], p[2]);
+ break;
+ case 4:
+ rv = (func) (p[0], p[1], p[2], p[3]);
+ break;
+ case 5:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4]);
+ break;
+ case 6:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5]);
+ break;
+ case 7:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6]);
+ break;
+ case 8:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+ break;
+ case 9:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
+ break;
+ case 10:
+ rv = (func) (p[0], p[1], p[2], p[3], p[4], p[5],
+ p[6], p[7], p[8], p[9]);
+ break;
+ default:
+ rv = SW_OUT_OF_RANGE;
+ }
+
+ *(a_uint32_t *) args[1] = rv;
+
+ return rv;
+}
+
+static sw_error_t
+cmd_api_output(sw_api_param_t *pp, a_uint32_t nr_param, a_uint32_t * args)
+{
+ a_uint16_t i;
+ a_uint32_t *pbuf;
+ a_uint16_t rtn_size = 1;
+ sw_error_t rtn = (sw_error_t) (*ioctl_buf);
+ sw_api_param_t *pptmp = NULL;
+
+ if (rtn != SW_OK)
+ {
+ cmd_print_error(rtn);
+ return rtn;
+ }
+
+ pbuf = ioctl_buf + rtn_size;
+ for (i = 0; i < nr_param; i++)
+ {
+ pptmp = pp + i;
+ if (pptmp->param_type & SW_PARAM_PTR)
+ {
+
+ if (pptmp->param_type & SW_PARAM_OUT)
+ {
+
+ sw_data_type_t *data_type;
+ if (!(data_type = cmd_data_type_find(pptmp->data_type)))
+ return SW_NO_SUCH;
+
+ if (data_type->show_func)
+ {
+ data_type->show_func(pptmp->param_name, pbuf, pptmp->data_size);
+ }
+ else
+ {
+ dprintf("\n Error, not define output print function!");
+ }
+ }
+
+ if ((pbuf - ioctl_buf +
+ (pptmp->data_size + 3) / 4) > (IOCTL_BUF_SIZE/4))
+ return SW_NO_RESOURCE;
+
+ pbuf += (pptmp->data_size + 3) / 4;
+
+ }
+ }
+ return SW_OK;
+}
+
+void
+cmd_strtol(char *str, a_uint32_t * arg_val)
+{
+ if (str[0] == '0' && (str[1] == 'x' || str[1] == 'X'))
+ sscanf(str, "%x", arg_val);
+ else
+ sscanf(str, "%d", arg_val);
+}
+
+static sw_error_t
+cmd_parse_api(char **cmd_str, a_uint32_t * arg_val)
+{
+ char *tmp_str;
+ a_uint32_t arg_index, arg_start = 2, reserve_index = 1; /*reserve for dev_id */
+ a_uint32_t last_param_in = 0;
+ a_uint32_t *temp;
+ void *pentry;
+ sw_api_param_t *pptmp = NULL;
+ sw_api_t sw_api;
+ a_uint32_t ignorecnt = 0;
+ sw_api.api_id = arg_val[0];
+ SW_RTN_ON_ERROR(sw_api_get(&sw_api));
+
+ /*set device id */
+ arg_val[arg_start] = get_devid();
+
+ for (arg_index = reserve_index; arg_index < sw_api.api_nr; arg_index++)
+ {
+ tmp_str = NULL;
+ pptmp = sw_api.api_pp + arg_index;
+
+ if (!(pptmp->param_type & SW_PARAM_IN))
+ {
+ ignorecnt++;
+ }
+
+ if (pptmp->param_type & SW_PARAM_IN)
+ {
+ tmp_str = cmd_str[arg_index - reserve_index - ignorecnt];
+ last_param_in = arg_index;
+ if((pptmp->api_id == 314) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_NEXT wr
+ if((pptmp->api_id == 327) && last_param_in == 2) last_param_in = 4;//SW_API_FDB_EXTEND_FIRST wr
+ }
+ temp = &arg_val[arg_start + arg_index];
+
+ sw_data_type_t *data_type;
+ if (!(data_type = cmd_data_type_find(pptmp->data_type)))
+ return SW_NO_SUCH;
+
+ pentry = temp;
+ if (pptmp->param_type & SW_PARAM_PTR)
+ {
+ if (cmd_input_parser(temp, arg_index, sw_api.api_pp) != SW_OK)
+ return SW_NO_RESOURCE;
+
+ pentry = (void *) *temp;
+ }
+
+ if (pptmp->param_type & SW_PARAM_IN)
+ {
+#if 1
+ if(pptmp->param_type & SW_PARAM_PTR) //quiet mode
+ {
+ if(!get_talk_mode())
+ set_full_cmdstrp((char **)(cmd_str + (last_param_in - reserve_index)));
+ }
+#endif
+ /*check and convert input param */
+ if (data_type->param_check != NULL)
+ {
+ if (data_type->param_check(tmp_str, pentry, pptmp->data_size) != SW_OK)
+ return SW_BAD_PARAM;
+ }
+ }
+ }
+
+ /*superfluous args */
+ /*
+ if(cmd_str[last_param_in] != NULL)
+ return SW_BAD_PARAM;
+ */
+
+ return SW_OK;
+}
+
+static sw_error_t
+cmd_parse_sw(char **cmd_str, a_uint32_t * arg_val)
+{
+ char *tmp_str;
+ a_uint32_t arg_index = 0;
+ a_uint32_t api_id = arg_val[0];
+
+ tmp_str = cmd_str[arg_index];
+ while (tmp_str)
+ {
+ arg_index++;
+ cmd_strtol(tmp_str, &arg_val[arg_index]);
+ tmp_str = cmd_str[arg_index];
+ }
+
+ /*args number check */
+ if ( (arg_index == 0 && ( api_id == SW_CMD_VLAN_SHOW ||
+ api_id == SW_CMD_FDB_SHOW ||
+ api_id == SW_CMD_RESV_FDB_SHOW ||
+ api_id == SW_CMD_HOST_SHOW ||
+ api_id == SW_CMD_NAT_SHOW ||
+ api_id == SW_CMD_NAPT_SHOW ||
+ api_id == SW_CMD_INTFMAC_SHOW ||
+ api_id == SW_CMD_PUBADDR_SHOW )) ||
+ ( arg_index == 1 && api_id == SW_CMD_SET_DEVID) )
+ return SW_OK;
+
+ return SW_BAD_PARAM;
+}
+
+/*user command api*/
+sw_error_t
+cmd_exec_api(a_uint32_t *arg_val)
+{
+ sw_error_t rv;
+ sw_api_t sw_api;
+
+ sw_api.api_id = arg_val[0];
+ SW_RTN_ON_ERROR(sw_api_get(&sw_api));
+
+ /*save cmd return value */
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ /*save set device id */
+ arg_val[2] = get_devid();
+
+ rv = cmd_api_func(sw_api.api_fp, sw_api.api_nr, arg_val);
+ SW_RTN_ON_ERROR(rv);
+
+ rv = cmd_api_output(sw_api.api_pp, sw_api.api_nr, arg_val);
+ SW_RTN_ON_ERROR(rv);
+
+ return rv;
+}
+
+
+void
+cmd_print_usage (int cmd_index, int cmd_index_sub)
+{
+ if(GCMD_NAME(cmd_index))
+ dprintf("usage: %s", GCMD_NAME(cmd_index));
+
+ if (GCMD_SUB_NAME(cmd_index, cmd_index_sub))
+ dprintf(" %s", GCMD_SUB_NAME(cmd_index, cmd_index_sub));
+
+ if(GCMD_SUB_ACT(cmd_index, cmd_index_sub) && GCMD_SUB_USAGE(cmd_index, cmd_index_sub))
+ dprintf(" %s %s\n\n", GCMD_SUB_ACT(cmd_index, cmd_index_sub),
+ GCMD_SUB_USAGE(cmd_index, cmd_index_sub));
+}
+/*
+ main function
+ input args:
+ arg_val[0] = cmd_num
+ arg_val[1] = rtn_code
+ arg_val[2] = dev_id
+ arg_val[3] = dbg_cmd_num or other
+*/
+
+/*command string lookup*/
+a_uint32_t
+cmd_lookup(char **cmd_str, int *cmd_index, int *cmd_index_sub)
+{
+ a_uint32_t no, sub_no;
+ a_uint32_t cmd_deepth = 0;
+
+ *cmd_index = GCMD_DESC_NO_MATCH;
+ *cmd_index_sub = GCMD_DESC_NO_MATCH;
+
+ if (cmd_str[0] == NULL)
+ return cmd_deepth;
+
+ for (no = 0; GCMD_DESC_VALID(no); no++)
+ {
+ if (strcasecmp(cmd_str[0], GCMD_NAME(no)))
+ continue;
+
+ for (sub_no = 0; GCMD_SUB_DESC_VALID(no, sub_no); sub_no++)
+ {
+ if (cmd_str[1] != NULL && cmd_str[2] != NULL)
+ {
+
+ if (GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+ && !strcasecmp(cmd_str[1], GCMD_SUB_NAME(no, sub_no))
+ && !strcasecmp(cmd_str[2], GCMD_SUB_ACT(no, sub_no)))
+ {
+ *cmd_index = no;
+ *cmd_index_sub = sub_no;
+ cmd_deepth = 3;
+ return cmd_deepth;
+ }
+
+ else if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+ && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no)))
+ {
+ *cmd_index = no;
+ *cmd_index_sub = sub_no;
+ cmd_deepth = 2;
+ return cmd_deepth;
+ }
+ }
+ else if (cmd_str[1] != NULL && cmd_str[2] == NULL)
+ {
+
+ if (!GCMD_SUB_NAME(no, sub_no) && GCMD_SUB_ACT(no, sub_no)
+ && !strcasecmp(cmd_str[1], GCMD_SUB_ACT(no, sub_no)))
+ {
+ *cmd_index = no;
+ *cmd_index_sub = sub_no;
+ cmd_deepth = 2;
+ return cmd_deepth;
+ }
+ }
+ }
+ }
+
+ return cmd_deepth;
+}
+
+static a_uint32_t *
+cmd_parse(char *cmd_str, int *cmd_index, int *cmd_index_sub)
+{
+ int cmd_nr = 0;
+ a_uint32_t *arg_val = ioctl_argp;
+ char *tmp_str[CMDSTR_ARGS_MAX];
+
+ if (cmd_str == NULL)
+ return NULL;
+
+ memset(arg_val, 0, CMDSTR_ARGS_MAX * sizeof (a_uint32_t));
+
+ /* split string into array */
+ if ((tmp_str[cmd_nr] = (void *) strtok(cmd_str, " ")) == NULL)
+ return NULL;
+
+ /*handle help */
+ if (!strcasecmp(tmp_str[cmd_nr], "help"))
+ {
+ dprintf("input ? get help\n\n");
+ return NULL;
+ }
+
+ while (tmp_str[cmd_nr])
+ {
+ if (++cmd_nr == 3)
+ break;
+ tmp_str[cmd_nr] = (void *) strtok(NULL, " ");
+ }
+
+ /*commond string lookup */
+ int cmd_depth = cmd_lookup(tmp_str, cmd_index, cmd_index_sub);
+
+ if (*cmd_index == GCMD_DESC_NO_MATCH || *cmd_index_sub == GCMD_DESC_NO_MATCH)
+ {
+ dprintf("invalid or incomplete command.\n\n");
+ return NULL;
+ }
+
+ /*parse param */
+ cmd_nr = 0;
+ if (cmd_depth == 2)
+ {
+ tmp_str[cmd_nr] = tmp_str[2];
+ cmd_nr++;
+ }
+
+ tmp_str[cmd_nr] = (void *) strtok(NULL, " ");
+ while (tmp_str[cmd_nr])
+ {
+ if (++cmd_nr == CMDSTR_ARGS_MAX)
+ break;
+ tmp_str[cmd_nr] = (void *) strtok(NULL, " ");
+ }
+
+ arg_val[0] = GCMD_SUB_API(*cmd_index, *cmd_index_sub);
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+
+ int rtn_code;
+ if (arg_val[0] < SW_API_MAX)
+ {
+ /*api command parse */
+ rtn_code = cmd_parse_api(tmp_str, arg_val);
+
+ }
+ else if (arg_val[0] > SW_API_MAX)
+ {
+ /*user command parse */
+ rtn_code = cmd_parse_sw(tmp_str, arg_val);
+
+ }
+ else
+ {
+ rtn_code = SW_BAD_PARAM;
+ }
+
+ if(rtn_code != SW_OK)
+ {
+ cmd_print_error(rtn_code);
+
+ if(rtn_code == SW_BAD_PARAM)
+ cmd_print_usage(*cmd_index, *cmd_index_sub);
+
+ return NULL;
+ }
+
+ return arg_val;
+}
+
+static int
+cmd_exec(a_uint32_t *arg_val, int cmd_index, int cmd_index_sub)
+{
+ a_uint32_t api_id = arg_val[0];
+ sw_error_t rtn;
+
+ if( api_id < SW_API_MAX )
+ {
+ rtn = cmd_exec_api(arg_val);
+
+ }
+ else if ((api_id > SW_API_MAX ) && (api_id < SW_CMD_MAX))
+ {
+ if (GCMD_SUB_FUNC(cmd_index, cmd_index_sub))
+ rtn = GCMD_SUB_FUNC(cmd_index, cmd_index_sub)(arg_val);
+ }
+ else
+ {
+ rtn = SW_BAD_PARAM;
+ }
+
+ if(rtn != SW_OK)
+ cmd_print_error(rtn);
+ else
+ dprintf("\noperate done.\n\n");
+
+ return 0;
+}
+
+static int
+cmd_socket_init()
+{
+ sw_error_t rv;
+ garuda_init_spec_cfg chip_spec_cfg;
+
+ aos_mem_set(&chip_spec_cfg, 0 ,sizeof(garuda_init_spec_cfg));
+
+ init_cfg.cpu_mode = HSL_CPU_1;
+ init_cfg.reg_mode = HSL_MDIO;
+#if defined UK_MINOR_DEV
+ init_cfg.nl_prot = UK_MINOR_DEV;
+#else
+ init_cfg.nl_prot = 30;
+#endif
+ init_cfg.chip_type=CHIP_UNSPECIFIED;
+ init_cfg.reg_func.mdio_set = NULL;
+ init_cfg.reg_func.mdio_get = NULL;
+ init_cfg.chip_spec_cfg = &chip_spec_cfg;
+
+ rv = ssdk_init(0, &init_cfg);
+ if (SW_OK == rv)
+ {
+ dprintf("\n SSDK Init OK!");
+ }
+ else
+ {
+ dprintf("\n SSDK Init Fail! RV[%d]", rv);
+ }
+ return (int)rv;
+}
+
+static sw_error_t
+cmd_init(void)
+{
+ ioctl_buf = (a_uint32_t *) malloc(IOCTL_BUF_SIZE);
+ ioctl_argp = (a_uint32_t *) malloc(CMDSTR_ARGS_MAX * sizeof (a_uint32_t));
+ cmd_socket_init();
+
+ return SW_OK;
+}
+
+static sw_error_t
+cmd_exit(void)
+{
+ free(ioctl_buf);
+ free(ioctl_argp);
+ ssdk_cleanup();
+ return SW_OK;
+}
+
+static sw_error_t
+cmd_run_one(char *cmd_str)
+{
+ a_uint32_t *arg_list;
+ int cmd_index = 0, cmd_index_sub = 0;
+
+ if ((arg_list = cmd_parse(cmd_str, &cmd_index, &cmd_index_sub)) != NULL)
+ {
+ cmd_exec(arg_list, cmd_index, cmd_index_sub);
+ }
+
+ return SW_OK;
+}
+
+int
+cmd_is_batch(const char *cmd_str)
+{
+ char batch_cmd[] = "run";
+
+ if(!strncmp(cmd_str, batch_cmd, strlen(batch_cmd)))
+ return 1;
+ return 0;
+}
+
+static void
+cmd_batch_help(void)
+{
+ dprintf("usage:run <cmd_file> <result_file>\n");
+}
+
+static sw_error_t
+cmd_run_batch (char *cmd_str)
+{
+ FILE *in_fd = NULL;
+ char * line = NULL;
+ char *tmp_str[2];
+
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ /*usage: run cmd result*/
+ if((tmp_str[0] = (void *) strtok(cmd_str, " ")) == NULL)
+ return SW_BAD_PARAM;
+
+ /*check again*/
+ if(!cmd_is_batch(tmp_str[0]))
+ return SW_BAD_PARAM;
+
+ if((tmp_str[1] = (void *) strtok(NULL, " "))== NULL)
+ return SW_BAD_PARAM;
+ if((tmp_str[2] = (void *) strtok(NULL, " "))== NULL)
+ return SW_BAD_PARAM;
+
+ if((in_fd = fopen(tmp_str[1], "r")) == NULL)
+ {
+ dprintf("can't open cmd file %s\n", tmp_str[1]);
+ return SW_FAIL;
+ }
+ if((out_fd = fopen(tmp_str[2], "w+")) == NULL)
+ {
+ dprintf("can't open result file %s\n", tmp_str[2]);
+ return SW_FAIL;
+ }
+
+ size_t len = 0;
+ ssize_t read;
+
+ set_talk_mode(0);
+ while ((read = getline(&line, &len, in_fd)) != -1)
+ {
+ //dprintf("(%d)%s",read, line);
+ if(read <= 1 ) continue;
+
+ if(line[strlen(line)-1] == '\n');
+ line[strlen(line)-1] = '\0';
+
+ if(!strncmp(line, "echo", 4))
+ {
+ dprintf("%s\n", line+strlen("echo "));
+ continue;
+ }
+ else
+ {
+ dprintf("%s\n", line);
+ }
+ cmd_run_one(line);
+ }
+ set_talk_mode(1);
+
+ if (line) free(line);
+
+ fclose(out_fd);
+ fclose(in_fd);
+ out_fd = 0;
+ in_fd =0;
+
+ return SW_OK;
+
+}
+
+static sw_error_t
+cmd_args(char *cmd_str, int argc, const char *argv[])
+{
+ /*quiet mode*/
+ set_talk_mode(0);
+
+ if(cmd_is_batch(argv[1]))
+ {
+ if(argc != 4)
+ {
+ cmd_batch_help();
+ return SW_FAIL;
+ }
+
+ sprintf(cmd_str, "%s %s %s", argv[1], argv[2], argv[3]);
+ cmd_run_batch(cmd_str);
+
+ }
+ else
+ {
+ int argi;
+ for(argi = 1; argi < argc; argi++)
+ {
+ strcat(cmd_str, argv[argi]);
+ strcat(cmd_str, " ");
+ }
+ cmd_run_one(cmd_str);
+ }
+
+ return SW_OK;
+}
+
+int
+cmd_is_exit(char *cmd_str)
+{
+ if ((!strcasecmp(cmd_str, "q")) || (!strcasecmp(cmd_str, "quit")))
+ {
+ return 1;
+ }
+ return 0;
+}
+
+void cmd_welcome()
+{
+ char *ver = "", *date = "";
+#ifdef VERSION
+ ver = VERSION;
+#endif
+
+#ifdef BUILD_DATE
+ date = BUILD_DATE;
+#endif
+
+ dprintf("\n Welcome to SSDK Shell version: %s, at %s.\n", ver, date);
+}
+
+/* Dummy function to avoid linker complaints */
+void __aeabi_unwind_cpp_pr0(void)
+{
+};
+void __aeabi_unwind_cpp_pr1(void)
+{
+};
+
+int
+main(int argc, const char *argv[])
+{
+ char cmd_str[CMDSTR_BUF_SIZE];
+
+ cmd_init();
+
+ if(argc > 1)
+ {
+ memset(cmd_str, 0, sizeof(cmd_str));
+ cmd_args(cmd_str, argc, argv);
+ cmd_exit();
+ return 0;
+ }
+
+ cmd_welcome();
+
+ /*main loop*/
+ while (1)
+ {
+ memset(cmd_str, 0, sizeof(cmd_str));
+
+ if(next_cmd(cmd_str) == 0)/*loop through if '\n'*/
+ continue;
+
+ if (cmd_is_exit(cmd_str))
+ break;
+
+ if(cmd_is_batch(cmd_str))
+ {
+ if(cmd_run_batch(cmd_str)!= SW_OK)
+ cmd_batch_help();
+ }
+ else
+ {
+ cmd_run_one(cmd_str);
+ }
+ }
+
+ cmd_exit();
+ return 0;
+}
+
diff --git a/src/shell/shell_config.c b/src/shell/shell_config.c
new file mode 100644
index 0000000..42ee0ed
--- /dev/null
+++ b/src/shell/shell_config.c
@@ -0,0 +1,693 @@
+#include "shell_config.h"
+#include "shell_sw.h"
+
+
+/*cmdline tree descript*/
+struct cmd_des_t gcmd_des[] =
+{
+ /*port ctrl*/
+#ifdef IN_PORTCONTROL
+ {
+ "port", "config port control",
+ {
+ {"duplex", "get", "get duplex mode of a port", "<port_id>" , SW_API_PT_DUPLEX_GET, NULL},
+ {"duplex", "set", "set duplex mode of a port", "<port_id> <half|full>", SW_API_PT_DUPLEX_SET, NULL},
+ {"speed", "get", "get speed mode of a port", "<port_id>", SW_API_PT_SPEED_GET, NULL},
+ {"speed", "set", "set speed mode of a port", "<port_id> <10|100|1000>", SW_API_PT_SPEED_SET, NULL},
+ {"autoAdv", "get", "get auto-negotiation advertisement of a port", "<port_id>", SW_API_PT_AN_ADV_GET, NULL},
+ {"autoAdv", "set", "set auto-negotiation advertisement of a port", "<port_id> <cap_bitmap>", SW_API_PT_AN_ADV_SET, NULL},
+ {"autoNeg", "get", "get auto-negotiation status of a port", "<port_id>", SW_API_PT_AN_GET, NULL},
+ {"autoNeg", "enable", "enable auto-negotiation of a port", "<port_id>", SW_API_PT_AN_ENABLE, NULL},
+ {"autoNeg", "restart", "restart auto-negotiation process of a port", "<port_id>", SW_API_PT_AN_RESTART, NULL},
+ {"header", "set", "set atheros header/tag status of a port", "<port_id> <enable|disable>", SW_API_PT_HDR_SET, NULL},
+ {"header", "get", "get atheros header/tag status of a port", "<port_id>", SW_API_PT_HDR_GET, NULL},
+ {"txhdr", "set", "set tx frame atheros header/tag status of a port", "<port_id> <noheader|onlymanagement|allframe>", SW_API_PT_TXHDR_SET, NULL},
+ {"txhdr", "get", "get tx frame atheros header/tag status of a port", "<port_id>", SW_API_PT_TXHDR_GET, NULL},
+ {"rxhdr", "set", "set rx frame atheros header/tag status of a port", "<port_id> <noheader|onlymanagement|allframe>", SW_API_PT_RXHDR_SET, NULL},
+ {"rxhdr", "get", "get rx frame atheros header/tag status of a port", "<port_id>", SW_API_PT_RXHDR_GET, NULL},
+ {"hdrtype", "set", "set atheros header/tag type", "<enable|disable> <type 0x-0xffff>", SW_API_HEADER_TYPE_SET, NULL},
+ {"hdrtype", "get", "get atheros header/tag type", "", SW_API_HEADER_TYPE_GET, NULL},
+ {"flowCtrl", "set", "set flow control status of a port", "<port_id> <enable|disable>", SW_API_PT_FLOWCTRL_SET, NULL},
+ {"flowCtrl", "get", "get flow control status of a port", "<port_id>", SW_API_PT_FLOWCTRL_GET, NULL},
+ {"flowCtrlforcemode", "set", "set flow control force mode of a port", "<port_id> <enable|disable>", SW_API_PT_FLOWCTRL_MODE_SET, NULL},
+ {"flowCtrlforcemode", "get", "get flow control force mode of a port", "<port_id>", SW_API_PT_FLOWCTRL_MODE_GET, NULL},
+ {"powersave", "set", "set powersave status of a port", "<port_id> <enable|disable>", SW_API_PT_POWERSAVE_SET, NULL},
+ {"powersave", "get", "get powersave status of a port", "<port_id>", SW_API_PT_POWERSAVE_GET, NULL},
+ {"hibernate", "set", "set hibernate status of a port", "<port_id> <enable|disable>", SW_API_PT_HIBERNATE_SET, NULL},
+ {"hibernate", "get", "get hibernate status of a port", "<port_id>", SW_API_PT_HIBERNATE_GET, NULL},
+ {"cdt", "run", "run cable diagnostic test of a port", "<port_id> <mdi_pair>", SW_API_PT_CDT, NULL},
+ {"txmacstatus", "set", "set txmac status of a port", "<port_id> <enable|disable>", SW_API_TXMAC_STATUS_SET, NULL},
+ {"txmacstatus", "get", "get txmac status of a port", "<port_id>", SW_API_TXMAC_STATUS_GET, NULL},
+ {"rxmacstatus", "set", "set rxmac status of a port", "<port_id> <enable|disable>", SW_API_RXMAC_STATUS_SET, NULL},
+ {"rxmacstatus", "get", "get rxmac status of a port", "<port_id>", SW_API_RXMAC_STATUS_GET, NULL},
+ {"txfcstatus", "set", "set tx flow control status of a port", "<port_id> <enable|disable>", SW_API_TXFC_STATUS_SET, NULL},
+ {"txfcstatus", "get", "get tx flow control status of a port", "<port_id>", SW_API_TXFC_STATUS_GET, NULL},
+ {"rxfcstatus", "set", "set rx flow control status of a port", "<port_id> <enable|disable>", SW_API_RXFC_STATUS_SET, NULL},
+ {"rxfcstatus", "get", "get rx flow control status of a port", "<port_id>", SW_API_RXFC_STATUS_GET, NULL},
+ {"bpstatus", "set", "set back pressure status of a port", "<port_id> <enable|disable>", SW_API_BP_STATUS_SET, NULL},
+ {"bpstatus", "get", "get back pressure status of a port", "<port_id>", SW_API_BP_STATUS_GET, NULL},
+ {"linkforcemode", "set", "set link force mode of a port", "<port_id> <enable|disable>", SW_API_PT_LINK_MODE_SET, NULL},
+ {"linkforcemode", "get", "get link force mode of a port", "<port_id>", SW_API_PT_LINK_MODE_GET, NULL},
+ {"linkstatus", "get", "get link status of a port", "<port_id>", SW_API_PT_LINK_STATUS_GET, NULL},
+ {"macLoopback", "set", "set mac level loop back mode of port", "<port_id> <enable|disable>", SW_API_PT_MAC_LOOPBACK_SET, NULL},
+ {"macLoopback", "get", "get mac level loop back mode of port", "<port_id>", SW_API_PT_MAC_LOOPBACK_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL},/*end of desc*/
+ },
+ },
+#endif
+
+ /*vlan*/
+#ifdef IN_VLAN
+ {
+ "vlan", "config VLAN table",
+ {
+ {"entry", "create", "create a VLAN entry", "<vlan_id>", SW_API_VLAN_ADD, NULL},
+ {"entry", "del", "delete a VLAN entryn", "<vlan_id>", SW_API_VLAN_DEL, NULL},
+ {"entry", "update", "update port member of a VLAN entry", "<vlan_id> <member_bitmap> <0>", SW_API_VLAN_MEM_UPDATE, NULL},
+ {"entry", "find", "find a VLAN entry by VLAN id", "<vlan_id>", SW_API_VLAN_FIND, NULL},
+ {"entry", "next", "find next VLAN entry by VLAN id", "<vlan_id>",SW_API_VLAN_NEXT, NULL},
+ {"entry", "append", "append a VLAN entry", "", SW_API_VLAN_APPEND, NULL},
+ {"entry", "flush", "flush all VLAN entries", "",SW_API_VLAN_FLUSH, NULL},
+ {"entry", "show", "show whole VLAN entries", "", SW_CMD_VLAN_SHOW, cmd_show_vlan},
+ {"fid", "set", "set VLAN entry fid", "<vlan_id> <fid>",SW_API_VLAN_FID_SET, NULL},
+ {"fid", "get", "get VLAN entry fid", "<vlan_id>",SW_API_VLAN_FID_GET, NULL},
+ {"member", "add", "add VLAN entry member", "<vlan_id> <port_id> <unmodified|untagged|tagged>",SW_API_VLAN_MEMBER_ADD, NULL},
+ {"member", "del", "del VLAN entry member", "<vlan_id> <port_id>",SW_API_VLAN_MEMBER_DEL, NULL},
+ {"learnsts", "set", "set VLAN entry learn status", "<vlan_id> <enable|disable>",SW_API_VLAN_LEARN_STATE_SET, NULL},
+ {"learnsts", "get", "get VLAN entry learn status", "<vlan_id>",SW_API_VLAN_LEARN_STATE_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*portvlan*/
+#ifdef IN_PORTVLAN
+ {
+ "portVlan", "config port base VLAN",
+ {
+ {"ingress", "get", "get ingress VLAN mode of a port", "<port_id>", SW_API_PT_ING_MODE_GET, NULL},
+ {"ingress", "set", "set ingress VLAN mode of a port", "<port_id> <disable|secure|check|fallback>", SW_API_PT_ING_MODE_SET, NULL},
+ {"egress", "get", "get egress VLAN mode of a port", "<port_id>", SW_API_PT_EG_MODE_GET, NULL},
+ {"egress", "set", "set egress VLAN mode of a port", "<port_id> <unmodified|untagged|tagged|hybrid|untouched>", SW_API_PT_EG_MODE_SET, NULL},
+ {"member", "add", "add a member to the port based VLAN of a port", "<port_id> <memport_id>", SW_API_PT_VLAN_MEM_ADD, NULL},
+ {"member", "del", "delete a member from the port based VLAN of a port", "<port_id> <memport_id>", SW_API_PT_VLAN_MEM_DEL, NULL},
+ {"member", "update", "update members of the port based VLAN of a port", "<port_id> <port_bitmap>", SW_API_PT_VLAN_MEM_UPDATE, NULL},
+ {"member", "get", "get members of the port based VLAN of a port", "<port_id>", SW_API_PT_VLAN_MEM_GET, NULL},
+ {"defaultVid", "get", "get default VLAN id of a port", "<port_id>", SW_API_PT_DEF_VID_GET, NULL},
+ {"defaultVid", "set", "set default VLAN id of a port", "<port_id> <vid>", SW_API_PT_DEF_VID_SET, NULL},
+ {"forceVid", "set", "set VLAN id enforcement status of a port", "<port_id> <enable|disable>", SW_API_PT_FORCE_DEF_VID_SET, NULL},
+ {"forceVid", "get", "get VLAN id enforcement status of a port", "<port_id>", SW_API_PT_FORCE_DEF_VID_GET, NULL},
+ {"forceMode", "set", "set port based VLAN enforcement status of a port", "<port_id> <enable|disable>", SW_API_PT_FORCE_PORTVLAN_SET, NULL},
+ {"forceMode", "get", "get port based VLAN enforcement status of a port", "<port_id>", SW_API_PT_FORCE_PORTVLAN_GET, NULL},
+ {"nestVlan", "set", "set nest VLAN status of a port", "<port_id> <enable|disable>", SW_API_PT_NESTVLAN_SET, NULL},
+ {"nestVlan", "get", "get nest VLAN status of a port", "<port_id>", SW_API_PT_NESTVLAN_GET, NULL},
+ {"sVlanTPID", "set", "set service VLAN tpid", "<tpid>", SW_API_NESTVLAN_TPID_SET, NULL},
+ {"sVlanTPID", "get", "get service VLAN tpid", "", SW_API_NESTVLAN_TPID_GET, NULL},
+ /*shiva*/
+ {"invlan", "set", "set port invlan mode", "<port_id> <admit_all|admit_tagged|admit_untagged>", SW_API_PT_IN_VLAN_MODE_SET, NULL},
+ {"invlan", "get", "get port invlan mode", "<port_id>", SW_API_PT_IN_VLAN_MODE_GET, NULL},
+ {"tlsMode", "set", "set TLS mode", "<port_id> <enable|disable>", SW_API_PT_TLS_SET, NULL},
+ {"tlsMode", "get", "get TLS mode", "<port_id>", SW_API_PT_TLS_GET, NULL},
+ {"priPropagation", "set", "set priority propagation", "<port_id> <enable|disable>", SW_API_PT_PRI_PROPAGATION_SET, NULL},
+ {"priPropagation", "get", "get priority propagation", "<port_id>", SW_API_PT_PRI_PROPAGATION_GET, NULL},
+ {"defaultSVid", "set", "set default SVID", "<port_id> <vlan_id>", SW_API_PT_DEF_SVID_SET, NULL},
+ {"defaultSVid", "get", "get default SVID", "<port_id>", SW_API_PT_DEF_SVID_GET, NULL},
+ {"defaultCVid", "set", "set default CVID", "<port_id> <vlan_id>", SW_API_PT_DEF_CVID_SET, NULL},
+ {"defaultCVid", "get", "get default CVID", "<port_id>", SW_API_PT_DEF_CVID_GET, NULL},
+ {"vlanPropagation", "set", "set vlan propagation", "<port_id> <disable|clone|replace>", SW_API_PT_VLAN_PROPAGATION_SET, NULL},
+ {"vlanPropagation", "get", "get vlan propagation", "<port_id>", SW_API_PT_VLAN_PROPAGATION_GET, NULL},
+ {"translation", "add", "add vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_ADD, NULL},
+ {"translation", "del", "del vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_DEL, NULL},
+ {"translation", "get", "get vlan translation", "<port_id>", SW_API_PT_VLAN_TRANS_GET, NULL},
+ {"translation", "iterate", "iterate vlan translation tables", "<port_id> <iterator>", SW_API_PT_VLAN_TRANS_ITERATE, NULL},
+ {"qinqMode", "set", "set qinq mode", "<ctag|stag>", SW_API_QINQ_MODE_SET, NULL},
+ {"qinqMode", "get", "get qinq mode", "", SW_API_QINQ_MODE_GET, NULL},
+ {"qinqRole", "set", "set qinq role", "<port_id> <edge|core>", SW_API_PT_QINQ_ROLE_SET, NULL},
+ {"qinqRole", "get", "get qinq role", "<port_id>", SW_API_PT_QINQ_ROLE_GET, NULL},
+ {"macvlanxlt", "set", "set mac vlan xlt status", "<port_id> <enable|disable>", SW_API_PT_MAC_VLAN_XLT_SET, NULL},
+ {"macvlanxlt", "get", "set mac vlan xlt status", "<port_id>", SW_API_PT_MAC_VLAN_XLT_GET, NULL},
+ {"netiso", "set", "enable public/private net isolate", "<enable|disable>", SW_API_NETISOLATE_SET, NULL},
+ {"netiso", "get", "get public/private net isolate status", "", SW_API_NETISOLATE_GET, NULL},
+ {"egbypass", "set", "enable egress translation filter bypass", "<enable|disable>", SW_API_EG_FLTR_BYPASS_EN_SET, NULL},
+ {"egbypass", "get", "get the status of egress translation filter bypass", "", SW_API_EG_FLTR_BYPASS_EN_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*fdb*/
+#ifdef IN_FDB
+ {
+ "fdb", "config FDB table",
+ {
+ {"entry", "add", "add a FDB entry", "", SW_API_FDB_ADD, NULL},
+ {"entry", "del", "delete a FDB entry", "", SW_API_FDB_DELMAC, NULL},
+ {"entry", "flush", "flush all FDB entries", "<0:dynamic only|1:dynamic and static>", SW_API_FDB_DELALL, NULL},
+ {"entry", "show", "show whole FDB entries", "", SW_CMD_FDB_SHOW, cmd_show_fdb},
+ {"entry", "find", "find a FDB entry", "", SW_API_FDB_FIND, NULL},
+ {"entry", "iterate", "iterate all FDB entries", "<iterator>", SW_API_FDB_ITERATE, NULL},
+ {"entry", "extendnext", "find next FDB entry in extend mode", "", SW_API_FDB_EXTEND_NEXT, NULL},
+ {"entry", "extendfirst", "find first FDB entry in extend mode", "", SW_API_FDB_EXTEND_FIRST, NULL},
+ {"entry", "transfer", "transfer port info in FDB entry", "<old port_id> <new port_id> <fid>", SW_API_FDB_TRANSFER, NULL},
+ {"portEntry", "flush", "flush all FDB entries by a port", "<port_id> <0:dynamic only|1:dynamic and static>", SW_API_FDB_DELPORT, NULL},
+ {"firstEntry", "find", "find the first FDB entry", "", SW_API_FDB_FIRST, NULL},
+ {"nextEntry", "find", "find next FDB entry", "", SW_API_FDB_NEXT, NULL},
+ {"portLearn", "set", "set FDB entry learning status of a port", "<port_id> <enable|disable>", SW_API_FDB_PT_LEARN_SET, NULL},
+ {"portLearn", "get", "get FDB entry learning status of a port", "<port_id>", SW_API_FDB_PT_LEARN_GET, NULL},
+ {"ageCtrl", "set", "set FDB entry aging status", "<enable|disable>", SW_API_FDB_AGE_CTRL_SET, NULL},
+ {"ageCtrl", "get", "get FDB entry aging status", "", SW_API_FDB_AGE_CTRL_GET, NULL},
+ {"vlansmode", "set", "set FDB vlan search mode", "<ivl|svl>", SW_API_FDB_VLAN_IVL_SVL_SET, NULL},
+ {"vlansmode", "get", "get FDB vlan search mode", "", SW_API_FDB_VLAN_IVL_SVL_GET, NULL},
+ {"ageTime", "set", "set FDB entry aging time", "<time:s>", SW_API_FDB_AGE_TIME_SET, NULL},
+ {"ageTime", "get", "get FDB entry aging time", "", SW_API_FDB_AGE_TIME_GET, NULL},
+ {"ptlearnlimit", "set", "set port FDB entry learn limit", "<port_id> <enable|disable> <limitcounter>", SW_API_PT_FDB_LEARN_LIMIT_SET, NULL},
+ {"ptlearnlimit", "get", "get port FDB entry learn limit", "<port_id>", SW_API_PT_FDB_LEARN_LIMIT_GET, NULL},
+ {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed learn limit", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_FDB_LEARN_EXCEED_CMD_SET, NULL},
+ {"ptlearnexceedcmd", "get", "get port forwarding cmd when exceed learn limit", "<port_id>", SW_API_PT_FDB_LEARN_EXCEED_CMD_GET, NULL},
+ {"learnlimit", "set", "set FDB entry learn limit", "<enable|disable> <limitcounter>", SW_API_FDB_LEARN_LIMIT_SET, NULL},
+ {"learnlimit", "get", "get FDB entry learn limit", "", SW_API_FDB_LEARN_LIMIT_GET, NULL},
+ {"learnexceedcmd", "set", "set forwarding cmd when exceed learn limit", "<forward|drop|cpycpu|rdtcpu>", SW_API_FDB_LEARN_EXCEED_CMD_SET, NULL},
+ {"learnexceedcmd", "get", "get forwarding cmd when exceed learn limit", "", SW_API_FDB_LEARN_EXCEED_CMD_GET, NULL},
+ {"resventry", "add", "add a reserve FDB entry", "", SW_API_FDB_RESV_ADD, NULL},
+ {"resventry", "del", "delete reserve a FDB entry", "", SW_API_FDB_RESV_DEL, NULL},
+ {"resventry", "find", "find a reserve FDB entry", "", SW_API_FDB_RESV_FIND, NULL},
+ {"resventry", "iterate", "iterate all reserve FDB entries", "<iterator>", SW_API_FDB_RESV_ITERATE, NULL},
+ {"resventry", "show", "show whole resv FDB entries", "", SW_CMD_RESV_FDB_SHOW, cmd_show_resv_fdb},
+ {"ptLearnstatic", "set", "set FDB entry learning static status of a port", "<port_id> <enable|disable>", SW_API_FDB_PT_LEARN_STATIC_SET, NULL},
+ {"ptLearnStatic", "get", "get FDB entry learning static status of a port", "<port_id>", SW_API_FDB_PT_LEARN_STATIC_GET, NULL},
+ {"port", "add", "add one port to a FDB entry", "<fid> <macaddr> <port_id>", SW_API_FDB_PORT_ADD, NULL},
+ {"port", "del", "del one port from a FDB entry", "<fid> <macaddr> <port_id>", SW_API_FDB_PORT_DEL, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*acl*/
+#ifdef IN_ACL
+ {
+ "acl", "config ACL",
+ {
+ {"list", "create", "create an ACL list", "<list_id> <priority>", SW_API_ACL_LIST_CREAT, NULL},
+ {"list", "destroy", "destroy an ACL list", "<list_id>", SW_API_ACL_LIST_DESTROY, NULL},
+ {"list", "bind", "bind an ACL list to a port", "<list_id> <0-0:direction> <0-0:objtype> <objindex>", SW_API_ACL_LIST_BIND, NULL},
+ {"list", "unbind", "unbind an ACL list from a port", "<list_id> <0-0:direction> <0-0:objtype> <objindex>", SW_API_ACL_LIST_UNBIND, NULL},
+ {"rule", "add", "add ACL rules to an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_ADD, NULL},
+ {"rule", "del", "delete ACL rules from an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_DELETE, NULL},
+ {"rule", "query", "query a ACL rule", "<list_id> <rule_id>", SW_API_ACL_RULE_QUERY, NULL},
+ {"rule", "active", "active ACL rules in an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_ACTIVE, NULL},
+ {"rule", "deactive", "deactive ACL rules in an ACL list", "<list_id> <rule_id> <rule_nr>", SW_API_ACL_RULE_DEACTIVE, NULL},
+ {"srcfiltersts", "set", "set status of ACL rules source filter", "<rule_id> <enable|disable>", SW_API_ACL_RULE_SRC_FILTER_STS_SET, NULL},
+ {"srcfiltersts", "get", "get status of ACL rules source filter", "<rule_id>", SW_API_ACL_RULE_SRC_FILTER_STS_GET, NULL},
+ {"status", "set", "set status of ACL engine", "<enable|disable>", SW_API_ACL_STATUS_SET, NULL},
+ {"status", "get", "get status of ACL engine", "", SW_API_ACL_STATUS_GET, NULL},
+ {"udfprofile", "set", "set port udf profile", "<port_id> <l2/l2snap/l3/l3plus/l4> <offset> <length>", SW_API_ACL_PT_UDF_PROFILE_SET, NULL},
+ {"udfprofile", "get", "get port udf profile", "<port_id> <l2/l2snap/l3/l3plus/l4>", SW_API_ACL_PT_UDF_PROFILE_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*qos*/
+#ifdef IN_QOS
+ {
+ "qos", "config Qos",
+ {
+#ifndef ISISC
+ {"schMode", "set", "set traffic scheduling mode", "<sp|wrr|mix|mix_plus> <q0,q1,q3,q4>", SW_API_QOS_SCH_MODE_SET, NULL},
+ {"schMode", "get", "get traffic scheduling mode", "", SW_API_QOS_SCH_MODE_GET, NULL},
+#endif
+ {"qTxBufSts", "set", "set queue tx buffer counting status of a port", "<port_id> <enable|disable>", SW_API_QOS_QU_TX_BUF_ST_SET, NULL},
+ {"qTxBufSts", "get", "get queue tx buffer counting status of a port", "<port_id>", SW_API_QOS_QU_TX_BUF_ST_GET, NULL},
+#ifdef ISISC
+ {"qTxBufNr", "set", "set queue tx buffer number", "<port_id> <queueid:0-3> <number:0-120>", SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#else
+ {"qTxBufNr", "set", "set queue tx buffer number", "<port_id> <queueid:0-3> <number:0-60>", SW_API_QOS_QU_TX_BUF_NR_SET, NULL},
+#endif
+ {"qTxBufNr", "get", "get queue tx buffer number", "<port_id> <queueid:0-3>", SW_API_QOS_QU_TX_BUF_NR_GET, NULL},
+ {"ptTxBufSts", "set", "set port tx buffer counting status of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_TX_BUF_ST_SET, NULL},
+ {"ptTxBufSts", "get", "get port tx buffer counting status of a port", "<port_id>", SW_API_QOS_PT_TX_BUF_ST_GET, NULL},
+ {"ptRedEn", "set", "set status of port wred of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_RED_EN_SET, NULL},
+ {"ptRedEn", "get", "get status of port wred of a port", "<port_id>", SW_API_QOS_PT_RED_EN_GET, NULL},
+#ifdef ISISC
+ {"ptTxBufNr", "set", "set port tx buffer number", "<port_id> <number:0-504>", SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#else
+ {"ptTxBufNr", "set", "set port tx buffer number", "<port_id> <number:0-252>", SW_API_QOS_PT_TX_BUF_NR_SET, NULL},
+#endif
+ {"ptTxBufNr", "get", "get port tx buffer number", "<port_id>", SW_API_QOS_PT_TX_BUF_NR_GET, NULL},
+#ifdef ISISC
+ {"ptRxBufNr", "set", "set port rx buffer number", "<port_id> <number:0-120>", SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#else
+ {"ptRxBufNr", "set", "set port rx buffer number", "<port_id> <number:0-60>", SW_API_QOS_PT_RX_BUF_NR_SET, NULL},
+#endif
+ {"ptRxBufNr", "get", "get port rx buffer number", "<port_id>", SW_API_QOS_PT_RX_BUF_NR_GET, NULL},
+#ifndef ISISC
+ {"up2q", "set", "set user priority to queue mapping", "<up:0-7> <queueid:0-3>", SW_API_COSMAP_UP_QU_SET, NULL},
+ {"up2q", "get", "get user priority to queue mapping", "<up:0-7>", SW_API_COSMAP_UP_QU_GET, NULL},
+ {"dscp2q", "set", "set dscp to queue mapping", "<dscp:0-63> <queueid:0-3>", SW_API_COSMAP_DSCP_QU_SET, NULL},
+ {"dscp2q", "get", "get dscp to queue mapping", "<dscp:0-63>", SW_API_COSMAP_DSCP_QU_GET, NULL},
+#endif
+#ifdef ISISC
+ {"ptMode", "set", "set Qos mode of a port", "<port_id> <da|up|dscp> <enable|disable>", SW_API_QOS_PT_MODE_SET, NULL},
+ {"ptMode", "get", "get Qos mode of a port", "<port_id> <da|up|dscp>", SW_API_QOS_PT_MODE_GET, NULL},
+ {"ptModePri", "set", "set the priority of Qos modes of a port", "<port_id> <da|up|dscp> <priority:0-3>", SW_API_QOS_PT_MODE_PRI_SET, NULL},
+ {"ptModePri", "get", "get the priority of Qos modes of a port", "<port_id> <da|up|dscp>", SW_API_QOS_PT_MODE_PRI_GET, NULL},
+#else
+ {"ptMode", "set", "set Qos mode of a port", "<port_id> <da|up|dscp|port> <enable|disable>", SW_API_QOS_PT_MODE_SET, NULL},
+ {"ptMode", "get", "get Qos mode of a port", "<port_id> <da|up|dscp|port>", SW_API_QOS_PT_MODE_GET, NULL},
+ {"ptModePri", "set", "set the priority of Qos modes of a port", "<port_id> <da|up|dscp|port> <priority:0-3>", SW_API_QOS_PT_MODE_PRI_SET, NULL},
+ {"ptModePri", "get", "get the priority of Qos modes of a port", "<port_id> <da|up|dscp|port>", SW_API_QOS_PT_MODE_PRI_GET, NULL},
+#endif
+#ifndef ISISC
+ {"ptDefaultUp", "set", "set default user priority for received frames of a port", "<port_id> <up:0-7>", SW_API_QOS_PORT_DEF_UP_SET, NULL},
+ {"ptDefaultUp", "get", "get default user priority for received frames of a port", "<port_id>", SW_API_QOS_PORT_DEF_UP_GET, NULL},
+#endif
+ {"ptschMode", "set", "set port traffic scheduling mode", "<port_id> <sp|wrr|mix|mixplus> <q0,q1,q2,q3,q4,q5>", SW_API_QOS_PORT_SCH_MODE_SET, NULL},
+ {"ptschMode", "get", "get port traffic scheduling mode", "<port_id>", SW_API_QOS_PORT_SCH_MODE_GET, NULL},
+ {"ptDefaultSpri", "set", "set default stag priority for received frames of a port", "<port_id> <spri:0-7>", SW_API_QOS_PT_DEF_SPRI_SET, NULL},
+ {"ptDefaultSpri", "get", "get default stag priority for received frames of a port", "<port_id>", SW_API_QOS_PT_DEF_SPRI_GET, NULL},
+ {"ptDefaultCpri", "set", "set default ctag priority for received frames of a port", "<port_id> <cpri:0-7>", SW_API_QOS_PT_DEF_CPRI_SET, NULL},
+ {"ptDefaultCpri", "get", "get default ctag priority for received frames of a port", "<port_id>", SW_API_QOS_PT_DEF_CPRI_GET, NULL},
+ {"ptFSpriSts", "set", "set port force Stag priority status for received frames of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_FORCE_SPRI_ST_SET, NULL},
+ {"ptFSpriSts", "get", "get port force Stag priority status for received frames of a port", "<port_id>", SW_API_QOS_PT_FORCE_SPRI_ST_GET, NULL},
+ {"ptFCpriSts", "set", "set port force Ctag priority status for received frames of a port", "<port_id> <enable|disable>", SW_API_QOS_PT_FORCE_CPRI_ST_SET, NULL},
+ {"ptFCpriSts", "get", "get port force Ctag priority status for received frames of a port", "<port_id>", SW_API_QOS_PT_FORCE_SPRI_ST_GET, NULL},
+ {"ptQuRemark", "set", "set egress queue based remark", "<port_id> <queue_id> <table_id> <enable|disable>", SW_API_QOS_QUEUE_REMARK_SET, NULL},
+ {"ptQuRemark", "get", "get egress queue based remark", "<port_id> <queue_id>", SW_API_QOS_QUEUE_REMARK_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*igmp*/
+#ifdef IN_IGMP
+ {
+ "igmp", "config IGMP/MLD",
+ {
+ {"mode", "set", "set IGMP/MLD snooping status of a port", "<port_id> <enable|disable>", SW_API_PT_IGMPS_MODE_SET, NULL},
+ {"mode", "get", "get port IGMP/MLD snooping status", "<port_id>", SW_API_PT_IGMPS_MODE_GET, NULL},
+ {"cmd", "set", "set IGMP/MLD frames forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_IGMP_MLD_CMD_SET, NULL},
+ {"cmd", "get", "get IGMP/MLD frames forwarding command", "", SW_API_IGMP_MLD_CMD_GET, NULL},
+ {"portJoin", "set", "set IGMP/MLD hardware joining status", "<port_id> <enable|disable>", SW_API_IGMP_PT_JOIN_SET, NULL},
+ {"portJoin", "get", "get IGMP/MLD hardware joining status", "<port_id>", SW_API_IGMP_PT_JOIN_GET, NULL},
+ {"portLeave", "set", "set IGMP/MLD hardware leaving status", "<port_id> <enable|disable>", SW_API_IGMP_PT_LEAVE_SET, NULL},
+ {"portLeave", "get", "get IGMP/MLD hardware leaving status", "<port_id>", SW_API_IGMP_PT_LEAVE_GET, NULL},
+ {"rp", "set", "set IGMP/MLD router ports", "<port_bit_map>", SW_API_IGMP_RP_SET, NULL},
+ {"rp", "get", "get IGMP/MLD router ports", "", SW_API_IGMP_RP_GET, NULL},
+ {"createStatus", "set", "set IGMP/MLD ability for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_CREAT_SET, NULL},
+ {"createStatus", "get", "get IGMP/MLD ability for creating entry", "", SW_API_IGMP_ENTRY_CREAT_GET, NULL},
+ {"static", "set", "set IGMP/MLD static status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_STATIC_SET, NULL},
+ {"static", "get", "get IGMP/MLD static status for creating entry", "", SW_API_IGMP_ENTRY_STATIC_GET, NULL},
+ {"leaky", "set", "set IGMP/MLD leaky status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_LEAKY_SET, NULL},
+ {"leaky", "get", "get IGMP/MLD leaky status for creating entry", "", SW_API_IGMP_ENTRY_LEAKY_GET, NULL},
+ {"version3", "set", "set IGMP v3/MLD v2 status for creating entry", "<enable|disable>", SW_API_IGMP_ENTRY_V3_SET, NULL},
+ {"version3", "get", "get IGMP v3/MLD v2 status for creating entry", "", SW_API_IGMP_ENTRY_V3_GET, NULL},
+ {"queue", "set", "set IGMP/MLD queue status for creating entry", "<enable|disable> <queue_id>", SW_API_IGMP_ENTRY_QUEUE_SET, NULL},
+ {"queue", "get", "get IGMP/MLD queue status for creating entry", "", SW_API_IGMP_ENTRY_QUEUE_GET, NULL},
+ {"ptlearnlimit", "set", "set port Multicast entry learn limit", "<port_id> <enable|disable> <limitcounter>", SW_API_PT_IGMP_LEARN_LIMIT_SET, NULL},
+ {"ptlearnlimit", "get", "get port Multicast entry learn limit", "<port_id>", SW_API_PT_IGMP_LEARN_LIMIT_GET, NULL},
+ {"ptlearnexceedcmd", "set", "set port forwarding cmd when exceed multicast learn limit", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_IGMP_LEARN_EXCEED_CMD_SET, NULL},
+ {"ptlearnexceedcmd", "get", "get port forwarding cmd when exceed multicast learn limit", "<port_id>", SW_API_PT_IGMP_LEARN_EXCEED_CMD_GET, NULL},
+ {"multi", "set", "set igmp/mld entry", "<entry>", SW_API_IGMP_SG_ENTRY_SET, NULL},
+ {"multi", "clear", "clear igmp/mld entry", "<entry>", SW_API_IGMP_SG_ENTRY_CLEAR, NULL},
+ {"multi", "show", "show all igmp/mld entry", "", SW_API_IGMP_SG_ENTRY_SHOW, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*leaky*/
+#ifdef IN_LEAKY
+ {
+ "leaky", "config leaky",
+ {
+ {"ucMode", "set", "set unicast packets leaky mode", "<port|fdb>", SW_API_UC_LEAKY_MODE_SET, NULL},
+ {"ucMode", "get", "get unicast packets leaky mode", "", SW_API_UC_LEAKY_MODE_GET, NULL},
+ {"mcMode", "set", "set multicast packets leaky mode", "<port|fdb>", SW_API_MC_LEAKY_MODE_SET, NULL},
+ {"mcMode", "get", "get multicast packets leaky mode", "", SW_API_MC_LEAKY_MODE_GET, NULL},
+ {"arpMode", "set", "set arp packets leaky mode", "<port_id> <enable|disable>", SW_API_ARP_LEAKY_MODE_SET, NULL},
+ {"arpMode", "get", "get arp packets leaky mode", "<port_id>", SW_API_ARP_LEAKY_MODE_GET, NULL},
+ {"ptUcMode", "set", "set unicast packets leaky status of a port", "<port_id> <enable|disable>", SW_API_PT_UC_LEAKY_MODE_SET, NULL},
+ {"ptUcMode", "get", "get unicast packets leaky status of a port", "<port_id>", SW_API_PT_UC_LEAKY_MODE_GET, NULL},
+ {"ptMcMode", "set", "set multicast packets leaky status of a port", "<port_id> <enable|disable>", SW_API_PT_MC_LEAKY_MODE_SET, NULL},
+ {"ptMcMode", "get", "get multicast packets leaky status of a port", "<port_id>", SW_API_PT_MC_LEAKY_MODE_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*mirror*/
+#ifdef IN_MIRROR
+ {
+ "mirror", "config mirror",
+ {
+ {"analyPt", "set", "set mirror analysis port", "<port_id>", SW_API_MIRROR_ANALY_PT_SET, NULL},
+ {"analyPt", "get", "get mirror analysis port", "", SW_API_MIRROR_ANALY_PT_GET, NULL},
+ {"ptIngress", "set", "set ingress mirror status of a port", "<port_id> <enable|disable>", SW_API_MIRROR_IN_PT_SET, NULL},
+ {"ptIngress", "get", "get ingress mirror status of a port", "<port_id>", SW_API_MIRROR_IN_PT_GET, NULL},
+ {"ptEgress", "set", "set egress mirror status of a port", "<port_id> <enable|disable>", SW_API_MIRROR_EG_PT_SET, NULL},
+ {"ptEgress", "get", "get egress mirror status of a port", "<port_id>", SW_API_MIRROR_EG_PT_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*rate*/
+#ifdef IN_RATE
+ {
+ "rate", "config rate limit",
+ {
+ {"qEgress", "set", "set egress rate limit of a queue", "<port_id> <queueid:0-3> <speed:(kbps)> <enable|disable>", SW_API_RATE_QU_EGRL_SET, NULL},
+ {"qEgress", "get", "get egress rate limit of a queue", "<port_id> <queueid:0-3>", SW_API_RATE_QU_EGRL_GET, NULL},
+ {"ptEgress", "set", "set egress rate limit of a port", "<port_id> <speed:(kbps)> <enable|disable>", SW_API_RATE_PT_EGRL_SET, NULL},
+ {"ptEgress", "get", "get egress rate limit of a port", "<port_id>", SW_API_RATE_PT_EGRL_GET, NULL},
+ {"ptIngress", "set", "set ingress rate limit of a port", "<port_id> <speed:(kbps)> <enable|disable>", SW_API_RATE_PT_INRL_SET, NULL},
+ {"ptIngress", "get", "get ingress rate limit of a port", "<port_id>", SW_API_RATE_PT_INRL_GET, NULL},
+ {"stormCtrl", "set", "set storm control status of a particular frame type", "<port_id> <unicast|multicast|broadcast> <enable|disable>", SW_API_STORM_CTRL_FRAME_SET, NULL},
+ {"stormCtrl", "get", "get storm control status of a particular frame type", "<port_id> <unicast|multicast|broadcast>", SW_API_STORM_CTRL_FRAME_GET, NULL},
+ {"stormCtrlRate", "set", "set storm ctrl rate", "<port_id> <rate:(packets/s)>", SW_API_STORM_CTRL_RATE_SET, NULL},
+ {"stormCtrlRate", "get", "get storm ctrl rate", "<port_id>", SW_API_STORM_CTRL_RATE_GET, NULL},
+ {"portpolicer", "set", "set port policer", "<port_id>", SW_API_RATE_PORT_POLICER_SET, NULL},
+ {"portpolicer", "get", "get port policer", "<port_id>", SW_API_RATE_PORT_POLICER_GET, NULL},
+ {"portshaper", "set", "set port egress shaper", "<port_id> <enable|disable>", SW_API_RATE_PORT_SHAPER_SET, NULL},
+ {"portshaper", "get", "get port egress shaper", "<port_id>", SW_API_RATE_PORT_SHAPER_GET, NULL},
+ {"queueshaper", "set", "set queue egress shaper", "<port_id> <queue_id> <enable|disable>", SW_API_RATE_QUEUE_SHAPER_SET, NULL},
+ {"queueshaper", "get", "get queue egress shaper", "<port_id> <queue_id>", SW_API_RATE_QUEUE_SHAPER_GET, NULL},
+ {"aclpolicer", "set", "set acl policer", "<policer_id>", SW_API_RATE_ACL_POLICER_SET, NULL},
+ {"aclpolicer", "get", "get acl policer", "<policer_id>", SW_API_RATE_ACL_POLICER_GET, NULL},
+ {"ptAddRateByte", "set", "set add_rate_byte when cal rate ", "<port_id> <number:0-255>", SW_API_RATE_PT_ADDRATEBYTE_SET, NULL},
+ {"ptAddRateByte", "get", "get add_rate_byte when cal rate ", "<port_id>", SW_API_RATE_PT_ADDRATEBYTE_GET, NULL},
+ {"ptgolflowen", "set", "set status of port globle flow control", "<port_id> <enable|disable>", SW_API_RATE_PT_GOL_FLOW_EN_SET, NULL},
+ {"ptgolflowen", "get", "get status of port globle flow control", "<port_id>", SW_API_RATE_PT_GOL_FLOW_EN_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+#ifdef IN_SEC
+ {
+ "sec", "config security",
+ {
+ {"normItem", "set", "normItem", "<item> <value>", SW_API_SEC_NORM_SET, NULL},
+ {"normItem", "get", "normItem", "<item>", SW_API_SEC_NORM_GET, NULL},
+ {"mac", "set", "set MAC layer related security", "<resv_vid/invalid_src_addr> <value>", SW_API_SEC_MAC_SET, NULL},
+ {"mac", "get", "get MAC layer related security", "<resv_vid/invalid_src_addr>", SW_API_SEC_MAC_GET, NULL},
+ {"ip", "set", "set IP layer related security", "<invalid_ver/same_addr/ttl_change_status/ttl_val> <value>", SW_API_SEC_IP_SET, NULL},
+ {"ip", "get", "get IP layer related security", "<invalid_ver/same_addr/ttl_change_status/ttl_val>", SW_API_SEC_IP_GET, NULL},
+ {"ip4", "set", "set IP4 related security", "<invalid_hl/hdr_opts/invalid_df/frag_offset_min_len/frag_offset_min_size/frag_offset_max_len/invalid_frag_offset/invalid_sip/invalid_dip/invalid_chksum/invalid_pl/df_clear_status/ipid_random_status> <value>", SW_API_SEC_IP4_SET, NULL},
+ {"ip4", "get", "get IP4 related security", "<invalid_hl/hdr_opts/invalid_df/frag_offset_min_len/frag_offset_min_size/frag_offset_max_len/invalid_frag_offset/invalid_sip/invalid_dip/invalid_chksum/invalid_pl/df_clear_status/ipid_random_status>", SW_API_SEC_IP4_GET, NULL},
+ {"ip6", "set", "set IP6 related security", "<invalid_dip/invalid_sip/invalid_pl> <value>", SW_API_SEC_IP6_SET, NULL},
+ {"ip6", "get", "get IP6 related security", "<invalid_dip/invalid_sip/invalid_pl>", SW_API_SEC_IP6_GET, NULL},
+ {"tcp", "set", "set TCP related security", "<blat/invalid_hl/min_hdr_size/invalid_syn/su_block/sp_block/sap_block/xmas_scan/null_scan/sr_block/sf_block/sar_block/rst_scan/rst_with_data/fa_block/pa_block/ua_block/invalid_chksum/invalid_urgptr/invalid_opts> <value>", SW_API_SEC_TCP_SET, NULL},
+ {"tcp", "get", "get TCP related security", "<blat/invalid_hl/min_hdr_size/invalid_syn/su_block/sp_block/sap_block/xmas_scan/null_scan/sr_block/sf_block/sar_block/rst_scan/rst_with_data/fa_block/pa_block/ua_block/invalid_chksum/invalid_urgptr/invalid_opts>", SW_API_SEC_TCP_GET, NULL},
+ {"udp", "set", "set UDP related security", "<blat/invalid_len/invalid_chksum> <value>", SW_API_SEC_UDP_SET, NULL},
+ {"udp", "get", "get UDP related security", "<blat/invalid_len/invalid_chksum>", SW_API_SEC_UDP_GET, NULL},
+ {"icmp4", "set", "set ICMP4 related security", "<ping_pl_exceed/ping_frag/ping_max_pl> <value>", SW_API_SEC_ICMP4_SET, NULL},
+ {"icmp4", "get", "get ICMP4 related security", "<ping_pl_exceed/ping_frag/ping_max_pl>", SW_API_SEC_ICMP4_GET, NULL},
+ {"icmp6", "set", "set ICMP6 related security", "<ping_pl_exceed/ping_frag/ping_max_pl> <value>", SW_API_SEC_ICMP6_SET, NULL},
+ {"icmp6", "get", "get ICMP6 related security", "<ping_pl_exceed/ping_frag/ping_max_pl>", SW_API_SEC_ICMP6_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*stp*/
+#ifdef IN_STP
+ {
+ "stp", "config STP",
+ {
+ {"portState", "set", "set STP state of a port", "st_id <port_id> <disable|block|listen|learn|forward>", SW_API_STP_PT_STATE_SET, NULL},
+ {"portState", "get", "get STP state of a port", "st_id <port_id>", SW_API_STP_PT_STATE_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*mib*/
+#ifdef IN_MIB
+ {
+ "mib", "show MIB statistics information",
+ {
+ {"statistics", "get", "get statistics information of a port", "<port_id>", SW_API_PT_MIB_GET, NULL},
+ {"status", "set", "set mib status", "<enable|disable>", SW_API_MIB_STATUS_SET, NULL},
+ {"status", "get", "get mib status", "", SW_API_MIB_STATUS_GET, NULL},
+ {"counters", "flush", "flush counters of a port", "<port_id>", SW_API_PT_MIB_FLUSH_COUNTERS, NULL},
+ {"cpuKeep", "set", "set cpu keep bit", "<enable|disable>", SW_API_MIB_CPU_KEEP_SET, NULL},
+ {"cpuKeep", "get", "get cpu keep bit", "", SW_API_MIB_CPU_KEEP_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /* led */
+#ifdef IN_LED
+ {
+ "led", "set/get led control pattern",
+ {
+ {"ctrlpattern", "set", "set led control pattern", "<group_id> <led_id>", SW_API_LED_PATTERN_SET, NULL},
+ {"ctrlpattern", "get", "get led control pattern", "<group_id> <led_id>", SW_API_LED_PATTERN_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /* cosmap */
+#ifdef IN_COSMAP
+ {
+ "cosmap", "set/get cosmap table",
+ {
+ {"dscp2pri", "set", "set dscp to priority map table", "<dscp> <priority>", SW_API_COSMAP_DSCP_TO_PRI_SET, NULL},
+ {"dscp2pri", "get", "get dscp to priority map table", "<dscp>", SW_API_COSMAP_DSCP_TO_PRI_GET, NULL},
+ {"dscp2dp", "set", "set dscp to dp map table", "<dscp> <dp>", SW_API_COSMAP_DSCP_TO_DP_SET, NULL},
+ {"dscp2dp", "get", "get dscp to dp map table", "<dscp>", SW_API_COSMAP_DSCP_TO_DP_GET, NULL},
+ {"up2pri", "set", "set dot1p to priority map table", "<up> <priority>", SW_API_COSMAP_UP_TO_PRI_SET, NULL},
+ {"up2pri", "get", "get dot1p to priority map table", "<up>", SW_API_COSMAP_UP_TO_PRI_GET, NULL},
+ {"up2dp", "set", "set dot1p to dp map table", "<up> <dp>", SW_API_COSMAP_UP_TO_DP_SET, NULL},
+ {"up2dp", "get", "get dot1p to dp map table", "<up>", SW_API_COSMAP_UP_TO_DP_GET, NULL},
+ {"pri2q", "set", "set priority to queue mapping", "<priority> <queueid>", SW_API_COSMAP_PRI_TO_QU_SET, NULL},
+ {"pri2q", "get", "get priority to queue mapping", "<priority>", SW_API_COSMAP_PRI_TO_QU_GET, NULL},
+ {"pri2ehq", "set", "set priority to enhanced queue mapping", "<priority> <queueid>", SW_API_COSMAP_PRI_TO_EHQU_SET, NULL},
+ {"pri2ehq", "get", "get priority to enhanced queue mapping", "<priority>", SW_API_COSMAP_PRI_TO_EHQU_GET, NULL},
+ {"egRemark", "set", "set egress remark table", "<tableid>", SW_API_COSMAP_EG_REMARK_SET, NULL},
+ {"egRemark", "get", "get egress remark table", "<tableid>", SW_API_COSMAP_EG_REMARK_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*misc*/
+#ifdef IN_MISC
+ {
+ "misc", "config miscellaneous",
+ {
+ {"arp", "set", "set arp packets hardware identification status", "<enable|disable>", SW_API_ARP_STATUS_SET, NULL},
+ {"arp", "get", "get arp packets hardware identification status", "", SW_API_ARP_STATUS_GET, NULL},
+ {"frameMaxSize", "set", "set the maximal received frame size of the device", "<size:byte>", SW_API_FRAME_MAX_SIZE_SET, NULL},
+ {"frameMaxSize", "get", "get the maximal received frame size of the device", "", SW_API_FRAME_MAX_SIZE_GET, NULL},
+ {"ptUnkSaCmd", "set", "set forwarding command for frames with unknown source address", "<port_id> <forward|drop|cpycpu|rdtcpu>", SW_API_PT_UNK_SA_CMD_SET, NULL},
+ {"ptUnkSaCmd", "get", "get forwarding command for frames with unknown source address", "<port_id>", SW_API_PT_UNK_SA_CMD_GET, NULL},
+ {"ptUnkUcFilter", "set", "set flooding status of unknown unicast frames", "<port_id> <enable|disable>", SW_API_PT_UNK_UC_FILTER_SET, NULL},
+ {"ptUnkUcFilter", "get", "get flooding status of unknown unicast frames", "<port_id>", SW_API_PT_UNK_UC_FILTER_GET, NULL},
+ {"ptUnkMcFilter", "set", "set flooding status of unknown multicast frames", "<port_id> <enable|disable>", SW_API_PT_UNK_MC_FILTER_SET, NULL},
+ {"ptUnkMcFilter", "get", "get flooding status of unknown multicast frames", "<port_id>", SW_API_PT_UNK_MC_FILTER_GET, NULL},
+ {"ptBcFilter", "set", "set flooding status of broadcast frames", "<port_id> <enable|disable>", SW_API_PT_BC_FILTER_SET, NULL},
+ {"ptBcFilter", "get", "get flooding status of broadcast frames", "<port_id>", SW_API_PT_BC_FILTER_GET, NULL},
+ {"cpuPort", "set", "set cpu port status", "<enable|disable>", SW_API_CPU_PORT_STATUS_SET, NULL},
+ {"cpuPort", "get", "get cpu port status", "", SW_API_CPU_PORT_STATUS_GET, NULL},
+ {"bctoCpu", "set", "set broadcast frames to Cpu port status", "<enable|disable>", SW_API_BC_TO_CPU_PORT_SET, NULL},
+ {"bctoCpu", "get", "get broadcast frames to Cpu port status", "", SW_API_BC_TO_CPU_PORT_GET, NULL},
+ {"PppoeCmd", "set", "set pppoe frames forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_PPPOE_CMD_SET, NULL},
+ {"PppoeCmd", "get", "get pppoe frames forwarding command", "", SW_API_PPPOE_CMD_GET, NULL},
+ {"Pppoe", "set", "set pppoe frames hardware identification status", "<enable|disable>", SW_API_PPPOE_STATUS_SET, NULL},
+ {"Pppoe", "get", "get pppoe frames hardware identification status", "", SW_API_PPPOE_STATUS_GET, NULL},
+ {"ptDhcp", "set", "set dhcp frames hardware identification status", "<port_id> <enable|disable>", SW_API_PT_DHCP_SET, NULL},
+ {"ptDhcp", "get", "get dhcp frames hardware identification status", "<port_id>", SW_API_PT_DHCP_GET, NULL},
+ {"arpcmd", "set", "set arp packets forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_ARP_CMD_SET, NULL},
+ {"arpcmd", "get", "get arp packets forwarding command", "", SW_API_ARP_CMD_GET, NULL},
+ {"eapolcmd", "set", "set eapol packets forwarding command", "<forward|drop|cpycpu|rdtcpu>", SW_API_EAPOL_CMD_SET, NULL},
+ {"eapolcmd", "get", "get eapol packets forwarding command", "", SW_API_EAPOL_CMD_GET, NULL},
+ {"pppoesession", "add", "add a pppoe session entry", "<session_id> <enable|disable>", SW_API_PPPOE_SESSION_ADD, NULL},
+ {"pppoesession", "del", "del a pppoe session entry", "<session_id>", SW_API_PPPOE_SESSION_DEL, NULL},
+ {"pppoesession", "get", "get a pppoe session entry", "<session_id>", SW_API_PPPOE_SESSION_GET, NULL},
+ {"eapolstatus", "set", "set eapol frames hardware identification status", "<port_id> <enable|disable>", SW_API_EAPOL_STATUS_SET, NULL},
+ {"eapolstatus", "get", "get eapol frames hardware identification status", "<port_id>", SW_API_EAPOL_STATUS_GET, NULL},
+ {"rip", "set", "set rip packets hardware identification status", "<enable|disable>", SW_API_RIPV1_STATUS_SET, NULL},
+ {"rip", "get", "get rip packets hardware identification status", "", SW_API_RIPV1_STATUS_GET, NULL},
+ {"ptarpreq", "set", "set arp request packets hardware identification status", "<port_id> <enable|disable>", SW_API_PT_ARP_REQ_STATUS_SET, NULL},
+ {"ptarpreq", "get", "get arp request packets hardware identification status", "<port_id>", SW_API_PT_ARP_REQ_STATUS_GET, NULL},
+ {"ptarpack", "set", "set arp ack packets hardware identification status", "<port_id> <enable|disable>", SW_API_PT_ARP_ACK_STATUS_SET, NULL},
+ {"ptarpack", "get", "get arp ack packets hardware identification status", "<port_id>", SW_API_PT_ARP_ACK_STATUS_GET, NULL},
+ {"extendpppoe", "add", "add a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_ADD, NULL},
+ {"extendpppoe", "del", "del a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_DEL, NULL},
+ {"extendpppoe", "get", "get a pppoe session entry", "", SW_API_PPPOE_SESSION_TABLE_GET, NULL},
+ {"pppoeid", "set", "set a pppoe session id entry", "<index> <id>", SW_API_PPPOE_SESSION_ID_SET, NULL},
+ {"pppoeid", "get", "get a pppoe session id entry", "<index>", SW_API_PPPOE_SESSION_ID_GET, NULL},
+ {"intrmask", "set", "set switch interrupt mask", "<intr_mask>", SW_API_INTR_MASK_SET, NULL},
+ {"intrmask", "get", "get switch interrupt mask", "", SW_API_INTR_MASK_GET, NULL},
+ {"intrstatus", "get", "get switch interrupt status", "", SW_API_INTR_STATUS_GET, NULL},
+ {"intrstatus", "clear", "clear switch interrupt status", "<intr_mask>", SW_API_INTR_STATUS_CLEAR, NULL},
+ {"intrportlinkmask", "set", "set link interrupt mask of a port", "<port_id> <intr_mask>", SW_API_INTR_PORT_LINK_MASK_SET, NULL},
+ {"intrportlinkmask", "get", "get link interrupt mask of a port", "<port_id>", SW_API_INTR_PORT_LINK_MASK_GET, NULL},
+ {"intrportlinkstatus", "get", "get link interrupt status of a port", "<port_id>", SW_API_INTR_PORT_LINK_STATUS_GET, NULL},
+ {"intrmaskmaclinkchg", "set", "set switch interrupt mask for mac link change", "<port_id> <enable | disable>", SW_API_INTR_MASK_MAC_LINKCHG_SET, NULL},
+ {"intrmaskmaclinkchg", "get", "get switch interrupt mask for mac link change", "<port_id>", SW_API_INTR_MASK_MAC_LINKCHG_GET, NULL},
+ {"intrstatusmaclinkchg", "get", "get switch interrupt status for mac link change", "", SW_API_INTR_STATUS_MAC_LINKCHG_GET, NULL},
+ {"intrstatusmaclinkchg", "clear", "clear switch interrupt status for mac link change", "", SW_API_INTR_STATUS_MAC_LINKCHG_CLEAR, NULL},
+ {"cpuVid", "set", "set to_cpu vid status", "<enable|disable>", SW_API_CPU_VID_EN_SET, NULL},
+ {"cpuVid", "get", "get to_cpu vid status", "", SW_API_CPU_VID_EN_GET, NULL},
+ {"rtdPppoe", "set", "set RM_RTD_PPPOE_EN status", "<enable|disable>", SW_API_RTD_PPPOE_EN_SET, NULL},
+ {"rtdPppoe", "get", "get RM_RTD_PPPOE_EN status", "", SW_API_RTD_PPPOE_EN_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /* IP */
+#ifdef IN_IP
+ {
+ "ip", "config ip",
+ {
+ {"hostentry", "add", "add host entry", "", SW_API_IP_HOST_ADD, NULL},
+ {"hostentry", "del", "del host entry", "<del_mode>", SW_API_IP_HOST_DEL, NULL},
+ {"hostentry", "get", "get host entry", "<get_mode>", SW_API_IP_HOST_GET, NULL},
+ {"hostentry", "next", "next host entry", "<next_mode>", SW_API_IP_HOST_NEXT, NULL},
+ {"hostentry", "show", "show whole host entries", "", SW_CMD_HOST_SHOW, cmd_show_host},
+ {"hostentry", "bindcnt", "bind counter to host entry", "<host entry id> <cnt id> <enable|disable>", SW_API_IP_HOST_COUNTER_BIND, NULL},
+ {"hostentry", "bindpppoe", "bind pppoe to host entry", "<host entry id> <pppoe id> <enable|disable>", SW_API_IP_HOST_PPPOE_BIND, NULL},
+ {"ptarplearn", "set", "set port arp learn flag, bit0 req bit1 ack", "<port_id> <flag>", SW_API_IP_PT_ARP_LEARN_SET, NULL},
+ {"ptarplearn", "get", "get port arp learn flag, bit0 req bit1 ack", "<port_id>", SW_API_IP_PT_ARP_LEARN_GET, NULL},
+ {"arplearn", "set", "set arp learn mode", "<learnlocal|learnall>", SW_API_IP_ARP_LEARN_SET, NULL},
+ {"arplearn", "get", "get arp learn mode", "", SW_API_IP_ARP_LEARN_GET, NULL},
+ {"ptipsrcguard", "set", "set ip source guard mode", "<port_id> <mac_ip|mac_ip_port|mac_ip_vlan|mac_ip_port_vlan|no_guard>", SW_API_IP_SOURCE_GUARD_SET, NULL},
+ {"ptipsrcguard", "get", "get ip source guard mode", "", SW_API_IP_SOURCE_GUARD_GET, NULL},
+ {"ptarpsrcguard", "set", "set arp source guard mode", "<port_id> <mac_ip|mac_ip_port|mac_ip_vlan|mac_ip_port_vlan|no_guard>", SW_API_IP_ARP_GUARD_SET, NULL},
+ {"ptarpsrcguard", "get", "get arp source guard mode", "", SW_API_IP_ARP_GUARD_GET, NULL},
+ {"routestatus", "set", "set ip route status", "<enable|disable>", SW_API_IP_ROUTE_STATUS_SET, NULL},
+ {"routestatus", "get", "get ip route status", "", SW_API_IP_ROUTE_STATUS_GET, NULL},
+ {"intfentry", "add", "add interface mac address", "", SW_API_IP_INTF_ENTRY_ADD, NULL},
+ {"intfentry", "del", "del interface mac address", "", SW_API_IP_INTF_ENTRY_DEL, NULL},
+ {"intfentry", "show", "show whole interface mac entries", "", SW_CMD_INTFMAC_SHOW, cmd_show_intfmac},
+ {"ipunksrc", "set", "set ip unkown source command", "<forward|drop|cpycpu|rdtcpu>", SW_API_IP_UNK_SOURCE_CMD_SET, NULL},
+ {"ipunksrc", "get", "get ip unkown source command", "", SW_API_IP_UNK_SOURCE_CMD_GET, NULL},
+ {"arpunksrc", "set", "set arp unkown source command", "<forward|drop|cpycpu|rdtcpu>", SW_API_ARP_UNK_SOURCE_CMD_SET, NULL},
+ {"arpunksrc", "get", "get arp unkown source command", "", SW_API_ARP_UNK_SOURCE_CMD_GET, NULL},
+ {"ipagetime", "set", "set dynamic ip entry age time", "<time>", SW_API_IP_AGE_TIME_SET, NULL},
+ {"ipagetime", "get", "get dynamic ip entry age time", "", SW_API_IP_AGE_TIME_GET, NULL},
+ {"wcmphashmode", "set", "set wcmp hash mode", "<hashmode>", SW_API_WCMP_HASH_MODE_SET, NULL},
+ {"wcmphashmode", "get", "get wcmp hash mode", "", SW_API_WCMP_HASH_MODE_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /* NAT */
+#ifdef IN_NAT
+ {
+ "nat", "config nat",
+ {
+ {"natentry", "add", "add nat entry", "", SW_API_NAT_ADD, NULL},
+ {"natentry", "del", "del nat entry", "<del_mode>", SW_API_NAT_DEL, NULL},
+ {"natentry", "get", "get nat entry", "<get_mode>", SW_API_NAT_GET, NULL},
+ {"natentry", "next", "next nat entry", "<next_mode>", SW_API_NAT_NEXT, NULL},
+ {"natentry", "show", "show whole nat entries", "", SW_CMD_NAT_SHOW, cmd_show_nat},
+ {"natentry", "bindcnt", "bind counter to nat entry", "<nat entry id> <cnt id> <enable|disable>", SW_API_NAT_COUNTER_BIND, NULL},
+ {"naptentry", "add", "add napt entry", "", SW_API_NAPT_ADD, NULL},
+ {"naptentry", "del", "del napt entry", "<del_mode>", SW_API_NAPT_DEL, NULL},
+ {"naptentry", "get", "get napt entry", "<get_mode>", SW_API_NAPT_GET, NULL},
+ {"naptentry", "next", "next napt entry", "<next_mode>", SW_API_NAPT_NEXT, NULL},
+ {"naptentry", "show", "show whole napt entries", "", SW_CMD_NAPT_SHOW, cmd_show_napt},
+ {"naptentry", "bindcnt", "bind counter to napt entry", "<napt entry id> <cnt id> <enable|disable>", SW_API_NAPT_COUNTER_BIND, NULL},
+ {"natstatus", "set", "set nat status", "<enable|disable>", SW_API_NAT_STATUS_SET, NULL},
+ {"natstatus", "get", "get nat status", "", SW_API_NAT_STATUS_GET, NULL},
+ {"naptstatus", "set", "set napt status", "<enable|disable>", SW_API_NAPT_STATUS_SET, NULL},
+ {"naptstatus", "get", "get napt status", "", SW_API_NAPT_STATUS_GET, NULL},
+ {"nathash", "set", "set nat hash mode", "<flag>", SW_API_NAT_HASH_MODE_SET, NULL},
+ {"nathash", "get", "get nat hash mode", "", SW_API_NAT_HASH_MODE_GET, NULL},
+ {"naptmode", "set", "set napt mode", "<fullcone|strictcone|portstrict|synmatric>", SW_API_NAPT_MODE_SET, NULL},
+ {"naptmode", "get", "get napt mode", "", SW_API_NAPT_MODE_GET, NULL},
+ {"prvbaseaddr", "set", "set nat prv base address", "<ip4 addr>", SW_API_PRV_BASE_ADDR_SET, NULL},
+ {"prvbaseaddr", "get", "get nat prv base address", "", SW_API_PRV_BASE_ADDR_GET, NULL},
+ {"prvaddrmode", "set", "set nat prv address map mode", "<enable|disable>", SW_API_PRV_ADDR_MODE_SET, NULL},
+ {"prvaddrmode", "get", "get nat prv address map mode", "", SW_API_PRV_ADDR_MODE_GET, NULL},
+ {"pubaddr", "add", "add pub address", "", SW_API_PUB_ADDR_ENTRY_ADD, NULL},
+ {"pubaddr", "del", "del pub address", "<del_mode>", SW_API_PUB_ADDR_ENTRY_DEL, NULL},
+ {"pubaddr", "show", "show whole pub address entries", "", SW_CMD_PUBADDR_SHOW, cmd_show_pubaddr},
+ {"natunksess", "set", "set nat unkown session command", "<forward|drop|cpycpu|rdtcpu>", SW_API_NAT_UNK_SESSION_CMD_SET, NULL},
+ {"natunksess", "get", "get nat unkown session command", "", SW_API_NAT_UNK_SESSION_CMD_GET, NULL},
+ {"prvbasemask", "set", "set nat prv base mask", "<ip4 mask>", SW_API_PRV_BASE_MASK_SET, NULL},
+ {"prvbasemask", "get", "get nat prv base mask", "", SW_API_PRV_BASE_MASK_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*Trunk*/
+#ifdef IN_TRUNK
+ {
+ "trunk", "config trunk",
+ {
+ {"group", "set", "set trunk group member info", "<trunk_id> <disable|enable> <port_bitmap>", SW_API_TRUNK_GROUP_SET, NULL},
+ {"group", "get", "get trunk group member info", "<trunk_id>", SW_API_TRUNK_GROUP_GET, NULL},
+ {"hashmode", "set", "set trunk hash mode", "<hash_mode>", SW_API_TRUNK_HASH_SET, NULL},
+ {"hashmode", "get", "get trunk hash mode", "", SW_API_TRUNK_HASH_GET, NULL},
+ {"mansa", "set", "set trunk manipulable sa", "<macaddr>", SW_API_TRUNK_MAN_SA_SET, NULL},
+ {"mansa", "get", "get trunk manipulable sa", "", SW_API_TRUNK_MAN_SA_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /*Interface Control*/
+#ifdef IN_INTERFACECONTROL
+ {
+ "interface", "config interface",
+ {
+ {"macmode", "set", "set mac mode info", "<port_id>", SW_API_MAC_MODE_SET, NULL},
+ {"macmode", "get", "get mac mode info", "<port_id>", SW_API_MAC_MODE_GET, NULL},
+ {"pt3azstatus", "set", "get mac mode info", "<port_id> <enable/disable>", SW_API_PORT_3AZ_STATUS_SET, NULL},
+ {"pt3azstatus", "get", "get mac mode info", "<port_id>", SW_API_PORT_3AZ_STATUS_GET, NULL},
+ {"phymode", "set", "set phy mode info", "<phy_id>", SW_API_PHY_MODE_SET, NULL},
+ {"phymode", "get", "get phy mode info", "<phy_id>", SW_API_PHY_MODE_GET, NULL},
+ {"fx100ctrl", "set", "set fx100 config", "", SW_API_FX100_CTRL_SET, NULL},
+ {"fx100ctrl", "get", "get fx100 config", "", SW_API_FX100_CTRL_GET, NULL},
+ {"fx100status", "get", "get fx100 status", "", SW_API_FX100_STATUS_GET, NULL},
+ {"mac06exch", "set", "set mac0 and mac6 exchange status", "<enable/disable>", SW_API_MAC06_EXCH_SET, NULL},
+ {"mac06exch", "get", "get mac0 and mac6 exchange status", "", SW_API_MAC06_EXCH_GET, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+#endif
+
+ /* debug */
+ {
+ "debug", "read/write register",
+ {
+ {"phy", "get", "read phy register", "<ph_id> <reg_addr>", SW_API_PHY_GET, NULL},
+ {"phy", "set", "write phy register", "<ph_id> <reg_addr> <value>", SW_API_PHY_SET, NULL},
+ {"reg", "get", "read switch register", "<reg_addr> <4>", SW_API_REG_GET, NULL},
+ {"reg", "set", "write switch register", "<reg_addr> <value> <4>", SW_API_REG_SET, NULL},
+ {"field", "get", "read switch register field", "<reg_addr> <offset> <len> <4>", SW_API_REG_FIELD_GET, NULL},
+ {"field", "set", "write switch register field", "<reg_addr> <offset> <len> <value> <4>", SW_API_REG_FIELD_SET, NULL},
+ {"aclList", "dump", "dump all acl list", "", SW_API_ACL_LIST_DUMP, NULL},
+ {"aclRule", "dump", "dump all acl rule", "", SW_API_ACL_RULE_DUMP, NULL},
+ {"device", "reset", "reset device", "", SW_API_SWITCH_RESET, NULL},
+ {"ssdk", "config", "show ssdk configuration", "", SW_API_SSDK_CFG, NULL},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+
+ /*debug*/
+ {
+ "device", "set device id",
+ {
+ {"id", "set", "set device id", "<dev_id>", SW_CMD_SET_DEVID, cmd_set_devid},
+ {NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/
+ },
+ },
+
+ {"help", "type ? get help", {{NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/}},
+
+ {"quit", "type quit/q quit shell", {{NULL, NULL, NULL, NULL, (int)NULL, NULL}/*end of desc*/}},
+
+ {NULL, NULL, {{NULL, NULL, NULL, NULL, (int)NULL, NULL}}} /*end of desc*/
+};
+
diff --git a/src/shell/shell_io.c b/src/shell/shell_io.c
new file mode 100644
index 0000000..bbf7c64
--- /dev/null
+++ b/src/shell/shell_io.c
@@ -0,0 +1,9056 @@
+#include <stdio.h>
+#include "shell_io.h"
+#include "shell.h"
+
+#define SW_RTN_ON_NULL_PARAM(rtn) \
+ do { if ((rtn) == NULL) return SW_BAD_PARAM; } while(0);
+
+#define DEFAULT_FLAG "default"
+static char **full_cmdstrp;
+static int talk_mode = 1;
+
+int
+get_talk_mode(void)
+{
+ return talk_mode ;
+}
+
+void
+set_talk_mode(int mode)
+{
+ talk_mode = mode;
+}
+
+void
+set_full_cmdstrp(char **cmdstrp)
+{
+ full_cmdstrp = cmdstrp;
+}
+
+static char *
+get_cmd_buf(char *tag, char *defval)
+{
+ if(!full_cmdstrp || !(*full_cmdstrp))
+ {
+ dprintf("parameter (%s) or default (%s) absent\n", tag, defval);
+ exit(1);
+ }
+
+ if (!strcasecmp(*(full_cmdstrp), DEFAULT_FLAG))
+ {
+ full_cmdstrp++;
+ return defval;
+ }
+ else
+ {
+ return *(full_cmdstrp++);
+ }
+}
+
+static char *
+get_cmd_stdin(char *tag, char *defval)
+{
+ static char gsubcmdstr[128];
+ int pos = 0;
+ int c;
+
+ if(defval)
+ {
+ dprintf("%s(%s): ", tag, defval);
+ }
+ else
+ {
+ dprintf("%s: ", tag);
+ }
+
+ memset(gsubcmdstr, 0, 128);
+
+ while ((c = getchar()) != '\n')
+ {
+ gsubcmdstr[pos++] = c;
+ if (pos == 127)
+ {
+ dprintf("too long command\n");
+ return NULL;
+ }
+ }
+
+ gsubcmdstr[pos] = '\0';
+ if ('\0' == gsubcmdstr[0])
+ {
+ return defval;
+ }
+ else
+ {
+ return gsubcmdstr;
+ }
+}
+
+static char *
+get_sub_cmd(char *tag, char *defval)
+{
+ if(talk_mode)
+ return get_cmd_stdin(tag, defval);
+ else
+ return get_cmd_buf(tag, defval);
+}
+
+
+static inline a_bool_t
+is_hex(char c)
+{
+ if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f')
+ || (c >= 'A' && c <= 'F'))
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+static inline a_bool_t
+is_dec(char c)
+{
+ if ((c >= '0') && (c <= '9'))
+ return A_TRUE;
+
+ return A_FALSE;
+}
+
+static sw_data_type_t sw_data_type[] =
+{
+ SW_TYPE_DEF(SW_UINT8, NULL, NULL),
+ SW_TYPE_DEF(SW_INT8, NULL, NULL),
+ SW_TYPE_DEF(SW_UINT16, cmd_data_check_uint16, cmd_data_print_uint16),
+ SW_TYPE_DEF(SW_INT16, NULL, NULL),
+ SW_TYPE_DEF(SW_UINT32, cmd_data_check_uint32, cmd_data_print_uint32),
+ SW_TYPE_DEF(SW_INT32, NULL, NULL),
+ SW_TYPE_DEF(SW_UINT64, NULL, NULL),
+ SW_TYPE_DEF(SW_INT64, NULL, NULL),
+ SW_TYPE_DEF(SW_CAP, cmd_data_check_capable, cmd_data_print_capable),
+ SW_TYPE_DEF(SW_DUPLEX, cmd_data_check_duplex, cmd_data_print_duplex),
+ SW_TYPE_DEF(SW_SPEED, cmd_data_check_speed, cmd_data_print_speed),
+ SW_TYPE_DEF(SW_1QMODE, cmd_data_check_1qmode, cmd_data_print_1qmode),
+ SW_TYPE_DEF(SW_EGMODE, cmd_data_check_egmode, cmd_data_print_egmode),
+ SW_TYPE_DEF(SW_MIB, NULL, cmd_data_print_mib),
+ SW_TYPE_DEF(SW_VLAN, cmd_data_check_vlan, cmd_data_print_vlan),
+ SW_TYPE_DEF(SW_PBMP, cmd_data_check_pbmp, cmd_data_print_pbmp),
+ SW_TYPE_DEF(SW_ENABLE, cmd_data_check_enable, cmd_data_print_enable),
+ SW_TYPE_DEF(SW_MACADDR, cmd_data_check_macaddr, cmd_data_print_macaddr),
+ SW_TYPE_DEF(SW_FDBENTRY, cmd_data_check_fdbentry, cmd_data_print_fdbentry),
+ SW_TYPE_DEF(SW_SCH, cmd_data_check_qos_sch, cmd_data_print_qos_sch),
+ SW_TYPE_DEF(SW_QOS, cmd_data_check_qos_pt, cmd_data_print_qos_pt),
+ SW_TYPE_DEF(SW_STORM, cmd_data_check_storm, cmd_data_print_storm),
+ SW_TYPE_DEF(SW_STP, cmd_data_check_stp_state, cmd_data_print_stp_state),
+ SW_TYPE_DEF(SW_LEAKY, cmd_data_check_leaky, cmd_data_print_leaky),
+ SW_TYPE_DEF(SW_MACCMD, cmd_data_check_maccmd, cmd_data_print_maccmd),
+ SW_TYPE_DEF(SW_UINT_A, cmd_data_check_uinta, cmd_data_print_uinta),
+ SW_TYPE_DEF(SW_ACLRULE, cmd_data_check_aclrule, cmd_data_print_aclrule),
+ SW_TYPE_DEF(SW_LEDPATTERN, cmd_data_check_ledpattern, cmd_data_print_ledpattern),
+ SW_TYPE_DEF(SW_INVLAN, cmd_data_check_invlan_mode, cmd_data_print_invlan_mode),
+ SW_TYPE_DEF(SW_VLANPROPAGATION, cmd_data_check_vlan_propagation, cmd_data_print_vlan_propagation),
+ SW_TYPE_DEF(SW_VLANTRANSLATION, cmd_data_check_vlan_translation, cmd_data_print_vlan_translation),
+ SW_TYPE_DEF(SW_QINQMODE, cmd_data_check_qinq_mode, cmd_data_print_qinq_mode),
+ SW_TYPE_DEF(SW_QINQROLE, cmd_data_check_qinq_role, cmd_data_print_qinq_role),
+ SW_TYPE_DEF(SW_CABLESTATUS, NULL, cmd_data_print_cable_status),
+ SW_TYPE_DEF(SW_CABLELEN, NULL, cmd_data_print_cable_len),
+ SW_TYPE_DEF(SW_SSDK_CFG, NULL, cmd_data_print_ssdk_cfg),
+ SW_TYPE_DEF(SW_HDRMODE, cmd_data_check_hdrmode, cmd_data_print_hdrmode),
+ SW_TYPE_DEF(SW_FDBOPRATION, cmd_data_check_fdboperation, NULL),
+ SW_TYPE_DEF(SW_PPPOE, cmd_data_check_pppoe, cmd_data_print_pppoe),
+ SW_TYPE_DEF(SW_ACL_UDF_TYPE, cmd_data_check_udf_type, cmd_data_print_udf_type),
+ SW_TYPE_DEF(SW_IP_HOSTENTRY, cmd_data_check_host_entry, cmd_data_print_host_entry),
+ SW_TYPE_DEF(SW_ARP_LEARNMODE, cmd_data_check_arp_learn_mode, cmd_data_print_arp_learn_mode),
+ SW_TYPE_DEF(SW_IP_GUARDMODE, cmd_data_check_ip_guard_mode, cmd_data_print_ip_guard_mode),
+ SW_TYPE_DEF(SW_NATENTRY, cmd_data_check_nat_entry, cmd_data_print_nat_entry),
+ SW_TYPE_DEF(SW_NAPTENTRY, cmd_data_check_napt_entry, cmd_data_print_napt_entry),
+ SW_TYPE_DEF(SW_NAPTMODE, cmd_data_check_napt_mode, cmd_data_print_napt_mode),
+ SW_TYPE_DEF(SW_IP4ADDR, cmd_data_check_ip4addr, cmd_data_print_ip4addr),
+ SW_TYPE_DEF(SW_IP6ADDR, cmd_data_check_ip6addr, cmd_data_print_ip6addr),
+ SW_TYPE_DEF(SW_INTFMACENTRY, cmd_data_check_intf_mac_entry, cmd_data_print_intf_mac_entry),
+ SW_TYPE_DEF(SW_PUBADDRENTRY, cmd_data_check_pub_addr_entry, cmd_data_print_pub_addr_entry),
+ SW_TYPE_DEF(SW_INGPOLICER, cmd_data_check_port_policer, cmd_data_print_port_policer),
+ SW_TYPE_DEF(SW_EGSHAPER, cmd_data_check_egress_shaper, cmd_data_print_egress_shaper),
+ SW_TYPE_DEF(SW_ACLPOLICER, cmd_data_check_acl_policer, cmd_data_print_acl_policer),
+ SW_TYPE_DEF(SW_MACCONFIG, cmd_data_check_mac_config, cmd_data_print_mac_config),
+ SW_TYPE_DEF(SW_PHYCONFIG, cmd_data_check_phy_config, cmd_data_print_phy_config),
+ SW_TYPE_DEF(SW_FDBSMODE, cmd_data_check_fdb_smode, cmd_data_print_fdb_smode),
+ SW_TYPE_DEF(SW_FX100CONFIG, cmd_data_check_fx100_config, cmd_data_print_fx100_config),
+ SW_TYPE_DEF(SW_SGENTRY, cmd_data_check_multi, cmd_data_print_multi),
+ SW_TYPE_DEF(SW_SEC_MAC, cmd_data_check_sec_mac, NULL),
+ SW_TYPE_DEF(SW_SEC_IP, cmd_data_check_sec_ip, NULL),
+ SW_TYPE_DEF(SW_SEC_IP4, cmd_data_check_sec_ip4, NULL),
+ SW_TYPE_DEF(SW_SEC_IP6, cmd_data_check_sec_ip6, NULL),
+ SW_TYPE_DEF(SW_SEC_TCP, cmd_data_check_sec_tcp, NULL),
+ SW_TYPE_DEF(SW_SEC_UDP, cmd_data_check_sec_udp, NULL),
+ SW_TYPE_DEF(SW_SEC_ICMP4, cmd_data_check_sec_icmp4, NULL),
+ SW_TYPE_DEF(SW_SEC_ICMP6, cmd_data_check_sec_icmp6, NULL),
+ SW_TYPE_DEF(SW_REMARKENTRY, cmd_data_check_remark_entry, cmd_data_print_remark_entry),
+};
+
+sw_data_type_t *
+cmd_data_type_find(sw_data_type_e type)
+{
+ a_uint16_t i = 0;
+
+ do
+ {
+ if (type == sw_data_type[i].data_type)
+ return &sw_data_type[i];
+ }
+ while ( ++i < sizeof(sw_data_type)/sizeof(sw_data_type[0]));
+
+ return NULL;
+}
+
+sw_error_t
+cmd_data_check_uint32(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (0 == cmd_str[0])
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+ sscanf(cmd_str, "%x", arg_val);
+ else
+ sscanf(cmd_str, "%d", arg_val);
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_uint32(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:0x%x", param_name, *(a_uint32_t *) buf);
+}
+
+sw_error_t
+cmd_data_check_uint16(char *cmd_str, a_uint32_t *arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (0 == cmd_str[0])
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+ sscanf(cmd_str, "%x", arg_val);
+ else
+ sscanf(cmd_str, "%d", arg_val);
+
+ if (65535 < *arg_val)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_uint16(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:0x%04x", param_name, *(a_uint16_t *) buf);
+
+}
+
+sw_error_t
+cmd_data_check_pbmp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (cmd_str[0] == '0' && (cmd_str[1] == 'x' || cmd_str[1] == 'X'))
+ sscanf(cmd_str, "%x", arg_val);
+ else
+ sscanf(cmd_str, "%d", arg_val);
+
+ return SW_OK;
+
+}
+
+void
+cmd_data_print_pbmp(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:0x%x", param_name, *(a_uint32_t *) buf);
+
+}
+
+sw_error_t
+cmd_data_check_enable(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "disable"))
+ *arg_val = FAL_DISABLE;
+ else if (!strcasecmp(cmd_str, "enable"))
+ *arg_val = FAL_ENABLE;
+ else
+ {
+ //dprintf("input error");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_enable(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == 1)
+ {
+ dprintf("ENABLE");
+ }
+ else if (*(a_uint32_t *) buf == 0)
+ {
+ dprintf("DISABLE");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+/*mib*/
+static char *mib_regname[] =
+{
+ "RxBroad",
+ "RxPause",
+ "RxMulti",
+ "RxFcsErr",
+ "RxAlignErr",
+ "RxRunt",
+ "RxFragment",
+ "Rx64Byte",
+ "Rx128Byte",
+ "Rx256Byte",
+ "Rx512Byte",
+ "Rx1024Byte",
+ "Rx1518Byte",
+ "RxMaxByte",
+ "RxTooLong",
+ "RxGoodByte",
+ "RxGoodByte1",
+ "RxBadByte",
+ "RxBadByte1",
+ "RxOverFlow",
+ "Filtered",
+ "TxBroad",
+ "TxPause",
+ "TxMulti",
+ "TxUnderRun",
+ "Tx64Byte",
+ "Tx128Byte",
+ "Tx256Byte",
+ "Tx512Byte",
+ "Tx1024Byte",
+ "Tx1518Byte",
+ "TxMaxByte",
+ "TxOverSize",
+ "TxByte",
+ "TxByte1",
+ "TxCollision",
+ "TxAbortCol",
+ "TxMultiCol",
+ "TxSingleCol",
+ "TxExcDefer",
+ "TxDefer",
+ "TxLateCol",
+ "RxUniCast",
+ "TxUniCast"
+};
+
+void
+cmd_data_print_mib(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("\n[%s] \n", param_name);
+ a_uint32_t offset = 0;
+ for (offset = 0; offset < (sizeof (fal_mib_info_t) / sizeof (a_uint32_t));
+ offset++)
+ {
+
+ dprintf("%-12s<0x%08x> ", mib_regname[offset], *(buf + offset));
+ if ((offset + 1) % 3 == 0)
+ dprintf("\n");
+ }
+}
+
+/*port ctrl*/
+sw_error_t
+cmd_data_check_duplex(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "half"))
+ *arg_val = FAL_HALF_DUPLEX;
+ else if (!strcasecmp(cmd_str, "full"))
+ *arg_val = FAL_FULL_DUPLEX;
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_duplex(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == 0)
+ {
+ dprintf("HALF");
+ }
+ else if (*(a_uint32_t *) buf == 1)
+ {
+ dprintf("FULL");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_speed(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strncasecmp(cmd_str, "10", 3))
+ *arg_val = FAL_SPEED_10;
+ else if (!strncasecmp(cmd_str, "100", 4))
+ *arg_val = FAL_SPEED_100;
+ else if (!strncasecmp(cmd_str, "1000", 5))
+ *arg_val = FAL_SPEED_1000;
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_speed(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_SPEED_10)
+ {
+ dprintf("10(Mbps)");
+ }
+ else if (*(a_uint32_t *) buf == FAL_SPEED_100)
+ {
+ dprintf("100(Mbps)");
+ }
+ else if (*(a_uint32_t *) buf == FAL_SPEED_1000)
+ {
+ dprintf("1000(Mbps)");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_capable(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ cmd_strtol(cmd_str, arg_val);
+ if (*arg_val & (~FAL_PHY_GE_ADV_ALL))
+ {
+ //dprintf("input error should be within 0x3f\n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_capable(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == 0)
+ {
+ dprintf("None Capable");
+ return;
+ }
+
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_1000T_FD)
+ {
+ dprintf("1000T_FD|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_100TX_FD)
+ {
+ dprintf("100TX_FD|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_100TX_HD)
+ {
+ dprintf("100TX_HD|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_10T_HD)
+ {
+ dprintf("10T_HD|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_10T_FD)
+ {
+ dprintf("10T_FD|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_PAUSE)
+ {
+ dprintf("PAUSE|");
+ }
+ if (*(a_uint32_t *) buf & FAL_PHY_ADV_ASY_PAUSE)
+ {
+ dprintf("ASY_PAUSE|");
+ }
+}
+
+/*portvlan*/
+sw_error_t
+cmd_data_check_1qmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "disable"))
+ {
+ *arg_val = FAL_1Q_DISABLE;
+ }
+ else if (!strcasecmp(cmd_str, "secure"))
+ {
+ *arg_val = FAL_1Q_SECURE;
+ }
+ else if (!strcasecmp(cmd_str, "check"))
+ {
+ *arg_val = FAL_1Q_CHECK;
+ }
+ else if (!strcasecmp(cmd_str, "fallback"))
+ {
+ *arg_val = FAL_1Q_FALLBACK;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_1qmode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_1Q_DISABLE)
+ {
+ dprintf("DISABLE\n");
+ }
+ else if (*(a_uint32_t *) buf == FAL_1Q_SECURE)
+ {
+ dprintf("SECURE\n");
+ }
+ else if (*(a_uint32_t *) buf == FAL_1Q_CHECK)
+ {
+ dprintf("CHECK\n");
+ }
+ else if (*(a_uint32_t *) buf == FAL_1Q_FALLBACK)
+ {
+ dprintf("FALLBACK\n");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_egmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "unmodified"))
+ {
+ *arg_val = FAL_EG_UNMODIFIED;
+ }
+ else if (!strcasecmp(cmd_str, "untagged"))
+ {
+ *arg_val = FAL_EG_UNTAGGED;
+ }
+ else if (!strcasecmp(cmd_str, "tagged"))
+ {
+ *arg_val = FAL_EG_TAGGED;
+ }
+ else if (!strcasecmp(cmd_str, "hybrid"))
+ {
+ *arg_val = FAL_EG_HYBRID;
+ }
+ else if (!strcasecmp(cmd_str, "untouched"))
+ {
+ *arg_val = FAL_EG_UNTOUCHED;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_egmode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_EG_UNMODIFIED)
+ {
+ dprintf("UNMODIFIED");
+ }
+ else if (*(a_uint32_t *) buf == FAL_EG_UNTAGGED)
+ {
+ dprintf("UNTAGGED");
+ }
+ else if (*(a_uint32_t *) buf == FAL_EG_TAGGED)
+ {
+ dprintf("TAGGED");
+ }
+ else if (*(a_uint32_t *) buf == FAL_EG_HYBRID)
+ {
+ dprintf("HYBRID");
+ }
+ else if (*(a_uint32_t *) buf == FAL_EG_UNTOUCHED)
+ {
+ dprintf("UNTOUCHED");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+/*vlan*/
+sw_error_t
+cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_vlan_t entry;
+ a_uint32_t tmp;
+
+ memset(&entry, 0, sizeof (fal_vlan_t));
+
+ do
+ {
+ cmd = get_sub_cmd("vlanid", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 4095\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 4095\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.vid = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("fid", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 4095 or 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 4095 or 65535\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.fid = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("port member", "null");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input port number such as 1,3\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_portmap(cmd, &entry.mem_ports,
+ sizeof (fal_pbmp_t));
+ if (SW_OK != rv)
+ dprintf("usage: input port number such as 1,3\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("tagged member", "null");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input port number such as 1,3\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_portmap(cmd, &entry.tagged_ports,
+ sizeof (fal_pbmp_t));
+ if (SW_OK != rv)
+ dprintf("usage: input port number such as 1,3\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("untagged member", "null");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input port number such as 1,3\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_portmap(cmd, &entry.untagged_ports,
+ sizeof (fal_pbmp_t));
+ if (SW_OK != rv)
+ dprintf("usage: input port number such as 1,3\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("unmodify member", "null");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input port number such as 1,3\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_portmap(cmd, &entry.unmodify_ports,
+ sizeof (fal_pbmp_t));
+ if (SW_OK != rv)
+ dprintf("usage: input port number such as 1,3\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("learn disable", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.learn_dis,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("queue override", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.vid_pri_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == entry.vid_pri_en)
+ {
+ do
+ {
+ cmd = get_sub_cmd("queue", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input number such as <0/1/2/3>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: input number such as <0/1/2/3>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.vid_pri = tmp;
+ }
+
+ *val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_vlan(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_vlan_t *sw_vlan = (fal_vlan_t *) buf;
+
+ dprintf("\n[vid]:%-4d [fid]:%-5d [member]:0x%-4x",
+ sw_vlan->vid, sw_vlan->fid, sw_vlan->mem_ports);
+
+ dprintf("\n[tagged_member]:0x%-4x [untagged_member]:0x%-4x [unmodify_member]:0x%-4x ",
+ sw_vlan->tagged_ports, sw_vlan->untagged_ports, sw_vlan->unmodify_ports);
+
+ if (sw_vlan->learn_dis == 1)
+ {
+ dprintf("[learn_dis]:enable ");
+ }
+ else
+ {
+ dprintf("[learn_dis]:disable ");
+ }
+
+ if (sw_vlan->vid_pri_en == 1)
+ {
+ dprintf("[pri_en]:enable [pri]:0x%-4x\n", sw_vlan->vid_pri);
+ }
+ else
+ {
+ dprintf("[pri_en]:disable [pri]:0x%-4x\n", 0);
+ }
+}
+
+/*qos*/
+sw_error_t
+cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val, a_uint32_t size)
+{
+ if (cmdstr == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmdstr, "sp"))
+ {
+ *val = FAL_SCH_SP_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "wrr"))
+ {
+ *val = FAL_SCH_WRR_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "mixplus"))
+ {
+ *val = FAL_SCH_MIX_PLUS_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "mix"))
+ {
+ *val = FAL_SCH_MIX_MODE;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_qos_sch(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_SCH_SP_MODE)
+ {
+ dprintf("SP");
+ }
+ else if (*(a_uint32_t *) buf == FAL_SCH_WRR_MODE)
+ {
+ dprintf("WRR");
+ }
+ else if (*(a_uint32_t *) buf == FAL_SCH_MIX_MODE)
+ {
+ dprintf("MIX");
+ }
+ else if (*(a_uint32_t *) buf == FAL_SCH_MIX_PLUS_MODE)
+ {
+ dprintf("MIXPLUS");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val, a_uint32_t size)
+{
+ if (cmdstr == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmdstr, "da"))
+ {
+ *val = FAL_QOS_DA_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "up"))
+ {
+ *val = FAL_QOS_UP_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "dscp"))
+ {
+ *val = FAL_QOS_DSCP_MODE;
+ }
+ else if (!strcasecmp(cmdstr, "port"))
+ {
+ *val = FAL_QOS_PORT_MODE;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_qos_pt(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_QOS_DA_MODE)
+ {
+ dprintf("DA");
+ }
+ else if (*(a_uint32_t *) buf == FAL_QOS_UP_MODE)
+ {
+ dprintf("UP");
+ }
+ else if (*(a_uint32_t *) buf == FAL_QOS_DSCP_MODE)
+ {
+ dprintf("DSCP");
+ }
+ else if (*(a_uint32_t *) buf == FAL_QOS_PORT_MODE)
+ {
+ dprintf("PORT");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+/*rate*/
+sw_error_t
+cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val, a_uint32_t size)
+{
+ if (cmdstr == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmdstr, "unicast"))
+ {
+ *val = FAL_UNICAST_STORM;
+ }
+ else if (!strcasecmp(cmdstr, "multicast"))
+ {
+ *val = FAL_MULTICAST_STORM;
+ }
+ else if (!strcasecmp(cmdstr, "broadcast"))
+ {
+ *val = FAL_BROADCAST_STORM;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_storm(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_UNICAST_STORM)
+ {
+ dprintf("UNICAST");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MULTICAST_STORM)
+ {
+ dprintf("MULTICAST");
+ }
+ else if (*(a_uint32_t *) buf == FAL_BROADCAST_STORM)
+ {
+ dprintf("BROADCAST");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+/*stp*/
+sw_error_t
+cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val, a_uint32_t size)
+{
+ if (cmdstr == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmdstr, "disable"))
+ {
+ *val = FAL_STP_DISABLED;
+ }
+ else if (!strcasecmp(cmdstr, "block"))
+ {
+ *val = FAL_STP_BLOKING;
+ }
+ else if (!strcasecmp(cmdstr, "listen"))
+ {
+ *val = FAL_STP_LISTENING;
+ }
+ else if (!strcasecmp(cmdstr, "learn"))
+ {
+ *val = FAL_STP_LEARNING;
+ }
+ else if (!strcasecmp(cmdstr, "forward"))
+ {
+ *val = FAL_STP_FARWARDING;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_stp_state(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_STP_DISABLED)
+ {
+ dprintf("DISABLE");
+ }
+ else if (*(a_uint32_t *) buf == FAL_STP_BLOKING)
+ {
+ dprintf("BLOCK");
+ }
+ else if (*(a_uint32_t *) buf == FAL_STP_LISTENING)
+ {
+ dprintf("LISTEN");
+ }
+ else if (*(a_uint32_t *) buf == FAL_STP_LEARNING)
+ {
+ dprintf("LEARN");
+ }
+ else if (*(a_uint32_t *) buf == FAL_STP_FARWARDING)
+ {
+ dprintf("FORWARD");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+/*general*/
+sw_error_t
+cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val, a_uint32_t size)
+{
+ if (cmdstr == NULL)
+ return SW_BAD_VALUE;
+
+ if (!strcasecmp(cmdstr, "port"))
+ {
+ *val = FAL_LEAKY_PORT_CTRL;
+ }
+ else if (!strcasecmp(cmdstr, "fdb"))
+ {
+ *val = FAL_LEAKY_FDB_CTRL;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_leaky(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_LEAKY_PORT_CTRL)
+ {
+ dprintf("PORT");
+ }
+ else if (*(a_uint32_t *) buf == FAL_LEAKY_FDB_CTRL)
+ {
+ dprintf("FDB");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_uinta(char *cmdstr, a_uint32_t * val, a_uint32_t size)
+{
+ char *tmp_str = NULL;
+ a_uint32_t *tmp_ptr = val;
+ a_uint32_t i = 0;
+
+ tmp_str = (void *) strtok(cmdstr, ",");
+ while (tmp_str)
+ {
+ if (i >= (size / 4))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ sscanf(tmp_str, "%d", tmp_ptr);
+ tmp_ptr++;
+
+ i++;
+ tmp_str = (void *) strtok(NULL, ",");
+ }
+
+ if (i != (size / 4))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_uinta(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ a_uint32_t i;
+ a_uint32_t *tmp_ptr;
+
+ dprintf("[%s]:", param_name);
+
+ tmp_ptr = buf;
+ for (i = 0; i < (size / 4); i++)
+ {
+ dprintf(" %d, ", *tmp_ptr);
+ tmp_ptr++;
+ }
+}
+
+/*fdb*/
+sw_error_t
+cmd_data_check_maccmd(char *cmdstr, fal_fwd_cmd_t * val, a_uint32_t size)
+{
+ if (NULL == cmdstr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmdstr[0])
+ {
+ *val = FAL_MAC_FRWRD; //defualt
+ }
+ else if (!strcasecmp(cmdstr, "forward"))
+ {
+ *val = FAL_MAC_FRWRD;
+ }
+ else if (!strcasecmp(cmdstr, "drop"))
+ {
+ *val = FAL_MAC_DROP;
+ }
+ else if (!strcasecmp(cmdstr, "cpycpu"))
+ {
+ *val = FAL_MAC_CPY_TO_CPU;
+ }
+ else if (!strcasecmp(cmdstr, "rdtcpu"))
+ {
+ *val = FAL_MAC_RDT_TO_CPU;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_maccmd(char * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_MAC_FRWRD)
+ {
+ dprintf("FORWARD");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_DROP)
+ {
+ dprintf("DROP");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_CPY_TO_CPU)
+ {
+ dprintf("CPYCPU");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_RDT_TO_CPU)
+ {
+ dprintf("RDTCPU");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val,
+ a_uint32_t size)
+{
+ if (0 == cmdstr[0])
+ {
+ *val = def;
+ }
+ else if ((!strcasecmp(cmdstr, "yes")) || (!strcasecmp(cmdstr, "y")))
+ {
+ *val = A_TRUE;
+ }
+ else if ((!strcasecmp(cmdstr, "no")) || (!strcasecmp(cmdstr, "n")))
+ {
+ *val = A_FALSE;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_confirm(char * param_name, a_bool_t val, a_uint32_t size)
+{
+ dprintf("%s", param_name);
+ if (A_TRUE == val)
+ {
+ dprintf("YES");
+ }
+ else if (A_FALSE == val)
+ {
+ dprintf("NO");
+ }
+ else
+ {
+ dprintf("UNKNOW");
+ }
+
+ return;
+}
+
+sw_error_t
+cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size)
+{
+ char *tmp = NULL;
+ a_uint32_t i = 0;
+ a_uint32_t port;
+
+ *val = 0;
+ //default input null
+ if(!strcasecmp(cmdstr, "null"))
+ {
+ return SW_OK;
+ }
+
+ tmp = (void *) strtok(cmdstr, ",");
+ while (tmp)
+ {
+ if (SW_MAX_NR_PORT <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ sscanf(tmp, "%d", &port);
+ if (SW_MAX_NR_PORT <= port)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ *val |= (0x1 << port);
+ tmp = (void *) strtok(NULL, ",");
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_portmap(char * param_name, fal_pbmp_t val, a_uint32_t size)
+{
+ a_uint32_t i;
+ char tmp[16];
+ tmp[0] = '\0';
+
+ dprintf("%s", param_name);
+ for (i = 0; i < SW_MAX_NR_PORT; i++)
+ {
+ if (val & (0x1 << i))
+ {
+ if(strlen(tmp) == 0)
+ sprintf(tmp, "%d", i);
+ else
+ sprintf(tmp+strlen(tmp), ",%d", i);
+ }
+ }
+ dprintf("%s ", tmp);
+ return;
+}
+
+sw_error_t
+cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size)
+{
+ char *tmp = NULL;
+ a_uint32_t i = 0, j;
+ a_uint32_t addr;
+ fal_mac_addr_t mac;
+
+ memset(&mac, 0, sizeof (fal_mac_addr_t));
+ if (NULL == cmdstr)
+ {
+ *(fal_mac_addr_t *) val = mac;
+ return SW_BAD_VALUE; /*was: SW_OK;*/
+ }
+
+ if (0 == cmdstr[0])
+ {
+ *(fal_mac_addr_t *) val = mac;
+ return SW_OK;
+ }
+
+ tmp = (void *) strtok(cmdstr, "-");
+ while (tmp)
+ {
+ if (6 <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if ((2 < strlen(tmp)) || (0 == strlen(tmp)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (j = 0; j < strlen(tmp); j++)
+ {
+ if (A_FALSE == is_hex(tmp[j]))
+ return SW_BAD_VALUE;
+ }
+
+ sscanf(tmp, "%x", &addr);
+ if (0xff < addr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ mac.uc[i++] = addr;
+ tmp = (void *) strtok(NULL, "-");
+ }
+
+ if (6 != i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ *(fal_mac_addr_t *) val = mac;
+ return SW_OK;
+}
+
+void
+cmd_data_print_macaddr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_mac_addr_t *val;
+
+ val = (fal_mac_addr_t *) buf;
+ dprintf("%s", param_name);
+ for (i = 0; i < 5; i++)
+ {
+ dprintf("%02x-", val->uc[i]);
+ }
+ dprintf("%02x", val->uc[5]);
+
+}
+
+sw_error_t
+cmd_data_check_fdbentry(char *info, void *val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_fdb_entry_t entry;
+ a_uint32_t tmp;
+
+ memset(&entry, 0, sizeof (fal_fdb_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("addr", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the format is xx-xx-xx-xx-xx-xx \n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_macaddr(cmd, &entry.addr,
+ sizeof (fal_mac_addr_t));
+ if (SW_OK != rv)
+ dprintf("usage: the format is xx-xx-xx-xx-xx-xx \n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("fid", "65535");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 1 -- 4095 or 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else if (0 == cmd[0])
+ {
+ entry.fid = 65535;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 1 -- 4095 or 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.fid = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("dacmd", "forward");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_maccmd(cmd, &entry.dacmd,
+ sizeof (fal_fwd_cmd_t));
+ if (SW_OK != rv)
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("sacmd", "forward");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_maccmd(cmd, &entry.sacmd,
+ sizeof (fal_fwd_cmd_t));
+ if (SW_OK != rv)
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("dest port", "null");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input port number such as 1,3\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_portmap(cmd, &entry.port.map,
+ sizeof (fal_pbmp_t));
+ if (SW_OK != rv)
+ dprintf("usage: input port number such as 1,3\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.portmap_en = A_TRUE;
+
+ do
+ {
+ cmd = get_sub_cmd("static", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.static_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("leaky", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.leaky_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("mirror", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.mirror_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("clone", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.clone_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("queue override", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.da_pri_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == entry.da_pri_en)
+ {
+ do
+ {
+ cmd = get_sub_cmd("queue", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: input number such as <0/1/2/3>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: input number such as <0/1/2/3>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.da_queue = tmp;
+ }
+
+ do
+ {
+ cmd = get_sub_cmd("cross_pt_state", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.cross_pt_state,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("white_list_en", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.white_list_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_fdb_entry_t *) val = entry;
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_fdbentry(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t tmp;
+ fal_fdb_entry_t *entry;
+
+ entry = (fal_fdb_entry_t *) buf;
+ dprintf("\n");
+ cmd_data_print_macaddr("[addr]:", (a_uint32_t *) & (entry->addr),
+ sizeof (fal_mac_addr_t));
+ dprintf(" ");
+ dprintf("[fid]:%d", entry->fid);
+ dprintf(" ");
+ cmd_data_print_confirm("[static]:", entry->static_en, sizeof (a_bool_t));
+ dprintf(" ");
+ cmd_data_print_portmap("[dest_port]:", entry->port.map,
+ sizeof (fal_pbmp_t));
+ dprintf(" \n");
+ cmd_data_print_maccmd("dacmd", (a_uint32_t *) & (entry->dacmd),
+ sizeof (fal_fwd_cmd_t));
+ dprintf(" ");
+ cmd_data_print_maccmd("sacmd", (a_uint32_t *) & (entry->sacmd),
+ sizeof (fal_fwd_cmd_t));
+ dprintf(" ");
+ cmd_data_print_confirm("[leaky]:", entry->leaky_en, sizeof (a_bool_t));
+ dprintf(" ");
+ cmd_data_print_confirm("[mirror]:", entry->mirror_en, sizeof (a_bool_t));
+ dprintf(" ");
+ cmd_data_print_confirm("[clone]:", entry->clone_en, sizeof (a_bool_t));
+ dprintf(" ");
+ cmd_data_print_confirm("[da_pri]:", entry->da_pri_en, sizeof (a_bool_t));
+ dprintf(" ");
+ if (A_TRUE == entry->da_pri_en)
+ {
+ tmp = entry->da_queue;
+ dprintf("[queue]:%d", tmp);
+ }
+ else
+ {
+ dprintf("[queue]:0");
+ }
+ dprintf(" ");
+ cmd_data_print_confirm("[cross_pt_state]:", entry->cross_pt_state, sizeof (a_bool_t));
+ dprintf(" ");
+ cmd_data_print_confirm("[white_list_en]:", entry->white_list_en, sizeof (a_bool_t));
+ dprintf("\n");
+
+ return;
+}
+
+#define cmd_data_check_element(info, defval, usage, chk_func, param) \
+{\
+ sw_error_t ret;\
+ do {\
+ cmd = get_sub_cmd(info, defval);\
+ SW_RTN_ON_NULL_PARAM(cmd);\
+ \
+ if (!strncasecmp(cmd, "quit", 4)) {\
+ return SW_BAD_VALUE;\
+ } else if (!strncasecmp(cmd, "help", 4)) {\
+ dprintf("%s", usage);\
+ ret = SW_BAD_VALUE;\
+ } else {\
+ ret = chk_func param; \
+ if (SW_OK != ret)\
+ dprintf("%s", usage);\
+ }\
+ } while (talk_mode && (SW_OK != ret));\
+}
+
+sw_error_t
+cmd_data_check_integer(char *cmd_str, a_uint32_t * arg_val, a_uint32_t max_val,
+ a_uint32_t min_val)
+{
+ a_uint32_t tmp;
+ a_uint32_t i;
+
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if (0 == cmd_str[0])
+ {
+ return SW_BAD_PARAM;
+ }
+
+ if ((cmd_str[0] == '0') && ((cmd_str[1] == 'x') || (cmd_str[1] == 'X')))
+ {
+ for (i = 2; i < strlen(cmd_str); i++)
+ {
+ if (A_FALSE == is_hex(cmd_str[i]))
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+ sscanf(cmd_str, "%x", &tmp);
+ }
+ else
+ {
+ for (i = 0; i < strlen(cmd_str); i++)
+ {
+ if (A_FALSE == is_dec(cmd_str[i]))
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+ sscanf(cmd_str, "%d", &tmp);
+ }
+
+ if ((tmp > max_val) || (tmp < min_val))
+ return SW_BAD_PARAM;
+
+ *arg_val = tmp;
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ruletype(char *cmd_str, fal_acl_rule_type_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "mac"))
+ {
+ *arg_val = FAL_ACL_RULE_MAC;
+ }
+ else if (!strcasecmp(cmd_str, "ip4"))
+ {
+ *arg_val = FAL_ACL_RULE_IP4;
+ }
+ else if (!strcasecmp(cmd_str, "ip6"))
+ {
+ *arg_val = FAL_ACL_RULE_IP6;
+ }
+ else if (!strcasecmp(cmd_str, "udf"))
+ {
+ *arg_val = FAL_ACL_RULE_UDF;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_ruletype(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ fal_acl_rule_type_t *val;
+
+ val = (fal_acl_rule_type_t *) buf;
+ dprintf("%s", param_name);
+
+ if (FAL_ACL_RULE_MAC == *val)
+ {
+ dprintf("mac");
+ }
+ else if (FAL_ACL_RULE_IP4 == *val)
+ {
+ dprintf("ip4");
+ }
+ else if (FAL_ACL_RULE_IP6 == *val)
+ {
+ dprintf("ip6");
+ }
+ else if (FAL_ACL_RULE_UDF == *val)
+ {
+ dprintf("udf");
+ }
+ else
+ {
+ dprintf("unknow");
+ }
+}
+
+sw_error_t
+cmd_data_check_fieldop(char *cmdstr, fal_acl_field_op_t def,
+ fal_acl_field_op_t * val)
+{
+ if (0 == cmdstr[0])
+ {
+ *val = def;
+ }
+ else if ((!strcasecmp(cmdstr, "mask")) || (!strcasecmp(cmdstr, "m")))
+ {
+ *val = FAL_ACL_FIELD_MASK;
+ }
+ else if ((!strcasecmp(cmdstr, "range")) || (!strcasecmp(cmdstr, "r")))
+ {
+ *val = FAL_ACL_FIELD_RANGE;
+ }
+ else if ((!strcasecmp(cmdstr, "le")) || (!strcasecmp(cmdstr, "l")))
+ {
+ *val = FAL_ACL_FIELD_LE;
+ }
+ else if ((!strcasecmp(cmdstr, "ge")) || (!strcasecmp(cmdstr, "g")))
+ {
+ *val = FAL_ACL_FIELD_GE;
+ }
+ else if ((!strcasecmp(cmdstr, "ne")) || (!strcasecmp(cmdstr, "n")))
+ {
+ *val = FAL_ACL_FIELD_NE;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_fieldop(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ fal_acl_field_op_t *val;
+
+ val = (fal_acl_field_op_t *) buf;
+ dprintf("%s", param_name);
+
+ if (FAL_ACL_FIELD_MASK == *val)
+ {
+ dprintf("mask");
+ }
+ else if (FAL_ACL_FIELD_RANGE == *val)
+ {
+ dprintf("range");
+ }
+ else if (FAL_ACL_FIELD_LE == *val)
+ {
+ dprintf("le");
+ }
+ else if (FAL_ACL_FIELD_GE == *val)
+ {
+ dprintf("ge");
+ }
+ else if (FAL_ACL_FIELD_NE == *val)
+ {
+ dprintf("ne");
+ }
+ else
+ {
+ dprintf("unknow");
+ }
+}
+
+sw_error_t
+cmd_data_check_ip4addr(char *cmdstr, void * val, a_uint32_t size)
+{
+ char *tmp = NULL;
+ a_uint32_t i = 0, j;
+ a_uint32_t addr;
+ fal_ip4_addr_t ip4;
+ char cmd[128] = { 0 };
+
+ memset(&ip4, 0, sizeof (fal_ip4_addr_t));
+ if (NULL == cmdstr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmdstr[0])
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (i = 0; i < 128; i++)
+ {
+ if (0 == cmdstr[i])
+ {
+ break;
+ }
+ }
+
+ i++;
+ if (128 < i)
+ {
+ i = 128;
+ }
+
+ memcpy(cmd, cmdstr, i);
+ tmp = (void *) strtok(cmd, ".");
+ i = 0;
+ while (tmp)
+ {
+ if (4 <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if ((3 < strlen(tmp)) || (0 == strlen(tmp)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (j = 0; j < strlen(tmp); j++)
+ {
+ if (A_FALSE == is_dec(tmp[j]))
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+
+ sscanf(tmp, "%d", &addr);
+ if (255 < addr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ ip4 |= ((addr & 0xff) << (24 - i * 8));
+ i++;
+ tmp = (void *) strtok(NULL, ".");
+ }
+
+ if (4 != i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ *(fal_ip4_addr_t*)val = ip4;
+ return SW_OK;
+}
+
+void
+cmd_data_print_ip4addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip4_addr_t ip4;
+
+ ip4 = *((fal_ip4_addr_t *) buf);
+ dprintf("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ dprintf("%d.", (ip4 >> (24 - i * 8)) & 0xff);
+ }
+ dprintf("%d", (ip4 & 0xff));
+}
+
+sw_error_t
+cmd_data_check_multi(char *info, void *val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_igmp_sg_entry_t entry;
+
+ memset(&entry, 0, sizeof (fal_igmp_sg_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("group type", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.group.type), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if(entry.group.type==0)
+ {
+ cmd_data_check_element("group ip4 addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.group.u.ip4_addr), 4));
+ }
+ else
+ cmd_data_check_element("group ip6 addr", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd, &(entry.group.u.ip6_addr), 16));
+
+ do
+ {
+ cmd = get_sub_cmd("source type", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.source.type), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if(entry.source.type==0)
+ {
+ cmd_data_check_element("source ip4 addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.source.u.ip4_addr), 4));
+ }
+ else
+ cmd_data_check_element("source ip6 addr", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd, &(entry.source.u.ip6_addr), 16));
+
+ do
+ {
+ cmd = get_sub_cmd("portmap", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.port_map), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_igmp_sg_entry_t *)val = entry;
+
+ return SW_OK;
+}
+void
+cmd_data_print_multi(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_igmp_sg_entry_t *entry;
+
+ entry = (fal_igmp_sg_entry_t *) buf;
+
+ dprintf("\n[multicast info]: [group type]:%x [source type]:%x ", entry->group.type, entry->source.type);
+
+ if(entry->group.type == 0)
+ cmd_data_print_ip4addr("\n[group ip4 addr]:",
+ (a_uint32_t *) & (entry->group.u.ip4_addr),
+ sizeof (fal_ip4_addr_t));
+ else
+ cmd_data_print_ip6addr("\n[group ip6 addr]:",
+ (a_uint32_t *) & (entry->group.u.ip6_addr),
+ sizeof (fal_ip6_addr_t));
+
+ if(entry->source.type == 0)
+ cmd_data_print_ip4addr("\n[source ip4 addr]:",
+ (a_uint32_t *) & (entry->source.u.ip4_addr),
+ sizeof (fal_ip4_addr_t));
+ else
+ cmd_data_print_ip6addr("\n[source ip6 addr]:",
+ (a_uint32_t *) & (entry->source.u.ip6_addr),
+ sizeof (fal_ip6_addr_t));
+
+ dprintf("\n[entry portmap]: [portmap]:0x%x ", entry->port_map);
+
+}
+
+sw_error_t
+cmd_data_check_ip6addr(char *cmdstr, void * val, a_uint32_t size)
+{
+ char *tmp = NULL;
+ a_uint32_t j;
+ a_uint32_t i = 0, cnt = 0, rep = 0, loc = 0;
+ a_uint32_t data;
+ a_uint32_t addr[8];
+ fal_ip6_addr_t ip6;
+
+ if (NULL == cmdstr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmdstr[0])
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (i = 0; i < 8; i++)
+ {
+ addr[i] = 0;
+ }
+
+ for (i = 0; i < strlen(cmdstr); i++)
+ {
+ if (':' == cmdstr[i])
+ {
+ if ((i == (strlen(cmdstr) - 1))
+ || (0 == i))
+ {
+ return SW_BAD_VALUE;
+ }
+ cnt++;
+
+ if (':' == cmdstr[i - 1])
+ {
+ rep++;
+ loc = cnt - 1;
+ }
+ }
+ }
+
+ if (1 < rep)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ tmp = (void *) strtok(cmdstr, ":");
+ i = 0;
+ while (tmp)
+ {
+ if (8 <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if ((4 < strlen(tmp)) || (0 == strlen(tmp)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (j = 0; j < strlen(tmp); j++)
+ {
+ if (A_FALSE == is_hex(tmp[j]))
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+
+ sscanf(tmp, "%x", &data);
+ if (65535 < data)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ addr[i++] = data;
+ tmp = (void *) strtok(NULL, ":");
+ }
+
+ if (0 == rep)
+ {
+ if (8 != i)
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+ else
+ {
+ if (8 <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (j = i - 1; j >= loc; j--)
+ {
+ addr[8 - i + j] = addr[j];
+ addr[j] = 0;
+ }
+ }
+
+ for (i = 0; i < 4; i++)
+ {
+ ip6.ul[i] = (addr[i * 2] << 16) | addr[i * 2 + 1];
+ }
+
+ dprintf("\n");
+ for (i = 0; i < 4; i++)
+ {
+ dprintf("%08x ", ip6.ul[i]);
+ }
+ dprintf("\n");
+
+ *(fal_ip6_addr_t*)val = ip6;
+ return SW_OK;
+}
+
+void
+cmd_data_print_ip6addr(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint32_t i;
+ fal_ip6_addr_t ip6;
+
+ ip6 = *(fal_ip6_addr_t *) buf;
+ dprintf("%s", param_name);
+ for (i = 0; i < 3; i++)
+ {
+ dprintf("%x:%x:", (ip6.ul[i] >> 16) & 0xffff, ip6.ul[i] & 0xffff);
+ }
+ dprintf("%x:%x", (ip6.ul[3] >> 16) & 0xffff, ip6.ul[3] & 0xffff);
+}
+
+sw_error_t
+cmd_data_check_mac_field(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata;
+
+ /* get destination mac address field configuration */
+ cmd_data_check_element("mac dst addr field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("dst mac addr", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd,
+ &(entry->dest_mac_val),
+ sizeof
+ (fal_mac_addr_t)));
+
+ cmd_data_check_element("dst mac addr mask", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd,
+ &(entry->dest_mac_mask),
+ sizeof
+ (fal_mac_addr_t)));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_DA);
+ }
+
+ /* get source mac address field configuration */
+ cmd_data_check_element("mac src addr field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("src mac addr", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd,
+ &(entry->src_mac_val),
+ sizeof
+ (fal_mac_addr_t)));
+
+ cmd_data_check_element("src mac addr mask", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd,
+ &(entry->src_mac_mask),
+ sizeof
+ (fal_mac_addr_t)));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_SA);
+ }
+
+ /* get ethernet type field configuration */
+ cmd_data_check_element("ethernet type field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ethernet type", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535\n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xffff,
+ 0x0));
+ entry->ethtype_val = tmpdata & 0xffff;
+
+ cmd_data_check_element("ethernet type mask", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535\n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xffff,
+ 0x0));
+ entry->ethtype_mask = tmpdata & 0xffff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE);
+ }
+
+ /* get vlanid field configuration */
+ cmd_data_check_element("vlanid field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("vlanid opration", "mask",
+ "usage: <mask/range/le/ge/ne> \n",
+ cmd_data_check_fieldop, (cmd, FAL_ACL_FIELD_MASK,
+ &(entry->vid_op)));
+
+ if (FAL_ACL_FIELD_MASK == entry->vid_op)
+ {
+ cmd_data_check_element("vlanid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("vlanid mask", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->vid_mask = tmpdata & 0xfff;
+ }
+ else if (FAL_ACL_FIELD_RANGE == entry->vid_op)
+ {
+ cmd_data_check_element("vlanid low", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("vlanid high", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->vid_mask = tmpdata & 0xfff;
+ }
+ else
+ {
+ cmd_data_check_element("vlanid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->vid_val = tmpdata & 0xfff;
+ }
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_VID);
+ }
+
+ /* get vlan tagged field configuration */
+ cmd_data_check_element("vlan tagged field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("tagged", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->tagged_val = tmpdata & 0x1;
+
+ cmd_data_check_element("tagged mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->tagged_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_TAGGED);
+ }
+
+ /* get up field configuration */
+ cmd_data_check_element("up field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("up", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->up_val = tmpdata & 0x7;
+
+ cmd_data_check_element("up mask", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->up_mask = tmpdata & 0x7;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_UP);
+ }
+
+ /* get cfi field configuration */
+ cmd_data_check_element("cfi field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("cfi", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->cfi_val = tmpdata & 0x1;
+
+ cmd_data_check_element("cfi mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->cfi_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_CFI);
+ }
+
+ /* get svlan tagged field configuration */
+ cmd_data_check_element("svlan tagged field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("stagged", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->stagged_val = tmpdata & 0x1;
+
+ cmd_data_check_element("stagged mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->stagged_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_STAGGED);
+ }
+
+ /* get stag vlanid field configuration */
+ cmd_data_check_element("stag vid field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("stag vid opration", "mask",
+ "usage: <mask/range/le/ge/ne> \n",
+ cmd_data_check_fieldop, (cmd, FAL_ACL_FIELD_MASK,
+ &(entry->stag_vid_op)));
+
+ if (FAL_ACL_FIELD_MASK == entry->stag_vid_op)
+ {
+ cmd_data_check_element("stag vid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->stag_vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("stag vid mask", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->stag_vid_mask = tmpdata & 0xfff;
+ }
+ else if (FAL_ACL_FIELD_RANGE == entry->stag_vid_op)
+ {
+ cmd_data_check_element("stag vid low", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->stag_vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("stag vid high", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->stag_vid_mask = tmpdata & 0xfff;
+ }
+ else
+ {
+ cmd_data_check_element("stag vid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->stag_vid_val = tmpdata & 0xfff;
+ }
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_STAG_VID);
+ }
+
+
+ /* get stag priority field configuration */
+ cmd_data_check_element("stag pri field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("stag pri", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->stag_pri_val = tmpdata & 0x7;
+
+ cmd_data_check_element("stag pri mask", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->stag_pri_mask = tmpdata & 0x7;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI);
+ }
+
+ /* get stag dei field configuration */
+ cmd_data_check_element("stag dei field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("stag dei", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->stag_dei_val = tmpdata & 0x1;
+
+ cmd_data_check_element("stag dei mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->stag_dei_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI);
+ }
+
+ /* get cvlan tagged field configuration */
+ cmd_data_check_element("cvlan tagged field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ctagged", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ctagged_val = tmpdata & 0x1;
+
+ cmd_data_check_element("ctagged mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ctagged_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_CTAGGED);
+ }
+
+ /* get ctag vlanid field configuration */
+ cmd_data_check_element("ctag vid field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ctag vid opration", "mask",
+ "usage: <mask/range/le/ge/ne> \n",
+ cmd_data_check_fieldop, (cmd, FAL_ACL_FIELD_MASK,
+ &(entry->ctag_vid_op)));
+
+ if (FAL_ACL_FIELD_MASK == entry->ctag_vid_op)
+ {
+ cmd_data_check_element("ctag vid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->ctag_vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("ctag vid mask", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->ctag_vid_mask = tmpdata & 0xfff;
+ }
+ else if (FAL_ACL_FIELD_RANGE == entry->ctag_vid_op)
+ {
+ cmd_data_check_element("ctag vid low", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->ctag_vid_val = tmpdata & 0xfff;
+
+ cmd_data_check_element("ctag vid high", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->ctag_vid_mask = tmpdata & 0xfff;
+ }
+ else
+ {
+ cmd_data_check_element("ctag vid", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xfff, 0x0));
+ entry->ctag_vid_val = tmpdata & 0xfff;
+ }
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID);
+ }
+
+ /* get ctag priority field configuration */
+ cmd_data_check_element("ctag pri field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ctag pri", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->ctag_pri_val = tmpdata & 0x7;
+
+ cmd_data_check_element("ctag pri mask", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->ctag_pri_mask = tmpdata & 0x7;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI);
+ }
+
+ /* get ctag cfi field configuration */
+ cmd_data_check_element("ctag cfi field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ctag cfi", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ctag_cfi_val = tmpdata & 0x1;
+
+ cmd_data_check_element("ctag cfi mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ctag_cfi_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip4_field(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata;
+
+ /* get ip4 source address field configuration */
+ cmd_data_check_element("ip4 src address field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip4 src addr", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd,
+ &(entry->src_ip4_val), 4));
+
+ cmd_data_check_element("ip4 src addr mask", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd,
+ &(entry->src_ip4_mask), 4));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP4_SIP);
+ }
+
+ /* get ip4 destination address field configuration */
+ cmd_data_check_element("ip4 dst address field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip4 dst addr", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd,
+ &(entry->
+ dest_ip4_val), 4));
+
+ cmd_data_check_element("ip4 dst addr mask", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd,
+ &(entry->
+ dest_ip4_mask), 4));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP4_DIP);
+ }
+
+ /* get ripv1 field configuration */
+ cmd_data_check_element("ripv1 field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ripv1", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ripv1_val = tmpdata & 0x1;
+
+ cmd_data_check_element("ripv1 mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ripv1_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_RIPV1);
+ }
+
+ /* get dhcpv4 field configuration */
+ cmd_data_check_element("dhcpv4 field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("dhcpv4", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->dhcpv4_val = tmpdata & 0x1;
+
+ cmd_data_check_element("dhcpv4 mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->dhcpv4_mask = tmpdata & 0x1;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_DHCPV4);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip6_field(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata;
+
+ /* get ip6 source address field configuration */
+ cmd_data_check_element("ip6 src address field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip6 src addr", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd,
+ &(entry->src_ip6_val), 16));
+
+ cmd_data_check_element("ip6 src addr mask", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd,
+ &(entry->
+ src_ip6_mask), 16));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP6_SIP);
+ }
+
+ /* get ip6 destination address field configuration */
+ cmd_data_check_element("ip6 dst address field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip6 dst addr", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd,
+ &(entry->
+ dest_ip6_val), 16));
+
+ cmd_data_check_element("ip6 dst addr mask", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd,
+ &(entry->
+ dest_ip6_mask), 16));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP6_DIP);
+ }
+
+ /* get ip6 flow label field configuration */
+ cmd_data_check_element("ip6 flow label field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip6 label", NULL,
+ "usage: the format is 0x0-0xfffff or 0-1048575\n",
+ cmd_data_check_integer, (cmd,
+ &(entry->ip6_lable_val),
+ 0xfffff, 0x0));
+
+ cmd_data_check_element("ip6 label mask", NULL,
+ "usage: the format is 0x0-0xfffff or 0-1048575\n",
+ cmd_data_check_integer, (cmd,
+ &(entry->
+ ip6_lable_mask),
+ 0xfffff, 0x0));
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP6_LABEL);
+ }
+
+ /* get dhcpv6 field configuration */
+ cmd_data_check_element("dhcpv6 field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("dhcpv6", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->dhcpv6_val = tmpdata & 0xff;
+
+ cmd_data_check_element("dhcpv6 mask", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->dhcpv6_mask = tmpdata & 0xff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_DHCPV6);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ip_field(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata;
+
+ /* get ip protocol field configuration */
+ cmd_data_check_element("ip protocol field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip protocol", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->ip_proto_val = tmpdata & 0xff;
+
+ cmd_data_check_element("ip protocol mask", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->ip_proto_mask = tmpdata & 0xff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP_PROTO);
+ }
+
+ /* get ip dscp field configuration */
+ cmd_data_check_element("ip dscp field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip dscp", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->ip_dscp_val = tmpdata & 0xff;
+
+ cmd_data_check_element("ip dscp mask", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->ip_dscp_mask = tmpdata & 0xff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_IP_DSCP);
+ }
+
+ /* get ip l4 destination port field configuration */
+ cmd_data_check_element("ip l4 dst port field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip l4 dst port opration", "mask",
+ "usage: <mask/range/le/ge/ne> \n",
+ cmd_data_check_fieldop, (cmd, FAL_ACL_FIELD_MASK,
+ &(entry->
+ dest_l4port_op)));
+
+ if (FAL_ACL_FIELD_MASK == entry->dest_l4port_op)
+ {
+ cmd_data_check_element("ip l4 dst port", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->dest_l4port_val = tmpdata & 0xffff;
+
+ cmd_data_check_element("ip l4 dst port mask", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->dest_l4port_mask = tmpdata & 0xffff;
+ }
+ else if (FAL_ACL_FIELD_RANGE == entry->dest_l4port_op)
+ {
+ cmd_data_check_element("ip l4 dst port low", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->dest_l4port_val = tmpdata & 0xffff;
+
+ cmd_data_check_element("ip l4 dst port high", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->dest_l4port_mask = tmpdata & 0xffff;
+ }
+ else
+ {
+ cmd_data_check_element("ip l4 dst port", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->dest_l4port_val = tmpdata & 0xffff;
+ }
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_L4_DPORT);
+ }
+
+ /* get ip l4 source port field configuration */
+ cmd_data_check_element("ip l4 src port field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("ip l4 src port opration", "mask",
+ "usage: <mask/range/le/ge/ne> \n",
+ cmd_data_check_fieldop, (cmd, FAL_ACL_FIELD_MASK,
+ &(entry->
+ src_l4port_op)));
+
+ if (FAL_ACL_FIELD_MASK == entry->src_l4port_op)
+ {
+ cmd_data_check_element("ip l4 src port", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->src_l4port_val = tmpdata & 0xffff;
+
+ cmd_data_check_element("ip l4 src port mask", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->src_l4port_mask = tmpdata & 0xffff;
+ }
+ else if (FAL_ACL_FIELD_RANGE == entry->src_l4port_op)
+ {
+ cmd_data_check_element("ip l4 src port low", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->src_l4port_val = tmpdata & 0xffff;
+
+ cmd_data_check_element("ip l4 src port high", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->src_l4port_mask = tmpdata & 0xffff;
+ }
+ else
+ {
+ cmd_data_check_element("ip l4 src port", NULL,
+ "usage: the format is 0x0-0xffff or 0-65535 \n",
+ cmd_data_check_integer, (cmd, &tmpdata,
+ 0xffff, 0x0));
+ entry->src_l4port_val = tmpdata & 0xffff;
+ }
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_L4_SPORT);
+ }
+
+ /* get tcp flags field configuration */
+ cmd_data_check_element("tcp flags field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("tcp flags", NULL,
+ "usage: the format is 0x0-0x3f or 0-63 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x3f,
+ 0x0));
+ entry->tcp_flag_val = tmpdata & 0x3f;
+
+ cmd_data_check_element("tcp flags mask", NULL,
+ "usage: the format is 0x0-0x3f or 0-63 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x3f,
+ 0x0));
+ entry->tcp_flag_mask = tmpdata & 0x3f;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_TCP_FLAG);
+ }
+
+ /* get icmp type field configuration */
+ cmd_data_check_element("icmp type field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("icmp type", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->icmp_type_val = tmpdata & 0xff;
+
+ cmd_data_check_element("icmp type mask", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->icmp_type_mask = tmpdata & 0xff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_ICMP_TYPE);
+ }
+
+ /* get icmp code field configuration */
+ cmd_data_check_element("icmp code field", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("icmp code", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->icmp_code_val = tmpdata & 0xff;
+
+ cmd_data_check_element("icmp code mask", NULL,
+ "usage: the format is 0x0-0xff or 0-255 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xff,
+ 0x0));
+ entry->icmp_code_mask = tmpdata & 0xff;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_ICMP_CODE);
+ }
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_udf_type(char *cmdstr, fal_acl_udf_type_t * arg_val, a_uint32_t size)
+{
+ if (NULL == cmdstr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmdstr, "l2"))
+ {
+ *arg_val = FAL_ACL_UDF_TYPE_L2;
+ }
+ else if (!strcasecmp(cmdstr, "l2snap"))
+ {
+ *arg_val = FAL_ACL_UDF_TYPE_L2_SNAP;
+ }
+ else if (!strcasecmp(cmdstr, "l3"))
+ {
+ *arg_val = FAL_ACL_UDF_TYPE_L3;
+ }
+ else if (!strcasecmp(cmdstr, "l3plus"))
+ {
+ *arg_val = FAL_ACL_UDF_TYPE_L3_PLUS;
+ }
+ else if (!strcasecmp(cmdstr, "l4"))
+ {
+ *arg_val = FAL_ACL_UDF_TYPE_L4;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_udf_type(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ fal_acl_udf_type_t *val;
+
+ val = (fal_acl_udf_type_t *) buf;
+ dprintf("%s", param_name);
+
+ if (FAL_ACL_UDF_TYPE_L2 == *val)
+ {
+ dprintf("l2");
+ }
+ else if (FAL_ACL_UDF_TYPE_L2_SNAP == *val)
+ {
+ dprintf("l2snap");
+ }
+ else if (FAL_ACL_UDF_TYPE_L3 == *val)
+ {
+ dprintf("l3");
+ }
+ else if (FAL_ACL_UDF_TYPE_L3_PLUS == *val)
+ {
+ dprintf("l3plus");
+ }
+ else if (FAL_ACL_UDF_TYPE_L4 == *val)
+ {
+ dprintf("l4");
+ }
+ else
+ {
+ dprintf("unknow");
+ }
+}
+
+sw_error_t
+cmd_data_check_udf_element(char *cmdstr, a_uint8_t * val, a_uint32_t * len)
+{
+ char *tmp = NULL;
+ a_uint32_t i = 0, j;
+ a_uint32_t data;
+
+ memset(val, 0, 16);
+ if (NULL == cmdstr)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmdstr[0])
+ {
+ return SW_BAD_VALUE;
+ }
+
+ tmp = (void *) strtok(cmdstr, "-");
+ while (tmp)
+ {
+ if (16 <= i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if ((2 < strlen(tmp)) || (0 == strlen(tmp)))
+ {
+ return SW_BAD_VALUE;
+ }
+
+ for (j = 0; j < strlen(tmp); j++)
+ {
+ if (A_FALSE == is_hex(tmp[j]))
+ {
+ return SW_BAD_VALUE;
+ }
+ }
+
+ sscanf(tmp, "%x", &data);
+
+ val[i++] = data & 0xff;
+ tmp = (void *) strtok(NULL, "-");
+ }
+
+ if (0 == i)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ *len = i;
+ return SW_OK;
+}
+
+void
+cmd_data_print_udf_element(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ a_uint8_t *val, i;
+
+ if (size)
+ {
+ val = (a_uint8_t *) buf;
+ dprintf("%s", param_name);
+
+ for (i = 0; i < (size - 1); i++)
+ {
+ dprintf("%02x-", *val);
+ val++;
+ }
+ dprintf("%02x", *val);
+ }
+}
+
+
+sw_error_t
+cmd_data_check_udf_field(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata, vlen, mlen;
+
+ /* get udf field configuration */
+ cmd_data_check_element("user define field", "no",
+ "usage: <yes/no/y/n>\n", cmd_data_check_confirm,
+ (cmd, A_FALSE, &tmpdata, sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("udf type", NULL,
+ "usage: <l2/l3>\n",
+ cmd_data_check_udf_type, (cmd,
+ &(entry->udf_type), 4));
+
+ cmd_data_check_element("udf offset", NULL,
+ "usage: <0-126, must be even>\n",
+ cmd_data_check_uint32, (cmd, &tmpdata, vlen));
+ entry->udf_offset = tmpdata;
+
+ cmd_data_check_element("udf value", NULL,
+ "usage: the format is xx-xx-xx-xx-xx\n",
+ cmd_data_check_udf_element, (cmd,
+ &(entry->udf_val[0]), &vlen));
+
+ cmd_data_check_element("udf mask", NULL,
+ "usage: the format is xx-xx-xx-xx-xx\n",
+ cmd_data_check_udf_element, (cmd,
+ &(entry->udf_mask[0]), &mlen));
+
+ if (vlen != mlen)
+ {
+ return SW_BAD_VALUE;
+ }
+ entry->udf_len = vlen;
+
+ FAL_FIELD_FLG_SET(entry->field_flg, FAL_ACL_FIELD_UDF);
+ }
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_acl_action(fal_acl_rule_t * entry)
+{
+ char *cmd;
+ a_uint32_t tmpdata;
+
+ /* get permit action configuration */
+ cmd_data_check_element("permit", "yes", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_TRUE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_PERMIT);
+ }
+
+ /* get deny action configuration */
+ cmd_data_check_element("deny", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_DENY);
+ }
+
+ /* get redirect to cpu action configuration */
+ cmd_data_check_element("rdt to cpu", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_RDTCPU);
+ }
+
+ /* get port redirection action configuration */
+ cmd_data_check_element("rdt to port", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("dst port", "null",
+ "usage: input port number such as 1,3\n",
+ cmd_data_check_portmap, (cmd, &entry->ports,
+ sizeof (fal_pbmp_t)));
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REDPT);
+ }
+
+ /* get copy to cpu action configuration */
+ cmd_data_check_element("copy to cpu", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_CPYCPU);
+ }
+
+ /* get mirror action configuration */
+ cmd_data_check_element("mirror", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_MIRROR);
+ }
+
+ /* get remark dscp action configuration */
+ cmd_data_check_element("remark dscp", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("dscp", NULL,
+ "usage: the format is 0x0-0x3f or 0-63 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x3f,
+ 0x0));
+ entry->dscp = tmpdata & 0x3f;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
+ }
+
+ /* get remark up action configuration */
+ cmd_data_check_element("remark up", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("up", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->up = tmpdata & 0x7;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_UP);
+ }
+
+ /* get remark queue action configuration */
+ cmd_data_check_element("remark queue", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ cmd_data_check_element("queue", NULL,
+ "usage: the format is 0x0-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->queue = tmpdata & 0x7;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_QUEUE);
+ }
+
+ /* get modify vlan action configuration */
+ cmd_data_check_element("modify vlan", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("vlan", NULL,
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xfff,
+ 0x0));
+ entry->vid = tmpdata & 0xfff;
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_MODIFY_VLAN);
+
+ if (!FAL_ACTION_FLG_TST(entry->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ cmd_data_check_element("port member", "null",
+ "usage: input port number such as 1,3\n",
+ cmd_data_check_portmap, (cmd, &entry->ports,
+ sizeof (fal_pbmp_t)));
+ }
+ }
+
+ /* get nest vlan action configuration */
+ cmd_data_check_element("nest vlan", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("vlan", NULL,
+ "usage: the format is 0x1-0xfff or 1-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xfff,
+ 0x1));
+ entry->vid = tmpdata & 0xfff;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_NEST_VLAN);
+ }
+
+ cmd_data_check_element("stag vid", "0",
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xfff,
+ 0x0));
+ entry->stag_vid = tmpdata & 0xfff;
+
+ cmd_data_check_element("ctag vid", "0",
+ "usage: the format is 0x0-0xfff or 0-4095 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xfff,
+ 0x0));
+ entry->ctag_vid = tmpdata & 0xfff;
+
+ /* chang lookup vid action configuration */
+ cmd_data_check_element("lookup vid change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID);
+ }
+
+ /* chang stag vid action configuration */
+ cmd_data_check_element("stag vid change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID);
+ }
+
+ /* chang stag pri action configuration */
+ cmd_data_check_element("stag pri change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("stag pri", NULL,
+ "usage: the format is 0x1-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->stag_pri = tmpdata & 0x7;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI);
+ }
+
+ /* chang stag dei action configuration */
+ cmd_data_check_element("stag dei change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("stag dei", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->stag_dei = tmpdata & 0x1;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI);
+ }
+
+ /* chang ctag vid action configuration */
+ cmd_data_check_element("ctag vid change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID);
+ }
+
+
+ /* chang ctag pri action configuration */
+ cmd_data_check_element("ctag pri change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("ctag pri", NULL,
+ "usage: the format is 0x1-0x7 or 0-7 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x7,
+ 0x0));
+ entry->ctag_pri = tmpdata & 0x7;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI);
+ }
+
+ /* chang ctag cfi action configuration */
+ cmd_data_check_element("ctag cfi change", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("ctag cfi", NULL,
+ "usage: the format is 0x0-0x1 or 0-1 \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0x1,
+ 0x0));
+ entry->ctag_cfi = tmpdata & 0x1;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI);
+ }
+
+ /* police action configuration */
+ cmd_data_check_element("police en", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("policer ptr", NULL,
+ "usage: the format is integer \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xffffffff,
+ 0x0));
+ entry->policer_ptr = tmpdata;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_POLICER_EN);
+ }
+
+ /* wcmp action configuration */
+ cmd_data_check_element("wcmp en", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("wcmp ptr", NULL,
+ "usage: the format is integer \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xffffffff,
+ 0x0));
+ entry->wcmp_ptr = tmpdata;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_WCMP_EN);
+ }
+
+ /* arp action configuration */
+ cmd_data_check_element("arp en", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("arp ptr", "0",
+ "usage: the format is integer \n",
+ cmd_data_check_integer, (cmd, &tmpdata, 0xffffffff,
+ 0x0));
+ entry->arp_ptr = tmpdata;
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_ARP_EN);
+ }
+
+ /* policy forward action configuration */
+ cmd_data_check_element("policy en", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (A_TRUE == tmpdata)
+ {
+ cmd_data_check_element("route", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (tmpdata)
+ {
+ entry->policy_fwd = FAL_ACL_POLICY_ROUTE;
+ }
+
+ cmd_data_check_element("snat", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (tmpdata)
+ {
+ entry->policy_fwd = FAL_ACL_POLICY_SNAT;
+ }
+
+ cmd_data_check_element("dnat", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (tmpdata)
+ {
+ entry->policy_fwd = FAL_ACL_POLICY_DNAT;
+ }
+
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN);
+ }
+
+ cmd_data_check_element("eg bypass", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS);
+ }
+
+ cmd_data_check_element("trigger intr", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_ACTION_FLG_SET(entry->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR);
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_aclrule(char *info, void *val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_acl_rule_t entry;
+ a_uint32_t tmpdata;
+
+ memset(&entry, 0, sizeof (fal_acl_rule_t));
+
+ dprintf("\n");
+
+ /* get rule type configuration */
+ cmd_data_check_element("rule type", NULL, "usage: <mac/ip4/ip6/udf> \n",
+ cmd_data_check_ruletype, (cmd, &entry.rule_type,
+ sizeof
+ (fal_acl_rule_type_t)));
+
+ if (FAL_ACL_RULE_MAC == entry.rule_type)
+ {
+ rv = cmd_data_check_mac_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+ }
+
+ if (FAL_ACL_RULE_IP4 == entry.rule_type)
+ {
+ rv = cmd_data_check_mac_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ rv = cmd_data_check_ip4_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ rv = cmd_data_check_ip_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+ }
+
+ if (FAL_ACL_RULE_IP6 == entry.rule_type)
+ {
+ rv = cmd_data_check_mac_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ rv = cmd_data_check_ip6_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ rv = cmd_data_check_ip_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+ }
+
+ rv = cmd_data_check_udf_field(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ /* get rule inverse configuration */
+ cmd_data_check_element("rule inverse", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+
+ if (tmpdata)
+ {
+ FAL_FIELD_FLG_SET(entry.field_flg, FAL_ACL_FIELD_INVERSE_ALL);
+ }
+
+ rv = cmd_data_check_acl_action(&entry);
+ if (SW_OK != rv)
+ {
+ return rv;
+ }
+
+ *(fal_acl_rule_t *) val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_aclrule(char * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ fal_acl_rule_t *rule;
+
+ rule = (fal_acl_rule_t *) buf;
+
+ cmd_data_print_ruletype("\n[rule_type]:",
+ (a_uint32_t *) & (rule->rule_type),
+ sizeof (fal_acl_rule_type_t));
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_DA))
+ {
+ cmd_data_print_macaddr("\n[mac_dst_addr]:",
+ (a_uint32_t *) & (rule->dest_mac_val),
+ sizeof (fal_mac_addr_t));
+ cmd_data_print_macaddr(" [mac_dst_addr_mask]:",
+ (a_uint32_t *) & (rule->dest_mac_mask),
+ sizeof (fal_mac_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_SA))
+ {
+ cmd_data_print_macaddr("\n[mac_src_addr]:",
+ (a_uint32_t *) & (rule->src_mac_val),
+ sizeof (fal_mac_addr_t));
+ cmd_data_print_macaddr(" [mac_src_addr_mask]:",
+ (a_uint32_t *) & (rule->src_mac_mask),
+ sizeof (fal_mac_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_ETHTYPE))
+ {
+ dprintf("\n[mac_eth_type]:0x%x", rule->ethtype_val);
+ dprintf(" [mac_eth_type_mask]:0x%x", rule->ethtype_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_TAGGED))
+ {
+ dprintf("\n[mac_tagged]:0x%x", rule->tagged_val);
+ dprintf(" [mac_tagged_mask]:0x%x", rule->tagged_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_UP))
+ {
+ dprintf("\n[mac_up]:0x%x", rule->up_val);
+ dprintf(" [mac_up_mask]:0x%x", rule->up_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CFI))
+ {
+ dprintf("\n[mac_cfi]:0x%x", rule->cfi_val);
+ dprintf(" [mac_cfi_mask]:0x%x", rule->cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_VID))
+ {
+ cmd_data_print_fieldop("\n[mac_vlanid_op]:",
+ (a_uint32_t *) & (rule->vid_op),
+ sizeof (fal_acl_field_op_t));
+ if (FAL_ACL_FIELD_MASK == rule->vid_op)
+ {
+ dprintf(" [vlanid]:0x%x", rule->vid_val);
+ dprintf(" [vlanid_mask]:0x%x", rule->vid_mask);
+ }
+ else
+ {
+ dprintf(" [vlanid_low]:0x%x", rule->vid_val);
+ dprintf(" [vlanid_high]:0x%x", rule->vid_mask);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAGGED))
+ {
+ dprintf("\n[mac_stagged]:0x%x", rule->stagged_val);
+ dprintf(" [mac_stagged_mask]:0x%x", rule->stagged_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_PRI))
+ {
+ dprintf("\n[mac_stag_pri]:0x%x", rule->stag_pri_val);
+ dprintf(" [mac_stag_pri_mask]:0x%x", rule->stag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_DEI))
+ {
+ dprintf("\n[mac_stag_dei]:0x%x", rule->stag_dei_val);
+ dprintf(" [mac_stag_dei_mask]:0x%x", rule->stag_dei_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_STAG_VID))
+ {
+ cmd_data_print_fieldop("\n[mac_stag_vlanid_op]:",
+ (a_uint32_t *) & (rule->stag_vid_op),
+ sizeof (fal_acl_field_op_t));
+ if (FAL_ACL_FIELD_MASK == rule->stag_vid_op)
+ {
+ dprintf(" [stag_vlanid]:0x%x", rule->stag_vid_val);
+ dprintf(" [stag_vlanid_mask]:0x%x", rule->stag_vid_mask);
+ }
+ else
+ {
+ dprintf(" [stag_vlanid_low]:0x%x", rule->stag_vid_val);
+ dprintf(" [stag_vlanid_high]:0x%x", rule->stag_vid_mask);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAGGED))
+ {
+ dprintf("\n[mac_ctagged]:0x%x", rule->ctagged_val);
+ dprintf(" [mac_ctagged_mask]:0x%x", rule->ctagged_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_PRI))
+ {
+ dprintf("\n[mac_ctag_pri]:0x%x", rule->ctag_pri_val);
+ dprintf(" [mac_ctag_pri_mask]:0x%x", rule->ctag_pri_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_CFI))
+ {
+ dprintf("\n[mac_ctag_cfi]:0x%x", rule->ctag_cfi_val);
+ dprintf(" [mac_ctag_cfi_mask]:0x%x", rule->ctag_cfi_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_MAC_CTAG_VID))
+ {
+ cmd_data_print_fieldop("\n[mac_ctag_vlanid_op]:",
+ (a_uint32_t *) & (rule->ctag_vid_op),
+ sizeof (fal_acl_field_op_t));
+ if (FAL_ACL_FIELD_MASK == rule->ctag_vid_op)
+ {
+ dprintf(" [ctag_vlanid]:0x%x", rule->ctag_vid_val);
+ dprintf(" [ctag_vlanid_mask]:0x%x", rule->ctag_vid_mask);
+ }
+ else
+ {
+ dprintf(" [ctag_vlanid_low]:0x%x", rule->ctag_vid_val);
+ dprintf(" [ctag_vlanid_high]:0x%x", rule->ctag_vid_mask);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_DIP))
+ {
+ cmd_data_print_ip4addr("\n[ip4_dst_addr]:",
+ (a_uint32_t *) & (rule->dest_ip4_val),
+ sizeof (fal_ip4_addr_t));
+ cmd_data_print_ip4addr(" [ip4_dst_addr_mask]:",
+ (a_uint32_t *) & (rule->dest_ip4_mask),
+ sizeof (fal_ip4_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP4_SIP))
+ {
+ cmd_data_print_ip4addr("\n[ip4_src_addr]:",
+ (a_uint32_t *) & (rule->src_ip4_val),
+ sizeof (fal_ip4_addr_t));
+ cmd_data_print_ip4addr(" [ip4_src_addr_mask]:",
+ (a_uint32_t *) & (rule->src_ip4_mask),
+ sizeof (fal_ip4_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_RIPV1))
+ {
+ dprintf("\n[ip4_ripv1]:0x%x", rule->ripv1_val);
+ dprintf(" [ip4_ripv1_mask]:0x%x", rule->ripv1_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_DHCPV4))
+ {
+ dprintf("\n[ip4_dhcpv4]:0x%x", rule->dhcpv4_val);
+ dprintf(" [ip4_dhcpv4_mask]:0x%x", rule->dhcpv4_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_DIP))
+ {
+ cmd_data_print_ip6addr("\n[ip6_dst_addr]:",
+ (a_uint32_t *) & (rule->dest_ip6_val),
+ sizeof (fal_ip6_addr_t));
+ cmd_data_print_ip6addr("\n[ip6_dst_addr_mask]:",
+ (a_uint32_t *) & (rule->dest_ip6_mask),
+ sizeof (fal_ip6_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_SIP))
+ {
+ cmd_data_print_ip6addr("\n[ip6_src_addr]:",
+ (a_uint32_t *) & (rule->src_ip6_val),
+ sizeof (fal_ip6_addr_t));
+ cmd_data_print_ip6addr("\n[ip6_src_addr_mask]:",
+ (a_uint32_t *) & (rule->src_ip6_mask),
+ sizeof (fal_ip6_addr_t));
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP6_LABEL))
+ {
+ dprintf("\n[ip6_flow_label]:0x%x", rule->ip6_lable_val);
+ dprintf(" [ip6_flow_label_mask]:0x%x", rule->ip6_lable_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_DHCPV6))
+ {
+ dprintf("\n[ip6_dhcpv6]:0x%x", rule->dhcpv6_val);
+ dprintf(" [ip6_dhcpv6_mask]:0x%x", rule->dhcpv6_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_PROTO))
+ {
+ dprintf("\n[ip_proto]:0x%x", rule->ip_proto_val);
+ dprintf(" [ip_proto_mask]:0x%x", rule->ip_proto_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_IP_DSCP))
+ {
+ dprintf("\n[ip_dscp]:0x%x", rule->ip_dscp_val);
+ dprintf(" [ip_dscp_mask]:0x%x", rule->ip_dscp_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_DPORT))
+ {
+ cmd_data_print_fieldop("\n[ip_l4_dport_op]:",
+ (a_uint32_t *) & (rule->dest_l4port_op),
+ sizeof (fal_acl_field_op_t));
+ if (FAL_ACL_FIELD_MASK == rule->dest_l4port_op)
+ {
+ dprintf(" [dport]:0x%x", rule->dest_l4port_val);
+ dprintf(" [dport_mask]:0x%x", rule->dest_l4port_mask);
+ }
+ else
+ {
+ dprintf(" [dport_low]:0x%x", rule->dest_l4port_val);
+ dprintf(" [dport_high]:0x%x", rule->dest_l4port_mask);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_L4_SPORT))
+ {
+ cmd_data_print_fieldop("\n[ip_l4_sport_op]:",
+ (a_uint32_t *) & (rule->src_l4port_op),
+ sizeof (fal_acl_field_op_t));
+ if (FAL_ACL_FIELD_MASK == rule->src_l4port_op)
+ {
+ dprintf(" [sport]:0x%x", rule->src_l4port_val);
+ dprintf(" [sport_mask]:0x%x", rule->src_l4port_mask);
+ }
+ else
+ {
+ dprintf(" [sport_low]:0x%x", rule->src_l4port_val);
+ dprintf(" [sport_high]:0x%x", rule->src_l4port_mask);
+ }
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_TCP_FLAG))
+ {
+ dprintf("\n[ip_tcp_flags]:0x%x", rule->tcp_flag_val);
+ dprintf(" [ip_tcp_flags_mask]:0x%x", rule->tcp_flag_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_TYPE))
+ {
+ dprintf("\n[ip_icmp_type]:0x%x", rule->icmp_type_val);
+ dprintf(" [ip_icmp_type_mask]:0x%x", rule->icmp_type_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_ICMP_CODE))
+ {
+ dprintf("\n[ip_icmp_code]:0x%x", rule->icmp_code_val);
+ dprintf(" [ip_icmp_code_mask]:0x%x", rule->icmp_code_mask);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_UDF))
+ {
+ cmd_data_print_udf_type("\n[udf_type]:",
+ (a_uint32_t *) & (rule->udf_type),
+ sizeof (fal_acl_udf_type_t));
+
+ dprintf(" [offset]:%d", rule->udf_offset);
+
+ cmd_data_print_udf_element("\n[udf_value]:",
+ (a_uint32_t *) & (rule->udf_val[0]),
+ rule->udf_len);
+
+ cmd_data_print_udf_element("\n[udf_mask]:",
+ (a_uint32_t *) & (rule->udf_mask[0]),
+ rule->udf_len);
+ }
+
+ if (FAL_FIELD_FLG_TST(rule->field_flg, FAL_ACL_FIELD_INVERSE_ALL))
+ {
+ dprintf("\n[rule_inverse]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_PERMIT))
+ {
+ dprintf("\n[permit]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_DENY))
+ {
+ dprintf("\n[deny]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_RDTCPU))
+ {
+ dprintf("\n[rdt_to_cpu]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_CPYCPU))
+ {
+ dprintf("\n[cpy_to_cpu]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_MIRROR))
+ {
+ dprintf("\n[mirror]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ dprintf("\n[rdt_to_port]:yes");
+ cmd_data_print_portmap(" [dest_port]:", rule->ports,
+ sizeof (fal_pbmp_t));
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_MODIFY_VLAN))
+ {
+ dprintf("\n[modify_vlan_id]:yes");
+ dprintf(" [vlan_id]:%d", rule->vid);
+ if (!FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REDPT))
+ {
+ cmd_data_print_portmap(" [port_member]:", rule->ports,
+ sizeof (fal_pbmp_t));
+ }
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_NEST_VLAN))
+ {
+ dprintf("\n[nest_vlan]:yes");
+ dprintf(" [vlan_id]:%d", rule->vid);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP))
+ {
+ dprintf("\n[remark_dscp]:yes");
+ dprintf(" [dscp]:%d", rule->dscp);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_UP))
+ {
+ dprintf("\n[remark_up]:yes");
+ dprintf(" [up]:%d", rule->up);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_QUEUE))
+ {
+ dprintf("\n[remark_queue]:yes");
+ dprintf(" [queue]:%d", rule->queue);
+ }
+
+ dprintf("\n[stag_vid]:%d", rule->stag_vid);
+ dprintf("\n[ctag_vid]:%d", rule->ctag_vid);
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_LOOKUP_VID))
+ {
+ dprintf("\n[change_lookup_vid]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_VID))
+ {
+ dprintf("\n[change_stag_vid]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_VID))
+ {
+ dprintf("\n[change_ctag_vid]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_PRI))
+ {
+ dprintf("\n[change_stag_pri]:yes");
+ dprintf(" [stag_pri]:%d", rule->stag_pri);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_STAG_DEI))
+ {
+ dprintf("\n[change_stag_dei]:yes");
+ dprintf(" [stag_dei]:%d", rule->stag_dei);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_PRI))
+ {
+ dprintf("\n[change_ctag_pri]:yes");
+ dprintf(" [ctag_pri]:%d", rule->ctag_pri);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_REMARK_CTAG_CFI))
+ {
+ dprintf("\n[change_ctag_cfi]:yes");
+ dprintf(" [ctag_cfi]:%d", rule->ctag_cfi);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_POLICER_EN))
+ {
+ dprintf("\n[police_en]:yes");
+ dprintf(" [policer_ptr]:%d", rule->policer_ptr);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_WCMP_EN))
+ {
+ dprintf("\n[wcmp_en]:yes");
+ dprintf(" [wcmp_ptr]:%d", rule->wcmp_ptr);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_ARP_EN))
+ {
+ dprintf("\n[arp_en]:yes");
+ dprintf(" [arp_ptr]:%d", rule->arp_ptr);
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_POLICY_FORWARD_EN))
+ {
+ if (FAL_ACL_POLICY_ROUTE == rule->policy_fwd)
+ {
+ dprintf("\n[policy_forward]:route");
+ }
+
+ if (FAL_ACL_POLICY_SNAT == rule->policy_fwd)
+ {
+ dprintf("\n[policy_forward]:snat");
+ }
+
+ if (FAL_ACL_POLICY_DNAT == rule->policy_fwd)
+ {
+ dprintf("\n[policy_forward]:dnat");
+ }
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_BYPASS_EGRESS_TRANS))
+ {
+ dprintf("\n[eg_bypass]:yes");
+ }
+
+ if (FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_MATCH_TRIGGER_INTR))
+ {
+ dprintf("\n[trigger_intr]:yes");
+ }
+
+ dprintf("\n[match_counter]:%d", rule->match_cnt);
+
+ return;
+}
+
+sw_error_t
+cmd_data_check_patternmode(char *cmd_str, led_pattern_mode_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "always_off"))
+ {
+ *arg_val = LED_ALWAYS_OFF;
+ }
+ else if (!strcasecmp(cmd_str, "always_blink"))
+ {
+ *arg_val = LED_ALWAYS_BLINK;
+ }
+ else if (!strcasecmp(cmd_str, "always_on"))
+ {
+ *arg_val = LED_ALWAYS_ON;
+ }
+ else if (!strcasecmp(cmd_str, "map"))
+ {
+ *arg_val = LED_PATTERN_MAP_EN;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_blinkfreq(char *cmd_str, led_blink_freq_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "2HZ"))
+ {
+ *arg_val = LED_BLINK_2HZ;
+ }
+ else if (!strcasecmp(cmd_str, "4HZ"))
+ {
+ *arg_val = LED_BLINK_4HZ;
+ }
+ else if (!strcasecmp(cmd_str, "8HZ"))
+ {
+ *arg_val = LED_BLINK_8HZ;
+ }
+ else if (!strcasecmp(cmd_str, "TXRX"))
+ {
+ *arg_val = LED_BLINK_TXRX;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_ledpattern(char *info, void * val, a_uint32_t size)
+{
+ char *cmd;
+ led_ctrl_pattern_t pattern;
+ a_uint32_t tmpdata;
+
+ memset(&pattern, 0, sizeof (led_ctrl_pattern_t));
+
+ dprintf("\n");
+
+ /* get pattern mode configuration */
+ cmd_data_check_element("pattern_mode", NULL, "usage: <always_off/always_blink/always_on/map>\n",
+ cmd_data_check_patternmode, (cmd, &pattern.mode,
+ sizeof(led_pattern_mode_t)));
+
+ if (LED_PATTERN_MAP_EN == pattern.mode)
+ {
+ cmd_data_check_element("full_duplex_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << FULL_DUPLEX_LIGHT_EN);
+ }
+
+ cmd_data_check_element("half_duplex_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << HALF_DUPLEX_LIGHT_EN);
+ }
+
+ cmd_data_check_element("power_on_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << POWER_ON_LIGHT_EN);
+ }
+
+ cmd_data_check_element("link_1000m_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << LINK_1000M_LIGHT_EN);
+ }
+
+ cmd_data_check_element("link_100m_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << LINK_100M_LIGHT_EN);
+ }
+
+ cmd_data_check_element("link_10m_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << LINK_10M_LIGHT_EN);
+ }
+
+ cmd_data_check_element("conllision_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << COLLISION_BLINK_EN);
+ }
+
+ cmd_data_check_element("rx_traffic_blink", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << RX_TRAFFIC_BLINK_EN);
+ }
+
+ cmd_data_check_element("tx_traffic_blink", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << TX_TRAFFIC_BLINK_EN);
+ }
+
+ cmd_data_check_element("linkup_override_light", "no", "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &tmpdata,
+ sizeof (a_bool_t)));
+ if (1 == tmpdata)
+ {
+ pattern.map |= (1 << LINKUP_OVERRIDE_EN);
+ }
+
+ cmd_data_check_element("blink freq", NULL, "usage: <2HZ/4HZ/8HZ/TXRX> \n",
+ cmd_data_check_blinkfreq, (cmd, &pattern.freq,
+ sizeof(led_blink_freq_t)));
+ }
+
+ *(led_ctrl_pattern_t *)val = pattern;
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_ledpattern(a_uint8_t * param_name, a_uint32_t * buf,
+ a_uint32_t size)
+{
+ led_ctrl_pattern_t *pattern;
+
+ pattern = (led_ctrl_pattern_t *) buf;
+
+ if (LED_ALWAYS_OFF == pattern->mode)
+ {
+ dprintf("[pattern_mode]:always_off");
+ }
+ else if (LED_ALWAYS_BLINK == pattern->mode)
+ {
+ dprintf("[pattern_mode]:always_blink");
+ }
+ else if (LED_ALWAYS_ON == pattern->mode)
+ {
+ dprintf("[pattern_mode]:always_on");
+ }
+ else
+ {
+ dprintf("[pattern_mode]:map");
+ }
+ dprintf("\n");
+
+ if (LED_PATTERN_MAP_EN == pattern->mode)
+ {
+ if (pattern->map & (1 << FULL_DUPLEX_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[full_duplex_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << HALF_DUPLEX_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[half_duplex_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << POWER_ON_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[power_on_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << LINK_1000M_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[link_1000m_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << LINK_100M_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[link_100m_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << LINK_10M_LIGHT_EN))
+ {
+ cmd_data_print_confirm("[link_10m_light]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << COLLISION_BLINK_EN))
+ {
+ cmd_data_print_confirm("[conllision_blink]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << RX_TRAFFIC_BLINK_EN))
+ {
+ cmd_data_print_confirm("[rx_traffic_blink]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << TX_TRAFFIC_BLINK_EN))
+ {
+ cmd_data_print_confirm("[tx_traffic_blink]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (pattern->map & (1 << LINKUP_OVERRIDE_EN))
+ {
+ cmd_data_print_confirm("[linkup_override]:", A_TRUE, sizeof (a_bool_t));
+ dprintf("\n");
+ }
+
+ if (LED_BLINK_2HZ == pattern->freq)
+ {
+ dprintf("[blink_frequency]:2HZ\n");
+ }
+ else if (LED_BLINK_4HZ == pattern->freq)
+ {
+ dprintf("[blink_frequency]:4HZ\n");
+ }
+ else if (LED_BLINK_8HZ == pattern->freq)
+ {
+ dprintf("[blink_frequency]:8HZ\n");
+ }
+ else
+ {
+ dprintf("[blink_frequency]:TXRX\n");
+ }
+ }
+}
+
+/*Shiva*/
+sw_error_t
+cmd_data_check_invlan_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "admit_all"))
+ {
+ *arg_val = FAL_INVLAN_ADMIT_ALL;
+ }
+ else if (!strcasecmp(cmd_str, "admit_tagged"))
+ {
+ *arg_val = FAL_INVLAN_ADMIT_TAGGED;
+ }
+ else if (!strcasecmp(cmd_str, "admit_untagged"))
+ {
+ *arg_val = FAL_INVLAN_ADMIT_UNTAGGED;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_invlan_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == FAL_INVLAN_ADMIT_ALL)
+ {
+ dprintf("ADMIT_ALL");
+ }
+ else if (*(a_uint32_t *) buf == FAL_INVLAN_ADMIT_TAGGED)
+ {
+ dprintf("ADMIT_TAGGED");
+ }
+ else if (*(a_uint32_t *) buf == FAL_INVLAN_ADMIT_UNTAGGED)
+ {
+ dprintf("ADMIT_UNTAGGED");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_vlan_propagation(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "disable"))
+ {
+ *arg_val = FAL_VLAN_PROPAGATION_DISABLE;
+ }
+ else if (!strcasecmp(cmd_str, "clone"))
+ {
+ *arg_val = FAL_VLAN_PROPAGATION_CLONE;
+ }
+ else if (!strcasecmp(cmd_str, "replace"))
+ {
+ *arg_val = FAL_VLAN_PROPAGATION_REPLACE;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_vlan_propagation(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == FAL_VLAN_PROPAGATION_DISABLE)
+ {
+ dprintf("DISABLE");
+ }
+ else if (*(a_uint32_t *) buf == FAL_VLAN_PROPAGATION_CLONE)
+ {
+ dprintf("CLONE");
+ }
+ else if (*(a_uint32_t *) buf == FAL_VLAN_PROPAGATION_REPLACE)
+ {
+ dprintf("REPLACE");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_vlan_translation(char *info, fal_vlan_trans_entry_t *val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_vlan_trans_entry_t entry;
+
+ memset(&entry, 0, sizeof (fal_vlan_trans_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("ovid", "1");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 4095\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &entry.o_vid, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 4095\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("bi direction", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.bi_dir,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("forward direction", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.forward_dir,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("reverse direction", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.reverse_dir,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("svid", "1");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 4095\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &entry.s_vid, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 4095\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cvid", "1");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 4095\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &entry.c_vid, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 4095\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("ovid_is_cvid", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.o_vid_is_cvid,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("svid_enable", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.s_vid_enable,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cvid_enable", "yes");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.c_vid_enable,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("one_2_one_vlan", "no");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.one_2_one_vlan,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_vlan_translation(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_vlan_trans_entry_t *entry;
+
+ entry = (fal_vlan_trans_entry_t *) buf;
+ dprintf("[Ovid]:0x%x [Svid]:0x%x [Cvid]:0x%x [BiDirect]:%s [ForwardDirect]:%s [ReverseDirect]:%s",
+ entry->o_vid, entry->s_vid, entry->c_vid,
+ entry->bi_dir?"ENABLE":"DISABLE",
+ entry->forward_dir?"ENABLE":"DISABLE",
+ entry->reverse_dir?"ENABLE":"DISABLE");
+
+ dprintf("[OvidIsCvid]:%s [SvidEnable]:%s [CvidEnable]:%s [One2OneVlan]:%s",
+ entry->o_vid_is_cvid?"YES":"NO",
+ entry->s_vid_enable?"YES":"NO",
+ entry->c_vid_enable?"YES":"NO",
+ entry->one_2_one_vlan?"YES":"NO");
+
+}
+
+sw_error_t
+cmd_data_check_qinq_mode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "ctag"))
+ {
+ *arg_val = FAL_QINQ_CTAG_MODE;
+ }
+ else if (!strcasecmp(cmd_str, "stag"))
+ {
+ *arg_val = FAL_QINQ_STAG_MODE;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_qinq_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == FAL_QINQ_CTAG_MODE)
+ {
+ dprintf("CTAG");
+ }
+ else if (*(a_uint32_t *) buf == FAL_QINQ_STAG_MODE)
+ {
+ dprintf("STAG");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_qinq_role(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "edge"))
+ {
+ *arg_val = FAL_QINQ_EDGE_PORT;
+ }
+ else if (!strcasecmp(cmd_str, "core"))
+ {
+ *arg_val = FAL_QINQ_CORE_PORT;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_qinq_role(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == FAL_QINQ_EDGE_PORT)
+ {
+ dprintf("EDGE");
+ }
+ else if (*(a_uint32_t *) buf == FAL_QINQ_CORE_PORT)
+ {
+ dprintf("CORE");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+void
+cmd_data_print_cable_status(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+
+ if (*(a_uint32_t *) buf == FAL_CABLE_STATUS_NORMAL)
+ {
+ dprintf("NORMAL");
+ }
+ else if (*(a_uint32_t *) buf == FAL_CABLE_STATUS_SHORT)
+ {
+ dprintf("SHORT");
+ }
+ else if (*(a_uint32_t *) buf == FAL_CABLE_STATUS_OPENED)
+ {
+ dprintf("OPENED");
+ }
+ else if (*(a_uint32_t *) buf == FAL_CABLE_STATUS_INVALID)
+ {
+ dprintf("INVALID");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+void
+cmd_data_print_cable_len(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:%d", param_name, *(a_uint32_t *) buf);
+}
+
+inline char*
+cmd_cpu_mode(hsl_init_mode mode)
+{
+ switch (mode)
+ {
+ case HSL_NO_CPU:
+ return "no_cpu";
+ case HSL_CPU_1:
+ return "cpu_1";
+ case HSL_CPU_2:
+ return "cpu_2";
+ case HSL_CPU_1_PLUS:
+ return "cpu_1_plus";
+ }
+
+ return "unknow";
+}
+
+inline char*
+cmd_access_mode(hsl_access_mode mode)
+{
+ switch (mode)
+ {
+ case HSL_MDIO:
+ return "mdio";
+ case HSL_HEADER:
+ return "header";
+ }
+
+ return "unknow";
+}
+
+static void
+_cmd_collect_shell_cfg(ssdk_cfg_t *shell_cfg)
+{
+ memset(shell_cfg, 0, sizeof(ssdk_cfg_t));
+ shell_cfg->init_cfg = init_cfg;
+
+#ifdef VERSION
+ aos_mem_copy(shell_cfg->build_ver, VERSION, sizeof(VERSION));
+#endif
+
+#ifdef BUILD_DATE
+ aos_mem_copy(shell_cfg->build_date, BUILD_DATE, sizeof(BUILD_DATE));
+#endif
+
+#if defined ATHENA
+ aos_mem_copy(shell_cfg->chip_type, "athena", sizeof("athena"));
+#elif defined GARUDA
+ aos_mem_copy(shell_cfg->chip_type, "garuda", sizeof("garuda"));
+#elif defined SHIVA
+ aos_mem_copy(shell_cfg->chip_type, "shiva", sizeof("shiva"));
+#elif defined HORUS
+ aos_mem_copy(shell_cfg->chip_type, "horus", sizeof("horus"));
+#elif defined ISIS
+ aos_mem_copy(shell_cfg->chip_type, "isis", sizeof("isis"));
+#elif defined ISISC
+ aos_mem_copy(shell_cfg->chip_type, "isisc", sizeof("isisc"));
+#endif
+
+#ifdef CPU
+ aos_mem_copy(shell_cfg->cpu_type, CPU, sizeof(CPU));
+#endif
+
+#ifdef OS
+ aos_mem_copy(shell_cfg->os_info, OS, sizeof(OS));
+#if defined KVER26
+ aos_mem_copy(shell_cfg->os_info+sizeof(OS)-1, " version 2.6", sizeof(" version 2.6"));
+#elif defined KVER24
+ aos_mem_copy(shell_cfg->os_info+sizeof(OS)-1, " version 2.4", sizeof(" version 2.4"));
+#else
+ aos_mem_copy(shell_cfg->os_info+sizeof(OS)-1, " version unknown", sizeof(" version unknown"));
+#endif
+#endif
+
+#ifdef HSL_STANDALONG
+ shell_cfg->fal_mod = A_FALSE;
+#else
+ shell_cfg->fal_mod = A_TRUE;
+#endif
+
+#ifdef USER_MODE
+ shell_cfg->kernel_mode = A_FALSE;
+#else
+ shell_cfg->kernel_mode = A_TRUE;
+#endif
+
+#ifdef UK_IF
+ shell_cfg->uk_if = A_TRUE;
+#else
+ shell_cfg->uk_if = A_FALSE;
+#endif
+
+ return;
+}
+
+#define BOOL2STR(val_bool) (((val_bool)==A_TRUE)?"true":"false" )
+#define BOOL2NAME(val_bool) (((feature->in_##val_bool)==A_TRUE)?(#val_bool):"" )
+#define DEFINED2STR(name) (((init->reg_func.name))?"y":"n" )
+
+static void
+_cmd_data_print_cfg(ssdk_cfg_t *entry)
+{
+ ssdk_init_cfg *init = &(entry->init_cfg);
+
+ dprintf("[build verison]:%-10s [build date]:%s\n", entry->build_ver, entry->build_date);
+ dprintf("[chip type]:%-14s [arch]:%-12s [os]:%s\n", entry->chip_type, entry->cpu_type, entry->os_info);
+ dprintf("[fal]:%-20s [kernel mode]:%-5s [uk if]:%s\n",
+ BOOL2STR(entry->fal_mod), BOOL2STR(entry->kernel_mode), BOOL2STR(entry->uk_if));
+
+ dprintf("[cpu mode]:%-15s [reg access]:%-6s [ioctl minor]:%d\n",
+ cmd_cpu_mode(init->cpu_mode), cmd_access_mode(init->reg_mode),
+ init->nl_prot);
+
+ dprintf("[inf defined]:mdio_set(%s) mdio_get(%s) header_reg_set(%s) header_reg_get(%s)\n",
+ DEFINED2STR(mdio_set), DEFINED2STR(mdio_get), DEFINED2STR(header_reg_set), DEFINED2STR(header_reg_get));
+
+}
+
+void
+cmd_data_print_ssdk_cfg(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ ssdk_cfg_t *ssdk_cfg = (ssdk_cfg_t *) buf;
+ dprintf("1.SSDK CONFIGURATION:\n");
+ _cmd_data_print_cfg(ssdk_cfg);
+
+ dprintf("\n2.DEMO SHELL CONFIGURATION:\n");
+ ssdk_cfg_t shell_cfg;
+ _cmd_collect_shell_cfg(&shell_cfg);
+ _cmd_data_print_cfg(&shell_cfg);
+
+ dprintf("\n3.SSDK FEATURES LIST:\n");
+ ssdk_features *feature = &(ssdk_cfg->features);
+ dprintf("%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s\n",
+ BOOL2NAME(acl), BOOL2NAME(fdb), BOOL2NAME(igmp), BOOL2NAME(leaky),
+ BOOL2NAME(led), BOOL2NAME(mib), BOOL2NAME(mirror), BOOL2NAME(misc),
+ BOOL2NAME(portcontrol), BOOL2NAME(portvlan), BOOL2NAME(qos), BOOL2NAME(rate),
+ BOOL2NAME(stp), BOOL2NAME(vlan), BOOL2NAME(reduced_acl),
+ BOOL2NAME(cosmap), BOOL2NAME(ip), BOOL2NAME(nat), BOOL2NAME(sec), BOOL2NAME(trunk), BOOL2NAME(interfacectrl));
+
+}
+
+sw_error_t
+cmd_data_check_hdrmode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "noheader"))
+ {
+ *arg_val = FAL_NO_HEADER_EN;
+ }
+ else if (!strcasecmp(cmd_str, "onlymanagement"))
+ {
+ *arg_val = FAL_ONLY_MANAGE_FRAME_EN;
+ }
+ else if (!strcasecmp(cmd_str, "allframe"))
+ {
+ *arg_val = FAL_ALL_TYPE_FRAME_EN;
+ }
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_hdrmode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_NO_HEADER_EN)
+ {
+ dprintf("NOHEADER");
+ }
+ else if (*(a_uint32_t *) buf == FAL_ONLY_MANAGE_FRAME_EN)
+ {
+ dprintf("ONLYMANAGEMENT");
+ }
+ else if (*(a_uint32_t *) buf == FAL_ALL_TYPE_FRAME_EN)
+ {
+ dprintf("ALLFRAME");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_fdboperation(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_fdb_op_t entry;
+
+ memset(&entry, 0, sizeof (fal_fdb_op_t));
+
+ do
+ {
+ cmd = get_sub_cmd("port_en", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.port_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("fid_en", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.fid_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("multi_en", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.multicast_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_fdb_op_t *) val = entry;
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_pppoe(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_pppoe_session_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_pppoe_session_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("sessionid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &entry.session_id, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: the range is 0 -- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("multi_session", "no");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.multi_session,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("uni_session", "no");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.uni_session,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_pppoe_session_t*)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_pppoe(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_pppoe_session_t *entry;
+
+ entry = (fal_pppoe_session_t *) buf;
+ dprintf("[EntryID]:0x%x [SessionID]:0x%x [MultiSession]:%s [UniSession]:%s",
+ entry->entry_id,
+ entry->session_id,
+ entry->multi_session ? "YES":"NO",
+ entry->uni_session ? "YES":"NO");
+}
+
+sw_error_t
+cmd_data_check_host_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_host_entry_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_host_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entryflags", "0x1");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: bitmap for host entry\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.flags), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: bitmap for host entry\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entrystatus", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.status), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (FAL_IP_IP4_ADDR & (entry.flags))
+ {
+ cmd_data_check_element("ip4 addr", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.ip4_addr), 4));
+ }
+ else
+ {
+ cmd_data_check_element("ip6 addr", NULL,
+ "usage: the format is xxxx::xxxx \n",
+ cmd_data_check_ip6addr, (cmd, &(entry.ip6_addr), 16));
+ }
+
+ cmd_data_check_element("mac addr", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd,
+ &(entry.mac_addr),
+ sizeof (fal_mac_addr_t)));
+
+ do
+ {
+ cmd = get_sub_cmd("interface id", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.intf_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("port id", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.port_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("action", "forward");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_maccmd(cmd, &(entry.action),
+ sizeof (fal_fwd_cmd_t));
+ if (SW_OK != rv)
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("mirror", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.mirror_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("counter", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.counter_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == entry.counter_en)
+ {
+ do
+ {
+ cmd = get_sub_cmd("counter id", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.counter_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ }
+
+ *(fal_host_entry_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_host_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_host_entry_t *entry;
+
+ entry = (fal_host_entry_t *) buf;
+ dprintf("\n[entryid]:0x%x [entryflags]:0x%x [entrystatus]:0x%x",
+ entry->entry_id, entry->flags, entry->status);
+
+ if (FAL_IP_IP4_ADDR & entry->flags)
+ {
+ cmd_data_print_ip4addr("\n[ip_addr]:",
+ (a_uint32_t *) & (entry->ip4_addr),
+ sizeof (fal_ip4_addr_t));
+ }
+ else
+ {
+ cmd_data_print_ip6addr("\n[ip_addr]:",
+ (a_uint32_t *) & (entry->ip6_addr),
+ sizeof (fal_ip6_addr_t));
+ }
+
+ cmd_data_print_macaddr(" [mac_addr]:",
+ (a_uint32_t *) & (entry->mac_addr),
+ sizeof (fal_mac_addr_t));
+
+ dprintf("\n[interfaceid]:0x%x [portid]:0x%x ", entry->intf_id, entry->port_id);
+
+ cmd_data_print_maccmd("action", (a_uint32_t *) & (entry->action),
+ sizeof (fal_fwd_cmd_t));
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ dprintf("\n[mirror]:Enable ");
+ }
+ else
+ {
+ dprintf("\n[mirror]:Disable ");
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ dprintf("\n[counter]:Enable [counter_id]:%d [pkt]%d [byte]%d",
+ entry->counter_id, entry->packet, entry->byte);
+ }
+ else
+ {
+ dprintf("\n[couter]:Disable ");
+ }
+
+ if (A_TRUE == entry->pppoe_en)
+ {
+ dprintf("\n[pppoe]:Enable [pppoe_id]:%d", entry->pppoe_id);
+ }
+ else
+ {
+ dprintf("\n[pppoe]:Disable ");
+ }
+}
+
+sw_error_t
+cmd_data_check_arp_learn_mode(char *cmd_str, fal_arp_learn_mode_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "learnlocal"))
+ {
+ *arg_val = FAL_ARP_LEARN_LOCAL;
+ }
+ else if (!strcasecmp(cmd_str, "learnall"))
+ {
+ *arg_val = FAL_ARP_LEARN_ALL;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_arp_learn_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_ARP_LEARN_LOCAL)
+ {
+ dprintf("LearnLocal");
+ }
+ else if (*(a_uint32_t *) buf == FAL_ARP_LEARN_ALL)
+ {
+ dprintf("LearnAll");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_ip_guard_mode(char *cmd_str, fal_source_guard_mode_t * arg_val, a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "mac_ip"))
+ {
+ *arg_val = FAL_MAC_IP_GUARD;
+ }
+ else if (!strcasecmp(cmd_str, "mac_ip_port"))
+ {
+ *arg_val = FAL_MAC_IP_PORT_GUARD;
+ }
+ else if (!strcasecmp(cmd_str, "mac_ip_vlan"))
+ {
+ *arg_val = FAL_MAC_IP_VLAN_GUARD;
+ }
+ else if (!strcasecmp(cmd_str, "mac_ip_port_vlan"))
+ {
+ *arg_val = FAL_MAC_IP_PORT_VLAN_GUARD;
+ }
+ else if (!strcasecmp(cmd_str, "no_guard"))
+ {
+ *arg_val = FAL_NO_SOURCE_GUARD;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_ip_guard_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_MAC_IP_GUARD)
+ {
+ dprintf("MAC_IP_GUARD");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_IP_PORT_GUARD)
+ {
+ dprintf("MAC_IP_PORT_GUARD");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_IP_VLAN_GUARD)
+ {
+ dprintf("MAC_IP_VLAN_GUARD");
+ }
+ else if (*(a_uint32_t *) buf == FAL_MAC_IP_PORT_VLAN_GUARD)
+ {
+ dprintf("MAC_IP_PORT_VLAN_GUARD");
+ }
+ else if (*(a_uint32_t *) buf == FAL_NO_SOURCE_GUARD)
+ {
+ dprintf("NO_GUARD");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_nat_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ a_uint32_t tmp;
+ fal_nat_entry_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_nat_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entryflags", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: bitmap for host entry\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.flags), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: bitmap for host entry\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entrystatus", "0xf");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.status), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("select_idx", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.slct_idx), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ cmd_data_check_element("src addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.src_addr), 4));
+
+ cmd_data_check_element("trans addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.trans_addr), 4));
+
+ do
+ {
+ cmd = get_sub_cmd("port num", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: 0- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: 0- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.port_num = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("port range", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: 0- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: 0- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.port_range = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("action", "forward");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_maccmd(cmd, &entry.action,
+ sizeof (fal_fwd_cmd_t));
+ if (SW_OK != rv)
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("mirror", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.mirror_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("counter", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.counter_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == entry.counter_en)
+ {
+ do
+ {
+ cmd = get_sub_cmd("counter id", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.counter_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ }
+
+ *(fal_nat_entry_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_nat_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_nat_entry_t *entry;
+
+ entry = (fal_nat_entry_t *) buf;
+ dprintf("\n[entryid]:0x%x [entryflags]:0x%x [entrystatus]:0x%x [select_idx]:0x%x",
+ entry->entry_id, entry->flags, entry->status, entry->slct_idx);
+
+ cmd_data_print_ip4addr("\n[src_addr]:",
+ (a_uint32_t *) & (entry->src_addr),
+ sizeof (fal_ip4_addr_t));
+
+ cmd_data_print_ip4addr("\n[trans_addr]:",
+ (a_uint32_t *) & (entry->trans_addr),
+ sizeof (fal_ip4_addr_t));
+
+ dprintf("\n[port_num]:0x%x [port_range]:0x%x ", entry->port_num, entry->port_range);
+
+ cmd_data_print_maccmd("action", (a_uint32_t *) & (entry->action),
+ sizeof (fal_fwd_cmd_t));
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ dprintf("\n[mirror]:Enable ");
+ }
+ else
+ {
+ dprintf("\n[mirror]:Disable ");
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ dprintf("\n[counter]:Enable [counter_id]:%d [in_pkt]%d [in_byte]%d [eg_pkt]%d [eg_byte]%d ",
+ entry->counter_id, entry->ingress_packet, entry->ingress_byte,
+ entry->egress_packet, entry->egress_byte);
+ }
+ else
+ {
+ dprintf("\n[couter]:Disable ");
+ }
+}
+
+sw_error_t
+cmd_data_check_napt_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ a_uint32_t tmp;
+ fal_napt_entry_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_napt_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entryflags", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: bitmap for host entry\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.flags), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: bitmap for host entry\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("entrystatus", "0xf");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.status), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ cmd_data_check_element("src addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.src_addr), 4));
+
+ cmd_data_check_element("dst addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.dst_addr), 4));
+
+ if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & (entry.flags))
+ {
+ do
+ {
+ cmd = get_sub_cmd("trans addr index", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.trans_addr), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ }
+ else
+ {
+ cmd_data_check_element("trans addr", "0.0.0.0",
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.trans_addr), 4));
+ }
+
+ do
+ {
+ cmd = get_sub_cmd("src port", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: 0- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: 0- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.src_port = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("dst port", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: 0- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: 0- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.dst_port = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("trans port", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: 0- 65535\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: 0- 65535\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.trans_port = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("action", "forward");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_maccmd(cmd, &(entry.action),
+ sizeof (fal_fwd_cmd_t));
+ if (SW_OK != rv)
+ dprintf("usage: <forward/drop/cpycpu/rdtcpu>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("mirror", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.mirror_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("counter", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &entry.counter_en,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == entry.counter_en)
+ {
+ do
+ {
+ cmd = get_sub_cmd("counter id", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.counter_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ }
+
+ *(fal_napt_entry_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_napt_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_napt_entry_t *entry;
+
+ entry = (fal_napt_entry_t *) buf;
+ dprintf("\n[entryid]:0x%x [entryflags]:0x%x [entrystatus]:0x%x",
+ entry->entry_id, entry->flags, entry->status);
+
+ cmd_data_print_ip4addr("\n[src_addr]:",
+ (a_uint32_t *) & (entry->src_addr),
+ sizeof (fal_ip4_addr_t));
+
+ cmd_data_print_ip4addr("\n[dst_addr]:",
+ (a_uint32_t *) & (entry->dst_addr),
+ sizeof (fal_ip4_addr_t));
+
+ if (FAL_NAT_ENTRY_TRANS_IPADDR_INDEX & entry->flags)
+ {
+ dprintf("\n[trans_addr_index]:0x%x", entry->trans_addr);
+ }
+ else
+ {
+ cmd_data_print_ip4addr("\n[trans_addr]:",
+ (a_uint32_t *) & (entry->trans_addr),
+ sizeof (fal_ip4_addr_t));
+ }
+
+ dprintf("\n[src_port]:0x%x [dst_port]:0x%x [trans_port]:0x%x ", entry->src_port, entry->dst_port, entry->trans_port);
+
+ cmd_data_print_maccmd("action", (a_uint32_t *) & (entry->action),
+ sizeof (fal_fwd_cmd_t));
+
+ if (A_TRUE == entry->mirror_en)
+ {
+ dprintf("\n[mirror]:Enable ");
+ }
+ else
+ {
+ dprintf("\n[mirror]:Disable ");
+ }
+
+ if (A_TRUE == entry->counter_en)
+ {
+ dprintf("\n[counter]:Enable [counter_id]:%d [in_pkt]%d [in_byte]%d [eg_pkt]%d [eg_byte]%d ",
+ entry->counter_id, entry->ingress_packet, entry->ingress_byte,
+ entry->egress_packet, entry->egress_byte);
+ }
+ else
+ {
+ dprintf("\n[couter]:Disable ");
+ }
+}
+
+sw_error_t
+cmd_data_check_napt_mode(char *cmd_str, fal_napt_mode_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (!strcasecmp(cmd_str, "fullcone"))
+ {
+ *arg_val = FAL_NAPT_FULL_CONE;
+ }
+ else if (!strcasecmp(cmd_str, "strictcone"))
+ {
+ *arg_val = FAL_NAPT_STRICT_CONE;
+ }
+ else if (!strcasecmp(cmd_str, "portstrict"))
+ {
+ *arg_val = FAL_NAPT_PORT_STRICT;
+ }
+ else if (!strcasecmp(cmd_str, "synmatric"))
+ {
+ *arg_val = FAL_NAPT_SYNMETRIC;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_napt_mode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_NAPT_FULL_CONE)
+ {
+ dprintf("FullCone");
+ }
+ else if (*(a_uint32_t *) buf == FAL_NAPT_STRICT_CONE)
+ {
+ dprintf("StrictCone");
+ }
+ else if (*(a_uint32_t *) buf == FAL_NAPT_PORT_STRICT)
+ {
+ dprintf("PortStrict");
+ }
+ else if (*(a_uint32_t *) buf == FAL_NAPT_SYNMETRIC)
+ {
+ dprintf("Synmatric");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_intf_mac_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ a_uint32_t tmp;
+ sw_error_t rv;
+ fal_intf_mac_entry_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_intf_mac_entry_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("vid low", NULL);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: low vlan id\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: low vlan id\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.vid_low = tmp & 0xffff;
+
+ do
+ {
+ cmd = get_sub_cmd("vid high", NULL);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: high vlan id\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: high vlan id\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ entry.vid_high = tmp & 0xffff;
+
+ cmd_data_check_element("mac addr", NULL,
+ "usage: the format is xx-xx-xx-xx-xx-xx \n",
+ cmd_data_check_macaddr, (cmd, &(entry.mac_addr),
+ sizeof (fal_mac_addr_t)));
+
+ do
+ {
+ cmd = get_sub_cmd("ip4_route", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.ip4_route,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("ip6_route", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &entry.ip6_route,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_intf_mac_entry_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_intf_mac_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_intf_mac_entry_t *entry;
+
+ entry = (fal_intf_mac_entry_t *) buf;
+ dprintf("\n[entryid]:0x%x [vid_low]:0x%x [vid_high]:0x%x",
+ entry->entry_id, entry->vid_low, entry->vid_high);
+
+ cmd_data_print_macaddr("\n[mac_addr]:",
+ (a_uint32_t *) & (entry->mac_addr),
+ sizeof (fal_mac_addr_t));
+
+ if (A_TRUE == entry->ip4_route)
+ {
+ dprintf("\n[ip4_route]:TRUE");
+ }
+ else
+ {
+ dprintf("\n[ip4_route]:FALSE");
+ }
+
+ if (A_TRUE == entry->ip6_route)
+ {
+ dprintf(" [ip6_route]:TRUE");
+ }
+ else
+ {
+ dprintf(" [ip6_route]:FALSE");
+ }
+}
+
+sw_error_t
+cmd_data_check_pub_addr_entry(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_nat_pub_addr_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_nat_pub_addr_t));
+
+ do
+ {
+ cmd = get_sub_cmd("entryid", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.entry_id), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ cmd_data_check_element("pub addr", NULL,
+ "usage: the format is xx.xx.xx.xx \n",
+ cmd_data_check_ip4addr, (cmd, &(entry.pub_addr), 4));
+
+ *(fal_nat_pub_addr_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_pub_addr_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_nat_pub_addr_t *entry;
+
+ entry = (fal_nat_pub_addr_t *) buf;
+ dprintf("[entryid]:0x%x ", entry->entry_id);
+ cmd_data_print_ip4addr("[pub_addr]:",
+ (a_uint32_t *) & (entry->pub_addr),
+ sizeof (fal_ip4_addr_t));
+
+}
+
+sw_error_t
+cmd_data_check_egress_shaper(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ a_bool_t bool;
+ fal_egress_shaper_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_egress_shaper_t));
+
+ do
+ {
+ cmd = get_sub_cmd("bytebased", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == bool)
+ {
+ entry.meter_unit = FAL_BYTE_BASED;
+ }
+ else
+ {
+ entry.meter_unit = FAL_FRAME_BASED;
+ }
+
+ do
+ {
+ cmd = get_sub_cmd("cir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cbs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("eir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("ebs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_egress_shaper_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_egress_shaper(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_egress_shaper_t *entry;
+
+ entry = (fal_egress_shaper_t *) buf;
+
+ if (FAL_BYTE_BASED == entry->meter_unit)
+ {
+ dprintf("\n[byte_based]:yes ");
+ }
+ else
+ {
+ dprintf("\n[byte_based]:no ");
+ }
+
+ dprintf("[cir]:0x%08x [cbs]:0x%08x [eir]:0x%08x [ebs]:0x%08x",
+ entry->cir, entry->cbs, entry->eir, entry->ebs);
+}
+
+sw_error_t
+cmd_data_check_policer_timesslot(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strncasecmp(cmd_str, "100us", 5))
+ *arg_val = FAL_RATE_MI_100US;
+ else if (!strncasecmp(cmd_str, "1ms", 3))
+ *arg_val = FAL_RATE_MI_1MS;
+ else if (!strncasecmp(cmd_str, "10ms", 4))
+ *arg_val = FAL_RATE_MI_10MS;
+ else if (!strncasecmp(cmd_str, "100ms", 5))
+ *arg_val = FAL_RATE_MI_100MS;
+ else
+ {
+ //dprintf("input error \n");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_policer_timesslot(char * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == FAL_RATE_MI_100US)
+ {
+ dprintf("100us");
+ }
+ else if (*(a_uint32_t *) buf == FAL_RATE_MI_1MS)
+ {
+ dprintf("1ms");
+ }
+ else if (*(a_uint32_t *) buf == FAL_RATE_MI_10MS)
+ {
+ dprintf("10ms");
+ }
+ else if (*(a_uint32_t *) buf == FAL_RATE_MI_100MS)
+ {
+ dprintf("100ms");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+
+sw_error_t
+cmd_data_check_acl_policer(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ a_bool_t bool;
+ fal_acl_policer_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_acl_policer_t));
+
+ do
+ {
+ cmd = get_sub_cmd("counter_mode", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.counter_mode),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("bytebased", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == bool)
+ {
+ entry.meter_unit = FAL_BYTE_BASED;
+ }
+ else
+ {
+ entry.meter_unit = FAL_FRAME_BASED;
+ }
+
+ if (A_TRUE == entry.counter_mode)
+ {
+ *(fal_acl_policer_t *)val = entry;
+ return SW_OK;
+ }
+
+ do
+ {
+ cmd = get_sub_cmd("couple_flag", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.couple_flag),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("color_aware", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.color_mode),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("deficit_flag", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.deficit_en),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cbs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("eir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("ebs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("meter_interval", "1ms");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_policer_timesslot(cmd, &(entry.meter_interval),
+ sizeof (fal_rate_mt_t));
+ if (SW_OK != rv)
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_acl_policer_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_acl_policer(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_acl_policer_t *entry;
+
+ entry = (fal_acl_policer_t *) buf;
+
+ if (A_TRUE == entry->counter_mode)
+ {
+ dprintf("[counter_mode]:yes ");
+ }
+ else
+ {
+ dprintf("[counter_mode]:no ");
+ }
+
+ if (FAL_BYTE_BASED == entry->meter_unit)
+ {
+ dprintf("[meter_unit]:byte_based ");
+ }
+ else
+ {
+ dprintf("[meter_unit]:frame_based ");
+ }
+
+ if (A_TRUE == entry->counter_mode)
+ {
+ dprintf("[counter_lo]:0x%x [counter_hi]", entry->counter_low, entry->counter_high);
+ }
+ else
+ {
+ if (A_TRUE == entry->color_mode)
+ {
+ dprintf("[color_aware]:yes ");
+ }
+ else
+ {
+ dprintf("[color_aware]:no ");
+ }
+
+ if (A_TRUE == entry->couple_flag)
+ {
+ dprintf("[couple_falg]:yes ");
+ }
+ else
+ {
+ dprintf("[couple_falg]:no ");
+ }
+
+ if (A_TRUE == entry->deficit_en)
+ {
+ dprintf("[deficit_falg]:yes ");
+ }
+ else
+ {
+ dprintf("[deficit_falg]:no ");
+ }
+
+ cmd_data_print_policer_timesslot("meter_interval",
+ (a_uint32_t *) & (entry->meter_interval),
+ sizeof (fal_rate_mt_t));
+
+ dprintf("\n[cir]:0x%08x [cbs]:0x%08x [eir]:0x%08x [ebs]:0x%08x",
+ entry->cir, entry->cbs, entry->eir, entry->ebs);
+ }
+
+ return;
+}
+
+sw_error_t
+cmd_data_check_port_policer(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ a_bool_t bool;
+ fal_port_policer_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_port_policer_t));
+
+ do
+ {
+ cmd = get_sub_cmd("combine_enable", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.combine_mode),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("bytebased", "yes");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_TRUE, &bool,
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ if (A_TRUE == bool)
+ {
+ entry.meter_unit = FAL_BYTE_BASED;
+ }
+ else
+ {
+ entry.meter_unit = FAL_FRAME_BASED;
+ }
+
+ do
+ {
+ cmd = get_sub_cmd("couple_flag", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.couple_flag),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("color_aware", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.color_mode),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("deficit_flag", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.deficit_en),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("c_enable", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.c_enable),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("cbs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.cbs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("c_rate_flag", "0xfe");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.c_rate_flag), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("c_meter_interval", "1ms");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_policer_timesslot(cmd, &(entry.c_meter_interval),
+ sizeof (fal_rate_mt_t));
+ if (SW_OK != rv)
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("e_enable", "no");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <yes/no/y/n>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_confirm(cmd, A_FALSE, &(entry.e_enable),
+ sizeof (a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <yes/no/y/n>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("eir", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.eir), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("ebs", "0");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.ebs), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("e_rate_flag", "0xfe");
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: integer\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint32(cmd, &(entry.e_rate_flag), sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ dprintf("usage: integer\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ do
+ {
+ cmd = get_sub_cmd("e_meter_interval", "1ms");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_policer_timesslot(cmd, &(entry.e_meter_interval),
+ sizeof (fal_rate_mt_t));
+ if (SW_OK != rv)
+ dprintf("usage: the format <100us/1ms/10ms/100ms>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ *(fal_port_policer_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_port_policer(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_port_policer_t *entry;
+
+ entry = (fal_port_policer_t *) buf;
+
+ if (A_TRUE == entry->combine_mode)
+ {
+ dprintf("[combine_mode]:yes ");
+ }
+ else
+ {
+ dprintf("[combine_mode]:no ");
+ }
+
+ if (FAL_BYTE_BASED == entry->meter_unit)
+ {
+ dprintf("[meter_unit]:byte_based ");
+ }
+ else
+ {
+ dprintf("[meter_unit]:frame_based ");
+ }
+
+ if (A_TRUE == entry->color_mode)
+ {
+ dprintf("[color_aware]:yes ");
+ }
+ else
+ {
+ dprintf("[color_aware]:no ");
+ }
+
+ if (A_TRUE == entry->couple_flag)
+ {
+ dprintf("[couple_falg]:yes ");
+ }
+ else
+ {
+ dprintf("[couple_falg]:no ");
+ }
+
+ if (A_TRUE == entry->deficit_en)
+ {
+ dprintf("[deficit_falg]:yes ");
+ }
+ else
+ {
+ dprintf("[deficit_falg]:no ");
+ }
+
+ if (A_TRUE == entry->c_enable)
+ {
+ dprintf("\n[c_enable]:yes ");
+ }
+ else
+ {
+ dprintf("\n[c_enable]:no ");
+ }
+
+ dprintf("[cir]:0x%08x [cbs]:0x%08x ", entry->cir,entry->cbs);
+
+
+
+ dprintf("[c_rate_flag]:0x%08x ", entry->c_rate_flag);
+
+ cmd_data_print_policer_timesslot("c_meter_interval",
+ (a_uint32_t *) & (entry->c_meter_interval),
+ sizeof (fal_rate_mt_t));
+
+ if (A_TRUE == entry->e_enable)
+ {
+ dprintf("\n[e_enable]:yes ");
+ }
+ else
+ {
+ dprintf("\n[e_enable]:no ");
+ }
+
+ dprintf("[eir]:0x%08x [ebs]:0x%08x ", entry->eir, entry->ebs);
+
+ dprintf("[e_rate_flag]:0x%08x ", entry->e_rate_flag);
+
+ cmd_data_print_policer_timesslot("e_meter_interval",
+ (a_uint32_t *) & (entry->e_meter_interval),
+ sizeof (fal_rate_mt_t));
+ return;
+}
+
+sw_error_t
+cmd_data_check_mac_mode(char *cmd_str, fal_interface_mac_mode_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmd_str[0])
+ {
+ *arg_val = FAL_MAC_MODE_RGMII;
+ }
+ else if (!strcasecmp(cmd_str, "rgmii"))
+ {
+ *arg_val = FAL_MAC_MODE_RGMII;
+ }
+ else if (!strcasecmp(cmd_str, "rmii"))
+ {
+ *arg_val = FAL_MAC_MODE_RMII;
+ }
+ else if (!strcasecmp(cmd_str, "gmii"))
+ {
+ *arg_val = FAL_MAC_MODE_GMII;
+ }
+ else if (!strcasecmp(cmd_str, "mii"))
+ {
+ *arg_val = FAL_MAC_MODE_MII;
+ }
+ else if (!strcasecmp(cmd_str, "sgmii"))
+ {
+ *arg_val = FAL_MAC_MODE_SGMII;
+ }
+ else if (!strcasecmp(cmd_str, "fiber"))
+ {
+ *arg_val = FAL_MAC_MODE_FIBER;
+ }
+ else if (!strcasecmp(cmd_str, "default"))
+ {
+ *arg_val = FAL_MAC_MODE_DEFAULT;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_clock_mode(char *cmd_str, fal_interface_clock_mode_t * arg_val,
+ a_uint32_t size)
+{
+ if (NULL == cmd_str)
+ {
+ return SW_BAD_VALUE;
+ }
+
+ if (0 == cmd_str[0])
+ {
+ *arg_val = FAL_INTERFACE_CLOCK_MAC_MODE;
+ }
+ if (!strcasecmp(cmd_str, "mac"))
+ {
+ *arg_val = FAL_INTERFACE_CLOCK_MAC_MODE;
+ }
+ else if (!strcasecmp(cmd_str, "phy"))
+ {
+ *arg_val = FAL_INTERFACE_CLOCK_PHY_MODE;
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_mac_config(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ fal_mac_config_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_mac_config_t));
+
+ cmd_data_check_element("mac_mode", "rgmii",
+ "usage: port0 <rgmii/rmii/gmii/mii/sgmii/fiber/default>\nport6 <rgmii/mii/sgmii/fiber/default>\n",
+ cmd_data_check_mac_mode, (cmd, &(entry.mac_mode), 4));
+
+ if (FAL_MAC_MODE_RGMII == entry.mac_mode)
+ {
+ cmd_data_check_element("txclk_delay_cmd", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rgmii.txclk_delay_cmd), 4));
+
+ cmd_data_check_element("txclk_delay_select", "0",
+ "usage: <0-3>\n",
+ cmd_data_check_uint32, (cmd, &(entry.config.rgmii.txclk_delay_sel), 4));
+
+ cmd_data_check_element("rxclk_delay_cmd", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rgmii.rxclk_delay_cmd), 4));
+
+ cmd_data_check_element("rxclk_delay_select", "0",
+ "usage: <0-3>\n",
+ cmd_data_check_uint32, (cmd, &(entry.config.rgmii.rxclk_delay_sel), 4));
+ }
+
+ if (FAL_MAC_MODE_RMII == entry.mac_mode)
+ {
+ cmd_data_check_element("master_mode", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rmii.master_mode), 4));
+
+ cmd_data_check_element("slave_mode", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rmii.slave_mode), 4));
+
+ cmd_data_check_element("clock_inverse", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rmii.clock_inverse), 4));
+ cmd_data_check_element("pipe_rxclk_sel", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.rmii.pipe_rxclk_sel), 4));
+
+ }
+
+ if ((FAL_MAC_MODE_GMII == entry.mac_mode)
+ || (FAL_MAC_MODE_MII == entry.mac_mode))
+ {
+ cmd_data_check_element("clock_mode", "mac",
+ "usage: <phy/mac>\n",
+ cmd_data_check_clock_mode, (cmd, &(entry.config.gmii.clock_mode), 4));
+
+ cmd_data_check_element("txclk_select", "0",
+ "usage: <0-1>\n",
+ cmd_data_check_uint32, (cmd, &(entry.config.gmii.txclk_select), 4));
+
+ cmd_data_check_element("rxclk_select", "0",
+ "usage: <0-1>\n",
+ cmd_data_check_uint32, (cmd, &(entry.config.gmii.rxclk_select), 4));
+ }
+
+ if (FAL_MAC_MODE_SGMII == entry.mac_mode)
+ {
+ cmd_data_check_element("clock_mode", "mac",
+ "usage: <phy/mac>\n",
+ cmd_data_check_clock_mode, (cmd, &(entry.config.sgmii.clock_mode), 4));
+
+ cmd_data_check_element("auto_neg", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.sgmii.auto_neg), 4));
+
+ cmd_data_check_element("force_speed", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.sgmii.force_speed), 4));
+
+ cmd_data_check_element("prbs_enable", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.sgmii.prbs_enable), 4));
+
+ cmd_data_check_element("rem_phy_lpbk", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.sgmii.rem_phy_lpbk), 4));
+ }
+
+ if (FAL_MAC_MODE_FIBER == entry.mac_mode)
+ {
+ cmd_data_check_element("auto_neg", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.fiber.auto_neg), 4));
+
+ cmd_data_check_element("fx100_enable", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.config.fiber.fx100_enable), 4));
+ }
+
+ *(fal_mac_config_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_mac_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_mac_config_t *entry;
+
+ entry = (fal_mac_config_t *) buf;
+
+ if (FAL_MAC_MODE_RGMII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:rgmii");
+ }
+ else if (FAL_MAC_MODE_RMII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:rmii");
+ }
+ else if (FAL_MAC_MODE_GMII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:gmii");
+ }
+ else if (FAL_MAC_MODE_MII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:mii");
+ }
+ else if (FAL_MAC_MODE_SGMII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:sgmii");
+ }
+ else if (FAL_MAC_MODE_FIBER == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:fiber");
+ }
+ else
+ {
+ dprintf("[mac_mode]:default");
+ }
+
+ if (FAL_MAC_MODE_RGMII == entry->mac_mode)
+ {
+ if (A_TRUE == entry->config.rgmii.txclk_delay_cmd)
+ {
+ dprintf("\n[txclk_delay_cmd]:yes [txclk_delay_select]:%d", entry->config.rgmii.txclk_delay_sel);
+ }
+ else
+ {
+ dprintf("\n[txclk_delay_cmd]:no");
+ }
+
+ if (A_TRUE == entry->config.rgmii.rxclk_delay_cmd)
+ {
+ dprintf("\n[rxclk_delay_cmd]:yes [rxclk_delay_select]:%d", entry->config.rgmii.rxclk_delay_sel);
+ }
+ else
+ {
+ dprintf("\n[rxclk_delay_cmd]:no");
+ }
+
+ }
+ else if (FAL_MAC_MODE_RMII == entry->mac_mode)
+ {
+ if (A_TRUE == entry->config.rmii.master_mode)
+ {
+ dprintf("\n[master_mode]:yes");
+ }
+ else
+ {
+ dprintf("\n[master_mode]:no");
+ }
+
+ if (A_TRUE == entry->config.rmii.slave_mode)
+ {
+ dprintf("\n[slave_mode]:yes");
+ }
+ else
+ {
+ dprintf("\n[slave_mode]:no");
+ }
+
+ if (A_TRUE == entry->config.rmii.clock_inverse)
+ {
+ dprintf("\n[clock_inverse]:yes");
+ }
+ else
+ {
+ dprintf("\n[clock_inverse]:no");
+ }
+
+ if (A_TRUE == entry->config.rmii.pipe_rxclk_sel)
+ {
+ dprintf("\n[pipe_rxclk_sel]:yes");
+ }
+ else
+ {
+ dprintf("\n[pipe_rxclk_sel]:no");
+ }
+
+
+ }
+ else if ((FAL_MAC_MODE_GMII == entry->mac_mode)
+ || (FAL_MAC_MODE_MII == entry->mac_mode))
+ {
+
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == entry->config.gmii.clock_mode)
+ {
+ dprintf("\n[clock_mode]:phy [txclk_select]:%d [rxclk_select]:%d", entry->config.gmii.txclk_select, entry->config.gmii.rxclk_select);
+ }
+ else
+ {
+ dprintf("\n[clock_mode]:mac [txclk_select]:%d [rxclk_select]:%d", entry->config.gmii.txclk_select, entry->config.gmii.rxclk_select);
+ }
+ }
+ else if (FAL_MAC_MODE_SGMII == entry->mac_mode)
+ {
+ if (FAL_INTERFACE_CLOCK_PHY_MODE == entry->config.sgmii.clock_mode)
+ {
+ dprintf("\n[clock_mode]:phy");
+ }
+ else
+ {
+ dprintf("\n[clock_mode]:mac");
+ }
+
+ if (A_TRUE == entry->config.sgmii.auto_neg)
+ {
+ dprintf("\n[auto_neg]:yes");
+ }
+ else
+ {
+ dprintf("\n[auto_neg]:no");
+ }
+ if (A_TRUE == entry->config.sgmii.force_speed)
+ {
+ dprintf("\n[force_speed]:yes");
+ }
+ else
+ {
+ dprintf("\n[force_speed]:no");
+ }
+ if (A_TRUE == entry->config.sgmii.prbs_enable)
+ {
+ dprintf("\n[prbs_enable]:yes");
+ }
+ else
+ {
+ dprintf("\n[prbs_enable]:no");
+ }
+ if (A_TRUE == entry->config.sgmii.rem_phy_lpbk)
+ {
+ dprintf("\n[rem_phy_lpbk]:yes");
+ }
+ else
+ {
+ dprintf("\n[rem_phy_lpbk]:no");
+ }
+ }
+ else if (FAL_MAC_MODE_FIBER == entry->mac_mode)
+ {
+ if (A_TRUE == entry->config.fiber.auto_neg)
+ {
+ dprintf("\n[auto_neg]:yes");
+ }
+ else
+ {
+ dprintf("\n[auto_neg]:no");
+ }
+ if (A_TRUE == entry->config.fiber.fx100_enable)
+ {
+ dprintf("\n[fx100_enable]:yes");
+ }
+ else
+ {
+ dprintf("\n[fx100_enable]:no");
+ }
+ }
+
+ return;
+}
+
+sw_error_t
+cmd_data_check_phy_config(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ fal_phy_config_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_phy_config_t));
+
+ cmd_data_check_element("mac_mode", "rgmii",
+ "usage: <rgmii/default>\n",
+ cmd_data_check_mac_mode, (cmd, &(entry.mac_mode), 4));
+
+ if (FAL_MAC_MODE_RGMII == entry.mac_mode)
+ {
+
+ cmd_data_check_element("txclk_delay_cmd", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.txclk_delay_cmd), 4));
+
+ cmd_data_check_element("txclk_delay_select", "0",
+ "usage: <0-3>\n",
+ cmd_data_check_uint32, (cmd, &(entry.txclk_delay_sel), 4));
+
+ cmd_data_check_element("rxclk_delay_cmd", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.rxclk_delay_cmd), 4));
+
+ cmd_data_check_element("rxclk_delay_select", "0",
+ "usage: <0-3>\n",
+ cmd_data_check_uint32, (cmd, &(entry.rxclk_delay_sel), 4));
+ }
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ *(fal_phy_config_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_phy_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_phy_config_t *entry;
+
+ entry = (fal_phy_config_t *) buf;
+
+ if (FAL_MAC_MODE_RGMII == entry->mac_mode)
+ {
+ dprintf("[mac_mode]:rgmii");
+ }
+ else
+ {
+ dprintf("[mac_mode]:default");
+ }
+
+ if (FAL_MAC_MODE_RGMII == entry->mac_mode)
+ {
+ if (A_TRUE == entry->txclk_delay_cmd)
+ {
+ dprintf("\n[txclk_delay_cmd]:yes [txclk_delay_select]:%d", entry->txclk_delay_sel);
+ }
+ else
+ {
+ dprintf("\n[txclk_delay_cmd]:no");
+ }
+
+ if (A_TRUE == entry->rxclk_delay_cmd)
+ {
+ dprintf("\n[rxclk_delay_cmd]:yes [rxclk_delay_select]:%d", entry->rxclk_delay_sel);
+ }
+ else
+ {
+ dprintf("\n[rxclk_delay_cmd]:no");
+ }
+ }
+ return;
+}
+
+sw_error_t
+cmd_data_check_fdb_smode(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "ivl"))
+ *arg_val = INVALID_VLAN_IVL;
+ else if (!strcasecmp(cmd_str, "svl"))
+ *arg_val = INVALID_VLAN_SVL;
+ else
+ {
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+void
+cmd_data_print_fdb_smode(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ dprintf("[%s]:", param_name);
+ if (*(a_uint32_t *) buf == 1)
+ {
+ dprintf("IVL");
+ }
+ else if (*(a_uint32_t *) buf == 0)
+ {
+ dprintf("SVL");
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ }
+}
+
+sw_error_t
+cmd_data_check_fx100_link_mode(char* cmd_str, fx100_ctrl_link_mode_t* arg_val)
+{
+ if (0 == cmd_str[0])
+ {
+ *arg_val = Fx100BASE_MODE;
+ }
+ else if (!strcasecmp(cmd_str, "fx100base"))
+ {
+ *arg_val = Fx100BASE_MODE;
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_fx100_fd_mode(char *cmd_str, a_uint32_t * arg_val)
+{
+ if (0 == cmd_str[0])
+ {
+ *arg_val = FX100_FULL_DUPLEX;
+ }
+ else if (!strcasecmp(cmd_str, "fullduplex"))
+ {
+ *arg_val = FX100_FULL_DUPLEX;
+ }
+ else if (!strcasecmp(cmd_str, "halfduplex"))
+ {
+ *arg_val = FX100_HALF_DUPLEX;
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sgmii_fiber_mode(char *cmd_str, a_uint32_t * arg_val)
+{
+ if (0 == cmd_str[0])
+ {
+ *arg_val = FX100_SERDS_MODE;
+ }
+ else if (!strcasecmp(cmd_str, "fx100serds"))
+ {
+ *arg_val = FX100_SERDS_MODE;
+ }
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+ return SW_OK;
+}
+
+
+
+sw_error_t
+cmd_data_check_fx100_config(char *cmd_str, void * val, a_uint32_t size)
+{
+ char *cmd;
+ fal_fx100_ctrl_config_t entry;
+
+ aos_mem_zero(&entry, sizeof (fal_fx100_ctrl_config_t));
+
+ cmd_data_check_element("link_mode", "fx100base",
+ "usage: <fx100base>\n",
+ cmd_data_check_fx100_link_mode, (cmd, &(entry.link_mode)));
+
+ cmd_data_check_element("overshoot", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.overshoot), 4));
+
+ cmd_data_check_element("loopback_mode", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.loopback), 4));
+
+ cmd_data_check_element("fd_mode", "fullduplex",
+ "usage: <fullduplex/halfduplex>\n",
+ cmd_data_check_fx100_fd_mode, (cmd, &(entry.fd_mode)));
+
+ cmd_data_check_element("col_test", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.col_test), 4));
+
+ cmd_data_check_element("sgmii_fiber", "fx100serds",
+ "usage: <fx100serds>\n",
+ cmd_data_check_sgmii_fiber_mode, (cmd, &(entry.sgmii_fiber_mode)));
+
+ cmd_data_check_element("crs_ctrl", "yes",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_TRUE, &(entry.crs_ctrl), 4));
+
+ cmd_data_check_element("loopback_ctrl", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.loopback_ctrl), 4));
+
+ cmd_data_check_element("crs_col_100_ctrl", "yes",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_TRUE, &(entry.crs_col_100_ctrl), 4));
+
+ cmd_data_check_element("loop_en", "no",
+ "usage: <yes/no/y/n>\n",
+ cmd_data_check_confirm, (cmd, A_FALSE, &(entry.loop_en), 4));
+
+
+
+ *(fal_fx100_ctrl_config_t *)val = entry;
+ return SW_OK;
+}
+
+void
+cmd_data_print_fx100_config(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_fx100_ctrl_config_t* entry;
+
+ entry = (fal_fx100_ctrl_config_t*)buf;
+
+ if (Fx100BASE_MODE == entry->link_mode)
+ {
+ dprintf("[link_mode]: fx100base\n");
+ }
+
+ if (A_TRUE == entry->overshoot)
+ {
+ dprintf("[overshoot]: yes\n");
+ }
+ else
+ {
+ dprintf("[overshoot]: no\n");
+ }
+
+ if (A_TRUE == entry->loopback)
+ {
+ dprintf("[loopback_mode]: yes\n");
+ }
+ else
+ {
+ dprintf("[loopback_mode]: no\n");
+ }
+
+ if (FX100_FULL_DUPLEX == entry->fd_mode)
+ {
+ dprintf("[fd_mode]: fullduplex\n");
+ }
+ else
+ {
+ dprintf("[fd_mode]: halfduplex\n");
+ }
+
+ if (A_TRUE == entry->col_test)
+ {
+ dprintf("[col_test]: yes\n");
+ }
+ else
+ {
+ dprintf("[col_test]: no\n");
+ }
+
+ if (FX100_SERDS_MODE == entry->sgmii_fiber_mode)
+ {
+ dprintf("[sgmii_fiber]: fx100_serds\n");
+ }
+
+ if (A_TRUE == entry->crs_ctrl)
+ {
+ dprintf("[crs_ctrl]: yes\n");
+ }
+ else
+ {
+ dprintf("[crs_ctrl]: no\n");
+ }
+
+ if (A_TRUE == entry->loopback_ctrl)
+ {
+ dprintf("[loopback_ctrl]: yes\n");
+ }
+ else
+ {
+ dprintf("[loopback_ctrl]: no\n");
+ }
+
+ if (A_TRUE == entry->crs_col_100_ctrl)
+ {
+ dprintf("[crs_col_100_ctrl]: yes\n");
+ }
+ else
+ {
+ dprintf("[crs_col_100_ctrl]: no\n");
+ }
+
+ if (A_TRUE == entry->loop_en)
+ {
+ dprintf("[loop_en]: yes\n");
+ }
+ else
+ {
+ dprintf("[loop_en]: no\n");
+ }
+
+}
+
+sw_error_t
+cmd_data_check_sec_mac(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "resv_vid"))
+ *arg_val = FAL_NORM_MAC_RESV_VID_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_src_addr"))
+ *arg_val = FAL_NORM_MAC_INVALID_SRC_ADDR_CMD;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_ip(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "invalid_ver"))
+ *arg_val = FAL_NORM_IP_INVALID_VER_CMD;
+ else if (!strcasecmp(cmd_str, "same_addr"))
+ *arg_val = FAL_NROM_IP_SAME_ADDR_CMD;
+ else if (!strcasecmp(cmd_str, "ttl_change_status"))
+ *arg_val = FAL_NROM_IP_TTL_CHANGE_STATUS;
+ else if (!strcasecmp(cmd_str, "ttl_val"))
+ *arg_val = FAL_NROM_IP_TTL_VALUE;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_ip4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "invalid_hl"))
+ *arg_val = FAL_NROM_IP4_INVALID_HL_CMD;
+ else if (!strcasecmp(cmd_str, "hdr_opts"))
+ *arg_val = FAL_NROM_IP4_HDR_OPTIONS_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_df"))
+ *arg_val = FAL_NROM_IP4_INVALID_DF_CMD;
+ else if (!strcasecmp(cmd_str, "frag_offset_min_len"))
+ *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MIN_LEN_CMD;
+ else if (!strcasecmp(cmd_str, "frag_offset_min_size"))
+ *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MIN_SIZE;
+ else if (!strcasecmp(cmd_str, "frag_offset_max_len"))
+ *arg_val = FAL_NROM_IP4_FRAG_OFFSET_MAX_LEN_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_frag_offset"))
+ *arg_val = FAL_NROM_IP4_INVALID_FRAG_OFFSET_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_sip"))
+ *arg_val = FAL_NROM_IP4_INVALID_SIP_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_dip"))
+ *arg_val = FAL_NROM_IP4_INVALID_DIP_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_chksum"))
+ *arg_val = FAL_NROM_IP4_INVALID_CHKSUM_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_pl"))
+ *arg_val = FAL_NROM_IP4_INVALID_PL_CMD;
+ else if (!strcasecmp(cmd_str, "df_clear_status"))
+ *arg_val = FAL_NROM_IP4_DF_CLEAR_STATUS;
+ else if (!strcasecmp(cmd_str, "ipid_random_status"))
+ *arg_val = FAL_NROM_IP4_IPID_RANDOM_STATUS;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_ip6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "invalid_dip"))
+ *arg_val = FAL_NROM_IP6_INVALID_DIP_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_sip"))
+ *arg_val = FAL_NROM_IP6_INVALID_SIP_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_pl"))
+ *arg_val = FAL_NROM_IP6_INVALID_PL_CMD;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_tcp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "blat"))
+ *arg_val = FAL_NROM_TCP_BLAT_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_hl"))
+ *arg_val = FAL_NROM_TCP_INVALID_HL_CMD;
+ else if (!strcasecmp(cmd_str, "min_hdr_size"))
+ *arg_val = FAL_NROM_TCP_MIN_HDR_SIZE;
+ else if (!strcasecmp(cmd_str, "invalid_syn"))
+ *arg_val = FAL_NROM_TCP_INVALID_SYN_CMD;
+ else if (!strcasecmp(cmd_str, "su_block"))
+ *arg_val = FAL_NROM_TCP_SU_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "sp_block"))
+ *arg_val = FAL_NROM_TCP_SP_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "sap_block"))
+ *arg_val = FAL_NROM_TCP_SAP_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "xmas_scan"))
+ *arg_val = FAL_NROM_TCP_XMAS_SCAN_CMD;
+ else if (!strcasecmp(cmd_str, "null_scan"))
+ *arg_val = FAL_NROM_TCP_NULL_SCAN_CMD;
+ else if (!strcasecmp(cmd_str, "sr_block"))
+ *arg_val = FAL_NROM_TCP_SR_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "sf_block"))
+ *arg_val = FAL_NROM_TCP_SF_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "sar_block"))
+ *arg_val = FAL_NROM_TCP_SAR_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "rst_scan"))
+ *arg_val = FAL_NROM_TCP_RST_SCAN_CMD;
+ else if (!strcasecmp(cmd_str, "rst_with_data"))
+ *arg_val = FAL_NROM_TCP_RST_WITH_DATA_CMD;
+ else if (!strcasecmp(cmd_str, "fa_block"))
+ *arg_val = FAL_NROM_TCP_FA_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "pa_block"))
+ *arg_val = FAL_NROM_TCP_PA_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "ua_block"))
+ *arg_val = FAL_NROM_TCP_UA_BLOCK_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_chksum"))
+ *arg_val = FAL_NROM_TCP_INVALID_CHKSUM_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_urgptr"))
+ *arg_val = FAL_NROM_TCP_INVALID_URGPTR_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_opts"))
+ *arg_val = FAL_NROM_TCP_INVALID_OPTIONS_CMD;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_data_check_sec_udp(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "blat"))
+ *arg_val = FAL_NROM_UDP_BLAT_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_len"))
+ *arg_val = FAL_NROM_UDP_INVALID_LEN_CMD;
+ else if (!strcasecmp(cmd_str, "invalid_chksum"))
+ *arg_val = FAL_NROM_UDP_INVALID_CHKSUM_CMD;
+ else
+ {
+ dprintf("UNKNOWN VALUE");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_icmp4(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "ping_pl_exceed"))
+ *arg_val = FAL_NROM_ICMP4_PING_PL_EXCEED_CMD;
+ else if (!strcasecmp(cmd_str, "ping_frag"))
+ *arg_val = FAL_NROM_ICMP4_PING_FRAG_CMD;
+ else if (!strcasecmp(cmd_str, "ping_max_pl"))
+ *arg_val = FAL_NROM_ICMP4_PING_MAX_PL_VALUE;
+ else
+ {
+ //dprintf("input error");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_sec_icmp6(char *cmd_str, a_uint32_t * arg_val, a_uint32_t size)
+{
+ if (cmd_str == NULL)
+ return SW_BAD_PARAM;
+
+ if (!strcasecmp(cmd_str, "ping_pl_exceed"))
+ *arg_val = FAL_NROM_ICMP6_PING_PL_EXCEED_CMD;
+ else if (!strcasecmp(cmd_str, "ping_frag"))
+ *arg_val = FAL_NROM_ICMP6_PING_FRAG_CMD;
+ else if (!strcasecmp(cmd_str, "ping_max_pl"))
+ *arg_val = FAL_NROM_ICMP6_PING_MAX_PL_VALUE;
+ else
+ {
+ //dprintf("input error");
+ return SW_BAD_VALUE;
+ }
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_data_check_remark_entry(char *info, void *val, a_uint32_t size)
+{
+ char *cmd;
+ sw_error_t rv;
+ fal_egress_remark_table_t *pEntry = (fal_egress_remark_table_t *)val;
+ a_uint32_t tmp;
+
+ memset(pEntry, 0, sizeof(fal_egress_remark_table_t));
+
+ /* get remark_dscp */
+ do
+ {
+ cmd = get_sub_cmd("remark dscp", "enable");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <enable/disable>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_enable(cmd, &(pEntry->remark_dscp), sizeof(a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <enable/disable>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ /* get remark_up */
+ do
+ {
+ cmd = get_sub_cmd("remark up", "enable");
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: <enable/disable>\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_enable(cmd, &(pEntry->remark_up), sizeof(a_bool_t));
+ if (SW_OK != rv)
+ dprintf("usage: <enable/disable>\n");
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+
+ /* get g_dscp */
+ do
+ {
+ cmd = get_sub_cmd("green dscp", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ }
+
+ if (tmp > 63)
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_OUT_OF_RANGE;
+ }
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ pEntry->g_dscp = tmp;
+
+ /* get y_dscp */
+ do
+ {
+ cmd = get_sub_cmd("yellow dscp", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ }
+
+ if (tmp > 63)
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_OUT_OF_RANGE;
+ }
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ pEntry->y_dscp = tmp;
+
+ /* get g_up */
+ do
+ {
+ cmd = get_sub_cmd("green up", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ dprintf("usage: the range is 0 -- 7\n");
+ }
+
+ if (tmp > 63)
+ {
+ dprintf("usage: the range is 0 -- 7\n");
+ rv = SW_OUT_OF_RANGE;
+ }
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ pEntry->g_up = tmp;
+
+ /* get y_up */
+ do
+ {
+ cmd = get_sub_cmd("yellow up", NULL);
+ SW_RTN_ON_NULL_PARAM(cmd);
+
+ if (!strncasecmp(cmd, "quit", 4))
+ {
+ return SW_BAD_VALUE;
+ }
+ else if (!strncasecmp(cmd, "help", 4))
+ {
+ dprintf("usage: the range is 0 -- 63\n");
+ rv = SW_BAD_VALUE;
+ }
+ else
+ {
+ rv = cmd_data_check_uint16(cmd, &tmp, sizeof (a_uint32_t));
+ if (SW_OK != rv)
+ {
+ dprintf("usage: the range is 0 -- 7\n");
+ }
+
+ if (tmp > 63)
+ {
+ dprintf("usage: the range is 0 -- 7\n");
+ rv = SW_OUT_OF_RANGE;
+ }
+ }
+ }
+ while (talk_mode && (SW_OK != rv));
+ pEntry->y_up = tmp;
+
+/*
+ dprintf("remark_dscp=%d, remark_up=%d, g_dscp=%d, y_dscp=%d\n",
+ pEntry->remark_dscp,
+ pEntry->remark_up,
+ pEntry->g_dscp,
+ pEntry->y_dscp);
+
+ *(fal_egress_remark_table_t *) val = entry;
+*/
+ return SW_OK;
+}
+
+void
+cmd_data_print_remark_entry(a_uint8_t * param_name, a_uint32_t * buf, a_uint32_t size)
+{
+ fal_egress_remark_table_t *entry;
+
+ entry = (fal_egress_remark_table_t *) buf;
+ dprintf("\n");
+ dprintf("[remark dscp]:%s\n", entry->remark_dscp?"enabled":"disabled");
+ dprintf("[remark up]:%s\n", entry->remark_up?"enabled":"disabled");
+ dprintf("[green dscp]:%d\n", entry->g_dscp);
+ dprintf("[yellow dscp]:%d\n", entry->y_dscp);
+ dprintf("[green up]:%d\n", entry->g_up);
+ dprintf("[yellow up]:%d\n", entry->y_up);
+
+ return;
+}
+
+
diff --git a/src/shell/shell_lib.c b/src/shell/shell_lib.c
new file mode 100644
index 0000000..0c216d1
--- /dev/null
+++ b/src/shell/shell_lib.c
@@ -0,0 +1,875 @@
+#include <stdio.h>
+#include <signal.h>
+#include <termios.h>
+#include "shell_config.h"
+
+#define printc(isPrint, fmt, args...) if(isPrint == 1) printf(fmt, ##args)
+
+static char *cmd_promptp = "dev0@atheros>"; /*command prompt pointer */
+static struct termios term_save; /* terminal setting saved */
+static int term_cursor; /*terminal position */
+static int cmd_cursor; /*command position */
+static char *cmd_strp; /*command string pointer */
+static int cmd_strlen; /*command string length */
+
+#define HISTORY_MAX_SIZE 20
+static char *history_buf[HISTORY_MAX_SIZE + 1]; /* history buffer */
+static int history_nr; /* saved history lines */
+static int history_cur; /* current pointer to history line */
+
+static void term_config(void);
+static void term_restore(void);
+static void term_sig_handler(int sig);
+static void term_init(char *out_cmd);
+static void term_echo(void);
+static void cursor_backward(void);
+static void cursor_forward(void);
+static void handle_backward(void);
+static void handle_delete(void);
+static void handle_tab(void);
+static void handle_up(void);
+static void handle_down(void);
+static void handle_left(void);
+static void handle_right(void);
+static void handle_normal(char *out_cmd, char c);
+static void handle_help(void);
+static void prompt_print(void);
+static void out_cmd_print(void);
+static int history_prev(void);
+static int history_next(void);
+static void history_record(char *out_cmd);
+
+
+struct key_bind_t
+{
+ int is_eseq; /*is escape sequence */
+ int key_last; /*relative key or escape sequence last character */
+ void (*func) ();
+};
+
+struct key_bind_t key_bind[] =
+{
+ {0, '\b', handle_backward},
+ {0, 127, handle_delete},
+ {0, '\t', handle_tab},
+ {0, '?', handle_help},
+ {1, 'A', handle_up},
+ {1, 'B', handle_down},
+ {1, 'C', handle_right},
+ {1, 'D', handle_left},
+};
+
+/* saving orignal setting and set new attrib to terminal*/
+static void
+term_config(void)
+{
+ struct termios term_tmp;
+ tcgetattr(0, (void *) &term_save);
+ memcpy(&term_tmp, &term_save, sizeof (struct termios));
+
+ /*unbuffered input and turn off echo */
+ term_tmp.c_lflag &= ~(ICANON | ECHO | ECHONL);
+
+ tcsetattr(0, TCSANOW, (void *) &term_tmp);
+}
+
+/*restore termial setting*/
+static void
+term_restore(void)
+{
+ tcsetattr(0, TCSANOW, (void *) &term_save);
+}
+
+/*termial signal handler*/
+static void
+term_sig_handler(int sig)
+{
+ switch (sig)
+ {
+ case SIGINT:
+ if (cmd_promptp)
+ printf("\n%s", cmd_promptp);
+
+ while (cmd_strlen-- > 0)
+ cmd_strp[cmd_strlen] = '\0';
+
+ cmd_strp[0] = '\0';
+ cmd_strlen = 0;
+ term_cursor = strlen(cmd_promptp);
+ cmd_cursor = 0;
+
+ fflush(stdout);
+
+ break;
+
+ case SIGUSR1:
+ case SIGKILL:
+ case SIGABRT:
+ case SIGTERM:
+ case SIGHUP:
+ printf("exit.\n");
+ term_restore();
+ exit(0);
+ default:
+ break;
+ }
+}
+
+/*termial initial*/
+static void
+term_init(char *out_cmd)
+{
+ term_cursor = 0;
+ cmd_cursor = 0;
+
+ cmd_strp = out_cmd;
+ cmd_strlen = strlen(out_cmd);
+
+ // Initialize signal
+ signal(SIGINT, term_sig_handler);
+ signal(SIGUSR1, term_sig_handler);
+ signal(SIGKILL, term_sig_handler);
+ signal(SIGABRT, term_sig_handler);
+ signal(SIGTERM, term_sig_handler);
+ signal(SIGHUP, term_sig_handler);
+ //signal(SIGQUIT, SIG_IGN);
+
+ prompt_print();
+}
+
+/* printf current char*/
+static void
+term_echo(void)
+{
+
+ if (cmd_strp[cmd_cursor])
+ {
+ putchar(cmd_strp[cmd_cursor]);
+ }
+ else
+ {
+ putchar(' ');
+ }
+
+ term_cursor++;
+ cmd_cursor++;
+}
+
+/* cursor move back one character */
+static void
+cursor_backward(void)
+{
+ if (cmd_cursor > 0 && term_cursor > 0)
+ {
+ cmd_cursor--;
+ term_cursor--;
+ putchar('\b');
+ }
+}
+
+/* cursor move forward one character */
+static void
+cursor_forward(void)
+{
+ if (cmd_cursor < cmd_strlen)
+ term_echo();
+}
+
+/* move backward one characters. */
+static void
+handle_backward(void)
+{
+ if (cmd_cursor > 0)
+ {
+ cursor_backward();
+ handle_delete();
+ }
+}
+
+/*delete one character in front of cursor */
+static void
+handle_delete(void)
+{
+ int cur_tmp = cmd_cursor;
+
+ /*when cursour at the end of string */
+ if (cmd_cursor >= cmd_strlen)
+ return;
+
+ /*delete one character from string */
+ strcpy(cmd_strp + cur_tmp, cmd_strp + cur_tmp + 1);
+ cmd_strlen--;
+
+ /*clear characters after cursor */
+ printf("\033[J");
+
+ /*re-print from delete position */
+ while (cmd_cursor < cmd_strlen)
+ term_echo();
+
+ /*move cursor back to delete position */
+ cur_tmp = cmd_cursor - cur_tmp;
+ while (cur_tmp--)
+ cursor_backward();
+}
+
+/* deal with up arrow*/
+static void
+handle_up(void)
+{
+ /*get previous history */
+ if (history_prev() < 0)
+ return;
+
+ /*copy current history cmd to out_cmd */
+ strcpy(cmd_strp, history_buf[history_cur]);
+
+ /*print out_cmd */
+ out_cmd_print();
+}
+
+/* deal with down arrow*/
+static void
+handle_down(void)
+{
+ /*get previous history */
+ if (history_next() < 0)
+ return;
+
+ /*copy current history cmd to out_cmd */
+ strcpy(cmd_strp, history_buf[history_cur]);
+
+ /*print out_cmd */
+ out_cmd_print();
+}
+
+/* deal with left arrow*/
+static void
+handle_left(void)
+{
+ cursor_backward();
+}
+
+/* deal with right arrow*/
+static void
+handle_right(void)
+{
+ cursor_forward();
+}
+
+static void
+print_cmd_all (void)
+{
+ int cmd_no = 0;
+ for (cmd_no = 0; GCMD_DESC_VALID(cmd_no); cmd_no++)
+ {
+ if (!GCMD_NAME(cmd_no))
+ continue;
+
+ printf("%-10s%s\n", GCMD_NAME(cmd_no), GCMD_MEMO(cmd_no));
+ }
+}
+
+
+static void
+print_sub_all (int cmd_id)
+{
+ int cmd_sub_no = 0, cmd_sub_nr = 0;
+ for (cmd_sub_no = 0; GCMD_SUB_DESC_VALID(cmd_id, cmd_sub_no); cmd_sub_no++)
+ {
+
+ if (!GCMD_SUB_NAME(cmd_id, cmd_sub_no))
+ continue;
+ if(cmd_sub_no == 0 || strcasecmp(GCMD_SUB_NAME(cmd_id, cmd_sub_no),
+ GCMD_SUB_NAME(cmd_id, cmd_sub_no-1)))
+ {
+ printf("%-10s\t", GCMD_SUB_NAME(cmd_id, cmd_sub_no));
+ if(cmd_sub_nr && !((cmd_sub_nr+1) %5))
+ {
+ printf("\n");
+ }
+ cmd_sub_nr++;
+ }
+ }
+ printf("\n");
+}
+
+/*
+1. partly_cmd_nr = 0 && index = no match: none
+2. partly_cmd_nr = 0 && index = matched: full matched
+3. partly_cmd_nr = 1 && index = matched: partly matched & to be completed
+4. partly_cmd_nr > 1 && index = matched: partly matched & to be list them
+*/
+#define NONE_MATCHED(pmatch_nr, pmatch_id) ( (pmatch_nr == 0) && (pmatch_id == GCMD_DESC_NO_MATCH) )
+#define FULL_MATCHED(pmatch_nr, pmatch_id) ( (pmatch_nr == 0) && (pmatch_id != GCMD_DESC_NO_MATCH) )
+#define ONE_PART_MATCHED(pmatch_nr, pmatch_id) ( (pmatch_nr == 1) && (pmatch_id != GCMD_DESC_NO_MATCH) )
+#define MULTI_PART_MATCHED(pmatch_nr, pmatch_id) ( (pmatch_nr > 1 ) && (pmatch_id != GCMD_DESC_NO_MATCH) )
+
+
+static int
+search_cmd_type(char *name, int *pmatch_id, int is_print)
+{
+ int cmd_no = 0, pmatch_nr = 0;
+
+ *pmatch_id = GCMD_DESC_NO_MATCH;
+
+ /*search type in glb_num_types print matched */
+ for (cmd_no = 0; GCMD_DESC_VALID(cmd_no); cmd_no++)
+ {
+
+ if (!GCMD_NAME(cmd_no))
+ continue;
+
+ if (!strcasecmp(name, GCMD_NAME(cmd_no)))
+ {
+ /*full matched */
+ *pmatch_id = cmd_no;
+ break;
+ }
+ else if (!strncasecmp(name, GCMD_NAME(cmd_no), strlen(name)))
+ {
+ /*partly matched */
+ printc(is_print, "%-10s%s\n", GCMD_NAME(cmd_no), GCMD_MEMO(cmd_no));
+ pmatch_nr++;
+ *pmatch_id = cmd_no;
+ }
+ }
+
+ return pmatch_nr;
+}
+
+static int
+search_cmd_sub(int cmd_id, int *pmatch_sub_id, char *sub_name, int is_print)
+{
+
+ int cmd_sub_no, pmatch_sub_nr = 0, fmatch_sub_save = GCMD_DESC_NO_MATCH;
+
+ *pmatch_sub_id = GCMD_DESC_NO_MATCH;
+
+ /*search for full matched */
+ for (cmd_sub_no = 0; GCMD_SUB_DESC_VALID(cmd_id, cmd_sub_no); cmd_sub_no++)
+ {
+ if (!GCMD_SUB_NAME(cmd_id, cmd_sub_no))
+ continue;
+
+ if (!strcasecmp(sub_name, GCMD_SUB_NAME(cmd_id, cmd_sub_no)))
+ {
+ /*full matched */
+ printc(is_print, "%-10s\t%s\n", GCMD_SUB_ACT(cmd_id, cmd_sub_no), GCMD_SUB_MEMO(cmd_id, cmd_sub_no));
+ //*pmatch_sub_id = cmd_sub_no;
+ if(fmatch_sub_save == GCMD_DESC_NO_MATCH)
+ {
+ *pmatch_sub_id = fmatch_sub_save = cmd_sub_no;
+ }
+
+ }
+ else if (!strncasecmp(sub_name, GCMD_SUB_NAME(cmd_id, cmd_sub_no), strlen(sub_name)))
+ {
+ if(fmatch_sub_save != GCMD_DESC_NO_MATCH)
+ continue;
+
+ /*partly matched */
+ if (*pmatch_sub_id == GCMD_DESC_NO_MATCH || (GCMD_SUB_NAME(cmd_id, cmd_sub_no-1) &&
+ strcasecmp(GCMD_SUB_NAME(cmd_id, cmd_sub_no), GCMD_SUB_NAME(cmd_id, cmd_sub_no-1))))
+ {
+ printc(is_print, "%-10s\t", GCMD_SUB_NAME(cmd_id, cmd_sub_no));
+ pmatch_sub_nr++;
+ *pmatch_sub_id = cmd_sub_no;
+ }
+ }
+ }
+
+ if (pmatch_sub_nr > 1)
+ printc(is_print, "\n");
+
+ return pmatch_sub_nr;
+}
+
+static int
+search_cmd_action(int cmd_id, int *pmatch_act_id, char *sub_name, char *action, int is_print)
+{
+ int cmd_act_no = 0, pmatch_act_nr = 0;
+
+ *pmatch_act_id = GCMD_DESC_NO_MATCH;
+
+ /*search for full matched */
+ for (cmd_act_no = 0; GCMD_SUB_DESC_VALID(cmd_id, cmd_act_no); cmd_act_no++)
+ {
+
+ if (strcasecmp(sub_name, GCMD_SUB_NAME(cmd_id, cmd_act_no)))
+ continue;
+
+ if (!GCMD_SUB_ACT(cmd_id, cmd_act_no))
+ continue;
+
+ if (!strcasecmp(action, GCMD_SUB_ACT(cmd_id, cmd_act_no)))
+ {
+ /*full matched */
+ if (*pmatch_act_id == GCMD_DESC_NO_MATCH)
+ {
+ printc(is_print, "%-10s\n", GCMD_SUB_USAGE(cmd_id, cmd_act_no));
+ }
+
+ *pmatch_act_id = cmd_act_no;
+ break;
+ }
+ else if (!strncasecmp(action, GCMD_SUB_ACT(cmd_id, cmd_act_no), strlen(action)))
+ {
+ /*partly matched */
+ if (*pmatch_act_id == GCMD_DESC_NO_MATCH ||( GCMD_SUB_ACT(cmd_id, cmd_act_no-1) &&
+ strcasecmp(GCMD_SUB_ACT(cmd_id, cmd_act_no), GCMD_SUB_ACT(cmd_id, cmd_act_no-1))))
+ {
+ printc(is_print, "%-10s\t%s\n", GCMD_SUB_ACT(cmd_id, cmd_act_no), GCMD_SUB_MEMO(cmd_id, cmd_act_no));
+ pmatch_act_nr++;
+ *pmatch_act_id = cmd_act_no;
+ }
+ }
+ }
+
+ return pmatch_act_nr;
+}
+
+/*print help info*/
+static void
+handle_help(void)
+{
+ int pmatch_id = GCMD_DESC_NO_MATCH, pmatch_sub_id = GCMD_DESC_NO_MATCH, pmatch_act_id = GCMD_DESC_NO_MATCH;
+ int cmd_nr = 0, pmatch_nr = 0, pmatch_sub_nr = 0;
+ char *tmp_str[3], *cmd_strp_cp = strdup(cmd_strp);
+
+ /* split command string into temp array */
+ tmp_str[cmd_nr] = (void *) strtok(cmd_strp_cp, " ");
+
+ while (tmp_str[cmd_nr])
+ {
+ if (++cmd_nr == 3)
+ break;
+ tmp_str[cmd_nr] = (void *) strtok(NULL, " ");
+ }
+
+ /*echo input ? */
+ printf("?\n");
+
+ int is_print = 0;
+
+ /* print matched command */
+ switch (cmd_nr)
+ {
+ case 3:
+ pmatch_nr = search_cmd_type(tmp_str[0], &pmatch_id, is_print);
+ if(FULL_MATCHED(pmatch_nr, pmatch_id))
+ pmatch_sub_nr = search_cmd_sub(pmatch_id, &pmatch_sub_id, tmp_str[1], is_print);
+
+ if(FULL_MATCHED(pmatch_sub_nr, pmatch_sub_id))
+ {
+ is_print = 1;
+ search_cmd_action(pmatch_id, &pmatch_act_id, tmp_str[1], tmp_str[2], is_print);
+ }
+ break;
+
+ case 2:
+ pmatch_nr = search_cmd_type(tmp_str[0], &pmatch_id, is_print);
+ if(FULL_MATCHED(pmatch_nr, pmatch_id))
+ {
+ is_print = 1;
+ search_cmd_sub(pmatch_id, &pmatch_sub_id, tmp_str[1], is_print);
+ }
+ break;
+
+ case 1:
+ is_print = 1;
+ pmatch_nr = search_cmd_type(tmp_str[0], &pmatch_id, is_print);
+
+ if(NONE_MATCHED(pmatch_nr, pmatch_id))
+ {
+ print_cmd_all();
+ }
+ else if(FULL_MATCHED(pmatch_nr, pmatch_id))
+ {
+ print_sub_all(pmatch_id);
+ }
+ break;
+
+ case 0:
+ print_cmd_all();
+ break;
+
+ default:
+ break;
+ }
+
+ printf("\n");
+
+ /* re-print prompt */
+ prompt_print();
+
+ /* re-print from cursor */
+ while (cmd_cursor < cmd_strlen)
+ term_echo();
+
+ if(cmd_strp_cp)
+ free(cmd_strp_cp);
+}
+
+static void
+_cmd_complete(char *matchBuf, char *fullName)
+{
+ //printf ("***%s-%s****", matchBuf, fullName);
+ int offset = cmd_strlen - cmd_cursor;
+ int diff = strlen(fullName) - strlen(matchBuf);;
+
+ /*print prompt */
+ if (cmd_promptp)
+ printf("\n%s", cmd_promptp);
+
+ /*give position to new char */
+ memmove(cmd_strp + cmd_cursor + diff, cmd_strp + cmd_cursor, offset);
+ /*insert new char */
+ memcpy(cmd_strp + cmd_cursor, fullName + strlen(matchBuf), diff);
+ /*caculate new cursor */
+ cmd_cursor += diff;
+
+ /*set new cursor and len */
+ cmd_strlen = strlen(cmd_strp);
+ term_cursor = cmd_strlen + strlen(cmd_promptp);
+
+ /*re-print command */
+ printf("%s", cmd_strp);
+
+ /*set terminal cursor */
+ if (cmd_strlen - cmd_cursor)
+ printf("\033[%dD", cmd_strlen - cmd_cursor); /*move cursor left */
+}
+
+void _cursor_recover(void)
+{
+ if(strlen(cmd_strp) != cmd_cursor)
+ {
+ int clear = strlen(cmd_strp) - cmd_cursor;
+ while(clear--)
+ {
+ printf("\b");
+ }
+ }
+}
+
+/* deal with tab completion*/
+#define MATCH_BUF_MAX 100
+static void
+handle_tab(void)
+{
+
+ int cmd_nr = 0;
+ char matchBuf[MATCH_BUF_MAX];
+ char *tmp_str[3];
+
+ memset(matchBuf, 0, MATCH_BUF_MAX);
+ strncpy(matchBuf, cmd_strp, cmd_cursor);
+
+ printf("\n");
+
+ /* split command string into temp array */
+ tmp_str[cmd_nr] = (void *) strtok(matchBuf, " ");
+
+ if(!tmp_str[cmd_nr])
+ {
+ print_cmd_all();
+ if (cmd_promptp)
+ printf("\n%s%s", cmd_promptp, cmd_strp);
+ _cursor_recover();
+ return;
+ }
+
+ while (tmp_str[cmd_nr])
+ {
+ if (++cmd_nr == 3)
+ break;
+ tmp_str[cmd_nr] = (void *) strtok(NULL, " ");
+ }
+
+ int is_print = 1, is_completed = 0;
+ int pmatch_nr = 0, pmatch_id = GCMD_DESC_NO_MATCH;
+
+ pmatch_nr = search_cmd_type(tmp_str[0], &pmatch_id, is_print);
+
+ if (cmd_nr == 1)
+ {
+ if (ONE_PART_MATCHED(pmatch_nr, pmatch_id))
+ {
+ _cmd_complete(tmp_str[0], GCMD_NAME(pmatch_id));
+ is_completed = 1;
+ }
+
+ if(NONE_MATCHED(pmatch_nr, pmatch_id))
+ {
+ print_cmd_all();
+
+ }
+ else if(FULL_MATCHED(pmatch_nr, pmatch_id))
+ {
+ print_sub_all(pmatch_id);
+ }
+
+ }
+ else if (cmd_nr > 1)
+ {
+ if (FULL_MATCHED(pmatch_nr, pmatch_id))
+ {
+
+ int pmatch_sub_nr = 0, pmatch_sub_id = GCMD_DESC_NO_MATCH;
+
+ if(cmd_nr == 3) is_print = 0;
+ pmatch_sub_nr = search_cmd_sub(pmatch_id, &pmatch_sub_id, tmp_str[1], is_print);
+
+ if(cmd_nr == 2)
+ {
+ if (ONE_PART_MATCHED(pmatch_sub_nr, pmatch_sub_id))
+ {
+ _cmd_complete(tmp_str[1], GCMD_SUB_NAME(pmatch_id, pmatch_sub_id));
+ is_completed = 1;
+ }
+
+ }
+ else if (cmd_nr == 3)
+ {
+ int pmatch_act_nr = 0, pmatch_act_id = GCMD_DESC_NO_MATCH;
+ pmatch_act_nr = search_cmd_action(pmatch_id, &pmatch_act_id, tmp_str[1], tmp_str[2], is_print);
+
+ if (ONE_PART_MATCHED(pmatch_act_nr, pmatch_act_id))
+ {
+ _cmd_complete(tmp_str[2], GCMD_SUB_ACT(pmatch_id, pmatch_act_id));
+ is_completed = 1;
+
+ }
+ else if (FULL_MATCHED(pmatch_act_nr, pmatch_act_id))
+ {
+ is_print = 1;
+ printc(is_print, "%-10s\n", GCMD_SUB_USAGE(pmatch_id, pmatch_act_id));
+ }
+ }
+ }
+ }
+
+ if (is_completed == 0)
+ {
+ /*re-echo */
+ if (cmd_promptp)
+ printf("\n%s%s", cmd_promptp, cmd_strp);
+ _cursor_recover();
+ }
+ //_cursor_recover();
+}
+
+/*deal with normal character*/
+static void
+handle_normal(char *out_cmd, char c)
+{
+ int tmp_cursor = cmd_cursor;
+
+ /*buffer full */
+ if (++cmd_strlen > (MATCH_BUF_MAX - 2))
+ return;
+
+ /*append operation */
+ if (cmd_cursor == (cmd_strlen - 1))
+ {
+ *(out_cmd + cmd_cursor) = c;
+ *(out_cmd + cmd_cursor + 1) = 0;
+ term_echo();
+ }
+ else
+ {
+ /* Insert operation */
+ /*give position to new char */
+ memmove(out_cmd + tmp_cursor + 1, out_cmd + tmp_cursor,
+ cmd_strlen - tmp_cursor);
+ *(out_cmd + tmp_cursor) = c;
+
+ /* re-print from cursor */
+ while (cmd_cursor < cmd_strlen)
+ term_echo();
+
+ /* restore curor to insert position */
+ tmp_cursor = cmd_cursor - tmp_cursor - 1;
+ while (tmp_cursor--)
+ cursor_backward();
+ }
+}
+
+/*print prompt info*/
+static void
+prompt_print(void)
+{
+ if (cmd_promptp)
+ printf("%s", cmd_promptp);
+
+ term_cursor = strlen(cmd_promptp);
+ cmd_cursor = 0;
+ fflush(stdout);
+}
+
+/*print current output command*/
+static void
+out_cmd_print(void)
+{
+ cmd_strlen = strlen(history_buf[history_cur]);
+
+ putchar('\r');
+ prompt_print();
+
+ while (cmd_cursor < cmd_strlen)
+ term_echo();
+
+ /*clear characters after cursor */
+ printf("\033[J");
+
+}
+
+/* get previous history command*/
+static int
+history_prev(void)
+{
+ if (history_cur > 0)
+ {
+ /*record current*/
+ if (cmd_strp[0] != 0 || history_buf[history_cur] == 0)
+ {
+ if(history_buf[history_cur])
+ free(history_buf[history_cur]);
+ history_buf[history_cur] = strdup(cmd_strp);
+ }
+ history_cur--;
+ return 0;
+ }
+
+ return -1;
+}
+
+/* get next history command*/
+static int
+history_next(void)
+{
+ if ((history_cur >= 0) && (history_cur < history_nr))
+ {
+ history_cur++;
+ return 0;
+ }
+
+ return -1;
+}
+
+/*record history command*/
+static void
+history_record(char *out_cmd)
+{
+ int i;
+
+ /* cleanup may be saved current command line */
+ if (cmd_strlen > 0) /* no put empty line */
+ {
+ i = history_nr;
+
+ free(history_buf[HISTORY_MAX_SIZE]);
+ history_buf[HISTORY_MAX_SIZE] = 0;
+ /* After max history, remove the oldest command */
+ if (i >= HISTORY_MAX_SIZE)
+ {
+ free(history_buf[0]);
+ for (i = 0; i < (HISTORY_MAX_SIZE - 1); i++)
+ history_buf[i] = history_buf[i + 1];
+ }
+ history_buf[i++] = strdup(out_cmd);
+ history_cur = i;
+ history_nr = i;
+ }
+}
+
+int
+_isspace(int ch)
+{
+ return (unsigned int) (ch - 9) < 5u || ch == ' ';
+}
+
+/*call by main*/
+int
+next_cmd(char *out_cmd)
+{
+ unsigned char c = 0;
+ int key_no = 0;
+ int seq_char = 0;
+ int str_valid = 0;
+
+ /*set terminal new attrib */
+ term_config();
+
+ /*termial initial */
+ term_init(out_cmd);
+
+ /*main loop */
+ while ((c = getc(stdin)) != '\n')
+ {
+ key_no = 0;
+ seq_char = 0;
+
+ if (!_isspace(c))
+ {
+ str_valid = 1;
+ }
+
+ if (c == 27) /*escape sequence */
+ {
+ if ((c = getc(stdin)) == '[' || c == 'O')
+ {
+ c = getc(stdin);
+ seq_char = 1;
+ }
+ }
+
+ /*search for bind key handle function */
+ while (key_no < sizeof (key_bind) / sizeof (key_bind[0]))
+ {
+ if ((seq_char == key_bind[key_no].is_eseq)
+ && (c == key_bind[key_no].key_last))
+ {
+ key_bind[key_no].func();
+ break;
+ }
+ key_no++;
+ }
+
+ if (key_no == sizeof (key_bind) / sizeof (key_bind[0]))
+ handle_normal(out_cmd, c);
+
+ }
+
+ /*handle enter when at the end of a line */
+ if (term_cursor)
+ putchar('\n');
+
+ /* record command history without '\n' */
+ history_record(out_cmd);
+#if 0
+ /* add '\n' to out_cmd */
+ if (str_valid)
+ {
+ out_cmd[cmd_strlen++] = '\n';
+ }
+ else
+ {
+ cmd_strlen = 0;
+ out_cmd[cmd_strlen++] = '\n';
+ }
+
+ if (cmd_strlen > 1 && out_cmd[cmd_strlen - 1] == '\n')
+ out_cmd[cmd_strlen - 1] = 0;
+#else
+ if (!str_valid)
+ cmd_strlen = 0;
+#endif
+ /*retore terminal to orginal status */
+ term_restore();
+
+ fflush(stdout);
+
+ return cmd_strlen;
+}
diff --git a/src/shell/shell_sw.c b/src/shell/shell_sw.c
new file mode 100644
index 0000000..d7be6ba
--- /dev/null
+++ b/src/shell/shell_sw.c
@@ -0,0 +1,491 @@
+#include <stdio.h>
+#include "shell.h"
+#include "fal.h"
+
+static int sw_devid = 0;
+
+sw_error_t
+cmd_set_devid(a_uint32_t *arg_val)
+{
+ if (arg_val[1] >= SW_MAX_NR_DEV)
+ {
+ dprintf("dev_id should be less than <%d>\n", SW_MAX_NR_DEV);
+ return SW_FAIL;
+ }
+ sw_devid = arg_val[1];
+
+ return SW_OK;
+}
+
+int
+get_devid(void)
+{
+ return sw_devid;
+}
+
+
+#if defined ISIS
+
+sw_error_t
+cmd_show_fdb(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_fdb_op_t *fdb_op = (fal_fdb_op_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+ fal_fdb_entry_t *fdb_entry = (fal_fdb_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4 + sizeof(fal_fdb_op_t) / 4);
+
+ aos_mem_zero(fdb_op, sizeof (fal_fdb_op_t));
+ aos_mem_zero(fdb_entry, sizeof (fal_fdb_entry_t));
+ arg_val[0] = SW_API_FDB_EXTEND_FIRST;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = (a_uint32_t) fdb_op;
+ arg_val[4] = (a_uint32_t) fdb_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ arg_val[0] = SW_API_FDB_EXTEND_NEXT;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+#elif defined ISISC
+
+sw_error_t
+cmd_show_fdb(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_fdb_op_t *fdb_op = (fal_fdb_op_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+ fal_fdb_entry_t *fdb_entry = (fal_fdb_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4 + sizeof(fal_fdb_op_t) / 4);
+
+ aos_mem_zero(fdb_op, sizeof (fal_fdb_op_t));
+ aos_mem_zero(fdb_entry, sizeof (fal_fdb_entry_t));
+ arg_val[0] = SW_API_FDB_EXTEND_FIRST;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = (a_uint32_t) fdb_op;
+ arg_val[4] = (a_uint32_t) fdb_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ arg_val[0] = SW_API_FDB_EXTEND_NEXT;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+#elif defined SHIVA
+
+sw_error_t
+cmd_show_fdb(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_fdb_entry_t *fdb_entry = (fal_fdb_entry_t *) (ioctl_buf + 2);
+
+ memset(fdb_entry, 0, sizeof (fal_fdb_entry_t));
+ arg_val[0] = SW_API_FDB_ITERATE;
+ *(ioctl_buf + 1) = 0;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = (a_uint32_t) (ioctl_buf + 1);
+ arg_val[4] = (a_uint32_t) fdb_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+#else
+
+sw_error_t
+cmd_show_fdb(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t rtn_size = 1, cnt = 0;
+ fal_fdb_entry_t *fdb_entry = (fal_fdb_entry_t *) (ioctl_buf + rtn_size);
+
+ memset(fdb_entry, 0, sizeof (fal_fdb_entry_t));
+ arg_val[0] = SW_API_FDB_FIRST;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = (a_uint32_t) fdb_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ arg_val[0] = SW_API_FDB_NEXT;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+#endif
+
+#if defined ISIS
+
+sw_error_t
+cmd_show_vlan(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t rtn_size = 1 ,tmp_vid = FAL_NEXT_ENTRY_FIRST_ID, cnt = 0;
+ fal_vlan_t *vlan_entry = (fal_vlan_t *) (ioctl_buf + rtn_size);
+
+ while (1)
+ {
+ arg_val[0] = SW_API_VLAN_NEXT;
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = tmp_vid;
+ arg_val[4] = (a_uint32_t) vlan_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+
+ tmp_vid = vlan_entry->vid;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+#elif defined ISISC
+
+sw_error_t
+cmd_show_vlan(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t rtn_size = 1 ,tmp_vid = FAL_NEXT_ENTRY_FIRST_ID, cnt = 0;
+ fal_vlan_t *vlan_entry = (fal_vlan_t *) (ioctl_buf + rtn_size);
+
+ while (1)
+ {
+ arg_val[0] = SW_API_VLAN_NEXT;
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = tmp_vid;
+ arg_val[4] = (a_uint32_t) vlan_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+
+ tmp_vid = vlan_entry->vid;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+
+#else
+
+sw_error_t
+cmd_show_vlan(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t rtn_size = 1 ,tmp_vid = 0, cnt = 0;
+ fal_vlan_t *vlan_entry = (fal_vlan_t *) (ioctl_buf + rtn_size);
+
+ while (1)
+ {
+ arg_val[0] = SW_API_VLAN_NEXT;
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = tmp_vid;
+ arg_val[4] = (a_uint32_t) vlan_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+
+ tmp_vid = vlan_entry->vid;
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+#endif
+
+
+sw_error_t
+cmd_show_resv_fdb(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ a_uint32_t *iterator = ioctl_buf + 1;
+ fal_fdb_entry_t *entry = (fal_fdb_entry_t *) (ioctl_buf + 2);
+
+ *iterator = 0;
+ while (1)
+ {
+ arg_val[0] = SW_API_FDB_RESV_ITERATE;
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = (a_uint32_t) iterator;
+ arg_val[4] = (a_uint32_t) entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ dprintf("\n");
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_show_host(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_host_entry_t *host_entry = (fal_host_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+
+ aos_mem_zero(host_entry, sizeof (fal_host_entry_t));
+ host_entry->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ arg_val[0] = SW_API_IP_HOST_NEXT;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = 0;
+ arg_val[4] = (a_uint32_t) host_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_show_intfmac(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_intf_mac_entry_t *intfmac_entry = (fal_intf_mac_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+
+ aos_mem_zero(intfmac_entry, sizeof (fal_intf_mac_entry_t));
+ intfmac_entry->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ arg_val[0] = SW_API_IP_INTF_ENTRY_NEXT;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = 0;
+ arg_val[4] = (a_uint32_t) intfmac_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+sw_error_t
+cmd_show_pubaddr(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_nat_pub_addr_t *pubaddr_entry = (fal_nat_pub_addr_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+
+ aos_mem_zero(pubaddr_entry, sizeof (fal_nat_pub_addr_t));
+ pubaddr_entry->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ arg_val[0] = SW_API_PUB_ADDR_ENTRY_NEXT;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = 0;
+ arg_val[4] = (a_uint32_t) pubaddr_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_show_nat(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_nat_entry_t *nat_entry = (fal_nat_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+
+ aos_mem_zero(nat_entry, sizeof (fal_nat_entry_t));
+ nat_entry->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ arg_val[0] = SW_API_NAT_NEXT;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = 0;
+ arg_val[4] = (a_uint32_t) nat_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+
+sw_error_t
+cmd_show_napt(a_uint32_t *arg_val)
+{
+ sw_error_t rtn;
+ a_uint32_t cnt = 0;
+ fal_napt_entry_t *napt_entry = (fal_napt_entry_t *) (ioctl_buf + sizeof(sw_error_t) / 4);
+
+ aos_mem_zero(napt_entry, sizeof (fal_napt_entry_t));
+ napt_entry->entry_id = FAL_NEXT_ENTRY_FIRST_ID;
+ arg_val[0] = SW_API_NAPT_NEXT;
+
+ while (1)
+ {
+ arg_val[1] = (a_uint32_t) ioctl_buf;
+ arg_val[2] = get_devid();
+ arg_val[3] = 0;
+ arg_val[4] = (a_uint32_t) napt_entry;
+
+ rtn = cmd_exec_api(arg_val);
+ if ((SW_OK != rtn) || (SW_OK != (sw_error_t) (*ioctl_buf)))
+ {
+ break;
+ }
+ cnt++;
+ }
+
+ if((rtn != SW_OK) && (rtn != SW_NO_MORE))
+ cmd_print_error(rtn);
+ else
+ dprintf("\ntotal %d entries\n", cnt);
+
+ return SW_OK;
+}
+
+
diff --git a/src/util/Makefile b/src/util/Makefile
new file mode 100644
index 0000000..f909cbb
--- /dev/null
+++ b/src/util/Makefile
@@ -0,0 +1,12 @@
+LOC_DIR=src/util
+LIB=UTIL
+
+include $(PRJ_PATH)/make/config.mk
+
+SRC_LIST=$(wildcard *.c)
+
+include $(PRJ_PATH)/make/components.mk
+include $(PRJ_PATH)/make/defs.mk
+include $(PRJ_PATH)/make/target.mk
+
+all: dep obj
diff --git a/src/util/util.c b/src/util/util.c
new file mode 100644
index 0000000..86ba10f
--- /dev/null
+++ b/src/util/util.c
@@ -0,0 +1,476 @@
+/*
+ * Copyright (c) 2012 Qualcomm Atheros, Inc.
+ * All rights reserved.
+ * Qualcomm Atheros Confidential and Proprietary.
+ *
+ */
+
+#include "sw.h"
+#include "util.h"
+
+
+static sll_node_t *
+sll_nd_new(sll_head_t * sll)
+{
+ sll_node_t *new_nd;
+
+ if (LL_FIX_NDNR & sll->flag)
+ {
+ if (NULL == sll->free_nd)
+ {
+ new_nd = NULL;
+ }
+ else
+ {
+ new_nd = sll->free_nd;
+ sll->free_nd = sll->free_nd->next;
+ }
+ }
+ else
+ {
+ new_nd = aos_mem_alloc(sizeof (sll_node_t));
+ }
+
+ if (NULL != new_nd)
+ {
+ aos_mem_zero(new_nd, sizeof (sll_node_t));
+ }
+
+ return new_nd;
+}
+
+static void
+sll_nd_free(sll_head_t * sll, sll_node_t * nd)
+{
+ if (LL_FIX_NDNR & sll->flag)
+ {
+ nd->next = sll->free_nd;
+ sll->free_nd = nd;
+ }
+ else
+ {
+ aos_mem_free(nd);
+ }
+ return;
+}
+
+//#define SLL_DENUG
+#ifdef SLL_DENUG
+static void
+sll_nd_dump(sll_head_t * sll, const char * info)
+{
+ sll_node_t * curr;
+
+ if (NULL == sll->nd_dump)
+ {
+ return;
+ }
+
+ aos_printk("\n%s node number = %d\n", info, sll->nd_nr);
+ curr = sll->fst_nd;
+ while (NULL != curr)
+ {
+ sll->nd_dump(curr->data);
+ curr = curr->next;
+ }
+}
+#else
+#define sll_nd_dump(sll, info)
+#endif
+
+sll_head_t *
+sll_creat(ll_nd_cmp cmp_func, ll_nd_dump dump_func, a_uint32_t flag, a_uint32_t nd_nr)
+{
+ sll_head_t *head;
+ sll_node_t *node;
+ a_uint32_t i, size;
+
+ if (flag & LL_FIX_NDNR)
+ {
+ size = sizeof (sll_head_t) + sizeof (sll_node_t) * nd_nr;
+ }
+ else
+ {
+ size = sizeof (sll_head_t);
+ }
+
+ head = aos_mem_alloc(size);
+ if (NULL == head)
+ {
+ return NULL;
+ }
+ aos_mem_zero(head, size);
+
+ head->fst_nd = NULL;
+ head->nd_nr = 0;
+ head->flag = flag;
+ head->nd_cmp = cmp_func;
+ head->nd_dump = dump_func;
+ head->free_nd = NULL;
+
+ if (flag & LL_FIX_NDNR)
+ {
+ node = (sll_node_t *) ((a_uint8_t *) head + sizeof (sll_head_t));
+ for (i = 0; i < nd_nr; i++)
+ {
+ node[i].next = head->free_nd;
+ head->free_nd = &(node[i]);
+ }
+ }
+
+ return head;
+}
+
+void
+sll_destroy(sll_head_t * sll)
+{
+ aos_mem_free(sll);
+ return;
+}
+
+void
+sll_lock(sll_head_t * sll)
+{
+ return;
+}
+
+void
+sll_unlock(sll_head_t * sll)
+{
+ return;
+}
+
+void *
+sll_nd_find(const sll_head_t * sll, void *data, a_uint32_t * iterator)
+{
+ sll_node_t *node;
+ ll_cmp_rslt_t rslt;
+
+ node = sll->fst_nd;
+ while (NULL != node)
+ {
+ rslt = sll->nd_cmp(node->data, data);
+ if (LL_CMP_EQUAL == rslt)
+ {
+ *iterator = (a_uint32_t) node;
+ return node->data;
+ }
+
+ if ((LL_CMP_GREATER == rslt) && (sll->flag & LL_IN_ORDER))
+ {
+ return NULL;
+ }
+ node = node->next;
+ }
+
+ return NULL;
+}
+
+void *
+sll_nd_next(const sll_head_t * sll, a_uint32_t * iterator)
+{
+ sll_node_t *curr = NULL;
+
+ if (0 == *iterator)
+ {
+ if (NULL != sll->fst_nd)
+ {
+ curr = sll->fst_nd;
+ }
+ }
+ else
+ {
+ curr = ((sll_node_t *)(*iterator))->next;
+ }
+
+ if (NULL == curr)
+ {
+ return NULL;
+ }
+ else
+ {
+ *iterator = (a_uint32_t) curr;
+ return curr->data;
+ }
+}
+
+sw_error_t
+sll_nd_insert(sll_head_t * sll, void *data)
+{
+ sll_node_t *node = NULL;
+ sll_node_t *curr = NULL;
+ sll_node_t *prev;
+ ll_cmp_rslt_t rslt;
+
+ sll_nd_dump(sll, "sll_nd_insert before insert");
+
+ node = sll_nd_new(sll);
+ if (NULL == node)
+ {
+ return SW_NO_RESOURCE;
+ }
+ node->data = data;
+
+ if ((NULL == sll->fst_nd)
+ || (0 == (sll->flag & LL_IN_ORDER)))
+ {
+ node->next = sll->fst_nd;
+ sll->fst_nd = node;
+ sll->nd_nr++;
+ sll_nd_dump(sll, "sll_nd_insert after insert");
+ return SW_OK;
+ }
+
+ curr = sll->fst_nd;
+ prev = NULL;
+ while (NULL != curr)
+ {
+ rslt = sll->nd_cmp(curr->data, data);
+
+ if (LL_CMP_EQUAL == rslt)
+ {
+ return SW_ALREADY_EXIST;
+ }
+
+ if (LL_CMP_GREATER == rslt)
+ {
+ break;
+ }
+ prev = curr;
+ curr = curr->next;
+ }
+
+ if (NULL == prev)
+ {
+ node->next = sll->fst_nd;
+ sll->fst_nd = node;
+ }
+ else
+ {
+ prev->next = node;
+ node->next = curr;
+ }
+ sll->nd_nr++;
+
+ sll_nd_dump(sll, "sll_nd_insert after insert");
+ return SW_OK;
+}
+
+sw_error_t
+sll_nd_delete(sll_head_t * sll, void *data)
+{
+ sll_node_t *curr;
+ sll_node_t *prev = NULL;
+ ll_cmp_rslt_t rslt;
+
+ sll_nd_dump(sll, "sll_nd_delete before delete");
+
+ curr = sll->fst_nd;
+ while (NULL != curr)
+ {
+ rslt = sll->nd_cmp(curr->data, data);
+ if (LL_CMP_EQUAL == rslt)
+ {
+ if (NULL != prev)
+ {
+ prev->next = curr->next;
+ }
+ else
+ {
+ sll->fst_nd = curr->next;
+ }
+ sll->nd_nr--;
+ sll_nd_free(sll, curr);
+
+ sll_nd_dump(sll, "sll_nd_delete after delete");
+ return SW_OK;
+ }
+
+ if ((LL_CMP_GREATER == rslt) && (sll->flag & LL_IN_ORDER))
+ {
+ return SW_NOT_FOUND;
+ }
+
+ prev = curr;
+ curr = curr->next;
+ }
+
+ return SW_NOT_FOUND;
+}
+
+
+#define ID_SIZE_U8 0x1
+#define ID_SIZE_U16 0x2
+#define ID_SIZE_U32 0x4
+
+#define ID_NR_IN_U8 256
+#define ID_NR_IN_U16 65536
+
+sid_pool_t *
+sid_pool_creat(a_uint32_t id_nr, a_uint32_t min_id)
+{
+ sid_pool_t * pool;
+ a_uint32_t size;
+ a_uint32_t id_size;
+ a_uint32_t i;
+
+ if (0 == id_nr)
+ {
+ return NULL;
+ }
+
+ pool = aos_mem_alloc(sizeof(sid_pool_t));
+ if (NULL == pool)
+ {
+ return NULL;
+ }
+ aos_mem_zero(pool, sizeof(sid_pool_t));
+
+ pool->id_min = min_id;
+ pool->id_nr = id_nr;
+ pool->id_ptr = 0;
+
+ if (ID_NR_IN_U8 >= id_nr)
+ {
+ size = ((id_nr + 3) >> 2) << 2;
+ id_size = ID_SIZE_U8;
+ }
+ else if (ID_NR_IN_U16 >= id_nr)
+ {
+ size = ((id_nr + 1) >> 1) << 2;
+ id_size = ID_SIZE_U16;
+ }
+ else
+ {
+ size = id_nr << 2;
+ id_size = ID_SIZE_U32;
+ }
+ pool->id_size = id_size;
+
+ pool->id_pool = aos_mem_alloc(size);
+ if (NULL == pool->id_pool)
+ {
+ aos_mem_free(pool);
+ return NULL;
+ }
+ aos_mem_zero(pool->id_pool, size);
+
+ if (ID_SIZE_U8 == id_size)
+ {
+ a_uint8_t *p_id;
+
+ p_id = pool->id_pool;
+ for (i = 0; i < id_nr; i++)
+ {
+ p_id[i] = i;
+ }
+ }
+ else if (ID_SIZE_U16 == id_size)
+ {
+ a_uint16_t *p_id;
+
+ p_id = pool->id_pool;
+ for (i = 0; i < id_nr; i++)
+ {
+ p_id[i] = i;
+ }
+ }
+ else
+ {
+ a_uint32_t *p_id;
+
+ p_id = pool->id_pool;
+ for (i = 0; i < id_nr; i++)
+ {
+ p_id[i] = i;
+ }
+ }
+
+ return pool;
+}
+
+void
+sid_pool_destroy(sid_pool_t * pool)
+{
+ aos_mem_free(pool->id_pool);
+ aos_mem_free(pool);
+ return;
+}
+
+sw_error_t
+sid_pool_id_alloc(sid_pool_t * pool, a_uint32_t * id)
+{
+ if (pool->id_nr <= pool->id_ptr)
+ {
+ return SW_NO_RESOURCE;
+ }
+
+ if (ID_SIZE_U8 == pool->id_size)
+ {
+ a_uint8_t *p_id;
+
+ p_id = pool->id_pool;
+ *id = p_id[pool->id_ptr] + pool->id_min;
+ }
+ else if (ID_SIZE_U16 == pool->id_size)
+ {
+ a_uint16_t *p_id;
+
+ p_id = pool->id_pool;
+ *id = p_id[pool->id_ptr] + pool->id_min;
+ }
+ else
+ {
+ a_uint32_t *p_id;
+
+ p_id = pool->id_pool;
+ *id = p_id[pool->id_ptr] + pool->id_min;
+ }
+
+ pool->id_ptr++;
+ return SW_OK;
+}
+
+sw_error_t
+sid_pool_id_free(sid_pool_t * pool, a_uint32_t id)
+{
+ if (0 == pool->id_ptr)
+ {
+ return SW_FAIL;
+ }
+
+ pool->id_ptr--;
+ if (ID_SIZE_U8 == pool->id_size)
+ {
+ a_uint8_t *p_id;
+
+ if (ID_NR_IN_U8 < (id - id - pool->id_min))
+ {
+ return SW_FAIL;
+ }
+
+ p_id = pool->id_pool;
+ p_id[pool->id_ptr] = id - pool->id_min;
+ }
+ else if (ID_SIZE_U16 == pool->id_size)
+ {
+ a_uint16_t *p_id;
+
+ if (ID_NR_IN_U16 < (id - id - pool->id_min))
+ {
+ return SW_FAIL;
+ }
+
+ p_id = pool->id_pool;
+ p_id[pool->id_ptr] = id - pool->id_min;
+ }
+ else
+ {
+ a_uint32_t *p_id;
+
+ p_id = pool->id_pool;
+ p_id[pool->id_ptr] = id - pool->id_min;
+ }
+
+ return SW_OK;
+}