[qca-ssdk] support cypress uniphy0 new interface mode
Change-Id: I4c02de4a7cfdab140670b84d20bf6d6b0c66a7a8
Signed-off-by: esong <song@codeaurora.org>
diff --git a/include/adpt/cppe/adpt_cppe_portctrl.h b/include/adpt/cppe/adpt_cppe_portctrl.h
index 905c5b3..081b4e9 100755
--- a/include/adpt/cppe/adpt_cppe_portctrl.h
+++ b/include/adpt/cppe/adpt_cppe_portctrl.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -24,14 +24,19 @@
extern "C" {
#endif /* __cplusplus */
-#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0
-#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 1
-#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0
-#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 1
-#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0
-#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 1
-#define CPPE_PORT5_GMAC_SEL_GMAC 0
-#define CPPE_PORT5_GMAC_SEL_XGMAC 1
+#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2 0x0
+#define CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4 0x1
+#define CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3 0x0
+#define CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS 0x1
+#define CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4 0x0
+#define CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0 0x1
+#define CPPE_PORT5_GMAC_SEL_GMAC 0x0
+#define CPPE_PORT5_GMAC_SEL_XGMAC 0x1
+#define CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK 0x0
+#define CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK 0x1
+#define CPPE_PCS0_CHANNEL0_SEL_PSGMII 0x0
+#define CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS 0x1
+#define CPPE_DETECTION_PHY_FAILURE 0xFFFF
sw_error_t
_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
@@ -48,6 +53,9 @@
sw_error_t
adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
fal_mtu_ctrl_t *ctrl);
+sw_error_t
+adpt_cppe_port_to_channel_convert(a_uint32_t dev_id,
+ a_uint32_t port_id, a_uint32_t *channel_id);
#ifdef __cplusplus
}
diff --git a/include/adpt/cppe/adpt_cppe_uniphy.h b/include/adpt/cppe/adpt_cppe_uniphy.h
new file mode 100755
index 0000000..9eee37b
--- /dev/null
+++ b/include/adpt/cppe/adpt_cppe_uniphy.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#ifndef _ADPT_CPPE_UNIPHYH_
+#define _ADPT_CPPE_UNIPHYH_
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+sw_error_t
+__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id);
+sw_error_t
+__adpt_cppe_uniphy_connection_qca8072_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index);
+sw_error_t
+__adpt_cppe_uniphy_connection_qca808x_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index);
+sw_error_t
+__adpt_cppe_uniphy_sgmiiplus_mode_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index);
+void
+__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+ a_bool_t enable);
+sw_error_t
+__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index);
+void
+__adpt_hppe_gcc_uniphy_software_reset(a_uint32_t dev_id,
+ a_uint32_t uniphy_index);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif
diff --git a/include/hsl/hppe/hppe_global_reg.h b/include/hsl/hppe/hppe_global_reg.h
index 5a1785d..904f4f1 100755
--- a/include/hsl/hppe/hppe_global_reg.h
+++ b/include/hsl/hppe/hppe_global_reg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -144,7 +144,9 @@
a_uint32_t port4_pcs_sel:2;
a_uint32_t port5_pcs_sel:2;
a_uint32_t port5_gmac_sel:1;
- a_uint32_t _reserved0:25;
+ a_uint32_t pcs0_ch4_sel:1;
+ a_uint32_t pcs0_ch0_sel:1;
+ a_uint32_t _reserved0:23;
};
union cppe_port_mux_ctrl_u {
diff --git a/include/hsl/hppe/hppe_init.h b/include/hsl/hppe/hppe_init.h
index b2adacf..6698d63 100755
--- a/include/hsl/hppe/hppe_init.h
+++ b/include/hsl/hppe/hppe_init.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -46,13 +46,32 @@
#define HPPE_UNIPHY_BASE1 0x10000
#define HPPE_UNIPHY_BASE2 0x20000
#define HPPE_UNIPHY_MAX_DIRECT_ACCESS_REG 0x7fff
-#define HPPE_UNIPHY_INDIRECT_REG_ADDR 0x83fc
+#define HPPE_UNIPHY_INDIRECT_REG_ADDR 0x83fc
#define HPPE_UNIPHY_INDIRECT_HIGH_ADDR 0x1fff00
-#define HPPE_UNIPHY_INDIRECT_LOW_ADDR 0xff
-#define HPPE_UNIPHY_INDIRECT_DATA 0x20
-#define UNIPHY_CALIBRATION_DONE 0x1
-#define UNIPHY_10GR_LINKUP 0x1
-#define UNIPHY_10GR_LINK_LOSS 0x7
+#define HPPE_UNIPHY_INDIRECT_LOW_ADDR 0xff
+#define HPPE_UNIPHY_INDIRECT_DATA 0x20
+#define UNIPHY_CALIBRATION_DONE 0x1
+#define UNIPHY_10GR_LINKUP 0x1
+#define UNIPHY_10GR_LINK_LOSS 0x7
+#define UNIPHY_ATHEROS_NEGOTIATION 0x0
+#define UNIPHY_STANDARD_NEGOTIATION 0x1
+#define UNIPHY_CH0_QSGMII_SGMII_MODE 0x0
+#define UNIPHY_CH0_PSGMII_MODE 0x1
+#define UNIPHY_CH0_SGMII_MODE 0x0
+#define UNIPHY_CH0_QSGMII_MODE 0x1
+#define UNIPHY_SGMII_MODE_ENABLE 0x1
+#define UNIPHY_SGMII_MODE_DISABLE 0x0
+#define UNIPHY_SGMIIPLUS_MODE_ENABLE 0x1
+#define UNIPHY_SGMIIPLUS_MODE_DISABLE 0x0
+#define UNIPHY_XPCS_MODE_ENABLE 0x1
+#define UNIPHY_XPCS_MODE_DISABLE 0x0
+#define UNIPHY_PHY_SGMII_MODE 0x3
+#define UNIPHY_PHY_SGMIIPLUS_MODE 0x5
+#define UNIPHY_SGMII_CHANNEL1_DISABLE 0x0
+#define UNIPHY_SGMII_CHANNEL1_ENABLE 0x1
+#define UNIPHY_SGMII_CHANNEL4_DISABLE 0x0
+#define UNIPHY_SGMII_CHANNEL4_ENABLE 0x1
+
#define SGMII_1000M_SOURCE1_CLOCK1 0x101
#define SGMII_100M_SOURCE1_CLOCK1 0x109
diff --git a/include/hsl/hppe/hppe_uniphy.h b/include/hsl/hppe/hppe_uniphy.h
index e7980b9..66e0739 100755
--- a/include/hsl/hppe/hppe_uniphy.h
+++ b/include/hsl/hppe/hppe_uniphy.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -20,30 +20,32 @@
#ifndef _HPPE_UNIPHY_H_
#define _HPPE_UNIPHY_H_
-#define UNIPHY_OFFSET_CALIB_4_MAX_ENTRY 3
-#define UNIPHY_MODE_CTRL_MAX_ENTRY 3
-#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY 3
-#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY 3
-#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY 3
-#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY 3
-#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY 3
-#define SR_XS_PCS_KR_STS1_MAX_ENTRY 3
-#define VR_XS_PCS_DIG_CTRL1_MAX_ENTRY 3
-#define SR_MII_CTRL_MAX_ENTRY 3
-#define VR_MII_AN_CTRL_MAX_ENTRY 3
-#define VR_MII_AN_INTR_STS_MAX_ENTRY 3
+#define UNIPHY_OFFSET_CALIB_4_MAX_ENTRY 3
+#define UNIPHY_MODE_CTRL_MAX_ENTRY 3
+#define UNIPHY_CHANNEL0_INPUT_OUTPUT_4_MAX_ENTRY 3
+#define UNIPHY_CHANNEL1_INPUT_OUTPUT_4_MAX_ENTRY 3
+#define UNIPHY_CHANNEL2_INPUT_OUTPUT_4_MAX_ENTRY 3
+#define UNIPHY_CHANNEL3_INPUT_OUTPUT_4_MAX_ENTRY 3
+#define UNIPHY_CHANNEL4_INPUT_OUTPUT_4_MAX_ENTRY 3
+#define SR_XS_PCS_KR_STS1_MAX_ENTRY 3
+#define VR_XS_PCS_DIG_CTRL1_MAX_ENTRY 3
+#define SR_MII_CTRL_MAX_ENTRY 3
+#define VR_MII_AN_CTRL_MAX_ENTRY 3
+#define VR_MII_AN_INTR_STS_MAX_ENTRY 3
-#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY 3
-#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY 3
-#define UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY 3
-#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 3
-#define UNIPHY_RX_AFE_2_MAX_ENTRY 3
-#define BANDGAP_IP_MBIAS_2_MAX_ENTRY 4
-#define LDO_0P9V_RELATED_1_MAX_ENTRY 4
-#define OTP_VTT_LDO_RELATED_MAX_ENTRY 4
-#define OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY 4
-#define PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 4
-#define PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY 4
+#define UNIPHY_PLL_CONTROL_VCO_RELATED_SELECTION_MAX_ENTRY 3
+#define UNIPHY_TX_AC_JTAG_MUX_DRIVER_SELECTION_MAX_ENTRY 3
+#define UNIPHY_RESISTOR_CALIBRATION_1_MAX_ENTRY 3
+#define UNIPHY_PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 3
+#define UNIPHY_RX_AFE_2_MAX_ENTRY 3
+#define BANDGAP_IP_MBIAS_2_MAX_ENTRY 4
+#define LDO_0P9V_RELATED_1_MAX_ENTRY 4
+#define OTP_VTT_LDO_RELATED_MAX_ENTRY 4
+#define OTP_TEMPERATURE_COMPENSATE_1_MAX_ENTRY 4
+#define PLL_VCO_RELATED_CONTROL_1_MAX_ENTRY 4
+#define PLL_CONTROL_VCO_RELATED_SELECTION_2_MAX_ENTRY 4
+#define UNIPHY_MISC2_PHY_MODE_MAX_ENTRY 4
+#define UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY 4
sw_error_t
hppe_uniphy_offset_calib_4_get(
@@ -359,13 +361,13 @@
a_uint32_t value);
sw_error_t
-hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_athr_csco_mode_25m_get(
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value);
sw_error_t
-hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_athr_csco_mode_25m_set(
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value);
@@ -2410,5 +2412,29 @@
a_uint32_t index,
a_uint32_t value);
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_get(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union uniphy_misc2_phy_mode_u *value);
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_set(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union uniphy_misc2_phy_mode_u *value);
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_get(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union pll_power_on_and_reset_u *value);
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_set(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union pll_power_on_and_reset_u *value);
+
#endif
diff --git a/include/hsl/hppe/hppe_uniphy_reg.h b/include/hsl/hppe/hppe_uniphy_reg.h
index 067c3c5..773a3fe 100755
--- a/include/hsl/hppe/hppe_uniphy_reg.h
+++ b/include/hsl/hppe/hppe_uniphy_reg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -88,11 +88,11 @@
#define UNIPHY_MODE_CTRL_INC 0x1
#define UNIPHY_MODE_CTRL_TYPE REG_TYPE_RW
#define UNIPHY_MODE_CTRL_DEFAULT 0x221
- /*[field] NEWADDEDFROMHERE_CH0_ATHR_CSCO_MODE_25M*/
- #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_ATHR_CSCO_MODE_25M
- #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_ATHR_CSCO_MODE_25M_OFFSET 0
- #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_ATHR_CSCO_MODE_25M_LEN 1
- #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_ATHR_CSCO_MODE_25M_DEFAULT 0x1
+ /*[field] NEWADDEDFROMHERE_CH0_AUTONEG_MODE*/
+ #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE
+ #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_OFFSET 0
+ #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_LEN 1
+ #define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH0_AUTONEG_MODE_DEFAULT 0x1
/*[field] NEWADDEDFROMHERE_CH1_CH0_SGMII*/
#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII
#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_CH1_CH0_SGMII_OFFSET 1
@@ -150,7 +150,7 @@
#define UNIPHY_MODE_CTRL_NEWADDEDFROMHERE_SW_V17_V18_DEFAULT 0x0
struct uniphy_mode_ctrl {
- a_uint32_t newaddedfromhere_ch0_athr_csco_mode_25m:1;
+ a_uint32_t newaddedfromhere_ch0_autoneg_mode:1;
a_uint32_t newaddedfromhere_ch1_ch0_sgmii:1;
a_uint32_t newaddedfromhere_ch4_ch1_0_sgmii:1;
a_uint32_t newaddedfromhere_sgmii_even_low:1;
@@ -1483,4 +1483,112 @@
struct pll_control_vco_related_selection_2 bf;
};
+/*[register] PLL_POWER_ON_AND_RESET*/
+#define PLL_POWER_ON_AND_RESET
+#define PLL_POWER_ON_AND_RESET_ADDRESS 0x780
+#define PLL_POWER_ON_AND_RESET_NUM 4
+#define PLL_POWER_ON_AND_RESET_INC 0x1
+#define PLL_POWER_ON_AND_RESET_TYPE REG_TYPE_RW
+#define PLL_POWER_ON_AND_RESET_DEFAULT 0x2ff
+ /*[field] MIIREG_UPHY_PLL_RSTN*/
+ #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN
+ #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_OFFSET 0
+ #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_LEN 1
+ #define MIIREG_UPHY_PLL_RSTN_MIIREG_UPHY_PLL_RSTN_DEFAULT 0x1
+ /*[field] MIIREG_REG_UPHY_PLL_EN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_OFFSET 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_REG_UPHY_PLL_EN_DEFAULT 0x1
+ /*[field] MIIREG_UPHY_RXCLK_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_OFFSET 2
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_SW_RSTN_DEFAULT 0x1
+ /*[field] MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_OFFSET 3
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_RXCLK_FLOOP_SW_RSTN_DEFAULT 0x1
+ /*[field] MIIREG_UPHY_TXCLK_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_OFFSET 4
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_TXCLK_SW_RSTN_DEFAULT 0x0
+ /*[field] MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_OFFSET 5
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_SSC_CTRL_CLK_SW_RSTN_DEFAULT 0x0
+ /*[field] MIIREG_UPHY_ANA_EN_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_OFFSET 6
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_ANA_EN_SW_RSTN_DEFAULT 0x0
+ /*[field] MIIREG_UPHY_PLL_MMDIV_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_OFFSET 7
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PLL_MMDIV_RSTN_DEFAULT 0x0
+ /*[field] MIIREG_UPHY_CMN_12GPLL_ISOLATION*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_OFFSET 8
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_CMN_12GPLL_ISOLATION_DEFAULT 0x0
+ /*[field] MIIREG_UPHY_PCS_SW_RSTN*/
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_OFFSET 9
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_LEN 1
+ #define PLL_POWER_ON_AND_RESET_MIIREG_UPHY_PCS_SW_RSTN_DEFAULT 0x0
+
+struct pll_power_on_and_reset {
+ a_uint32_t pll_reset:1;
+ a_uint32_t pll_power_on:1;
+ a_uint32_t software_reset_rxclk:1;
+ a_uint32_t software_reset_rxclk_floop:1;
+ a_uint32_t software_reset_txclk:1;
+ a_uint32_t software_reset_ctrlclk:1;
+ a_uint32_t software_reset_analog_reset:1;
+ a_uint32_t reference_clock_reset:1;
+ a_uint32_t cmn_12gpll_isolation:1;
+ a_uint32_t pqsgmii_pcs_reset:1;
+ a_uint32_t _reserved0:22;
+};
+
+union pll_power_on_and_reset_u {
+ a_uint32_t val;
+ struct pll_power_on_and_reset bf;
+};
+
+/*[register] UNIPHY_MISC2_PHY_MODE*/
+#define UNIPHY_MISC2_PHY_MODE
+#define UNIPHY_MISC2_PHY_MODE_ADDRESS 0x218
+#define UNIPHY_MISC2_PHY_MODE_NUM 4
+#define UNIPHY_MISC2_PHY_MODE_INC 0x1
+#define UNIPHY_MISC2_PHY_MODE_TYPE REG_TYPE_RW
+#define UNIPHY_MISC2_PHY_MODE_DEFAULT 0x0
+ /*[field] MMD1_REG_REG_RATE*/
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_OFFSET 0
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_LEN 2
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_RATE_DEFAULT 0x1
+ /*[field] MMD1_REG_REG_PHY_MODE*/
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_OFFSET 4
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_LEN 3
+ #define UNIPHY_MISC2_PHY_MODE_MMD1_REG_REG_PHY_MODE_DEFAULT 0x1
+
+
+struct uniphy_misc2_phy_mode {
+ a_uint32_t phy_rate:2;
+ a_uint32_t _reserved0:2;
+ a_uint32_t phy_mode:3;
+ a_uint32_t _reserved1:25;
+};
+
+union uniphy_misc2_phy_mode_u {
+ a_uint32_t val;
+ struct uniphy_misc2_phy_mode bf;
+};
+
#endif
diff --git a/include/hsl/phy/hsl_phy.h b/include/hsl/phy/hsl_phy.h
index 8dcfe64..1bbceb7 100755
--- a/include/hsl/phy/hsl_phy.h
+++ b/include/hsl/phy/hsl_phy.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -522,44 +522,44 @@
a_bool_t phy_combo[SW_MAX_NR_PORT];
} phy_info_t;
/*qca808x_end*/
-#define MALIBU5PORT_PHY 0x004DD0B1
-#define MALIBU2PORT_PHY 0x004DD0B2
-#define QCA8030_PHY 0x004DD076
-#define QCA8033_PHY 0x004DD074
-#define QCA8035_PHY 0x004DD072
+#define MALIBU5PORT_PHY 0x004DD0B1
+#define MALIBU2PORT_PHY 0x004DD0B2
+#define QCA8030_PHY 0x004DD076
+#define QCA8033_PHY 0x004DD074
+#define QCA8035_PHY 0x004DD072
/*qca808x_start*/
-#define QCA8081_PHY 0x004DD100
-#define QCA8081_PHY_V1_1 0x004DD101
-#define INVALID_PHY_ID 0
+#define QCA8081_PHY 0x004DD100
+#define QCA8081_PHY_V1_1 0x004DD101
+#define INVALID_PHY_ID 0
/*qca808x_end*/
-#define F1V1_PHY 0x004DD033
-#define F1V2_PHY 0x004DD034
-#define F1V3_PHY 0x004DD035
-#define F1V4_PHY 0x004DD036
-#define F2V1_PHY 0x004DD042
-#define AQUANTIA_PHY_107 0x03a1b4e2
-#define AQUANTIA_PHY_108 0x03a1b4f2
-#define AQUANTIA_PHY_109 0x03a1b502
-#define AQUANTIA_PHY_111 0x03a1b610
-#define AQUANTIA_PHY_111B0 0x03a1b612
-#define AQUANTIA_PHY_112 0x03a1b660
-#define PHY_805XV2 0x004DD082
-#define PHY_805XV1 0x004DD081
+#define F1V1_PHY 0x004DD033
+#define F1V2_PHY 0x004DD034
+#define F1V3_PHY 0x004DD035
+#define F1V4_PHY 0x004DD036
+#define F2V1_PHY 0x004DD042
+#define AQUANTIA_PHY_107 0x03a1b4e2
+#define AQUANTIA_PHY_108 0x03a1b4f2
+#define AQUANTIA_PHY_109 0x03a1b502
+#define AQUANTIA_PHY_111 0x03a1b610
+#define AQUANTIA_PHY_111B0 0x03a1b612
+#define AQUANTIA_PHY_112 0x03a1b660
+#define PHY_805XV2 0x004DD082
+#define PHY_805XV1 0x004DD081
/*qca808x_start*/
-#define SFP_PHY 0xaaaabbbb
+#define SFP_PHY 0xaaaabbbb
/*qca808x_end*/
-#define SFP_PHY_MASK 0xffffffff
+#define SFP_PHY_MASK 0xffffffff
-#define CABLE_PAIR_A 0
-#define CABLE_PAIR_B 1
-#define CABLE_PAIR_C 2
-#define CABLE_PAIR_D 3
+#define CABLE_PAIR_A 0
+#define CABLE_PAIR_B 1
+#define CABLE_PAIR_C 2
+#define CABLE_PAIR_D 3
/*qca808x_start*/
-#define PHY_MDIO_ACCESS 0
-#define PHY_I2C_ACCESS 1
+#define PHY_MDIO_ACCESS 0
+#define PHY_I2C_ACCESS 1
-#define INVALID_PHY_ADDR 0xff
+#define INVALID_PHY_ADDR 0xff
sw_error_t
hsl_phy_api_ops_register(phy_type_t phy_type, hsl_phy_ops_t * phy_api_ops);
@@ -624,11 +624,15 @@
a_uint8_t access_type);
/*qca808x_end*/
sw_error_t
-hsl_ssdk_phy_serdes_reset(a_uint32_t dev_id);
+hsl_port_phy_serdes_reset(a_uint32_t dev_id);
sw_error_t
-hsl_ssdk_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode);
+hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode);
phy_type_t hsl_phy_type_get(a_uint32_t dev_id, a_uint32_t port_id);
+
+a_uint32_t
+hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id);
+
/*qca808x_start*/
sw_error_t ssdk_phy_driver_cleanup(void);
/*qca808x_end*/
diff --git a/include/init/ssdk_plat.h b/include/init/ssdk_plat.h
index 74507b3..496acf2 100755
--- a/include/init/ssdk_plat.h
+++ b/include/init/ssdk_plat.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012, 2014-2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2014-2015, 2017-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -186,19 +186,23 @@
#define QCA_PHY_MIB_WORK_DELAY 120000
#define QCA_MIB_ITEM_NUMBER 41
-#define SSDK_MAX_UNIPHY_INSTANCE 3
-#define SSDK_UNIPHY_INSTANCE0 0
-#define SSDK_UNIPHY_INSTANCE1 1
-#define SSDK_UNIPHY_INSTANCE2 2
+#define SSDK_MAX_UNIPHY_INSTANCE 3
+#define SSDK_UNIPHY_INSTANCE0 0
+#define SSDK_UNIPHY_INSTANCE1 1
+#define SSDK_UNIPHY_INSTANCE2 2
+#define SSDK_UNIPHY_CHANNEL0 0
+#define SSDK_UNIPHY_CHANNEL1 1
+#define SSDK_UNIPHY_CHANNEL4 4
+
/*qca808x_start*/
-#define SSDK_PHYSICAL_PORT0 0
-#define SSDK_PHYSICAL_PORT1 1
-#define SSDK_PHYSICAL_PORT2 2
-#define SSDK_PHYSICAL_PORT3 3
-#define SSDK_PHYSICAL_PORT4 4
-#define SSDK_PHYSICAL_PORT5 5
-#define SSDK_PHYSICAL_PORT6 6
-#define SSDK_PHYSICAL_PORT7 7
+#define SSDK_PHYSICAL_PORT0 0
+#define SSDK_PHYSICAL_PORT1 1
+#define SSDK_PHYSICAL_PORT2 2
+#define SSDK_PHYSICAL_PORT3 3
+#define SSDK_PHYSICAL_PORT4 4
+#define SSDK_PHYSICAL_PORT5 5
+#define SSDK_PHYSICAL_PORT6 6
+#define SSDK_PHYSICAL_PORT7 7
/*qca808x_end*/
#define SSDK_GLOBAL_INT0_ACL_INI_INT (1<<29)
#define SSDK_GLOBAL_INT0_LOOKUP_INI_INT (1<<28)
diff --git a/src/adpt/cppe/Makefile b/src/adpt/cppe/Makefile
index 26ba4ae..1689390 100755
--- a/src/adpt/cppe/Makefile
+++ b/src/adpt/cppe/Makefile
@@ -17,6 +17,10 @@
SRC_LIST += adpt_cppe_qos.c
endif
+ifeq (TRUE, $(IN_UNIPHY))
+ SRC_LIST += adpt_cppe_uniphy.c
+endif
+
ifeq (, $(findstring CPPE, $(SUPPORT_CHIP)))
SRC_LIST=
endif
diff --git a/src/adpt/cppe/adpt_cppe_portctrl.c b/src/adpt/cppe/adpt_cppe_portctrl.c
index e690108..fa2e7c4 100755
--- a/src/adpt/cppe/adpt_cppe_portctrl.c
+++ b/src/adpt/cppe/adpt_cppe_portctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -24,48 +24,114 @@
#include "hppe_portctrl.h"
#include "cppe_portctrl_reg.h"
#include "cppe_portctrl.h"
-#include "adpt.h"
#include "hsl.h"
#include "hsl_dev.h"
-#include "ssdk_dts.h"
+#include "hsl_phy.h"
+#include "hsl_port_prop.h"
+#include "adpt.h"
+#include "adpt_hppe.h"
#include "adpt_cppe_portctrl.h"
sw_error_t
-_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type)
+_adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id,
+ a_uint32_t port_type)
{
sw_error_t rv = SW_OK;
a_uint32_t mode0, mode1;
union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
- memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+ memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
mode0 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
mode1 = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE1);
- if ((mode0 == PORT_WRAPPER_PSGMII) && (mode1 == PORT_WRAPPER_MAX)) {
- cppe_port_mux_ctrl.bf.port3_pcs_sel =
- CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
- cppe_port_mux_ctrl.bf.port4_pcs_sel =
- CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
- cppe_port_mux_ctrl.bf.port5_pcs_sel =
- CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
- cppe_port_mux_ctrl.bf.port5_gmac_sel =
- CPPE_PORT5_GMAC_SEL_GMAC;
- } else if (((mode0 == PORT_WRAPPER_PSGMII) || (mode0 == PORT_WRAPPER_QSGMII))
- && (mode1 == PORT_WRAPPER_USXGMII)) {
- cppe_port_mux_ctrl.bf.port3_pcs_sel =
- CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
- cppe_port_mux_ctrl.bf.port4_pcs_sel =
- CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
- cppe_port_mux_ctrl.bf.port5_pcs_sel =
- CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
- cppe_port_mux_ctrl.bf.port5_gmac_sel =
- CPPE_PORT5_GMAC_SEL_XGMAC;
- } else {
- return SW_OK;
+ switch (port_id) {
+ case SSDK_PHYSICAL_PORT3:
+ case SSDK_PHYSICAL_PORT4:
+ if (mode0 == PORT_WRAPPER_PSGMII) {
+ if (hsl_port_phyid_get(dev_id,
+ SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ } else {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ }
+ } else if (mode0 == PORT_WRAPPER_QSGMII) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ } else if (mode0 == PORT_WRAPPER_SGMII_PLUS) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS;
+ } else if (mode0 ==PORT_WRAPPER_SGMII_CHANNEL0) {
+ if (hsl_port_phyid_get(dev_id,
+ SSDK_PHYSICAL_PORT4) == QCA8081_PHY_V1_1) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_SGMIIPLUS;
+ } else {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ }
+ } else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL4) ||
+ (mode0 == PORT_WRAPPER_SGMII0_RGMII4)) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ cppe_port_mux_ctrl.bf.port5_pcs_sel =
+ CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
+ cppe_port_mux_ctrl.bf.port5_gmac_sel =
+ CPPE_PORT5_GMAC_SEL_GMAC;
+ } else if ((mode0 == PORT_WRAPPER_SGMII_CHANNEL1) ||
+ (mode0 == PORT_WRAPPER_SGMII1_RGMII4)) {
+ cppe_port_mux_ctrl.bf.port3_pcs_sel =
+ CPPE_PORT3_PCS_SEL_PCS0_CHANNEL2;
+ cppe_port_mux_ctrl.bf.port4_pcs_sel =
+ CPPE_PORT4_PCS_SEL_PCS0_CHANNEL3;
+ }
+ break;
+ case SSDK_PHYSICAL_PORT5:
+ if (mode0 == PORT_WRAPPER_PSGMII) {
+ if (hsl_port_phyid_get(dev_id,
+ SSDK_PHYSICAL_PORT3) != MALIBU2PORT_PHY) {
+ cppe_port_mux_ctrl.bf.port5_pcs_sel =
+ CPPE_PORT5_PCS_SEL_PCS0_CHANNEL4;
+ cppe_port_mux_ctrl.bf.port5_gmac_sel =
+ CPPE_PORT5_GMAC_SEL_GMAC;
+ }
+ }
+ if ((mode1 == PORT_WRAPPER_SGMII_PLUS) ||
+ (mode1 == PORT_WRAPPER_SGMII0_RGMII4) ||
+ (mode1 == PORT_WRAPPER_SGMII_CHANNEL0)) {
+ cppe_port_mux_ctrl.bf.port5_pcs_sel =
+ CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
+ cppe_port_mux_ctrl.bf.port5_gmac_sel =
+ CPPE_PORT5_GMAC_SEL_GMAC;
+ } else if (mode1 == PORT_WRAPPER_USXGMII) {
+ cppe_port_mux_ctrl.bf.port5_pcs_sel =
+ CPPE_PORT5_PCS_SEL_PCS1_CHANNEL0;
+ cppe_port_mux_ctrl.bf.port5_gmac_sel =
+ CPPE_PORT5_GMAC_SEL_XGMAC;
+ }
+ break;
+ default:
+ break;
}
rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
@@ -164,6 +230,24 @@
return SW_OK;
}
+sw_error_t
+adpt_cppe_port_to_channel_convert(a_uint32_t dev_id, a_uint32_t port_id,
+ a_uint32_t *channel_id)
+{
+ ADPT_DEV_ID_CHECK(dev_id);
+ ADPT_NULL_POINT_CHECK(channel_id);
+
+ *channel_id = port_id;
+
+ if (port_id == SSDK_PHYSICAL_PORT3) {
+ if (hsl_port_phyid_get(dev_id,
+ port_id) == MALIBU2PORT_PHY) {
+ *channel_id = SSDK_PHYSICAL_PORT5;
+ }
+ }
+ return SW_OK;
+}
+
/**
* @}
*/
diff --git a/src/adpt/cppe/adpt_cppe_uniphy.c b/src/adpt/cppe/adpt_cppe_uniphy.c
new file mode 100755
index 0000000..b5eb188
--- /dev/null
+++ b/src/adpt/cppe/adpt_cppe_uniphy.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "ssdk_clk.h"
+#include "adpt_hppe.h"
+#include "adpt.h"
+#include "hppe_reg_access.h"
+#include "hsl_phy.h"
+#include "adpt_cppe_portctrl.h"
+#include "adpt_cppe_uniphy.h"
+
+#ifdef HAWKEYE_CHIP
+
+static sw_error_t
+__adpt_cppe_uniphy_reset(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+ sw_error_t rv = SW_OK;
+ union pll_power_on_and_reset_u pll_software_reset;
+
+ memset(&pll_software_reset, 0, sizeof(pll_software_reset));
+ ADPT_DEV_ID_CHECK(dev_id);
+
+ rv = hppe_uniphy_pll_reset_ctrl_get(dev_id, uniphy_index,
+ &pll_software_reset);
+ SW_RTN_ON_ERROR (rv);
+ pll_software_reset.bf.software_reset_analog_reset = 0;
+ rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+ &pll_software_reset);
+ SW_RTN_ON_ERROR (rv);
+ msleep(500);
+ pll_software_reset.bf.software_reset_analog_reset = 1;
+ rv = hppe_uniphy_pll_reset_ctrl_set(dev_id, uniphy_index,
+ &pll_software_reset);
+ SW_RTN_ON_ERROR (rv);
+ msleep(500);
+
+ return SW_OK;
+}
+
+static sw_error_t
+__adpt_cppe_uniphy_port_disable(a_uint32_t dev_id, a_uint32_t uniphy_index,
+ a_uint32_t port_id)
+{
+ /*disable unused uniphy port, need add it once CoreBSP framework is ready*/
+
+ return SW_OK;
+}
+
+static sw_error_t
+__adpt_cppe_uniphy_port_software_reset(a_uint32_t dev_id,
+ a_uint32_t uniphy_index, a_uint32_t port_id)
+{
+ /*reset operation should be in one ahb write operatrion */
+ /*need update it again once CoreBSP framework is ready to support*/
+
+ __adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
+
+ return SW_OK;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_channel_selection_set(a_uint32_t dev_id)
+{
+ sw_error_t rv = SW_OK;
+ union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+
+ memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+ ADPT_DEV_ID_CHECK(dev_id);
+
+ rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+ cppe_port_mux_ctrl.bf.pcs0_ch0_sel =
+ CPPE_PCS0_CHANNEL0_SEL_PSGMII;
+ cppe_port_mux_ctrl.bf.pcs0_ch4_sel =
+ CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK;
+ rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ return rv;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_connection_qca8072_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t i = 0;
+ union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+ union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+ memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+ memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+ ADPT_DEV_ID_CHECK(dev_id);
+
+ if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+ return SW_BAD_VALUE;
+ }
+
+ /* keep xpcs to reset status */
+ __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+ /* disable GCC_UNIPHY0_MISC port 1, 2 and 3*/
+ for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT4; i++) {
+ rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i);
+ SW_RTN_ON_ERROR (rv);
+ }
+
+ /* disable instance0 clock */
+ for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) {
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ i, A_FALSE);
+ }
+
+ rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+ cppe_port_mux_ctrl.bf.pcs0_ch0_sel =
+ CPPE_PCS0_CHANNEL0_SEL_PSGMII;
+ cppe_port_mux_ctrl.bf.pcs0_ch4_sel =
+ CPPE_PCS0_CHANNEL4_SEL_PORT3_CLOCK;
+ rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ /* configure uniphy to Athr mode and psgmii mode */
+ rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_PSGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
+ rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ /* configure uniphy gcc port 4 and port 5 software reset */
+ for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) {
+ rv = __adpt_cppe_uniphy_port_software_reset(dev_id, uniphy_index, i);
+ SW_RTN_ON_ERROR (rv);
+ }
+
+ /* wait uniphy calibration done */
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+ SW_RTN_ON_ERROR (rv);
+
+ rv = hsl_port_phy_serdes_reset(dev_id);
+ SW_RTN_ON_ERROR (rv);
+
+ /* enable instance0 clock */
+ for (i = SSDK_PHYSICAL_PORT4; i < SSDK_PHYSICAL_PORT6; i++) {
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ i, A_TRUE);
+ }
+
+ return rv;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_connection_qca808x_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t i = 0;
+
+ union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+ union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+ union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode;
+
+ memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+ memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+ memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode));
+
+ ADPT_DEV_ID_CHECK(dev_id);
+
+ if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+ return SW_BAD_VALUE;
+ }
+
+ /*set the PHY mode to SGMII*/
+ rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, uniphy_index,
+ &uniphy_misc2_phy_mode);
+ SW_RTN_ON_ERROR (rv);
+ uniphy_misc2_phy_mode.bf.phy_mode = UNIPHY_PHY_SGMII_MODE;
+ rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, uniphy_index,
+ &uniphy_misc2_phy_mode);
+ SW_RTN_ON_ERROR (rv);
+
+ /*reset uniphy*/
+ rv = __adpt_cppe_uniphy_reset(dev_id, uniphy_index);
+ SW_RTN_ON_ERROR (rv);
+
+ /* keep xpcs to reset status */
+ __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+ /* disable GCC_UNIPHY0_MISC port 1, 2, 3 and 5*/
+ for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) {
+ if (i == SSDK_PHYSICAL_PORT4) {
+ continue;
+ }
+ rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i);
+ SW_RTN_ON_ERROR (rv);
+ }
+
+ /* disable instance0 port 4 clock */
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4, A_FALSE);
+
+ /* configure uniphy to Athr mode and sgmiiplus mode */
+ rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_ENABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
+
+ rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+ cppe_port_mux_ctrl.bf.pcs0_ch0_sel =
+ CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS;
+ cppe_port_mux_ctrl.bf.pcs0_ch4_sel =
+ CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK;
+ rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ /* configure uniphy gcc port 4 software reset */
+ rv = __adpt_cppe_uniphy_port_software_reset(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4);
+ SW_RTN_ON_ERROR (rv);
+
+ /* wait uniphy calibration done */
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+ /* enable instance clock */
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4, A_TRUE);
+ return rv;
+}
+
+sw_error_t
+__adpt_cppe_uniphy_sgmiiplus_mode_set(a_uint32_t dev_id,
+ a_uint32_t uniphy_index)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t i = 0;
+
+ union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+ union cppe_port_mux_ctrl_u cppe_port_mux_ctrl;
+ union uniphy_misc2_phy_mode_u uniphy_misc2_phy_mode;
+
+ memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+ memset(&cppe_port_mux_ctrl, 0, sizeof(cppe_port_mux_ctrl));
+ memset(&uniphy_misc2_phy_mode, 0, sizeof(uniphy_misc2_phy_mode));
+
+ ADPT_DEV_ID_CHECK(dev_id);
+
+ rv = hppe_uniphy_phy_mode_ctrl_get(dev_id, uniphy_index,
+ &uniphy_misc2_phy_mode);
+ SW_RTN_ON_ERROR (rv);
+ uniphy_misc2_phy_mode.bf.phy_mode = UNIPHY_PHY_SGMIIPLUS_MODE;
+ rv = hppe_uniphy_phy_mode_ctrl_set(dev_id, uniphy_index,
+ &uniphy_misc2_phy_mode);
+ SW_RTN_ON_ERROR (rv);
+
+ /*reset uniphy*/
+ rv = __adpt_cppe_uniphy_reset(dev_id, uniphy_index);
+ SW_RTN_ON_ERROR (rv);
+
+ /* keep xpcs to reset status */
+ __adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
+
+ /* disable GCC_UNIPHY0_MISC port 1, 2, 3 and 5*/
+ for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++) {
+ if (i == SSDK_PHYSICAL_PORT4) {
+ continue;
+ }
+ rv = __adpt_cppe_uniphy_port_disable(dev_id, uniphy_index, i);
+ SW_RTN_ON_ERROR (rv);
+ }
+
+ /* disable instance0 port 4 clock */
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4, A_FALSE);
+
+ /* configure uniphy to Athr mode and sgmiiplus mode */
+ rv = hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_ENABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
+
+ rv = hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ rv = cppe_port_mux_ctrl_get(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+ cppe_port_mux_ctrl.bf.pcs0_ch0_sel =
+ CPPE_PCS0_CHANNEL0_SEL_SGMIIPLUS;
+ cppe_port_mux_ctrl.bf.pcs0_ch4_sel =
+ CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK;
+ rv = cppe_port_mux_ctrl_set(dev_id, &cppe_port_mux_ctrl);
+ SW_RTN_ON_ERROR (rv);
+
+ /* configure uniphy gcc port 4 software reset */
+ rv = __adpt_cppe_uniphy_port_software_reset(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4);
+ SW_RTN_ON_ERROR (rv);
+
+ /* wait uniphy calibration done */
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
+
+ /* enable instance clock */
+ qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
+ SSDK_PHYSICAL_PORT4, A_TRUE);
+ return rv;
+}
+
+#endif
+
+/**
+ * @}
+ */
diff --git a/src/adpt/hppe/adpt_hppe_portctrl.c b/src/adpt/hppe/adpt_hppe_portctrl.c
index 7c00529..aa5a8d7 100755
--- a/src/adpt/hppe/adpt_hppe_portctrl.c
+++ b/src/adpt/hppe/adpt_hppe_portctrl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -4044,14 +4044,23 @@
return;
}
+
static void
adpt_hppe_uniphy_port_adapter_reset(a_uint32_t dev_id, a_uint32_t port_id)
{
a_uint32_t uniphy_index, mode, mode1;
+#if defined(CPPE)
+ a_uint32_t channel_id = 0;
+#endif
if (port_id < HPPE_MUX_PORT1)
{
uniphy_index = SSDK_UNIPHY_INSTANCE0;
+#if defined(CPPE)
+ adpt_cppe_port_to_channel_convert(dev_id, port_id,
+ &channel_id);
+ port_id = channel_id;
+#endif
adpt_hppe_uniphy_psgmii_port_reset(dev_id, uniphy_index,
port_id);
}
@@ -4348,6 +4357,15 @@
if (port_id < HPPE_MUX_PORT1)
{
+#if defined(CPPE)
+ if (port_id == SSDK_PHYSICAL_PORT4) {
+ mode = ssdk_dt_global_get_mac_mode(dev_id, SSDK_UNIPHY_INSTANCE0);
+ if (mode == PORT_WRAPPER_SGMII_PLUS) {
+ adpt_hppe_sgmiiplus_speed_clock_set(dev_id, port_id, phy_speed);
+ return;
+ }
+ }
+#endif
adpt_hppe_pqsgmii_speed_clock_set(dev_id, port_id, phy_speed);
}
else
@@ -4388,10 +4406,18 @@
a_bool_t enable)
{
a_uint32_t mode = 0, uniphy_index = 0, mode1 = 0;
+#if defined(CPPE)
+ a_uint32_t channel_id = 0;
+#endif
if (port_id < HPPE_MUX_PORT1)
{
uniphy_index = SSDK_UNIPHY_INSTANCE0;
+#if defined(CPPE)
+ adpt_cppe_port_to_channel_convert(dev_id, port_id,
+ &channel_id);
+ port_id = channel_id;
+#endif
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
port_id, enable);
}
diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
index 7931b6e..76badaa 100755
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -26,6 +26,11 @@
#include "adpt.h"
#include "hppe_reg_access.h"
#include "hsl_phy.h"
+#include "adpt_hppe.h"
+#if defined(CPPE)
+#include "adpt_cppe_uniphy.h"
+#include "adpt_cppe_portctrl.h"
+#endif
#ifdef HAWKEYE_CHIP
@@ -57,8 +62,8 @@
return SW_OK;
}
-static sw_error_t
-__adpt_hppe_uniphy_calibration(a_uint32_t dev_id, a_uint32_t uniphy_index)
+sw_error_t
+__adpt_hppe_uniphy_calibrate(a_uint32_t dev_id, a_uint32_t uniphy_index)
{
a_uint32_t reg_value = 0;
a_uint32_t retries = 100, calibration_done = 0;
@@ -86,7 +91,7 @@
return SW_OK;
}
-static void
+void
__adpt_hppe_gcc_uniphy_xpcs_reset(a_uint32_t dev_id, a_uint32_t uniphy_index, a_bool_t enable)
{
enum unphy_rst_type rst_type;
@@ -109,7 +114,7 @@
return;
}
-static void
+void
__adpt_hppe_gcc_uniphy_software_reset(a_uint32_t dev_id, a_uint32_t uniphy_index)
{
@@ -166,11 +171,16 @@
/* configure uniphy to usxgmii mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 1;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_ENABLE;
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
/* configure uniphy usxgmii gcc software reset */
@@ -179,7 +189,7 @@
msleep(100);
/* wait calibration done to uniphy */
- __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
/* enable instance clock */
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
@@ -240,11 +250,16 @@
/* configure uniphy to 10g_r mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 1;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_ENABLE;
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
@@ -256,7 +271,7 @@
__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
/* wait uniphy calibration done */
- rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
/* configure gcc speed clock to 10g r mode*/
if (uniphy_index == SSDK_UNIPHY_INSTANCE1)
@@ -285,6 +300,14 @@
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+#if defined(CPPE)
+ if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+ && (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ rv = __adpt_cppe_uniphy_sgmiiplus_mode_set(dev_id, uniphy_index);
+ return rv;
+ }
+#endif
+
hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET,
uniphy_index, UNIPHY_MISC2_REG_SGMII_PLUS_MODE);
/*reset uniphy*/
@@ -305,12 +328,18 @@
/* configure uniphy to Athr mode and sgmiiplus mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_athr_csco_mode_25m = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 1;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_ENABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
@@ -318,7 +347,7 @@
__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
/* wait uniphy calibration done */
- rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
/* enable instance clock */
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
@@ -331,12 +360,30 @@
{
a_uint32_t i, max_port, mode;
sw_error_t rv = SW_OK;
+#if defined(CPPE)
+ a_uint32_t phy_type = 0;
+#endif
union uniphy_mode_ctrl_u uniphy_mode_ctrl;
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+#if defined(CPPE)
+ if ((uniphy_index == SSDK_UNIPHY_INSTANCE0) &&
+ (channel == SSDK_UNIPHY_CHANNEL0)) {
+ if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ phy_type = hsl_port_phyid_get(dev_id,
+ SSDK_PHYSICAL_PORT4);
+ if (phy_type == QCA8081_PHY_V1_1) {
+ rv = __adpt_cppe_uniphy_connection_qca808x_set(dev_id,
+ uniphy_index);
+ return rv;
+ }
+ }
+ }
+#endif
+
/*set the PHY mode to SGMII*/
hppe_uniphy_reg_set(dev_id, UNIPHY_MISC2_REG_OFFSET,
uniphy_index, UNIPHY_MISC2_REG_SGMII_MODE);
@@ -363,6 +410,14 @@
i, A_FALSE);
}
+#if defined(CPPE)
+ if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+ (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ rv = __adpt_cppe_uniphy_channel_selection_set(dev_id);
+ SW_RTN_ON_ERROR (rv);
+ }
+#endif
+
/* configure uniphy to Athr mode and sgmii mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
mode = ssdk_dt_global_get_mac_mode(dev_id, uniphy_index);
@@ -370,33 +425,46 @@
{
uniphy_mode_ctrl.bf.newaddedfromhere_ch0_mode_ctrl_25m = 0;
}
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_athr_csco_mode_25m = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
if (uniphy_index == SSDK_UNIPHY_INSTANCE0) {
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
/* select channel as a sgmii interface */
- if (channel == 0)
+ if (channel == SSDK_UNIPHY_CHANNEL0)
{
- uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+ UNIPHY_SGMII_CHANNEL1_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+ UNIPHY_SGMII_CHANNEL4_DISABLE;
}
- else if (channel == 1)
+ else if (channel == SSDK_UNIPHY_CHANNEL1)
{
- uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = 1;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+ UNIPHY_SGMII_CHANNEL1_ENABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+ UNIPHY_SGMII_CHANNEL4_DISABLE;
}
- else if (channel == 4)
+ else if (channel == SSDK_UNIPHY_CHANNEL4)
{
- uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii = 1;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch1_ch0_sgmii =
+ UNIPHY_SGMII_CHANNEL1_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch4_ch1_0_sgmii =
+ UNIPHY_SGMII_CHANNEL4_ENABLE;
}
}
else
{
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 1;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_ENABLE;
}
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
@@ -405,7 +473,7 @@
__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
/* wait uniphy calibration done */
- rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
/* enable instance clock */
if (uniphy_index == SSDK_UNIPHY_INSTANCE0)
@@ -434,7 +502,8 @@
ADPT_DEV_ID_CHECK(dev_id);
/* configure malibu phy to qsgmii mode*/
- hsl_ssdk_phy_mode_set(dev_id, PORT_QSGMII);
+ rv = hsl_port_phy_mode_set(dev_id, PORT_QSGMII);
+ SW_RTN_ON_ERROR (rv);
/* keep xpcs to reset status */
__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
@@ -448,21 +517,28 @@
/* configure uniphy to Athr mode and qsgmii mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_athr_csco_mode_25m = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 1;
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_QSGMII_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_QSGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
/* configure uniphy gcc software reset */
__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
/* wait uniphy calibration done */
- rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
- hsl_ssdk_phy_serdes_reset(dev_id);
+ rv = hsl_port_phy_serdes_reset(dev_id);
+ SW_RTN_ON_ERROR (rv);
/* enable instance0 clock */
for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
@@ -479,12 +555,27 @@
{
a_uint32_t i;
sw_error_t rv = SW_OK;
+#if defined(CPPE)
+ a_uint32_t phy_type = 0;
+#endif
union uniphy_mode_ctrl_u uniphy_mode_ctrl;
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+#if defined(CPPE)
+ if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ phy_type = hsl_port_phyid_get(dev_id,
+ SSDK_PHYSICAL_PORT3);
+ if (phy_type == MALIBU2PORT_PHY) {
+ rv = __adpt_cppe_uniphy_connection_qca8072_set(dev_id,
+ uniphy_index);
+ return rv;
+ }
+ }
+#endif
+
/* keep xpcs to reset status */
__adpt_hppe_gcc_uniphy_xpcs_reset(dev_id, uniphy_index, A_TRUE);
@@ -495,23 +586,38 @@
i, A_FALSE);
}
+#if defined(CPPE)
+ if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
+ (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ rv = __adpt_cppe_uniphy_channel_selection_set(dev_id);
+ SW_RTN_ON_ERROR (rv);
+ }
+#endif
+
/* configure uniphy to Athr mode and psgmii mode */
hppe_uniphy_mode_ctrl_get(dev_id, uniphy_index, &uniphy_mode_ctrl);
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_athr_csco_mode_25m = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 1;
- uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
- uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 0;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_autoneg_mode =
+ UNIPHY_ATHEROS_NEGOTIATION;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii =
+ UNIPHY_CH0_PSGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii =
+ UNIPHY_CH0_SGMII_MODE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode =
+ UNIPHY_SGMII_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode =
+ UNIPHY_SGMIIPLUS_MODE_DISABLE;
+ uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode =
+ UNIPHY_XPCS_MODE_DISABLE;
hppe_uniphy_mode_ctrl_set(dev_id, uniphy_index, &uniphy_mode_ctrl);
/* configure uniphy gcc software reset */
__adpt_hppe_gcc_uniphy_software_reset(dev_id, uniphy_index);
/* wait uniphy calibration done */
- rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+ rv = __adpt_hppe_uniphy_calibrate(dev_id, uniphy_index);
- hsl_ssdk_phy_serdes_reset(dev_id);
+ rv = hsl_port_phy_serdes_reset(dev_id);
+ SW_RTN_ON_ERROR (rv);
/* enable instance0 clock */
for (i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT6; i++)
@@ -547,17 +653,20 @@
case PORT_WRAPPER_SGMII0_RGMII4:
case PORT_WRAPPER_SGMII_CHANNEL0:
case PORT_WRAPPER_SGMII_FIBER:
- rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, 0);
+ rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+ SSDK_UNIPHY_CHANNEL0);
break;
case PORT_WRAPPER_SGMII1_RGMII4:
case PORT_WRAPPER_SGMII_CHANNEL1:
- rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, 1);
+ rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+ SSDK_UNIPHY_CHANNEL1);
break;
case PORT_WRAPPER_SGMII4_RGMII4:
case PORT_WRAPPER_SGMII_CHANNEL4:
- rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index, 4);
+ rv = __adpt_hppe_uniphy_sgmii_mode_set(dev_id, index,
+ SSDK_UNIPHY_CHANNEL4);
break;
case PORT_WRAPPER_SGMII_PLUS:
diff --git a/src/hsl/hppe/hppe_uniphy.c b/src/hsl/hppe/hppe_uniphy.c
index 6192041..ede1060 100755
--- a/src/hsl/hppe/hppe_uniphy.c
+++ b/src/hsl/hppe/hppe_uniphy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -790,7 +790,7 @@
}
sw_error_t
-hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_athr_csco_mode_25m_get(
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_get(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t *value)
@@ -799,12 +799,12 @@
sw_error_t ret = SW_OK;
ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val);
- *value = reg_val.bf.newaddedfromhere_ch0_athr_csco_mode_25m;
+ *value = reg_val.bf.newaddedfromhere_ch0_autoneg_mode;
return ret;
}
sw_error_t
-hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_athr_csco_mode_25m_set(
+hppe_uniphy_mode_ctrl_newaddedfromhere_ch0_autoneg_mode_set(
a_uint32_t dev_id,
a_uint32_t index,
a_uint32_t value)
@@ -815,7 +815,7 @@
ret = hppe_uniphy_mode_ctrl_get(dev_id, index, ®_val);
if (SW_OK != ret)
return ret;
- reg_val.bf.newaddedfromhere_ch0_athr_csco_mode_25m = value;
+ reg_val.bf.newaddedfromhere_ch0_autoneg_mode = value;
ret = hppe_uniphy_mode_ctrl_set(dev_id, index, ®_val);
return ret;
}
@@ -6058,3 +6058,63 @@
}
#endif
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_get(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union uniphy_misc2_phy_mode_u *value)
+{
+ if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY)
+ return SW_OUT_OF_RANGE;
+ return hppe_uniphy_reg_get(
+ dev_id,
+ NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS,
+ index * UNIPHY_MISC2_PHY_MODE_INC,
+ &value->val);
+}
+
+sw_error_t
+hppe_uniphy_phy_mode_ctrl_set(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union uniphy_misc2_phy_mode_u *value)
+{
+ if (index >= UNIPHY_MISC2_PHY_MODE_MAX_ENTRY)
+ return SW_OUT_OF_RANGE;
+ return hppe_uniphy_reg_set(
+ dev_id,
+ NSS_UNIPHY_BASE_ADDR + UNIPHY_MISC2_PHY_MODE_ADDRESS,
+ index * UNIPHY_MISC2_PHY_MODE_INC,
+ value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_get(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union pll_power_on_and_reset_u *value)
+{
+ if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY)
+ return SW_OUT_OF_RANGE;
+ return hppe_uniphy_reg_get(
+ dev_id,
+ NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS,
+ index * PLL_POWER_ON_AND_RESET_INC,
+ &value->val);
+}
+
+sw_error_t
+hppe_uniphy_pll_reset_ctrl_set(
+ a_uint32_t dev_id,
+ a_uint32_t index,
+ union pll_power_on_and_reset_u *value)
+{
+ if (index >= UNIPHY_PLL_POWER_ON_AND_RESET_INC_MAX_ENTRY)
+ return SW_OUT_OF_RANGE;
+ return hppe_uniphy_reg_set(
+ dev_id,
+ NSS_UNIPHY_BASE_ADDR + PLL_POWER_ON_AND_RESET_ADDRESS,
+ index * PLL_POWER_ON_AND_RESET_INC,
+ value->val);
+}
+
diff --git a/src/hsl/phy/hsl_phy.c b/src/hsl/phy/hsl_phy.c
index a5ee6c9..9810ffc 100755
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved.
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
@@ -42,6 +42,7 @@
/*qca808x_start*/
#include "sw.h"
#include "ssdk_plat.h"
+#include "hsl_port_prop.h"
phy_info_t *phy_info[SW_MAX_NR_DEV] = {0};
a_uint32_t port_bmp[SW_MAX_NR_DEV] = {0};
@@ -513,7 +514,7 @@
return;
}
sw_error_t
-hsl_ssdk_phy_serdes_reset(a_uint32_t dev_id)
+hsl_port_phy_serdes_reset(a_uint32_t dev_id)
{
sw_error_t rv;
int i = 0;
@@ -533,8 +534,37 @@
return SW_OK;
}
+
+a_uint32_t
+hsl_port_phyid_get(a_uint32_t dev_id, fal_port_t port_id)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t phy_addr, phy_id;
+ hsl_phy_ops_t *phy_drv;
+
+ phy_drv = hsl_phy_api_ops_get (dev_id, port_id);
+ if (phy_drv == NULL) {
+ return INVALID_PHY_ID;
+ }
+ if (NULL == phy_drv->phy_id_get) {
+ return INVALID_PHY_ID;
+ }
+
+ rv = hsl_port_prop_get_phyid (dev_id, port_id, &phy_addr);
+ if(rv) {
+ return INVALID_PHY_ID;
+ }
+
+ rv = phy_drv->phy_id_get (dev_id, phy_addr, &phy_id);
+ if(rv) {
+ return INVALID_PHY_ID;
+ }
+
+ return phy_id;
+}
+
sw_error_t
-hsl_ssdk_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode)
+hsl_port_phy_mode_set(a_uint32_t dev_id, fal_port_interface_mode_t mode)
{
sw_error_t rv;
a_uint32_t i = 0, phy_addr = 0;