diff --git a/config b/config
index 32f20d0..d4a9503 100755
--- a/config
+++ b/config
@@ -213,6 +213,7 @@
 IN_BM=TRUE
 IN_SHAPER=TRUE
 IN_POLICER=TRUE
+IN_UNIPHY=TRUE
 ifneq ($(HK_CHIP), enable)
 CHIP_TYPE=NONHK_CHIP
 endif
diff --git a/include/adpt/adpt.h b/include/adpt/adpt.h
index 78ad325..7d4a7bc 100755
--- a/include/adpt/adpt.h
+++ b/include/adpt/adpt.h
@@ -278,6 +278,12 @@
 				a_bool_t * enable);
 typedef sw_error_t (*adpt_port_source_filter_set_func)(a_uint32_t dev_id, fal_port_t port_id,
 				a_bool_t enable);
+typedef sw_error_t (*adpt_port_mac_mux_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				a_uint32_t mux);
+typedef sw_error_t (*adpt_port_mac_speed_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_speed_t speed);
+typedef sw_error_t (*adpt_port_mac_duplex_set_func)(a_uint32_t dev_id, fal_port_t port_id,
+				fal_port_duplex_t duplex);
 // mirror
 typedef sw_error_t (*adpt_mirr_port_in_set_func)(a_uint32_t dev_id, fal_port_t port_id,
                          a_bool_t enable);
@@ -827,6 +833,9 @@
 typedef sw_error_t (*adpt_debug_port_counter_status_get_func)(a_uint32_t dev_id,
 			fal_port_t port_id, fal_counter_en_t * cnt_en);
 
+/* uniphy */
+typedef sw_error_t (*adpt_uniphy_mode_set_func)(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode);
+
 typedef struct
 {
 	a_uint32_t adpt_fdb_func_bitmap;
@@ -961,6 +970,9 @@
 	adpt_port_wol_status_get_func adpt_port_wol_status_get;
 	adpt_port_source_filter_set_func adpt_port_source_filter_set;
 	adpt_port_source_filter_get_func adpt_port_source_filter_get;
+	adpt_port_mac_mux_set_func adpt_port_mac_mux_set;
+	adpt_port_mac_speed_set_func adpt_port_mac_speed_set;
+	adpt_port_mac_duplex_set_func adpt_port_mac_duplex_set;
 // mirror
 	a_uint32_t adpt_mirror_func_bitmap;
 	adpt_mirr_port_in_set_func adpt_mirr_port_in_set;
@@ -1246,6 +1258,9 @@
 	/* misc */
 	adpt_debug_port_counter_enable_func adpt_debug_port_counter_enable;
 	adpt_debug_port_counter_status_get_func adpt_debug_port_counter_status_get;
+
+	/* uniphy */
+	adpt_uniphy_mode_set_func adpt_uniphy_mode_set;
 }adpt_api_t;
 
 
diff --git a/include/adpt/hppe/adpt_hppe.h b/include/adpt/hppe/adpt_hppe.h
index d65099a..48a2165 100755
--- a/include/adpt/hppe/adpt_hppe.h
+++ b/include/adpt/hppe/adpt_hppe.h
@@ -74,6 +74,8 @@
 
 void adpt_hppe_policer_func_bitmap_init(a_uint32_t dev_id);
 
+sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id);
+
 #ifdef __cplusplus
 }
 #endif                          /* __cplusplus */
diff --git a/include/hsl/hppe/hppe_init.h b/include/hsl/hppe/hppe_init.h
index 7cd7179..9423f70 100755
--- a/include/hsl/hppe/hppe_init.h
+++ b/include/hsl/hppe/hppe_init.h
@@ -27,6 +27,12 @@
 #include "init/ssdk_init.h"
 #define MII_PHYADDR_C45 (1<<30)
 #define HPPE_GCC_UNIPHY_REG_INC 0x100
+#define HPPE_TO_XGMAC_PORT_ID(port_id)  (port_id - 5)
+#define HPPE_TO_GMAC_PORT_ID(port_id) (port_id -1)
+#define HPPE_MUX_PORT1  5
+#define HPPE_MUX_PORT2  6
+#define HPPE_PORT_GMAC_TYPE	1
+#define HPPE_PORT_XGMAC_TYPE	2
 #define HPPE_UNIPHY_INSTANCE0	0
 #define HPPE_UNIPHY_INSTANCE1	1
 #define HPPE_UNIPHY_INSTANCE2	2
diff --git a/include/init/ssdk_init.h b/include/init/ssdk_init.h
index c10c071..be82488 100755
--- a/include/init/ssdk_init.h
+++ b/include/init/ssdk_init.h
@@ -297,7 +297,7 @@
 sw_error_t
 ssdk_hsl_access_mode_set(a_uint32_t dev_id, hsl_access_mode reg_mode);
 
-a_uint32_t ssdk_dt_global_get_mac_mode(void);
+a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t index);
 
 uint32_t
 qca_hppe_gcc_speed_clock1_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
@@ -333,6 +333,17 @@
 a_uint32_t
 qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id);
 
+void
+qca_hppe_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+			a_uint32_t port_id, a_bool_t enable);
+uint32_t
+qca_hppe_gcc_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+uint32_t
+qca_hppe_gcc_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
+			a_uint8_t * reg_data, a_uint32_t len);
+
+
 #ifdef __cplusplus
 }
 #endif                          /* __cplusplus */
diff --git a/src/adpt/adpt.c b/src/adpt/adpt.c
index 9f96a58..04b9563 100755
--- a/src/adpt/adpt.c
+++ b/src/adpt/adpt.c
@@ -340,8 +340,14 @@
 
 			rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MISC);
 			SW_RTN_ON_ERROR(rv);
+
+#ifdef HAWKEYE_CHIP
+			/* uniphy */
+			rv = adpt_hppe_uniphy_init(dev_id);
+			SW_RTN_ON_ERROR(rv);
+#endif
 			break;
-		#endif
+			#endif
 		default:
 			break;
 	}
diff --git a/src/adpt/hppe/Makefile b/src/adpt/hppe/Makefile
index 257c78e..322cfb0 100755
--- a/src/adpt/hppe/Makefile
+++ b/src/adpt/hppe/Makefile
@@ -89,6 +89,10 @@
   SRC_LIST += adpt_hppe_misc.c
 endif
 
+ifeq (TRUE, $(IN_UNIPHY))
+  SRC_LIST += adpt_hppe_uniphy.c
+endif
+
 ifeq (, $(findstring HPPE, $(SUPPORT_CHIP)))
   SRC_LIST=
 endif
diff --git a/src/adpt/hppe/adpt_hppe_portctrl.c b/src/adpt/hppe/adpt_hppe_portctrl.c
index 015a566..764eebd 100755
--- a/src/adpt/hppe/adpt_hppe_portctrl.c
+++ b/src/adpt/hppe/adpt_hppe_portctrl.c
@@ -20,11 +20,21 @@
 #include "sw.h"
 #include "hppe_portctrl_reg.h"
 #include "hppe_portctrl.h"
+#include "hppe_xgportctrl_reg.h"
+#include "hppe_xgportctrl.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_fdb_reg.h"
+#include "hppe_fdb.h"
+#include "hppe_global_reg.h"
+#include "hppe_global.h"
 #include "adpt.h"
 #include "hsl.h"
 #include "hsl_dev.h"
 #include "hsl_port_prop.h"
 #include "hsl_phy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
 
 extern a_bool_t hppe_mac_port_valid_check (fal_port_t port_id);
 
@@ -41,6 +51,272 @@
       return hppe_mac_port_valid_check (port_id);
     }
 }
+static sw_error_t
+__adpt_xgmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_configuration_u xgmac_rx_enable;
+
+	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);
+	if( rv != SW_OK )
+		return rv;
+	*port_rxmac_status = xgmac_rx_enable.bf.re;
+
+	return rv;
+}
+static sw_error_t
+__adpt_gmac_port_rx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* port_rxmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rx_enable;
+
+	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
+	if( rv != SW_OK )
+		return rv;
+	* port_rxmac_status = gmac_rx_enable.bf.rxmac_en;
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_xgmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_configuration_u xgmac_rx_enable;
+
+	memset(&xgmac_rx_enable, 0, sizeof(xgmac_rx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |=  hppe_mac_rx_configuration_get(dev_id, port_id,  &xgmac_rx_enable);
+	if (A_TRUE == enable)
+		 xgmac_rx_enable.bf.re = 1;
+	if (A_FALSE == enable)
+		 xgmac_rx_enable.bf.re= 0;
+	rv |= hppe_mac_rx_configuration_set(dev_id, port_id, &xgmac_rx_enable);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_gmac_port_rx_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rx_enable;
+
+	memset(&gmac_rx_enable, 0, sizeof(gmac_rx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rx_enable);
+	if (A_TRUE == enable)
+		gmac_rx_enable.bf.rxmac_en = 1;
+	if (A_FALSE == enable)
+		gmac_rx_enable.bf.rxmac_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rx_enable);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_xgmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u xgmac_tx_enable;
+
+	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
+	if( rv != SW_OK )
+		return  rv;
+	*port_txmac_status = xgmac_tx_enable.bf.te;
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_tx_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t *port_txmac_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_tx_enable;
+
+	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
+	if( rv != SW_OK )
+		return  rv;
+	*port_txmac_status = gmac_tx_enable.bf.txmac_en;
+
+	return SW_OK;
+}
+static sw_error_t
+__adpt_xgmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u xgmac_tx_enable;
+
+	memset(&xgmac_tx_enable, 0, sizeof(xgmac_tx_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	 rv |=hppe_mac_tx_configuration_get(dev_id, port_id,  &xgmac_tx_enable);
+	 if (A_TRUE == enable)
+		 xgmac_tx_enable.bf.te = 1;
+	 if (A_FALSE == enable)
+		 xgmac_tx_enable.bf.te = 0;
+	 rv |= hppe_mac_tx_configuration_set(dev_id, port_id, &xgmac_tx_enable);
+
+	 return SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_tx_status_set (a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_tx_enable;
+
+	memset(&gmac_tx_enable, 0, sizeof(gmac_tx_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_tx_enable);
+	if (A_TRUE == enable)
+		gmac_tx_enable.bf.txmac_en = 1;
+	if (A_FALSE == enable)
+		gmac_tx_enable.bf.txmac_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_tx_enable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_xgmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;
+
+	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id, &xgmac_txfc_enable);
+	if( rv != SW_OK )
+		return rv;
+	*txfc_status = xgmac_txfc_enable.bf.tfe;
+
+	return  SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* txfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_txfc_enable;
+
+	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
+	if( rv != SW_OK )
+		return rv;
+	*txfc_status = gmac_txfc_enable.bf.tx_flow_en;
+
+	return  SW_OK;
+}
+static sw_error_t
+__adpt_xgmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_q0_tx_flow_ctrl_u xgmac_txfc_enable;
+
+	memset(&xgmac_txfc_enable, 0, sizeof(xgmac_txfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |= hppe_mac_q0_tx_flow_ctrl_get(dev_id, port_id,  &xgmac_txfc_enable);
+	if (A_TRUE == enable)
+		xgmac_txfc_enable.bf.tfe = 1;
+	if (A_FALSE == enable)
+		xgmac_txfc_enable.bf.tfe = 0;
+	 rv |= hppe_mac_q0_tx_flow_ctrl_set(dev_id, port_id,  &xgmac_txfc_enable);
+
+	 return SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,  a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_txfc_enable;
+
+	memset(&gmac_txfc_enable, 0, sizeof(gmac_txfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_txfc_enable);
+	if (A_TRUE == enable)
+		gmac_txfc_enable.bf.tx_flow_en = 1;
+	if (A_FALSE == enable)
+		gmac_txfc_enable.bf.tx_flow_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_txfc_enable);
+
+	return SW_OK;
+}
+static sw_error_t
+__adpt_xgmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id,  a_uint32_t* rxfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;
+
+	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv = hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
+	if(rv != SW_OK)
+		return rv;
+	*rxfc_status = xgmac_rxfc_enable.bf.rfe;
+
+	return  SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_rxfc_status_get(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t* rxfc_status)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rxfc_enable;
+
+	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv = hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
+	if( rv != SW_OK)
+		return rv;
+	*rxfc_status = gmac_rxfc_enable.bf.rx_flow_en;
+
+	return SW_OK;
+}
+static sw_error_t
+__adpt_xgmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_rx_flow_ctrl_u xgmac_rxfc_enable;
+
+	memset(&xgmac_rxfc_enable, 0, sizeof(xgmac_rxfc_enable));
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	rv |= hppe_mac_rx_flow_ctrl_get(dev_id, port_id, &xgmac_rxfc_enable);
+	if (A_TRUE == enable)
+		xgmac_rxfc_enable.bf.rfe= 1;
+	if (A_FALSE == enable)
+		xgmac_rxfc_enable.bf.rfe = 0;
+	rv |= hppe_mac_rx_flow_ctrl_set(dev_id, port_id, &xgmac_rxfc_enable);
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_gmac_port_rxfc_status_set(a_uint32_t dev_id,fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u gmac_rxfc_enable;
+
+	memset(&gmac_rxfc_enable, 0, sizeof(gmac_rxfc_enable));
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	rv |= hppe_mac_enable_get(dev_id, port_id, &gmac_rxfc_enable);
+	if (A_TRUE == enable)
+		gmac_rxfc_enable.bf.rx_flow_en = 1;
+	if (A_FALSE == enable)
+		gmac_rxfc_enable.bf.rx_flow_en = 0;
+	rv |= hppe_mac_enable_set(dev_id, port_id, &gmac_rxfc_enable);
+
+	return SW_OK;
+}
 
 sw_error_t
 adpt_hppe_port_local_loopback_get(a_uint32_t dev_id, fal_port_t port_id,
@@ -149,24 +425,25 @@
 				      a_bool_t * enable)
 {
 	sw_error_t rv = SW_OK;
-	union mac_enable_u mac_enable;
+	a_uint32_t port_rxmac_status = 0, port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 	ADPT_NULL_POINT_CHECK(enable);
 
-	port_id = port_id - 1;
-	rv = hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		 __adpt_gmac_port_rx_status_get( dev_id, port_id, &port_rxmac_status);
+	else
+		return SW_BAD_VALUE;
 
-	if( rv != SW_OK )
-		return rv;
-
-	if (mac_enable.bf.rxmac_en)
+	if (port_rxmac_status)
 		*enable = A_TRUE;
 	else
 		*enable = A_FALSE;
 
-	return SW_OK;
+	return rv;
 }
 
 sw_error_t
@@ -204,20 +481,17 @@
 adpt_hppe_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
 				      a_bool_t enable)
 {
-	union mac_enable_u mac_enable;
+	a_uint32_t port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 
-	port_id = port_id - 1;
-	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
-
-	if (A_TRUE == enable)
-		mac_enable.bf.txmac_en = 1;
-	if (A_FALSE == enable)
-		mac_enable.bf.txmac_en = 0;
-
-	hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_tx_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_tx_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
 
 	return SW_OK;
 }
@@ -416,44 +690,45 @@
 				     a_bool_t * enable)
 {
 	sw_error_t rv = SW_OK;
-	union mac_enable_u mac_enable;
+	a_uint32_t rxfc_status = 0, port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 	ADPT_NULL_POINT_CHECK(enable);
 
-	port_id = port_id - 1;
-	rv = hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_rxfc_status_get( dev_id, port_id, &rxfc_status);
+	else
+		return SW_BAD_VALUE;
 
-	if( rv != SW_OK )
-		return rv;
-
-	if (mac_enable.bf.rx_flow_en)
+	if (rxfc_status)
 		*enable = A_TRUE;
 	else
 		*enable = A_FALSE;
 
-	return SW_OK;
+	return rv;
 }
 
 sw_error_t
 adpt_hppe_port_txfc_status_get(a_uint32_t dev_id, fal_port_t port_id,
 				     a_bool_t * enable)
 {
-	sw_error_t rv = SW_OK;
-	union mac_enable_u mac_enable;
+	a_uint32_t txfc_status = 0, port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 	ADPT_NULL_POINT_CHECK(enable);
 
-	port_id = port_id - 1;
-	rv = hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_txfc_status_get( dev_id, port_id, &txfc_status);
+	else
+		return SW_BAD_VALUE;
 
-	if( rv != SW_OK )
-		return rv;
-
-	if (mac_enable.bf.tx_flow_en)
+	if (txfc_status)
 		*enable = A_TRUE;
 	else
 		*enable = A_FALSE;
@@ -489,6 +764,7 @@
 	return rv;
 
 }
+
 sw_error_t
 adpt_hppe_port_mru_set(a_uint32_t dev_id, fal_port_t port_id,
 		fal_mru_ctrl_t *ctrl)
@@ -540,24 +816,25 @@
 				      a_bool_t * enable)
 {
 	sw_error_t rv = SW_OK;
-	union mac_enable_u mac_enable;
+	a_uint32_t port_txmac_status = 0, port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 	ADPT_NULL_POINT_CHECK(enable);
 
-	port_id = port_id - 1;
-	rv = hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_tx_status_get( dev_id, port_id, &port_txmac_status);
+	else
+		return SW_BAD_VALUE;
 
-	if( rv != SW_OK )
-		return rv;
-
-	if (mac_enable.bf.txmac_en)
+	if (port_txmac_status)
 		*enable = A_TRUE;
 	else
 		*enable = A_FALSE;
 
-	return SW_OK;
+	return rv;
 }
 
 sw_error_t
@@ -1181,20 +1458,17 @@
 adpt_hppe_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
 				     a_bool_t enable)
 {
-	union mac_enable_u mac_enable;
+	a_uint32_t port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 
-	port_id = port_id - 1;
-	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
-
-	if (A_TRUE == enable)
-		mac_enable.bf.tx_flow_en = 1;
-	if (A_FALSE == enable)
-		mac_enable.bf.tx_flow_en = 0;
-
-	hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_txfc_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_txfc_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
 
 	return SW_OK;
 }
@@ -1363,20 +1637,17 @@
 adpt_hppe_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id,
 				      a_bool_t enable)
 {
-	union mac_enable_u mac_enable;
+	a_uint32_t port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 
-	port_id = port_id - 1;
-	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
-
-	if (A_TRUE == enable)
-		mac_enable.bf.rxmac_en = 1;
-	if (A_FALSE == enable)
-		mac_enable.bf.rxmac_en = 0;
-
-	hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_rx_status_set(dev_id, port_id, enable);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_rx_status_set(dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
 
 	return SW_OK;
 }
@@ -1686,20 +1957,17 @@
 adpt_hppe_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id,
 				     a_bool_t enable)
 {
-	union mac_enable_u mac_enable;
+	a_uint32_t port_mac_type;
 
-	memset(&mac_enable, 0, sizeof(mac_enable));
 	ADPT_DEV_ID_CHECK(dev_id);
 
-	port_id = port_id - 1;
-	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
-
-	if (A_TRUE == enable)
-		mac_enable.bf.rx_flow_en = 1;
-	if (A_FALSE == enable)
-		mac_enable.bf.rx_flow_en = 0;
-
-	hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+	port_mac_type =qca_hppe_port_mac_type_get(dev_id, port_id);
+	if(port_mac_type == HPPE_PORT_XGMAC_TYPE)
+		__adpt_xgmac_port_rxfc_status_set( dev_id, port_id, enable);
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+		__adpt_gmac_port_rxfc_status_set( dev_id, port_id, enable);
+	else
+		return SW_BAD_VALUE;
 
 	return SW_OK;
 }
@@ -1866,7 +2134,567 @@
 
 	return hppe_port_in_forward_set(dev_id, port_id, &port_in_forward);
 }
+#ifdef HAWKEYE_CHIP
+static sw_error_t
+adpt_hppe_port_bridge_txmac_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
+{
+	sw_error_t rv = SW_OK;
+	union port_bridge_ctrl_u port_bridge_ctrl = {0};
 
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_bridge_ctrl_get(dev_id, port_id, &port_bridge_ctrl);
+
+	if( rv != SW_OK )
+		return rv;
+
+	if(enable == A_TRUE)
+		port_bridge_ctrl.bf.txmac_en= 1;
+	else
+		port_bridge_ctrl.bf.txmac_en= 0;
+
+	return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
+}
+#endif
+static sw_error_t
+__adpt_hppe_gmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	union mac_speed_u mac_speed;
+
+	memset(&mac_speed, 0, sizeof(mac_speed));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_mac_speed_get(dev_id, port_id, &mac_speed);
+
+	if(FAL_SPEED_10 == speed)
+		mac_speed.bf.mac_speed = 0;
+	else if(FAL_SPEED_100 == speed)
+		mac_speed.bf.mac_speed = 1;
+	else if(FAL_SPEED_1000 == speed)
+		mac_speed.bf.mac_speed = 2;
+
+	rv = hppe_mac_speed_set(dev_id, port_id, &mac_speed);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_xgmac_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	union mac_tx_configuration_u mac_tx_configuration;
+	a_uint32_t mode;
+
+	memset(&mac_tx_configuration, 0, sizeof(mac_tx_configuration));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_XGMAC_PORT_ID(port_id);
+	hppe_mac_tx_configuration_get(dev_id, port_id, &mac_tx_configuration);
+
+	if(FAL_SPEED_1000 == speed)
+	{
+		mac_tx_configuration.bf.uss= 0;
+		mac_tx_configuration.bf.ss= 3;
+	}
+	else if(FAL_SPEED_10000 == speed)
+	{
+		if (port_id == 0)
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE1);
+		}
+		else
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE2);
+		}
+		if (mode == PORT_WRAPPER_USXGMII)
+		{
+			mac_tx_configuration.bf.uss= 1;
+			mac_tx_configuration.bf.ss= 0;
+		}
+		else
+		{
+			mac_tx_configuration.bf.uss= 0;
+			mac_tx_configuration.bf.ss= 0;
+		}
+	}
+	else if(FAL_SPEED_5000 == speed)
+	{
+		mac_tx_configuration.bf.uss= 1;
+		mac_tx_configuration.bf.ss= 1;
+	}
+	else if(FAL_SPEED_2500 == speed)
+	{
+		if (port_id == 0)
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE1);
+		}
+		else
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE2);
+		}
+		if (mode == PORT_WRAPPER_USXGMII)
+		{
+			mac_tx_configuration.bf.uss= 1;
+			mac_tx_configuration.bf.ss= 2;
+		}
+		else
+		{
+			mac_tx_configuration.bf.uss= 0;
+			mac_tx_configuration.bf.ss= 2;
+		}
+	}
+	else if(FAL_SPEED_100 == speed)
+	{
+		mac_tx_configuration.bf.uss= 0;
+		mac_tx_configuration.bf.ss= 3;
+	}
+	else if(FAL_SPEED_10 == speed)
+	{
+		mac_tx_configuration.bf.uss= 0;
+		mac_tx_configuration.bf.ss= 3;
+	}
+
+	rv = hppe_mac_tx_configuration_set(dev_id, port_id, &mac_tx_configuration);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_gmac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	sw_error_t rv = SW_OK;
+	union mac_enable_u mac_enable;
+
+	memset(&mac_enable, 0, sizeof(mac_enable));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	port_id = HPPE_TO_GMAC_PORT_ID(port_id);
+	hppe_mac_enable_get(dev_id, port_id, &mac_enable);
+
+	if (FAL_FULL_DUPLEX == duplex)
+		mac_enable.bf.duplex = 1;
+	else
+		mac_enable.bf.duplex = 0;
+
+	rv = hppe_mac_enable_set(dev_id, port_id, &mac_enable);
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mac_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+	{
+		return rv;
+	}
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+	{
+		rv = __adpt_hppe_gmac_duplex_set(dev_id, port_id, duplex);
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+
+	return rv;
+}
+
+sw_error_t
+adpt_hppe_port_mux_set(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t port_type)
+{
+	sw_error_t rv = SW_OK;
+	union port_mux_ctrl_u port_mux_ctrl;
+	a_uint32_t mode, mode1;
+
+	memset(&port_mux_ctrl, 0, sizeof(port_mux_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	rv = hppe_port_mux_ctrl_get(dev_id, &port_mux_ctrl);
+	port_mux_ctrl.bf.port4_pcs_sel = 1;
+
+	if (port_id == HPPE_MUX_PORT1)
+	{
+		if (port_type == HPPE_PORT_GMAC_TYPE)
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE0);
+			mode1 = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE1);
+			if ((mode == PORT_WRAPPER_PSGMII) || (mode == PORT_WRAPPER_SGMII4_RGMII4))
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = 1;
+				port_mux_ctrl.bf.port5_gmac_sel = 1;
+			}
+			else if (mode1 == PORT_WRAPPER_SGMII0_RGMII4)
+			{
+				port_mux_ctrl.bf.port5_pcs_sel = 2;
+				port_mux_ctrl.bf.port5_gmac_sel = 1;
+			}
+		}
+		else if (port_type == HPPE_PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port5_pcs_sel = 2;
+			port_mux_ctrl.bf.port5_gmac_sel = 0;
+		}
+	}
+	else if (port_id == HPPE_MUX_PORT2)
+	{
+		if (port_type == HPPE_PORT_GMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = 1;
+			port_mux_ctrl.bf.port6_gmac_sel = 1;
+		}
+		else if (port_type == HPPE_PORT_XGMAC_TYPE)
+		{
+			port_mux_ctrl.bf.port6_pcs_sel = 1;
+			port_mux_ctrl.bf.port6_gmac_sel = 0;
+		}
+	}
+	else
+	{
+		return SW_OK;
+	}
+	rv = hppe_port_mux_ctrl_set(dev_id, &port_mux_ctrl);
+
+	return rv;
+}
+sw_error_t
+adpt_hppe_port_mac_speed_set(a_uint32_t dev_id, a_uint32_t port_id,
+				fal_port_speed_t speed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type;
+
+	port_mac_type = qca_hppe_port_mac_type_get(dev_id, port_id);
+	if (port_mac_type == HPPE_PORT_XGMAC_TYPE)
+	{
+		rv = __adpt_hppe_xgmac_speed_set(dev_id, port_id, speed);
+
+	}
+	else if (port_mac_type == HPPE_PORT_GMAC_TYPE)
+	{
+		rv = __adpt_hppe_gmac_speed_set(dev_id, port_id, speed);
+	}
+	else
+	{
+		return SW_BAD_VALUE;
+	}
+	return rv;
+}
+
+#if 0
+static sw_error_t
+adpt_hppe_port_mac_select(a_uint32_t dev_id, a_uint32_t port_id,
+				a_uint32_t speed)
+{
+	sw_error_t rv = SW_OK;
+	a_uint32_t port_mac_type, mode;
+
+	if (port_id == HPPE_MUX_PORT2)
+	{
+		mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE2);
+		if (mode == PORT_WRAPPER_USXGMII)
+		{
+			port_mac_type = __adpt_hppe_port_mac_type_get(port_id);
+			if (speed < FAL_SPEED_1000)
+			{
+				//select gmac;
+				if (port_mac_type != HPPE_PORT_GMAC_TYPE)
+				{
+					rv = adpt_hppe_port_mux_set(0, 0x3b);
+				}
+				hppe_port_type[1] = HPPE_PORT_GMAC_TYPE;
+			}
+			else
+			{
+				//select xgmac;
+				if (port_mac_type != HPPE_PORT_XGMAC_TYPE)
+				{
+					rv = adpt_hppe_port_mux_set(0, 0x1b);
+				}
+				hppe_port_type[1] = HPPE_PORT_XGMAC_TYPE;
+			}
+		}
+	}
+
+	return rv;
+}
+#endif
+#ifdef HAWKEYE_CHIP
+static void
+adpt_hppe_uniphy_psgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+			a_uint32_t port_id)
+{
+	union uniphy_channel0_input_output_4_u uniphy_channel0_input_output_4;
+	union uniphy_channel1_input_output_4_u uniphy_channel1_input_output_4;
+	union uniphy_channel2_input_output_4_u uniphy_channel2_input_output_4;
+	union uniphy_channel3_input_output_4_u uniphy_channel3_input_output_4;
+	union uniphy_channel4_input_output_4_u uniphy_channel4_input_output_4;
+
+	memset(&uniphy_channel0_input_output_4, 0, sizeof(uniphy_channel0_input_output_4));
+	memset(&uniphy_channel1_input_output_4, 0, sizeof(uniphy_channel1_input_output_4));
+	memset(&uniphy_channel2_input_output_4, 0, sizeof(uniphy_channel2_input_output_4));
+	memset(&uniphy_channel3_input_output_4, 0, sizeof(uniphy_channel3_input_output_4));
+	memset(&uniphy_channel4_input_output_4, 0, sizeof(uniphy_channel4_input_output_4));
+
+	if (port_id == 1)
+	{
+		hppe_uniphy_channel0_input_output_4_get(0, uniphy_index, &uniphy_channel0_input_output_4);
+		uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 0;
+		hppe_uniphy_channel0_input_output_4_set(0, uniphy_index, &uniphy_channel0_input_output_4);
+		uniphy_channel0_input_output_4.bf.newaddedfromhere_ch0_adp_sw_rstn = 1;
+		hppe_uniphy_channel0_input_output_4_set(0, uniphy_index, &uniphy_channel0_input_output_4);
+	}
+	else if (port_id == 2)
+	{
+		hppe_uniphy_channel1_input_output_4_get(0, uniphy_index, &uniphy_channel1_input_output_4);
+		uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 0;
+		hppe_uniphy_channel1_input_output_4_set(0, uniphy_index, &uniphy_channel1_input_output_4);
+		uniphy_channel1_input_output_4.bf.newaddedfromhere_ch1_adp_sw_rstn = 1;
+		hppe_uniphy_channel1_input_output_4_set(0, uniphy_index, &uniphy_channel1_input_output_4);
+	}
+	else if (port_id == 3)
+	{
+		hppe_uniphy_channel2_input_output_4_get(0, uniphy_index, &uniphy_channel2_input_output_4);
+		uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 0;
+		hppe_uniphy_channel2_input_output_4_set(0, uniphy_index, &uniphy_channel2_input_output_4);
+		uniphy_channel2_input_output_4.bf.newaddedfromhere_ch2_adp_sw_rstn = 1;
+		hppe_uniphy_channel2_input_output_4_set(0, uniphy_index, &uniphy_channel2_input_output_4);
+	}
+	else if (port_id == 4)
+	{
+		hppe_uniphy_channel3_input_output_4_get(0, uniphy_index, &uniphy_channel3_input_output_4);
+		uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 0;
+		hppe_uniphy_channel3_input_output_4_set(0, uniphy_index, &uniphy_channel3_input_output_4);
+		uniphy_channel3_input_output_4.bf.newaddedfromhere_ch3_adp_sw_rstn = 1;
+		hppe_uniphy_channel3_input_output_4_set(0, uniphy_index, &uniphy_channel3_input_output_4);
+	}
+	else if (port_id == 5)
+	{
+		hppe_uniphy_channel4_input_output_4_get(0, uniphy_index, &uniphy_channel4_input_output_4);
+		uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 0;
+		hppe_uniphy_channel4_input_output_4_set(0, uniphy_index, &uniphy_channel4_input_output_4);
+		uniphy_channel4_input_output_4.bf.newaddedfromhere_ch4_adp_sw_rstn = 1;
+		hppe_uniphy_channel4_input_output_4_set(0, uniphy_index, &uniphy_channel4_input_output_4);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_port_reset(a_uint32_t dev_id, a_uint32_t uniphy_index,
+			a_uint32_t port_id)
+{
+	union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1;
+
+	memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1));
+
+	hppe_vr_xs_pcs_dig_ctrl1_get(0, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+	vr_xs_pcs_dig_ctrl1.bf.usra_rst = 1;
+	hppe_vr_xs_pcs_dig_ctrl1_set(0, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+
+	return;
+}
+static void
+adpt_hppe_uniphy_port_adapter_reset(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index, mode;
+
+	if (port_id < HPPE_MUX_PORT1)
+	{
+		uniphy_index = HPPE_UNIPHY_INSTANCE0;
+		adpt_hppe_uniphy_psgmii_port_reset(0, uniphy_index,
+						port_id);
+	}
+	else
+	{
+		if (port_id == HPPE_MUX_PORT1)
+		{
+			mode = ssdk_dt_global_get_mac_mode(HPPE_UNIPHY_INSTANCE0);
+			if ((mode == PORT_WRAPPER_PSGMII) || (mode == PORT_WRAPPER_SGMII4_RGMII4))
+			{
+				uniphy_index = HPPE_UNIPHY_INSTANCE0;
+				adpt_hppe_uniphy_psgmii_port_reset(0, uniphy_index,
+						port_id);
+				return;
+			}
+			else
+				uniphy_index = HPPE_UNIPHY_INSTANCE1;
+		}
+		else
+			uniphy_index = HPPE_UNIPHY_INSTANCE2;
+
+		mode = ssdk_dt_global_get_mac_mode(uniphy_index);
+
+		if ((mode == PORT_WRAPPER_SGMII_PLUS) || (mode == PORT_WRAPPER_SGMII0_RGMII4))
+		{
+			/* only reset channel 0 */
+			adpt_hppe_uniphy_psgmii_port_reset(0, uniphy_index, 1);
+		}
+		else if (mode == PORT_WRAPPER_USXGMII)
+		{
+			adpt_hppe_uniphy_usxgmii_port_reset(0, uniphy_index,
+						port_id);
+		}
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_speed_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				fal_port_speed_t speed)
+{
+	union sr_mii_ctrl_u sr_mii_ctrl;
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+
+	hppe_sr_mii_ctrl_get(0, uniphy_index, &sr_mii_ctrl);
+	sr_mii_ctrl.bf.duplex_mode = 1;
+	if (speed == FAL_SPEED_10)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_100)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	else if (speed == FAL_SPEED_1000)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 1;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_10000)
+	{
+		sr_mii_ctrl.bf.ss5 = 0;
+		sr_mii_ctrl.bf.ss6 = 1;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	else if (speed == FAL_SPEED_2500)
+	{
+		sr_mii_ctrl.bf.ss5 = 1;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 0;
+	}
+	else if (speed == FAL_SPEED_5000)
+	{
+		sr_mii_ctrl.bf.ss5 = 1;
+		sr_mii_ctrl.bf.ss6 = 0;
+		sr_mii_ctrl.bf.ss13 = 1;
+	}
+	hppe_sr_mii_ctrl_set(0, uniphy_index, &sr_mii_ctrl);
+
+	return;
+}
+static void
+adpt_hppe_uniphy_usxgmii_duplex_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
+				fal_port_duplex_t duplex)
+{
+	union sr_mii_ctrl_u sr_mii_ctrl;
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+
+	hppe_sr_mii_ctrl_get(0, uniphy_index, &sr_mii_ctrl);
+
+	if (duplex == FAL_FULL_DUPLEX)
+		sr_mii_ctrl.bf.duplex_mode = 1;
+	else
+		sr_mii_ctrl.bf.duplex_mode = 0;
+
+	hppe_sr_mii_ctrl_set(0, uniphy_index, &sr_mii_ctrl);
+
+	return;
+}
+sw_error_t
+adpt_hppe_uniphy_usxgmii_autoneg_completed(a_uint32_t dev_id,
+				a_uint32_t uniphy_index)
+{
+	a_uint32_t autoneg_complete = 0, retries = 100;
+	union vr_mii_an_intr_sts_u vr_mii_an_intr_sts;
+
+	memset(&vr_mii_an_intr_sts, 0, sizeof(vr_mii_an_intr_sts));
+
+	// swith uniphy xpcs auto-neg complete and clear interrupt
+	while (autoneg_complete != 0x1) {
+		mdelay(1);
+		if (retries-- == 0)
+		{
+			printk("uniphy autoneg time out!\n");
+			return SW_TIMEOUT;
+		}
+		hppe_vr_mii_an_intr_sts_get(0, uniphy_index, &vr_mii_an_intr_sts);
+		autoneg_complete = vr_mii_an_intr_sts.bf.cl37_ancmplt_intr;
+	}
+
+	vr_mii_an_intr_sts.bf.cl37_ancmplt_intr = 0;
+	hppe_vr_mii_an_intr_sts_set(0, uniphy_index, &vr_mii_an_intr_sts);
+
+	return SW_OK;
+}
+static void
+adpt_hppe_uniphy_speed_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_speed_t speed)
+{
+	a_uint32_t uniphy_index, mode;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = HPPE_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = HPPE_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		adpt_hppe_uniphy_usxgmii_autoneg_completed(0,uniphy_index);
+		/* configure xpcs speed at usxgmii mode */
+		adpt_hppe_uniphy_usxgmii_speed_set(0, uniphy_index, speed);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_duplex_set(a_uint32_t dev_id, a_uint32_t port_id, fal_port_duplex_t duplex)
+{
+	a_uint32_t uniphy_index, mode;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = HPPE_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = HPPE_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		/* adpt_hppe_uniphy_usxgmii_autoneg_completed(0,uniphy_index); */
+		/* configure xpcs duplex at usxgmii mode */
+		adpt_hppe_uniphy_usxgmii_duplex_set(0, uniphy_index, duplex);
+	}
+
+	return;
+}
+static void
+adpt_hppe_uniphy_autoneg_status_check(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	a_uint32_t uniphy_index, mode;
+
+	if (port_id == HPPE_MUX_PORT1)
+		uniphy_index = HPPE_UNIPHY_INSTANCE1;
+	else if (port_id == HPPE_MUX_PORT2)
+		uniphy_index = HPPE_UNIPHY_INSTANCE2;
+
+	mode = ssdk_dt_global_get_mac_mode(uniphy_index);
+	if (mode == PORT_WRAPPER_USXGMII)
+	{
+		adpt_hppe_uniphy_usxgmii_autoneg_completed(0,uniphy_index);;
+	}
+	return;
+}
+#endif
 void adpt_hppe_port_ctrl_func_bitmap_init(a_uint32_t dev_id)
 {
 	adpt_api_t *p_adpt_api = NULL;
@@ -2289,6 +3117,10 @@
 		p_adpt_api->adpt_port_source_filter_set = adpt_hppe_port_source_filter_set;
 	}
 
+	p_adpt_api->adpt_port_mac_mux_set = adpt_hppe_port_mux_set;
+	p_adpt_api->adpt_port_mac_speed_set = adpt_hppe_port_mac_speed_set;
+	p_adpt_api->adpt_port_mac_duplex_set = adpt_hppe_port_mac_duplex_set;
+
 	return SW_OK;
 }
 
diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
new file mode 100755
index 0000000..feb4b63
--- /dev/null
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all copies.
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
+ * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+/**
+ * @defgroup
+ * @{
+ */
+#include "sw.h"
+#include "hppe_uniphy_reg.h"
+#include "hppe_uniphy.h"
+#include "hppe_init.h"
+#include "ssdk_init.h"
+#include "adpt.h"
+
+#ifdef HAWKEYE_CHIP
+static sw_error_t
+__adpt_hppe_uniphy_10g_r_linkup(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value = 0;
+	a_uint32_t retries = 100, linkup = 0;
+
+	union sr_xs_pcs_kr_sts1_u sr_xs_pcs_kr_sts1;
+
+	memset(&sr_xs_pcs_kr_sts1, 0, sizeof(sr_xs_pcs_kr_sts1));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	//wait 10G_R link up  to uniphy;
+	while (linkup != UNIPHY_10GR_LINKUP) {
+		mdelay(1);
+		if (retries-- == 0)
+			return SW_TIMEOUT;
+		reg_value = 0;
+		hppe_sr_xs_pcs_kr_sts1_get(0, uniphy_index, &sr_xs_pcs_kr_sts1);
+		reg_value = sr_xs_pcs_kr_sts1.bf.plu;
+		linkup = (reg_value & UNIPHY_10GR_LINKUP);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_calibration(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value = 0;
+	a_uint32_t retries = 100, calibration_done = 0;
+
+	union uniphy_offset_calib_4_u uniphy_offset_calib_4;
+
+	memset(&uniphy_offset_calib_4, 0, sizeof(uniphy_offset_calib_4));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	//wait calibration done to uniphy;
+	while (calibration_done != UNIPHY_CALIBRATION_DONE) {
+		mdelay(1);
+		if (retries-- == 0)
+		{
+			printk("uniphy callibration time out!\n");
+			return SW_TIMEOUT;
+		}
+		reg_value = 0;
+		hppe_uniphy_offset_calib_4_get(0, uniphy_index, &uniphy_offset_calib_4);
+		reg_value = uniphy_offset_calib_4.bf.mmd1_reg_calibration_done_reg;
+
+		calibration_done = (reg_value & UNIPHY_CALIBRATION_DONE);
+	}
+
+	return SW_OK;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_usxgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value, i;
+	sw_error_t rv = SW_OK;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+	union vr_xs_pcs_dig_ctrl1_u vr_xs_pcs_dig_ctrl1;
+	union vr_mii_an_ctrl_u vr_mii_an_ctrl;
+	union sr_mii_ctrl_u sr_mii_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	memset(&vr_xs_pcs_dig_ctrl1, 0, sizeof(vr_xs_pcs_dig_ctrl1));
+	memset(&vr_mii_an_ctrl, 0, sizeof(vr_mii_an_ctrl));
+	memset(&sr_mii_ctrl, 0, sizeof(sr_mii_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	// disable instance clock;
+	for (i = 1; i < 2; i++)
+	{
+		qca_hppe_gcc_uniphy_port_clock_set(0, uniphy_index,
+			i, A_FALSE);
+	}
+
+	// keep xpcs to reset status;
+	reg_value = 0;
+	qca_hppe_gcc_uniphy_reg_read(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	reg_value |= 0x4;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+
+	// configure uniphy to usxgmii mode;
+	hppe_uniphy_mode_ctrl_get(0, uniphy_index, &uniphy_mode_ctrl);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 1;
+	hppe_uniphy_mode_ctrl_set(0, uniphy_index, &uniphy_mode_ctrl);
+
+	//configure uniphy usxgmii gcc software reset;
+	reg_value = 0;
+	qca_hppe_gcc_uniphy_reg_read(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	reg_value |= HPPE_GCC_UNIPHY_USXGMII_SOFT_RESET;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	// release reset;
+	reg_value &= ~HPPE_GCC_UNIPHY_USXGMII_SOFT_RESET;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+
+	//wait calibration done to uniphy;
+	rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+
+	// enable instance clock;
+	for (i = 1; i < 2; i++)
+	{
+		qca_hppe_gcc_uniphy_port_clock_set(0, uniphy_index,
+			i, A_TRUE);
+	}
+
+	// release xpcs reset status;
+	reg_value = 0;
+	qca_hppe_gcc_uniphy_reg_read(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	reg_value &= ~0x4;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+
+	//wait 10g base_r link up;
+	rv = __adpt_hppe_uniphy_10g_r_linkup(dev_id, uniphy_index);
+
+	//enable uniphy usxgmii;
+	hppe_vr_xs_pcs_dig_ctrl1_get(0, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+	vr_xs_pcs_dig_ctrl1.bf.usxg_en = 1;
+	hppe_vr_xs_pcs_dig_ctrl1_set(0, uniphy_index, &vr_xs_pcs_dig_ctrl1);
+
+	//enable uniphy autoneg complete interrupt and 10M/100M 8-bits MII width;
+	hppe_vr_mii_an_ctrl_get(0, uniphy_index, &vr_mii_an_ctrl);
+	vr_mii_an_ctrl.bf.mii_an_intr_en = 1;
+	vr_mii_an_ctrl.bf.mii_ctrl = 1;
+	hppe_vr_mii_an_ctrl_set(0, uniphy_index, &vr_mii_an_ctrl);
+
+	//enable uniphy autoneg ability and usxgmii 10g speed and full duplex;
+	hppe_sr_mii_ctrl_get(0, uniphy_index, &sr_mii_ctrl);
+	sr_mii_ctrl.bf.an_enable = 1;
+	sr_mii_ctrl.bf.ss5 = 0;
+	sr_mii_ctrl.bf.ss6 = 1;
+	sr_mii_ctrl.bf.ss13 = 1;
+	sr_mii_ctrl.bf.duplex_mode = 1;
+	hppe_sr_mii_ctrl_set(0, uniphy_index, &sr_mii_ctrl);
+
+	return rv;
+}
+
+static sw_error_t
+__adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index)
+{
+	a_uint32_t reg_value, i;
+	sw_error_t rv = SW_OK;
+
+	union uniphy_mode_ctrl_u uniphy_mode_ctrl;
+
+	memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
+	ADPT_DEV_ID_CHECK(dev_id);
+
+	// keep xpcs to reset status;
+	reg_value = 0;
+	qca_hppe_gcc_uniphy_reg_read(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	reg_value |= 0x4;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	// disable instance0 clock;
+	for (i = 1; i < 6; i++)
+	{
+		qca_hppe_gcc_uniphy_port_clock_set(0, uniphy_index,
+			i, A_FALSE);
+	}
+
+	// configure uniphy to Athr mode and psgmii mode
+	hppe_uniphy_mode_ctrl_get(0, uniphy_index, &uniphy_mode_ctrl);
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_athr_csco_mode_25m = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_psgmii_qsgmii = 1;
+	uniphy_mode_ctrl.bf.newaddedfromhere_ch0_qsgmii_sgmii = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sg_mode = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_sgplus_mode = 0;
+	uniphy_mode_ctrl.bf.newaddedfromhere_xpcs_mode = 0;
+	hppe_uniphy_mode_ctrl_set(0, uniphy_index, &uniphy_mode_ctrl);
+
+	//configure uniphy gcc software reset;
+	reg_value = 0;
+	qca_hppe_gcc_uniphy_reg_read(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	reg_value |= HPPE_GCC_UNIPHY_PSGMII_SOFT_RESET;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+	// release reset;
+	reg_value &= ~HPPE_GCC_UNIPHY_PSGMII_SOFT_RESET;
+	qca_hppe_gcc_uniphy_reg_write(0, 0x4 + (uniphy_index * HPPE_GCC_UNIPHY_REG_INC),
+		(a_uint8_t *)&reg_value, 4);
+
+	//wait uniphy calibration done;
+	rv = __adpt_hppe_uniphy_calibration(dev_id, uniphy_index);
+
+	return rv;
+}
+
+
+sw_error_t
+adpt_hppe_uniphy_mode_set(a_uint32_t dev_id, a_uint32_t index, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	if (mode == PORT_WRAPPER_MAX)
+		return SW_OK;
+
+	switch(mode) {
+		case PORT_WRAPPER_PSGMII:
+			rv = __adpt_hppe_uniphy_psgmii_mode_set(dev_id, index);
+			break;
+
+		case PORT_WRAPPER_QSGMII:
+
+			break;
+
+		case PORT_WRAPPER_USXGMII:
+			rv = __adpt_hppe_uniphy_usxgmii_mode_set(dev_id, index);
+			break;
+
+		default:
+			break;
+	}
+	return rv;
+}
+sw_error_t adpt_hppe_uniphy_init(a_uint32_t dev_id)
+{
+	adpt_api_t *p_adpt_api = NULL;
+
+	p_adpt_api = adpt_api_ptr_get(dev_id);
+
+	if(p_adpt_api == NULL)
+		return SW_FAIL;
+
+	p_adpt_api->adpt_uniphy_mode_set = adpt_hppe_uniphy_mode_set;
+
+	return SW_OK;
+}
+#endif
+
+/**
+ * @}
+ */
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index c37b641..bf1a980 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -131,11 +131,26 @@
 void __iomem *gcc_hppe_clock_config1_base = NULL;
 void __iomem *gcc_hppe_clock_config2_base = NULL;
 
-a_uint32_t ssdk_dt_global_get_mac_mode(void)
+a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t index)
 {
-	return ssdk_dt_global.mac_mode;
+	if (index == 0)
+		return ssdk_dt_global.mac_mode;
+	if (index == 1)
+		return ssdk_dt_global.mac_mode1;
+	if (index == 2)
+		return ssdk_dt_global.mac_mode2;
+	return 0;
 }
 
+a_uint32_t hppe_port_type[6] = {0,0,0,0,0,0}; // this variable should be init by ssdk_init
+
+a_uint32_t
+qca_hppe_port_mac_type_get(a_uint32_t dev_id, a_uint32_t port_id)
+{
+	if ((port_id < 1) || (port_id > 6))
+		return 0;
+	return hppe_port_type[port_id - 1];
+}
 phy_identification_t phy_array[] =
 {
 	#ifdef IN_MALIBU_PHY
@@ -1936,14 +1951,77 @@
 
 #ifndef BOARD_AR71XX
 #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
+static void ssdk_dt_parse_mac_mode(ssdk_init_cfg *cfg, struct device_node *switch_node)
+{
+	const __be32 *mac_mode;
+	a_uint32_t len = 0;
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
+	if (!mac_mode)
+		printk("mac mode doesn't exit!\n");
+	else {
+		cfg->mac_mode = be32_to_cpup(mac_mode);
+		printk("mac mode = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.mac_mode = cfg->mac_mode;
+	}
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode1", &len);
+	if(!mac_mode)
+		printk("mac mode1 doesn't exit!\n");
+	else {
+		cfg->mac_mode1 = be32_to_cpup(mac_mode);
+		printk("mac mode1 = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.mac_mode1 = cfg->mac_mode1;
+	}
+
+	mac_mode = of_get_property(switch_node, "switch_mac_mode2", &len);
+	if(!mac_mode)
+		printk("mac mode2 doesn't exit!\n");
+	else {
+		cfg->mac_mode2 = be32_to_cpup(mac_mode);
+		printk("mac mode2 = 0x%x\n", be32_to_cpup(mac_mode));
+		ssdk_dt_global.mac_mode2 = cfg->mac_mode2;
+	}
+
+	return;
+}
+
+static void ssdk_dt_parse_uniphy(void)
+{
+	struct device_node *uniphy_node = NULL;
+	a_uint32_t len = 0;
+	const __be32 *reg_cfg;
+
+	/* read uniphy register base and address space */
+	uniphy_node = of_find_node_by_name(NULL, "ess-uniphy");
+	if (!uniphy_node)
+		printk("ess-uniphy DT doesn't exist!\n");
+	else {
+		printk("ess-uniphy DT exist!\n");
+		reg_cfg = of_get_property(uniphy_node, "reg", &len);
+		if(!reg_cfg)
+			printk("uniphy reg address doesn't exist!\n");
+		else {
+			ssdk_dt_global.uniphyreg_base_addr = be32_to_cpup(reg_cfg);
+			ssdk_dt_global.uniphyreg_size = be32_to_cpup(reg_cfg + 1);
+		}
+		if (of_property_read_string(uniphy_node, "uniphy_access_mode", (const char **)&ssdk_dt_global.uniphy_access_mode))
+			printk("uniphy access mode doesn't exist!\n");
+		else {
+			if(!strcmp(ssdk_dt_global.uniphy_access_mode, "local bus"))
+				ssdk_dt_global.uniphy_reg_access_mode = HSL_REG_LOCAL_BUS;
+		}
+	}
+
+	return;
+}
 static int ssdk_dt_parse(ssdk_init_cfg *cfg)
 {
 	struct device_node *switch_node = NULL,*mdio_node = NULL;
 	struct device_node *psgmii_node = NULL;
 	struct device_node *child = NULL;
-	struct device_node *uniphy_node = NULL;
 	a_uint32_t len = 0,i = 0,j = 0;
-	const __be32 *reg_cfg, *mac_mode,*led_source,*phy_addr;
+	const __be32 *reg_cfg,*led_source,*phy_addr;
 	const __be32 *led_number;
 	a_uint8_t *led_str;
 	a_uint8_t *status_value;
@@ -1993,52 +2071,9 @@
 	else
 		ssdk_dt_global.switch_reg_access_mode = HSL_REG_MDIO;
 
-	mac_mode = of_get_property(switch_node, "switch_mac_mode", &len);
-	if (!mac_mode)
-		printk("%s: error reading device node properties for mac mode\n", switch_node->name);
-	else {
-		cfg->mac_mode = be32_to_cpup(mac_mode);
-		printk("mac mode = %d\n", be32_to_cpup(mac_mode));
-		ssdk_dt_global.mac_mode = cfg->mac_mode;
-	}
+	ssdk_dt_parse_mac_mode(cfg, switch_node);
 
-	mac_mode = of_get_property(switch_node, "switch_mac_mode1", &len);
-	if(!mac_mode)
-		printk("%s: error reading device node properties for mac mode1\n", switch_node->name);
-	else {
-		cfg->mac_mode1 = be32_to_cpup(mac_mode);
-		printk("mac mode1 = %d\n", be32_to_cpup(mac_mode));
-		ssdk_dt_global.mac_mode1 = cfg->mac_mode1;
-	}
-
-	mac_mode = of_get_property(switch_node, "switch_mac_mode2", &len);
-	if(!mac_mode)
-		printk("%s: error reading device node properties for mac mode2\n", switch_node->name);
-	else {
-		cfg->mac_mode2 = be32_to_cpup(mac_mode);
-		printk("mac mode2 = %d\n", be32_to_cpup(mac_mode));
-		ssdk_dt_global.mac_mode2 = cfg->mac_mode2;
-	}
-
-	// read uniphy register base and address space
-	uniphy_node = of_find_node_by_name(NULL, "ess-uniphy");
-	if (!uniphy_node)
-		printk("ess-uniphy DT doesn't exist!\n");
-	else {
-		reg_cfg = of_get_property(uniphy_node, "reg", &len);
-		if(!reg_cfg)
-			printk("%s: error reading device node properties for reg\n", uniphy_node->name);
-		else {
-			ssdk_dt_global.uniphyreg_base_addr = be32_to_cpup(reg_cfg);
-			ssdk_dt_global.uniphyreg_size = be32_to_cpup(reg_cfg + 1);
-        	}
-		if (of_property_read_string(uniphy_node, "uniphy_access_mode", (const char **)&ssdk_dt_global.uniphy_access_mode))
-			printk("%s: error reading device node properties for uniphy_access_mode\n", uniphy_node->name);
-		else {
-			if(!strcmp(ssdk_dt_global.uniphy_access_mode, "local bus"))
-				ssdk_dt_global.uniphy_reg_access_mode = HSL_REG_LOCAL_BUS;
-		}
-	}
+	ssdk_dt_parse_uniphy();
 
 	if (of_property_read_u32(switch_node, "switch_cpu_bmp", &cfg->port_cfg.cpu_bmp)
 		|| of_property_read_u32(switch_node, "switch_lan_bmp", &cfg->port_cfg.lan_bmp)
@@ -2674,6 +2709,29 @@
 		qca_switch_reg_write(0, 0x001034 + (addr_delta*i), (a_uint8_t *)&val, 4);
 	}
 
+#ifdef HAWKEYE_CHIP
+	for(i = 1; i < 7; i++) {
+		hppe_port_type[i - 1] = HPPE_PORT_GMAC_TYPE;
+		fal_port_txmac_status_set (0, i, A_FALSE);
+		fal_port_rxmac_status_set (0, i, A_FALSE);
+		fal_port_rxfc_status_set(0, i, A_TRUE);
+		fal_port_txfc_status_set(0, i, A_TRUE);
+		fal_port_max_frame_size_set(0, i, 1518);
+	}
+
+	for(i = 5; i < 7; i++) {
+		hppe_port_type[i - 1] = HPPE_PORT_XGMAC_TYPE;
+		fal_port_txmac_status_set (0, i, A_FALSE);
+		fal_port_rxmac_status_set (0, i, A_FALSE);
+		fal_port_rxfc_status_set(0, i, A_TRUE);
+		fal_port_txfc_status_set(0, i, A_TRUE);
+		fal_port_max_frame_size_set(0, i, 1518);
+	}
+
+	for(i = 1; i < 7; i++) {
+		hppe_port_type[i -1] = 0;
+	}
+#endif
 	return 0;
 }
 
@@ -3344,7 +3402,7 @@
 
 	return 0;
 }
-static void
+void
 qca_hppe_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
 			a_uint32_t port_id, a_bool_t enable)
 {
@@ -3364,7 +3422,6 @@
 	}
 
 }
-
 sw_error_t
 qca_hppe_xgphy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
                            a_uint32_t reg, a_uint16_t* data)
@@ -3391,6 +3448,129 @@
 
 	return 0;
 }
+static sw_error_t
+qca_hppe_port_mux_set(fal_port_t port_id, a_uint32_t mode1, a_uint32_t mode2)
+{
+	adpt_api_t *p_api;
+	a_uint32_t  mode;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(0));
+
+	if ((NULL == p_api->adpt_port_mac_mux_set) || (NULL == p_api->adpt_port_mac_speed_set) ||
+				(NULL == p_api->adpt_port_mac_duplex_set))
+		return SW_NOT_SUPPORTED;
+
+	if (hppe_port_type[port_id - 1] == HPPE_PORT_GMAC_TYPE)
+	{
+		rv = p_api->adpt_port_mac_speed_set(0, port_id, FAL_SPEED_1000);
+		rv = p_api->adpt_port_mac_duplex_set(0, port_id, FAL_FULL_DUPLEX);
+	}
+	else if (hppe_port_type[port_id - 1] == HPPE_PORT_XGMAC_TYPE)
+	{
+		if (port_id == HPPE_MUX_PORT1)
+			mode = mode1;
+		else if (port_id == HPPE_MUX_PORT2)
+			mode = mode2;
+		if (mode == PORT_WRAPPER_SGMII_PLUS)
+		{
+			rv = p_api->adpt_port_mac_speed_set(0, port_id, FAL_SPEED_2500);
+			rv = p_api->adpt_port_mac_duplex_set(0, port_id, FAL_FULL_DUPLEX);
+		}
+		else
+		{
+			rv = p_api->adpt_port_mac_speed_set(0, port_id, FAL_SPEED_10000);
+			rv = p_api->adpt_port_mac_duplex_set(0, port_id, FAL_FULL_DUPLEX);
+		}
+	}
+	if ((hppe_port_type[port_id - 1] == HPPE_PORT_GMAC_TYPE) ||
+			(hppe_port_type[port_id - 1] == HPPE_PORT_XGMAC_TYPE))
+		rv = p_api->adpt_port_mac_mux_set(0, port_id, hppe_port_type[port_id - 1]);
+
+	return rv;
+}
+
+static sw_error_t
+qca_hppe_port_mac_type_set(a_uint32_t port_id, a_uint32_t mode)
+{
+	sw_error_t rv = SW_OK;
+
+	switch (mode) {
+
+		case PORT_WRAPPER_PSGMII:
+		case PORT_WRAPPER_QSGMII:
+		case PORT_WRAPPER_SGMII0_RGMII4:
+		case PORT_WRAPPER_SGMII1_RGMII4:
+		case PORT_WRAPPER_SGMII4_RGMII4:
+			hppe_port_type[port_id - 1] = HPPE_PORT_GMAC_TYPE;
+			break;
+		case PORT_WRAPPER_SGMII_PLUS:
+		case PORT_WRAPPER_USXGMII:
+		case PORT_WRAPPER_XFI:
+			hppe_port_type[port_id -1] = HPPE_PORT_XGMAC_TYPE;
+			break;
+	}
+	return rv;
+}
+static sw_error_t
+qca_hppe_port_mux_mac_type_init(a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2)
+{
+	a_uint32_t  mode;
+	sw_error_t rv = SW_OK;
+	fal_port_t port_id;
+
+	switch (mode0) {
+		case PORT_WRAPPER_PSGMII:
+			for(port_id = 1; port_id < 6; port_id++) {
+				qca_hppe_port_mac_type_set(port_id, mode0);
+			}
+			break;
+		case PORT_WRAPPER_QSGMII:
+			for(port_id = 1; port_id < 5; port_id++) {
+				qca_hppe_port_mac_type_set(port_id, mode0);
+			}
+			break;
+		case PORT_WRAPPER_SGMII0_RGMII4:
+			qca_hppe_port_mac_type_set(1, mode0);
+			break;
+		case PORT_WRAPPER_SGMII1_RGMII4:
+			qca_hppe_port_mac_type_set(2, mode0);
+			break;
+		case PORT_WRAPPER_SGMII4_RGMII4:
+			qca_hppe_port_mac_type_set(5, mode0);
+			break;
+	}
+
+	qca_hppe_port_mac_type_set(5, mode1);
+	qca_hppe_port_mac_type_set(6, mode2);
+
+	for (port_id = 1; port_id < 7; port_id++) {
+		qca_hppe_port_mux_set(port_id,mode1, mode2);
+	}
+
+	return rv;
+}
+
+static sw_error_t
+qca_hppe_interface_mode_init(a_uint32_t mode0, a_uint32_t mode1, a_uint32_t mode2)
+{
+
+	adpt_api_t *p_api;
+	sw_error_t rv = SW_OK;
+
+	SW_RTN_ON_NULL(p_api = adpt_api_ptr_get(0));
+
+	if (NULL == p_api->adpt_uniphy_mode_set)
+		return SW_NOT_SUPPORTED;
+
+	rv = p_api->adpt_uniphy_mode_set(0, HPPE_UNIPHY_INSTANCE0, mode0);
+	rv = p_api->adpt_uniphy_mode_set(0, HPPE_UNIPHY_INSTANCE1, mode1);
+	rv = p_api->adpt_uniphy_mode_set(0, HPPE_UNIPHY_INSTANCE2, mode2);
+
+	rv = qca_hppe_port_mux_mac_type_init(mode0, mode1, mode2);
+
+	return rv;
+}
 #endif
 
 uint32_t
@@ -3501,7 +3681,7 @@
 static int
 qca_hppe_hw_init(ssdk_init_cfg *cfg)
 {
-	a_uint32_t val;
+	a_uint32_t val, i = 0;
 	void __iomem *ppe_gpio_base;
 
 
@@ -3539,12 +3719,40 @@
 	qca_hppe_shaper_hw_init();
 	qca_hppe_flow_hw_init();
 
-	qca_hppe_xgmac_hw_init();
-	printk("hppe xgmac init success\n");
 #ifdef HAWKEYE_CHIP
 	qca_hppe_gcc_uniphy_init();
 
 	qca_hppe_gcc_speed_clock_init();
+
+	qca_hppe_interface_mode_init(cfg->mac_mode, cfg->mac_mode1,
+				cfg->mac_mode2);
+#else
+#ifndef ESS_ONLY_FPGA
+	qca_hppe_xgmac_hw_init();
+	printk("hppe xgmac init success\n");
+
+	for(i = 0; i < 4; i++) {
+		hppe_port_type[i] = HPPE_PORT_GMAC_TYPE;
+	}
+	for(i = 4; i < 6; i++) {
+		hppe_port_type[i] = HPPE_PORT_XGMAC_TYPE;
+	}
+
+	ssdk_dt_global.mac_mode = PORT_WRAPPER_QSGMII;
+	ssdk_dt_global.mac_mode1 = PORT_WRAPPER_USXGMII;
+	ssdk_dt_global.mac_mode2 = PORT_WRAPPER_USXGMII;
+
+#else
+
+	for(i = 0; i < 5; i++) {
+		hppe_port_type[i] = HPPE_PORT_GMAC_TYPE;
+	}
+	hppe_port_type[i] = HPPE_PORT_XGMAC_TYPE;
+
+	ssdk_dt_global.mac_mode = PORT_WRAPPER_PSGMII;
+	ssdk_dt_global.mac_mode1 = PORT_WRAPPER_MAX;
+	ssdk_dt_global.mac_mode2 = PORT_WRAPPER_USXGMII;
+#endif
 #endif
 	return 0;
 }
diff --git a/src/ref/ref_misc.c b/src/ref/ref_misc.c
index 3b8ee2f..1993479 100755
--- a/src/ref/ref_misc.c
+++ b/src/ref/ref_misc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2017, The Linux Foundation. All rights reserved.
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
  * above copyright notice and this permission notice appear in all copies.
@@ -106,7 +106,7 @@
 	rv += qca_ar8327_sw_hw_apply(dev);
 	priv->init = false;
 
-	mac_mode = ssdk_dt_global_get_mac_mode();
+	mac_mode = ssdk_dt_global_get_mac_mode(0);
 	/* set mac5 flowcontol force for RGMII */
 	if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
 		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)) {
diff --git a/src/ref/ref_port_ctrl.c b/src/ref/ref_port_ctrl.c
index 93a610a..6c36ba2 100755
--- a/src/ref/ref_port_ctrl.c
+++ b/src/ref/ref_port_ctrl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012, 2016,  The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2016-2017,  The Linux Foundation. All rights reserved.
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
  * above copyright notice and this permission notice appear in all copies.
@@ -233,7 +233,7 @@
 {
 	a_uint32_t rgmii_mode;
 
-	rgmii_mode = ssdk_dt_global_get_mac_mode();
+	rgmii_mode = ssdk_dt_global_get_mac_mode(0);
 
 	if(((rgmii_mode == PORT_WRAPPER_SGMII0_RGMII5) ||
 		(rgmii_mode == PORT_WRAPPER_SGMII1_RGMII5)) && (port_id == 5))
@@ -471,7 +471,7 @@
 {
 	a_uint32_t mac_mode;
 
-	mac_mode = ssdk_dt_global_get_mac_mode();
+	mac_mode = ssdk_dt_global_get_mac_mode(0);
 
 	if( port_id >= AR8327_NUM_PORTS-1 || port_id < 1)
 		return A_FALSE;
@@ -694,7 +694,7 @@
 	a_uint16_t phy_spec_status, phy_link_status;
 	a_uint32_t speed, duplex;
 
-	mac_mode = ssdk_dt_global_get_mac_mode();
+	mac_mode = ssdk_dt_global_get_mac_mode(0);
 
 	if ((mac_mode == PORT_WRAPPER_SGMII0_RGMII5)
 		||(mac_mode == PORT_WRAPPER_SGMII1_RGMII5)