Merge "[qca-ssdk]: [ReducedProfile]: Add the IN_XX macros for HPPE"
diff --git a/include/fal/fal_acl.h b/include/fal/fal_acl.h
index f0f8b88..8ac9c2f 100755
--- a/include/fal/fal_acl.h
+++ b/include/fal/fal_acl.h
@@ -507,6 +507,9 @@
a_uint8_t cpu_code;/*cpu code*/
a_uint64_t match_bytes;/*rule match bytes counter*/
/*Only IPQ807x support End*/
+
+ /*new add acl action for IPQ60xx*/
+ a_uint8_t dscp_mask;/*modify dscp mask,IPQ60xx support*/
} fal_acl_rule_t;
diff --git a/include/fal/fal_fdb.h b/include/fal/fal_fdb.h
index a4f6e72..791dba9 100755
--- a/include/fal/fal_fdb.h
+++ b/include/fal/fal_fdb.h
@@ -154,14 +154,11 @@
fal_fdb_entry_flush(a_uint32_t dev_id, a_uint32_t flag);
-#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_entry_del_byport(a_uint32_t dev_id, a_uint32_t port_id, a_uint32_t flag);
-
sw_error_t
fal_fdb_entry_del_bymac(a_uint32_t dev_id, const fal_fdb_entry_t *entry);
-#endif
sw_error_t
fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry);
@@ -170,11 +167,11 @@
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_entry_getnext(a_uint32_t dev_id, fal_fdb_entry_t * entry);
-
+#endif
sw_error_t
fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry);
-#endif
+
sw_error_t
fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable);
@@ -183,32 +180,38 @@
#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable);
-
+#endif
sw_error_t
fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, fal_fwd_cmd_t cmd);
-
+#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable, fal_fwd_cmd_t *cmd);
+#endif
sw_error_t
fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable, fal_fwd_cmd_t cmd);
+#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t *enable, fal_fwd_cmd_t *cmd);
+#endif
sw_error_t
fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
+#endif
sw_error_t
fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable);
+#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable);
@@ -305,10 +308,10 @@
sw_error_t
fal_fdb_port_maclimit_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, fal_maclimit_ctrl_t * maclimit_ctrl);
+#endif
sw_error_t
fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag);
-#endif
#define fal_fdb_add fal_fdb_entry_add
#define fal_fdb_del_all fal_fdb_entry_flush
diff --git a/include/fal/fal_qos.h b/include/fal/fal_qos.h
index a2b4fc8..8e5d429 100755
--- a/include/fal/fal_qos.h
+++ b/include/fal/fal_qos.h
@@ -264,76 +264,71 @@
sw_error_t
fal_qos_port_mode_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_bool_t * enable);
-#endif
+
sw_error_t
fal_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_uint32_t pri);
-#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_mode_pri_get(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_uint32_t * pri);
-#endif
+
sw_error_t
fal_qos_port_default_up_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t up);
-#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_default_up_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * up);
-#endif
+
sw_error_t
fal_qos_port_sch_mode_set(a_uint32_t dev_id, a_uint32_t port_id,
fal_sch_mode_t mode, const a_uint32_t weight[]);
-#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_sch_mode_get(a_uint32_t dev_id, a_uint32_t port_id,
fal_sch_mode_t * mode, a_uint32_t weight[]);
-#endif
+
sw_error_t
fal_qos_port_default_spri_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t spri);
-#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_default_spri_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * spri);
-#endif
+
sw_error_t
fal_qos_port_default_cpri_set(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t cpri);
-#ifndef IN_QOS_MINI
sw_error_t
fal_qos_port_default_cpri_get(a_uint32_t dev_id, fal_port_t port_id,
a_uint32_t * cpri);
-#endif
+
sw_error_t
fal_qos_port_force_spri_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
-#ifndef IN_QOS_MINI
+
sw_error_t
fal_qos_port_force_spri_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t* enable);
-#endif
+
sw_error_t
fal_qos_port_force_cpri_status_set(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t enable);
-#ifndef IN_QOS_MINI
+
sw_error_t
fal_qos_port_force_cpri_status_get(a_uint32_t dev_id, fal_port_t port_id,
a_bool_t* enable);
-#endif
+
sw_error_t
fal_qos_queue_remark_table_set(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t tbl_id, a_bool_t enable);
-#ifndef IN_QOS_MINI
+
sw_error_t
fal_qos_queue_remark_table_get(a_uint32_t dev_id, fal_port_t port_id,
fal_queue_t queue_id, a_uint32_t * tbl_id, a_bool_t * enable);
diff --git a/include/hsl/hppe/hppe_acl_reg.h b/include/hsl/hppe/hppe_acl_reg.h
index c273a26..db18ea4 100755
--- a/include/hsl/hppe/hppe_acl_reg.h
+++ b/include/hsl/hppe/hppe_acl_reg.h
@@ -828,7 +828,9 @@
a_uint32_t cpu_code_en:1;
a_uint32_t cpu_code:8;
a_uint32_t metadata_en:1;
- a_uint32_t _reserved0:14;
+ a_uint32_t dscp_tc_mask:8;
+ a_uint32_t qos_res_prec:3;
+ a_uint32_t _reserved0:3;
};
union ipo_action_u {
diff --git a/include/hsl/phy/aquantia_phy.h b/include/hsl/phy/aquantia_phy.h
index b409166..71930d1 100755
--- a/include/hsl/phy/aquantia_phy.h
+++ b/include/hsl/phy/aquantia_phy.h
@@ -327,7 +327,7 @@
AQUANTIA_PHY_COPPER_PAGES = 1
/**< copper pages */
} AQUANTIA_PHY_reg_pages_t;
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
aquantia_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
a_bool_t enable);
@@ -341,7 +341,7 @@
a_uint32_t mdi_pair,
fal_cable_status_t * cable_status,
a_uint32_t * cable_len);
-
+#endif
sw_error_t
aquantia_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
fal_port_duplex_t duplex);
@@ -377,7 +377,7 @@
a_bool_t
aquantia_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
aquantia_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t intr_mask_flag);
@@ -385,7 +385,7 @@
sw_error_t
aquantia_phy_intr_mask_get (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t * intr_mask_flag);
-
+#endif
int aquantia_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
#ifdef __cplusplus
diff --git a/include/hsl/phy/malibu_phy.h b/include/hsl/phy/malibu_phy.h
index 397107d..220420a 100755
--- a/include/hsl/phy/malibu_phy.h
+++ b/include/hsl/phy/malibu_phy.h
@@ -571,7 +571,7 @@
MALIBU_PHY_COPPER_PAGES = 1
/**< copper pages */
} malibu_phy_reg_pages_t;
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
malibu_phy_set_powersave (a_uint32_t dev_id, a_uint32_t phy_id,
a_bool_t enable);
@@ -593,7 +593,7 @@
a_uint32_t mdi_pair,
fal_cable_status_t * cable_status,
a_uint32_t * cable_len);
-
+#endif
sw_error_t
malibu_phy_set_duplex (a_uint32_t dev_id, a_uint32_t phy_id,
fal_port_duplex_t duplex);
@@ -628,7 +628,7 @@
a_uint32_t * autoneg);
a_bool_t malibu_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
malibu_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t intr_mask_flag);
@@ -652,11 +652,11 @@
sw_error_t
malibu_phy_show_counter (a_uint32_t dev_id, a_uint32_t phy_id,
fal_port_counter_info_t * counter_info);
-
+#endif
sw_error_t
malibu_phy_get_8023az(a_uint32_t dev_id, a_uint32_t phy_id,
a_bool_t * enable);
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
malibu_phy_set_8023az(a_uint32_t dev_id, a_uint32_t phy_id,
a_bool_t enable);
@@ -664,7 +664,7 @@
sw_error_t
malibu_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t *phy_data);
-
+#endif
int malibu_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
#ifdef __cplusplus
diff --git a/include/hsl/phy/qca803x_phy.h b/include/hsl/phy/qca803x_phy.h
index 94d7fc5..33b669e 100755
--- a/include/hsl/phy/qca803x_phy.h
+++ b/include/hsl/phy/qca803x_phy.h
@@ -382,7 +382,7 @@
a_uint32_t * autoneg);
a_bool_t qca803x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
qca803x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t intr_mask_flag);
@@ -398,7 +398,7 @@
sw_error_t
qca803x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t *phy_data);
-
+#endif
int qca803x_phy_init(a_uint32_t dev_id, a_uint32_t port_bmp);
#ifdef __cplusplus
diff --git a/include/hsl/phy/qca808x_phy.h b/include/hsl/phy/qca808x_phy.h
index 3a9c2f9..a175125 100755
--- a/include/hsl/phy/qca808x_phy.h
+++ b/include/hsl/phy/qca808x_phy.h
@@ -478,7 +478,7 @@
a_uint32_t * autoneg);
a_bool_t qca808x_phy_autoneg_status (a_uint32_t dev_id, a_uint32_t phy_id);
-
+#ifndef IN_PORTCONTROL_MINI
sw_error_t
qca808x_phy_intr_mask_set (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t intr_mask_flag);
@@ -490,7 +490,7 @@
sw_error_t
qca808x_phy_intr_status_get (a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t * intr_status_flag);
-
+#endif
sw_error_t
qca808x_phy_get_phy_id(a_uint32_t dev_id, a_uint32_t phy_id,
a_uint32_t *phy_data);
diff --git a/src/adpt/hppe/adpt_hppe_acl.c b/src/adpt/hppe/adpt_hppe_acl.c
index 729ff4f..c9b89f6 100755
--- a/src/adpt/hppe/adpt_hppe_acl.c
+++ b/src/adpt/hppe/adpt_hppe_acl.c
@@ -19,6 +19,7 @@
*/
#include "sw.h"
#include "adpt.h"
+#include "adpt_hppe.h"
#include "hppe_acl_reg.h"
#include "hppe_acl.h"
@@ -998,7 +999,8 @@
rule->dest_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port;
rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff;
- rule->dest_ip6_mask.ul[3] = ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
+ rule->dest_ip6_mask.ul[3] =
+ ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff;
}
else if(ip_bit_range == 1)
@@ -1012,7 +1014,8 @@
rule->dest_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000;
rule->dest_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
rule->dest_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000;
- rule->dest_ip6_mask.ul[1] = ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+ rule->dest_ip6_mask.ul[1] =
+ ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
}
else if(ip_bit_range == 2)
{
@@ -1020,8 +1023,10 @@
|| ipv6rule_mask->ip_ext_2_mask)
{
FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_DIP);
- rule->dest_ip6_val.ul[0] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
- rule->dest_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+ rule->dest_ip6_val.ul[0] =
+ ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
+ rule->dest_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|
+ ipv6rule_mask->ip_ext_1_mask;
}
if(ipv6rule_mask->ip_port_mask)
{
@@ -1066,7 +1071,8 @@
}
rule->src_ip6_val.ul[3] = ipv6rule->ip_ext_1<<16|ipv6rule->ip_port;
rule->src_ip6_val.ul[2] |= (ipv6rule->ip_ext_2)&0xffff;
- rule->src_ip6_mask.ul[3] = ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
+ rule->src_ip6_mask.ul[3] =
+ ipv6rule_mask->ip_ext_1_mask<<16|ipv6rule_mask->ip_port_mask;
rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_ext_2_mask)&0xffff;
}
else if(ip_bit_range == 1)
@@ -1080,7 +1086,8 @@
rule->src_ip6_val.ul[2] |= (ipv6rule->ip_port<<16)&0xffff0000;
rule->src_ip6_val.ul[1] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
rule->src_ip6_mask.ul[2] |= (ipv6rule_mask->ip_port_mask<<16)&0xffff0000;
- rule->src_ip6_mask.ul[1] = ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+ rule->src_ip6_mask.ul[1] =
+ ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
}
else if(ip_bit_range == 2)
{
@@ -1089,7 +1096,8 @@
{
FAL_FIELD_FLG_SET(rule->field_flg, FAL_ACL_FIELD_IP6_SIP);
rule->src_ip6_val.ul[0] = ipv6rule->ip_ext_2<<16|ipv6rule->ip_ext_1;
- rule->src_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|ipv6rule_mask->ip_ext_1_mask;
+ rule->src_ip6_mask.ul[0] = ipv6rule_mask->ip_ext_2_mask<<16|
+ ipv6rule_mask->ip_ext_1_mask;
}
if(ipv6rule_mask->ip_port_mask)
{
@@ -1446,6 +1454,12 @@
{
FAL_ACTION_FLG_SET(rule->action_flg, FAL_ACL_ACTION_REMARK_DSCP);
rule->dscp = hw_act->bf.dscp_tc;
+#if defined(CPPE)
+ if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+ {
+ rule->dscp_mask = hw_act->bf.dscp_tc_mask;
+ }
+#endif
}
if(hw_act->bf.int_dp_change_en == 1)
{
@@ -2906,6 +2920,12 @@
{
hw_act->bf.dscp_tc_change_en = 1;
hw_act->bf.dscp_tc = rule->dscp;
+#if defined(CPPE)
+ if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
+ {
+ hw_act->bf.dscp_tc_mask = rule->dscp_mask;
+ }
+#endif
}
if(FAL_ACTION_FLG_TST(rule->action_flg, FAL_ACL_ACTION_INT_DP))
{
diff --git a/src/adpt/hppe/adpt_hppe_fdb.c b/src/adpt/hppe/adpt_hppe_fdb.c
index d041ac5..2d8a635 100755
--- a/src/adpt/hppe/adpt_hppe_fdb.c
+++ b/src/adpt/hppe/adpt_hppe_fdb.c
@@ -523,7 +523,7 @@
return rv;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_next(a_uint32_t dev_id, fal_fdb_entry_t * entry)
{
@@ -541,7 +541,7 @@
return rv;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_add(a_uint32_t dev_id, const fal_fdb_entry_t * entry)
{
@@ -673,7 +673,7 @@
return SW_OK;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_transfer(a_uint32_t dev_id, fal_port_t old_port, fal_port_t new_port,
a_uint32_t fid, fal_fdb_op_t * option)
@@ -731,7 +731,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_find(a_uint32_t dev_id, fal_fdb_entry_t * entry)
{
@@ -783,7 +783,7 @@
*iterator = entry_index + 1;
return SW_OK;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_age_time_set(a_uint32_t dev_id, a_uint32_t * time)
{
@@ -818,7 +818,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_extend_first(a_uint32_t dev_id, fal_fdb_op_t * option,
fal_fdb_entry_t * entry)
@@ -870,7 +870,7 @@
return hppe_l2_global_conf_set(dev_id, &l2_global_conf);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_learn_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
{
@@ -1070,7 +1070,7 @@
return rv;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
@@ -1089,7 +1089,7 @@
return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_port_learn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable)
{
@@ -1108,7 +1108,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_port_newaddr_lrn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
{
@@ -1128,7 +1128,7 @@
return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_port_newaddr_lrn_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
{
@@ -1150,7 +1150,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_port_stamove_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
{
@@ -1170,7 +1170,7 @@
return hppe_port_bridge_ctrl_set(dev_id, port_id, &port_bridge_ctrl);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_port_stamove_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
{
@@ -1249,7 +1249,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_age_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
{
@@ -1267,7 +1267,7 @@
return hppe_l2_global_conf_set(dev_id, &l2_global_conf);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
adpt_hppe_fdb_age_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
{
@@ -1286,7 +1286,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_fdb_del_by_fid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
{
@@ -1428,8 +1428,10 @@
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETFIRST))
p_adpt_api->adpt_fdb_first = adpt_hppe_fdb_first;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT))
p_adpt_api->adpt_fdb_next = adpt_hppe_fdb_next;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_ADD))
p_adpt_api->adpt_fdb_add = adpt_hppe_fdb_add;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_DEL_BYPORT))
@@ -1438,22 +1440,27 @@
p_adpt_api->adpt_fdb_del_by_mac = adpt_hppe_fdb_del_by_mac;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_FLUSH))
p_adpt_api->adpt_fdb_del_all = adpt_hppe_fdb_del_all;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_UPDATE_BYPORT))
p_adpt_api->adpt_fdb_transfer = adpt_hppe_fdb_transfer;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_SEARCH))
p_adpt_api->adpt_fdb_find = adpt_hppe_fdb_find;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_GETNEXT_BYINDEX))
p_adpt_api->adpt_fdb_iterate = adpt_hppe_fdb_iterate;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_SET))
p_adpt_api->adpt_fdb_age_time_set = adpt_hppe_fdb_age_time_set;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_TIME_GET))
p_adpt_api->adpt_fdb_age_time_get = adpt_hppe_fdb_age_time_get;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETFIRST))
p_adpt_api->adpt_fdb_extend_first = adpt_hppe_fdb_extend_first;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_ENTRY_EXTEND_GETNEXT))
p_adpt_api->adpt_fdb_extend_next = adpt_hppe_fdb_extend_next;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_SET))
p_adpt_api->adpt_fdb_learn_ctrl_set = adpt_hppe_fdb_learn_ctrl_set;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_LEARNING_CTRL_GET))
p_adpt_api->adpt_fdb_learn_ctrl_get = adpt_hppe_fdb_learn_ctrl_get;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_LIMIT_SET))
@@ -1464,16 +1471,22 @@
p_adpt_api->adpt_fdb_port_add = adpt_hppe_fdb_port_add;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_DEL))
p_adpt_api->adpt_fdb_port_del = adpt_hppe_fdb_port_del;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_SET))
p_adpt_api->adpt_fdb_port_learn_set = adpt_hppe_fdb_port_learn_set;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARN_GET))
p_adpt_api->adpt_fdb_port_learn_get = adpt_hppe_fdb_port_learn_get;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_SET))
p_adpt_api->adpt_fdb_port_newaddr_lrn_set = adpt_hppe_fdb_port_newaddr_lrn_set;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNING_CTRL_GET))
p_adpt_api->adpt_fdb_port_newaddr_lrn_get = adpt_hppe_fdb_port_newaddr_lrn_get;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_SET))
p_adpt_api->adpt_fdb_port_stamove_set = adpt_hppe_fdb_port_stamove_set;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_STAMOVE_CTRL_GET))
p_adpt_api->adpt_fdb_port_stamove_get = adpt_hppe_fdb_port_stamove_get;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_LEARNED_MAC_COUNTER_GET))
@@ -1482,14 +1495,17 @@
p_adpt_api->adpt_port_fdb_learn_exceed_cmd_set = adpt_hppe_port_fdb_learn_exceed_cmd_set;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_PORT_FDB_LEARN_EXCEED_CMD_GET))
p_adpt_api->adpt_port_fdb_learn_exceed_cmd_get = adpt_hppe_port_fdb_learn_exceed_cmd_get;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_SET))
p_adpt_api->adpt_fdb_age_ctrl_set = adpt_hppe_fdb_age_ctrl_set;
+#ifndef IN_FDB_MINI
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_AGING_CTRL_GET))
p_adpt_api->adpt_fdb_age_ctrl_get = adpt_hppe_fdb_age_ctrl_get;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_SET))
p_adpt_api->adpt_fdb_port_maclimit_ctrl_set = adpt_hppe_fdb_port_maclimit_ctrl_set;
if (p_adpt_api->adpt_fdb_func_bitmap[0] & (1 << FUNC_FDB_PORT_MACLIMIT_CTRL_GET))
p_adpt_api->adpt_fdb_port_maclimit_ctrl_get = adpt_hppe_fdb_port_maclimit_ctrl_get;
+#endif
if (p_adpt_api->adpt_fdb_func_bitmap[1] & (1 << (FUNC_FDB_DEL_BY_FID % 32)))
p_adpt_api->adpt_fdb_del_by_fid = adpt_hppe_fdb_del_by_fid;
diff --git a/src/adpt/hppe/adpt_hppe_misc.c b/src/adpt/hppe/adpt_hppe_misc.c
index b6b0d77..0d396d1 100755
--- a/src/adpt/hppe/adpt_hppe_misc.c
+++ b/src/adpt/hppe/adpt_hppe_misc.c
@@ -34,6 +34,7 @@
#define VP_PORT_MIN_ID 64
#define PHYSICAL_PORT_MAX_ID 7
+#ifndef IN_MISC_MINI
char cpucode[][85] = {
"Forwarding to CPU",
"Unkown L2 protocol exception redirect/copy to CPU",
@@ -951,7 +952,7 @@
return SW_OK;
}
-
+#endif
sw_error_t adpt_hppe_misc_init(a_uint32_t dev_id)
{
adpt_api_t *p_adpt_api = NULL;
@@ -960,13 +961,13 @@
if(p_adpt_api == NULL)
return SW_FAIL;
-
+#ifndef IN_MISC_MINI
p_adpt_api->adpt_debug_port_counter_enable = adpt_hppe_debug_port_counter_enable;
p_adpt_api->adpt_debug_port_counter_status_get = adpt_hppe_debug_port_counter_status_get;
p_adpt_api->adpt_debug_counter_set = adpt_hppe_debug_counter_set;
p_adpt_api->adpt_debug_counter_get = adpt_hppe_debug_counter_get;
-
+#endif
return SW_OK;
}
diff --git a/src/adpt/hppe/adpt_hppe_qos.c b/src/adpt/hppe/adpt_hppe_qos.c
index c60137c..289d658 100755
--- a/src/adpt/hppe/adpt_hppe_qos.c
+++ b/src/adpt/hppe/adpt_hppe_qos.c
@@ -72,7 +72,7 @@
return SW_OK;
}
-
+#ifndef IN_QOS_MINI
sw_error_t
adpt_hppe_qos_port_mode_pri_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_mode_t mode, a_uint32_t pri)
@@ -118,7 +118,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_qos_port_pri_set(a_uint32_t dev_id, fal_port_t port_id,
fal_qos_pri_precedence_t *pri)
@@ -689,7 +689,7 @@
tdm_depth_cfg.bf.tdm_depth = tick_num;
return hppe_tdm_depth_cfg_set(dev_id, &tdm_depth_cfg);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
adpt_hppe_tdm_tick_num_get(a_uint32_t dev_id, a_uint32_t *tick_num)
{
@@ -703,7 +703,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_port_scheduler_cfg_reset(a_uint32_t dev_id,
fal_port_t port_id)
@@ -764,7 +764,7 @@
psch_tdm_cfg.bf.des_port = cfg->de_scheduler_port;
return hppe_psch_tdm_cfg_tbl_set(dev_id, tick_index, &psch_tdm_cfg);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
adpt_hppe_port_scheduler_cfg_get(a_uint32_t dev_id,
a_uint32_t tick_index,
@@ -782,7 +782,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
adpt_hppe_scheduler_dequeue_ctrl_get(a_uint32_t dev_id,
a_uint32_t queue_id,
@@ -973,20 +973,26 @@
p_adpt_api->adpt_ring_queue_map_get = adpt_hppe_ring_queue_map_get;
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_SET))
p_adpt_api->adpt_tdm_tick_num_set = adpt_hppe_tdm_tick_num_set;
+#ifndef IN_QOS_MINI
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_TDM_TICK_NUM_GET))
p_adpt_api->adpt_tdm_tick_num_get = adpt_hppe_tdm_tick_num_get;
+#endif
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_SET))
p_adpt_api->adpt_port_scheduler_cfg_set = adpt_hppe_port_scheduler_cfg_set;
+#ifndef IN_QOS_MINI
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_PORT_SCHEDULER_CFG_GET))
p_adpt_api->adpt_port_scheduler_cfg_get = adpt_hppe_port_scheduler_cfg_get;
+#endif
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_GET))
p_adpt_api->adpt_scheduler_dequeue_ctrl_get = adpt_hppe_scheduler_dequeue_ctrl_get;
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_SCHEDULER_DEQUEUE_CTRL_SET))
p_adpt_api->adpt_scheduler_dequeue_ctrl_set = adpt_hppe_scheduler_dequeue_ctrl_set;
+#ifndef IN_QOS_MINI
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_GET))
p_adpt_api->adpt_qos_port_mode_pri_get = adpt_hppe_qos_port_mode_pri_get;
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_MODE_PRI_SET))
p_adpt_api->adpt_qos_port_mode_pri_set = adpt_hppe_qos_port_mode_pri_set;
+#endif
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_CFG_RESET))
p_adpt_api->adpt_port_scheduler_cfg_reset = adpt_hppe_port_scheduler_cfg_reset;
if (p_adpt_api->adpt_qos_func_bitmap & (1 << FUNC_QOS_PORT_SCHEDULER_RESOURCE_GET))
diff --git a/src/fal/fal_fdb.c b/src/fal/fal_fdb.c
index 520a122..02dc74a 100755
--- a/src/fal/fal_fdb.c
+++ b/src/fal/fal_fdb.c
@@ -76,7 +76,6 @@
return rv;
}
-#ifndef IN_FDB_MINI
static sw_error_t
_fal_fdb_entry_del_byport(a_uint32_t dev_id, fal_port_t port_id, a_uint32_t flag)
{
@@ -125,7 +124,6 @@
rv = p_api->fdb_del_by_mac(dev_id, entry);
return rv;
}
-#endif
static sw_error_t
_fal_fdb_entry_getfirst(a_uint32_t dev_id, fal_fdb_entry_t * entry)
@@ -175,7 +173,7 @@
rv = p_api->fdb_next(dev_id, entry);
return rv;
}
-
+#endif
static sw_error_t
_fal_fdb_entry_search(a_uint32_t dev_id, fal_fdb_entry_t * entry)
@@ -200,7 +198,6 @@
rv = p_api->fdb_find(dev_id, entry);
return rv;
}
-#endif
static sw_error_t
_fal_fdb_port_learn_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
@@ -250,6 +247,7 @@
rv = p_api->port_learn_get(dev_id, port_id, enable);
return rv;
}
+#endif
static sw_error_t
_fal_fdb_port_learning_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
@@ -266,6 +264,7 @@
return rv;
}
+#ifndef IN_FDB_MINI
static sw_error_t
_fal_fdb_port_learning_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
{
@@ -280,6 +279,7 @@
rv = p_api->adpt_fdb_port_newaddr_lrn_get(dev_id, port_id, enable, cmd);
return rv;
}
+#endif
static sw_error_t
_fal_fdb_port_stamove_ctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable, fal_fwd_cmd_t cmd)
@@ -296,6 +296,7 @@
return rv;
}
+#ifndef IN_FDB_MINI
static sw_error_t
_fal_fdb_port_stamove_ctrl_get(a_uint32_t dev_id, fal_port_t port_id, a_bool_t *enable, fal_fwd_cmd_t *cmd)
{
@@ -310,6 +311,7 @@
rv = p_api->adpt_fdb_port_stamove_get(dev_id, port_id, enable, cmd);
return rv;
}
+#endif
static sw_error_t
_fal_fdb_aging_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
@@ -335,7 +337,7 @@
return rv;
}
-
+#ifndef IN_FDB_MINI
static sw_error_t
_fal_fdb_aging_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
{
@@ -870,6 +872,7 @@
rv = p_api->fdb_rfs_del(dev_id, entry);
return rv;
}
+#endif
sw_error_t
_fal_fdb_learning_ctrl_set(a_uint32_t dev_id, a_bool_t enable)
@@ -885,6 +888,8 @@
rv = p_api->adpt_fdb_learn_ctrl_set(dev_id, enable);
return rv;
}
+
+#ifndef IN_FDB_MINI
sw_error_t
_fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
{
@@ -942,6 +947,7 @@
rv = p_api->adpt_fdb_port_maclimit_ctrl_get(dev_id, port_id, maclimit_ctrl);
return rv;
}
+#endif
sw_error_t
_fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
{
@@ -956,7 +962,7 @@
rv = p_api->adpt_fdb_del_by_fid(dev_id, fid, flag);
return rv;
}
-
+#ifndef IN_FDB_MINI
/*insert flag for inner fal, don't remove it*/
/**
@@ -997,7 +1003,6 @@
return rv;
}
-#ifndef IN_FDB_MINI
/**
* @brief Delete Fdb entries on a particular port
* @details Comments:
@@ -1038,7 +1043,6 @@
FAL_API_UNLOCK;
return rv;
}
-#endif
/**
* @brief Get first Fdb entry from particular device
@@ -1076,6 +1080,7 @@
FAL_API_UNLOCK;
return rv;
}
+#endif
/**
* @brief Find a particular Fdb entry from device through mac address.
@@ -1096,7 +1101,6 @@
FAL_API_UNLOCK;
return rv;
}
-#endif
/**
* @brief Set dynamic address and station move learning status on a particular port.
@@ -1137,6 +1141,7 @@
FAL_API_UNLOCK;
return rv;
}
+#endif
/**
* @brief Set dynamic address learning and forward command on a particular port.
@@ -1157,6 +1162,7 @@
return rv;
}
+#ifndef IN_FDB_MINI
/**
* @brief Get dynamic address learning and forward command on a particular port.
* @param[in] dev_id device id
@@ -1175,6 +1181,7 @@
FAL_API_UNLOCK;
return rv;
}
+#endif
/**
* @brief Set station move learning and forward command on a particular port.
@@ -1195,6 +1202,7 @@
return rv;
}
+#ifndef IN_FDB_MINI
/**
* @brief Get station move learning and forward command on a particular port.
* @param[in] dev_id device id
@@ -1213,6 +1221,7 @@
FAL_API_UNLOCK;
return rv;
}
+#endif
/**
* @brief Set dynamic address aging status on particular device.
@@ -1234,6 +1243,7 @@
return rv;
}
+#ifndef IN_FDB_MINI
/**
* @brief Get dynamic address aging status on particular device.
* @param[in] dev_id device id
@@ -1769,6 +1779,8 @@
FAL_API_UNLOCK;
return rv;
}
+
+#ifndef IN_FDB_MINI
sw_error_t
fal_fdb_learning_ctrl_get(a_uint32_t dev_id, a_bool_t * enable)
{
@@ -1810,6 +1822,7 @@
FAL_API_UNLOCK;
return rv;
}
+#endif
sw_error_t
fal_fdb_entry_del_byfid(a_uint32_t dev_id, a_uint16_t fid, a_uint32_t flag)
{
@@ -1821,35 +1834,48 @@
return rv;
}
-
#ifndef IN_FDB_MINI
EXPORT_SYMBOL(fal_fdb_entry_add);
+#endif
+
EXPORT_SYMBOL(fal_fdb_entry_del_byport);
+
EXPORT_SYMBOL(fal_fdb_entry_del_bymac);
+
EXPORT_SYMBOL(fal_fdb_entry_search);
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_port_learn_get);
- EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_set);
-
#endif
+ EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_set);
+
EXPORT_SYMBOL(fal_fdb_entry_flush);
EXPORT_SYMBOL(fal_fdb_entry_getfirst);
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_entry_getnext);
+#endif
+
EXPORT_SYMBOL(fal_fdb_port_learn_set);
EXPORT_SYMBOL(fal_fdb_learning_ctrl_set);
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_learning_ctrl_get);
+#endif
+
EXPORT_SYMBOL(fal_fdb_entry_getnext_byindex);
EXPORT_SYMBOL(fal_fdb_entry_extend_getnext);
@@ -1860,12 +1886,20 @@
EXPORT_SYMBOL(fal_fdb_port_learning_ctrl_get);
+#endif
+
EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_set);
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_port_stamove_ctrl_get);
+#endif
+
EXPORT_SYMBOL(fal_fdb_aging_ctrl_set);
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_aging_ctrl_get);
EXPORT_SYMBOL(fal_fdb_aging_time_set);
@@ -1890,11 +1924,16 @@
EXPORT_SYMBOL(fal_fdb_port_maclimit_ctrl_get);
- EXPORT_SYMBOL(fal_fdb_entry_del_byfid);
#endif
+ EXPORT_SYMBOL(fal_fdb_entry_del_byfid);
+
+#ifndef IN_FDB_MINI
+
EXPORT_SYMBOL(fal_fdb_port_learned_mac_counter_get);
+#endif
+
/*insert flag for outter fal, don't remove it*/
/**
diff --git a/src/fal/fal_qos.c b/src/fal/fal_qos.c
old mode 100644
new mode 100755
index 2330225..046accc
--- a/src/fal/fal_qos.c
+++ b/src/fal/fal_qos.c
@@ -638,6 +638,7 @@
rv = p_api->qos_queue_remark_table_get(dev_id, port_id, queue_id, tbl_id, enable);
return rv;
}
+#endif
sw_error_t
_fal_qos_port_pri_precedence_set(a_uint32_t dev_id, fal_port_t port_id,
@@ -973,6 +974,7 @@
rv = p_api->adpt_port_scheduler_resource_get(dev_id, port_id, cfg);
return rv;
}
+#ifndef IN_QOS_MINI
/*insert flag for inner fal, don't remove it*/
/**
@@ -1964,8 +1966,6 @@
EXPORT_SYMBOL(fal_qos_port_pri_precedence_set);
-EXPORT_SYMBOL(fal_qos_port_tx_buf_status_get);
-
EXPORT_SYMBOL(fal_qos_port_pri_precedence_get);
EXPORT_SYMBOL(fal_qos_port_group_set);
diff --git a/src/hsl/hppe/hppe_fdb.c b/src/hsl/hppe/hppe_fdb.c
index b139b79..43481d0 100755
--- a/src/hsl/hppe/hppe_fdb.c
+++ b/src/hsl/hppe/hppe_fdb.c
@@ -22,7 +22,7 @@
#include "hppe_reg_access.h"
#include "hppe_fdb_reg.h"
#include "hppe_fdb.h"
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_l2_dbg_addr_get(
a_uint32_t dev_id,
@@ -74,7 +74,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS,
&value->val);
}
-
+#endif
sw_error_t
hppe_fdb_tbl_op_set(
a_uint32_t dev_id,
@@ -85,7 +85,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_OP_ADDRESS,
value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_get(
a_uint32_t dev_id,
@@ -96,7 +96,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_ADDRESS,
&value->val);
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_set(
a_uint32_t dev_id,
@@ -118,7 +118,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_OP_RSLT_ADDRESS,
&value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_op_rslt_set(
a_uint32_t dev_id,
@@ -126,7 +126,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_get(
a_uint32_t dev_id,
@@ -137,7 +137,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_ADDRESS,
&value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_set(
a_uint32_t dev_id,
@@ -167,7 +167,7 @@
IPE_L2_BASE_ADDR + AGE_TIMER_ADDRESS,
value->val);
}
-
+#endif
sw_error_t
hppe_l2_global_conf_get(
a_uint32_t dev_id,
@@ -189,7 +189,7 @@
IPE_L2_BASE_ADDR + L2_GLOBAL_CONF_ADDRESS,
value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_l2_dbgcnt_cmd_get(
a_uint32_t dev_id,
@@ -252,7 +252,7 @@
IPE_L2_BASE_ADDR + L2_DBGCNT_WDATA_ADDRESS,
value->val);
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data0_get(
a_uint32_t dev_id,
@@ -282,7 +282,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA1_ADDRESS,
&value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data1_set(
a_uint32_t dev_id,
@@ -290,7 +290,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data2_get(
a_uint32_t dev_id,
@@ -301,7 +301,7 @@
IPE_L2_BASE_ADDR + FDB_TBL_RD_OP_RSLT_DATA2_ADDRESS,
&value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data2_set(
a_uint32_t dev_id,
@@ -309,7 +309,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_op_data0_get(
a_uint32_t dev_id,
@@ -469,7 +469,7 @@
index * PORT_BRIDGE_CTRL_INC,
value->val);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_port_lrn_limit_ctrl_get(
a_uint32_t dev_id,
@@ -521,7 +521,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_rfdb_tbl_get(
a_uint32_t dev_id,
@@ -549,7 +549,7 @@
value->val,
2);
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_get(
a_uint32_t dev_id,
@@ -1541,7 +1541,7 @@
ret = hppe_l2_dbgcnt_wdata_set(dev_id, ®_val);
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data0_data_get(
a_uint32_t dev_id,
@@ -1554,7 +1554,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data0_data_set(
a_uint32_t dev_id,
@@ -1562,7 +1562,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data1_data_get(
a_uint32_t dev_id,
@@ -1575,7 +1575,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data1_data_set(
a_uint32_t dev_id,
@@ -1583,7 +1583,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data2_data_get(
a_uint32_t dev_id,
@@ -1596,7 +1596,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_rslt_data2_data_set(
a_uint32_t dev_id,
@@ -1617,7 +1617,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_op_data0_data_set(
a_uint32_t dev_id,
@@ -1633,7 +1633,7 @@
ret = hppe_fdb_tbl_op_data0_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_op_data1_data_get(
a_uint32_t dev_id,
@@ -1646,7 +1646,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_op_data1_data_set(
a_uint32_t dev_id,
@@ -1662,7 +1662,7 @@
ret = hppe_fdb_tbl_op_data1_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_op_data2_data_get(
a_uint32_t dev_id,
@@ -1675,7 +1675,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_op_data2_data_set(
a_uint32_t dev_id,
@@ -1691,7 +1691,7 @@
ret = hppe_fdb_tbl_op_data2_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_data0_data_get(
a_uint32_t dev_id,
@@ -1704,7 +1704,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_data0_data_set(
a_uint32_t dev_id,
@@ -1720,7 +1720,7 @@
ret = hppe_fdb_tbl_rd_op_data0_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_data1_data_get(
a_uint32_t dev_id,
@@ -1733,7 +1733,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_data1_data_set(
a_uint32_t dev_id,
@@ -1749,7 +1749,7 @@
ret = hppe_fdb_tbl_rd_op_data1_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_fdb_tbl_rd_op_data2_data_get(
a_uint32_t dev_id,
@@ -1762,7 +1762,7 @@
*value = reg_val.bf.data;
return ret;
}
-
+#endif
sw_error_t
hppe_fdb_tbl_rd_op_data2_data_set(
a_uint32_t dev_id,
@@ -1778,7 +1778,7 @@
ret = hppe_fdb_tbl_rd_op_data2_set(dev_id, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_port_bridge_ctrl_txmac_en_get(
a_uint32_t dev_id,
@@ -2111,7 +2111,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_rfdb_tbl_mac_addr_get(
a_uint32_t dev_id,
@@ -2144,7 +2144,7 @@
ret = hppe_rfdb_tbl_set(dev_id, index, ®_val);
return ret;
}
-
+#ifndef IN_FDB_MINI
sw_error_t
hppe_rfdb_tbl_valid_get(
a_uint32_t dev_id,
@@ -2158,7 +2158,7 @@
*value = reg_val.bf.valid;
return ret;
}
-
+#endif
sw_error_t
hppe_rfdb_tbl_valid_set(
a_uint32_t dev_id,
diff --git a/src/hsl/hppe/hppe_qos.c b/src/hsl/hppe/hppe_qos.c
index 6df4943..f617917 100755
--- a/src/hsl/hppe/hppe_qos.c
+++ b/src/hsl/hppe/hppe_qos.c
@@ -218,7 +218,7 @@
index * PORT_QOS_CTRL_INC,
value->val);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_tdm_depth_cfg_get(
a_uint32_t dev_id,
@@ -229,7 +229,7 @@
TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS,
&value->val);
}
-
+#endif
sw_error_t
hppe_tdm_depth_cfg_set(
a_uint32_t dev_id,
@@ -240,7 +240,7 @@
TRAFFIC_MANAGER_BASE_ADDR + TDM_DEPTH_CFG_ADDRESS,
value->val);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_min_max_mode_cfg_get(
a_uint32_t dev_id,
@@ -347,7 +347,7 @@
TRAFFIC_MANAGER_BASE_ADDR + ECO_RESERVE_1_ADDRESS,
value->val);
}
-
+#endif
sw_error_t
hppe_l0_flow_map_tbl_get(
a_uint32_t dev_id,
@@ -459,7 +459,7 @@
index * L0_FLOW_PORT_MAP_TBL_INC,
value->val);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_l0_c_drr_head_tbl_get(
a_uint32_t dev_id,
@@ -743,7 +743,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_ring_q_map_tbl_get(
a_uint32_t dev_id,
@@ -771,7 +771,7 @@
value->val,
10);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_rfc_block_tbl_get(
a_uint32_t dev_id,
@@ -819,7 +819,7 @@
{
return SW_NOT_SUPPORTED;
}
-
+#endif
sw_error_t
hppe_deq_dis_tbl_get(
a_uint32_t dev_id,
@@ -973,7 +973,7 @@
value->val,
2);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_l1_c_drr_head_tbl_set(
a_uint32_t dev_id,
@@ -1306,7 +1306,7 @@
index * PSCH_TDM_CFG_TBL_INC,
&value->val);
}
-
+#endif
sw_error_t
hppe_psch_tdm_cfg_tbl_set(
a_uint32_t dev_id,
@@ -1319,7 +1319,7 @@
index * PSCH_TDM_CFG_TBL_INC,
value->val);
}
-
+#ifndef IN_QOS_MINI
sw_error_t
hppe_tdm_depth_cfg_tdm_depth_get(
a_uint32_t dev_id,
@@ -4544,4 +4544,5 @@
reg_val.bf.qos_info = value;
ret = hppe_dscp_qos_group_1_set(dev_id, index, ®_val);
return ret;
-}
\ No newline at end of file
+}
+#endif
\ No newline at end of file
diff --git a/src/hsl/phy/aquantia_phy.c b/src/hsl/phy/aquantia_phy.c
index 4b5c5b0..9749bdc 100755
--- a/src/hsl/phy/aquantia_phy.c
+++ b/src/hsl/phy/aquantia_phy.c
@@ -58,7 +58,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_get_phy_id - get the phy id
@@ -82,7 +82,7 @@
return rv;
}
-
+#endif
sw_error_t
aquantia_phy_get_speed(a_uint32_t dev_id, a_uint32_t phy_id,
fal_port_speed_t * speed)
@@ -160,7 +160,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_reset - reset the phy
@@ -686,7 +686,7 @@
return rv;
}
-
+#endif
/******************************************************************************
*
* AQUANTIA_autoneg_done
@@ -712,7 +712,7 @@
return A_TRUE;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_get_ability - get the phy ability
@@ -772,7 +772,7 @@
return rv;
}
-
+#endif
/******************************************************************************
*
* aquantia_phy_status - test to see if the specified phy link is alive
@@ -1010,6 +1010,7 @@
return rv;
}
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_set_802.3az
@@ -1081,7 +1082,7 @@
return rv;
}
-
+#endif
/******************************************************************************
*
* aquantia_phy_set_speed - Determines the speed of phy ports associated with the
@@ -1283,7 +1284,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_set wol enable or disable
@@ -1416,7 +1417,7 @@
return rv;
}
-
+#endif
sw_error_t
aquantia_phy_interface_set_mode(a_uint32_t dev_id, a_uint32_t phy_id, fal_port_interface_mode_t interface_mode)
{
@@ -1543,7 +1544,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* aquantia_phy_intr_mask_set - Set interrupt mask with the
@@ -1616,7 +1617,7 @@
return rv;
}
-
+#endif
/******************************************************************************
*
* aquantia_phy_off - power off the phy
@@ -1658,7 +1659,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
static sw_error_t
_aquantia_phy_line_side_counter_get(a_uint32_t dev_id, a_uint32_t phy_id,
fal_port_counter_info_t * counter_infor)
@@ -1777,7 +1778,7 @@
return rv;
}
-
+#endif
/******************************************************************************
*
* aquantia_phy_get_status
@@ -2132,14 +2133,19 @@
aquantia_phy_api_ops->phy_autoneg_status_get = aquantia_phy_autoneg_status;
aquantia_phy_api_ops->phy_autoneg_adv_set = aquantia_phy_set_autoneg_adv;
aquantia_phy_api_ops->phy_autoneg_adv_get = aquantia_phy_get_autoneg_adv;
+#ifndef IN_PORTCONTROL_MINI
aquantia_phy_api_ops->phy_powersave_set = aquantia_phy_set_powersave;
aquantia_phy_api_ops->phy_powersave_get = aquantia_phy_get_powersave;
aquantia_phy_api_ops->phy_8023az_set = aquantia_phy_set_8023az;
aquantia_phy_api_ops->phy_8023az_get = aquantia_phy_get_8023az;
+#endif
aquantia_phy_api_ops->phy_power_on = aquantia_phy_poweron;
aquantia_phy_api_ops->phy_power_off = aquantia_phy_poweroff;
+#ifndef IN_PORTCONTROL_MINI
aquantia_phy_api_ops->phy_cdt = aquantia_phy_cdt;
+#endif
aquantia_phy_api_ops->phy_link_status_get = aquantia_phy_get_link_status;
+#ifndef IN_PORTCONTROL_MINI
aquantia_phy_api_ops->phy_mdix_set = aquantia_phy_set_mdix;
aquantia_phy_api_ops->phy_mdix_get = aquantia_phy_get_mdix;
aquantia_phy_api_ops->phy_mdix_status_get = aquantia_phy_get_mdix_status;
@@ -2155,10 +2161,13 @@
aquantia_phy_api_ops->phy_intr_mask_set = aquantia_phy_intr_mask_set;
aquantia_phy_api_ops->phy_intr_mask_get = aquantia_phy_intr_mask_get;
aquantia_phy_api_ops->phy_id_get = aquantia_phy_get_phy_id;
+#endif
aquantia_phy_api_ops->phy_interface_mode_set = aquantia_phy_interface_set_mode;
aquantia_phy_api_ops->phy_interface_mode_status_get=aquantia_phy_interface_get_mode_status;
aquantia_phy_api_ops->phy_get_status = aquantia_phy_get_status;
+#ifndef IN_PORTCONTROL_MINI
aquantia_phy_api_ops->phy_counter_show = aquantia_phy_show_counter;
+#endif
aquantia_phy_api_ops->phy_eee_adv_set = aquantia_phy_set_eee_adv;
aquantia_phy_api_ops->phy_eee_adv_get = aquantia_phy_get_eee_adv;
aquantia_phy_api_ops->phy_eee_partner_adv_get = aquantia_phy_get_eee_partner_adv;
diff --git a/src/hsl/phy/malibu_phy.c b/src/hsl/phy/malibu_phy.c
index 3a70e98..de94687 100755
--- a/src/hsl/phy/malibu_phy.c
+++ b/src/hsl/phy/malibu_phy.c
@@ -340,7 +340,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_reset - reset the phy
@@ -360,7 +360,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* malibu_phy_set_powersave - set power saving status
@@ -421,7 +421,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_get_powersave - get power saving status
@@ -453,7 +453,7 @@
}
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* malibu_phy_set_802.3az
@@ -542,7 +542,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_get_hibernate - get hibernate status
@@ -1195,7 +1195,7 @@
return A_TRUE;
}
-
+#endif
/******************************************************************************
*
* malibu_phy_off - power off the phy
@@ -1259,7 +1259,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_get_ability - get the phy ability
@@ -1361,7 +1361,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* malibu_phy_status - test to see if the specified phy link is alive
@@ -1892,7 +1892,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_set wol frame mac address
@@ -2004,7 +2004,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* malibu_serdes_reset - malibu psgmii serdes reset
@@ -2188,7 +2188,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* malibu_phy_intr_mask_set - Set interrupt mask with the
@@ -2447,7 +2447,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* malibu_phy_get status
@@ -2761,9 +2761,10 @@
}
phy_api_ops_init(MALIBU_PHY_CHIP);
-
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_hibernation_set = malibu_phy_set_hibernate;
malibu_phy_api_ops->phy_hibernation_get = malibu_phy_get_hibernate;
+#endif
malibu_phy_api_ops->phy_speed_get = malibu_phy_get_speed;
malibu_phy_api_ops->phy_speed_set = malibu_phy_set_speed;
malibu_phy_api_ops->phy_duplex_get = malibu_phy_get_duplex;
@@ -2773,10 +2774,13 @@
malibu_phy_api_ops->phy_autoneg_status_get = malibu_phy_autoneg_status;
malibu_phy_api_ops->phy_autoneg_adv_set = malibu_phy_set_autoneg_adv;
malibu_phy_api_ops->phy_autoneg_adv_get = malibu_phy_get_autoneg_adv;
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_powersave_set = malibu_phy_set_powersave;
malibu_phy_api_ops->phy_powersave_get = malibu_phy_get_powersave;
malibu_phy_api_ops->phy_cdt = malibu_phy_cdt;
+#endif
malibu_phy_api_ops->phy_link_status_get = malibu_phy_get_link_status;
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_mdix_set = malibu_phy_set_mdix;
malibu_phy_api_ops->phy_mdix_get = malibu_phy_get_mdix;
malibu_phy_api_ops->phy_mdix_status_get = malibu_phy_get_mdix_status;
@@ -2792,28 +2796,35 @@
malibu_phy_api_ops->phy_combo_fiber_mode_set = malibu_phy_set_combo_fiber_mode;
malibu_phy_api_ops->phy_combo_fiber_mode_get = malibu_phy_get_combo_fiber_mode;
malibu_phy_api_ops->phy_reset = malibu_phy_reset;
+#endif
malibu_phy_api_ops->phy_power_off = malibu_phy_poweroff;
malibu_phy_api_ops->phy_power_on = malibu_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_id_get = malibu_phy_get_phy_id;
+#endif
malibu_phy_api_ops->phy_reg_write = malibu_phy_reg_write;
malibu_phy_api_ops->phy_reg_read = malibu_phy_reg_read;
malibu_phy_api_ops->phy_debug_write = malibu_phy_debug_write;
malibu_phy_api_ops->phy_debug_read = malibu_phy_debug_read;
malibu_phy_api_ops->phy_mmd_write = malibu_phy_mmd_write;
malibu_phy_api_ops->phy_mmd_read = malibu_phy_mmd_read;
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_magic_frame_mac_set = malibu_phy_set_magic_frame_mac;
malibu_phy_api_ops->phy_magic_frame_mac_get = malibu_phy_get_magic_frame_mac;
malibu_phy_api_ops->phy_wol_status_set = malibu_phy_set_wol_status;
malibu_phy_api_ops->phy_wol_status_get = malibu_phy_get_wol_status;
+#endif
malibu_phy_api_ops->phy_interface_mode_set = malibu_phy_interface_set_mode;
malibu_phy_api_ops->phy_interface_mode_get = malibu_phy_interface_get_mode;
malibu_phy_api_ops->phy_interface_mode_status_get = malibu_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
malibu_phy_api_ops->phy_intr_mask_set = malibu_phy_intr_mask_set;
malibu_phy_api_ops->phy_intr_mask_get = malibu_phy_intr_mask_get;
malibu_phy_api_ops->phy_intr_status_get = malibu_phy_intr_status_get;
malibu_phy_api_ops->phy_counter_set = malibu_phy_set_counter;
malibu_phy_api_ops->phy_counter_get = malibu_phy_get_counter;
malibu_phy_api_ops->phy_counter_show = malibu_phy_show_counter;
+#endif
malibu_phy_api_ops->phy_serdes_reset = malibu_phy_serdes_reset;
malibu_phy_api_ops->phy_get_status = malibu_phy_get_status;
malibu_phy_api_ops->phy_eee_adv_set = malibu_phy_set_eee_adv;
diff --git a/src/hsl/phy/qca803x_phy.c b/src/hsl/phy/qca803x_phy.c
index 34dc50b..127da7c 100755
--- a/src/hsl/phy/qca803x_phy.c
+++ b/src/hsl/phy/qca803x_phy.c
@@ -368,7 +368,7 @@
}
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca803x_phy_cdt - cable diagnostic test
@@ -631,7 +631,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* qca803x_set_autoneg_adv - set the phy autoneg Advertisement
@@ -784,7 +784,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca803x_phy_get_ability - get the phy ability
@@ -977,7 +977,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* qca803x_phy_off - power off the phy
@@ -1014,7 +1014,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca803x_phy_set_802.3az
@@ -1280,7 +1280,7 @@
return SW_OK;
}
-
+#endif
sw_error_t
__phy_chip_config_get(a_uint32_t dev_id, a_uint32_t phy_id,
qca803x_cfg_type_t cfg_sel, qca803x_cfg_t *cfg_value)
@@ -1419,7 +1419,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca803x_phy_set_intr_mask - Set interrupt mask with the
@@ -1764,7 +1764,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* qca803x_phy_get status
@@ -1984,6 +1984,7 @@
qca803x_phy_api_ops->phy_autoneg_adv_get = qca803x_phy_get_autoneg_adv;
qca803x_phy_api_ops->phy_link_status_get = qca803x_phy_get_link_status;
qca803x_phy_api_ops->phy_reset = qca803x_phy_reset;
+#ifndef IN_PORTCONTROL_MINI
qca803x_phy_api_ops->phy_powersave_set = qca803x_phy_set_powersave;
qca803x_phy_api_ops->phy_powersave_get = qca803x_phy_get_powersave;
qca803x_phy_api_ops->phy_cdt = qca803x_phy_cdt;
@@ -1994,15 +1995,19 @@
qca803x_phy_api_ops->phy_local_loopback_get = qca803x_phy_get_local_loopback;
qca803x_phy_api_ops->phy_remote_loopback_set = qca803x_phy_set_remote_loopback;
qca803x_phy_api_ops->phy_remote_loopback_get = qca803x_phy_get_remote_loopback;
+#endif
qca803x_phy_api_ops->phy_reg_write = qca803x_phy_reg_write;
qca803x_phy_api_ops->phy_reg_read = qca803x_phy_reg_read;
qca803x_phy_api_ops->phy_debug_write = qca803x_phy_debug_write;
qca803x_phy_api_ops->phy_debug_read = qca803x_phy_debug_read;
qca803x_phy_api_ops->phy_mmd_write = qca803x_phy_mmd_write;
qca803x_phy_api_ops->phy_mmd_read = qca803x_phy_mmd_read;
+#ifndef IN_PORTCONTROL_MINI
qca803x_phy_api_ops->phy_id_get = qca803x_phy_get_phy_id;
+#endif
qca803x_phy_api_ops->phy_power_off = qca803x_phy_poweroff;
qca803x_phy_api_ops->phy_power_on = qca803x_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
qca803x_phy_api_ops->phy_8023az_set = qca803x_phy_set_8023az;
qca803x_phy_api_ops->phy_8023az_get = qca803x_phy_get_8023az;
qca803x_phy_api_ops->phy_hibernation_set = qca803x_phy_set_hibernate;
@@ -2011,9 +2016,11 @@
qca803x_phy_api_ops->phy_magic_frame_mac_get = qca803x_phy_get_magic_frame_mac;
qca803x_phy_api_ops->phy_wol_status_set = qca803x_phy_set_wol_status;
qca803x_phy_api_ops->phy_wol_status_get = qca803x_phy_get_wol_status;
+#endif
qca803x_phy_api_ops->phy_interface_mode_set = qca803x_phy_interface_set_mode;
qca803x_phy_api_ops->phy_interface_mode_get = qca803x_phy_interface_get_mode;
qca803x_phy_api_ops->phy_interface_mode_status_get = qca803x_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
qca803x_phy_api_ops->phy_intr_mask_set = qca803x_phy_set_intr_mask;
qca803x_phy_api_ops->phy_intr_mask_get = qca803x_phy_get_intr_mask;
qca803x_phy_api_ops->phy_intr_status_get = qca803x_phy_get_intr_status;
@@ -2022,6 +2029,7 @@
qca803x_phy_api_ops->phy_combo_medium_status_get = qca803x_phy_get_combo_current_medium_type;
qca803x_phy_api_ops->phy_combo_fiber_mode_set = qca803x_phy_set_combo_fiber_mode;
qca803x_phy_api_ops->phy_combo_fiber_mode_get = qca803x_phy_get_combo_fiber_mode;
+#endif
qca803x_phy_api_ops->phy_get_status = qca803x_phy_get_status;
qca803x_phy_api_ops->phy_eee_adv_set = qca803x_phy_set_eee_adv;
qca803x_phy_api_ops->phy_eee_adv_get = qca803x_phy_get_eee_adv;
diff --git a/src/hsl/phy/qca808x_phy.c b/src/hsl/phy/qca808x_phy.c
index c865f69..f204463 100755
--- a/src/hsl/phy/qca808x_phy.c
+++ b/src/hsl/phy/qca808x_phy.c
@@ -544,7 +544,7 @@
return A_FALSE;
}
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca808x_phy_cdt - cable diagnostic test
@@ -870,7 +870,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* qca808x_set_autoneg_adv - set the phy autoneg Advertisement
@@ -1124,7 +1124,7 @@
return rv;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca808x_phy_set_802.3az
@@ -1403,7 +1403,7 @@
return SW_OK;
}
-
+#endif
/******************************************************************************
*
* qca808x_phy_interface mode set
@@ -1472,7 +1472,7 @@
return SW_OK;
}
-
+#ifndef IN_PORTCONTROL_MINI
/******************************************************************************
*
* qca808x_phy_set_intr_mask - Set interrupt mask with the
@@ -1714,6 +1714,7 @@
return SW_OK;
}
+#endif
/******************************************************************************
*
* qca808x_phy_set_eee_advertisement
@@ -1947,6 +1948,7 @@
qca808x_phy_api_ops->phy_autoneg_adv_get = qca808x_phy_get_autoneg_adv;
qca808x_phy_api_ops->phy_link_status_get = qca808x_phy_get_link_status;
qca808x_phy_api_ops->phy_reset = qca808x_phy_reset;
+#ifndef IN_PORTCONTROL_MINI
qca808x_phy_api_ops->phy_cdt = qca808x_phy_cdt;
qca808x_phy_api_ops->phy_mdix_set = qca808x_phy_set_mdix;
qca808x_phy_api_ops->phy_mdix_get = qca808x_phy_get_mdix;
@@ -1955,9 +1957,11 @@
qca808x_phy_api_ops->phy_local_loopback_get = qca808x_phy_get_local_loopback;
qca808x_phy_api_ops->phy_remote_loopback_set = qca808x_phy_set_remote_loopback;
qca808x_phy_api_ops->phy_remote_loopback_get = qca808x_phy_get_remote_loopback;
+#endif
qca808x_phy_api_ops->phy_id_get = qca808x_phy_get_phy_id;
qca808x_phy_api_ops->phy_power_off = qca808x_phy_poweroff;
qca808x_phy_api_ops->phy_power_on = qca808x_phy_poweron;
+#ifndef IN_PORTCONTROL_MINI
qca808x_phy_api_ops->phy_8023az_set = qca808x_phy_set_8023az;
qca808x_phy_api_ops->phy_8023az_get = qca808x_phy_get_8023az;
qca808x_phy_api_ops->phy_hibernation_set = qca808x_phy_set_hibernate;
@@ -1966,15 +1970,18 @@
qca808x_phy_api_ops->phy_magic_frame_mac_get = qca808x_phy_get_magic_frame_mac;
qca808x_phy_api_ops->phy_wol_status_set = qca808x_phy_set_wol_status;
qca808x_phy_api_ops->phy_wol_status_get = qca808x_phy_get_wol_status;
+#endif
qca808x_phy_api_ops->phy_interface_mode_set = qca808x_phy_interface_set_mode;
qca808x_phy_api_ops->phy_interface_mode_get = qca808x_phy_interface_get_mode;
qca808x_phy_api_ops->phy_interface_mode_status_get = qca808x_phy_interface_get_mode_status;
+#ifndef IN_PORTCONTROL_MINI
qca808x_phy_api_ops->phy_intr_mask_set = qca808x_phy_set_intr_mask;
qca808x_phy_api_ops->phy_intr_mask_get = qca808x_phy_get_intr_mask;
qca808x_phy_api_ops->phy_intr_status_get = qca808x_phy_get_intr_status;
qca808x_phy_api_ops->phy_counter_set = qca808x_phy_set_counter;
qca808x_phy_api_ops->phy_counter_get = qca808x_phy_get_counter;
qca808x_phy_api_ops->phy_counter_show = qca808x_phy_show_counter;
+#endif
qca808x_phy_api_ops->phy_eee_adv_set = qca808x_phy_set_eee_adv;
qca808x_phy_api_ops->phy_eee_adv_get = qca808x_phy_get_eee_adv;
qca808x_phy_api_ops->phy_eee_partner_adv_get = qca808x_phy_get_eee_partner_adv;
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index ae137db..f478270 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -2851,6 +2851,52 @@
return 0;
}
+#ifdef IN_TRUNK
+#define MULTIPLE_WAN_PORT_CNT 2
+#define TRUNK_ID_OF_MULTIPLE_WAN_PORTS 0
+
+static a_bool_t
+ssdk_dess_multiple_wan_port_check(a_uint32_t dev_id,
+ a_uint32_t wan_bitmap)
+{
+ a_uint32_t port_id = SSDK_PHYSICAL_PORT0, wan_ports_cnt = 0;
+
+ for(port_id = SSDK_PHYSICAL_PORT0; port_id < SSDK_MAX_PORT_NUM;
+ port_id++)
+ {
+ if(BIT(port_id) & wan_bitmap)
+ {
+ wan_ports_cnt++;
+ }
+ }
+ if(wan_ports_cnt >= MULTIPLE_WAN_PORT_CNT)
+ {
+ return A_TRUE;
+ }
+ else
+ {
+ return A_FALSE;
+ }
+}
+
+static sw_error_t
+ssdk_dess_trunk_init(a_uint32_t dev_id, ssdk_init_cfg *cfg)
+{
+ sw_error_t rv = SW_OK;
+ a_uint32_t wan_bitmap;
+
+ wan_bitmap = cfg->port_cfg.wan_bmp;
+ if(ssdk_dess_multiple_wan_port_check(dev_id, wan_bitmap))
+ {
+ rv = fal_trunk_group_set(dev_id, TRUNK_ID_OF_MULTIPLE_WAN_PORTS,
+ A_TRUE, wan_bitmap);
+ SW_RTN_ON_ERROR(rv);
+ }
+
+ return rv;
+}
+#endif
+
static sw_error_t
qca_dess_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
{
@@ -2876,12 +2922,12 @@
ssdk_portvlan_init(dev_id);
#endif
- #ifdef IN_PORTVLAN
+#ifdef IN_PORTVLAN
fal_port_rxhdr_mode_set(dev_id, 0, FAL_ALL_TYPE_FRAME_EN);
- #endif
- #ifdef IN_IP
+#endif
+#ifdef IN_IP
fal_ip_route_status_set(dev_id, A_TRUE);
- #endif
+#endif
ssdk_flow_default_act_init(dev_id);
@@ -2890,9 +2936,9 @@
reg_value = (reg_value|0x1000000|0x8);
reg_value &= ~2;
qca_switch_reg_write(dev_id, 0x0e38, (a_uint8_t *)®_value, 4);
- #ifdef IN_IP
+#ifdef IN_IP
fal_ip_vrf_base_addr_set(dev_id, 0, 0);
- #endif
+#endif
p_api = hsl_api_ptr_get (dev_id);
if (p_api && p_api->port_flowctrl_thresh_set)
@@ -2908,6 +2954,9 @@
/*add BGA Board led contorl*/
ssdk_dess_led_init(cfg);
+#ifdef IN_TRUNK
+ SW_RTN_ON_ERROR(ssdk_dess_trunk_init(dev_id, cfg));
+#endif
return SW_OK;
}
diff --git a/src/ref/ref_uci.c b/src/ref/ref_uci.c
index a280aaa..5f99b0d 100755
--- a/src/ref/ref_uci.c
+++ b/src/ref/ref_uci.c
@@ -8270,7 +8270,15 @@
rule.dscp = tmpdata;
FAL_ACTION_FLG_SET(rule.action_flg,
FAL_ACL_ACTION_REMARK_DSCP);
- } else if(!strcmp(ext_value_p->option_name, "vlan_priority_of_remark")) {
+ }
+#if defined(CPPE)
+ else if(!strcmp(ext_value_p->option_name, "dscp_of_remark_mask")) {
+ cmd_data_check_uint8((char*)ext_value_p->option_value,
+ &tmpdata, sizeof(tmpdata));
+ rule.dscp_mask = tmpdata;
+ }
+#endif
+ else if(!strcmp(ext_value_p->option_name, "vlan_priority_of_remark")) {
cmd_data_check_uint8((char*)ext_value_p->option_value,
&tmpdata, sizeof(tmpdata));
rule.up = tmpdata;