commit 403f8c665b73eb54269de1dc2490eb254b7fda2f
author Luo Jie <luoj@codeaurora.org> Tue Jun 25 16:41:08 2019 +0800
committer Gerrit - the friendly Code Review server <code-review@localhost> Mon Jul 22 19:16:32 2019 -0700
tree 991cb98fe6f58473710c02071f54bbc94b03bde8
parent 7235b2e0dd91663f455528f6683654d227e356ae

[qca-ssdk]: [ReducedProfile]: Cypress mini ssdk support

Change-Id: I7dc95b32dde39d3525417ca68a0a18a3a6b9d2b0
Signed-off-by: Luo Jie <luoj@codeaurora.org>

include/adpt/cppe/adpt_cppe_flow.h

diff --git a/include/adpt/cppe/adpt_cppe_flow.h b/include/adpt/cppe/adpt_cppe_flow.h
index 2d70de0..72480e5 100755
--- a/include/adpt/cppe/adpt_cppe_flow.h
+++ b/include/adpt/cppe/adpt_cppe_flow.h
@@ -24,11 +24,13 @@
 extern "C" {
 #endif                          /* __cplusplus */
 
+#ifndef IN_FLOW_MINI
 sw_error_t
 adpt_cppe_flow_copy_escape_set(a_uint32_t dev_id, a_bool_t enable);
 
 sw_error_t
 adpt_cppe_flow_copy_escape_get(a_uint32_t dev_id, a_bool_t *enable);
+#endif
 
 #ifdef __cplusplus
 }

include/adpt/cppe/adpt_cppe_portctrl.h

diff --git a/include/adpt/cppe/adpt_cppe_portctrl.h b/include/adpt/cppe/adpt_cppe_portctrl.h
index d8eda74..9e38ed3 100755
--- a/include/adpt/cppe/adpt_cppe_portctrl.h
+++ b/include/adpt/cppe/adpt_cppe_portctrl.h
@@ -49,6 +49,7 @@
 sw_error_t
 adpt_cppe_port_mru_get(a_uint32_t dev_id, fal_port_t port_id,
 		fal_mru_ctrl_t *ctrl);
+#ifndef IN_PORTCONTROL_MINI
 sw_error_t
 adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
 		fal_mtu_ctrl_t *ctrl);
@@ -56,9 +57,6 @@
 adpt_cppe_port_mtu_get(a_uint32_t dev_id, fal_port_t port_id,
 		fal_mtu_ctrl_t *ctrl);
 sw_error_t
-adpt_cppe_port_to_channel_convert(a_uint32_t dev_id,
-		a_uint32_t port_id, a_uint32_t *channel_id);
-sw_error_t
 adpt_cppe_port_source_filter_set(a_uint32_t dev_id,
 		fal_port_t port_id, a_bool_t enable);
 sw_error_t
@@ -72,6 +70,10 @@
 adpt_cppe_port_source_filter_config_get
 		(a_uint32_t dev_id, fal_port_t port_id,
 		fal_src_filter_config_t* src_filter_config);
+#endif
+sw_error_t
+adpt_cppe_port_to_channel_convert(a_uint32_t dev_id,
+		a_uint32_t port_id, a_uint32_t *channel_id);
 sw_error_t
 adpt_cppe_switch_port_loopback_set(a_uint32_t dev_id,
 	fal_port_t port_id, fal_loopback_config_t *loopback_cfg);

src/adpt/cppe/Makefile

diff --git a/src/adpt/cppe/Makefile b/src/adpt/cppe/Makefile
index cc7acbf..990c629 100755
--- a/src/adpt/cppe/Makefile
+++ b/src/adpt/cppe/Makefile
@@ -22,12 +22,16 @@
 endif
 
 ifeq (TRUE, $(IN_MISC))
+ifneq (TRUE, $(IN_MISC_MINI))
   SRC_LIST += adpt_cppe_misc.c
 endif
+endif
 
 ifeq (TRUE, $(IN_FLOW))
+ifneq (TRUE, $(IN_FLOW_MINI))
   SRC_LIST += adpt_cppe_flow.c
 endif
+endif
 
 ifeq (TRUE, $(IN_MIB))
   SRC_LIST += adpt_cppe_mib.c

src/adpt/cppe/adpt_cppe_portctrl.c

diff --git a/src/adpt/cppe/adpt_cppe_portctrl.c b/src/adpt/cppe/adpt_cppe_portctrl.c
index 03cd105..aad289d 100755
--- a/src/adpt/cppe/adpt_cppe_portctrl.c
+++ b/src/adpt/cppe/adpt_cppe_portctrl.c
@@ -187,6 +187,7 @@
 	return SW_OK;
 }
 
+#ifndef IN_PORTCONTROL_MINI
 sw_error_t
 adpt_cppe_port_mtu_set(a_uint32_t dev_id, fal_port_t port_id,
 		fal_mtu_ctrl_t *ctrl)
@@ -236,6 +237,7 @@
 
 	return SW_OK;
 }
+#endif
 
 sw_error_t
 adpt_cppe_port_to_channel_convert(a_uint32_t dev_id, a_uint32_t port_id,
@@ -255,6 +257,7 @@
 	return SW_OK;
 }
 
+#ifndef IN_PORTCONTROL_MINI
 sw_error_t
 adpt_cppe_port_source_filter_set(a_uint32_t dev_id,
 	fal_port_t port_id, a_bool_t enable)
@@ -348,6 +351,7 @@
 
 	return rv;
 }
+#endif
 
 static a_uint32_t port_loopback_rate[SW_MAX_NR_DEV][CPPE_LOOPBACK_PORT_NUM] = {
 	{14},