[qca-ssdk]: fix mode switch dynamically issues
Change-Id: Id17529e0008bcbcb97bb43ebe00b8c2b0a9eb827
Signed-off-by: xiaofeis <xiaofeis@codeaurora.org>
diff --git a/include/init/ssdk_clk.h b/include/init/ssdk_clk.h
index 57e0a98..4ef7fb0 100644
--- a/include/init/ssdk_clk.h
+++ b/include/init/ssdk_clk.h
@@ -142,6 +142,7 @@
#define NSS_IMEM_RATE 400000000
#define PTP_REF_RARE 150000000
#define NSS_AXI_RATE 461500000
+#define NSS_PORT5_DFLT_RATE 19200000
#define UNIPHY_CLK_RATE_125M 125000000
#define UNIPHY_CLK_RATE_312M 312500000
@@ -180,6 +181,7 @@
qca_gcc_uniphy_port_clock_set(a_uint32_t dev_id, a_uint32_t uniphy_index,
a_uint32_t port_id, a_bool_t enable);
void ssdk_ppe_clock_init(void);
+void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index);
void ssdk_uniphy_raw_clock_set(
a_uint8_t uniphy_index,
a_uint8_t direction,
diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
index da27982..acb6b07 100755
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -524,8 +524,10 @@
sw_error_t rv = SW_OK;
a_uint32_t clock = UNIPHY_CLK_RATE_125M;
- if (mode == PORT_WRAPPER_MAX)
+ if (mode == PORT_WRAPPER_MAX) {
+ ssdk_uniphy_raw_clock_reset(index);
return SW_OK;
+ }
switch(mode) {
case PORT_WRAPPER_PSGMII:
diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
index c017a5c..6d6602e 100755
--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
@@ -428,6 +428,22 @@
SSDK_INFO("ppe and uniphy clock init successfully!\n");
}
+void ssdk_uniphy_raw_clock_reset(a_uint8_t uniphy_index)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+ a_uint32_t id;
+
+ if (uniphy_index >= SSDK_MAX_UNIPHY_INSTANCE)
+ return;
+
+ id = uniphy_index*2;
+ if (clk_set_rate(uniphy_raw_clks[id]->clk, UNIPHY_DEFAULT_RATE))
+ SSDK_ERROR("set rate for %d fail!\n", id);
+ if (clk_set_rate(uniphy_raw_clks[id+1]->clk, UNIPHY_DEFAULT_RATE))
+ SSDK_ERROR("set rate for %d fail!\n", id+1);
+#endif
+}
+
void ssdk_uniphy_raw_clock_set(
a_uint8_t uniphy_index,
a_uint8_t direction,
@@ -445,16 +461,26 @@
id = uniphy_index*2 + direction;
old_clock = clk_get_rate(uniphy_raw_clks[id]->clk);
+ if (clock != old_clock) {
+ if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
+ if (UNIPHY_RX == direction)
+ ssdk_uniphy_clock_rate_set(0,
+ NSS_PORT5_RX_CLK_E,
+ NSS_PORT5_DFLT_RATE);
+ else
+ ssdk_uniphy_clock_rate_set(0,
+ NSS_PORT5_TX_CLK_E,
+ NSS_PORT5_DFLT_RATE);
+ }
+ if (clk_set_rate(uniphy_raw_clks[id]->clk, clock))
+ SSDK_ERROR("set rate: %d fail!\n", clock);
+ }
+
if (uniphy_index == SSDK_UNIPHY_INSTANCE1) {
if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + direction],
uniphy_raw_clks[id]->clk))
SSDK_ERROR("set parent fail!\n");
}
-
- if (clock != old_clock) {
- if (clk_set_rate(uniphy_raw_clks[id]->clk, clock))
- SSDK_ERROR("set rate: %d fail!\n", clock);
- }
#endif
}