[qca-ssdk]: config master-slave seed and faste retrain for napa.
Change-Id: Id883979175693b4e4af1c67ea0b7eadf5a947c2b
Signed-off-by: zhongjia <zhongjia@codeaurora.org>
diff --git a/include/hsl/phy/qca808x_phy.h b/include/hsl/phy/qca808x_phy.h
index a175125..4ab3ab1 100755
--- a/include/hsl/phy/qca808x_phy.h
+++ b/include/hsl/phy/qca808x_phy.h
@@ -60,6 +60,7 @@
#define QCA808X_PHY_CDT_CONTROL 22
#define QCA808X_DEBUG_PORT_ADDRESS 29
#define QCA808X_DEBUG_PORT_DATA 30
+#define QCA808X_DEBUG_LOCAL_SEED 9
/* Chip Configuration Register */
#define QCA808X_PHY_CHIP_CONFIG 31
@@ -74,9 +75,10 @@
#define QCA808X_DEBUG_PHY_HIBERNATION_STAT 0xc
#define QCA808X_DEBUG_PHY_POWER_SAVING_CTRL 0x29
#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_CTRL 0x3c
-#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER 0x3d
-#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS 0x8000
-#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14
+#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_PARTNER 0x3d
+#define QCA808X_PHY_MMD7_ADDR_8023AZ_EEE_STATUS 0x8000
+#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_CAPABILITY 0x14
+#define QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT 0x40
#define QCA808X_PHY_MMD3_ADDR_8023AZ_EEE_DB 0x800f
#define QCA808X_PHY_8023AZ_EEE_LP_STAT 0x2000
@@ -110,6 +112,12 @@
#define QCA808X_PHY_MMD3_NUM 3
#define QCA808X_PHY_MMD1_NUM 1
+#define QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL 0x93
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
+#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
+#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
#define QCA808X_PHY_EEE_ADV_100M 0x0002
#define QCA808X_PHY_EEE_ADV_1000M 0x0004
#define QCA808X_PHY_EEE_PARTNER_ADV_100M 0x0002
@@ -119,6 +127,16 @@
#define QCA808X_PHY_EEE_STATUS_100M 0x0002
#define QCA808X_PHY_EEE_STATUS_1000M 0x0004
+#define QCA808X_PHY_FAST_RETRAIN_CTRL 0x1
+#define QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE 0x529
+#define QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE 0x341
+#define QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE 0x419
+#define QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE 0x341
+#define QCA808X_PHY_FAST_RETRAIN_2500BT 0x20
+#define QCA808X_PHY_ADV_LOOP_TIMING 0x1
+#define QCA808X_PHY_EEE_ADV_THP 0x8
+#define QCA808X_PHY_TOP_OPTION1_DATA 0x0
+
/* CDT */
#define QCA808X_MDI_PAIR_NUM 4
#define QCA808X_RUN_CDT 0x8000
@@ -174,6 +192,11 @@
#define QCA808X_CTRL_SPEED_100 0x2000
#define QCA808X_CTRL_SPEED_10 0x0000
+#define QCA808X_MASTER_SLAVE_SEED_ENABLE 0x2
+#define QCA808X_MASTER_SLAVE_SEED_CFG 0x1FFC
+#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
+#define QCA808X_MASTER_SLAVE_CONFIG_FAULT 0x8000
+
#define QCA808X_RESET_DONE(phy_control) \
(((phy_control) & (QCA808X_CTRL_SOFTWARE_RESET)) == 0)
diff --git a/src/hsl/phy/qca808x_phy.c b/src/hsl/phy/qca808x_phy.c
index f204463..d7d7430 100755
--- a/src/hsl/phy/qca808x_phy.c
+++ b/src/hsl/phy/qca808x_phy.c
@@ -194,6 +194,46 @@
return phy_data;
}
+static sw_error_t
+qca808x_phy_ms_random_seed_set(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ a_uint16_t phy_data;
+ sw_error_t rv = SW_OK;
+
+ phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+ QCA808X_DEBUG_LOCAL_SEED);
+ phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_CFG);
+ phy_data |= (prandom_u32()%QCA808X_MASTER_SLAVE_SEED_RANGE) << 2;
+ SSDK_DEBUG("QCA808X_DEBUG_LOCAL_SEED:%x\n", phy_data);
+ rv = qca808x_phy_debug_write(dev_id, phy_id,
+ QCA808X_DEBUG_LOCAL_SEED, phy_data);
+
+ return rv;
+}
+
+static sw_error_t
+qca808x_phy_ms_seed_enable(a_uint32_t dev_id, a_uint32_t phy_id,
+ a_bool_t enable)
+{
+ a_uint16_t phy_data;
+ sw_error_t rv = SW_OK;
+
+ phy_data = qca808x_phy_debug_read(dev_id, phy_id,
+ QCA808X_DEBUG_LOCAL_SEED);
+ if(enable)
+ {
+ phy_data |= QCA808X_MASTER_SLAVE_SEED_ENABLE;
+ }
+ else
+ {
+ phy_data &= ~(QCA808X_MASTER_SLAVE_SEED_ENABLE);
+ }
+ rv = qca808x_phy_debug_write(dev_id, phy_id,
+ QCA808X_DEBUG_LOCAL_SEED, phy_data);
+
+ return rv;
+}
+
/******************************************************************************
*
* qca808x_phy_get status
@@ -215,6 +255,19 @@
}
else {
phy_status->link_status = A_FALSE;
+ SW_RTN_ON_ERROR(
+ qca808x_phy_ms_random_seed_set (dev_id, phy_id));
+ /*protect logic, if MASTER_SLAVE_CONFIG_FAULT is 1,
+ then disable this logic*/
+ phy_data = qca808x_phy_reg_read(dev_id, phy_id,
+ QCA808X_1000BASET_STATUS);
+ if((phy_data & QCA808X_MASTER_SLAVE_CONFIG_FAULT) >> 15)
+ {
+ SW_RTN_ON_ERROR(
+ qca808x_phy_ms_seed_enable (dev_id, phy_id, A_FALSE));
+ SSDK_INFO("master_slave_config_fault was set\n");
+ }
+
return SW_OK;
}
@@ -521,6 +574,9 @@
rv = qca808x_phy_reg_write(dev_id, phy_id, QCA808X_PHY_CONTROL,
phy_data | QCA808X_CTRL_SOFTWARE_RESET);
+ SW_RTN_ON_ERROR(rv);
+ /*the configure will lost when reset.*/
+ rv = qca808x_phy_ms_seed_enable(dev_id, phy_id, A_TRUE);
return rv;
}
@@ -1884,6 +1940,67 @@
}
static sw_error_t
+qca808x_phy_fast_retrain_cfg(a_uint32_t dev_id, a_uint32_t phy_id)
+{
+ sw_error_t rv = SW_OK;
+
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+ QCA808X_PHY_MMD7_AUTONEGOTIATION_CONTROL,
+ QCA808X_ADVERTISE_2500FULL |
+ QCA808X_PHY_FAST_RETRAIN_2500BT |
+ QCA808X_PHY_ADV_LOOP_TIMING);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+ QCA808X_PHY_MMD1_FAST_RETRAIN_STATUS_CTL,
+ QCA808X_PHY_FAST_RETRAIN_CTRL);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+ QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+ QCA808X_PHY_MSE_THRESHOLD_20DB_VALUE);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+ QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+ QCA808X_PHY_MSE_THRESHOLD_17DB_VALUE);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+ QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+ QCA808X_PHY_MSE_THRESHOLD_27DB_VALUE);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD1_NUM,
+ QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+ QCA808X_PHY_MSE_THRESHOLD_28DB_VALUE);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+ QCA808X_PHY_MMD7_ADDR_EEE_LP_ADVERTISEMENT,
+ QCA808X_PHY_EEE_ADV_THP);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD7_NUM,
+ QCA808X_PHY_MMD7_TOP_OPTION1,
+ QCA808X_PHY_TOP_OPTION1_DATA);
+ SW_RTN_ON_ERROR(rv);
+ /*adjust the threshold for link down*/
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa100, 0x9203);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa105, 0x8001);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa106, 0x1111);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa103, 0x1698);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa011, 0x5f85);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_mmd_write(dev_id, phy_id, QCA808X_PHY_MMD3_NUM,
+ 0xa101, 0x48ad);
+
+ return rv;
+}
+
+static sw_error_t
qca808x_phy_hw_init(a_uint32_t dev_id, a_uint32_t port_bmp)
{
a_uint16_t phy_data = 0;
@@ -1911,6 +2028,15 @@
rv = qca808x_phy_mmd_write(dev_id, phy_addr, QCA808X_PHY_MMD3_NUM,
QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, phy_data);
SW_RTN_ON_ERROR(rv);
+ /*config the fast retrain*/
+ rv = qca808x_phy_fast_retrain_cfg(dev_id, phy_addr);
+ SW_RTN_ON_ERROR(rv);
+ /*enable seed and configure ramdom seed in order that napa can be
+ as slave easier*/
+ rv = qca808x_phy_ms_seed_enable(dev_id, phy_addr, A_TRUE);
+ SW_RTN_ON_ERROR(rv);
+ rv = qca808x_phy_ms_random_seed_set(dev_id, phy_addr);
+ SW_RTN_ON_ERROR(rv);
}
}