Merge "[qca-ssdk] enhance channel0 sgmii feature.."
diff --git a/include/hsl/hsl_api.h b/include/hsl/hsl_api.h
index d2030b4..95658b4 100755
--- a/include/hsl/hsl_api.h
+++ b/include/hsl/hsl_api.h
@@ -1909,6 +1909,19 @@
typedef sw_error_t
(*hsl_interface_mac06_exch_get) (a_uint32_t dev_id, a_bool_t * enable);
+ typedef sw_error_t
+ (*hsl_interface_pad_get) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value);
+
+ typedef sw_error_t
+ (*hsl_interface_pad_set) (a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value);
+
+ typedef sw_error_t
+ (*hsl_interface_sgmii_get) (a_uint32_t dev_id, a_uint32_t * value);
+
+ typedef sw_error_t
+ (*hsl_interface_sgmii_set) (a_uint32_t dev_id, a_uint32_t value);
+
+
/* REG */
#define REG_FUNC_PROTOTYPE_DEF
typedef sw_error_t
@@ -2493,6 +2506,10 @@
hsl_interface_fx100_status_get interface_fx100_status_get;
hsl_interface_mac06_exch_set interface_mac06_exch_set;
hsl_interface_mac06_exch_get interface_mac06_exch_get;
+ hsl_interface_pad_get interface_mac_pad_get;
+ hsl_interface_pad_set interface_mac_pad_set;
+ hsl_interface_sgmii_get interface_mac_sgmii_get;
+ hsl_interface_sgmii_set interface_mac_sgmii_set;
#endif
#endif
diff --git a/src/hsl/dess/dess_port_ctrl.c b/src/hsl/dess/dess_port_ctrl.c
index 061cf25..b79e82b 100755
--- a/src/hsl/dess/dess_port_ctrl.c
+++ b/src/hsl/dess/dess_port_ctrl.c
@@ -465,7 +465,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, force, reg;
+ a_uint32_t val, force, reg, tmp;
if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -495,10 +495,13 @@
/* flow control isn't in force mode so can't set */
return SW_DISABLE;
}
+ tmp = reg;
SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD (PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+ if (reg == tmp)
+ return SW_OK;
HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
@@ -553,7 +556,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg;
+ a_uint32_t reg, tmp;
if (A_TRUE != hsl_port_prop_check (dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -563,9 +566,12 @@
HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR (rv);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
if (A_TRUE == enable)
{
+ if (tmp== 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 0, reg);
}
else if (A_FALSE == enable)
@@ -575,6 +581,8 @@
{
return SW_DISABLE;
}
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD (PORT_STATUS, FLOW_LINK_EN, 1, reg);
}
else
@@ -961,7 +969,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -986,6 +994,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
@@ -1006,7 +1015,8 @@
SW_SET_REG_BY_FIELD (PORT_STATUS, TXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1047,7 +1057,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -1072,6 +1082,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
@@ -1092,7 +1103,8 @@
SW_SET_REG_BY_FIELD (PORT_STATUS, RXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1133,7 +1145,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -1158,6 +1170,7 @@
HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR (rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
@@ -1178,7 +1191,8 @@
SW_SET_REG_BY_FIELD (PORT_STATUS, TX_FLOW_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1219,7 +1233,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -1244,6 +1258,7 @@
HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR (rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
@@ -1264,7 +1279,8 @@
SW_SET_REG_BY_FIELD (PORT_STATUS, RX_FLOW_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1305,7 +1321,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val;
+ a_uint32_t val, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -1326,6 +1342,10 @@
{
return SW_BAD_PARAM;
}
+ HSL_REG_FIELD_GET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ if (tmp == val)
+ return SW_OK;
HSL_REG_FIELD_SET (rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
@@ -1367,7 +1387,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg;
+ a_uint32_t reg, tmp;
HSL_DEV_ID_CHECK (dev_id);
@@ -1379,13 +1399,18 @@
HSL_REG_ENTRY_GET (rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR (rv);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
if (A_TRUE == enable)
{
+ if(tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD (PORT_STATUS, LINK_EN, 0, reg);
}
else if (A_FALSE == enable)
{
+ if(tmp == 1)
+ return SW_OK;
/* for those ports without PHY, it can't sync link status */
if (A_FALSE == _dess_port_phy_connected (dev_id, port_id))
{
diff --git a/src/hsl/isis/isis_interface_ctrl.c b/src/hsl/isis/isis_interface_ctrl.c
index 9945710..c95ebed 100755
--- a/src/hsl/isis/isis_interface_ctrl.c
+++ b/src/hsl/isis/isis_interface_ctrl.c
@@ -1403,6 +1403,97 @@
return SW_OK;
}
+static sw_error_t
+_isis_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ reg = value;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *value = reg;
+
+ return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ reg = value;
+
+ switch (port_num)
+ {
+ case ISIS_MAC_0:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISIS_MAC_5:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISIS_MAC_6:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ switch (port_num)
+ {
+ case ISIS_MAC_0:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISIS_MAC_5:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISIS_MAC_6:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ *value = reg;
+
+ return rv;
+}
+
+
+
/**
* @brief Set 802.3az status on a particular port.
* @param[in] dev_id device id
@@ -1511,6 +1602,79 @@
return rv;
}
+/**
+ * @brief Get mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_pad_get(dev_id, port_num, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_pad_set(dev_id,port_num,value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_sgmii_get(dev_id, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isis_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isis_interface_mac_sgmii_set(dev_id, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
sw_error_t
isis_interface_ctrl_init(a_uint32_t dev_id)
{
@@ -1528,6 +1692,10 @@
p_api->interface_mac_mode_get = isis_interface_mac_mode_get;
p_api->interface_phy_mode_set = isis_interface_phy_mode_set;
p_api->interface_phy_mode_get = isis_interface_phy_mode_get;
+ p_api->interface_mac_pad_get = isis_interface_mac_pad_get;
+ p_api->interface_mac_pad_set = isis_interface_mac_pad_set;
+ p_api->interface_mac_sgmii_get = isis_interface_mac_sgmii_get;
+ p_api->interface_mac_sgmii_set = isis_interface_mac_sgmii_set;
}
#endif
diff --git a/src/hsl/isis/isis_port_ctrl.c b/src/hsl/isis/isis_port_ctrl.c
index a366c57..e79edba 100755
--- a/src/hsl/isis/isis_port_ctrl.c
+++ b/src/hsl/isis/isis_port_ctrl.c
@@ -43,7 +43,7 @@
fal_port_duplex_t duplex)
{
sw_error_t rv;
- a_uint32_t phy_id, reg_save, reg_val, force;
+ a_uint32_t phy_id, reg_save, reg_val, force, tmp;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
@@ -64,6 +64,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val);
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -71,10 +72,14 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
if (FAL_HALF_DUPLEX == duplex)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
}
else
{
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
}
reg_save = reg_val;
@@ -82,6 +87,12 @@
else
{
/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+ rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp);
+ SW_RTN_ON_ERROR(rv);
+ if (tmp == duplex)
+ return SW_OK;
reg_save = reg_val;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
@@ -90,8 +101,6 @@
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
- rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
- SW_RTN_ON_ERROR(rv);
rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
SW_RTN_ON_ERROR(rv);
@@ -149,7 +158,7 @@
fal_port_speed_t speed)
{
sw_error_t rv;
- a_uint32_t phy_id, reg_save, reg_val, force;
+ a_uint32_t phy_id, reg_save, reg_val, force, tmp;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
@@ -170,6 +179,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val);
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -177,14 +187,20 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
if (FAL_SPEED_10 == speed)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
}
else if (FAL_SPEED_100 == speed)
{
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
}
else
{
+ if (tmp == 2)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
}
reg_save = reg_val;
@@ -193,6 +209,12 @@
else
{
/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+ rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp);
+ SW_RTN_ON_ERROR(rv);
+ if (tmp == speed)
+ return SW_OK;
reg_save = reg_val;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
@@ -201,9 +223,6 @@
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
- rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
- SW_RTN_ON_ERROR(rv);
-
rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
SW_RTN_ON_ERROR(rv);
@@ -410,7 +429,7 @@
_isis_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, force, reg;
+ a_uint32_t val, force, reg, tmp;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -440,10 +459,13 @@
/* flow control isn't in force mode so can't set */
return SW_DISABLE;
}
+ tmp = reg;
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
@@ -485,7 +507,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg;
+ a_uint32_t reg, tmp;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -495,9 +517,12 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
if (A_TRUE == enable)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
}
else if (A_FALSE == enable)
@@ -507,6 +532,8 @@
{
return SW_DISABLE;
}
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
}
else
@@ -889,7 +916,7 @@
_isis_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -914,6 +941,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -934,7 +962,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -973,7 +1002,7 @@
_isis_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -998,6 +1027,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -1018,7 +1048,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1057,7 +1088,7 @@
_isis_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1082,6 +1113,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -1102,7 +1134,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
}
}
-
+ if ( tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1141,7 +1174,7 @@
_isis_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1166,6 +1199,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
@@ -1186,7 +1220,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
}
}
-
+ if ( tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1225,7 +1260,7 @@
_isis_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val;
+ a_uint32_t val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1246,7 +1281,10 @@
{
return SW_BAD_PARAM;
}
-
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ if (tmp == val)
+ return SW_OK;
HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
return rv;
@@ -1285,7 +1323,7 @@
_isis_port_link_forcemode_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg;
+ a_uint32_t reg, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1297,13 +1335,18 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, LINK_EN, tmp, reg);
if (A_TRUE == enable)
{
+ if(tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg);
}
else if (A_FALSE == enable)
{
+ if(tmp == 1)
+ return SW_OK;
/* for those ports without PHY, it can't sync link status */
if (A_FALSE == _isis_port_phy_connected(dev_id, port_id))
{
diff --git a/src/hsl/isisc/isisc_interface_ctrl.c b/src/hsl/isisc/isisc_interface_ctrl.c
index a0bb4bb..cb419d2 100755
--- a/src/hsl/isisc/isisc_interface_ctrl.c
+++ b/src/hsl/isisc/isisc_interface_ctrl.c
@@ -437,6 +437,97 @@
return rv;
}
+
+static sw_error_t
+_isisc_interface_mac_sgmii_set(a_uint32_t dev_id,a_uint32_t value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+ reg = value;
+
+ HSL_REG_ENTRY_SET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t *value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ HSL_REG_ENTRY_GET(rv, dev_id, SGMII_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+
+ SW_RTN_ON_ERROR(rv);
+
+ *value = reg;
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ reg = value;
+
+ switch (port_num)
+ {
+ case ISISC_MAC_0:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISISC_MAC_5:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISISC_MAC_6:
+ HSL_REG_ENTRY_SET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+
+ return rv;
+}
+
+static sw_error_t
+_isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t *value)
+{
+ sw_error_t rv;
+ a_uint32_t reg;
+
+ switch (port_num)
+ {
+ case ISISC_MAC_0:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT0_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISISC_MAC_5:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT5_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ case ISISC_MAC_6:
+ HSL_REG_ENTRY_GET(rv, dev_id, PORT6_PAD_CTRL, 0,
+ (a_uint8_t *) (®), sizeof (a_uint32_t));
+ break;
+ default:
+ return SW_BAD_PARAM;
+ }
+ SW_RTN_ON_ERROR(rv);
+
+ *value = reg;
+
+ return rv;
+}
+
+
+
static sw_error_t
_isisc_port_rmii_mode_set(a_uint32_t dev_id, fal_port_t port_id, fal_mac_rmii_config_t * config)
{
@@ -2120,6 +2211,79 @@
return rv;
}
+/**
+ * @brief Get mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_pad_get(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t* value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_pad_get(dev_id, port_num, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set mac pad configuration.
+ * @param[in] dev_id device id
+ * @param[in] port_num port num
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_pad_set(a_uint32_t dev_id,a_uint32_t port_num, a_uint32_t value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_pad_set(dev_id,port_num,value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+/**
+ * @brief Get mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[out] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_sgmii_get(a_uint32_t dev_id, a_uint32_t* value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_sgmii_get(dev_id, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
+/**
+ * @brief Set mac SGMII configuration.
+ * @param[in] dev_id device id
+ * @param[in] config value
+ * @return SW_OK or error code
+ */
+HSL_LOCAL sw_error_t
+isisc_interface_mac_sgmii_set(a_uint32_t dev_id, a_uint32_t value)
+{
+ sw_error_t rv;
+
+ HSL_API_LOCK;
+ rv = _isisc_interface_mac_sgmii_set(dev_id, value);
+ HSL_API_UNLOCK;
+ return rv;
+}
+
+
sw_error_t
isisc_interface_ctrl_init(a_uint32_t dev_id)
{
@@ -2142,6 +2306,10 @@
p_api->interface_fx100_status_get = isisc_interface_fx100_status_get;
p_api->interface_mac06_exch_set = isisc_interface_mac06_exch_set;
p_api->interface_mac06_exch_get = isisc_interface_mac06_exch_get;
+ p_api->interface_mac_pad_get = isisc_interface_mac_pad_get;
+ p_api->interface_mac_pad_set = isisc_interface_mac_pad_set;
+ p_api->interface_mac_sgmii_get = isisc_interface_mac_sgmii_get;
+ p_api->interface_mac_sgmii_set = isisc_interface_mac_sgmii_set;
}
#endif
diff --git a/src/hsl/isisc/isisc_port_ctrl.c b/src/hsl/isisc/isisc_port_ctrl.c
index e66c306..b6c168c 100755
--- a/src/hsl/isisc/isisc_port_ctrl.c
+++ b/src/hsl/isisc/isisc_port_ctrl.c
@@ -42,7 +42,7 @@
fal_port_duplex_t duplex)
{
sw_error_t rv;
- a_uint32_t phy_id, reg_save, reg_val, force;
+ a_uint32_t phy_id, reg_save, reg_val, force, tmp;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
@@ -63,6 +63,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, DUPLEX_MODE, tmp, reg_val);
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -70,10 +71,14 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
if (FAL_HALF_DUPLEX == duplex)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 0, reg_val);
}
else
{
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, DUPLEX_MODE, 1, reg_val);
}
reg_save = reg_val;
@@ -81,6 +86,12 @@
else
{
/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+ rv = phy_drv->phy_duplex_get (dev_id, phy_id, &tmp);
+ SW_RTN_ON_ERROR(rv);
+ if (tmp == duplex)
+ return SW_OK;
reg_save = reg_val;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
@@ -89,9 +100,6 @@
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
- rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
- SW_RTN_ON_ERROR(rv);
-
rv = phy_drv->phy_duplex_set (dev_id, phy_id, duplex);
SW_RTN_ON_ERROR(rv);
@@ -150,7 +158,7 @@
fal_port_speed_t speed)
{
sw_error_t rv;
- a_uint32_t phy_id, reg_save, reg_val, force;
+ a_uint32_t phy_id, reg_save, reg_val, force, tmp;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
@@ -171,6 +179,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
+ SW_GET_FIELD_BY_REG(PORT_STATUS, SPEED_MODE, tmp, reg_val);
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -178,14 +187,20 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
if (FAL_SPEED_10 == speed)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 0, reg_val);
}
else if (FAL_SPEED_100 == speed)
{
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 1, reg_val);
}
else
{
+ if (tmp == 2)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, SPEED_MODE, 2, reg_val);
}
reg_save = reg_val;
@@ -194,6 +209,12 @@
else
{
/* hardware requirement: set mac be config by sw and turn off RX/TX MAC */
+ rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
+ SW_RTN_ON_ERROR(rv);
+ rv = phy_drv->phy_speed_get (dev_id, phy_id, &tmp);
+ SW_RTN_ON_ERROR(rv);
+ if (tmp == speed)
+ return SW_OK;
reg_save = reg_val;
SW_SET_REG_BY_FIELD(PORT_STATUS, LINK_EN, 0, reg_val);
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, 0, reg_val);
@@ -202,8 +223,6 @@
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
- rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
- SW_RTN_ON_ERROR(rv);
rv = phy_drv->phy_speed_set (dev_id, phy_id, speed);
SW_RTN_ON_ERROR(rv);
@@ -411,7 +430,7 @@
_isisc_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, force, reg;
+ a_uint32_t val, force, reg, tmp;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -441,10 +460,13 @@
/* flow control isn't in force mode so can't set */
return SW_DISABLE;
}
+ tmp = reg;
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
@@ -486,7 +508,7 @@
a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg;
+ a_uint32_t reg, tmp;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -496,9 +518,12 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ SW_GET_FIELD_BY_REG(PORT_STATUS, FLOW_LINK_EN, tmp, reg);
if (A_TRUE == enable)
{
+ if (tmp == 0)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 0, reg);
}
else if (A_FALSE == enable)
@@ -508,6 +533,8 @@
{
return SW_DISABLE;
}
+ if (tmp == 1)
+ return SW_OK;
SW_SET_REG_BY_FIELD(PORT_STATUS, FLOW_LINK_EN, 1, reg);
}
else
@@ -890,7 +917,7 @@
_isisc_port_txmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -915,6 +942,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -935,7 +963,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, TXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -974,7 +1003,7 @@
_isisc_port_rxmac_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t reg, force, val;
+ a_uint32_t reg, force, val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -999,6 +1028,7 @@
{
return SW_BAD_PARAM;
}
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -1019,7 +1049,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, RXMAC_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1058,7 +1089,7 @@
_isisc_port_txfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1083,6 +1114,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -1103,7 +1135,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
}
}
-
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1142,7 +1175,7 @@
_isisc_port_rxfc_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, reg, force;
+ a_uint32_t val, reg, force, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1167,6 +1200,7 @@
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
SW_RTN_ON_ERROR(rv);
+ tmp = reg;
/* for those ports without PHY device we set MAC register */
if (A_FALSE == _isisc_port_phy_connected(dev_id, port_id))
@@ -1187,7 +1221,8 @@
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
}
}
-
+ if ( tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
return rv;
@@ -1226,7 +1261,7 @@
_isisc_port_bp_status_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val;
+ a_uint32_t val, tmp;
HSL_DEV_ID_CHECK(dev_id);
@@ -1247,6 +1282,10 @@
{
return SW_BAD_PARAM;
}
+ HSL_REG_FIELD_GET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
+ (a_uint8_t *) (&tmp), sizeof (a_uint32_t));
+ if (tmp == val)
+ return SW_OK;
HSL_REG_FIELD_SET(rv, dev_id, PORT_STATUS, port_id, TX_HALF_FLOW_EN,
(a_uint8_t *) (&val), sizeof (a_uint32_t));
diff --git a/src/hsl/shiva/shiva_port_ctrl.c b/src/hsl/shiva/shiva_port_ctrl.c
index 0442550..7976bd9 100755
--- a/src/hsl/shiva/shiva_port_ctrl.c
+++ b/src/hsl/shiva/shiva_port_ctrl.c
@@ -33,7 +33,7 @@
sw_error_t rv;
a_uint32_t phy_id = 0;
a_uint32_t reg_save = 0;
- a_uint32_t reg_val = 0;
+ a_uint32_t reg_val = 0, tmp;
hsl_phy_ops_t *phy_drv;
HSL_DEV_ID_CHECK(dev_id);
@@ -55,6 +55,11 @@
rv = hsl_port_prop_get_phyid(dev_id, port_id, &phy_id);
SW_RTN_ON_ERROR(rv);
+ rv = phy_drv->phy_duplex_get(dev_id, phy_id, &tmp);
+ SW_RTN_ON_ERROR(rv);
+ if (tmp == duplex)
+ return SW_OK;
+
//save reg value
HSL_REG_ENTRY_GET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®_val), sizeof (a_uint32_t));
@@ -362,7 +367,7 @@
_shiva_port_flowctrl_set(a_uint32_t dev_id, fal_port_t port_id, a_bool_t enable)
{
sw_error_t rv;
- a_uint32_t val, force, reg;
+ a_uint32_t val, force, reg, tmp;
if (A_TRUE != hsl_port_prop_check(dev_id, port_id, HSL_PP_INCL_CPU))
{
@@ -392,10 +397,13 @@
/* flow control isn't in force mode so can't set */
return SW_DISABLE;
}
+ tmp = reg;
SW_SET_REG_BY_FIELD(PORT_STATUS, RX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_FLOW_EN, val, reg);
SW_SET_REG_BY_FIELD(PORT_STATUS, TX_HALF_FLOW_EN, val, reg);
+ if (tmp == reg)
+ return SW_OK;
HSL_REG_ENTRY_SET(rv, dev_id, PORT_STATUS, port_id,
(a_uint8_t *) (®), sizeof (a_uint32_t));
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index ffc36d6..7bc177d 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -233,17 +233,22 @@
void
qca_mac_disable()
{
- qca_ar8216_mii_write(AR8327_REG_PAD0_CTRL, 0);
- qca_ar8216_mii_write(AR8327_REG_PAD5_CTRL, 0);
- qca_ar8216_mii_write(AR8327_REG_PAD6_CTRL, 0);
- qca_ar8216_mii_write(AR8327_REG_PAD_SGMII_CTRL, AR8327_REG_PAD_SGMII_CTRL_HW_INIT);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(0), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(1), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(2), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(3), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(4), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(5), 0);
- qca_ar8216_mii_write(AR8327_REG_PORT_STATUS(6), 0);
+ hsl_api_t *p_api;
+
+ p_api = hsl_api_ptr_get (0);
+ if(p_api
+ && p_api->interface_mac_pad_set
+ && p_api->interface_mac_sgmii_set)
+ {
+ p_api->interface_mac_pad_set(0,0,0);
+ p_api->interface_mac_pad_set(0,5,0);
+ p_api->interface_mac_pad_set(0,6,0);
+ p_api->interface_mac_sgmii_set(0,AR8327_REG_PAD_SGMII_CTRL_HW_INIT);
+ }
+ else
+ {
+ printk("API not support \n");
+ }
}
@@ -1792,13 +1797,7 @@
{
sw_error_t rv;
- #ifndef BOARD_AR71XX
- if(ssdk_dt_global.switch_reg_access_mode == HSL_REG_MDIO) {
- qca_ar8327_phy_disable();
- qca_mac_disable();
- msleep(1000);
- }
- #endif
+
#if (defined(KERNEL_MODULE) && defined(USER_MODE))
rv = hsl_dev_init(dev_id, cfg);
@@ -1812,7 +1811,19 @@
#endif
#endif
- ssdk_phy_init(cfg);
+ ssdk_phy_init(cfg);
+
+
+#ifndef BOARD_AR71XX
+ if(ssdk_dt_global.switch_reg_access_mode == HSL_REG_MDIO) {
+ qca_ar8327_phy_disable();
+ qca_mac_disable();
+ msleep(1000);
+ }
+#endif
+
+
+
if (cfg->chip_type == CHIP_DESS)
ssdk_psgmii_self_test();