commit 80d2febec27a7f0bd43284c4b4e87e5a56e59a91
author esong <song@codeaurora.org> Mon Jul 22 11:31:40 2019 +0800
committer Gerrit - the friendly Code Review server <code-review@localhost> Mon Jul 22 19:31:53 2019 -0700
tree 850325cdc92cf7985a246f0d8e9ab6f3ed1a4b6e
parent 7235b2e0dd91663f455528f6683654d227e356ae

[qca-ssdk] fix cypress printing issue and update printing log level

Change-Id: I4f8e75f996961e2e51077b6208001cf343715728
Signed-off-by: esong <song@codeaurora.org>

src/adpt/cppe/adpt_cppe_uniphy.c

diff --git a/src/adpt/cppe/adpt_cppe_uniphy.c b/src/adpt/cppe/adpt_cppe_uniphy.c
index 7bbb3f0..a3cec58 100755
--- a/src/adpt/cppe/adpt_cppe_uniphy.c
+++ b/src/adpt/cppe/adpt_cppe_uniphy.c
@@ -291,11 +291,11 @@
 				SSDK_PHYSICAL_PORT4, A_TRUE);
 	}
 	if (mode == PORT_WRAPPER_PSGMII) {
-		SSDK_INFO("cypress uniphy %d psgmii configuration is done!\n", uniphy_index);
-	} else if (PORT_WRAPPER_SGMII_CHANNEL0) {
-		SSDK_INFO("cypress uniphy %d sgmii configuration is done!\n", uniphy_index);
+		SSDK_DEBUG("cypress uniphy %d psgmii configuration is done!\n", uniphy_index);
+	} else if (mode == PORT_WRAPPER_SGMII_CHANNEL0) {
+		SSDK_DEBUG("cypress uniphy %d sgmii configuration is done!\n", uniphy_index);
 	} else {
-		SSDK_INFO("cypress uniphy %d sgmiiplus configuration is done!\n", uniphy_index);
+		SSDK_DEBUG("cypress uniphy %d sgmiiplus configuration is done!\n", uniphy_index);
 	}
 
 	return rv;

src/adpt/hppe/adpt_hppe_uniphy.c

diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
index a422d5c..8242f37 100755
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -308,7 +308,7 @@
 #if defined(CPPE)
 	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
 		&& (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
-		SSDK_INFO("cypress uniphy %d is sgmiiplus mode\n", uniphy_index);
+		SSDK_DEBUG("cypress uniphy %d is sgmiiplus mode\n", uniphy_index);
 		rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
 			PORT_WRAPPER_SGMII_PLUS);
 		return rv;
@@ -386,7 +386,7 @@
 		if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
 			if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4,
 					HSL_PP_EXCL_CPU) == A_TRUE) {
-				SSDK_INFO("cypress uniphy %d is sgmii mode\n", uniphy_index);
+				SSDK_DEBUG("cypress uniphy %d is sgmii mode\n", uniphy_index);
 				rv = __adpt_cppe_uniphy_mode_set(dev_id,
 					uniphy_index, PORT_WRAPPER_SGMII_CHANNEL0);
 				return rv;
@@ -424,7 +424,7 @@
 #if defined(CPPE)
 	if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
 		(uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
-		SSDK_INFO("uniphy %d sgmii channel selection\n", uniphy_index);
+		SSDK_DEBUG("uniphy %d sgmii channel selection\n", uniphy_index);
 		rv = __adpt_cppe_uniphy_channel_selection_set(dev_id,
 			CPPE_PCS0_CHANNEL0_SEL_PSGMII,
 			CPPE_PCS0_CHANNEL4_SEL_PORT5_CLOCK);