Merge "[qca-ssdk] add cypress uniphy debug infor"
diff --git a/src/adpt/cppe/adpt_cppe_uniphy.c b/src/adpt/cppe/adpt_cppe_uniphy.c
index 2a0687a..a35b1c8 100755
--- a/src/adpt/cppe/adpt_cppe_uniphy.c
+++ b/src/adpt/cppe/adpt_cppe_uniphy.c
@@ -116,6 +116,7 @@
ADPT_DEV_ID_CHECK(dev_id);
if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+ SSDK_ERROR("uniphy index is %d\n", uniphy_index);
return SW_BAD_VALUE;
}
@@ -179,6 +180,7 @@
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
i, A_TRUE);
}
+ SSDK_INFO("cypress uniphy %d psgmii configuration is done!\n", uniphy_index);
return rv;
}
@@ -201,6 +203,7 @@
ADPT_DEV_ID_CHECK(dev_id);
if (uniphy_index != SSDK_UNIPHY_INSTANCE0) {
+ SSDK_ERROR("uniphy index is %d\n", uniphy_index);
return SW_BAD_VALUE;
}
@@ -273,6 +276,7 @@
/* enable instance clock */
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
SSDK_PHYSICAL_PORT4, A_TRUE);
+ SSDK_INFO("cypress uniphy %d sgmii configuration is done!\n", uniphy_index);
return rv;
}
@@ -361,6 +365,7 @@
/* enable instance clock */
qca_gcc_uniphy_port_clock_set(dev_id, uniphy_index,
SSDK_PHYSICAL_PORT4, A_TRUE);
+ SSDK_INFO("cypress uniphy %d sgmiiplus configuration is done!\n", uniphy_index);
return rv;
}
diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c
index ea6aef9..46241b8 100755
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -79,7 +79,7 @@
mdelay(1);
if (retries-- == 0)
{
- printk("uniphy callibration time out!\n");
+ SSDK_ERROR("uniphy callibration time out!\n");
return SW_TIMEOUT;
}
reg_value = 0;
@@ -301,9 +301,11 @@
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+ SSDK_DEBUG("uniphy %d is sgmiiplus mode\n", uniphy_index);
#if defined(CPPE)
if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION)
&& (uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ SSDK_INFO("cypress uniphy %d is sgmiiplus mode\n", uniphy_index);
rv = __adpt_cppe_uniphy_sgmiiplus_mode_set(dev_id, uniphy_index);
return rv;
}
@@ -367,12 +369,14 @@
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+ SSDK_DEBUG("uniphy %d is sgmii mode\n", uniphy_index);
#if defined(CPPE)
if ((uniphy_index == SSDK_UNIPHY_INSTANCE0) &&
(channel == SSDK_UNIPHY_CHANNEL0)) {
if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
if (hsl_port_prop_check(dev_id, SSDK_PHYSICAL_PORT4,
HSL_PP_EXCL_CPU) == A_TRUE) {
+ SSDK_INFO("cypress uniphy %d is sgmii mode\n", uniphy_index);
rv = __adpt_cppe_uniphy_sgmii_mode_set(dev_id,
uniphy_index);
return rv;
@@ -410,6 +414,7 @@
#if defined(CPPE)
if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
(uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ SSDK_INFO("uniphy %d sgmii channel selection\n", uniphy_index);
rv = __adpt_cppe_uniphy_channel_selection_set(dev_id);
SW_RTN_ON_ERROR (rv);
}
@@ -561,11 +566,13 @@
memset(&uniphy_mode_ctrl, 0, sizeof(uniphy_mode_ctrl));
ADPT_DEV_ID_CHECK(dev_id);
+ SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
#if defined(CPPE)
if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
phy_type = hsl_port_phyid_get(dev_id,
SSDK_PHYSICAL_PORT3);
if (phy_type == MALIBU2PORT_PHY) {
+ SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
rv = __adpt_cppe_uniphy_connection_qca8072_set(dev_id,
uniphy_index);
return rv;
@@ -586,6 +593,7 @@
#if defined(CPPE)
if ((adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) &&
(uniphy_index == SSDK_UNIPHY_INSTANCE0)) {
+ SSDK_INFO("uniphy %d psgmii channel selection\n", uniphy_index);
rv = __adpt_cppe_uniphy_channel_selection_set(dev_id);
SW_RTN_ON_ERROR (rv);
}