Merge "[qca-ssdk]: add gcc ppe clock init"
diff --git a/include/init/ssdk_init.h b/include/init/ssdk_init.h
index 7eb1ffd..566772b 100755
--- a/include/init/ssdk_init.h
+++ b/include/init/ssdk_init.h
@@ -245,6 +245,8 @@
a_uint8_t *uniphy_access_mode;
hsl_reg_mode uniphy_reg_access_mode;
ssdk_dt_scheduler_cfg scheduler_cfg;
+ a_uint8_t bm_tick_mode;
+ a_uint8_t tm_tick_mode;
} ssdk_dt_cfg;
#if defined ATHENA
diff --git a/src/adpt/hppe/adpt_hppe_portctrl.c b/src/adpt/hppe/adpt_hppe_portctrl.c
index df97926..4dbfb26 100755
--- a/src/adpt/hppe/adpt_hppe_portctrl.c
+++ b/src/adpt/hppe/adpt_hppe_portctrl.c
@@ -3132,9 +3132,9 @@
portbmp[priv->device_id] = qca_ssdk_port_bmp_get(priv->device_id);
- for (port_id = 0; port_id < SW_MAX_NR_DEV; port_id ++) {
+ for (port_id = 1; port_id < SW_MAX_NR_DEV; port_id ++) {
- if(!(portbmp[priv->device_id] & (0x1 << i)))
+ if(!(portbmp[priv->device_id] & (0x1 << port_id)))
continue;
adpt_hppe_port_phy_status_get(priv->device_id, port_id, &phy_status);
@@ -3174,7 +3174,7 @@
adpt_hppe_port_mac_speed_set(priv->device_id, port_id, phy_status.speed);
priv->port_old_speed[port_id - 1] = (a_uint32_t)phy_status.speed;
}
- if ((a_uint32_t)phy_status.duplex != priv->hppe_port_duplex[port_id - 1])
+ if ((a_uint32_t)phy_status.duplex != priv->port_old_duplex[port_id - 1])
{
adpt_hppe_uniphy_duplex_set(priv->device_id, port_id, phy_status.duplex);
adpt_hppe_port_mac_duplex_set(priv->device_id, port_id, phy_status.duplex);
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index 6d84abc..c24a236 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -1303,6 +1303,19 @@
#endif
void
+qca_mac_sw_sync_port_status_init(struct qca_phy_priv *priv)
+{
+ a_uint32_t port_id;
+
+ for (port_id = 1; port_id < AR8327_NUM_PORTS; port_id ++) {
+ priv->port_old_link[port_id - 1] = 0;
+ priv->port_old_speed[port_id - 1] = FAL_SPEED_BUTT;
+ priv->port_old_duplex[port_id - 1] = FAL_DUPLEX_BUTT;
+ priv->port_old_tx_flowctrl[port_id - 1] = 0;
+ priv->port_old_rx_flowctrl[port_id - 1] = 0;
+ }
+}
+void
qca_mac_sw_sync_work_task(struct work_struct *work)
{
adpt_api_t *p_adpt_api;
@@ -1330,6 +1343,8 @@
if (priv->version != QCA_VER_HPPE)
return -1;
+ qca_mac_sw_sync_port_status_init(priv);
+
mutex_init(&priv->mac_sw_sync_lock);
INIT_DELAYED_WORK(&priv->mac_sw_sync_dwork,
@@ -1463,7 +1478,6 @@
struct qca_phy_priv *priv;
int ret = 0;
a_uint32_t chip_id = 0;
-
priv = qca_phy_priv_global;
priv->mii_read = qca_ar8216_mii_read;
@@ -1480,19 +1494,6 @@
SSDK_INFO("Chip version 0x%02x%02x\n", priv->version, priv->revision);
}
-#ifdef HAWKEYE_CHIP
- if (priv->version == QCA_VER_HPPE)
- {
- priv->port_old_link[AR8327_NUM_PORTS] = {0};
- priv->port_old_speed[AR8327_NUM_PORTS] = {1000,
- 1000,1000,1000,1000,10000,1000};
- priv->port_old_duplex[AR8327_NUM_PORTS] = {1,
- 1,1,1,1,1,1};
- priv->port_old_tx_flowctrl[AR8327_NUM_PORTS] = {0};
- priv->port_old_rx_flowctrl[AR8327_NUM_PORTS] = {0};
- }
-#endif
-
mutex_init(&priv->reg_mutex);
sw_dev = &priv->sw_dev;
@@ -3311,7 +3312,7 @@
return 0;
}
-fal_port_scheduler_cfg_t port_scheduler_tbl[] = {
+fal_port_scheduler_cfg_t port_scheduler0_tbl[] = {
{0xee, 6, 0},
{0xde, 4, 5},
{0x9f, 0, 6},
@@ -3364,7 +3365,35 @@
{0xaf, 5, 4},
};
-fal_port_tdm_tick_cfg_t port_tdm_tbl[] = {
+fal_port_scheduler_cfg_t port_scheduler1_tbl[] = {
+ {0x27, 5, 6},
+ {0x0f, 0, 5},
+ {0x0f, 2, 6},
+ {0x0f, 3, 5},
+ {0x4e, 6, 0},
+ {0x2e, 5, 6},
+ {0x0f, 1, 5},
+ {0x0f, 0, 6},
+ {0x0f, 3, 5},
+ {0x4d, 6, 1},
+ {0x2d, 5, 6},
+ {0x0f, 1, 5},
+ {0x0f, 2, 6},
+ {0x0f, 0, 5},
+ {0x4e, 6, 0},
+ {0x2e, 5, 6},
+ {0x0f, 1, 5},
+ {0x0f, 0, 6},
+ {0x0f, 3, 5},
+ {0x4b, 6, 2},
+ {0x2b, 5, 6},
+ {0x0f, 1, 5},
+ {0x0f, 2, 6},
+ {0x0f, 0, 5},
+ {0x47, 6, 3},
+};
+
+fal_port_tdm_tick_cfg_t port_tdm0_tbl[] = {
{1, FAL_PORT_TDB_DIR_INGRESS, 5},
{1, FAL_PORT_TDB_DIR_EGRESS, 5},
{1, FAL_PORT_TDB_DIR_INGRESS, 0},
@@ -3467,13 +3496,114 @@
{1, FAL_PORT_TDB_DIR_EGRESS, 7},
};
+fal_port_tdm_tick_cfg_t port_tdm1_tbl[] = {
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 1},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 3},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 2},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 1},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 3},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 2},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+};
+
static int
qca_hppe_tdm_hw_init(void)
{
adpt_api_t *p_api;
a_uint32_t i = 0;
- a_uint32_t num = sizeof(port_scheduler_tbl) / sizeof(fal_port_scheduler_cfg_t);
+ a_uint32_t num;
fal_port_tdm_ctrl_t tdm_ctrl;
+ fal_port_scheduler_cfg_t *scheduler_cfg;
+ fal_port_tdm_tick_cfg_t *bm_cfg;
p_api = adpt_api_ptr_get(0);
if (!p_api)
@@ -3483,23 +3613,45 @@
!p_api->adpt_tdm_tick_num_set)
return SW_FAIL;
+ if (ssdk_dt_global.tm_tick_mode == 0) {
+ num = sizeof(port_scheduler0_tbl) / sizeof(fal_port_scheduler_cfg_t);
+ scheduler_cfg = port_scheduler0_tbl;
+ } else if (ssdk_dt_global.tm_tick_mode == 1) {
+ num = sizeof(port_scheduler1_tbl) / sizeof(fal_port_scheduler_cfg_t);
+ scheduler_cfg = port_scheduler1_tbl;
+ } else {
+ return SW_BAD_VALUE;
+ }
+
for (i = 0; i < num; i++) {
- p_api->adpt_port_scheduler_cfg_set(0, i, &port_scheduler_tbl[i]);
+ p_api->adpt_port_scheduler_cfg_set(0, i, &scheduler_cfg[i]);
}
p_api->adpt_tdm_tick_num_set(0, num);
- num = sizeof(port_tdm_tbl) / sizeof(fal_port_tdm_tick_cfg_t);
+ if (!p_api->adpt_port_tdm_tick_cfg_set ||
+ !p_api->adpt_port_tdm_ctrl_set)
+ return SW_FAIL;
+ if (ssdk_dt_global.bm_tick_mode == 0) {
+ num = sizeof(port_tdm0_tbl) / sizeof(fal_port_tdm_tick_cfg_t);
+ bm_cfg = port_tdm0_tbl;
+ } else if (ssdk_dt_global.bm_tick_mode == 1) {
+ num = sizeof(port_tdm1_tbl) / sizeof(fal_port_tdm_tick_cfg_t);
+ bm_cfg = port_tdm1_tbl;
+ } else {
+ return SW_BAD_VALUE;
+ }
for (i = 0; i < num; i++) {
- p_api->adpt_port_tdm_tick_cfg_set(0, i, &port_tdm_tbl[i]);
+ p_api->adpt_port_tdm_tick_cfg_set(0, i, &bm_cfg[i]);
}
tdm_ctrl.enable = 1;
tdm_ctrl.offset = 0;
- tdm_ctrl.depth = 100;
+ tdm_ctrl.depth = num;
p_api->adpt_port_tdm_ctrl_set(0, &tdm_ctrl);
SSDK_INFO("tdm setup num=%d\n", num);
return 0;
}
+#ifndef HAWKEYE_CHIP
static int
qca_hppe_xgmac_hw_init(void)
{
@@ -3533,6 +3685,7 @@
return 0;
}
+#endif
static int
qca_hppe_bm_hw_init(void)
{
@@ -4180,9 +4333,11 @@
static int
qca_hppe_hw_init(ssdk_init_cfg *cfg)
{
- a_uint32_t val, i = 0;
+ a_uint32_t val;
void __iomem *ppe_gpio_base;
-
+ #ifndef HAWKEYE_CHIP
+ a_uint32_t i = 0;
+ #endif
qca_switch_init(0);