Merge "[qca-ssdk]: change the inappropriate print info."
diff --git a/include/init/ssdk_clk.h b/include/init/ssdk_clk.h
index 04384d3..46a3438 100644
--- a/include/init/ssdk_clk.h
+++ b/include/init/ssdk_clk.h
@@ -19,6 +19,29 @@
extern "C" {
#endif /* __cplusplus */
+#define PPE_RESET_ID "ppe_rst"
+#define UNIPHY0_SOFT_RESET_ID "uniphy0_soft_rst"
+#define UNIPHY0_XPCS_RESET_ID "uniphy0_xpcs_rst"
+#define UNIPHY1_SOFT_RESET_ID "uniphy1_soft_rst"
+#define UNIPHY1_XPCS_RESET_ID "uniphy1_xpcs_rst"
+#define UNIPHY2_SOFT_RESET_ID "uniphy2_soft_rst"
+#define UNIPHY2_XPCS_RESET_ID "uniphy2_xpcs_rst"
+
+enum ssdk_rst_action {
+ SSDK_RESET_DEASSERT = 0,
+ SSDK_RESET_ASSERT = 1
+};
+
+enum unphy_rst_type {
+ UNIPHY0_SOFT_RESET_E = 0,
+ UNIPHY0_XPCS_RESET_E,
+ UNIPHY1_SOFT_RESET_E,
+ UNIPHY1_XPCS_RESET_E,
+ UNIPHY2_SOFT_RESET_E,
+ UNIPHY2_XPCS_RESET_E,
+ UNIPHY_RST_MAX
+};
+
#define CMN_AHB_CLK "cmn_ahb_clk"
#define CMN_SYS_CLK "cmn_sys_clk"
#define UNIPHY0_AHB_CLK "uniphy0_ahb_clk"
@@ -76,7 +99,7 @@
#define UNIPHY2_PORT6_RX_CLK "uniphy2_port6_rx_clk"
#define UNIPHY2_PORT6_TX_CLK "uniphy2_port6_tx_clk"
#define PORT5_RX_SRC "nss_port5_rx_clk_src"
-#define PORT5_TX_SRC "nss_port5_rx_clk_src"
+#define PORT5_TX_SRC "nss_port5_tx_clk_src"
enum unphy_clk_type {
NSS_PORT1_RX_CLK_E = 0,
@@ -147,6 +170,11 @@
UNIPHY_TX,
};
+void ssdk_uniphy_reset(
+ a_uint32_t dev_id,
+ enum unphy_rst_type rst_type,
+ a_uint32_t action);
+
#if defined(HPPE)
void
qca_gcc_mac_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id,
@@ -165,6 +193,8 @@
a_uint32_t dev_id,
a_uint32_t port_id,
a_uint32_t rate);
+
+void ssdk_ppe_reset_init(void);
#endif
#ifdef __cplusplus
diff --git a/src/init/ssdk_clk.c b/src/init/ssdk_clk.c
index a884779..558586a 100644
--- a/src/init/ssdk_clk.c
+++ b/src/init/ssdk_clk.c
@@ -31,6 +31,9 @@
struct device_node *clock_node = NULL;
static struct clk *uniphy_port_clks[UNIPHYT_CLK_MAX] = {0};
+struct device_node *rst_node = NULL;
+struct reset_control *uniphy_rsts[UNIPHY_RST_MAX] = {0};
+
/* below 3 routines to be used as common */
void ssdk_clock_rate_set_and_enable(
struct device_node *node, a_uint8_t* clock_id, a_uint32_t rate)
@@ -45,8 +48,36 @@
clk_prepare_enable(clk);
}
}
+
+void ssdk_gcc_reset(struct reset_control *rst, a_uint32_t action)
+{
+ if (action == SSDK_RESET_ASSERT)
+ reset_control_assert(rst);
+ else
+ reset_control_deassert(rst);
+
+}
#endif
+void ssdk_uniphy_reset(
+ a_uint32_t dev_id,
+ enum unphy_rst_type rst_type,
+ a_uint32_t action)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+ struct reset_control *rst;
+
+ rst = uniphy_rsts[rst_type];
+ if (IS_ERR(rst)) {
+ SSDK_ERROR("reset(%d) nof exist!\n", rst_type);
+ return;
+ }
+
+ ssdk_gcc_reset(rst, action);
+#endif
+
+}
+
void ssdk_uniphy_clock_rate_set(
a_uint32_t dev_id,
enum unphy_clk_type clock_type,
@@ -91,6 +122,8 @@
/* below special for ppe */
#if defined(HPPE)
+static a_bool_t uniphy1_status = A_FALSE;
+
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
struct clk_uniphy {
struct clk_hw hw;
@@ -358,6 +391,17 @@
}
#endif
+static
+void ssdk_uniphy1_clock_source_set(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+ clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E],
+ uniphy_raw_clks[2]->clk);
+ clk_set_parent(uniphy_port_clks[PORT5_TX_SRC_E],
+ uniphy_raw_clks[3]->clk);
+#endif
+}
+
void ssdk_ppe_clock_init(void)
{
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
@@ -388,10 +432,12 @@
id = uniphy_index*2 + direction;
old_clock = clk_get_rate(uniphy_raw_clks[id]->clk);
- if (uniphy_index == UNIPHY_INSTANCE_1)
+ if (uniphy_index == UNIPHY_INSTANCE_1) {
if (clk_set_parent(uniphy_port_clks[PORT5_RX_SRC_E + direction],
uniphy_raw_clks[id]->clk))
SSDK_ERROR("set parent fail!\n");
+ uniphy1_status = A_TRUE;
+ }
if (clock != old_clock) {
if (clk_set_rate(uniphy_raw_clks[id]->clk, clock))
@@ -562,6 +608,8 @@
NSS_PORT5_RX_CLK_E, rate);
ssdk_uniphy_clock_rate_set(dev_id,
NSS_PORT5_TX_CLK_E, rate);
+ if (uniphy1_status)
+ ssdk_uniphy1_clock_source_set();
break;
case SSDK_PORT6:
ssdk_uniphy_clock_rate_set(dev_id,
@@ -574,6 +622,40 @@
}
}
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+static char *ppe_rst_ids[UNIPHY_RST_MAX] = {
+ UNIPHY0_SOFT_RESET_ID,
+ UNIPHY0_XPCS_RESET_ID,
+ UNIPHY1_SOFT_RESET_ID,
+ UNIPHY1_XPCS_RESET_ID,
+ UNIPHY2_SOFT_RESET_ID,
+ UNIPHY2_XPCS_RESET_ID
+};
+#endif
+void ssdk_ppe_reset_init(void)
+{
+#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
+ struct reset_control *rst;
+ a_uint32_t i;
+
+ rst_node = of_find_node_by_name(NULL, "ess-switch");
+ rst = of_reset_control_get(rst_node, PPE_RESET_ID);
+ if (IS_ERR(rst)) {
+ SSDK_ERROR("%s not exist!\n", PPE_RESET_ID);
+ return;
+ }
+
+ ssdk_gcc_reset(rst, SSDK_RESET_ASSERT);
+ msleep(100);
+ ssdk_gcc_reset(rst, SSDK_RESET_DEASSERT);
+ msleep(100);
+ SSDK_INFO("ppe reset successfully!\n");
+
+ for (i = UNIPHY0_SOFT_RESET_E; i < UNIPHY_RST_MAX; i++)
+ uniphy_rsts[i] = of_reset_control_get(rst_node,
+ ppe_rst_ids[i]);
+#endif
+}
#endif
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index f3be7fc..1149181 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -4074,26 +4074,13 @@
return SW_OK;
}
-#define GCC_NSS_PPE_RESET_ADDR 0x01868014
-#define GCC_NSS_PPE_RESET_VAL 0xf0000
static int
qca_hppe_hw_init(ssdk_init_cfg *cfg, a_uint32_t dev_id)
{
a_uint32_t val;
- void __iomem *ppe_gcc_base;
/* reset ppe */
- ppe_gcc_base = ioremap_nocache(GCC_NSS_PPE_RESET_ADDR, 0x100);
- if (!ppe_gcc_base) {
- SSDK_ERROR("can't get gcc ppe reset address!\n");
- return -1;
- }
- writel(GCC_NSS_PPE_RESET_VAL, ppe_gcc_base);
- msleep(100);
- writel(0, ppe_gcc_base);
- msleep(100);
- iounmap(ppe_gcc_base);
- SSDK_INFO("ppe reset successfully!\n");
+ ssdk_ppe_reset_init();
qca_switch_init(dev_id);