commit ac452fddc656fee00b521c62d7a5092384534299
author zhongjia <zhongjia@codeaurora.org> Mon Dec 03 14:26:44 2018 +0800
committer zhongjia <zhongjia@codeaurora.org> Wed Dec 12 18:44:46 2018 +0800
tree 993d29951528db1f240ca326dcfe8c94eb10ad4a
parent d84da8955bc4eecbb164bdd729b7862a89523bcb

[qca-ssdk]:[ReducedProfile]: cut out the code of UNIPHY in hsl layer.

Change-Id: I3775e7ab4727ada3ba1ba72792c03b7164cb06cc
Signed-off-by: zhongjia <zhongjia@codeaurora.org>

src/hsl/hppe/hppe_uniphy.c

diff --git a/src/hsl/hppe/hppe_uniphy.c b/src/hsl/hppe/hppe_uniphy.c
index 2b6fbdf..6192041 100755
--- a/src/hsl/hppe/hppe_uniphy.c
+++ b/src/hsl/hppe/hppe_uniphy.c
@@ -37,7 +37,7 @@
 				index * UNIPHY_OFFSET_CALIB_4_INC,
 				&value->val);
 }
-
+#ifndef IN_UNIPHY_MINI
 sw_error_t
 hppe_uniphy_offset_calib_4_set(
 		a_uint32_t dev_id,
@@ -50,7 +50,7 @@
 				index * UNIPHY_OFFSET_CALIB_4_INC,
 				value->val);
 }
-
+#endif
 sw_error_t
 hppe_uniphy_mode_ctrl_get(
 		a_uint32_t dev_id,
@@ -260,7 +260,7 @@
 				index * SR_XS_PCS_KR_STS1_INC,
 				&value->val);
 }
-
+#ifndef IN_UNIPHY_MINI
 sw_error_t
 hppe_sr_xs_pcs_kr_sts1_set(
 		a_uint32_t dev_id,
@@ -273,7 +273,7 @@
 				index * SR_XS_PCS_KR_STS1_INC,
 				value->val);
 }
-
+#endif
 sw_error_t
 hppe_vr_xs_pcs_dig_ctrl1_get(
 		a_uint32_t dev_id,
@@ -399,7 +399,7 @@
 	*value = reg_val.bf.mmd1_reg_cal_rep_time;
 	return ret;
 }
-
+#ifndef IN_UNIPHY_MINI
 sw_error_t
 hppe_uniphy_offset_calib_4_mmd1_reg_cal_rep_time_set(
 		a_uint32_t dev_id,
@@ -6056,5 +6056,5 @@
 	ret = hppe_pll_control_vco_related_selection_2_set(dev_id, index, &reg_val);
 	return ret;
 }
-
+#endif