diff --git a/include/init/ssdk_init.h b/include/init/ssdk_init.h
index ed04c0e..5198685 100755
--- a/include/init/ssdk_init.h
+++ b/include/init/ssdk_init.h
@@ -383,6 +383,9 @@
 qca_hppe_gcc_uniphy_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
 			a_uint8_t * reg_data, a_uint32_t len);
 
+void
+qca_hppe_gcc_mac_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable);
+
 #ifdef __cplusplus
 }
 #endif                          /* __cplusplus */
diff --git a/src/adpt/hppe/adpt_hppe_portctrl.c b/src/adpt/hppe/adpt_hppe_portctrl.c
index 1c9d359..df97926 100755
--- a/src/adpt/hppe/adpt_hppe_portctrl.c
+++ b/src/adpt/hppe/adpt_hppe_portctrl.c
@@ -3099,6 +3099,15 @@
 	return;
 }
 
+void
+adpt_hppe_gcc_mac_clock_status_set(a_uint32_t dev_id, a_uint32_t port_id,
+				a_bool_t enable)
+{
+
+	qca_hppe_gcc_mac_port_clock_set(dev_id, port_id, enable);
+
+	return;
+}
 a_bool_t
 adpt_hppe_port_phy_status_change(struct qca_phy_priv *priv, a_uint32_t port_id,
 				struct port_phy_status phy_status)
@@ -3152,6 +3161,7 @@
 			if (status == A_TRUE)
 			{
 				adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id, port_id, A_FALSE);
+				adpt_hppe_gcc_mac_clock_status_set(priv->device_id, port_id, A_FALSE);
 				if ((a_uint32_t)phy_status.speed != priv->port_old_speed[port_id - 1])
 				{
 					/* configure gcc speed clock according to port current speed */
@@ -3180,6 +3190,7 @@
 					adpt_hppe_port_txfc_status_set(priv->device_id, port_id, (a_bool_t)phy_status.rx_flowctrl);
 					priv->port_old_rx_flowctrl[port_id - 1] = phy_status.rx_flowctrl;
 				}
+				adpt_hppe_gcc_mac_clock_status_set(priv->device_id, port_id, A_TRUE);
 				adpt_hppe_gcc_uniphy_clock_status_set(priv->device_id, port_id, A_TRUE);
 				adpt_hppe_uniphy_port_adapter_reset(priv->device_id, port_id);
 			}
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index a45bd60..c2d9657 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -132,6 +132,7 @@
 void __iomem *gcc_uniphy_base = NULL;
 void __iomem *gcc_hppe_clock_config1_base = NULL;
 void __iomem *gcc_hppe_clock_config2_base = NULL;
+void __iomem *gcc_hppe_clock_config3_base = NULL;
 
 a_uint32_t ssdk_dt_global_get_mac_mode(a_uint32_t index)
 {
@@ -3525,6 +3526,13 @@
 	}
 	printk("Get gcc hppe colck config2 address successfully!\n");
 
+	gcc_hppe_clock_config3_base = ioremap_nocache(0x01868240, 0x2c);
+	if (!gcc_hppe_clock_config3_base) {
+		printk("can't get gcc hppe colck config3 address!\n");
+		return -1;
+	}
+	printk("Get gcc hppe colck config3 address successfully!\n");
+
 	return 0;
 }
 
@@ -3593,6 +3601,38 @@
 
 	return 0;
 }
+uint32_t
+qca_hppe_gcc_mac_clock_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr,
+				a_uint8_t * reg_data, a_uint32_t len)
+{
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if ((reg_addr%4)!= 0)
+	return SW_BAD_PARAM;
+
+	writel(reg_data, gcc_hppe_clock_config3_base + reg_addr);
+
+	return 0;
+}
+
+uint32_t
+qca_hppe_gcc_mac_clock_reg_read(a_uint32_t dev_id, a_uint32_t reg_addr,
+				a_uint8_t * reg_data, a_uint32_t len)
+{
+	uint32_t reg_val = 0;
+
+	if (len != sizeof (a_uint32_t))
+        return SW_BAD_LEN;
+
+	if ((reg_addr%4)!= 0)
+	return SW_BAD_PARAM;
+
+	reg_val = readl(gcc_hppe_clock_config3_base + reg_addr);
+	aos_mem_copy(reg_data, &reg_val, sizeof (a_uint32_t));
+
+	return 0;
+}
 
 uint32_t
 qca_hppe_gcc_uniphy_reg_write(a_uint32_t dev_id, a_uint32_t reg_addr, a_uint8_t * reg_data, a_uint32_t len)
@@ -3644,6 +3684,27 @@
 	}
 
 }
+
+void
+qca_hppe_gcc_mac_port_clock_set(a_uint32_t dev_id, a_uint32_t port_id, a_bool_t enable)
+{
+	a_uint32_t i, reg_value;
+
+	for (i = 0; i < 2; i++)
+	{
+		reg_value = 0;
+		qca_hppe_gcc_mac_clock_reg_read(dev_id, ((i * 4) + 0x8 * (port_id - 1)),
+				(a_uint8_t *)&reg_value, 4);
+		if (enable == A_TRUE)
+			reg_value |= 0x1;
+		else
+			reg_value &= ~0x1;
+		qca_hppe_gcc_mac_clock_reg_write(dev_id, ((i * 4)+ 0x8 * (port_id - 1)),
+				(a_uint8_t *)&reg_value, 4);
+	}
+
+}
+
 static sw_error_t
 qca_hppe_port_mux_set(fal_port_t port_id, a_uint32_t mode1, a_uint32_t mode2)
 {