Merge "[qca-ssdk]: new TDM configuration for CPPE"
diff --git a/include/adpt/adpt.h b/include/adpt/adpt.h
index 3f3a9db..b41342e 100755
--- a/include/adpt/adpt.h
+++ b/include/adpt/adpt.h
@@ -978,7 +978,11 @@
typedef sw_error_t (*adpt_ptp_interrupt_get_func)(a_uint32_t dev_id,
a_uint32_t port_id, fal_ptp_interrupt_t *interrupt);
-
+typedef struct
+{
+ ssdk_chip_type chip_type;
+ a_uint32_t chip_revision;
+}adpt_chip_ver_t;
typedef struct
{
a_uint32_t adpt_fdb_func_bitmap[2];
diff --git a/include/adpt/hppe/adpt_hppe.h b/include/adpt/hppe/adpt_hppe.h
index 5ca914f..743e7ed 100755
--- a/include/adpt/hppe/adpt_hppe.h
+++ b/include/adpt/hppe/adpt_hppe.h
@@ -95,6 +95,11 @@
void adpt_hppe_ptp_func_bitmap_init(a_uint32_t dev_id);
sw_error_t adpt_hppe_ptp_init(a_uint32_t dev_id);
+#define HPPE_REVISION 0x0
+#define CPPE_REVISION 0x1
+#define UNKNOWN_REVISION 0xff
+a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/include/init/ssdk_init.h b/include/init/ssdk_init.h
index c1ec197..ea0f542 100755
--- a/include/init/ssdk_init.h
+++ b/include/init/ssdk_init.h
@@ -210,6 +210,7 @@
hsl_reg_func reg_func;
ssdk_chip_type chip_type;
+ a_uint32_t chip_revision;
/* os specific parameter */
/* when uk_if based on netlink, it's netlink protocol type*/
diff --git a/src/adpt/adpt.c b/src/adpt/adpt.c
index e078604..411ef2f 100755
--- a/src/adpt/adpt.c
+++ b/src/adpt/adpt.c
@@ -19,7 +19,8 @@
#endif
adpt_api_t *g_adpt_api[SW_MAX_NR_DEV] = {NULL};
-ssdk_chip_type g_chip_type = 0;
+
+adpt_chip_ver_t g_chip_ver[SW_MAX_NR_DEV] = {0};
adpt_api_t *adpt_api_ptr_get(a_uint32_t dev_id)
{
@@ -30,6 +31,11 @@
}
#if defined(HPPE)
+a_uint32_t adpt_hppe_chip_revision_get(a_uint32_t dev_id)
+{
+ return g_chip_ver[dev_id].chip_revision;
+}
+
static sw_error_t adpt_hppe_module_func_register(a_uint32_t dev_id, a_uint32_t module)
{
sw_error_t rv= SW_OK;
@@ -178,7 +184,7 @@
}
- switch (g_chip_type)
+ switch (g_chip_ver[dev_id].chip_type)
{
#if defined(HPPE)
case CHIP_HPPE:
@@ -259,8 +265,6 @@
{
sw_error_t rv= SW_OK;
- g_chip_type = cfg->chip_type;
-
switch (cfg->chip_type)
{
#if defined(HPPE)
@@ -272,6 +276,8 @@
return SW_FAIL;
}
+ g_chip_ver[dev_id].chip_type = cfg->chip_type;
+ g_chip_ver[dev_id].chip_revision = cfg->chip_revision;
g_adpt_api[dev_id]->adpt_mirror_func_bitmap = 0xffffffff;
rv = adpt_hppe_module_func_register(dev_id, FAL_MODULE_MIRROR);
SW_RTN_ON_ERROR(rv);
diff --git a/src/init/ssdk_hppe.c b/src/init/ssdk_hppe.c
index f4d7275..773a7a5 100755
--- a/src/init/ssdk_hppe.c
+++ b/src/init/ssdk_hppe.c
@@ -85,14 +85,21 @@
{
a_uint32_t i = 0;
a_uint32_t val, addr = 0x4000;
+ a_uint32_t port_max = SSDK_PHYSICAL_PORT7;
+ a_uint32_t xgmac_max = 2;
- for(i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT7; i++) {
+ if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ port_max = SSDK_PHYSICAL_PORT6;
+ xgmac_max = 1;
+ }
+
+ for(i = SSDK_PHYSICAL_PORT1; i < port_max; i++) {
fal_port_rxfc_status_set(dev_id, i, A_TRUE);
fal_port_txfc_status_set(dev_id, i, A_TRUE);
fal_port_txmac_status_set (dev_id, i, A_TRUE);
fal_port_rxmac_status_set (dev_id, i, A_TRUE);
}
- for (i = 0; i < 2; i ++) {
+ for (i = 0; i < xgmac_max; i ++) {
val = 0x00000081;
qca_switch_reg_write(0, 0x00003008 + (addr * i), (a_uint8_t *)&val, 4);
}
@@ -105,11 +112,22 @@
qca_hppe_portctrl_hw_init(a_uint32_t dev_id)
{
a_uint32_t i = 0;
+ a_uint32_t port_max = SSDK_PHYSICAL_PORT7;
+ if(adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ SSDK_INFO("Cypress PPE port initializing\n");
+ port_max = SSDK_PHYSICAL_PORT6;
#ifndef HAWKEYE_CHIP
- qca_hppe_fpga_xgmac_gpio_enable(dev_id);
+ qca_cppe_fpga_xgmac_clock_enable(dev_id);
#endif
- for(i = SSDK_PHYSICAL_PORT1; i < SSDK_PHYSICAL_PORT7; i++) {
+ } else {
+ SSDK_INFO("Hawkeye PPE port initializing\n");
+ port_max = SSDK_PHYSICAL_PORT7;
+#ifndef HAWKEYE_CHIP
+ qca_hppe_fpga_xgmac_gpio_enable(dev_id);
+#endif
+ }
+ for(i = SSDK_PHYSICAL_PORT1; i < port_max; i++) {
qca_hppe_port_mac_type_set(dev_id, i, PORT_GMAC_TYPE);
fal_port_txmac_status_set (dev_id, i, A_FALSE);
fal_port_rxmac_status_set (dev_id, i, A_FALSE);
@@ -118,7 +136,7 @@
fal_port_max_frame_size_set(dev_id, i, SSDK_MAX_FRAME_SIZE);
}
- for(i = SSDK_PHYSICAL_PORT5; i < SSDK_PHYSICAL_PORT7; i++) {
+ for(i = SSDK_PHYSICAL_PORT5; i < port_max; i++) {
qca_hppe_port_mac_type_set(dev_id, i, PORT_XGMAC_TYPE);
fal_port_txmac_status_set (dev_id, i, A_FALSE);
fal_port_rxmac_status_set (dev_id, i, A_FALSE);
@@ -342,6 +360,59 @@
{0x50, 6, 0},
};
+fal_port_scheduler_cfg_t cppe_port_scheduler0_tbl[] = {
+ {0xb7, 0, 6},
+ {0xbe, 3, 0},
+ {0xde, 6, 5},
+ {0xdd, 0, 1},
+ {0xbd, 5, 6},
+ {0xbe, 1, 0},
+ {0xee, 6, 4},
+ {0xcf, 0, 5},
+ {0x9f, 4, 6},
+ {0xbe, 5, 0},
+ {0x7e, 6, 7},
+ {0x5f, 0, 5},
+ {0x9f, 7, 6},
+ {0xbe, 5, 0},
+ {0xfa, 6, 2},
+ {0xbb, 0, 6},
+ {0x9f, 2, 5},
+ {0xcf, 6, 4},
+ {0xee, 5, 0},
+ {0xbe, 4, 6},
+ {0x3f, 0, 7},
+ {0x5f, 6, 5},
+ {0xde, 7, 0},
+ {0xbe, 5, 6},
+ {0xb7, 0, 3},
+ {0xe7, 6, 4},
+ {0xee, 3, 0},
+ {0xbe, 4, 6},
+ {0x9f, 0, 5},
+ {0xdd, 6, 1},
+ {0xfc, 5, 0},
+ {0xbe, 1, 6},
+ {0x9f, 0, 5},
+ {0x5f, 6, 7},
+ {0x7e, 5, 0},
+ {0xbe, 7, 6},
+ {0xaf, 0, 4},
+ {0xcf, 6, 5},
+ {0x9f, 4, 6},
+ {0xbe, 5, 0},
+ {0xfa, 6, 2},
+ {0xdb, 0, 5},
+ {0x9f, 2, 6},
+ {0xbe, 5, 0},
+ {0x7e, 6, 7},
+ {0x6f, 0, 4},
+ {0xaf, 7, 6},
+ {0x9f, 4, 5},
+ {0xde, 6, 0},
+ {0xf6, 5, 3},
+};
+
fal_port_tdm_tick_cfg_t port_tdm0_tbl[] = {
{1, FAL_PORT_TDB_DIR_INGRESS, 0},
{1, FAL_PORT_TDB_DIR_EGRESS, 5},
@@ -441,6 +512,105 @@
{1, FAL_PORT_TDB_DIR_EGRESS, 6},
};
+fal_port_tdm_tick_cfg_t cppe_port_tdm0_tbl[] = {
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 1},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 2},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 3},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 1},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 2},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 3},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 0},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 4},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 5},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 6},
+ {1, FAL_PORT_TDB_DIR_INGRESS, 7},
+ {1, FAL_PORT_TDB_DIR_EGRESS, 7},
+};
+
static sw_error_t
qca_hppe_tdm_hw_init(a_uint32_t dev_id)
{
@@ -460,8 +630,15 @@
bm_tick_mode = ssdk_bm_tick_mode_get(dev_id);
if (tm_tick_mode == 0) {
- num = sizeof(port_scheduler0_tbl) / sizeof(fal_port_scheduler_cfg_t);
- scheduler_cfg = port_scheduler0_tbl;
+ if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ num = sizeof(cppe_port_scheduler0_tbl) /
+ sizeof(fal_port_scheduler_cfg_t);
+ scheduler_cfg = cppe_port_scheduler0_tbl;
+ } else {
+ num = sizeof(port_scheduler0_tbl) /
+ sizeof(fal_port_scheduler_cfg_t);
+ scheduler_cfg = port_scheduler0_tbl;
+ }
} else if (tm_tick_mode == 1) {
num = sizeof(port_scheduler1_tbl) / sizeof(fal_port_scheduler_cfg_t);
scheduler_cfg = port_scheduler1_tbl;
@@ -478,8 +655,15 @@
SW_RTN_ON_NULL(p_api->adpt_port_tdm_ctrl_set);
if (bm_tick_mode == 0) {
- num = sizeof(port_tdm0_tbl) / sizeof(fal_port_tdm_tick_cfg_t);
- bm_cfg = port_tdm0_tbl;
+ if (adpt_hppe_chip_revision_get(dev_id) == CPPE_REVISION) {
+ num = sizeof(cppe_port_tdm0_tbl) /
+ sizeof(fal_port_tdm_tick_cfg_t);
+ bm_cfg = cppe_port_tdm0_tbl;
+ } else {
+ num = sizeof(port_tdm0_tbl) /
+ sizeof(fal_port_tdm_tick_cfg_t);
+ bm_cfg = port_tdm0_tbl;
+ }
} else {
return SW_BAD_VALUE;
}
diff --git a/src/init/ssdk_init.c b/src/init/ssdk_init.c
index ac53910..a91da2b 100755
--- a/src/init/ssdk_init.c
+++ b/src/init/ssdk_init.c
@@ -2503,6 +2503,7 @@
{
int rv = SW_OK;
a_uint8_t chip_ver = 0;
+ a_uint8_t chip_revision = 0;
/*qca808x_end*/
hsl_reg_mode reg_mode;
@@ -2515,6 +2516,7 @@
a_uint32_t reg_val = 0;
qca_switch_reg_read(dev_id,0,(a_uint8_t *)®_val, 4);
chip_ver = (reg_val&0xff00)>>8;
+ chip_revision = reg_val&0xff;
}
/*qca808x_start*/
if(chip_ver == QCA_VER_AR8227)
@@ -2525,8 +2527,15 @@
cfg->chip_type = CHIP_ISIS;
else if(chip_ver == QCA_VER_DESS)
cfg->chip_type = CHIP_DESS;
- else if(chip_ver == QCA_VER_HPPE)
+ else if(chip_ver == QCA_VER_HPPE) {
cfg->chip_type = CHIP_HPPE;
+ #ifdef HAWKEYE_CHIP
+ cfg->chip_revision = chip_revision;
+ #else
+ cfg->chip_revision = 1;/*cypress for debug*/
+ #endif
+
+ }
else {
/* try single phy without switch connected */
rv = chip_is_scomphy(dev_id, cfg);