commit 1cf9a165fc80b2f8109f85d5bd121e0c7c397e58
author Damjan Marion <damarion@cisco.com> Wed May 23 20:21:51 2018 +0200
committer Damjan Marion <dmarion.lists@gmail.com> Fri May 25 11:44:43 2018 +0000
tree 207e20914dc9edab3f2f225377e2c1af9d476190
parent d57f63698f99fad0288ac040d83b3ecd380d4bfd

Vectorized bihash_{48,40,24,16}_8 key compare

bihash_48_8 case:
Scalar code: 6 clocks
SSE4.2 code: 3 clocks
AVX2 code: 2.27 clocks
AVX512 code: 1.5 clocks

Change-Id: I40700175835a1e7321276e47eadbf9771d3c5a68
Signed-off-by: Damjan Marion <damarion@cisco.com>

src/vppinfra/bihash_48_8.h

diff --git a/src/vppinfra/bihash_48_8.h b/src/vppinfra/bihash_48_8.h
index 107bcac..760ec0a 100644
--- a/src/vppinfra/bihash_48_8.h
+++ b/src/vppinfra/bihash_48_8.h
@@ -69,10 +69,26 @@
 }
 
 static inline int
-clib_bihash_key_compare_48_8 (const u64 * a, const u64 * b)
+clib_bihash_key_compare_48_8 (u64 * a, u64 * b)
 {
+#if defined (CLIB_HAVE_VEC512)
+  u64x8 v = u64x8_load_unaligned (a) ^ u64x8_load_unaligned (b);
+  return (u64x8_is_zero_mask (v) & 0x3f) == 0;
+#elif defined (CLIB_HAVE_VEC256)
+  u64x4 v;
+  v = u64x4_load_unaligned (a) ^ u64x4_load_unaligned (b);
+  v |= u64x4_load_unaligned (a + 2) ^ u64x4_load_unaligned (b + 2);
+  return u64x4_is_all_zero (v);
+#elif defined(CLIB_HAVE_VEC128) && defined(CLIB_HAVE_VEC128_UNALIGNED_LOAD_STORE)
+  u64x2 v;
+  v = u64x2_load_unaligned (a) ^ u64x2_load_unaligned (b);
+  v |= u64x2_load_unaligned (a + 2) ^ u64x2_load_unaligned (b + 2);
+  v |= u64x2_load_unaligned (a + 4) ^ u64x2_load_unaligned (b + 4);
+  return u64x2_is_all_zero (v);
+#else
   return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2]) | (a[3] ^ b[3])
 	  | (a[4] ^ b[4]) | (a[5] ^ b[5])) == 0;
+#endif
 }
 
 #undef __included_bihash_template_h__