commit 290526e3c72888ac05928ed0a6dddee02f7df650
author Junfeng Wang <Drenfong.Wang@intel.com> Tue Mar 09 16:44:57 2021 +0800
committer John Lo <lojultra2020@outlook.com> Fri Mar 19 21:34:16 2021 +0000
tree 5117191488c7107d6404abaaca97d76022e7e759
parent 162b70d50aaf5daa744417818c01cae573580f6f

vxlan: add tunnel cache to graph node

Type: improvement

Signed-off-by: Drenfong Wong <drenfong.wang@intel.com>
Change-Id: Ia81aaa86fe071cbbed028cc85c5f3fa0f1940a0f

src/vnet/vxlan/decap.c

diff --git a/src/vnet/vxlan/decap.c b/src/vnet/vxlan/decap.c
index 4678aa3..2ba24d8 100644
--- a/src/vnet/vxlan/decap.c
+++ b/src/vnet/vxlan/decap.c
@@ -469,11 +469,6 @@
   last_tunnel_cache4 last4;
   last_tunnel_cache6 last6;
 
-#ifdef CLIB_HAVE_VEC512
-  vtep4_cache_t vtep4_u512;
-  clib_memset (&vtep4_u512, 0, sizeof (vtep4_u512));
-#endif
-
   from = vlib_frame_vector_args (frame);
   n_left_from = frame->n_vectors;
   next_index = node->cached_next_index;
@@ -584,8 +579,8 @@
 	  if (is_ip4)
 	    {
 #ifdef CLIB_HAVE_VEC512
-	      if (!vtep4_check_vector
-		  (&vxm->vtep_table, b0, ip40, &last_vtep4, &vtep4_u512))
+	      if (!vtep4_check_vector (&vxm->vtep_table, b0, ip40, &last_vtep4,
+				       &vxm->vtep4_u512))
 #else
 	      if (!vtep4_check (&vxm->vtep_table, b0, ip40, &last_vtep4))
 #endif
@@ -672,8 +667,8 @@
 	  if (is_ip4)
 	    {
 #ifdef CLIB_HAVE_VEC512
-	      if (!vtep4_check_vector
-		  (&vxm->vtep_table, b1, ip41, &last_vtep4, &vtep4_u512))
+	      if (!vtep4_check_vector (&vxm->vtep_table, b1, ip41, &last_vtep4,
+				       &vxm->vtep4_u512))
 #else
 	      if (!vtep4_check (&vxm->vtep_table, b1, ip41, &last_vtep4))
 #endif
@@ -799,8 +794,8 @@
 	  if (is_ip4)
 	    {
 #ifdef CLIB_HAVE_VEC512
-	      if (!vtep4_check_vector
-		  (&vxm->vtep_table, b0, ip40, &last_vtep4, &vtep4_u512))
+	      if (!vtep4_check_vector (&vxm->vtep_table, b0, ip40, &last_vtep4,
+				       &vxm->vtep4_u512))
 #else
 	      if (!vtep4_check (&vxm->vtep_table, b0, ip40, &last_vtep4))
 #endif