commit 33af8c1ed89f15cf0601ee891e9603bef16f2c93
author Lijian.Zhang <Lijian.Zhang@arm.com> Mon Sep 16 16:22:36 2019 +0800
committer Neale Ranns <nranns@cisco.com> Wed Sep 25 08:59:07 2019 +0000
tree dfa3d9fe944cc1b12a5b4357067ed99e639a80d4
parent 896c896a3c4ed563a270281ff8b50fd253f4833f

fib: fix some typos in fib/mtrie

Type: fix

Change-Id: I1af0e4a9bc23a3b6b6d3a74df093801ab6cae1f8
Signed-off-by: Lijian Zhang <Lijian.Zhang@arm.com>

src/vnet/dpo/load_balance.h

diff --git a/src/vnet/dpo/load_balance.h b/src/vnet/dpo/load_balance.h
index a204b7f..5428e20 100644
--- a/src/vnet/dpo/load_balance.h
+++ b/src/vnet/dpo/load_balance.h
@@ -175,7 +175,7 @@
 } load_balance_t;
 
 STATIC_ASSERT(sizeof(load_balance_t) <= CLIB_CACHE_LINE_BYTES,
-	      "A load_balance object size exceeds one cachline");
+	      "A load_balance object size exceeds one cacheline");
 
 /**
  * Flags controlling load-balance formatting/display