Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064)
Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto"
AKA 32, 64, or 128 bytes, or use the inferred value from the build host.
produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h
Kernels which implement the following pseudo-file (aka x86_64) are
easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
Otherwise, extract the cpuid from /proc/cpuinfo and map it to the
cache line size.
Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74
Signed-off-by: Dave Barach <dave@barachs.net>
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
diff --git a/dpdk/Makefile b/dpdk/Makefile
index 331e1c3..7b70346 100644
--- a/dpdk/Makefile
+++ b/dpdk/Makefile
@@ -124,6 +124,7 @@
$(CPU_PART_CAVIUM_THUNDERX_81XX) $(CPU_PART_CAVIUM_THUNDERX_83XX)))
DPDK_TARGET = arm64-thunderx-linuxapp-$(DPDK_CC)
DPDK_MACHINE = thunderx
+DPDK_CACHE_LINE_SIZE := 128
else
$(warning Unknown Cavium CPU)
endif