Configure or deduce CLIB_LOG2_CACHE_LINE_BYTES (VPP-1064)
Added configure argument "--with-log2-cache-line-bytes=5|6|7|auto"
AKA 32, 64, or 128 bytes, or use the inferred value from the build host.
produces build-xxx/vpp/vppinfra/config.h, which .../src/vppinfra/cache.h
Kernels which implement the following pseudo-file (aka x86_64) are
easy: /sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size
Otherwise, extract the cpuid from /proc/cpuinfo and map it to the
cache line size.
Change-Id: I7ff861e042faf82c3901fa1db98864fbdea95b74
Signed-off-by: Dave Barach <dave@barachs.net>
Signed-off-by: Nitin Saxena <nitin.saxena@cavium.com>
diff --git a/src/vppinfra/cache.h b/src/vppinfra/cache.h
index e5c678e..ac08355 100644
--- a/src/vppinfra/cache.h
+++ b/src/vppinfra/cache.h
@@ -41,10 +41,13 @@
#include <vppinfra/error_bootstrap.h>
/*
- * Allow CFLAGS to override the arch-specific cache line size
+ * Allow CFLAGS to override the configured / deduced cache line size
*/
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
+/* defines CLIB_LOG2_CACHE_LINE_BYTES */
+#include <vppinfra/config.h>
+
/* Default cache line size of 64 bytes. */
#ifndef CLIB_LOG2_CACHE_LINE_BYTES
#define CLIB_LOG2_CACHE_LINE_BYTES 6