commit 70b1cbdf2bd7687f840a59475ca769c9bab907c9
author Tianyu Li <tianyu.li@arm.com> Wed Jun 23 07:35:03 2021 +0000
committer Damjan Marion <dmarion@me.com> Fri Jul 02 14:28:24 2021 +0000
tree 911e87072e23cb58243293f126281b8613a50896
parent ecadf6a5395968092e093f7fa1d40a17762ebac1

vlib: fix buffer pool alignment size

Alignment size should be CLIB_CACHE_LINE_BYTES(64)
instead of CLIB_LOG2_CACHE_LINE_BYTES(6)

Type: fix

Signed-off-by: Tianyu Li <tianyu.li@arm.com>
Change-Id: If2d5ae324093be64454377866297f5e76ccddc93

src/vlib/buffer.c

diff --git a/src/vlib/buffer.c b/src/vlib/buffer.c
index ae88b4e..adaafa3 100644
--- a/src/vlib/buffer.c
+++ b/src/vlib/buffer.c
@@ -509,7 +509,7 @@
   if (vec_len (bm->buffer_pools) >= 255)
     return ~0;
 
-  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_LOG2_CACHE_LINE_BYTES);
+  vec_add2_aligned (bm->buffer_pools, bp, 1, CLIB_CACHE_LINE_BYTES);
 
   if (bm->buffer_mem_size == 0)
     {