crypto-native: 256-bit AES CBC support
Used on intel client CPUs which suppport VAES instruction set without
AVX512
Type: improvement
Change-Id: I5f816a1ea9f89a8d298d2c0f38d8d7c06f414ba0
Signed-off-by: Damjan Marion <damarion@cisco.com>
diff --git a/src/vppinfra/vector_avx2.h b/src/vppinfra/vector_avx2.h
index f5c09a5..80c2e39 100644
--- a/src/vppinfra/vector_avx2.h
+++ b/src/vppinfra/vector_avx2.h
@@ -213,6 +213,16 @@
return v4[0];
}
+static_always_inline u8x32
+u8x32_xor3 (u8x32 a, u8x32 b, u8x32 c)
+{
+#if __AVX512F__
+ return (u8x32) _mm256_ternarylogic_epi32 ((__m256i) a, (__m256i) b,
+ (__m256i) c, 0x96);
+#endif
+ return a ^ b ^ c;
+}
+
static_always_inline u16x16
u16x16_mask_last (u16x16 v, u8 n_last)
{
@@ -391,6 +401,12 @@
a[3] = u64x4_permute_lanes (r[1], r[3], 0x31);
}
+static_always_inline u8x32
+u8x32_splat_u8x16 (u8x16 a)
+{
+ return (u8x32) _mm256_broadcastsi128_si256 ((__m128i) a);
+}
+
#endif /* included_vector_avx2_h */
/*