Improve L2FIB PDR/NDR performance (VPP-963)
1. Limit MAC entry update per l2-learn call to reduce update burst
when wall clock advance to the the next minute so all MAC time
stamps are behind current time needing update.
2. Optimize l2-learn node fast path code sequence.
3. Invalidate cache_key when update MAC entry.
4. Change L2 learn hit counter to L2 learn hit-update counter.
5. Increase L2FIB table memory size to 512MB to fit 4M entries
6. Set MAC learn limit at 4M entries
Change-Id: I3075ee8fb59645a56850126bac2e3e6d341cef4d
Signed-off-by: John Lo <loj@cisco.com>
diff --git a/src/vnet/l2/l2_fib.h b/src/vnet/l2/l2_fib.h
index 49a8b5b..7cc2dc5 100644
--- a/src/vnet/l2/l2_fib.h
+++ b/src/vnet/l2/l2_fib.h
@@ -25,7 +25,7 @@
* The size of the hash table
*/
#define L2FIB_NUM_BUCKETS (64 * 1024)
-#define L2FIB_MEMORY_SIZE (256<<20)
+#define L2FIB_MEMORY_SIZE (512<<20)
/* Ager scan interval is 1 minute for aging */
#define L2FIB_AGE_SCAN_INTERVAL (60.0)