Update to odulow per maintenance bronze
Hardening of FAPI TM, FHI Lib upgrade
Integration with oduhigh
Details in release notes
Test Performed: Unit Tests using testmac and with odulow
Issue-Id: ODULOW-10
Change-Id: I965f44a90bf7275c8ae9f41cf62074226850ef71
Signed-off-by: Luis Farias <luis.farias@intel.com>
diff --git a/docs/Architecture-Overview_fh.rst b/docs/Architecture-Overview_fh.rst
index 1a8bb45..3538e69 100644
--- a/docs/Architecture-Overview_fh.rst
+++ b/docs/Architecture-Overview_fh.rst
@@ -31,8 +31,7 @@
------------
The front haul interface, according to the ORAN Fronthaul specification,
-performs communication between O-RAN |br|
-Distributed Unit (O-DU) and O-RAN
+performs communication between O-RAN Distributed Unit (O-DU) and O-RAN
Radio Unit (O-RU) and consists of multiple HW and SW components.
The logical representation of HW and SW components is shown in Figure 1.
@@ -49,41 +48,39 @@
From the hardware perspective, two networking ports are used to
communicate to the Front Haul and Back (Mid) Haul network as well as to
receive PTP synchronization. The system timer is used to provide a
-“sense” of time to the gNB |br|
-application.
+“sense” of time to the gNB application.
From the software perspective, the following components are used:
-- Linux PTP provides synchronization of system timer to GPS time:
+* Linux PTP provides synchronization of system timer to GPS time:
-- Ptp4l is used to synchronize oscillator on Network Interface
- Controller (NIC) to PTP GM.
+ - Ptp4l is used to synchronize oscillator on Network Interface
+ Controller (NIC) to PTP GM.
-- Phc2sys is used to synchronize system timer to oscillator on NIC.
+ - Phc2sys is used to synchronize system timer to oscillator on NIC.
-- DPDK to provide the interface to the Ethernet port.
+* DPDK to provide the interface to the Ethernet port.
-- xRAN library is built on top of DPDK to perform U-plane and C-plane
+* xRAN library is built on top of DPDK to perform U-plane and C-plane
functionality according to the ORAN Fronthaul specification.
-- 5GNR reference PHY uses the xRAN library to access interface to O-RU.
+* 5GNR reference PHY uses the xRAN library to access interface to O-RU.
The interface between the library and PHY is defined to communicate
TTI event, symbol time, C-plane information as well as IQ sample
data.
-- 5G NR PHY communicates with the L2 application using the set of
+* 5G NR PHY communicates with the L2 application using the set of
MAC/PHY APIs and the shared memory interface defined as WLS.
-- L2, in turn, can use Back (Mid) Haul networking port to connect to
+* L2, in turn, can use Back (Mid) Haul networking port to connect to
the CU unit in the context of 3GPP specification.
In this document, we focus on the details of the design and
implementation of the xRAN library with respect to providing Front Haul
-functionality for both mmWave and Sub-6 scenarios
+functionality for both mmWave and Sub-6 scenarios.
The xRAN M-plane is not implemented and is outside of the scope of this
-description. Configuration files are used to |br|
-specify selected M-plane
+description. Configuration files are used to specify selected M-plane
level parameters.
ORAN FH Threads
@@ -92,9 +89,9 @@
ORAN FH Thread Performs:
- Symbol base “time event” to the rest of the system based on System
- Clock synchronized to GPS time via PTP
+ Clock synchronized to GPS time via PTP.
-- Baseline polling mode driver performing TX and RX of Ethernet packets
+- Baseline polling mode driver performing TX and RX of Ethernet packets.
- Most of the packet processing such as Transport header, Application
header, Data section header and interactions with the rest of the PHY
@@ -108,16 +105,14 @@
Communication between L1 and xRAN layer is performed using a set of
callback functions where L1 assigned callback and xRAN layer executes
those functions at a particular event or time moment. Detailed
-information on callback function |br|
-options and setting as well as design,
+information on callback function options and setting as well as design,
can be found in the sections below.
Sample Application Thread Model
-------------------------------
Configuration of a sample application for both O-DU and O-RU follows the
-model of 5G NR l1app application in the |br|
-section of xRAN only. No BBU or
+model of 5G NR l1app application in the section of xRAN only. No BBU or
FEC related threads are needed as minimal xRAN functionality is used
only.
@@ -137,8 +132,7 @@
----------------
Figure 1 corresponds to the O-RU part of the xRAN split. Implementation
-of the RU side of the xRAN protocol is not |br|
-covered in this document.
+of the RU side of the xRAN protocol is not covered in this document.
.. image:: images/eNB-gNB-Architecture-with-O-DU-and-RU.jpg
:width: 600
@@ -222,8 +216,7 @@
|br|
Information on specific features of C-Plane and U-plane provided in
-Section 6.0. Configuration of S-plane used on test |br|
-setup for simulation
+Section 6.0. Configuration of S-plane used on test setup for simulation
is provided in Appendix Appendix 2.
Data flow separation is based on VLAN (applicable when layer 2 or layer
@@ -253,25 +246,20 @@
-------------------------------------------
The ORAN Fronthaul specification defines the latency model of the front
-haul interface and interaction between O-DU and 0-RU. This
+haul interface and interaction between O-DU and O-RU. This
implementation of the xRAN library supports only the category with fixed
timing advance and Defined Transport method. It determines O-DU transmit
-and receive windows based on pre-defined transport network |br|
-characteristics, and the delay characteristics of the RUs within the
+and receive windows based on pre-defined transport network characteristics, and the delay characteristics of the RUs within the
timing domain.
Table 4 below provides default values used for the implementation of
O-DU – O-RU simulation with mmWave scenario. Table 5 and Table 6 below
provide default values used for the implementation of O-DU – O-RU
-simulation with |br|
-numerology 0 and numerology 1 for Sub6 scenarios.
+simulation with numerology 0 and numerology 1 for Sub6 scenarios.
Configuration can be adjusted via configuration files for sample |br|
application and reference PHY. However, simulation of the different
-range of the settings was not performed, and |bR|
-additional implementation changes might be required as well as testing with actual O-RU. |br|
-The
-parameters for the front haul network are out of scope as a direct
-connection between O-DU and 0-RU is used for simulation.
+range of the settings was not performed, and additional implementation changes might be required as well as testing with actual O-RU. The
+parameters for the front haul network are out of scope as a direct connection between O-DU and 0-RU is used for simulation.
|br|
|br|
@@ -387,8 +375,7 @@
synchronize local time to GPS time. Details of the configuration used
are provided in Appendix Appendix 2. Local time is used to get Top of
the Second (ToS) as a 1pps event for SW implementation. Timing event is
-obtained by performing polling of local time using |br|
-clock_gettime(CLOCK_REALTIME,..)
+obtained by performing polling of local time using clock_gettime(CLOCK_REALTIME,..)
All-time intervals are specified with respect to GPS time which
corresponds to OTA time.
diff --git a/docs/Assumptions_Dependencies.rst b/docs/Assumptions_Dependencies.rst
index 21a649a..29aae62 100644
--- a/docs/Assumptions_Dependencies.rst
+++ b/docs/Assumptions_Dependencies.rst
@@ -30,36 +30,33 @@
-----------
An L1 with a proprietary interface and a testmac supporting the FAPI interface are available through the Open Source Community(OSC) github in binary blob form and with the reference
-files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to |br|
-integrate with the O-DU
+files that support the tests required for the ORAN Bronze Release. The required header files that are needed to build the 5G FAPI TM and to run validation tests and to integrate with the O-DU
High to check network functionality are available from the same site.
-The L1 App and Testmac |br|
-repository is at https://github.com/intel/FlexRAN/
+The L1 App and Testmac repository is at https://github.com/intel/FlexRAN/
Requirements
------------
* Only Xeon® series Processor with Intel Architecture are supported and the platform should be |br|
- Intel® Xeon® SkyLake / CascadeLake platforms with at least 2.0 GHz core frequency
-* FPGA/ASIC card for FEC acceleration that's compliance with BBDev framework and interface if you need run high throughput case with HW FEC card assistant.
-* Bios setting steps and options might have difference, however at least you should have the same Bios setting as decribed in the README.me file available at https://github.com/intel/FlexRAN Bios settings section
-* Runing with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.
+ either Intel® Xeon® SkyLake or CascadeLake with at least 2.0 GHz core frequency.
+* FPGA/ASIC card for FEC acceleration that is compliant with the BBDev framework and interface. Only needed to run high throughput cases with the HW FEC card assistance.
+* Bios setting steps and options may have differences, however at least you should have the same Bios setting as decribed in the README.md file available at https://github.com/intel/FlexRAN Bios settings section.
+* Running with FH requires PTP for Linux\* version 2.0 (or later) to be installed to provide IEEE 1588 synchronization.
Dependencies
------------
-* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries)
+* Centos OS 7 (7.5+) (7.7 was used for the L1 and testmac binaries).
* RT Kernel kernel-rt-3.10.0-1062.12.1.rt56.1042
-* Data Plane Development Kit (DPDK v18.08) with corresponding DPDK patch according to O-RAN FH setup |br|
- configuation section.
+* Data Plane Development Kit (DPDK v19.11) with corresponding DPDK patch according to |br| O-RAN FH setup configuration section.
-* FEC SDK lib which was needed when you run FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules
+* FEC SDK lib which is needed when you run the FEC in SW mode, download through: https://software.intel.com/en-us/articles/flexran-lte-and-5g-nr-fec-software-development-kit-modules
-* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you could get is always latest ICC version, the verification for that version might not be performed yet, please feedback through O-DU Low WIKI page if you meet issue.
+* Intel® C++ Compiler v19.0.3 is used for test application and system integration. Free Intel® C++ Compiler can be gotten through below link with community license, however the version you get is always the latest ICC version, the verification for that version might not have been performed yet, please feedback through O-DU Low WIKI page if you meet any issues.
https://software.intel.com/en-us/system-studio/choose-download
-* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App, which is not needed if running sample APP for O-RAN FHI is not performed.
+* Optionally Octave v3.8.2 can be used to generate reference IQ samples (octave-3.8.2-20.el7.x86_64) for O-RAN FH Sample App. Only needed to run the sample APP for O-RAN FHI.
diff --git a/docs/PTP-configuration_fh.rst b/docs/PTP-configuration_fh.rst
index 63135b8..52e35ce 100644
--- a/docs/PTP-configuration_fh.rst
+++ b/docs/PTP-configuration_fh.rst
@@ -22,13 +22,13 @@
A.5 PTP Synchronization
-----------------------
Precision Time Protocol (PTP) provides an efficient way to synchronize
-time on the network nodes. This protocol uses Master-Slave architecture.
-Grandmaster Clock (Master) is a reference clock for the other nodes,
-which adapt their clocks to the master.
+time on the network nodes. This protocol uses Primary-Slave architecture.
+Main Reference Clock (Primary) is a reference clock for the other nodes,
+which adapt their clocks to the Primary.
-Using Physical Hardware Clock (PHC) from the Grandmaster Clock, NIC port
-precision timestamp packets can be served for other network nodes. Slave
-nodes adjust their PHC to the master following the IEEE 1588
+Using Physical Hardware Clock (PHC) from the Main Reference Clock, NIC port
+precision timestamp packets can be served for other network nodes. Secondary
+nodes adjust their PHC to the Primary following the IEEE 1588
specification.
There are existing implementations of PTP protocol that are widely used
@@ -128,8 +128,7 @@
----------
This tool handles all PTP traffic on the provided NIC port and updated
-PHC. It also determines the Grandmaster Clock and tracks |br|
-synchronization
+PHC. It also determines the Primary Reference Clock and tracks synchronization
status. This tool can be run as a daemon or as a regular Linux\*
application. When the synchronization is reached, it gives output on the
screen for precision tracking. The configuration file of ptp4l contains
@@ -142,61 +141,59 @@
./ptp4l -f ./configs/default.cfg -2 -i <if_name> -m
-The output below shows what the output on non-master node should look
+The output below shows what the output on non-Primary node should look
like when synchronization is started. This means that PHC on this
-machine is synchronized to the master PHC::
+machine is synchronized to the Primary PHC::
ptp4l[1434165.358]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE
ptp4l[1434165.358]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[1434166.384]: port 1: new foreign master fcaf6a.fffe.029708-1
+ ptp4l[1434166.384]: port 1: new foreign primary fcaf6a.fffe.029708-1
- ptp4l[1434170.352]: selected best master clock fcaf6a.fffe.029708
+ ptp4l[1434170.352]: selected best primary clock fcaf6a.fffe.029708
ptp4l[1434170.352]: updating UTC offset to 37
ptp4l[1434170.352]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
- ptp4l[1434171.763]: master offset -5873 s0 freq -18397 path delay 2778
+ ptp4l[1434171.763]: primary offset -5873 s0 freq -18397 path delay 2778
- ptp4l[1434172.763]: master offset -6088 s2 freq -18612 path delay 2778
+ ptp4l[1434172.763]: primary offset -6088 s2 freq -18612 path delay 2778
ptp4l[1434172.763]: port 1: UNCALIBRATED to SLAVE on
MASTER_CLOCK_SELECTED
- ptp4l[1434173.763]: master offset -5886 s2 freq -24498 path delay 2732
+ ptp4l[1434173.763]: primary offset -5886 s2 freq -24498 path delay 2732
- ptp4l[1434174.763]: master offset 221 s2 freq -20157 path delay 2728
+ ptp4l[1434174.763]: primary offset 221 s2 freq -20157 path delay 2728
- ptp4l[1434175.763]: master offset 1911 s2 freq -18401 path delay 2724
+ ptp4l[1434175.763]: primary offset 1911 s2 freq -18401 path delay 2724
- ptp4l[1434176.763]: master offset 1774 s2 freq -17964 path delay 2728
+ ptp4l[1434176.763]: primary offset 1774 s2 freq -17964 path delay 2728
- ptp4l[1434177.763]: master offset 1198 s2 freq -18008 path delay 2728
+ ptp4l[1434177.763]: primary offset 1198 s2 freq -18008 path delay 2728
- ptp4l[1434178.763]: master offset 746 s2 freq -18101 path delay 2755
+ ptp4l[1434178.763]: primary offset 746 s2 freq -18101 path delay 2755
- ptp4l[1434179.763]: master offset 218 s2 freq -18405 path delay 2792
+ ptp4l[1434179.763]: primary offset 218 s2 freq -18405 path delay 2792
- ptp4l[1434180.763]: master offset 103 s2 freq -18454 path delay 2792
+ ptp4l[1434180.763]: primary offset 103 s2 freq -18454 path delay 2792
- ptp4l[1434181.763]: master offset -13 s2 freq -18540 path delay 2813
+ ptp4l[1434181.763]: primary offset -13 s2 freq -18540 path delay 2813
- ptp4l[1434182.763]: master offset 9 s2 freq -18521 path delay 2813
+ ptp4l[1434182.763]: primary offset 9 s2 freq -18521 path delay 2813
- ptp4l[1434183.763]: master offset 11 s2 freq -18517 path delay 2813
+ ptp4l[1434183.763]: primary offset 11 s2 freq -18517 path delay 2813
phc2sys
-----------
The PHC clock is independent from the system clock. Synchronizing only
-PHC does not make the system clock exactly the same as the master. The
+PHC does not make the system clock exactly the same as the primary. The
xRAN library requires use of the system clock to determine a common
-point in time on two |br|
-machines (O-DU and RU) to start transmission at the
-same moment and keep time frames defined by ORAN Fronthaul |br|
-specification.
+point in time on two machines (O-DU and RU) to start transmission at the
+same moment and keep time frames defined by ORAN Fronthaul specification.
This application keeps the system clock updated to PHC. It makes it
possible to use POSIX timers as a time reference in xRAN application.
@@ -264,9 +261,8 @@
Configuration C3 27 can be simulated for O-DU using a separate server
acting as Fronthaul Network and O-RU at the same time. O-RU server can
-be configured to relay PTP and act as PTP master for O-DU. Settings
-below can be used to |br|
-instantiate this scenario. The difference is that
+be configured to relay PTP and act as PTP primary for O-DU. Settings
+below can be used to instantiate this scenario. The difference is that
on the O-DU side, the Fronthaul port can be used as the source of PTP as
well as for U-plane and C-plane traffic.
@@ -369,7 +365,7 @@
# Run time options
-1.Start slave port toward PTP GM::
+1.Start secondary port toward PTP GM::
./ptp4l -f ./configs/default_slave.cfg -2 -i enp25s0f0 –m
@@ -383,28 +379,28 @@
ptp4l[3904470.275]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[3904471.085]: port 1: new foreign master fcaf6a.fffe.029708-1
+ ptp4l[3904471.085]: port 1: new foreign primary fcaf6a.fffe.029708-1
- ptp4l[3904475.053]: selected best master clock fcaf6a.fffe.029708
+ ptp4l[3904475.053]: selected best primary clock fcaf6a.fffe.029708
ptp4l[3904475.053]: updating UTC offset to 37
ptp4l[3904475.053]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
- ptp4l[3904477.029]: master offset 196 s0 freq -18570 path delay 1109
+ ptp4l[3904477.029]: primary offset 196 s0 freq -18570 path delay 1109
- ptp4l[3904478.029]: master offset 212 s2 freq -18554 path delay 1109
+ ptp4l[3904478.029]: primary offset 212 s2 freq -18554 path delay 1109
ptp4l[3904478.029]: port 1: UNCALIBRATED to SLAVE on
MASTER_CLOCK_SELECTED
- ptp4l[3904479.029]: master offset 86 s2 freq -18468 path delay 1109
+ ptp4l[3904479.029]: primary offset 86 s2 freq -18468 path delay 1109
- ptp4l[3904480.029]: master offset 23 s2 freq -18505 path delay 1124
+ ptp4l[3904480.029]: primary offset 23 s2 freq -18505 path delay 1124
- ptp4l[3904481.029]: master offset 3 s2 freq -18518 path delay 1132
+ ptp4l[3904481.029]: primary offset 3 s2 freq -18518 path delay 1132
- ptp4l[3904482.029]: master offset -169 s2 freq -18689 path delay 1141
+ ptp4l[3904482.029]: primary offset -169 s2 freq -18689 path delay 1141
2.Synchronize local timer clock on O-RU for sample application::
@@ -450,7 +446,7 @@
phc2sys[3904512.268]: CLOCK_REALTIME phc offset -300 s2 freq -38892
delay 1532
-3. Modify configs/default.cfg as shown below to run PTP master on
+3. Modify configs/default.cfg as shown below to run PTP primary on
Fronthaul of O-RU::
diff --git a/configs/default.cfg b/configs/default.cfg
@@ -517,7 +513,7 @@
# Run time options
-4.Start PTP master toward O-DU::
+4.Start PTP primary toward O-DU::
./ptp4l -f ./configs/default.cfg -2 -i enp175s0f1 –m
@@ -535,11 +531,11 @@
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
ptp4l[3903863.734]: selected local clock 3cfdfe.fffe.bd005d as best
- master
+ primary
- ptp4l[3903863.734]: assuming the grand master role
+ ptp4l[3903863.734]: assuming the main reference role
-5.Synchronize local NIC PTP master clock to local NIC PTP slave clock::
+5.Synchronize local NIC PTP primary clock to local NIC PTP secondary clock::
./phc2sys -c enp175s0f1 -s enp25s0f0 -w -m -R 8
@@ -594,7 +590,7 @@
6. On O-DU Install PTP for Linux tools from source code the same way as
on O-RU above but no need to apply the patch for msg.c
-7. Start slave port toward PTP master from O-RU using the same
+7. Start secondary port toward PTP primary from O-RU using the same
default_slave.cfg as on O-RU (see above)::
./ptp4l -f ./configs/default_slave.cfg -2 -i enp181s0f0 –m
@@ -609,9 +605,9 @@
ptp4l[809092.934]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE
- ptp4l[809092.949]: port 1: new foreign master 3cfdfe.fffe.bd005d-1
+ ptp4l[809092.949]: port 1: new foreign primary 3cfdfe.fffe.bd005d-1
- ptp4l[809096.949]: selected best master clock 3cfdfe.fffe.bd005d
+ ptp4l[809096.949]: selected best primary clock 3cfdfe.fffe.bd005d
ptp4l[809096.950]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
@@ -711,8 +707,11 @@
requests for current port state and comparing it with the expected
value. This verification should be done before initialization.
-*notes. “SLAVE” is the only expected value in this release; only a
-non-master scenario is supported currently.*
+*notes. “SECONDARY” is the only expected value in this release; only a
+non-primary scenario is supported currently.*
+
+*notes1. Inclusive language terms were used except for the PTP traces where the source code has
+not been updated to support the inclusive language terms yet.*
.. |image0| image:: media/image3.png
:width: 2.52364in
diff --git a/docs/Setup-Configuration_fh.rst b/docs/Setup-Configuration_fh.rst
index 5108267..3a93e81 100644
--- a/docs/Setup-Configuration_fh.rst
+++ b/docs/Setup-Configuration_fh.rst
@@ -74,88 +74,48 @@
The recommended configuration for NICs is::
- ethtool -i enp216s0f0
-
+ ethtool -i enp33s0f0
driver: i40e
-
- version: 2.9.21
-
- firmware-version: 6.80 0x80003d05 1.2007.0
-
+ version: 2.10.19.82
+ firmware-version: 7.20 0x80007949 1.2585.0
expansion-rom-version:
-
- bus-info: 0000:d8:00.0
-
+ bus-info: 0000:21:00.0
supports-statistics: yes
-
supports-test: yes
-
supports-eeprom-access: yes
-
supports-register-dump: yes
-
supports-priv-flags: yes
-
- [root@5gnr-sc12-xran testmac]# ethtool -T enp216s0f0::
-
-
- Time stamping parameters for enp216s0f0:
-
- Capabilities:
-
- hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
-
- software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
-
- hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
-
- software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
-
- software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
-
- hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
-
- PTP Hardware Clock: 2
-
- Hardware Transmit Timestamp Modes:
-
- off (HWTSTAMP_TX_OFF)
-
- on (HWTSTAMP_TX_ON)
-
- Hardware Receive Filter Modes:
-
- none (HWTSTAMP_FILTER_NONE)
-
- ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
-
- ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
-
- ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
-
- ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
-
- ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
-
- ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
-
- ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
-
- ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
-
- ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
-
- ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
-
- ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
+ ethtool -T enp33s0f0
+ Time stamping parameters for enp33s0f0:
+ Capabilities:
+ hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)
+ software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)
+ hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)
+ software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)
+ software-system-clock (SOF_TIMESTAMPING_SOFTWARE)
+ hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)
+ PTP Hardware Clock: 4
+ Hardware Transmit Timestamp Modes:
+ off (HWTSTAMP_TX_OFF)
+ on (HWTSTAMP_TX_ON)
+ Hardware Receive Filter Modes:
+ none (HWTSTAMP_FILTER_NONE)
+ ptpv1-l4-sync (HWTSTAMP_FILTER_PTP_V1_L4_SYNC)
+ ptpv1-l4-delay-req (HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ)
+ ptpv2-l4-event (HWTSTAMP_FILTER_PTP_V2_L4_EVENT)
+ ptpv2-l4-sync (HWTSTAMP_FILTER_PTP_V2_L4_SYNC)
+ ptpv2-l4-delay-req (HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ)
+ ptpv2-l2-event (HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
+ ptpv2-l2-sync (HWTSTAMP_FILTER_PTP_V2_L2_SYNC)
+ ptpv2-l2-delay-req (HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ)
+ ptpv2-event (HWTSTAMP_FILTER_PTP_V2_EVENT)
+ ptpv2-sync (HWTSTAMP_FILTER_PTP_V2_SYNC)
+ ptpv2-delay-req (HWTSTAMP_FILTER_PTP_V2_DELAY_REQ)
-PTP Grand Master is required to be available in the network to provide
+
+A PTP Main Reference Clock is required to be available in the network to provide
synchronization of both O-DU and RU to GPS time.
-The software package includes Linux\* CentOS\* operating system and RT
-patch according to *Cloud-Native*-platform *Setup* document (refer to
-Table 2). Only real-time HOST is required.
-
1.Installing Intel® C++ Compiler v19.0.3 is preferred. or you could get
Intel® C++ Compiler through below link with community license,
however the version you could get is always latest version, the
@@ -163,11 +123,9 @@
feedback through O-DU Low project WIKI page if you meet an issue. |br|
`https://software.intel.com/en-us/system-studio/choose-download <https://software.intel.com/en-us/system-studio/choose-download%20>`__
-2.Download DPDK 18.08.
+2.Download DPDK 19.11.
-3.With FlexRAN BBDev patch as per release 20.02. (Note currently this may require a license from Intel)
-
-4.Change DPDK files according to below diff information which relevant to O-RAN FH::
+3.Change DPDK files according to below diff information which relevant to O-RAN FH::
diff --git a/drivers/net/i40e/i40e_ethdev.c
b/drivers/net/i40e/i40e_ethdev.c
@@ -282,11 +240,11 @@
[root@xran dpdk]# ./usertools/dpdk-setup.sh
- select [16] x86_64-native-linuxapp-icc
+ select [39] x86_64-native-linuxapp-icc
- select [19] Insert VFIO module
+ select [46] Insert VFIO module
- exit [35] Exit Script
+ exit [62] Exit Script
6.Make below file changes in dpdk that assure i40e to get best
latency of packet processing::
@@ -337,67 +295,49 @@
cat /proc/cmdline
- BOOT_IMAGE=/vmlinuz-3.10.0-957.10.1.rt56.921.el7.x86_64
- root=/dev/mapper/centos-root ro crashkernel=auto rd.lvm.lv=centos/root
- rd.lvm.lv=centos/swap intel_iommu=on iommu=pt usbcore.autosuspend=-1
- selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
- intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off
- idle=poll hugepagesz=1G hugepages=40 hugepagesz=2M hugepages=0
- default_hugepagesz=1G isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39
- kthread_cpus=0,20 irqaffinity=0,20 nohz_full=1-19,21-39
+ BOOT_IMAGE=/vmlinuz-3.10.0-1062.12.1.rt56.1042.el7.x86_64 root=/dev/mapper/centos-root ro
+ crashkernel=auto rd.lvm.lv=centos/root rd.lvm.lv=centos/swap intel_iommu=on iommu=pt
+ usbcore.autosuspend=-1 selinux=0 enforcing=0 nmi_watchdog=0 softlockup_panic=0 audit=0
+ intel_pstate=disable cgroup_memory=1 cgroup_enable=memory mce=off idle=poll
+ hugepagesz=1G hugepages=16 hugepagesz=2M hugepages=0 default_hugepagesz=1G
+ isolcpus=1-19,21-39 rcu_nocbs=1-19,21-39 kthread_cpus=0,20 irqaffinity=0,20
+ nohz_full=1-19,21-39
2.Download from Intel Website and install updated version of i40e
-driver if needed. The current recommended version of i40e is x2.9.21.
+driver if needed. The current recommended version of i40e is 2.10.19.82.
+However, any latest version of i40e after x2.9.21 expected to be functional for ORAN FH.
3.Identify PCIe Bus address of the Front Haul NIC::
- lspci \|grep Eth
-
- 19:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 19:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 41:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- 41:00.1 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- d8:00.0 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02) <<< port used for FH
-
- d8:00.1 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
+ lspci |grep Eth
+ 19:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 19:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 1d:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 1d:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 Intel(R) FPGA Programmable Acceleration Card N3000 for Networking (rev 02)
+ 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 67:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722 for 10GBASE-T (rev 09)
+
4.Identify the Ethernet device name::
- ethtool -i enp216s0f0
-
+ ethtool -i enp33s0f0
driver: i40e
-
- version: 2.9.21
-
- firmware-version: 6.80 0x80003d05 1.2007.0
-
+ version: 2.10.19.82
+ firmware-version: 7.20 0x80007949 1.2585.0
expansion-rom-version:
-
- bus-info: 0000:d8:00.0
-
+ bus-info: 0000:21:00.0
supports-statistics: yes
-
supports-test: yes
-
supports-eeprom-access: yes
-
supports-register-dump: yes
-
supports-priv-flags: yes
+ Enable
+
5.Enable two virtual functions (VF) on the device::
- echo 2 > /sys/class/net/enp216s0f0/device/sriov_numvfs
+ echo 2 > /sys/class/net/enp33s0f0/device/sriov_numvfs
More information about VFs supported by Intel NICs can be found at
https://doc.dpdk.org/guides/nics/intel_vf.html.
@@ -407,110 +347,105 @@
lspci|grep Eth
- 19:00.0 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 19:00.1 Ethernet controller: Intel Corporation 82599ES 10-Gigabit
- SFI/SFP+ Network Connection (rev 01)
-
- 41:00.0 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- 41:00.1 Ethernet controller: Intel Corporation Ethernet Connection X722
- for 10GBASE-T (rev 04)
-
- d8:00.0 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
-
- d8:00.1 Ethernet controller: Intel Corporation Ethernet Controller XL710
- for 40GbE QSFP+ (rev 02)
-
- d8:02.0 Ethernet controller: Intel Corporation XL710/X710 Virtual
- Function (rev 02)
-
- d8:02.1 Ethernet controller: Intel Corporation XL710/X710 Virtual
- Function (rev 02)
+ 21:00.0 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:00.1 Ethernet controller: Intel Corporation Ethernet Controller XXV710 for 25GbE SFP28 (rev 02)
+ 21:02.0 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
+ 21:02.1 Ethernet controller: Intel Corporation Ethernet Virtual Function 700 Series (rev 02)
+
6.Configure MAC address and VLAN settings for VFs for XRAN, based on
requirements for xRAN scenario and assignment of VLAN ID using IP
-tool perform configuration of VF as shown below::
-
- [root@xran app]# ip link set enp216s0f0 vf 0 mac 00:11:22:33:44:66 vlan
- 2
+tool perform configuration of VF.
- [root@xran app]# ip link set enp216s0f0 vf 1 mac 00:11:22:33:44:66 vlan
- 1
+ Example where O-DU and O-RU simulation run on the same sytem::
+
+ #!/bin/bash
+
+ echo 2 > /sys/bus/pci/devices/0000\:21\:00.0/sriov_numvfs
+ ip link set enp33s0f0 vf 1 mac 00:11:22:33:44:66 vlan 1
+ ip link set enp33s0f0 vf 0 mac 00:11:22:33:44:66 vlan 2
+ echo 2 > /sys/bus/pci/devices/0000\:21\:00.1/sriov_numvfs
+ ip link set enp33s0f1 vf 1 mac 00:11:22:33:44:55 vlan 1
+ ip link set enp33s0f1 vf 0 mac 00:11:22:33:44:55 vlan 2
+
+ where output is next::
[root@xran app]# ip link show
- 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode
- DEFAULT qlen 1
+ 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
- 2: enp65s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 2: enp25s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether a4:bf:01:3e:6b:79 brd ff:ff:ff:ff:ff:ff
+ link/ether 64:4c:36:10:1f:30 brd ff:ff:ff:ff:ff:ff
- 3: eno2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP
- mode DEFAULT qlen 1000
+ 3: enp25s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether a4:bf:01:3e:6b:7a brd ff:ff:ff:ff:ff:ff
+ link/ether 64:4c:36:10:1f:31 brd ff:ff:ff:ff:ff:ff
- 4: enp25s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 4: enp29s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 90:e2:ba:d3:b2:ec brd ff:ff:ff:ff:ff:ff
+ link/ether 64:4c:36:10:1f:34 brd ff:ff:ff:ff:ff:ff
- 5: enp129s0f0: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ 5: enp29s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:a8:e0:70 brd ff:ff:ff:ff:ff:ff
+ link/ether 64:4c:36:10:1f:35 brd ff:ff:ff:ff:ff:ff
- 6: enp129s0f1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ 6: enp33s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:a8:e0:71 brd ff:ff:ff:ff:ff:ff
+ link/ether 3c:fd:fe:b9:f8:b4 brd ff:ff:ff:ff:ff:ff
- 7: enp216s0f0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto, trust off
- link/ether 3c:fd:fe:9e:93:68 brd ff:ff:ff:ff:ff:ff
+ vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto, trust off
- vf 0 MAC 00:11:22:33:44:66, vlan 2, spoof checking on, link-state auto,
- trust off
+ 7: enp33s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- vf 1 MAC 00:11:22:33:44:66, vlan 1, spoof checking on, link-state auto,
- trust off
+ link/ether 3c:fd:fe:b9:f8:b5 brd ff:ff:ff:ff:ff:ff
- 8: enp25s0f1: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq
- state DOWN mode DEFAULT qlen 1000
+ vf 0 MAC 00:11:22:33:44:55, vlan 2, spoof checking on, link-state auto, trust off
- link/ether 90:e2:ba:d3:b2:ed brd ff:ff:ff:ff:ff:ff
+ vf 1 MAC 00:11:22:33:44:55, vlan 1, spoof checking on, link-state auto, trust off
- 9: enp216s0f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 8: eno1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 3c:fd:fe:9e:93:69 brd ff:ff:ff:ff:ff:ff
+ link/ether a4:bf:01:3e:1f:be brd ff:ff:ff:ff:ff:ff
- 12: enp216s2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state
- UP mode DEFAULT qlen 1000
+ 9: eno2: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP mode DEFAULT group default qlen 1000
- link/ether 96:fa:4d:04:4d:87 brd ff:ff:ff:ff:ff:ff
+ link/ether a4:bf:01:3e:1f:bf brd ff:ff:ff:ff:ff:ff
- 13: enp216s2f1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq
- state UP mode DEFAULT qlen 1000
+ 10: npacf0g0l0: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
- link/ether a6:67:49:bb:bd:5e brd ff:ff:ff:ff:ff:ff
+ link/generic
+
+ 11: npacf0g0l1: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
+
+ link/generic
+
+ 12: npacf0g0l2: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
+
+ link/generic
+
+ 13: npacf0g0l3: <LOWER_UP> mtu 9600 qdisc noop state UNKNOWN mode DEFAULT group default qlen 1000
+
+ link/generic
After this step FH NIC is configured.
-VF for C-plane is VF1 on PH enp216s0f0, it has ETH mac address
-00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is d8:02.1
+O-DU
+
+VF for C-plane is VF1 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 1. PCIe Bus address is VF1 is 21d8:02.1
-VF for U-plane is VF0 on PH enp216s0f0, it has ETH mac address
-00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is d8:02.0
+VF for U-plane is VF0 on PFH enp33s0f0enp216s0f0, it has ETH mac address 00:11:22:33:44:66 and VLAN tag 2. PCIe Bus address is VF1 is 21d8:02.0
+
+O-RU
+
+VF for C-plane is VF1 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 1. PCIe Bus address is VF1 is 21:0a.1
+
+VF for U-plane is VF0 on PF enp33s0f1, it has ETH mac address 00:11:22:33:44:55 and VLAN tag 2. PCIe Bus address is VF1 is 21:0a.0
+
A.4 Install and Configure Sample Application
--------------------------------------------
@@ -520,7 +455,7 @@
export GTEST_ROOT=`pwd`/gtest-1.7.0
- export RTE_SDK=`pwd`/dpdk-18.08
+ export RTE_SDK=`pwd`/dpdk-19.11
export RTE_TARGET=x86_64-native-linuxapp-icc
@@ -552,8 +487,7 @@
Update run_o_du.sh (run_o_ru.sh) with PCIe bus address of VF0 and VF1
used for U-plane and C-plane correspondingly::
- ./build/sample-app ./usecase/mu0_10mhz/config_file_o_du.dat 0000:d8:02.0
- 0000:d8:02.1
+ ./build/sample-app -c ./usecase/mu0_10mhz/config_file_o_du.dat -p 2 0000:21d8:02.0 0000:21d8:02.1
4. Run application using run_o_du.sh (run_o_ru.sh).
diff --git a/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst b/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst
index 661f09e..1a64844 100644
--- a/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst
+++ b/docs/Transport-Layer-and-ORAN-Fronthaul-Protocol-Implementation_fh.rst
@@ -40,29 +40,26 @@
Figure 8. ORAN Fronthaul Process
The XRAN library provides support for transporting In-band and
-Quadrature (IQ) samples between the O-DU and O-RU within the RAN
+Quadrature (IQ) samples between the O-DU and O-RU within the xRAN
architecture based on functional split 7.2x. The library defines the
xRAN packet formats to be used to transport radio samples within Front
Haul according to the ORAN Fronthaul specification. It provides
functionality for generating xRAN packets, appending IQ samples in the
-packet payload, and extracting IQ samples from xRAN packets. The Bronze release version
-of the library supports U-plane and C-plane only. It is ready to
-be used in the PTP synchronized |br|
-environment.
+packet payload, and extracting IQ samples from xRAN packets.
-Regarding the clock model and synchronization topology, configurations
+Note: The Bronze release version of the library supports U-plane and C-plane only. It is ready to be used in the PTP synchronized environment.
+
+Note: Regarding the clock model and synchronization topology, configurations
C1 and C3 of the connection between O-DU and O-RU are the only
configurations supported in this release of the xRAN implementation.
-Quality of PTP synchronization with respect to S-plane of ORAN Fronthaul
-requirements as defined for O-RU is out of the scope of this document.
-PTP master and PTP slave configuration are expected to satisfy only the
-O-DU side of |br|
-requirements and provide the “best-effort” PTP master for
+Note: Quality of PTP synchronization with respect to S-plane of ORAN
+Fronthaul requirements as defined for O-RU is out of the scope of this
+document. PTP primary and PTP secondary configuration are expected to satisfy
+only the O-DU side of requirements and provide the “best-effort” PTP primary for
O-RU. This may or may not be sufficient for achieving the end to end
system requirements of S-plane. Specialized dedicated NIC card with
-additional HW functionality might be |br|
-required to achieve PTP master
+additional HW functionality might be required to achieve PTP primary
functionality to satisfy O-RU precision requirements for RAN deployments
scenarios.
@@ -83,13 +80,12 @@
---------------------
The ORAN Fronthaul specification defines a list of mandatory
-functionality. Not all features defined as Mandatory for |br|
-O-DU are
+functionality. Not all features defined as Mandatory for O-DU are
currently supported to fully extended. The following tables contain
information on what is available and the level of validation performed
for this release.
-2. Cells with a red background are listed as mandatory in the
+Note. Cells with a red background are listed as mandatory in the
specification but not supported in this implementation of xRAN.
Table 7. ORAN Mandatory and Optional Feature Support
@@ -103,7 +99,7 @@
| | 8 spatial | | |
| | streams) | | |
+-----------------+-----------------+-----------+----------------+
-| | Support for | | N |
+| | Support for | | Y |
| | CAT-A RU (> 8 | | |
| | spatial | | |
| | streams) | | |
@@ -126,13 +122,12 @@
| | UE Channel Info | | N |
+-----------------+-----------------+-----------+----------------+
| Bandwidth | Programmable | Mandatory | Y |
-| Saving | s | | |
-| | tatic-bit-width | | |
+| Saving | static-bit-width| | |
| | Fixed Point IQ | | |
+-----------------+-----------------+-----------+----------------+
-| | Real-time | | Y |
-| | var | | |
-| | iable-bit-width | | |
+| | Real-time | | Y |
+| | variable-bit | | |
+| | -width | | |
+-----------------+-----------------+-----------+----------------+
| | Compressed IQ | | Y |
+-----------------+-----------------+-----------+----------------+
@@ -247,7 +242,7 @@
Table 8. Levels of Validation
+------------+------------+------------+------------+-----+-----+---+
-| Category | Item | Q4 (20.02) | | | | |
+| Category | Item | Q4 (20.04) | | | | |
+============+============+============+============+=====+=====+===+
| | | Status | C | I | T | |
+------------+------------+------------+------------+-----+-----+---+
@@ -407,7 +402,7 @@
| | and | | | | | |
| | U-plane | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Max Number | 4 | Y | Y | N | |
+| | Max Number | 16 | Y | Y | N | |
| | of VLAN | | | | | |
| | per | | | | | |
| | physical | | | | | |
@@ -430,7 +425,7 @@
| | Total | Supported | Y | N | N | |
| | _msgs_rcvd | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| B\ | RU | Index and | Y | N | N | |
+| B\ | RU | Index and | Y | Y | N | |
| eamforming | b\ | weights | | | | |
| | eamforming | | | | | |
| | type | | | | | |
@@ -440,16 +435,16 @@
| | control | | | | | |
| | method | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Number of | No-re | Y | N | N | |
+| | Number of | No-re | Y | Y | N | |
| | beams | strictions | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| IQ | U-plane | Supported | Y | N | N | |
+| IQ | U-plane | Supported | Y | Y | Y | |
| c\ | data | | | | | |
| ompression | c\ | | | | | |
| | ompression | | | | | |
| | method | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | U-plane | BFP: | Y | N | N | |
+| | U-plane | BFP: | Y | Y | Y | |
| | data IQ | 8,9,12,14 | | | | |
| | bitwidth | bits | | | | |
| | (Before / | | | | | |
@@ -457,7 +452,7 @@
| | co | | | | | |
| | mpression) | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Static | Supported | Y | Y | N | |
+| | Static | Supported | N | N | N | |
| | con\ | | | | | |
| | figuration | | | | | |
| | of U-plane | | | | | |
@@ -516,7 +511,7 @@
| | Section | Supported | Y | Y | Y | |
| | Type 1 | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | Section | Supported | Y | Y | N | |
+| | Section | Supported | Y | Y | Y | |
| | Type 3 | | | | | |
+------------+------------+------------+------------+-----+-----+---+
| | Section | Not | N | N | N | |
@@ -579,7 +574,7 @@
| | | (section | | | | |
| | | type) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | udCompHdr | Supported | N | N | N |
+| | | udCompHdr | Supported | Y | Y | N |
| | | (user data | | | | |
| | | c\ | | | | |
| | | ompression | | | | |
@@ -795,15 +790,15 @@
| | | Extension | | | | |
| | | Commands* | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | extType | Supported | Y | N | N |
+| | | extType | Supported | Y | Y | N |
| | | (extension | | | | |
| | | type) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | ef | Supported | Y | N | N |
+| | | ef | Supported | Y | Y | N |
| | | (extension | | | | |
| | | flag) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | extLen | Supported | Y | N | N |
+| | | extLen | Supported | Y | Y | N |
| | | (extension | | | | |
| | | length) | | | | |
+------------+------------+------------+------------+-----+-----+---+
@@ -818,7 +813,7 @@
| | E\ | | | | | |
| | xtensions | | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | *ExtType=1:| bfwCompHdr | Supported | Y | N | N |
+| | *ExtType=1:| bfwCompHdr | Supported | Y | Y | N |
| | B\ | (beam\ | | | | |
| | eamforming | forming | | | | |
| | Weights | weight | | | | |
@@ -826,7 +821,7 @@
| | Type* | ompression | | | | |
| | | header) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bf | Supported | Y | N | N |
+| | | bf | Supported | Y | Y | N |
| | | wCompParam | | | | |
| | | (b\ | | | | |
| | | eamforming | | | | |
@@ -835,14 +830,14 @@
| | | ompression | | | | |
| | | parameter) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bfwl | Supported | Y | N | N |
+| | | bfwl | Supported | Y | Y | N |
| | | (b\ | | | | |
| | | eamforming | | | | |
| | | weight | | | | |
| | | in-phase | | | | |
| | | value) | | | | |
+------------+------------+------------+------------+-----+-----+---+
-| | | bfwQ | Supported | Y | N | N |
+| | | bfwQ | Supported | Y | Y | N |
| | | (b\ | | | | |
| | | eamforming | | | | |
| | | weight | | | | |
@@ -1170,8 +1165,7 @@
are supported.
Handling of ecpriRtcid/ecpriPcid Bit field size is configurable and can
-be defined on the initialization stage of the xRAN |br|
-library.
+be defined on the initialization stage of the xRAN library.
.. image:: images/Bit-Allocations-of-ecpriRtcid-ecpriPcid.jpg
:width: 600
@@ -1186,8 +1180,7 @@
-------
The following diagrams show xRAN packet protocols’ headers and data
-arrangement with and without compression |br|
-support.
+arrangement with and without compression support.
XRAN packet meant for traffic with compression enabled has the
Compression Header added after each Application Header. According to
@@ -1233,8 +1226,7 @@
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The Common Radio Application Header is followed by the Application
-Header that is repeated for each Data Section |br|
-within the eCPRI message.
+Header that is repeated for each Data Section within the eCPRI message.
The relevant section of xRAN packet is shown in color.
.. image:: images/Data-Section-Application-Data-Header.jpg
@@ -1255,9 +1247,7 @@
~~~~~~~~~~~~
An xRAN packet data payload contains a number of PRBs. Each PRB is built
-of 12 IQ samples. The supported IQ bit width is 16. udCompParam is not
-included in the data payload as compression currently is not supported.
-The data section is shown in color.
+of 12 IQ samples. Flexible IQ bit width is supported. If compression is enabled udCompParam is included in the data payload. The data section is shown in colour.
.. image:: images/Data-Payload.jpg
:width: 600
@@ -1271,15 +1261,11 @@
C-Plane messages are encapsulated using a two-layered header approach.
The first layer consists of an eCPRI standard header, including
corresponding fields used to indicate the message type, while the second
-layer is an application layer |br|
-including necessary fields for control and
-synchronization. Within the application layer, a “section” defines the |br|
-characteristics of U-plane data to be transferred or received from a
-beam with one pattern id. In general, the transport header, |br|
-application
+layer is an application layer including necessary fields for control and
+synchronization. Within the application layer, a “section” defines the characteristics of U-plane data to be transferred or received from a
+beam with one pattern id. In general, the transport header,application
header, and sections are all intended to be aligned on 4-byte boundaries
-and are transmitted in “network byte |br|
-order” meaning the most significant
+and are transmitted in “network byte order” meaning the most significant
byte of a multi-byte parameter is transmitted first.
Table 9 is a list of sections currently supported.
@@ -1318,9 +1304,11 @@
Section extensions are not supported in this release.
The definition of the C-Plane packet can be found lib/api/xran_pkt_cp.h
-and the fields are appropriately re-ordered in |br|
-order to apply the
+and the fields are appropriately re-ordered in order to apply the
conversion of network byte order after setting values.
+The comments in source code of xRAN lib can be used to see more information on
+implementation specifics of handling sections as well as particular fields.
+Additional changes may be needed on C-plane to perform IOT with O-RU depending on the scenario.
Ethernet Header
~~~~~~~~~~~~~~~
@@ -1419,7 +1407,7 @@
- timeOffset
-- frameStrucutre: defined as the structure of
+- frameStructure: defined as the structure of
xran_cp_radioapp_frameStructure
- cpLength
diff --git a/docs/build_prerequisite.rst b/docs/build_prerequisite.rst
index b62cce1..a4f018f 100644
--- a/docs/build_prerequisite.rst
+++ b/docs/build_prerequisite.rst
@@ -28,7 +28,7 @@
Install ICC
------------
Intel® C++ Compiler v19.0.3 is used for the test application and system integration with L1,
-The Intel® C++ Compiler can be obtained using the follwoing link https://software.intel.com/en-us/system-studio/choose-download with community |br|
+The Intel® C++ Compiler can be obtained using the following link https://software.intel.com/en-us/system-studio/choose-download with community |br|
license::
COPY $icc_license_file $BUILD_DIR/license.lic
@@ -37,11 +37,12 @@
performed yet, so please provide feedback through O-DU Low project WIKI page if you face any issues.*
-Download Intel System Studio from Intel website and install ICC ::
+You can follow the installation guide from above website to download Intel System Studio and install. Intel® Math Kernel Library, Intel® Integrated Performance Primitives and Intel® C++ Compiler are mandatory components.
+Here we are using the Linux* Host,Linux* Target and standalone installer as one example, below link might need update based on the website ::
- #wget https://registrationcenter-download.intel.com/akdlm/irc_nas/16242/system_studio_2020_ultimate_edition_offline.tar.gz
+ #wget https://registrationcenter-download.intel.com/akdlm/irc_nas/16789/system_studio_2020_u2_ultimate_edition_offline.tar.gz
#cd /opt && mkdir intel && cp $BUILD_DIR/license.lic intel/license.lic
- #tar -zxvf $BUILD_DIR/system_studio_2020_ultimate_edition_offline.tar.gz
+ #tar -zxvf $BUILD_DIR/system_studio_2020_u2_ultimate_edition_offline.tar.gz
Edit system_studio_2020_ultimate_edition_offline/silent.cfg to accept the EULA file as below example::
@@ -60,36 +61,32 @@
#export PATH=/opt/intel/system_studio_2020/bin/:$PATH
-Build DPDK
------------
+Download and Build DPDK
+-----------------------
- download DPDK::
- #wget http://fast.dpdk.org/rel/dpdk-18.08.tar.xz
- #tar -xf dpdk-18.08.tar.xz
+ #wget http://static.dpdk.org/rel/dpdk-19.11.tar.x
+ #tar -xf dpdk-19.11.tar.xz
#export RTE_TARGET=x86_64-native-linuxapp-icc
- #export RTE_SDK=Intallation_DIR/dpdk-18.08
+ #export RTE_SDK=Intallation_DIR/dpdk-19.11
- - patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites
+ - patch DPDK for O-RAN FHI lib, this patch is specific for O-RAN FHI to reduce the data transmission latency of Intel NIC. This may not be needed for some NICs, please refer to |br| O-RAN FHI Lib Introduction -> setup configuration -> A.2 prerequisites
- - SW FEC was enabled by default, to enable HW FEC with specific accelerator card, you need get the associated driver and build steps from the accelerator card vendors.
+ - SW FEC was enabled by default, to enable HW FEC with specific accelerator card, you need to get the associated driver and build steps from the accelerator card vendors.
- - enable IGB UIO for NIC card::
-
- CONFIG_RTE_EAL_IGB_UIO=y
- CONFIG_RTE_KNI_KMOD=y
- build DPDK
build DPDK::
#./usertools/dpdk-setup.sh
- select [16] x86_64-native-linuxapp-icc
- select [19] Insert VFIO module
- exit [35] Exit Script
+ select [39] x86_64-native-linuxapp-icc
+ exit [62] Exit Script
- set DPDK path
DPDK path is needed during build and run lib/app::
- #export RTE_SDK="your DPDK path"
+ #export RTE_SDK=Intallation_DIR/dpdk-19.11
+ #export DESTDIR=Installation_DIR/dpdk-19.11
Install google test
@@ -100,6 +97,7 @@
#tar -xvf googletest-release-1.7.0.tar.gz
#mv googletest-release-1.7.0 gtest-1.7.0
#export GTEST_DIR=YOUR_DIR/gtest-1.7.0
+ #export GTEST_ROOT= $GTEST_DIR
#cd ${GTEST_DIR}
#g++ -isystem ${GTEST_DIR}/include -I${GTEST_DIR} -pthread -c ${GTEST_DIR}/src/gtest-all.cc
#ar -rv libgtest.a gtest-all.o
@@ -117,7 +115,52 @@
Configure FEC card
--------------------
-For the Bronze Release only as SW FEC is available so this step is not needed, for later releases the required information will be added to the document.
+For the Bronze Release only a SW FEC is available so this step is not needed, for later releases the required information will be added to the document.
+
+Customize a setup environment shell script
+------------------------------------------
+Using as an example the provided in the folder phy\\setupenv.sh as the starting point
+customize this script to provide the paths to the tools and libraries that
+are used building and running the code.
+You can add for example the following entries based on your particular installation and the
+following illustration is just an example::
+
+- export DIR_ROOT=/home/
+- #set the L1 binary root DIR
+- export DIR_ROOT_L1_BIN=$DIR_ROOT/FlexRAN
+- #set the phy root DIR
+- export DIR_ROOT_PHY=$DIR_ROOT/phy
+- #set the DPDK root DIR
+- #export DIR_ROOT_DPDK=/home/dpdk-19.11
+- #set the GTEST root DIR
+- #export DIR_ROOT_GTEST=/home/gtest/gtest-1.7.0
+- export DIR_WIRELESS_TEST_5G=$DIR_ROOT_L1_BIN/testcase
+- export DIR_WIRELESS_SDK=$DIR_ROOT_L1_BIN/sdk/build-avx512-icc
+- export DIR_WIRELESS_TABLE_5G=$DIR_ROOT_L1_BIN/l1/bin/nr5g/gnb/l1/table
+- #source /opt/intel/system_studio_2019/bin/iccvars.sh intel64 -platform linux
+- export XRAN_DIR=$DIR_ROOT_PHY/fhi_lib
+- export XRAN_LIB_SO=true
+- export RTE_TARGET=x86_64-native-linuxapp-icc
+- #export RTE_SDK=$DIR_ROOT_DPDK
+- #export DESTDIR=""
+- #export GTEST_ROOT=$DIR_ROOT_GTEST
+- export ORAN_5G_FAPI=true
+- export DIR_WIRELESS_WLS=$DIR_ROOT_PHY/wls_lib
+- export DEBUG_MODE=true
+- export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_WIRELESS_WLS:$XRAN_DIR/lib/build
+- export DIR_WIRELESS=$DIR_ROOT_L1_BIN/l1
+- export DIR_WIRELESS_ORAN_5G_FAPI=$DIR_ROOT_PHY/fapi_5g
+- export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$DIR_ROOT_L1_BIN/libs/cpa/bin
+
+Then issue::
+
+- source ./setupenv.sh
+
+This sets up the correct environment to build the code
+
+Then build the wls_lib, FHI_Lib, 5G FAPI TM prior to running the code with the steps described in the Run L1 section
+
+
diff --git a/docs/fapi_5g_tm_build.rst b/docs/fapi_5g_tm_build.rst
index da40ad8..2cd1d7a 100644
--- a/docs/fapi_5g_tm_build.rst
+++ b/docs/fapi_5g_tm_build.rst
@@ -23,7 +23,7 @@
and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 18.08 but it doesn't preclude the
+The current release was tested using DPDK version 19.11 but it doesn't preclude the
use of newer releases. |br|
Also the 5G FAPI TM currently uses the Intel Compiler that is defined as part of the ODULOW documentation.
diff --git a/docs/fapi_5g_tm_overview.rst b/docs/fapi_5g_tm_overview.rst
index 4fc163c..bf32e4b 100644
--- a/docs/fapi_5g_tm_overview.rst
+++ b/docs/fapi_5g_tm_overview.rst
@@ -26,8 +26,7 @@
The ORAN FAPI 5G Translator Module (TM) is a standalone application that communicates with the ODU-High using the 5G FAPI protocol defined
by the Small Cell Forum and communicates with the ODU Low using the Intel L2-L1 API using the Wireless Subsystem Interface
-Library (WLS) to handle the shared memory and buffer management required by the |br|
-Interfaces. In addition the ORAN 5G FAPI TM requires the
+Library (WLS) to handle the shared memory and buffer management required by the Interfaces. In addition the ORAN 5G FAPI TM requires the
Data Plane Design Kit (DPDK) which is integrated with the WLS Library.
Table 1. Terminology
diff --git a/docs/fapi_5g_tm_rel-notes.rst b/docs/fapi_5g_tm_rel-notes.rst
index 131e92b..dbc5ecd 100644
--- a/docs/fapi_5g_tm_rel-notes.rst
+++ b/docs/fapi_5g_tm_rel-notes.rst
@@ -20,8 +20,21 @@
ORAN 5G FAPI TM Release Notes
=============================
-Version oran_release_bronze_v1.0, May 2020
-------------------------------------------
+Version FAPI TM oran_release_bronze_v1.1, Aug 2020
+------------------------------------------------------
+
+* Increased test coverage. All supported DL, UL and FD standard MIMO cases are validated
+* Support for carrier aggregation
+* Support for API ordering
+* Support for handling Intel proprietary PHY shutdown message in radio mode
+* FAPI TM latency measurement
+* Bug fixes
+* Feedback provided to SCF on parameter gaps identified in SCF 5G FAPI specification dated March 2020
+* This version of the 5G FAPI TM incorporates the changes that were provided to the SCF.
+
+
+Version FAPI TM oran_release_bronze_v1.0, May 2020
+------------------------------------------------------
* First release of the 5G FAPI TM to ORAN in support of the Bronze Release
* This version supports 5G only
* PARAM.config and PARAM.resp are not supported
diff --git a/docs/index.rst b/docs/index.rst
index 64625fb..d13e079 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -12,14 +12,14 @@
.. See the License for the specific language governing permissions and
.. limitations under the License.
-.. ODULOW documentation master
+.. ODULOW documentation main
-.. _odulow documentation master:
+.. _odulow documentation main:
O-RAN O-DU Low
==============
-**User Guide, May 2020**
+**User Guide, August 2020**
.. toctree::
:maxdepth: 2
@@ -27,10 +27,11 @@
overview1.rst
Assumptions_Dependencies.rst
build_prerequisite.rst
+ release-notes.rst
.. _odulow_phy_fhi_library:
-.. fhi library documentation master
+.. fhi library documentation main
FHI Library
===========
@@ -41,7 +42,7 @@
overview.rst
Introduction_fh.rst
- release-notes.rst
+ release-notes-fh.rst
* :ref:`search`
diff --git a/docs/overview.rst b/docs/overview.rst
index 5f117d0..fb1573d 100644
--- a/docs/overview.rst
+++ b/docs/overview.rst
@@ -20,10 +20,9 @@
=====================================
The O-RAN FHI Lib is built on top of DPDK to perform U-plane and C-plane functions according to the
-ORAN Fronthaul |br|
-Interface specification between O-DU and O-RU.
-S-Plane support requires PTP for Linux version 2.0 or later |br|
-The management plane is outside of the scope of this library implementation.
+ORAN Fronthaul Interface specification between O-DU and O-RU.
+The S-Plane support requires PTP for Linux version 2.0 or later.
+The Management plane is outside of the scope of this library implementation.
Project Resources
diff --git a/docs/overview1.rst b/docs/overview1.rst
index abb4c79..debbfcf 100644
--- a/docs/overview1.rst
+++ b/docs/overview1.rst
@@ -23,10 +23,8 @@
:depth: 3
:local:
-The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel |br|
-Architecture. This 5GNR Reference PHY consists of a L1 binary \
-and three kinds of interfaces which are validated on a |br|
-Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \
+The O-DU low project focus on the baseband PHY Reference Design, which uses Xeon® series Processor with Intel Architecture. This 5GNR Reference PHY consists of a L1 binary \
+and three kinds of interfaces which are validated on a Intel® Xeon® SkyLake / CascadeLake platforms and demonstrates the capabilities of the software running different \
5GNR L1 features. It implements the relevant functions described in [3GPP TS 38.211, 212, 213, 214 and 215].
The L1 has three \
diff --git a/docs/release-notes-fh.rst b/docs/release-notes-fh.rst
new file mode 100644
index 0000000..4219b57
--- /dev/null
+++ b/docs/release-notes-fh.rst
@@ -0,0 +1,72 @@
+.. Copyright (c) 2019 Intel
+..
+.. Licensed under the Apache License, Version 2.0 (the "License");
+.. you may not use this file except in compliance with the License.
+.. You may obtain a copy of the License at
+..
+.. http://www.apache.org/licenses/LICENSE-2.0
+..
+.. Unless required by applicable law or agreed to in writing, software
+.. distributed under the License is distributed on an "AS IS" BASIS,
+.. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+.. See the License for the specific language governing permissions and
+.. limitations under the License.
+
+.. |br| raw:: html
+
+ <br />
+
+Front Haul Interface Library Release Notes
+==========================================
+
+Version FH oran_release_bronze_v1.1, Aug 2020
+------------------------------------------------
+
+* Add profile and support for LTE.
+* Add support for the 32x32 massive mimo scenario. Up to 2 cells demo showed with testmac
+* mmWave RRH integration. Address regression from the previous release.
+* Integrate block floating-point compression/decompression.
+* Enhance C-plane for the Category B scenario.
+
+
+Version FH oran_release_bronze_v1.0, May 2020
+------------------------------------------------
+
+* Integration and optimization of block floating point compression and decompression.
+* Category B support
+* Add support for alpha and beta value when calculating SFN based on GPS time.
+* Support End to End integration with commercial UE with xRAN/ORAN RRU for both mmWave and
+ sub-6 scenarios
+
+Version FH oran_release_amber_v1.0, 1 Nov 2019
+-------------------------------------------------
+* Second version released to ORAN in support of Release A
+* Incorporates support for 5G NR sub 6 and mmWave
+* Support for Application fragementation under Transport features was added
+* This release has been designed and implemented to support the following numerologies defined in the 3GPP |br|
+ specification
+ * Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells
+ * Numerology 1 with bandwidth 100MHz with up to 1 cell
+ * Numerology 3 with bandwidth 100MHz with up to 1 cell
+* The feature set of xRAN protocol should be aligned with Radio Unit (O-RU) implementation
+* Inter-operability testing (IOT) is required to confirm correctness of functionality on both sides
+* The following mandatory features of the ORAN FH interface are not yet supported in this release
+* RU Category Support of CAT-B RU (i.e. precoding in RU)
+* Beamforming Beam Index Based and Real Time BF weights
+* Transport Features QoS over FrontHaul
+
+
+Version FH seedcode_v1.0, 25 Jul 2019
+---------------------------------------
+* This first version supports only mmWave per 5G NR and it is not yet
+* optimized
+* It is a first draft prior to the November 2019 Release A
+* The following mandatory features of the ORAN FH interface are not yet
+* supported in this initial release
+* RU Category Support of CAT-B RU (i.e. precoding in RU)
+* Beamforming Beam Index Based and Real Time BF weights
+* Transport Features QoS over FrontHaul and Application Fragmentation
+
+
+
+
diff --git a/docs/release-notes.rst b/docs/release-notes.rst
index 0e3c67d..985fc28 100644
--- a/docs/release-notes.rst
+++ b/docs/release-notes.rst
@@ -16,49 +16,30 @@
<br />
-Front Haul Interface Library Release Notes
+O-DU Low Project Release Notes
==========================================
-Version ORAN-seedcode_v1.3, May 2020
---------------------------------------
+O-DU Low Bronze Release V 1.1, Aug 2020
+-----------------------------------------
+* Enhanced feature set for O-RAN FrontHaul compliant Radio<-> L1 interface, FAPI compliant L1<->L2 interfaces, and a shared memory and buffer management library for efficient L1<->L2 communication
+* Enhanced the code coverage test through more test cases.
+* Bug fixes according to unit test and integration test with third party.
+* Please refer to version FH oran_release_bronze_v1.1, FAPI TM oran_release_bronze_v1.1 and WLS oran_release_bronze_v1.1 release notes for additional details.
-* Third version released to ORAN in support of Release B
-* Add scripts to run refPHY in Docker* containers, Kubernetes* clusters, Multus*, and Data Plane
- Development Kit-Single-Root Input/Output Visualization (DPDK-SRIOV) plugin.
-* Integration and optimization of block floating point compression and decompression.
-* Category B support
-* Add support for alpha and beta value when calculating SFN based on GPS time.
-* Support End to End integration with commercial UE with xRAN/ORAN RRU for both mmWave and
- sub-6 scenarios
+O-DU Low Bronze Release V 1.0, May 2020
+-----------------------------------------
+O-DU Low Bronze release include:
+* ORAN WG8/WG4 Software Specification compliant DU Low implementation including O-RAN FrontHaul compliant Radio<-> L1 interface, FAPI compliant L1<->L2 interfaces, and a shared memory and buffer management library for efficient L1<->L2 communication
+* Ability to link in a high-performance L1 stack application with advanced 5GNR features including 3GPP TS 38.211, 212, 213, 214 and 215, running on Intel Xeon processor based O-DU hardware, and packaged with a comprehensive functional and performance evaluation framework
+* Please refer version FH oran_release_bronze_v1.0, FAPI TM oran_release_bronze_v1.0 and WLS oran_release_bronze_v1.0 release notes for Detail features
-Version ORAN-seedcode_v1.2, 1 Nov 2019
---------------------------------------
-* Second version released to ORAN in support of Release A
-* Incorporates support for 5G NR sub 6 and mmWave
-* Support for Application fragementation under Transport features was added
-* This release has been designed and implemented to support the following numerologies defined in the 3GPP |br|
- specification
-* Numerology 0 with bandwidth 5/10/20 MHz with up to 12 cells
-* Numerology 1 with bandwidth 100MHz with up to 1 cell
-* Numerology 3 with bandwidth 100MHz with up to 1 cell
-* The feature set of xRAN protocol should be aligned with Radio Unit (O-RU) implementation
-* Inter-operability testing (IOT) is required to confirm correctness of functionality on both sides
-* The following mandatory features of the ORAN FH interface are not yet supported in this release
-* RU Category Support of CAT-B RU (i.e. precoding in RU)
-* Beamforming Beam Index Based and Real Time BF weights
-* Transport Features QoS over FrontHaul
+O-DU Low Amber Release V 1.0, 1 Nov 2019
+------------------------------------------
+O-DU Low Amber release include:
+* ORAN WG4 Software Specification compliant O-FH lib implementation
+* Please refer version FH oran_release_amber_v1.0 release notes for Detail features
-Version ORAN-seedcode_v1.1, 25 Jul 2019
----------------------------------------
-* This first version supports only mmWave per 5G NR and it is not yet
-* optimized
-* It is a first draft prior to the November 2019 Release A
-* The following mandatory features of the ORAN FH interface are not yet
-* supported in this initial release
-* RU Category Support of CAT-B RU (i.e. precoding in RU)
-* Beamforming Beam Index Based and Real Time BF weights
-* Transport Features QoS over FrontHaul and Application Fragmentation
diff --git a/docs/run_l1.rst b/docs/run_l1.rst
index 2f1d6d6..49157ef 100644
--- a/docs/run_l1.rst
+++ b/docs/run_l1.rst
@@ -30,19 +30,23 @@
Download L1 and testmac through https://github.com/intel/FlexRAN
+CheckList Before Running the code
+---------------------------------
+Before running the L1 and Testmac code make sure that you have built the wls_lib, FHI_lib and 5G_FAPI_TM using the instructions provided earlier in this
+document and in the order specified in this documentation.
Run L1 with testmac
--------------------
-Three console windows are needed, one for L1 app, one for FAPI TM, one for testmac. They need to run in the following order L1-> FAPI TM-> testmac. |br|
-In each console window, the environment needs to be set using a shell script of example::
+Three console windows are needed, one for L1 app, one for FAPI TM, one for testmac. They need to run in the following order L1-> FAPI TM-> testmac.
+In each console window, the environment needs to be set using a shell script under folder phy/ example::
- #source ./setupenv.sh
+ #source ./setupenv.sh
* Run L1 under folder FlexRAN/l1/bin/nr5g/gnb/l1 in timer mode using::
#l1.sh -e
-**Note** that the markups dpdkBasebandFecMode and dpdkBasebandDevice needs to be adjusted in the relevant phycfg.xml under folder |br|
+**Note** that the markups dpdkBasebandFecMode and dpdkBasebandDevice needs to be adjusted in the relevant phycfg.xml under folder
FlexRAN/l1/bin/nr5g/gnb/l1 before starting L1. |br|
dpdkBasebandFecMode = 0 for LDPC Encoder/Decoder in software. |br|
dpdkBasebandFecMode = 1 for LDPC Encoder/Decoder in FPGA. (Not supported in the Bronze Release for the Open Source Community) |br|
@@ -70,13 +74,13 @@
testnum is always a 4 digit number. First digit represents the number of carriers to run.
For example, to run Test Case 5 for Uplink Rx mu=3, 100Mhz for 1 carrier, the command would be:
run 1 3 100 1005
-All the pre-defined test cases for the Bronze Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test |br|
+All the pre-defined test cases for the Bronze Release are defined in the Test Cases section in https://github.com/intel/FlexRAN and also in the Test
Cases section of this document.
-If user wants to run more slots (than specified in test config file) or change the mode or change the TTI interval of the test, then the command phystart can be used as follows:
+If the user wants to run more slots (than specified in test config file) or change the mode or change the TTI interval of the test, then the command phystart can be used as follows:
- **phystart mode interval num_tti**
-- **mode** is 0 (Radio) or 1 (Timer)
+- **mode** is 4 (ORAN compatible Radio) or 1 (Timer)
- **interval** is the TTI duration scaled as per Numerology (only used in timer mode).
diff --git a/docs/wls-lib-installation-guide.rst b/docs/wls-lib-installation-guide.rst
index 1cb6c56..c1f98fd 100644
--- a/docs/wls-lib-installation-guide.rst
+++ b/docs/wls-lib-installation-guide.rst
@@ -22,7 +22,7 @@
The wls library uses DPDK as the basis for the shared memory operations and requires that DPDK
be installed in the system since in the makefile it uses the RTE_SDK environment variable when
building the library. |br|
-The current release was tested using DPDK version 18.08 but it doesn't preclude the
+The current release was tested using DPDK version 19.11 but it doesn't preclude the
use of newer releases. |br|
Also the library uses the Intel Compiler that is defined as part of the ODULOW documentation.
diff --git a/docs/wls-lib-release-notes.rst b/docs/wls-lib-release-notes.rst
index 22dbc13..8064a85 100644
--- a/docs/wls-lib-release-notes.rst
+++ b/docs/wls-lib-release-notes.rst
@@ -15,7 +15,12 @@
WLS Library Release Notes
=========================
-Version oran_release_bronze_v1.0, May 2020
-------------------------------------------
+Version WLS oran_release_bronze_v1.1, Aug 2020
+--------------------------------------------------
+* Second release of this library aligned with FlexRAN 20.04
+* No changes to external interfaces,
+
+Version WLS oran_release_bronze_v1.0, May 2020
+--------------------------------------------------
* First release of the wls library to ORAN in support of the Bronze Release
* This version supports both single and dual instances using a single Open function
diff --git a/docs/wls-lib.rst b/docs/wls-lib.rst
index 12c303c..9bf023c 100644
--- a/docs/wls-lib.rst
+++ b/docs/wls-lib.rst
@@ -19,9 +19,9 @@
Wls Lib Overview
================
-The Wls_lib is a Wireless Service library that supports shared memory and buffer management used by applications |br|
-implementing a gNb or eNb. |br|
-This library uses DPDK, libhugetlbfs and pthreads to provide memcpy less data exchange between an L2 application, |br|
+The Wls_lib is a Wireless Service library that supports shared memory and buffer management used by applications
+implementing a gNb or eNb.
+This library uses DPDK, libhugetlbfs and pthreads to provide memcpy less data exchange between an L2 application,
API Translator Module and a L1 application by sharing the same memory zone from the DPDK perspective.
Project Resources
@@ -73,4 +73,6 @@
* **WLS_NumBlocks()** returns number of current available blocks provided by master for a new transfer of data from the slave.
-The **_1()** functions are only needed when using the WLS_Open_Dual().
\ No newline at end of file
+The **_1()** functions are only needed when using the WLS_Open_Dual().
+
+The source code and documentation will be updated in the next release to use inclusive engineering terms.
\ No newline at end of file
diff --git a/docs/xRAN-Library-Design_fh.rst b/docs/xRAN-Library-Design_fh.rst
index 07e2694..2e57169 100644
--- a/docs/xRAN-Library-Design_fh.rst
+++ b/docs/xRAN-Library-Design_fh.rst
@@ -27,127 +27,186 @@
functionality is encapsulated. The complete list of all \*.c and \*.h
files as well as Makefile for xRAN (aka FHI Lib Bronze Release) release is:
-├──fhi_lib
+├── app
-│ ├── lib
+│ ├── dpdk.sh
-│ │ ├── api
+│ ├── gen_test.m
-│ │ │ ├── xran_compression.h
+│ ├── Makefile
-│ │ │ ├── xran_compression.hpp
+│ ├── src
-│ │ │ ├── xran_cp_api.h
+│ │ ├── common.c
-│ │ │ ├── xran_fh_o_du.h
+│ │ ├── common.h
-│ │ │ ├── xran_mlog_lnx.h
+│ │ ├── config.c
-│ │ │ ├── xran_pkt_cp.h
+│ │ ├── config.h
-│ │ │ ├── xran_pkt.h
+│ │ ├── debug.h
-│ │ │ ├── xran_pkt_up.h
+│ │ ├── sample-app.c
-│ │ │ ├── xran_sync_api.h
+│ │ └── xran_mlog_task_id.h
-│ │ │ ├── xran_timer.h
+│ └── usecase
-│ │ │ ├── xran_transport.h
+│ ├── cat_b
-│ │ │ └── xran_up_api.h
+│ ├── lte_a
-│ │ ├── ethernet
+│ ├── lte_b
-│ │ │ ├── ethdi.c
+│ ├── mu0_10mhz
-│ │ │ ├── ethdi.h
+│ ├── mu0_20mhz
-│ │ │ ├── ethernet.c
+│ ├── mu0_5mhz
-│ │ │ └── ethernet.h
+│ ├── mu1_100mhz
-│ │ ├── Makefile
+│ └── mu3_100mhz
-│ │ └── src
+├── banner.txt
-│ │ │ ├── xran_app_frag.c
+├── build.sh
-│ │ │ ├── xran_app_frag.h
+├── lib
-│ │ │ ├── xran_common.c
+│ ├── api
-│ │ │ ├── xran_common.h
+│ │ ├── xran_compression.h
-│ │ │ ├── xran_compression.cpp
+│ │ ├── xran_compression.hpp
-│ │ │ ├── xran_cp_api.c
+│ │ ├── xran_cp_api.h
-│ │ │ ├── xran_frame_struct.c
+│ │ ├── xran_fh_o_du.h
-│ │ │ ├── xran_frame_struct.h
+│ │ ├── xran_mlog_lnx.h
-│ │ │ ├── xran_lib_mlog_tasks_id.h
+│ │ ├── xran_pkt_cp.h
-│ │ │ ├── xran_main.c
+│ │ ├── xran_pkt.h
-│ │ │ ├── xran_printf.h
+│ │ ├── xran_pkt_up.h
-│ │ │ ├── xran_sync_api.c
+│ │ ├── xran_sync_api.h
-│ │ │ ├── xran_timer.c
+│ │ ├── xran_timer.h
-│ │ │ ├── xran_transport.c
+│ │ ├── xran_transport.h
-│ │ │ ├── xran_ul_tables.c
+│ │ └── xran_up_api.h
-│ │ │ └── xran_up_api.c
+│ ├── ethernet
-│ ├── readme.txt
+│ │ ├── ethdi.c
-│ ├── Licenses.txt
+│ │ ├── ethdi.h
-│ ├── build.sh
+│ │ ├── ethernet.c
-│ └── test
+│ │ └── ethernet.h
-│ │ ├── common
+│ ├── Makefile
-│ │ │ ├── common.cpp
+│ └── src
-│ │ │ ├── common.hpp
+│ ├── xran_app_frag.c
-│ │ │ ├── common_typedef_xran.h
+│ ├── xran_app_frag.h
-│ │ ├── xranlib_unit_test_main.cc
+│ ├── xran_bfp_cplane16.cpp
-│ │ └── xran_lib_wrap.hpp
+│ ├── xran_bfp_cplane32.cpp
-│ │ ├── master.py
+│ ├── xran_bfp_cplane64.cpp
-│ │ ├── readme.txt
+│ ├── xran_bfp_cplane8.cpp
-│ │ └── test_xran
+│ ├── xran_bfp_ref.cpp
-│ │ │ ├── chain_tests.cc
+│ ├── xran_bfp_utils.hpp
-│ │ │ ├── compander_functional.cc
+│ ├── xran_common.c
-│ │ │ ├── conf.json
+│ ├── xran_common.h
-│ │ │ ├── c_plane_tests.cc
+│ ├── xran_compression.cpp
-│ │ │ ├── init_sys_functional.cc
+│ ├── xran_cp_api.c
-│ │ │ ├── Makefile
+│ ├── xran_frame_struct.c
-│ │ │ ├── prach_functional.cc
+│ ├── xran_frame_struct.h
-│ │ │ ├── prach_performance.cc
+│ ├── xran_lib_mlog_tasks_id.h
-│ │ │ ├── unittests.cc
+│ ├── xran_main.c
-│ │ │ ├── u_plane_functional.cc
+│ ├── xran_printf.h
+
+│ ├── xran_sync_api.c
+
+│ ├── xran_timer.c
+
+│ ├── xran_transport.c
+
+│ ├── xran_ul_tables.c
+
+│ └── xran_up_api.c
+
+├── Licenses.txt
+
+├── readme.md
+
+└── test
+
+ ├── common
+
+ │ ├── common.cpp
+
+ │ ├── common.hpp
+
+ │ ├── common_typedef_xran.h
+
+ │ ├── json.hpp
+
+ │ ├── MIT_License.txt
+
+ │ ├── xranlib_unit_test_main.cc
+
+ │ └── xran_lib_wrap.hpp
+
+ ├── master.py
+
+ ├── readme.txt
+
+ └── test_xran
+
+ ├── chain_tests.cc
+
+ ├── compander_functional.cc
+
+ ├── conf.json
+
+ ├── c_plane_tests.cc
+
+ ├── init_sys_functional.cc
+
+ ├── Makefile
+
+ ├── prach_functional.cc
+
+ ├── prach_performance.cc
+
+ ├── unittests.cc
+
+ └── u_plane_functional.cc
+
General Introduction
--------------------
@@ -164,15 +223,13 @@
This library depends on DPDK primitives to perform Ethernet networking
in userspace, including initialization and control of Ethernet ports.
Ethernet ports are expected to be SRIOV virtual functions (VF) but also
-can be physical functions (PF) as well
+can be physical functions (PF) as well.
This library is expected to be included in the project via
xran_fh_o_du.h, statically compiled and linked with the L1 application
as well as DPDK libraries. The xRAN packet processing-specific
functionality is encapsulated into this library and not exposed to the
-rest of the 5G NR pipeline. An abstract interface similar to the mmWave
-front haul interface is defined in xran_fh_o_du.h to be available for
-usage.
+rest of the 5G NR pipeline.
This way, xRAN specific changes are decoupled from the 5G NR L1
pipeline. As a result, the design and implementation of the 5G L1
@@ -263,12 +320,13 @@
required. The current version of the library does not support multiple
sessions without a restart of the full L1 application.
-
+Configuration
~~~~~~~~~~~~~
-The xRAN library configuration is provided in the set of structures,
-such as struct xran_fh_init and struct xran_fh_config. The sample
-application gives an example of a test configuration used for mmWave.
+The xRAN library configuration is provided in the set of structures, such as struct xran_fh_init and struct xran_fh_config.
+The sample application gives an example of a test configuration used for LTE and 5GNR mmWave and Sub 6. Sample application
+folder /app/usecase/ contains set of examples for different Radio Access technology (LTE|5G NR), different category (A|B)
+and list of numerologies (0,1,3) and list of bandwidths (5,10,20,100Mhz).
Some configuration options are not used in the Bronze Release and are reserved
for future use.
@@ -315,13 +373,13 @@
- Init DPDK timers and DPDK rings for internal packet processing
-- Instantiate ORAH FH thread doing
+- Instantiate ORAN FH thread doing
-- Timing processing (xran_timing_source_thread())
+ - Timing processing (xran_timing_source_thread())
-- ETH PMD (process_dpdk_io())
+ - ETH PMD (process_dpdk_io())
-- IO XRAN-PHY exchange (ring_processing_func())
+ - IO XRAN-PHY exchange (ring_processing_func())
**xran_open()** performs additional configuration as per run scenario:
@@ -343,8 +401,7 @@
~~~~~~~~~~~~~
Exchange of IQ samples, as well as C-plane specific information, is
-performed using a set of buffers allocated by xRAN |br|
-library from DPDK
+performed using a set of buffers allocated by xRAN library from DPDK
memory and shared with the l1 application. Buffers are allocated as a
standard mbuf structure and DPDK pools are used to manage the allocation
and free resources. Shared buffers are allocated at the init stage and
@@ -362,118 +419,65 @@
xran_prb_map and similar to the data plane. The same mbuf memory is used
to allocate memory map of PRBs for each TTI.
-/\* Beamforming weights for single stream for each PRBs given number of
-Antenna elements \*/
-
+/\* Beamforming waights for single stream for each PRBs given number of Antenna elements \*/
struct xran_cp_bf_weight{
-int16_t nAntElmTRx; /* num TRX for this allocation \*/
+ int16_t nAntElmTRx; /\*< num TRX for this allocation \*/
+ int8_t* p_ext_start; /\*< pointer to start of buffer for full C-plane packet \*/
+ int8_t* p_ext_section; /\*< pointer to form extType \*/
+ int16_t ext_section_sz; /\*< extType section size \*/
-int8_t\* p_ext_section; /* pointer to form extType \*/
-
-int16_t ext_section_sz; /* extType section size \*/
-
-};
-
-struct xran_cp_bf_attribute{
-
-int16_t weight[4];
-
-};
-
-struct xran_cp_bf_precoding{
-
-int16_t weight[4];
-
-};
-
-/\* section descriptor for given number of PRBs used on U-plane packet
-creation \*/
-
+/\* section descriptor for given number of PRBs used on U-plane packet creation \*/
struct xran_section_desc {
-uint16_t section_id; /* section id used for this element \*/
+ uint16_t section_id; /\*< section id used for this element \*/
-int16_t iq_buffer_offset; /* Offset in bytes for the content of IQs
-with in main symb buffer \*/
+ int16_t iq_buffer_offset; /\*< Offset in bytes for the content of IQs with in main symb buffer \*/
+ int16_t iq_buffer_len; /\*< Length in bytes for the content of IQs with in main symb buffer \*/
-int16_t iq_buffer_len; /* Length in bytes for the content of IQs with
-in main symb buffer \*/
-
-uint8_t \*pData; /* optional pointer to data buffer \*/
-
-void \*pCtrl; /* optional poitner to mbuf \*/
-
+ uint8_t \*pData; /\*< optional pointer to data buffer \*/
+ void \*pCtrl; /\*< optional poitner to mbuf \*/
+
};
-/* PRB element structure \*/
-
struct xran_prb_elm {
+ int16_t nRBStart; /\*< start RB of RB allocation \*/
+ int16_t nRBSize; /\*< number of RBs used \*/
+ int16_t nStartSymb; /\*< start symbol ID \*/
+ int16_t numSymb; /\\*< number of symbols \*/
+ int16_t nBeamIndex; /\*< beam index for given PRB \*/
+ int16_t bf_weight_update; /\* need to update beam weights or not \*/
+ int16_t compMethod; /\*< compression index for given PRB \*/
+ int16_t iqWidth; /\*< compression bit width for given PRB \*/
+ int16_t BeamFormingType; /\*< index based, weights based or attribute based beam forming\*/
-int16_t nRBStart; /* start RB of RB allocation \*/
+ struct xran_section_desc * p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT]; /\*< section desctiptors to U-plane data given RBs \*/
+ struct xran_cp_bf_weight bf_weight; /\*< beam forming information relevant for given RBs \*/
-int16_t nRBSize; /* number of RBs used \*/
-
-int16_t nStartSymb; /* start symbol ID \*/
-
-int16_t numSymb; /* number of symbols \*/
-
-int16_t nBeamIndex; /* beam index for given PRB \*/
-
-int16_t bf_weight_update; /* need to update beam weights or not \*/
-
-int16_t compMethod; /* compression index for given PRB \*/
-
-int16_t iqWidth; /* compression bit width for given PRB \*/
-
-int16_t BeamFormingType; /* index based, weights based or
-attribute-based beam forming*/
-
-struct xran_section_desc \* p_sec_desc[XRAN_NUM_OF_SYMBOL_PER_SLOT];
-/* section desctiptors to U-plane data given RBs \*/
-
-struct xran_cp_bf_weight bf_weight; /* beam forming information
-relevant for given RBs \*/
-
-union {
-
-struct xran_cp_bf_attribute bf_attribute;
-
-struct xran_cp_bf_precoding bf_precoding;
-
-};
-
-};
-
-/* PRB map structure \*/
+ union {
+ struct xran_cp_bf_attribute bf_attribute;
+ struct xran_cp_bf_precoding bf_precoding;
+
+ };
+
+/\* PRB map structure \*/
struct xran_prb_map {
-
-uint8_t dir; /* DL or UL direction \*/
-
-uint8_t xran_port; /* xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/
-
-uint16_t band_id; /* xran band id \*/
-
-uint16_t cc_id; /* componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)]
-\*/
-
-uint16_t ru_port_id; /* RU device antenna portid [0 -
-(XRAN_MAX_ANTENNA_NR-1)*/
-
-uint16_t tti_id; /* xRAN slot id [0 - (max tti-1)] \*/
-
-uint8_t start_sym_id; /* start symbol Id [0-13] \*/
-
-uint32_t nPrbElm; /* total number of PRB elements for given map [0-
-(XRAN_MAX_PRBS-1)] \*/
-
-struct xran_prb_elm prbMap[XRAN_MAX_PRBS];
-
+ uint8_t dir; /\*< DL or UL direction \*/
+ uint8_t xran_port; /\*< xran id of given RU [0-(XRAN_PORTS_NUM-1)] \*/
+ uint16_t band_id; /\*< xran band id \*/
+ uint16_t cc_id; /\*< componnent carrier id [0 - (XRAN_MAX_SECTOR_NR-1)] \*/
+ uint16_t ru_port_id; /\*< RU device antenna port id [0 - (XRAN_MAX_ANTENNA_NR-1) \*/
+ uint16_t tti_id; /\*< xRAN slot id [0 - (max tti-1)] \*/
+ uint8_t start_sym_id; /\*< start symbol Id [0-13] \*/
+ uint32_t nPrbElm; /\*< total number of PRB elements for given map [0- (XRAN_MAX_PRBS-1)] \*/
+ struct xran_prb_elm prbMap[XRAN_MAX_PRBS];
+
};
+
For the Bronze release C-plane sections are expected to be provided by L1
-pipeline. If 100% of RBs allocated at all times single element of RB map
+pipeline. If 100% of RBs always allocated single element of RB map
is expected to be allocated across all symbols. Dynamic RB allocation is
performed base on C-plane configuration.
@@ -1351,6 +1355,34 @@
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_DL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEX_STANDARD
+- frameId = [0..99]
+- subframeId = [0..9]
+- slotID = [0..9]
+- startSymbolid = 0
+- numberOfsections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_1
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+- reserved = 0
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 66
+- reMask = 0xfff
+- numSymbol = 14
+- ef = 0
+- beamId = 0
+
+
**C-Plane Message – uplink symbol data for uplink slot**
- Single CP message with the single section of section type 1
@@ -1362,6 +1394,34 @@
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_UL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEX_STANDARD
+- frameId = [0..99]
+- subframeId = [0..9]
+- slotID = [0..9]
+- startSymbolid = 3
+- numberOfsections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_1
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+- reserved = 0
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 66
+- reMask = 0xfff
+- numSymbol = 11
+- ef = 0
+- beamId = 0
+
+
**C-Plane Message – PRACH**
- Single CP message with the single section of section type 3 including
@@ -1390,14 +1450,46 @@
- Compression and beamforming are not used
+Common Header Fields::
+
+- dataDirection = XRAN_DIR_UL
+- payloadVersion = XRAN_PAYLOAD_VER
+- filterIndex = XRAN_FILTERINDEPRACH_ABC
+- frameId = [0,99]
+- subframeId = [0,3]
+- slotID = 3 or 7
+- startSymbolid = 7
+- numberOfSections = 1
+- sectionType = XRAN_CP_SECTIONTYPE_3
+- timeOffset = 2026
+- frameStructure.FFTSize = XRAN_FFTSIZE_1024
+- frameStructure.u = XRAN_SCS_120KHZ
+- cpLength = 0
+- udCompHdr.idIqWidth = 0
+- udCompHdr.udCompMeth = XRAN_COMPMETHOD_NONE
+
+Section Fields::
+
+- sectionId = [0..4095]
+- rb = XRAN_RBIND_EVERY
+- symInc = XRAN_SYMBOLNUMBER_NOTINC
+- startPrbc = 0
+- numPrbc = 12
+- reMask = 0xfff
+- numSymbol = 6
+- ef = 0
+- beamId = 0
+- frequencyOffset = -792
+- reserved
+
+
Functions to Store/Retrieve Section Information
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
There are several functions to store/retrieve section information of
C-Plane messages. Since U-plane messages must be generated by the
information in the sections of a C-Plane message, it is required to
-store and retrieve section |br|
-information.
+store and retrieve section information.
**APIs and Data Structure**
'''''''''''''''''''''''''''
@@ -1470,7 +1562,7 @@
maximum number of context is defined by two and it can be adjusted if
needed.
-8. Since the context index is not managed by the library and APIs are
+Note. Since the context index is not managed by the library and APIs are
expecting it from the caller as a parameter, the caller shall
consider a proper method to manage it to avoid corruption. The
current reference implementation uses a slot and subframe index to
@@ -1543,7 +1635,7 @@
builds eCPRI header filling structure fields by taking the IQ sample
size and populating a particular packet length and sequence number.
-Currently, the supported IQ bit width is 16.
+With compression, supported IQ bit widths are 8,9,10,12,14.
Implementation of a U-plane set of functions is defined in xran_up_api.c
and is used to prepare U-plane packet content according to the given
@@ -1641,7 +1733,7 @@
the system timer which in turn is synchronized to PTP (GPS)
Only single-shot timers are used to schedule processing based on
-particular events such as symbol time. The packet |br|
+events such as symbol time. The packet |br|
processing function
calls rte_timer_manage() in the loop, and the resulting execution of
timer function happens right |br|