commit a9733dbcc47e93a3b2843056f1d587196296c324
author Ron Shacham <rshacham@research.att.com> Mon Sep 14 12:05:31 2020 -0400
committer Ron Shacham <rshacham@research.att.com> Tue Sep 15 12:23:47 2020 -0400
tree 6c0d3112bd91fdea2e28bc887bb8b2a6599e792e
parent 3ebf932d23dcbec9ed19f4a51f9d00a0a54f5124

Separated E2Sim lib from E2SM-specific code

Issue-ID: SIM-18

Signed-off-by: Ron Shacham <rshacham@research.att.com>
Change-Id: Ic4b1edc9011130a5f92a169012cbaeab56f9bc1d
Signed-off-by: Ron Shacham <rshacham@research.att.com>

e2sim/src/ASN1c/RICcontrolFailure.c

diff --git a/e2sim/src/ASN1c/RICcontrolFailure.c b/e2sim/src/ASN1c/RICcontrolFailure.c
new file mode 100644
index 0000000..76b0bdc
--- /dev/null
+++ b/e2sim/src/ASN1c/RICcontrolFailure.c
@@ -0,0 +1,50 @@
+/*
+ * Generated by asn1c-0.9.29 (http://lionet.info/asn1c)
+ * From ASN.1 module "E2AP-PDU-Contents"
+ * 	found in "/root/e2ap-v01.00.00.asn"
+ * 	`asn1c -fcompound-names -fincludes-quoted -fno-include-deps -findirect-choice -gen-PER -D .`
+ */
+
+#include "RICcontrolFailure.h"
+
+asn_TYPE_member_t asn_MBR_RICcontrolFailure_1[] = {
+	{ ATF_NOFLAGS, 0, offsetof(struct RICcontrolFailure, protocolIEs),
+		(ASN_TAG_CLASS_CONTEXT | (0 << 2)),
+		-1,	/* IMPLICIT tag at current level */
+		&asn_DEF_ProtocolIE_Container_1527P9,
+		0,
+		{ 0, 0, 0 },
+		0, 0, /* No default value */
+		"protocolIEs"
+		},
+};
+static const ber_tlv_tag_t asn_DEF_RICcontrolFailure_tags_1[] = {
+	(ASN_TAG_CLASS_UNIVERSAL | (16 << 2))
+};
+static const asn_TYPE_tag2member_t asn_MAP_RICcontrolFailure_tag2el_1[] = {
+    { (ASN_TAG_CLASS_CONTEXT | (0 << 2)), 0, 0, 0 } /* protocolIEs */
+};
+asn_SEQUENCE_specifics_t asn_SPC_RICcontrolFailure_specs_1 = {
+	sizeof(struct RICcontrolFailure),
+	offsetof(struct RICcontrolFailure, _asn_ctx),
+	asn_MAP_RICcontrolFailure_tag2el_1,
+	1,	/* Count of tags in the map */
+	0, 0, 0,	/* Optional elements (not needed) */
+	1,	/* First extension addition */
+};
+asn_TYPE_descriptor_t asn_DEF_RICcontrolFailure = {
+	"RICcontrolFailure",
+	"RICcontrolFailure",
+	&asn_OP_SEQUENCE,
+	asn_DEF_RICcontrolFailure_tags_1,
+	sizeof(asn_DEF_RICcontrolFailure_tags_1)
+		/sizeof(asn_DEF_RICcontrolFailure_tags_1[0]), /* 1 */
+	asn_DEF_RICcontrolFailure_tags_1,	/* Same as above */
+	sizeof(asn_DEF_RICcontrolFailure_tags_1)
+		/sizeof(asn_DEF_RICcontrolFailure_tags_1[0]), /* 1 */
+	{ 0, 0, SEQUENCE_constraint },
+	asn_MBR_RICcontrolFailure_1,
+	1,	/* Elements count */
+	&asn_SPC_RICcontrolFailure_specs_1	/* Additional specs */
+};
+