| /* |
| * tps23880-regdefs.h |
| * |
| * TPS23880 Register Definitions |
| * |
| * Author: Cradlepoint Technology, Inc. <source@cradlepoint.com> |
| * Kyle Swenson <kswenson@cradlepoint.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 |
| * as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| */ |
| #ifndef __TPS23880_REGDEFS_H__ |
| #define __TPS23880_REGDEFS_H__ |
| |
| |
| /* NOTE: PORTS ARE ZERO INDEXED */ |
| #define RP(_reg, _p) ((_reg) + (_p)) |
| |
| #define LOWER_CHANNEL(_ch) ((_ch) & 0x02) |
| #define TWO_BIT_CHANNEL_SHIFT(_ch) ((_ch)<<1) |
| #define TWO_BIT_CHANNEL_MASK(_ch) (0x03 << TWO_BIT_CHANNEL_SHIFT((_ch))) |
| #define ONE_BIT_CHANNEL_SHIFT(_ch) ((_ch)) |
| |
| #define HN(_p) (1 << ((_p) + 4)) /*High nibble */ |
| #define LN(_p) (1 << (_p)) /* Low nibble */ |
| #define DBLREG(_reg, _p) ((((_p) & 0x03) >> 1) + (_reg)) /*Registers where ports 0 & 1 are on one register, and the 2 & 3 are on the next */ |
| #define DBLVAL(_v, _p) ((_v) << (((_p) & 0x01) << 2)) /*pop the value to the upper nibble if the port is odd */ |
| #define TWO_BIT_WORD_OFFSET(_v, _pid) ((_v) << ((_pid) << 1)) |
| #define TWO_BIT_WORD_MASK(_pid) TWO_BIT_WORD_OFFSET(0x03, (_pid)) |
| |
| |
| #define SUPPLY_PCUT_FAULT_MASK 0x0C |
| #define TPS23880_INTSTAT 0x00 |
| #define TPS23880_INTMASK 0x01 |
| #define TPS23880_INT_SUPPLY 0x80 |
| #define TPS23880_INT_STRTF 0x40 |
| #define TPS23880_INT_IFAULT 0x20 |
| #define TPS23880_INT_CLASC 0x10 |
| #define TPS23880_INT_DETC 0x08 |
| #define TPS23880_INT_DISF 0x04 |
| #define TPS23880_INT_PGC 0x02 |
| #define TPS23880_INT_PEC 0x01 |
| |
| |
| #define POWER_GOOD_MASK 0xF0 |
| #define TPS23880_PWREVN 0x02 |
| #define TPS23880_PWREVN_COR 0x03 |
| #define TPS23880_PWREVN_PGC(_p) HN(_p) |
| #define TPS23880_PWREVN_PEC(_p) LN(_p) |
| |
| #define TPS23880_PWREVN_PGC4 (1 << 7) |
| #define TPS23880_PWREVN_PGC3 (1 << 6) |
| #define TPS23880_PWREVN_PGC2 (1 << 5) |
| #define TPS23880_PWREVN_PGC1 (1 << 4) |
| #define TPS23880_PWREVN_PEC4 (1 << 3) |
| #define TPS23880_PWREVN_PEC3 (1 << 2) |
| #define TPS23880_PWREVN_PEC2 (1 << 1) |
| #define TPS23880_PWREVN_PEC1 (1 << 0) |
| |
| #define TPS23880_DETEVN 0x04 |
| #define TPS23880_DETEVN_COR 0x05 |
| #define CHANNEL_DETECT_MASK(x) (LN((x))) |
| #define CHANNEL_CLASS_MASK(x) (HN((x))) |
| #define TPS23880_DETEVN_CLSC(_p) HN(_p) |
| #define TPS23880_DETEVN_DETC(_p) LN(_p) |
| |
| #define TPS23880_DETEVN_CLSC4 (1 << 7) |
| #define TPS23880_DETEVN_CLSC3 (1 << 6) |
| #define TPS23880_DETEVN_CLSC2 (1 << 5) |
| #define TPS23880_DETEVN_CLSC1 (1 << 4) |
| #define TPS23880_DETEVN_DETC4 (1 << 3) |
| #define TPS23880_DETEVN_DETC3 (1 << 2) |
| #define TPS23880_DETEVN_DETC2 (1 << 1) |
| #define TPS23880_DETEVN_DETC1 (1 << 0) |
| |
| |
| #define TPS23880_FLTEVN 0x06 |
| #define TPS23880_FLTEVN_COR 0x07 |
| #define TPS23880_FLTEVN_DISF(_p) HN(_p) |
| #define TPS23880_FLTEVN_PCUT(_p) LN(_p) |
| |
| #define TPS23880_FLTEVN_DISF4 (1 << 7) |
| #define TPS23880_FLTEVN_DISF3 (1 << 6) |
| #define TPS23880_FLTEVN_DISF2 (1 << 5) |
| #define TPS23880_FLTEVN_DISF1 (1 << 4) |
| #define TPS23880_FLTEVN_PCUT4 (1 << 3) |
| #define TPS23880_FLTEVN_PCUT3 (1 << 2) |
| #define TPS23880_FLTEVN_PCUT2 (1 << 1) |
| #define TPS23880_FLTEVN_PCUT1 (1 << 0) |
| |
| |
| #define TPS23880_TSEVN 0x08 |
| #define TPS23880_TSEVN_COR 0x09 |
| #define TPS23880_TSEVN_ILIM(_p) HN(_p) |
| #define TPS23880_TSEVN_STRT(_p) LN(_p) |
| |
| #define TPS23880_TSEVN_ILIM4 (1 << 7) |
| #define TPS23880_TSEVN_ILIM3 (1 << 6) |
| #define TPS23880_TSEVN_ILIM2 (1 << 5) |
| #define TPS23880_TSEVN_ILIM1 (1 << 4) |
| #define TPS23880_TSEVN_STRT4 (1 << 3) |
| #define TPS23880_TSEVN_STRT3 (1 << 2) |
| #define TPS23880_TSEVN_STRT2 (1 << 1) |
| #define TPS23880_TSEVN_STRT1 (1 << 0) |
| |
| #define TPS23880_SUPEVN 0x0A |
| #define TPS23880_SUPEVN_COR 0x0B |
| #define TPS23880_SUPEVN_TSD (1 << 7) |
| #define TPS23880_SUPEVN_VDUV (1 << 6) |
| #define TPS23880_SUPEVN_VDWRN (1 << 5) |
| #define TPS23880_SUPEVN_VPUV (1 << 4) |
| #define TPS23880_SUPEVN_PCUT34 (1 << 3) |
| #define TPS23880_SUPEVN_PCUT12 (1 << 2) |
| #define TPS23880_SUPEVN_OSSE (1 << 1) |
| #define TPS23880_SUPEVN_RAMFLT (1 << 0) |
| |
| #define TPS23880_PWRON_FLTEVN 0x24 |
| #define TPS23880_PWRON_FLTEVN_COR 0x25 |
| |
| #define TPS23880_DISCOVERY 0x0C |
| #define TPS23880_CLASS_MASK 0xF0 |
| #define TPS23880_CLASS_SHIFT 4 |
| #define TPS23880_DETECT_MASK 0x0F |
| #define TPS23880_DETECT_SHIFT 0 |
| |
| #define TPS23880_DISCOVERY_CLASS_RESULT(det) (((det) & (0x0F << TPS23880_CLASS_SHIFT))>>TPS23880_CLASS_SHIFT) |
| #define TPS23880_DISCOVERY_DETECT_RESULT(det) (((det) & (0x0F << TPS23880_DETECT_SHIFT))>>TPS23880_DETECT_SHIFT) |
| |
| #define TPS23880_AUTOCLASS_CONNECTION_CHECK 0x1C |
| #define TPS23880_CONNECTION_SHIFT(_ch) (LOWER_CHANNEL(_ch)) |
| #define TPS23880_CONNECTION_MASK(_ch) (0x03 << (TPS23880_CONNECTION_SHIFT((_ch)))) |
| #define TPS23880_CONNECTION_RESULT(value, _ch) (((value) & (TPS23880_CONNECTION_MASK(_ch))) >> TPS23880_CONNECTION_SHIFT(_ch)) |
| #define TPS23880_AUTOCLASS_MASK(_ch) (HN(_ch)) |
| #define TPS23880_AUTOCLASS_SHIFT(_ch) ((_ch)+4) |
| #define TPS23880_AUTOCLASS_RESULT(value, _ch) (((value) & (TPS23880_AUTOCLASS_MASK(_ch))) >> TPS23880_AUTOCLASS_SHIFT(_ch)) |
| |
| #define TPS23880_STATPWR 0x10 |
| #define TPS23880_STATPWR_PG(_p) HN(_p) |
| #define TPS23880_STATPWR_PE(_p) LN(_p) |
| |
| #define TPS23880_OPMD 0x12 |
| |
| #define TPS23880_DISENA 0x13 |
| #define TPS23880_DISENA_EML_AC(_p) HN(_p) |
| #define TPS23880_DISENA_DC(_p) LN(_p) |
| |
| #define TPS23880_DETENA 0x14 |
| #define TPS23880_DETENA_PB 0x18 |
| #define TPS23880_DETENA_CLS(_p) HN(_p) |
| #define TPS23880_DETENA_DET(_p) LN(_p) |
| |
| #define TPS23880_TCONF 0x16 |
| #define TPS23880_TCONF_TSTART(_v) (((_v) & 0x03) << 4) |
| #define TPS23880_TCONF_TCUT(_v) (((_v) & 0x03) << 2) |
| #define TPS23880_TCONF_TDIS(_v) ((_v) & 0x03) |
| |
| #define TPS23880_GENERAL_MASK 0x17 |
| #define TPS23880_GENERAL_MASK_INTENA (1 << 7) |
| #define TPS23880_GENERAL_MASK_N_BIT_ACC (1 << 5) |
| #define TPS23880_GENERAL_MASK_CLCHE (1 << 3) |
| #define TPS23880_GENERAL_MASK_DECHE (1 << 2) |
| |
| |
| #define TPS23880_PWRPB 0x19 |
| #define TPS23880_PWRPB_OFF(_p) HN(_p) |
| #define TPS23880_PWRPB_ON(_p) LN(_p) |
| |
| #define TPS23880_RSTPB 0x1A |
| #define TPS23880_RSTPB_INTCLR 0x80 |
| #define TPS23880_RSTPB_PINCLR 0x40 |
| #define TPS23880_RSTPB_RSTALL 0x10 |
| #define TPS23880_RSTPB_RSTPORTS 0x0F |
| #define TPS23880_RESET_PORT(_ch) (0x03 << LOWER_CHANNEL((_ch))) |
| |
| #define TPS23880_ID_REG 0x1B |
| #define TPS23880_ID 0x55 |
| |
| #define TPS23880_OPMD_REG 0x12 |
| #define TPS23880_OPMD_SEMI 0xAAAA |
| |
| #define TPS23880_4P_PORT_POWER_ALLOCATION 0x29 |
| #define TPS23880_4P_PORT_POWER_SHIFT(ch) (LOWER_CHANNEL((ch))<<1) |
| #define TPS23880_4P_90W(ch) (0x07 << TPS23880_4P_PORT_POWER_SHIFT((ch))) |
| #define TPS23880_4P_PORT_POWER_ALLOCATION_MASK(ch) (0x0F << TPS23880_4P_PORT_POWER_SHIFT((ch))) |
| #define TPS23880_4P_MODE_SHIFT(ch) ((TPS23880_4P_PORT_POWER_SHIFT((ch))+3)) |
| #define TPS23880_4P_MODE(ch) (1 << (TPS23880_4P_MODE_SHIFT(ch))) |
| |
| |
| #define TPS23880_2P_POLICE(_p) (0x1E +(_p)) |
| #define TPS23880_4P_POLICE(_p) (0x2A +(_p)) |
| |
| #define TPS23880_VOLTAGE_BASE 0x32 |
| #define TPS23880_VOLTAGE_MASK 0x3FFF |
| #define TPS23880_CURRENT_BASE 0x30 |
| #define TPS23880_CURRENT_MASK 0x3FFF |
| |
| #define TPS23880_NUM_CHANNELS 4 |
| |
| #define TPS23880_INTERRUPT_SOURCES (TPS23880_INT_STRTF | TPS23880_INT_IFAULT | TPS23880_INT_CLASC | TPS23880_INT_DISF | TPS23880_INT_PGC | TPS23880_INT_PGC) |
| #endif |
| |