pse/ltc4266/ltc4266-regdefs.h

/*
 * ltc4266-regdefs.h
 *
 * LTC4266 Register Definitions
 *
 * Author: Cradlepoint Technology, Inc.  <source@cradlepoint.com>
 *         Kyle Swenson <kswenson@cradlepoint.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */
#ifndef __LTC4266_REGDEFS_H__
#define __LTC4266_REGDEFS_H__


/* NOTE: PORTS ARE ZERO INDEXED */
#define RP(_reg, _p) ((_reg) + (_p))
#define HN(_p) (1 << ((_p) + 4)) /*High nibble */
#define LN(_p) (1 << (_p)) /* Low nibble */
#define DBLREG(_reg, _p) ((((_p) & 0x03) >> 1) + (_reg)) /*Registers where ports 0 & 1 are on one register, and the 2 & 3 are on the next */
#define DBLVAL(_v, _p)	((_v) << (((_p) & 0x01) << 2)) /*pop the value to the upper nibble if the port is odd */
#define TWO_BIT_WORD_OFFSET(_v, _pid) ((_v) << ((_pid) << 1))
#define TWO_BIT_WORD_MASK(_pid) TWO_BIT_WORD_OFFSET(0x03, (_pid))

#define LTC4266_INTSTAT 0x00
#define LTC4266_INTMASK 0x01
/*The following are valid for both INTSTAT and INTMASK */
	#define LTC4266_INT_SUPPLY 0x80
	#define LTC4266_INT_TSTART 0x40
	#define LTC4266_INT_TCUT 0x20
	#define LTC4266_INT_CLASS 0x10
	#define LTC4266_INT_DET 0x08
	#define LTC4266_INT_DIS 0x04
	#define LTC4266_INT_PWRGD 0x02
	#define LTC4266_INT_PWRENA 0x01

#define LTC4266_PWREVN 0x02
#define LTC4266_PWREVN_COR 0x03
	#define LTC4266_PWREVN_PWRGD(_p) HN(_p)
	#define LTC4266_PWREVN_PWRENA(_p) LN(_p)

#define LTC4266_DETEVN 0x04
#define LTC4266_DETEVN_COR 0x05
	#define LTC4266_DETEVN_CLASS(_p)  HN(_p)
	#define LTC4266_DETEVN_DET(_p)  LN(_p)


#define LTC4266_FLTEVN 0x06
#define LTC4266_FLTEVN_COR 0x07
	#define LTC4266_FLTEVN_DIS(_p) HN(_p)
	#define LTC4266_FLTEVN_TCUT(_p) LN(_p)


#define LTC4266_TSEVN 0x08
#define LTC4266_TSEVN_COR 0x09
	#define LTC4266_TSEVN_TLIM(_p) HN(_P)
	#define LTC4266_TSEVN_TSTART(_p) LN(_P)


#define LTC4266_SUPEVN 0x0A
#define LTC4266_SUPEVN_COR 0x0B
	#define LTC4266_SUPEVN_OVERTEMP 0x80
	#define LTC4266_SUPEVN_FETBAD 0x40
	#define LTC4266_SUPEVN_UVLO3 0x20
	#define LTC4266_SUPEVN_UVLO48 0x10


#define LTC4266_STAT_REG(_p) RP(0x0C, (_p))
	#define LTC4266_PORT_CLASS(_stat) (((_stat) & 0x70) >> 4)
	#define LTC4266_PORT_DETECT(_stat) ((_stat) & 0x07)

#define LTC4266_STATPWR 0x10
	#define LTC4266_STATPWR_PG(_p) HN(_p)
	#define LTC4266_STATPWR_PE(_p) LN(_p)

#define LTC4266_STATPIN 0x11
	#define LTC4266_STATPIN_AD3 0x20
	#define LTC4266_STATPIN_AD2 0x10
	#define LTC4266_STATPIN_AD1 0x08
	#define LTC4266_STATPIN_AD0 0x04
	#define LTC4266_STATPIN_MID 0x02
	#define LTC4266_STATPIN_AUTO 0x01

#define LTC4266_OPMD_REG 0x12
#define LTC4266_OPMD_VAL(_val, _p) (((_val) & (0x03 << (_p))) >> (_p))
#define LTC4266_OPMD_SEMI 0xAA

#define LTC4266_DISENA 0x13
	#define LTC4266_DISENA_EML_AC(_p) HN(_p)
	#define LTC4266_DISENA_DC(_p)  LN(_p)

#define LTC4266_DETENA 0x14
	#define LTC4266_DETENA_CLS(_p) HN(_p)

	#define LTC4266_DETENA_DET(_p) LN(_p)

#define LTC4266_MIDSPAN 0x15
	#define LTC4266_MIDSPAN_MIDSP(_p) LN(_p)



#define LTC4266_TCONF 0x16
#define LTC4266_TCONF_TSTART(_v) (((_v) & 0x03) << 4)
#define LTC4266_TCONF_TCUT(_v)  (((_v) & 0x03) << 2)
#define LTC4266_TCONF_TDIS(_v) ((_v) & 0x03)

#define LTC4266_MCONF 0x17
#define LTC4266_MCONF_INTENA 0x80
#define LTC4266_MCONF_DETCHG 0x40
#define LTC4266_MCONF_FASTIV 0x10
#define LTC4266_MCONF_MSDMSK(_p) LN(_p)

#define LTC4266_DETPB 0x18
#define LTC4266_DETPB_CLS(_p) HN(_p)
#define LTC4266_DETPB_DET(_p) LN(_p)

#define LTC4266_PWRPB 0x19
#define LTC4266_PWRPB_OFF(_p) HN(_p)
#define LTC4266_PWRPB_ON(_p) LN(_p)

#define LTC4266_RSTPB 0x1A
#define LTC4266_RSTPB_INTCLR 0x80
#define LTC4266_RSTPB_PINCLR 0x40
#define LTC4266_RSTPB_RSTALL 0x10
#define LTC4266_RSTPB_RSTPORTS 0x0F

#define LTC4266_RSTPB_RST(_p) LN(_p)

#define LTC4266_ID 0x1B
#define LTC4266_ID_SIG  0x64

#define LTC4266_TLIM(_p) DBLREG(0x1E, _p)
	#define LTC4266_TLIM_EN(_p)  ((0x01) << (((_p) & 0x02) << 1))

#define LTC4266_ICUT_REG(_p)	DBLREG(0x2A, (_p))
#define LTC4266_ICUT_VAL(_v, _p)  DBLVAL(((_v) & 0x07), (_p))


/* Port _p current; 1 LSB = 61.035 uA if R_sense = 0.5 Ohm, else 122.07 uA */
#define LTC4266_IPLSB_REG(_p) (0x30 | ((_p) << 2))
#define LTC4266_IPMSB_REG(_p) (LTC4266_IPLSB_REG(_p) + 1)
/* Port_p voltage, 1LSB = 5.9667mV if R_sense = 0.5 Ohm, else 11.9334mV */
#define LTC4266_VPLSB_REG(_p) (LTC4266_IPLSB_REG(_p) + 2)
#define LTC4266_VPMSB_REG(_p) (LTC4266_IPLSB_REG(_p) + 3)

#define LTC4266_DBLPWR 0x40
#define LTC4266_DBLPWR_DBL(_p) HN(_p)

#define LTC4266_HPEN 0x44
#define LTC4266_HPEN_HPEN(_p)  LN(_p)

/* ZERO Indexed ports */
#define LTC4266_HPMD_REG(_p) (0x46 + (5*(_p)))
	#define LTC4266_HPMD_PONGEN 0x01
	#define LTC4266_HPMD_LEGEN 0x02

#define LTC4266_ICUT_REG_HP(_p) (LTC4266_HPMD_REG(_p) + 1)
	#define LTC4266_CUT_RDIS 0x80
	#define LTC4266_CUT_CUTRNG 0x40
	#define LTC4266_CUT_CUT_MSK 0x3F

#define LTC4266_LIM_REG(_p) (LTC4266_HPMD_REG(_p) + 2)
#define LTC4266_LIM_LIM 0x01
#define LTC4266_LIM_RLIM 0x80

#define LTC4266_HPSTAT_REG(_p) (LTC4266_HPMD_REG(_p) + 3)
#define LTC4266_HPSTAT_FETBAD 0x02
#define LTC4266_HPSTAT_PONGPD 0x01

#endif