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gerrit.nordix.org / codeaurora / cp-linux / 7d38e033b98fd00da3a0b3a506c27c772f7167bf / . / drivers / clk / imx / clk-imx51-imx53.c
blob: c6770348d2abc764b19208f3b2228c0d23d10e42 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame]1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9#include <linux/mm.h>
10#include <linux/delay.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/clkdev.h>
14#include <linux/clk-provider.h>
15#include <linux/err.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <soc/imx/revision.h>
20#include <dt-bindings/clock/imx5-clock.h>
21
22#include "clk.h"
23
24#define MX51_DPLL1_BASE 0x83f80000
25#define MX51_DPLL2_BASE 0x83f84000
26#define MX51_DPLL3_BASE 0x83f88000
27
28#define MX53_DPLL1_BASE 0x63f80000
29#define MX53_DPLL2_BASE 0x63f84000
30#define MX53_DPLL3_BASE 0x63f88000
31#define MX53_DPLL4_BASE 0x63f8c000
32
33#define MXC_CCM_CCR (ccm_base + 0x00)
34#define MXC_CCM_CCDR (ccm_base + 0x04)
35#define MXC_CCM_CSR (ccm_base + 0x08)
36#define MXC_CCM_CCSR (ccm_base + 0x0c)
37#define MXC_CCM_CACRR (ccm_base + 0x10)
38#define MXC_CCM_CBCDR (ccm_base + 0x14)
39#define MXC_CCM_CBCMR (ccm_base + 0x18)
40#define MXC_CCM_CSCMR1 (ccm_base + 0x1c)
41#define MXC_CCM_CSCMR2 (ccm_base + 0x20)
42#define MXC_CCM_CSCDR1 (ccm_base + 0x24)
43#define MXC_CCM_CS1CDR (ccm_base + 0x28)
44#define MXC_CCM_CS2CDR (ccm_base + 0x2c)
45#define MXC_CCM_CDCDR (ccm_base + 0x30)
46#define MXC_CCM_CHSCDR (ccm_base + 0x34)
47#define MXC_CCM_CSCDR2 (ccm_base + 0x38)
48#define MXC_CCM_CSCDR3 (ccm_base + 0x3c)
49#define MXC_CCM_CSCDR4 (ccm_base + 0x40)
50#define MXC_CCM_CWDR (ccm_base + 0x44)
51#define MXC_CCM_CDHIPR (ccm_base + 0x48)
52#define MXC_CCM_CDCR (ccm_base + 0x4c)
53#define MXC_CCM_CTOR (ccm_base + 0x50)
54#define MXC_CCM_CLPCR (ccm_base + 0x54)
55#define MXC_CCM_CISR (ccm_base + 0x58)
56#define MXC_CCM_CIMR (ccm_base + 0x5c)
57#define MXC_CCM_CCOSR (ccm_base + 0x60)
58#define MXC_CCM_CGPR (ccm_base + 0x64)
59#define MXC_CCM_CCGR0 (ccm_base + 0x68)
60#define MXC_CCM_CCGR1 (ccm_base + 0x6c)
61#define MXC_CCM_CCGR2 (ccm_base + 0x70)
62#define MXC_CCM_CCGR3 (ccm_base + 0x74)
63#define MXC_CCM_CCGR4 (ccm_base + 0x78)
64#define MXC_CCM_CCGR5 (ccm_base + 0x7c)
65#define MXC_CCM_CCGR6 (ccm_base + 0x80)
66#define MXC_CCM_CCGR7 (ccm_base + 0x84)
67
68/* Low-power Audio Playback Mode clock */
69static const char *lp_apm_sel[] = { "osc", };
70
71/* This is used multiple times */
72static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
73static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
74static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
75static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
76static const char *per_root_sel[] = { "per_podf", "ipg", };
77static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
78static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
79static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
80static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
81static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
82static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
83static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
84static const char *emi_slow_sel[] = { "main_bus", "ahb", };
85static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
86static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
87static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
88static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
89static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
90static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
91static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
92static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
93static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
94static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
95static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
96static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
97static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
98static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
99static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
100static const char *mx53_cko1_sel[] = {
101 "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
102 "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
103 "di_pred", "dummy", "dummy", "ahb",
104 "ipg", "per_root", "ckil", "dummy",};
105static const char *mx53_cko2_sel[] = {
106 "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
107 "dummy", "esdhc_a_podf",
108 "usboh3_podf", "dummy"/* wrck_clk_root */,
109 "ecspi_podf", "dummy"/* pll1_ref_clk */,
110 "esdhc_b_podf", "dummy"/* ddr_clk_root */,
111 "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
112 "vpu_sel", "ipu_sel",
113 "osc", "ckih1",
114 "dummy", "esdhc_c_sel",
115 "ssi1_root_podf", "ssi2_root_podf",
116 "dummy", "dummy",
117 "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
118 "dummy"/* tve_out */, "usb_phy_sel",
119 "tve_sel", "lp_apm",
120 "uart_root", "dummy"/* spdif0_clk_root */,
121 "dummy", "dummy", };
122static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
123static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
124static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
125static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
126static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
127static const char *step_sels[] = { "lp_apm", };
128static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
129
130static struct clk *clk[IMX5_CLK_END];
131static struct clk_onecell_data clk_data;
132
133static struct clk ** const uart_clks[] __initconst = {
134 &clk[IMX5_CLK_UART1_IPG_GATE],
135 &clk[IMX5_CLK_UART1_PER_GATE],
136 &clk[IMX5_CLK_UART2_IPG_GATE],
137 &clk[IMX5_CLK_UART2_PER_GATE],
138 &clk[IMX5_CLK_UART3_IPG_GATE],
139 &clk[IMX5_CLK_UART3_PER_GATE],
140 &clk[IMX5_CLK_UART4_IPG_GATE],
141 &clk[IMX5_CLK_UART4_PER_GATE],
142 &clk[IMX5_CLK_UART5_IPG_GATE],
143 &clk[IMX5_CLK_UART5_PER_GATE],
144 NULL
145};
146
147static void __init mx5_clocks_common_init(void __iomem *ccm_base)
148{
149 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
150 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
151 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
152 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0);
153 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0);
154
155 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
156 periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
157 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
158 main_bus_sel, ARRAY_SIZE(main_bus_sel));
159 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
160 per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
161 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
162 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
163 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
164 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
165 per_root_sel, ARRAY_SIZE(per_root_sel));
166 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
167 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28);
168 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24);
169 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26);
170 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0);
171 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2);
172 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4);
173 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0);
174 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
175 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
176 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
177 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
178 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
179 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
180 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
181
182 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
183 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
184 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
185 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
186 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
187 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
188 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
189 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
190 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
191 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
192
193 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
194 emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
195 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
196 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
197 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
198 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
199 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
200 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
201 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
202 standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
203 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
204 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
205 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
206 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
207 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
208 usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
209 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
210 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
211 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
212 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
213 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
214 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
215 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
216 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
217 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
218 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
219 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
220 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
221 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
222 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
223 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
224 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
225 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
226 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
227 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
228 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
229 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
230 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
231 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
232 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
233 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
234 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
235 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
236 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
237 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
238 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
239 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
240 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
241 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
242 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
243 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
244 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14);
245 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16);
246 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
247 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
248 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
249 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
250 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
251 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
252 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
253 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
254 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
255 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
256 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
257 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
258 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
259 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
260 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
261 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
262 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
263 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
264
265 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
266 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
267 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
268 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
269 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
270 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
271 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
272 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
273 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
274 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
275 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
276 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
277 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
278 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
279 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
280 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
281 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
282 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
283 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
284 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
285 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
286 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
287 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
288 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
289 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
290 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
291 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
292 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
293 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
294 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
295 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
296 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
297 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
298 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
299 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
300 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
301 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
302
303 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
304 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
305
306 /* Set SDHC parents to be PLL2 */
307 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
308 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
309
310 /* move usb phy clk to 24MHz */
311 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
312
313 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]);
314 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */
315 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]);
316 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */
317 clk_prepare_enable(clk[IMX5_CLK_SPBA]);
318 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */
319 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */
320 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]);
321 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]);
322 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]);
323 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]);
324 clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
325 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
326 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
327
328 imx_register_uart_clocks(uart_clks);
329}
330
331static void __init mx50_clocks_init(struct device_node *np)
332{
333 void __iomem *ccm_base;
334 void __iomem *pll_base;
335 unsigned long r;
336
337 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
338 WARN_ON(!pll_base);
339 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
340
341 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
342 WARN_ON(!pll_base);
343 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
344
345 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
346 WARN_ON(!pll_base);
347 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
348
349 ccm_base = of_iomap(np, 0);
350 WARN_ON(!ccm_base);
351
352 mx5_clocks_common_init(ccm_base);
353
354 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
355 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
356 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
357 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
358 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
359 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
360 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
361 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
362 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
363
364 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
365 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
366 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
367 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
368
369 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
370 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
371 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
372 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
373
374 imx_check_clocks(clk, ARRAY_SIZE(clk));
375
376 clk_data.clks = clk;
377 clk_data.clk_num = ARRAY_SIZE(clk);
378 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
379
380 /* set SDHC root clock to 200MHZ*/
381 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
382 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
383
384 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
385 imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
386 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
387
388 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
389 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
390}
391CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
392
393static void __init mx51_clocks_init(struct device_node *np)
394{
395 void __iomem *ccm_base;
396 void __iomem *pll_base;
397 u32 val;
398
399 pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
400 WARN_ON(!pll_base);
401 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
402
403 pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
404 WARN_ON(!pll_base);
405 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
406
407 pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
408 WARN_ON(!pll_base);
409 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
410
411 ccm_base = of_iomap(np, 0);
412 WARN_ON(!ccm_base);
413
414 mx5_clocks_common_init(ccm_base);
415
416 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
417 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
418 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
419 mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel));
420 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
421 mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel));
422 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
423 mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
424 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
425 mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
426 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
427 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
428 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
429 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
430 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
431 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
432 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
433 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
434 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6);
435 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
436 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
437 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
438 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
439 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
440 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
441 spdif_sel, ARRAY_SIZE(spdif_sel));
442 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
443 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
444 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
445 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
446 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
447
448 imx_check_clocks(clk, ARRAY_SIZE(clk));
449
450 clk_data.clks = clk;
451 clk_data.clk_num = ARRAY_SIZE(clk);
452 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
453
454 /* set the usboh3 parent to pll2_sw */
455 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
456
457 /* set SDHC root clock to 166.25MHZ*/
458 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
459 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
460
461 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
462 imx_print_silicon_rev("i.MX51", mx51_revision());
463 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
464
465 /*
466 * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
467 * longer supported. Set to one for better power saving.
468 *
469 * The effect of not setting these bits is that MIPI clocks can't be
470 * enabled without the IPU clock being enabled aswell.
471 */
472 val = readl(MXC_CCM_CCDR);
473 val |= 1 << 18;
474 writel(val, MXC_CCM_CCDR);
475
476 val = readl(MXC_CCM_CLPCR);
477 val |= 1 << 23;
478 writel(val, MXC_CCM_CLPCR);
479}
480CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
481
482static void __init mx53_clocks_init(struct device_node *np)
483{
484 void __iomem *ccm_base;
485 void __iomem *pll_base;
486 unsigned long r;
487
488 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
489 WARN_ON(!pll_base);
490 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base);
491
492 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
493 WARN_ON(!pll_base);
494 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base);
495
496 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
497 WARN_ON(!pll_base);
498 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base);
499
500 pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
501 WARN_ON(!pll_base);
502 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base);
503
504 ccm_base = of_iomap(np, 0);
505 WARN_ON(!ccm_base);
506
507 mx5_clocks_common_init(ccm_base);
508
509 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
510 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
511 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
512 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
513 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
514 mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
515 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
516 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
517 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
518 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
519 mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
520 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
521 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
522 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
523 mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel));
524 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
525 mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel));
526 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
527 mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
528 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
529 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
530 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
531 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
532 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
533 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
534 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
535 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
536 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
537 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
538 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
539 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
540 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
541 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
542 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
543 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
544 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
545
546 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
547 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
548 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
549 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
550
551 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
552 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
553 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
554 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
555 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
556 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
557 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
558 clk[IMX5_CLK_CPU_PODF],
559 clk[IMX5_CLK_CPU_PODF_SEL],
560 clk[IMX5_CLK_PLL1_SW],
561 clk[IMX5_CLK_STEP_SEL]);
562
563 imx_check_clocks(clk, ARRAY_SIZE(clk));
564
565 clk_data.clks = clk;
566 clk_data.clk_num = ARRAY_SIZE(clk);
567 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
568
569 /* set SDHC root clock to 200MHZ*/
570 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
571 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
572
573 /* move can bus clk to 24MHz */
574 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
575
576 /* make sure step clock is running from 24MHz */
577 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
578
579 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
580 imx_print_silicon_rev("i.MX53", mx53_revision());
581 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
582
583 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
584 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
585}
586CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);