Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | Binding for TO CDCE925 programmable I2C clock synthesizers. |
| 2 | |
| 3 | Reference |
| 4 | This binding uses the common clock binding[1]. |
| 5 | |
| 6 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 7 | [2] http://www.ti.com/product/cdce925 |
| 8 | |
| 9 | The driver provides clock sources for each output Y1 through Y5. |
| 10 | |
| 11 | Required properties: |
| 12 | - compatible: Shall be "ti,cdce925" |
| 13 | - reg: I2C device address. |
| 14 | - clocks: Points to a fixed parent clock that provides the input frequency. |
| 15 | - #clock-cells: From common clock bindings: Shall be 1. |
| 16 | |
| 17 | Optional properties: |
| 18 | - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a |
| 19 | board, or to compensate for external influences. |
| 20 | |
| 21 | For both PLL1 and PLL2 an optional child node can be used to specify spread |
| 22 | spectrum clocking parameters for a board. |
| 23 | - spread-spectrum: SSC mode as defined in the data sheet. |
| 24 | - spread-spectrum-center: Use "centered" mode instead of "max" mode. When |
| 25 | present, the clock runs at the requested frequency on average. Otherwise |
| 26 | the requested frequency is the maximum value of the SCC range. |
| 27 | |
| 28 | |
| 29 | Example: |
| 30 | |
| 31 | clockgen: cdce925pw@64 { |
| 32 | compatible = "cdce925"; |
| 33 | reg = <0x64>; |
| 34 | clocks = <&xtal_27Mhz>; |
| 35 | #clock-cells = <1>; |
| 36 | xtal-load-pf = <5>; |
| 37 | /* PLL options to get SSC 1% centered */ |
| 38 | PLL2 { |
| 39 | spread-spectrum = <4>; |
| 40 | spread-spectrum-center; |
| 41 | }; |
| 42 | }; |