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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / arch / arm / boot / dts / imx6qdl-phytec-pfla02.dtsi
blob: d6d98d4263847e1ec6429d1a88fc2de40ebd36d0 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/*
2 * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 model = "Phytec phyFLEX-i.MX6 Quad";
16 compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
17
18 memory {
19 reg = <0x10000000 0x80000000>;
20 };
21
22 regulators {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 reg_usb_otg_vbus: regulator@0 {
28 compatible = "regulator-fixed";
29 reg = <0>;
30 regulator-name = "usb_otg_vbus";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 gpio = <&gpio4 15 0>;
34 enable-active-high;
35 };
36
37 reg_usb_h1_vbus: regulator@1 {
38 compatible = "regulator-fixed";
39 reg = <1>;
40 regulator-name = "usb_h1_vbus";
41 regulator-min-microvolt = <5000000>;
42 regulator-max-microvolt = <5000000>;
43 gpio = <&gpio1 0 0>;
44 enable-active-high;
45 };
46 };
47
48 gpio_leds: leds {
49 compatible = "gpio-leds";
50
51 green {
52 label = "phyflex:green";
53 gpios = <&gpio1 30 0>;
54 };
55
56 red {
57 label = "phyflex:red";
58 gpios = <&gpio2 31 0>;
59 };
60 };
61};
62
63&audmux {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_audmux>;
66 status = "disabled";
67};
68
69&can1 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_flexcan1>;
72 status = "disabled";
73};
74
75&ecspi3 {
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_ecspi3>;
78 status = "okay";
79 fsl,spi-num-chipselects = <1>;
80 cs-gpios = <&gpio4 24 0>;
81
82 flash@0 {
83 compatible = "m25p80", "jedec,spi-nor";
84 spi-max-frequency = <20000000>;
85 reg = <0>;
86 };
87};
88
89&fec {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet>;
92 phy-mode = "rgmii";
93 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
94 phy-supply = <&vdd_eth_io_reg>;
95 status = "disabled";
96};
97
98&gpmi {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_gpmi_nand>;
101 nand-on-flash-bbt;
102 status = "okay";
103};
104
105&i2c1 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&pinctrl_i2c1>;
108 status = "okay";
109
110 eeprom@50 {
111 compatible = "atmel,24c32";
112 reg = <0x50>;
113 };
114
115 pmic@58 {
116 compatible = "dlg,da9063";
117 reg = <0x58>;
118 interrupt-parent = <&gpio2>;
119 interrupts = <9 0x8>; /* active-low GPIO2_9 */
120
121 regulators {
122 vddcore_reg: bcore1 {
123 regulator-min-microvolt = <730000>;
124 regulator-max-microvolt = <1380000>;
125 regulator-always-on;
126 };
127
128 vddsoc_reg: bcore2 {
129 regulator-min-microvolt = <730000>;
130 regulator-max-microvolt = <1380000>;
131 regulator-always-on;
132 };
133
134 vdd_ddr3_reg: bpro {
135 regulator-min-microvolt = <1500000>;
136 regulator-max-microvolt = <1500000>;
137 regulator-always-on;
138 };
139
140 vdd_3v3_reg: bperi {
141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <3300000>;
143 regulator-always-on;
144 };
145
146 vdd_buckmem_reg: bmem {
147 regulator-min-microvolt = <3300000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-always-on;
150 };
151
152 vdd_eth_reg: bio {
153 regulator-min-microvolt = <1200000>;
154 regulator-max-microvolt = <1200000>;
155 regulator-always-on;
156 };
157
158 vdd_eth_io_reg: ldo4 {
159 regulator-min-microvolt = <2500000>;
160 regulator-max-microvolt = <2500000>;
161 regulator-always-on;
162 };
163
164 vdd_mx6_snvs_reg: ldo5 {
165 regulator-min-microvolt = <3000000>;
166 regulator-max-microvolt = <3000000>;
167 regulator-always-on;
168 };
169
170 vdd_3v3_pmic_io_reg: ldo6 {
171 regulator-min-microvolt = <3300000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-always-on;
174 };
175
176 vdd_sd0_reg: ldo9 {
177 regulator-min-microvolt = <3300000>;
178 regulator-max-microvolt = <3300000>;
179 };
180
181 vdd_sd1_reg: ldo10 {
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 };
185
186 vdd_mx6_high_reg: ldo11 {
187 regulator-min-microvolt = <3000000>;
188 regulator-max-microvolt = <3000000>;
189 regulator-always-on;
190 };
191 };
192 };
193};
194
195&i2c2 {
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_i2c2>;
198 clock-frequency = <100000>;
199};
200
201&i2c3 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_i2c3>;
204 clock-frequency = <100000>;
205};
206
207&iomuxc {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_hog>;
210
211 imx6q-phytec-pfla02 {
212 pinctrl_hog: hoggrp {
213 fsl,pins = <
214 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
215 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
216 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */
217 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
218 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
219 >;
220 };
221
222 pinctrl_ecspi3: ecspi3grp {
223 fsl,pins = <
224 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
225 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
226 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
227 >;
228 };
229
230 pinctrl_enet: enetgrp {
231 fsl,pins = <
232 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
233 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
234 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
235 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
236 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
237 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
238 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
239 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
240 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
241 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
242 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
243 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
244 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
245 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
246 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
247 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
248 >;
249 };
250
251 pinctrl_flexcan1: flexcan1grp {
252 fsl,pins = <
253 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
254 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
255 >;
256 };
257
258 pinctrl_gpmi_nand: gpminandgrp {
259 fsl,pins = <
260 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
261 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
262 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
263 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
264 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
265 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
266 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
267 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
268 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
269 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
270 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
271 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
272 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
273 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
274 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
275 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
276 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
277 >;
278 };
279
280 pinctrl_i2c1: i2c1grp {
281 fsl,pins = <
282 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
283 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
284 >;
285 };
286
287 pinctrl_i2c2: i2c2grp {
288 fsl,pins = <
289 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
290 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
291 >;
292 };
293
294 pinctrl_i2c3: i2c3grp {
295 fsl,pins = <
296 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
297 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
298 >;
299 };
300
301 pinctrl_pcie: pciegrp {
302 fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>;
303 };
304
305 pinctrl_uart3: uart3grp {
306 fsl,pins = <
307 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
308 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
309 MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
310 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
311 >;
312 };
313
314 pinctrl_uart4: uart4grp {
315 fsl,pins = <
316 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
317 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
318 >;
319 };
320
321 pinctrl_usbh1: usbh1grp {
322 fsl,pins = <
323 MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x80000000
324 >;
325 };
326
327 pinctrl_usbotg: usbotggrp {
328 fsl,pins = <
329 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
330 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
331 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000
332 >;
333 };
334
335 pinctrl_usdhc2: usdhc2grp {
336 fsl,pins = <
337 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
338 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
339 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
340 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
341 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
342 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
343 >;
344 };
345
346 pinctrl_usdhc3: usdhc3grp {
347 fsl,pins = <
348 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
349 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
350 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
351 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
352 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
353 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
354 >;
355 };
356
357 pinctrl_usdhc3_cdwp: usdhc3cdwp {
358 fsl,pins = <
359 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
360 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
361 >;
362 };
363
364 pinctrl_audmux: audmuxgrp {
365 fsl,pins = <
366 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
367 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
368 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
369 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
370 >;
371 };
372 };
373};
374
375&pcie {
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_pcie>;
378 reset-gpio = <&gpio4 17 0>;
379 status = "disabled";
380};
381
382&uart3 {
383 pinctrl-names = "default";
384 pinctrl-0 = <&pinctrl_uart3>;
385 status = "disabled";
386};
387
388&uart4 {
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_uart4>;
391 status = "disabled";
392};
393
394&usbh1 {
395 vbus-supply = <&reg_usb_h1_vbus>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_usbh1>;
398 status = "disabled";
399};
400
401&usbotg {
402 vbus-supply = <&reg_usb_otg_vbus>;
403 pinctrl-names = "default";
404 pinctrl-0 = <&pinctrl_usbotg>;
405 disable-over-current;
406 status = "disabled";
407};
408
409&usdhc2 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&pinctrl_usdhc2>;
412 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
413 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
414 status = "disabled";
415};
416
417&usdhc3 {
418 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_usdhc3
420 &pinctrl_usdhc3_cdwp>;
421 cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
422 wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
423 status = "disabled";
424};