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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / arch / arm / mach-omap2 / dma.c
blob: 1ed4be184a29b16f6f8d97a082fb80d424ca0665 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/*
2 * OMAP2+ DMA driver
3 *
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
11 *
12 * Copyright (C) 2009 Texas Instruments
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
15 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16 * Converted DMA library into platform driver
17 * - G, Manjunath Kondaiah <manjugk@ti.com>
18 *
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License version 2 as
21 * published by the Free Software Foundation.
22 */
23
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/slab.h>
27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/device.h>
30#include <linux/dma-mapping.h>
31#include <linux/of.h>
32#include <linux/omap-dma.h>
33
34#include "soc.h"
35#include "omap_hwmod.h"
36#include "omap_device.h"
37
38static enum omap_reg_offsets dma_common_ch_end;
39
40static const struct omap_dma_reg reg_map[] = {
41 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
42 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
43 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
44 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
45 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
46 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
47 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
48 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
49 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
50 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
51 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
52 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
53 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
54 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
55 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
56 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
57
58 /* Common register offsets */
59 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
60 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
61 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
62 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
63 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
64 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
65 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
66 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
67 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
68 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
69 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
70 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
71 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
72
73 /* Channel specific register offsets */
74 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
75 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
76 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
77 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
78 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
79
80 /* OMAP4 specific registers */
81 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
82 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
83 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
84};
85
86static void __iomem *dma_base;
87static inline void dma_write(u32 val, int reg, int lch)
88{
89 void __iomem *addr = dma_base;
90
91 addr += reg_map[reg].offset;
92 addr += reg_map[reg].stride * lch;
93
94 writel_relaxed(val, addr);
95}
96
97static inline u32 dma_read(int reg, int lch)
98{
99 void __iomem *addr = dma_base;
100
101 addr += reg_map[reg].offset;
102 addr += reg_map[reg].stride * lch;
103
104 return readl_relaxed(addr);
105}
106
107static void omap2_clear_dma(int lch)
108{
109 int i;
110
111 for (i = CSDP; i <= dma_common_ch_end; i += 1)
112 dma_write(0, i, lch);
113}
114
115static void omap2_show_dma_caps(void)
116{
117 u8 revision = dma_read(REVISION, 0) & 0xff;
118 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
119 revision >> 4, revision & 0xf);
120}
121
122static unsigned configure_dma_errata(void)
123{
124 unsigned errata = 0;
125
126 /*
127 * Errata applicable for OMAP2430ES1.0 and all omap2420
128 *
129 * I.
130 * Erratum ID: Not Available
131 * Inter Frame DMA buffering issue DMA will wrongly
132 * buffer elements if packing and bursting is enabled. This might
133 * result in data gets stalled in FIFO at the end of the block.
134 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
135 * guarantee no data will stay in the DMA FIFO in case inter frame
136 * buffering occurs
137 *
138 * II.
139 * Erratum ID: Not Available
140 * DMA may hang when several channels are used in parallel
141 * In the following configuration, DMA channel hanging can occur:
142 * a. Channel i, hardware synchronized, is enabled
143 * b. Another channel (Channel x), software synchronized, is enabled.
144 * c. Channel i is disabled before end of transfer
145 * d. Channel i is reenabled.
146 * e. Steps 1 to 4 are repeated a certain number of times.
147 * f. A third channel (Channel y), software synchronized, is enabled.
148 * Channel x and Channel y may hang immediately after step 'f'.
149 * Workaround:
150 * For any channel used - make sure NextLCH_ID is set to the value j.
151 */
152 if (cpu_is_omap2420() || (cpu_is_omap2430() &&
153 (omap_type() == OMAP2430_REV_ES1_0))) {
154
155 SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
156 SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
157 }
158
159 /*
160 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
161 * after a transaction error.
162 * Workaround: SW should explicitely disable the channel.
163 */
164 if (cpu_class_is_omap2())
165 SET_DMA_ERRATA(DMA_ERRATA_i378);
166
167 /*
168 * Erratum ID: i541: sDMA FIFO draining does not finish
169 * If sDMA channel is disabled on the fly, sDMA enters standby even
170 * through FIFO Drain is still in progress
171 * Workaround: Put sDMA in NoStandby more before a logical channel is
172 * disabled, then put it back to SmartStandby right after the channel
173 * finishes FIFO draining.
174 */
175 if (cpu_is_omap34xx())
176 SET_DMA_ERRATA(DMA_ERRATA_i541);
177
178 /*
179 * Erratum ID: i88 : Special programming model needed to disable DMA
180 * before end of block.
181 * Workaround: software must ensure that the DMA is configured in No
182 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
183 */
184 if (omap_type() == OMAP3430_REV_ES1_0)
185 SET_DMA_ERRATA(DMA_ERRATA_i88);
186
187 /*
188 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
189 * read before the DMA controller finished disabling the channel.
190 */
191 SET_DMA_ERRATA(DMA_ERRATA_3_3);
192
193 /*
194 * Erratum ID: Not Available
195 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
196 * after secure sram context save and restore.
197 * Work around: Hence we need to manually clear those IRQs to avoid
198 * spurious interrupts. This affects only secure devices.
199 */
200 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
201 SET_DMA_ERRATA(DMA_ROMCODE_BUG);
202
203 return errata;
204}
205
206static struct omap_system_dma_plat_info dma_plat_info __initdata = {
207 .reg_map = reg_map,
208 .channel_stride = 0x60,
209 .show_dma_caps = omap2_show_dma_caps,
210 .clear_dma = omap2_clear_dma,
211 .dma_write = dma_write,
212 .dma_read = dma_read,
213};
214
215static struct platform_device_info omap_dma_dev_info = {
216 .name = "omap-dma-engine",
217 .id = -1,
218 .dma_mask = DMA_BIT_MASK(32),
219};
220
221/* One time initializations */
222static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
223{
224 struct platform_device *pdev;
225 struct omap_system_dma_plat_info p;
226 struct omap_dma_dev_attr *d;
227 struct resource *mem;
228 char *name = "omap_dma_system";
229
230 p = dma_plat_info;
231 p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
232 p.errata = configure_dma_errata();
233
234 pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
235 if (IS_ERR(pdev)) {
236 pr_err("%s: Can't build omap_device for %s:%s.\n",
237 __func__, name, oh->name);
238 return PTR_ERR(pdev);
239 }
240
241 omap_dma_dev_info.res = pdev->resource;
242 omap_dma_dev_info.num_res = pdev->num_resources;
243
244 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
245 if (!mem) {
246 dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
247 return -EINVAL;
248 }
249
250 dma_base = ioremap(mem->start, resource_size(mem));
251 if (!dma_base) {
252 dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
253 return -ENOMEM;
254 }
255
256 d = oh->dev_attr;
257
258 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
259 d->dev_caps |= HS_CHANNELS_RESERVED;
260
261 if (platform_get_irq_byname(pdev, "0") < 0)
262 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
263
264 /* Check the capabilities register for descriptor loading feature */
265 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
266 dma_common_ch_end = CCDN;
267 else
268 dma_common_ch_end = CCFN;
269
270 return 0;
271}
272
273static int __init omap2_system_dma_init(void)
274{
275 struct platform_device *pdev;
276 int res;
277
278 res = omap_hwmod_for_each_by_class("dma",
279 omap2_system_dma_init_dev, NULL);
280 if (res)
281 return res;
282
283 if (of_have_populated_dt())
284 return res;
285
286 pdev = platform_device_register_full(&omap_dma_dev_info);
287 if (IS_ERR(pdev))
288 return PTR_ERR(pdev);
289
290 return res;
291}
292omap_arch_initcall(omap2_system_dma_init);