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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / arch / arm64 / include / asm / insn.h
blob: 30e50eb54a6795aa9c504a2d22dfabd8b8db195a [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/*
2 * Copyright (C) 2013 Huawei Ltd.
3 * Author: Jiang Liu <liuj97@gmail.com>
4 *
5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_INSN_H
20#define __ASM_INSN_H
21#include <linux/types.h>
22
23/* A64 instructions are always 32 bits. */
24#define AARCH64_INSN_SIZE 4
25
26#ifndef __ASSEMBLY__
27/*
28 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
29 * Section C3.1 "A64 instruction index by encoding":
30 * AArch64 main encoding table
31 * Bit position
32 * 28 27 26 25 Encoding Group
33 * 0 0 - - Unallocated
34 * 1 0 0 - Data processing, immediate
35 * 1 0 1 - Branch, exception generation and system instructions
36 * - 1 - 0 Loads and stores
37 * - 1 0 1 Data processing - register
38 * 0 1 1 1 Data processing - SIMD and floating point
39 * 1 1 1 1 Data processing - SIMD and floating point
40 * "-" means "don't care"
41 */
42enum aarch64_insn_encoding_class {
43 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
44 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
45 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
46 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
47 AARCH64_INSN_CLS_LDST, /* Loads and stores */
48 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
49 * system instructions */
50};
51
52enum aarch64_insn_hint_op {
53 AARCH64_INSN_HINT_NOP = 0x0 << 5,
54 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
55 AARCH64_INSN_HINT_WFE = 0x2 << 5,
56 AARCH64_INSN_HINT_WFI = 0x3 << 5,
57 AARCH64_INSN_HINT_SEV = 0x4 << 5,
58 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
59};
60
61enum aarch64_insn_imm_type {
62 AARCH64_INSN_IMM_ADR,
63 AARCH64_INSN_IMM_26,
64 AARCH64_INSN_IMM_19,
65 AARCH64_INSN_IMM_16,
66 AARCH64_INSN_IMM_14,
67 AARCH64_INSN_IMM_12,
68 AARCH64_INSN_IMM_9,
69 AARCH64_INSN_IMM_7,
70 AARCH64_INSN_IMM_6,
71 AARCH64_INSN_IMM_S,
72 AARCH64_INSN_IMM_R,
73 AARCH64_INSN_IMM_MAX
74};
75
76enum aarch64_insn_register_type {
77 AARCH64_INSN_REGTYPE_RT,
78 AARCH64_INSN_REGTYPE_RN,
79 AARCH64_INSN_REGTYPE_RT2,
80 AARCH64_INSN_REGTYPE_RM,
81 AARCH64_INSN_REGTYPE_RD,
82 AARCH64_INSN_REGTYPE_RA,
83};
84
85enum aarch64_insn_register {
86 AARCH64_INSN_REG_0 = 0,
87 AARCH64_INSN_REG_1 = 1,
88 AARCH64_INSN_REG_2 = 2,
89 AARCH64_INSN_REG_3 = 3,
90 AARCH64_INSN_REG_4 = 4,
91 AARCH64_INSN_REG_5 = 5,
92 AARCH64_INSN_REG_6 = 6,
93 AARCH64_INSN_REG_7 = 7,
94 AARCH64_INSN_REG_8 = 8,
95 AARCH64_INSN_REG_9 = 9,
96 AARCH64_INSN_REG_10 = 10,
97 AARCH64_INSN_REG_11 = 11,
98 AARCH64_INSN_REG_12 = 12,
99 AARCH64_INSN_REG_13 = 13,
100 AARCH64_INSN_REG_14 = 14,
101 AARCH64_INSN_REG_15 = 15,
102 AARCH64_INSN_REG_16 = 16,
103 AARCH64_INSN_REG_17 = 17,
104 AARCH64_INSN_REG_18 = 18,
105 AARCH64_INSN_REG_19 = 19,
106 AARCH64_INSN_REG_20 = 20,
107 AARCH64_INSN_REG_21 = 21,
108 AARCH64_INSN_REG_22 = 22,
109 AARCH64_INSN_REG_23 = 23,
110 AARCH64_INSN_REG_24 = 24,
111 AARCH64_INSN_REG_25 = 25,
112 AARCH64_INSN_REG_26 = 26,
113 AARCH64_INSN_REG_27 = 27,
114 AARCH64_INSN_REG_28 = 28,
115 AARCH64_INSN_REG_29 = 29,
116 AARCH64_INSN_REG_FP = 29, /* Frame pointer */
117 AARCH64_INSN_REG_30 = 30,
118 AARCH64_INSN_REG_LR = 30, /* Link register */
119 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
120 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
121};
122
123enum aarch64_insn_variant {
124 AARCH64_INSN_VARIANT_32BIT,
125 AARCH64_INSN_VARIANT_64BIT
126};
127
128enum aarch64_insn_condition {
129 AARCH64_INSN_COND_EQ = 0x0, /* == */
130 AARCH64_INSN_COND_NE = 0x1, /* != */
131 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
132 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
133 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
134 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
135 AARCH64_INSN_COND_VS = 0x6, /* overflow */
136 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
137 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
138 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
139 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
140 AARCH64_INSN_COND_LT = 0xb, /* signed < */
141 AARCH64_INSN_COND_GT = 0xc, /* signed > */
142 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
143 AARCH64_INSN_COND_AL = 0xe, /* always */
144};
145
146enum aarch64_insn_branch_type {
147 AARCH64_INSN_BRANCH_NOLINK,
148 AARCH64_INSN_BRANCH_LINK,
149 AARCH64_INSN_BRANCH_RETURN,
150 AARCH64_INSN_BRANCH_COMP_ZERO,
151 AARCH64_INSN_BRANCH_COMP_NONZERO,
152};
153
154enum aarch64_insn_size_type {
155 AARCH64_INSN_SIZE_8,
156 AARCH64_INSN_SIZE_16,
157 AARCH64_INSN_SIZE_32,
158 AARCH64_INSN_SIZE_64,
159};
160
161enum aarch64_insn_ldst_type {
162 AARCH64_INSN_LDST_LOAD_REG_OFFSET,
163 AARCH64_INSN_LDST_STORE_REG_OFFSET,
164 AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
165 AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
166 AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
167 AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
168};
169
170enum aarch64_insn_adsb_type {
171 AARCH64_INSN_ADSB_ADD,
172 AARCH64_INSN_ADSB_SUB,
173 AARCH64_INSN_ADSB_ADD_SETFLAGS,
174 AARCH64_INSN_ADSB_SUB_SETFLAGS
175};
176
177enum aarch64_insn_movewide_type {
178 AARCH64_INSN_MOVEWIDE_ZERO,
179 AARCH64_INSN_MOVEWIDE_KEEP,
180 AARCH64_INSN_MOVEWIDE_INVERSE
181};
182
183enum aarch64_insn_bitfield_type {
184 AARCH64_INSN_BITFIELD_MOVE,
185 AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
186 AARCH64_INSN_BITFIELD_MOVE_SIGNED
187};
188
189enum aarch64_insn_data1_type {
190 AARCH64_INSN_DATA1_REVERSE_16,
191 AARCH64_INSN_DATA1_REVERSE_32,
192 AARCH64_INSN_DATA1_REVERSE_64,
193};
194
195enum aarch64_insn_data2_type {
196 AARCH64_INSN_DATA2_UDIV,
197 AARCH64_INSN_DATA2_SDIV,
198 AARCH64_INSN_DATA2_LSLV,
199 AARCH64_INSN_DATA2_LSRV,
200 AARCH64_INSN_DATA2_ASRV,
201 AARCH64_INSN_DATA2_RORV,
202};
203
204enum aarch64_insn_data3_type {
205 AARCH64_INSN_DATA3_MADD,
206 AARCH64_INSN_DATA3_MSUB,
207};
208
209enum aarch64_insn_logic_type {
210 AARCH64_INSN_LOGIC_AND,
211 AARCH64_INSN_LOGIC_BIC,
212 AARCH64_INSN_LOGIC_ORR,
213 AARCH64_INSN_LOGIC_ORN,
214 AARCH64_INSN_LOGIC_EOR,
215 AARCH64_INSN_LOGIC_EON,
216 AARCH64_INSN_LOGIC_AND_SETFLAGS,
217 AARCH64_INSN_LOGIC_BIC_SETFLAGS
218};
219
220#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
221static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
222{ return (code & (mask)) == (val); } \
223static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
224{ return (val); }
225
226__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
227__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
228__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
229__AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
230__AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
231__AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
232__AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
233__AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
234__AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
235__AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
236__AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
237__AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
238__AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
239__AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
240__AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
241__AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
242__AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
243__AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
244__AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
245__AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
246__AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
247__AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
248__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
249__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
250__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
251__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
252__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
253__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
254__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
255__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
256__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
257__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
258__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
259__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
260__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
261__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
262__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
263__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
264__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
265__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
266__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
267__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
268__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
269__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
270__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
271__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
272__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
273__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
274__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
275__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
276__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
277__AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
278__AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
279__AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
280
281#undef __AARCH64_INSN_FUNCS
282
283bool aarch64_insn_is_nop(u32 insn);
284bool aarch64_insn_is_branch_imm(u32 insn);
285
286int aarch64_insn_read(void *addr, u32 *insnp);
287int aarch64_insn_write(void *addr, u32 insn);
288enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
289u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
290u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
291 u32 insn, u64 imm);
292u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
293 enum aarch64_insn_branch_type type);
294u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
295 enum aarch64_insn_register reg,
296 enum aarch64_insn_variant variant,
297 enum aarch64_insn_branch_type type);
298u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
299 enum aarch64_insn_condition cond);
300u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
301u32 aarch64_insn_gen_nop(void);
302u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
303 enum aarch64_insn_branch_type type);
304u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
305 enum aarch64_insn_register base,
306 enum aarch64_insn_register offset,
307 enum aarch64_insn_size_type size,
308 enum aarch64_insn_ldst_type type);
309u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
310 enum aarch64_insn_register reg2,
311 enum aarch64_insn_register base,
312 int offset,
313 enum aarch64_insn_variant variant,
314 enum aarch64_insn_ldst_type type);
315u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
316 enum aarch64_insn_register src,
317 int imm, enum aarch64_insn_variant variant,
318 enum aarch64_insn_adsb_type type);
319u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
320 enum aarch64_insn_register src,
321 int immr, int imms,
322 enum aarch64_insn_variant variant,
323 enum aarch64_insn_bitfield_type type);
324u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
325 int imm, int shift,
326 enum aarch64_insn_variant variant,
327 enum aarch64_insn_movewide_type type);
328u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
329 enum aarch64_insn_register src,
330 enum aarch64_insn_register reg,
331 int shift,
332 enum aarch64_insn_variant variant,
333 enum aarch64_insn_adsb_type type);
334u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
335 enum aarch64_insn_register src,
336 enum aarch64_insn_variant variant,
337 enum aarch64_insn_data1_type type);
338u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
339 enum aarch64_insn_register src,
340 enum aarch64_insn_register reg,
341 enum aarch64_insn_variant variant,
342 enum aarch64_insn_data2_type type);
343u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
344 enum aarch64_insn_register src,
345 enum aarch64_insn_register reg1,
346 enum aarch64_insn_register reg2,
347 enum aarch64_insn_variant variant,
348 enum aarch64_insn_data3_type type);
349u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
350 enum aarch64_insn_register src,
351 enum aarch64_insn_register reg,
352 int shift,
353 enum aarch64_insn_variant variant,
354 enum aarch64_insn_logic_type type);
355s32 aarch64_get_branch_offset(u32 insn);
356u32 aarch64_set_branch_offset(u32 insn, s32 offset);
357
358bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
359
360int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
361int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
362int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
363
364bool aarch32_insn_is_wide(u32 insn);
365
366#define A32_RN_OFFSET 16
367#define A32_RT_OFFSET 12
368#define A32_RT2_OFFSET 0
369
370u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
371u32 aarch32_insn_mcr_extract_opc2(u32 insn);
372u32 aarch32_insn_mcr_extract_crm(u32 insn);
373#endif /* __ASSEMBLY__ */
374
375#endif /* __ASM_INSN_H */