| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright 2005-2008 Analog Devices Inc. |
| 3 | * |
| 4 | * Licensed under the GPL-2 or later |
| 5 | */ |
| 6 | |
| 7 | #ifndef _BF537_IRQ_H_ |
| 8 | #define _BF537_IRQ_H_ |
| 9 | |
| 10 | #include <mach-common/irq.h> |
| 11 | |
| 12 | #define NR_PERI_INTS 32 |
| 13 | |
| 14 | #define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */ |
| 15 | #define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */ |
| 16 | #define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */ |
| 17 | #define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */ |
| 18 | #define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */ |
| 19 | #define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */ |
| 20 | #define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */ |
| 21 | #define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */ |
| 22 | #define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */ |
| 23 | #define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */ |
| 24 | #define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */ |
| 25 | #define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */ |
| 26 | #define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */ |
| 27 | #define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */ |
| 28 | #define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */ |
| 29 | #define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */ |
| 30 | #define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */ |
| 31 | #define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */ |
| 32 | #define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */ |
| 33 | #define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */ |
| 34 | #define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */ |
| 35 | #define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */ |
| 36 | #define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */ |
| 37 | #define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */ |
| 38 | #define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */ |
| 39 | #define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */ |
| 40 | #define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */ |
| 41 | #define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */ |
| 42 | #define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */ |
| 43 | #define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */ |
| 44 | #define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */ |
| 45 | #define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */ |
| 46 | |
| 47 | #define SYS_IRQS 39 |
| 48 | |
| 49 | #define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */ |
| 50 | #define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */ |
| 51 | #define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */ |
| 52 | #define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */ |
| 53 | #define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */ |
| 54 | #define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */ |
| 55 | #define IRQ_UART0_ERROR 48 /* UART Error Interrupt */ |
| 56 | #define IRQ_UART1_ERROR 49 /* UART Error Interrupt */ |
| 57 | |
| 58 | #define IRQ_PF0 50 |
| 59 | #define IRQ_PF1 51 |
| 60 | #define IRQ_PF2 52 |
| 61 | #define IRQ_PF3 53 |
| 62 | #define IRQ_PF4 54 |
| 63 | #define IRQ_PF5 55 |
| 64 | #define IRQ_PF6 56 |
| 65 | #define IRQ_PF7 57 |
| 66 | #define IRQ_PF8 58 |
| 67 | #define IRQ_PF9 59 |
| 68 | #define IRQ_PF10 60 |
| 69 | #define IRQ_PF11 61 |
| 70 | #define IRQ_PF12 62 |
| 71 | #define IRQ_PF13 63 |
| 72 | #define IRQ_PF14 64 |
| 73 | #define IRQ_PF15 65 |
| 74 | |
| 75 | #define IRQ_PG0 66 |
| 76 | #define IRQ_PG1 67 |
| 77 | #define IRQ_PG2 68 |
| 78 | #define IRQ_PG3 69 |
| 79 | #define IRQ_PG4 70 |
| 80 | #define IRQ_PG5 71 |
| 81 | #define IRQ_PG6 72 |
| 82 | #define IRQ_PG7 73 |
| 83 | #define IRQ_PG8 74 |
| 84 | #define IRQ_PG9 75 |
| 85 | #define IRQ_PG10 76 |
| 86 | #define IRQ_PG11 77 |
| 87 | #define IRQ_PG12 78 |
| 88 | #define IRQ_PG13 79 |
| 89 | #define IRQ_PG14 80 |
| 90 | #define IRQ_PG15 81 |
| 91 | |
| 92 | #define IRQ_PH0 82 |
| 93 | #define IRQ_PH1 83 |
| 94 | #define IRQ_PH2 84 |
| 95 | #define IRQ_PH3 85 |
| 96 | #define IRQ_PH4 86 |
| 97 | #define IRQ_PH5 87 |
| 98 | #define IRQ_PH6 88 |
| 99 | #define IRQ_PH7 89 |
| 100 | #define IRQ_PH8 90 |
| 101 | #define IRQ_PH9 91 |
| 102 | #define IRQ_PH10 92 |
| 103 | #define IRQ_PH11 93 |
| 104 | #define IRQ_PH12 94 |
| 105 | #define IRQ_PH13 95 |
| 106 | #define IRQ_PH14 96 |
| 107 | #define IRQ_PH15 97 |
| 108 | |
| 109 | #define GPIO_IRQ_BASE IRQ_PF0 |
| 110 | |
| 111 | #define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */ |
| 112 | #define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */ |
| 113 | #define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */ |
| 114 | #define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */ |
| 115 | #define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */ |
| 116 | #define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */ |
| 117 | #define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */ |
| 118 | #define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */ |
| 119 | |
| 120 | #define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */ |
| 121 | #define IRQ_PORTH_INTA 107 /* Port H Interrupt A */ |
| 122 | |
| 123 | #if 0 /* No Interrupt B support (yet) */ |
| 124 | #define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */ |
| 125 | #define IRQ_PORTH_INTB 109 /* Port H Interrupt B */ |
| 126 | #else |
| 127 | #define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX |
| 128 | #endif |
| 129 | |
| 130 | #define IRQ_PORTF_INTA 110 /* Port F Interrupt A */ |
| 131 | #define IRQ_PORTG_INTA 111 /* Port G Interrupt A */ |
| 132 | |
| 133 | #if 0 /* No Interrupt B support (yet) */ |
| 134 | #define IRQ_WATCH 112 /* Watchdog Timer */ |
| 135 | #define IRQ_PORTF_INTB 113 /* Port F Interrupt B */ |
| 136 | #else |
| 137 | #define IRQ_WATCH IRQ_PF_INTB_WATCH |
| 138 | #endif |
| 139 | |
| 140 | #define NR_MACH_IRQS (113 + 1) |
| 141 | |
| 142 | /* IAR0 BIT FIELDS */ |
| 143 | #define IRQ_PLL_WAKEUP_POS 0 |
| 144 | #define IRQ_DMA_ERROR_POS 4 |
| 145 | #define IRQ_ERROR_POS 8 |
| 146 | #define IRQ_RTC_POS 12 |
| 147 | #define IRQ_PPI_POS 16 |
| 148 | #define IRQ_SPORT0_RX_POS 20 |
| 149 | #define IRQ_SPORT0_TX_POS 24 |
| 150 | #define IRQ_SPORT1_RX_POS 28 |
| 151 | |
| 152 | /* IAR1 BIT FIELDS */ |
| 153 | #define IRQ_SPORT1_TX_POS 0 |
| 154 | #define IRQ_TWI_POS 4 |
| 155 | #define IRQ_SPI_POS 8 |
| 156 | #define IRQ_UART0_RX_POS 12 |
| 157 | #define IRQ_UART0_TX_POS 16 |
| 158 | #define IRQ_UART1_RX_POS 20 |
| 159 | #define IRQ_UART1_TX_POS 24 |
| 160 | #define IRQ_CAN_RX_POS 28 |
| 161 | |
| 162 | /* IAR2 BIT FIELDS */ |
| 163 | #define IRQ_CAN_TX_POS 0 |
| 164 | #define IRQ_MAC_RX_POS 4 |
| 165 | #define IRQ_MAC_TX_POS 8 |
| 166 | #define IRQ_TIMER0_POS 12 |
| 167 | #define IRQ_TIMER1_POS 16 |
| 168 | #define IRQ_TIMER2_POS 20 |
| 169 | #define IRQ_TIMER3_POS 24 |
| 170 | #define IRQ_TIMER4_POS 28 |
| 171 | |
| 172 | /* IAR3 BIT FIELDS */ |
| 173 | #define IRQ_TIMER5_POS 0 |
| 174 | #define IRQ_TIMER6_POS 4 |
| 175 | #define IRQ_TIMER7_POS 8 |
| 176 | #define IRQ_PROG_INTA_POS 12 |
| 177 | #define IRQ_PORTG_INTB_POS 16 |
| 178 | #define IRQ_MEM_DMA0_POS 20 |
| 179 | #define IRQ_MEM_DMA1_POS 24 |
| 180 | #define IRQ_WATCH_POS 28 |
| 181 | |
| 182 | #define init_mach_irq init_mach_irq |
| 183 | |
| 184 | #endif |