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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / arch / mips / include / asm / octeon / cvmx-l2t-defs.h
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Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__
30
31#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
32
33union cvmx_l2t_err {
34 uint64_t u64;
35 struct cvmx_l2t_err_s {
36#ifdef __BIG_ENDIAN_BITFIELD
37 uint64_t reserved_29_63:35;
38 uint64_t fadru:1;
39 uint64_t lck_intena2:1;
40 uint64_t lckerr2:1;
41 uint64_t lck_intena:1;
42 uint64_t lckerr:1;
43 uint64_t fset:3;
44 uint64_t fadr:10;
45 uint64_t fsyn:6;
46 uint64_t ded_err:1;
47 uint64_t sec_err:1;
48 uint64_t ded_intena:1;
49 uint64_t sec_intena:1;
50 uint64_t ecc_ena:1;
51#else
52 uint64_t ecc_ena:1;
53 uint64_t sec_intena:1;
54 uint64_t ded_intena:1;
55 uint64_t sec_err:1;
56 uint64_t ded_err:1;
57 uint64_t fsyn:6;
58 uint64_t fadr:10;
59 uint64_t fset:3;
60 uint64_t lckerr:1;
61 uint64_t lck_intena:1;
62 uint64_t lckerr2:1;
63 uint64_t lck_intena2:1;
64 uint64_t fadru:1;
65 uint64_t reserved_29_63:35;
66#endif
67 } s;
68 struct cvmx_l2t_err_cn30xx {
69#ifdef __BIG_ENDIAN_BITFIELD
70 uint64_t reserved_28_63:36;
71 uint64_t lck_intena2:1;
72 uint64_t lckerr2:1;
73 uint64_t lck_intena:1;
74 uint64_t lckerr:1;
75 uint64_t reserved_23_23:1;
76 uint64_t fset:2;
77 uint64_t reserved_19_20:2;
78 uint64_t fadr:8;
79 uint64_t fsyn:6;
80 uint64_t ded_err:1;
81 uint64_t sec_err:1;
82 uint64_t ded_intena:1;
83 uint64_t sec_intena:1;
84 uint64_t ecc_ena:1;
85#else
86 uint64_t ecc_ena:1;
87 uint64_t sec_intena:1;
88 uint64_t ded_intena:1;
89 uint64_t sec_err:1;
90 uint64_t ded_err:1;
91 uint64_t fsyn:6;
92 uint64_t fadr:8;
93 uint64_t reserved_19_20:2;
94 uint64_t fset:2;
95 uint64_t reserved_23_23:1;
96 uint64_t lckerr:1;
97 uint64_t lck_intena:1;
98 uint64_t lckerr2:1;
99 uint64_t lck_intena2:1;
100 uint64_t reserved_28_63:36;
101#endif
102 } cn30xx;
103 struct cvmx_l2t_err_cn31xx {
104#ifdef __BIG_ENDIAN_BITFIELD
105 uint64_t reserved_28_63:36;
106 uint64_t lck_intena2:1;
107 uint64_t lckerr2:1;
108 uint64_t lck_intena:1;
109 uint64_t lckerr:1;
110 uint64_t reserved_23_23:1;
111 uint64_t fset:2;
112 uint64_t reserved_20_20:1;
113 uint64_t fadr:9;
114 uint64_t fsyn:6;
115 uint64_t ded_err:1;
116 uint64_t sec_err:1;
117 uint64_t ded_intena:1;
118 uint64_t sec_intena:1;
119 uint64_t ecc_ena:1;
120#else
121 uint64_t ecc_ena:1;
122 uint64_t sec_intena:1;
123 uint64_t ded_intena:1;
124 uint64_t sec_err:1;
125 uint64_t ded_err:1;
126 uint64_t fsyn:6;
127 uint64_t fadr:9;
128 uint64_t reserved_20_20:1;
129 uint64_t fset:2;
130 uint64_t reserved_23_23:1;
131 uint64_t lckerr:1;
132 uint64_t lck_intena:1;
133 uint64_t lckerr2:1;
134 uint64_t lck_intena2:1;
135 uint64_t reserved_28_63:36;
136#endif
137 } cn31xx;
138 struct cvmx_l2t_err_cn38xx {
139#ifdef __BIG_ENDIAN_BITFIELD
140 uint64_t reserved_28_63:36;
141 uint64_t lck_intena2:1;
142 uint64_t lckerr2:1;
143 uint64_t lck_intena:1;
144 uint64_t lckerr:1;
145 uint64_t fset:3;
146 uint64_t fadr:10;
147 uint64_t fsyn:6;
148 uint64_t ded_err:1;
149 uint64_t sec_err:1;
150 uint64_t ded_intena:1;
151 uint64_t sec_intena:1;
152 uint64_t ecc_ena:1;
153#else
154 uint64_t ecc_ena:1;
155 uint64_t sec_intena:1;
156 uint64_t ded_intena:1;
157 uint64_t sec_err:1;
158 uint64_t ded_err:1;
159 uint64_t fsyn:6;
160 uint64_t fadr:10;
161 uint64_t fset:3;
162 uint64_t lckerr:1;
163 uint64_t lck_intena:1;
164 uint64_t lckerr2:1;
165 uint64_t lck_intena2:1;
166 uint64_t reserved_28_63:36;
167#endif
168 } cn38xx;
169 struct cvmx_l2t_err_cn38xx cn38xxp2;
170 struct cvmx_l2t_err_cn50xx {
171#ifdef __BIG_ENDIAN_BITFIELD
172 uint64_t reserved_28_63:36;
173 uint64_t lck_intena2:1;
174 uint64_t lckerr2:1;
175 uint64_t lck_intena:1;
176 uint64_t lckerr:1;
177 uint64_t fset:3;
178 uint64_t reserved_18_20:3;
179 uint64_t fadr:7;
180 uint64_t fsyn:6;
181 uint64_t ded_err:1;
182 uint64_t sec_err:1;
183 uint64_t ded_intena:1;
184 uint64_t sec_intena:1;
185 uint64_t ecc_ena:1;
186#else
187 uint64_t ecc_ena:1;
188 uint64_t sec_intena:1;
189 uint64_t ded_intena:1;
190 uint64_t sec_err:1;
191 uint64_t ded_err:1;
192 uint64_t fsyn:6;
193 uint64_t fadr:7;
194 uint64_t reserved_18_20:3;
195 uint64_t fset:3;
196 uint64_t lckerr:1;
197 uint64_t lck_intena:1;
198 uint64_t lckerr2:1;
199 uint64_t lck_intena2:1;
200 uint64_t reserved_28_63:36;
201#endif
202 } cn50xx;
203 struct cvmx_l2t_err_cn52xx {
204#ifdef __BIG_ENDIAN_BITFIELD
205 uint64_t reserved_28_63:36;
206 uint64_t lck_intena2:1;
207 uint64_t lckerr2:1;
208 uint64_t lck_intena:1;
209 uint64_t lckerr:1;
210 uint64_t fset:3;
211 uint64_t reserved_20_20:1;
212 uint64_t fadr:9;
213 uint64_t fsyn:6;
214 uint64_t ded_err:1;
215 uint64_t sec_err:1;
216 uint64_t ded_intena:1;
217 uint64_t sec_intena:1;
218 uint64_t ecc_ena:1;
219#else
220 uint64_t ecc_ena:1;
221 uint64_t sec_intena:1;
222 uint64_t ded_intena:1;
223 uint64_t sec_err:1;
224 uint64_t ded_err:1;
225 uint64_t fsyn:6;
226 uint64_t fadr:9;
227 uint64_t reserved_20_20:1;
228 uint64_t fset:3;
229 uint64_t lckerr:1;
230 uint64_t lck_intena:1;
231 uint64_t lckerr2:1;
232 uint64_t lck_intena2:1;
233 uint64_t reserved_28_63:36;
234#endif
235 } cn52xx;
236 struct cvmx_l2t_err_cn52xx cn52xxp1;
237 struct cvmx_l2t_err_s cn56xx;
238 struct cvmx_l2t_err_s cn56xxp1;
239 struct cvmx_l2t_err_s cn58xx;
240 struct cvmx_l2t_err_s cn58xxp1;
241};
242
243#endif