blob: c4a0336660dd102d6542b3f3a5721214439dce08 [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -06001#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5#include <cpu/gpio.h>
6
7static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
8{
9 unsigned short data;
10
11 if (cflag & CRTSCTS) {
12 /* enable RTS/CTS */
13 if (port->mapbase == 0xa4430000) { /* SCIF0 */
14 /* Clear PTCR bit 9-2; enable all scif pins but sck */
15 data = __raw_readw(PORT_PTCR);
16 __raw_writew((data & 0xfc03), PORT_PTCR);
17 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
18 /* Clear PVCR bit 9-2 */
19 data = __raw_readw(PORT_PVCR);
20 __raw_writew((data & 0xfc03), PORT_PVCR);
21 }
22 } else {
23 if (port->mapbase == 0xa4430000) { /* SCIF0 */
24 /* Clear PTCR bit 5-2; enable only tx and rx */
25 data = __raw_readw(PORT_PTCR);
26 __raw_writew((data & 0xffc3), PORT_PTCR);
27 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
28 /* Clear PVCR bit 5-2 */
29 data = __raw_readw(PORT_PVCR);
30 __raw_writew((data & 0xffc3), PORT_PVCR);
31 }
32 }
33}
34
35struct plat_sci_port_ops sh7720_sci_port_ops = {
36 .init_pins = sh7720_sci_init_pins,
37};