| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | #ifndef _SPARC64_DCR_H |
| 2 | #define _SPARC64_DCR_H |
| 3 | |
| 4 | /* UltraSparc-III/III+ Dispatch Control Register, ASR 0x12 */ |
| 5 | #define DCR_DPE 0x0000000000001000 /* III+: D$ Parity Error Enable */ |
| 6 | #define DCR_OBS 0x0000000000000fc0 /* Observability Bus Controls */ |
| 7 | #define DCR_BPE 0x0000000000000020 /* Branch Predict Enable */ |
| 8 | #define DCR_RPE 0x0000000000000010 /* Return Address Prediction Enable */ |
| 9 | #define DCR_SI 0x0000000000000008 /* Single Instruction Disable */ |
| 10 | #define DCR_IPE 0x0000000000000004 /* III+: I$ Parity Error Enable */ |
| 11 | #define DCR_IFPOE 0x0000000000000002 /* IRQ FP Operation Enable */ |
| 12 | #define DCR_MS 0x0000000000000001 /* Multi-Scalar dispatch */ |
| 13 | |
| 14 | #endif /* _SPARC64_DCR_H */ |