| Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * x86 TSC related functions |
| 3 | */ |
| 4 | #ifndef _ASM_X86_TSC_H |
| 5 | #define _ASM_X86_TSC_H |
| 6 | |
| 7 | #include <asm/processor.h> |
| 8 | |
| 9 | #define NS_SCALE 10 /* 2^10, carefully chosen */ |
| 10 | #define US_SCALE 32 /* 2^32, arbitralrily chosen */ |
| 11 | |
| 12 | /* |
| 13 | * Standard way to access the cycle counter. |
| 14 | */ |
| 15 | typedef unsigned long long cycles_t; |
| 16 | |
| 17 | extern unsigned int cpu_khz; |
| 18 | extern unsigned int tsc_khz; |
| 19 | |
| 20 | extern void disable_TSC(void); |
| 21 | |
| 22 | static inline cycles_t get_cycles(void) |
| 23 | { |
| 24 | #ifndef CONFIG_X86_TSC |
| 25 | if (!cpu_has_tsc) |
| 26 | return 0; |
| 27 | #endif |
| 28 | |
| 29 | return rdtsc(); |
| 30 | } |
| 31 | |
| 32 | extern void tsc_init(void); |
| 33 | extern void mark_tsc_unstable(char *reason); |
| 34 | extern int unsynchronized_tsc(void); |
| 35 | extern int check_tsc_unstable(void); |
| 36 | extern int check_tsc_disabled(void); |
| 37 | extern unsigned long native_calibrate_tsc(void); |
| 38 | extern unsigned long long native_sched_clock_from_tsc(u64 tsc); |
| 39 | |
| 40 | extern int tsc_clocksource_reliable; |
| 41 | |
| 42 | /* |
| 43 | * Boot-time check whether the TSCs are synchronized across |
| 44 | * all CPUs/cores: |
| 45 | */ |
| 46 | extern void check_tsc_sync_source(int cpu); |
| 47 | extern void check_tsc_sync_target(void); |
| 48 | |
| 49 | extern int notsc_setup(char *); |
| 50 | extern void tsc_save_sched_clock_state(void); |
| 51 | extern void tsc_restore_sched_clock_state(void); |
| 52 | |
| 53 | /* MSR based TSC calibration for Intel Atom SoC platforms */ |
| 54 | unsigned long try_msr_calibrate_tsc(void); |
| 55 | |
| 56 | #endif /* _ASM_X86_TSC_H */ |