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gerrit.nordix.org / codeaurora / cp-linux / 8d8f6542b666daf5e87de156590e635c2c4da0c0 / . / drivers / scsi / arcmsr / arcmsr.h
blob: 3bcaaac0ae4bb5080b0d4c64223e20d7a8754dfa [file] [log] [blame]
Kyle Swenson8d8f6542021-03-15 11:02:55 -0600[diff] [blame^]1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr.h
5** BY : Nick Cheng
6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved.
10**
11** Web site: www.areca.com.tw
12** E-mail: support@areca.com.tw
13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44*/
45#include <linux/interrupt.h>
46struct device_attribute;
47/*The limit of outstanding scsi command that firmware can handle*/
48#ifdef CONFIG_XEN
49 #define ARCMSR_MAX_FREECCB_NUM 160
50#define ARCMSR_MAX_OUTSTANDING_CMD 155
51#else
52 #define ARCMSR_MAX_FREECCB_NUM 320
53#define ARCMSR_MAX_OUTSTANDING_CMD 255
54#endif
55#define ARCMSR_DRIVER_VERSION "v1.30.00.04-20140919"
56#define ARCMSR_SCSI_INITIATOR_ID 255
57#define ARCMSR_MAX_XFER_SECTORS 512
58#define ARCMSR_MAX_XFER_SECTORS_B 4096
59#define ARCMSR_MAX_XFER_SECTORS_C 304
60#define ARCMSR_MAX_TARGETID 17
61#define ARCMSR_MAX_TARGETLUN 8
62#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD
63#define ARCMSR_MAX_QBUFFER 4096
64#define ARCMSR_DEFAULT_SG_ENTRIES 38
65#define ARCMSR_MAX_HBB_POSTQUEUE 264
66#define ARCMSR_MAX_ARC1214_POSTQUEUE 256
67#define ARCMSR_MAX_ARC1214_DONEQUEUE 257
68#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */
69#define ARCMSR_CDB_SG_PAGE_LENGTH 256
70#define ARCMST_NUM_MSIX_VECTORS 4
71#ifndef PCI_DEVICE_ID_ARECA_1880
72#define PCI_DEVICE_ID_ARECA_1880 0x1880
73 #endif
74#ifndef PCI_DEVICE_ID_ARECA_1214
75 #define PCI_DEVICE_ID_ARECA_1214 0x1214
76#endif
77/*
78**********************************************************************************
79**
80**********************************************************************************
81*/
82#define ARC_SUCCESS 0
83#define ARC_FAILURE 1
84/*
85*******************************************************************************
86** split 64bits dma addressing
87*******************************************************************************
88*/
89#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
90#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
91/*
92*******************************************************************************
93** MESSAGE CONTROL CODE
94*******************************************************************************
95*/
96struct CMD_MESSAGE
97{
98 uint32_t HeaderLength;
99 uint8_t Signature[8];
100 uint32_t Timeout;
101 uint32_t ControlCode;
102 uint32_t ReturnCode;
103 uint32_t Length;
104};
105/*
106*******************************************************************************
107** IOP Message Transfer Data for user space
108*******************************************************************************
109*/
110#define ARCMSR_API_DATA_BUFLEN 1032
111struct CMD_MESSAGE_FIELD
112{
113 struct CMD_MESSAGE cmdmessage;
114 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN];
115};
116/* IOP message transfer */
117#define ARCMSR_MESSAGE_FAIL 0x0001
118/* DeviceType */
119#define ARECA_SATA_RAID 0x90000000
120/* FunctionCode */
121#define FUNCTION_READ_RQBUFFER 0x0801
122#define FUNCTION_WRITE_WQBUFFER 0x0802
123#define FUNCTION_CLEAR_RQBUFFER 0x0803
124#define FUNCTION_CLEAR_WQBUFFER 0x0804
125#define FUNCTION_CLEAR_ALLQBUFFER 0x0805
126#define FUNCTION_RETURN_CODE_3F 0x0806
127#define FUNCTION_SAY_HELLO 0x0807
128#define FUNCTION_SAY_GOODBYE 0x0808
129#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809
130#define FUNCTION_GET_FIRMWARE_STATUS 0x080A
131#define FUNCTION_HARDWARE_RESET 0x080B
132/* ARECA IO CONTROL CODE*/
133#define ARCMSR_MESSAGE_READ_RQBUFFER \
134 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER
135#define ARCMSR_MESSAGE_WRITE_WQBUFFER \
136 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER
137#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \
138 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER
139#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \
140 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER
141#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \
142 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER
143#define ARCMSR_MESSAGE_RETURN_CODE_3F \
144 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F
145#define ARCMSR_MESSAGE_SAY_HELLO \
146 ARECA_SATA_RAID | FUNCTION_SAY_HELLO
147#define ARCMSR_MESSAGE_SAY_GOODBYE \
148 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE
149#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \
150 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE
151/* ARECA IOCTL ReturnCode */
152#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001
153#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006
154#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F
155#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088
156/*
157*************************************************************
158** structure for holding DMA address data
159*************************************************************
160*/
161#define IS_DMA64 (sizeof(dma_addr_t) == 8)
162#define IS_SG64_ADDR 0x01000000 /* bit24 */
163struct SG32ENTRY
164{
165 __le32 length;
166 __le32 address;
167}__attribute__ ((packed));
168struct SG64ENTRY
169{
170 __le32 length;
171 __le32 address;
172 __le32 addresshigh;
173}__attribute__ ((packed));
174/*
175********************************************************************
176** Q Buffer of IOP Message Transfer
177********************************************************************
178*/
179struct QBUFFER
180{
181 uint32_t data_len;
182 uint8_t data[124];
183};
184/*
185*******************************************************************************
186** FIRMWARE INFO for Intel IOP R 80331 processor (Type A)
187*******************************************************************************
188*/
189struct FIRMWARE_INFO
190{
191 uint32_t signature; /*0, 00-03*/
192 uint32_t request_len; /*1, 04-07*/
193 uint32_t numbers_queue; /*2, 08-11*/
194 uint32_t sdram_size; /*3, 12-15*/
195 uint32_t ide_channels; /*4, 16-19*/
196 char vendor[40]; /*5, 20-59*/
197 char model[8]; /*15, 60-67*/
198 char firmware_ver[16]; /*17, 68-83*/
199 char device_map[16]; /*21, 84-99*/
200 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/
201 uint8_t cfgSerial[16]; /*26,104-119*/
202 uint32_t cfgPicStatus; /*30,120-123*/
203};
204/* signature of set and get firmware config */
205#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060
206#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063
207/* message code of inbound message register */
208#define ARCMSR_INBOUND_MESG0_NOP 0x00000000
209#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001
210#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002
211#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003
212#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004
213#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005
214#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006
215#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007
216#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008
217/* doorbell interrupt generator */
218#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001
219#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002
220#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001
221#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002
222/* ccb areca cdb flag */
223#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000
224#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000
225#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000
226#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000
227#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001
228/* outbound firmware ok */
229#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000
230/* ARC-1680 Bus Reset*/
231#define ARCMSR_ARC1680_BUS_RESET 0x00000003
232/* ARC-1880 Bus Reset*/
233#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024
234#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080
235
236/*
237************************************************************************
238** SPEC. for Areca Type B adapter
239************************************************************************
240*/
241/* ARECA HBB COMMAND for its FIRMWARE */
242/* window of "instruction flags" from driver to iop */
243#define ARCMSR_DRV2IOP_DOORBELL 0x00020400
244#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404
245/* window of "instruction flags" from iop to driver */
246#define ARCMSR_IOP2DRV_DOORBELL 0x00020408
247#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C
248/* ARECA FLAG LANGUAGE */
249/* ioctl transfer */
250#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001
251/* ioctl transfer */
252#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002
253#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004
254#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
255
256#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F
257#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0
258#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7
259/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
260#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008
261/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
262#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008
263/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
264#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008
265/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
266#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008
267/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
268#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008
269/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */
270#define ARCMSR_MESSAGE_START_BGRB 0x00060008
271#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008
272#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008
273#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008
274/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */
275#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000
276/* ioctl transfer */
277#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001
278/* ioctl transfer */
279#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002
280#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004
281#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008
282#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010
283
284/* data tunnel buffer between user space program and its firmware */
285/* user space data to iop 128bytes */
286#define ARCMSR_MESSAGE_WBUFFER 0x0000fe00
287/* iop data to user space 128bytes */
288#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00
289/* iop message_rwbuffer for message command */
290#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00
291/*
292************************************************************************
293** SPEC. for Areca HBC adapter
294************************************************************************
295*/
296#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12
297#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20
298/* Host Interrupt Mask */
299#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/
300#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/
301#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/
302#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */
303/* Host Interrupt Status */
304#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001
305 /*
306 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register.
307 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled).
308 */
309#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004
310 /*
311 ** Set if Outbound Doorbell register bits 30:1 have a non-zero
312 ** value. This bit clears only when Outbound Doorbell bits
313 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell
314 ** Clear register clears bits in the Outbound Doorbell register.
315 */
316#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008
317 /*
318 ** Set whenever the Outbound Post List Producer/Consumer
319 ** Register (FIFO) is not empty. It clears when the Outbound
320 ** Post List FIFO is empty.
321 */
322#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010
323 /*
324 ** This bit indicates a SAS interrupt from a source external to
325 ** the PCIe core. This bit is not maskable.
326 */
327 /* DoorBell*/
328#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002
329#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004
330 /*inbound message 0 ready*/
331#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008
332 /*more than 12 request completed in a time*/
333#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010
334#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002
335 /*outbound DATA WRITE isr door bell clear*/
336#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002
337#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004
338 /*outbound DATA READ isr door bell clear*/
339#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004
340 /*outbound message 0 ready*/
341#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008
342 /*outbound message cmd isr door bell clear*/
343#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008
344 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
345#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000
346/*
347*******************************************************************************
348** SPEC. for Areca Type D adapter
349*******************************************************************************
350*/
351#define ARCMSR_ARC1214_CHIP_ID 0x00004
352#define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008
353#define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034
354#define ARCMSR_ARC1214_SAMPLE_RESET 0x00100
355#define ARCMSR_ARC1214_RESET_REQUEST 0x00108
356#define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200
357#define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C
358#define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400
359#define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404
360#define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420
361#define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424
362#define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460
363#define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480
364#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484
365#define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000
366#define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004
367#define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018
368#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060
369#define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064
370#define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C
371#define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070
372#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088
373#define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C
374#define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000
375#define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100
376#define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200
377/* Host Interrupt Mask */
378#define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010
379#define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000
380/* Host Interrupt Status */
381#define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000
382#define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010
383/* DoorBell*/
384#define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001
385#define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002
386/*inbound message 0 ready*/
387#define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001
388/*outbound DATA WRITE isr door bell clear*/
389#define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002
390/*outbound message 0 ready*/
391#define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000
392/*outbound message cmd isr door bell clear*/
393/*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/
394#define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000
395#define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001
396/*
397*******************************************************************************
398** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504)
399*******************************************************************************
400*/
401struct ARCMSR_CDB
402{
403 uint8_t Bus;
404 uint8_t TargetID;
405 uint8_t LUN;
406 uint8_t Function;
407 uint8_t CdbLength;
408 uint8_t sgcount;
409 uint8_t Flags;
410#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01
411#define ARCMSR_CDB_FLAG_BIOS 0x02
412#define ARCMSR_CDB_FLAG_WRITE 0x04
413#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00
414#define ARCMSR_CDB_FLAG_HEADQ 0x08
415#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10
416
417 uint8_t msgPages;
418 uint32_t msgContext;
419 uint32_t DataLength;
420 uint8_t Cdb[16];
421 uint8_t DeviceStatus;
422#define ARCMSR_DEV_CHECK_CONDITION 0x02
423#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0
424#define ARCMSR_DEV_ABORTED 0xF1
425#define ARCMSR_DEV_INIT_FAIL 0xF2
426
427 uint8_t SenseData[15];
428 union
429 {
430 struct SG32ENTRY sg32entry[1];
431 struct SG64ENTRY sg64entry[1];
432 } u;
433};
434/*
435*******************************************************************************
436** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor
437*******************************************************************************
438*/
439struct MessageUnit_A
440{
441 uint32_t resrved0[4]; /*0000 000F*/
442 uint32_t inbound_msgaddr0; /*0010 0013*/
443 uint32_t inbound_msgaddr1; /*0014 0017*/
444 uint32_t outbound_msgaddr0; /*0018 001B*/
445 uint32_t outbound_msgaddr1; /*001C 001F*/
446 uint32_t inbound_doorbell; /*0020 0023*/
447 uint32_t inbound_intstatus; /*0024 0027*/
448 uint32_t inbound_intmask; /*0028 002B*/
449 uint32_t outbound_doorbell; /*002C 002F*/
450 uint32_t outbound_intstatus; /*0030 0033*/
451 uint32_t outbound_intmask; /*0034 0037*/
452 uint32_t reserved1[2]; /*0038 003F*/
453 uint32_t inbound_queueport; /*0040 0043*/
454 uint32_t outbound_queueport; /*0044 0047*/
455 uint32_t reserved2[2]; /*0048 004F*/
456 uint32_t reserved3[492]; /*0050 07FF 492*/
457 uint32_t reserved4[128]; /*0800 09FF 128*/
458 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/
459 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/
460 uint32_t reserved5[32]; /*0E80 0EFF 32*/
461 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/
462 uint32_t reserved6[32]; /*0F80 0FFF 32*/
463};
464
465struct MessageUnit_B
466{
467 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
468 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE];
469 uint32_t postq_index;
470 uint32_t doneq_index;
471 uint32_t __iomem *drv2iop_doorbell;
472 uint32_t __iomem *drv2iop_doorbell_mask;
473 uint32_t __iomem *iop2drv_doorbell;
474 uint32_t __iomem *iop2drv_doorbell_mask;
475 uint32_t __iomem *message_rwbuffer;
476 uint32_t __iomem *message_wbuffer;
477 uint32_t __iomem *message_rbuffer;
478};
479/*
480*********************************************************************
481** LSI
482*********************************************************************
483*/
484struct MessageUnit_C{
485 uint32_t message_unit_status; /*0000 0003*/
486 uint32_t slave_error_attribute; /*0004 0007*/
487 uint32_t slave_error_address; /*0008 000B*/
488 uint32_t posted_outbound_doorbell; /*000C 000F*/
489 uint32_t master_error_attribute; /*0010 0013*/
490 uint32_t master_error_address_low; /*0014 0017*/
491 uint32_t master_error_address_high; /*0018 001B*/
492 uint32_t hcb_size; /*001C 001F*/
493 uint32_t inbound_doorbell; /*0020 0023*/
494 uint32_t diagnostic_rw_data; /*0024 0027*/
495 uint32_t diagnostic_rw_address_low; /*0028 002B*/
496 uint32_t diagnostic_rw_address_high; /*002C 002F*/
497 uint32_t host_int_status; /*0030 0033*/
498 uint32_t host_int_mask; /*0034 0037*/
499 uint32_t dcr_data; /*0038 003B*/
500 uint32_t dcr_address; /*003C 003F*/
501 uint32_t inbound_queueport; /*0040 0043*/
502 uint32_t outbound_queueport; /*0044 0047*/
503 uint32_t hcb_pci_address_low; /*0048 004B*/
504 uint32_t hcb_pci_address_high; /*004C 004F*/
505 uint32_t iop_int_status; /*0050 0053*/
506 uint32_t iop_int_mask; /*0054 0057*/
507 uint32_t iop_inbound_queue_port; /*0058 005B*/
508 uint32_t iop_outbound_queue_port; /*005C 005F*/
509 uint32_t inbound_free_list_index; /*0060 0063*/
510 uint32_t inbound_post_list_index; /*0064 0067*/
511 uint32_t outbound_free_list_index; /*0068 006B*/
512 uint32_t outbound_post_list_index; /*006C 006F*/
513 uint32_t inbound_doorbell_clear; /*0070 0073*/
514 uint32_t i2o_message_unit_control; /*0074 0077*/
515 uint32_t last_used_message_source_address_low; /*0078 007B*/
516 uint32_t last_used_message_source_address_high; /*007C 007F*/
517 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/
518 uint32_t message_dest_address_index; /*0090 0093*/
519 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/
520 uint32_t utility_A_int_counter_timer; /*0098 009B*/
521 uint32_t outbound_doorbell; /*009C 009F*/
522 uint32_t outbound_doorbell_clear; /*00A0 00A3*/
523 uint32_t message_source_address_index; /*00A4 00A7*/
524 uint32_t message_done_queue_index; /*00A8 00AB*/
525 uint32_t reserved0; /*00AC 00AF*/
526 uint32_t inbound_msgaddr0; /*00B0 00B3*/
527 uint32_t inbound_msgaddr1; /*00B4 00B7*/
528 uint32_t outbound_msgaddr0; /*00B8 00BB*/
529 uint32_t outbound_msgaddr1; /*00BC 00BF*/
530 uint32_t inbound_queueport_low; /*00C0 00C3*/
531 uint32_t inbound_queueport_high; /*00C4 00C7*/
532 uint32_t outbound_queueport_low; /*00C8 00CB*/
533 uint32_t outbound_queueport_high; /*00CC 00CF*/
534 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/
535 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/
536 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/
537 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/
538 uint32_t message_dest_queue_port_low; /*00E0 00E3*/
539 uint32_t message_dest_queue_port_high; /*00E4 00E7*/
540 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/
541 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/
542 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/
543 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/
544 uint32_t host_diagnostic; /*00F8 00FB*/
545 uint32_t write_sequence; /*00FC 00FF*/
546 uint32_t reserved1[34]; /*0100 0187*/
547 uint32_t reserved2[1950]; /*0188 1FFF*/
548 uint32_t message_wbuffer[32]; /*2000 207F*/
549 uint32_t reserved3[32]; /*2080 20FF*/
550 uint32_t message_rbuffer[32]; /*2100 217F*/
551 uint32_t reserved4[32]; /*2180 21FF*/
552 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/
553};
554/*
555*********************************************************************
556** Messaging Unit (MU) of Type D processor
557*********************************************************************
558*/
559struct InBound_SRB {
560 uint32_t addressLow; /* pointer to SRB block */
561 uint32_t addressHigh;
562 uint32_t length; /* in DWORDs */
563 uint32_t reserved0;
564};
565
566struct OutBound_SRB {
567 uint32_t addressLow; /* pointer to SRB block */
568 uint32_t addressHigh;
569};
570
571struct MessageUnit_D {
572 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE];
573 volatile struct OutBound_SRB
574 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE];
575 u16 postq_index;
576 volatile u16 doneq_index;
577 u32 __iomem *chip_id; /* 0x00004 */
578 u32 __iomem *cpu_mem_config; /* 0x00008 */
579 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */
580 u32 __iomem *sample_at_reset; /* 0x00100 */
581 u32 __iomem *reset_request; /* 0x00108 */
582 u32 __iomem *host_int_status; /* 0x00200 */
583 u32 __iomem *pcief0_int_enable; /* 0x0020C */
584 u32 __iomem *inbound_msgaddr0; /* 0x00400 */
585 u32 __iomem *inbound_msgaddr1; /* 0x00404 */
586 u32 __iomem *outbound_msgaddr0; /* 0x00420 */
587 u32 __iomem *outbound_msgaddr1; /* 0x00424 */
588 u32 __iomem *inbound_doorbell; /* 0x00460 */
589 u32 __iomem *outbound_doorbell; /* 0x00480 */
590 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */
591 u32 __iomem *inboundlist_base_low; /* 0x01000 */
592 u32 __iomem *inboundlist_base_high; /* 0x01004 */
593 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */
594 u32 __iomem *outboundlist_base_low; /* 0x01060 */
595 u32 __iomem *outboundlist_base_high; /* 0x01064 */
596 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */
597 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */
598 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */
599 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */
600 u32 __iomem *message_wbuffer; /* 0x2000 */
601 u32 __iomem *message_rbuffer; /* 0x2100 */
602 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */
603};
604/*
605*******************************************************************************
606** Adapter Control Block
607*******************************************************************************
608*/
609struct AdapterControlBlock
610{
611 uint32_t adapter_type; /* adapter A,B..... */
612 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */
613 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */
614 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */
615 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */
616 u32 roundup_ccbsize;
617 struct pci_dev * pdev;
618 struct Scsi_Host * host;
619 unsigned long vir2phy_offset;
620 struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS];
621 /* Offset is used in making arc cdb physical to virtual calculations */
622 uint32_t outbound_int_enable;
623 uint32_t cdb_phyaddr_hi32;
624 uint32_t reg_mu_acc_handle0;
625 spinlock_t eh_lock;
626 spinlock_t ccblist_lock;
627 spinlock_t postq_lock;
628 spinlock_t doneq_lock;
629 spinlock_t rqbuffer_lock;
630 spinlock_t wqbuffer_lock;
631 union {
632 struct MessageUnit_A __iomem *pmuA;
633 struct MessageUnit_B *pmuB;
634 struct MessageUnit_C __iomem *pmuC;
635 struct MessageUnit_D *pmuD;
636 };
637 /* message unit ATU inbound base address0 */
638 void __iomem *mem_base0;
639 void __iomem *mem_base1;
640 uint32_t acb_flags;
641 u16 dev_id;
642 uint8_t adapter_index;
643 #define ACB_F_SCSISTOPADAPTER 0x0001
644 #define ACB_F_MSG_STOP_BGRB 0x0002
645 /* stop RAID background rebuild */
646 #define ACB_F_MSG_START_BGRB 0x0004
647 /* stop RAID background rebuild */
648 #define ACB_F_IOPDATA_OVERFLOW 0x0008
649 /* iop message data rqbuffer overflow */
650 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010
651 /* message clear wqbuffer */
652 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020
653 /* message clear rqbuffer */
654 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040
655 #define ACB_F_BUS_RESET 0x0080
656 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */
657
658 #define ACB_F_IOP_INITED 0x0100
659 /* iop init */
660 #define ACB_F_ABORT 0x0200
661 #define ACB_F_FIRMWARE_TRAP 0x0400
662 #define ACB_F_MSI_ENABLED 0x1000
663 #define ACB_F_MSIX_ENABLED 0x2000
664 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM];
665 /* used for memory free */
666 struct list_head ccb_free_list;
667 /* head of free ccb list */
668
669 atomic_t ccboutstandingcount;
670 /*The present outstanding command number that in the IOP that
671 waiting for being handled by FW*/
672
673 void * dma_coherent;
674 /* dma_coherent used for memory free */
675 dma_addr_t dma_coherent_handle;
676 /* dma_coherent_handle used for memory free */
677 dma_addr_t dma_coherent_handle2;
678 void *dma_coherent2;
679 unsigned int uncache_size;
680 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER];
681 /* data collection buffer for read from 80331 */
682 int32_t rqbuf_getIndex;
683 /* first of read buffer */
684 int32_t rqbuf_putIndex;
685 /* last of read buffer */
686 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER];
687 /* data collection buffer for write to 80331 */
688 int32_t wqbuf_getIndex;
689 /* first of write buffer */
690 int32_t wqbuf_putIndex;
691 /* last of write buffer */
692 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN];
693 /* id0 ..... id15, lun0...lun7 */
694#define ARECA_RAID_GONE 0x55
695#define ARECA_RAID_GOOD 0xaa
696 uint32_t num_resets;
697 uint32_t num_aborts;
698 uint32_t signature;
699 uint32_t firm_request_len;
700 uint32_t firm_numbers_queue;
701 uint32_t firm_sdram_size;
702 uint32_t firm_hd_channels;
703 uint32_t firm_cfg_version;
704 char firm_model[12];
705 char firm_version[20];
706 char device_map[20]; /*21,84-99*/
707 struct work_struct arcmsr_do_message_isr_bh;
708 struct timer_list eternal_timer;
709 unsigned short fw_flag;
710 #define FW_NORMAL 0x0000
711 #define FW_BOG 0x0001
712 #define FW_DEADLOCK 0x0010
713 atomic_t rq_map_token;
714 atomic_t ante_token_value;
715 uint32_t maxOutstanding;
716 int msix_vector_count;
717};/* HW_DEVICE_EXTENSION */
718/*
719*******************************************************************************
720** Command Control Block
721** this CCB length must be 32 bytes boundary
722*******************************************************************************
723*/
724struct CommandControlBlock{
725 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
726 struct list_head list; /*x32: 8byte, x64: 16byte*/
727 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
728 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
729 uint32_t cdb_phyaddr; /*x32: 4byte, x64: 4byte*/
730 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
731 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
732 #define CCB_FLAG_READ 0x0000
733 #define CCB_FLAG_WRITE 0x0001
734 #define CCB_FLAG_ERROR 0x0002
735 #define CCB_FLAG_FLUSHCACHE 0x0004
736 #define CCB_FLAG_MASTER_ABORTED 0x0008
737 uint16_t startdone; /*x32:2byte,x32:2byte*/
738 #define ARCMSR_CCB_DONE 0x0000
739 #define ARCMSR_CCB_START 0x55AA
740 #define ARCMSR_CCB_ABORTED 0xAA55
741 #define ARCMSR_CCB_ILLEGAL 0xFFFF
742 #if BITS_PER_LONG == 64
743 /* ======================512+64 bytes======================== */
744 uint32_t reserved[5]; /*24 byte*/
745 #else
746 /* ======================512+32 bytes======================== */
747 uint32_t reserved; /*8 byte*/
748 #endif
749 /* ======================================================= */
750 struct ARCMSR_CDB arcmsr_cdb;
751};
752/*
753*******************************************************************************
754** ARECA SCSI sense data
755*******************************************************************************
756*/
757struct SENSE_DATA
758{
759 uint8_t ErrorCode:7;
760#define SCSI_SENSE_CURRENT_ERRORS 0x70
761#define SCSI_SENSE_DEFERRED_ERRORS 0x71
762 uint8_t Valid:1;
763 uint8_t SegmentNumber;
764 uint8_t SenseKey:4;
765 uint8_t Reserved:1;
766 uint8_t IncorrectLength:1;
767 uint8_t EndOfMedia:1;
768 uint8_t FileMark:1;
769 uint8_t Information[4];
770 uint8_t AdditionalSenseLength;
771 uint8_t CommandSpecificInformation[4];
772 uint8_t AdditionalSenseCode;
773 uint8_t AdditionalSenseCodeQualifier;
774 uint8_t FieldReplaceableUnitCode;
775 uint8_t SenseKeySpecific[3];
776};
777/*
778*******************************************************************************
779** Outbound Interrupt Status Register - OISR
780*******************************************************************************
781*/
782#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30
783#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10
784#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08
785#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04
786#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02
787#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01
788#define ARCMSR_MU_OUTBOUND_HANDLE_INT \
789 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \
790 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \
791 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \
792 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \
793 |ARCMSR_MU_OUTBOUND_PCI_INT)
794/*
795*******************************************************************************
796** Outbound Interrupt Mask Register - OIMR
797*******************************************************************************
798*/
799#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34
800#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10
801#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08
802#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04
803#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02
804#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01
805#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F
806
807extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *);
808extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *,
809 struct QBUFFER __iomem *);
810extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *);
811extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *);
812extern struct device_attribute *arcmsr_host_attrs[];
813extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *);
814void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb);