Kyle Swenson | 8d8f654 | 2021-03-15 11:02:55 -0600 | [diff] [blame^] | 1 | /* |
| 2 | * Intel PXA25x on-chip full speed USB device controller |
| 3 | * |
| 4 | * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix |
| 5 | * Copyright (C) 2003 David Brownell |
| 6 | * |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __LINUX_USB_GADGET_PXA25X_H |
| 15 | #define __LINUX_USB_GADGET_PXA25X_H |
| 16 | |
| 17 | #include <linux/types.h> |
| 18 | |
| 19 | /*-------------------------------------------------------------------------*/ |
| 20 | |
| 21 | /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ |
| 22 | #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ |
| 23 | #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ |
| 24 | #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ |
| 25 | #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ |
| 26 | #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ |
| 27 | |
| 28 | /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ |
| 29 | #define UDCCFR UDC_RES2 /* UDC Control Function Register */ |
| 30 | #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ |
| 31 | #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ |
| 32 | |
| 33 | /* latest pxa255 errata define new "must be one" bits in UDCCFR */ |
| 34 | #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM)) |
| 35 | |
| 36 | /*-------------------------------------------------------------------------*/ |
| 37 | |
| 38 | struct pxa25x_udc; |
| 39 | |
| 40 | struct pxa25x_ep { |
| 41 | struct usb_ep ep; |
| 42 | struct pxa25x_udc *dev; |
| 43 | |
| 44 | struct list_head queue; |
| 45 | unsigned long pio_irqs; |
| 46 | |
| 47 | unsigned short fifo_size; |
| 48 | u8 bEndpointAddress; |
| 49 | u8 bmAttributes; |
| 50 | |
| 51 | unsigned stopped : 1; |
| 52 | unsigned dma_fixup : 1; |
| 53 | |
| 54 | /* UDCCS = UDC Control/Status for this EP |
| 55 | * UBCR = UDC Byte Count Remaining (contents of OUT fifo) |
| 56 | * UDDR = UDC Endpoint Data Register (the fifo) |
| 57 | * DRCM = DMA Request Channel Map |
| 58 | */ |
| 59 | volatile u32 *reg_udccs; |
| 60 | volatile u32 *reg_ubcr; |
| 61 | volatile u32 *reg_uddr; |
| 62 | }; |
| 63 | |
| 64 | struct pxa25x_request { |
| 65 | struct usb_request req; |
| 66 | struct list_head queue; |
| 67 | }; |
| 68 | |
| 69 | enum ep0_state { |
| 70 | EP0_IDLE, |
| 71 | EP0_IN_DATA_PHASE, |
| 72 | EP0_OUT_DATA_PHASE, |
| 73 | EP0_END_XFER, |
| 74 | EP0_STALL, |
| 75 | }; |
| 76 | |
| 77 | #define EP0_FIFO_SIZE ((unsigned)16) |
| 78 | #define BULK_FIFO_SIZE ((unsigned)64) |
| 79 | #define ISO_FIFO_SIZE ((unsigned)256) |
| 80 | #define INT_FIFO_SIZE ((unsigned)8) |
| 81 | |
| 82 | struct udc_stats { |
| 83 | struct ep0stats { |
| 84 | unsigned long ops; |
| 85 | unsigned long bytes; |
| 86 | } read, write; |
| 87 | unsigned long irqs; |
| 88 | }; |
| 89 | |
| 90 | #ifdef CONFIG_USB_PXA25X_SMALL |
| 91 | /* when memory's tight, SMALL config saves code+data. */ |
| 92 | #define PXA_UDC_NUM_ENDPOINTS 3 |
| 93 | #endif |
| 94 | |
| 95 | #ifndef PXA_UDC_NUM_ENDPOINTS |
| 96 | #define PXA_UDC_NUM_ENDPOINTS 16 |
| 97 | #endif |
| 98 | |
| 99 | struct pxa25x_udc { |
| 100 | struct usb_gadget gadget; |
| 101 | struct usb_gadget_driver *driver; |
| 102 | |
| 103 | enum ep0_state ep0state; |
| 104 | struct udc_stats stats; |
| 105 | unsigned got_irq : 1, |
| 106 | vbus : 1, |
| 107 | pullup : 1, |
| 108 | has_cfr : 1, |
| 109 | req_pending : 1, |
| 110 | req_std : 1, |
| 111 | req_config : 1, |
| 112 | suspended : 1, |
| 113 | active : 1; |
| 114 | |
| 115 | #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200)) |
| 116 | struct timer_list timer; |
| 117 | |
| 118 | struct device *dev; |
| 119 | struct clk *clk; |
| 120 | struct pxa2xx_udc_mach_info *mach; |
| 121 | struct usb_phy *transceiver; |
| 122 | u64 dma_mask; |
| 123 | struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS]; |
| 124 | |
| 125 | #ifdef CONFIG_USB_GADGET_DEBUG_FS |
| 126 | struct dentry *debugfs_udc; |
| 127 | #endif |
| 128 | }; |
| 129 | #define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget)) |
| 130 | |
| 131 | /*-------------------------------------------------------------------------*/ |
| 132 | |
| 133 | #ifdef CONFIG_ARCH_LUBBOCK |
| 134 | #include <mach/lubbock.h> |
| 135 | /* lubbock can also report usb connect/disconnect irqs */ |
| 136 | #endif |
| 137 | |
| 138 | static struct pxa25x_udc *the_controller; |
| 139 | |
| 140 | /*-------------------------------------------------------------------------*/ |
| 141 | |
| 142 | /* |
| 143 | * Debugging support vanishes in non-debug builds. DBG_NORMAL should be |
| 144 | * mostly silent during normal use/testing, with no timing side-effects. |
| 145 | */ |
| 146 | #define DBG_NORMAL 1 /* error paths, device state transitions */ |
| 147 | #define DBG_VERBOSE 2 /* add some success path trace info */ |
| 148 | #define DBG_NOISY 3 /* ... even more: request level */ |
| 149 | #define DBG_VERY_NOISY 4 /* ... even more: packet level */ |
| 150 | |
| 151 | #define DMSG(stuff...) pr_debug("udc: " stuff) |
| 152 | |
| 153 | #ifdef DEBUG |
| 154 | |
| 155 | static const char *state_name[] = { |
| 156 | "EP0_IDLE", |
| 157 | "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", |
| 158 | "EP0_END_XFER", "EP0_STALL" |
| 159 | }; |
| 160 | |
| 161 | #ifdef VERBOSE_DEBUG |
| 162 | # define UDC_DEBUG DBG_VERBOSE |
| 163 | #else |
| 164 | # define UDC_DEBUG DBG_NORMAL |
| 165 | #endif |
| 166 | |
| 167 | static void __maybe_unused |
| 168 | dump_udccr(const char *label) |
| 169 | { |
| 170 | u32 udccr = UDCCR; |
| 171 | DMSG("%s %02X =%s%s%s%s%s%s%s%s\n", |
| 172 | label, udccr, |
| 173 | (udccr & UDCCR_REM) ? " rem" : "", |
| 174 | (udccr & UDCCR_RSTIR) ? " rstir" : "", |
| 175 | (udccr & UDCCR_SRM) ? " srm" : "", |
| 176 | (udccr & UDCCR_SUSIR) ? " susir" : "", |
| 177 | (udccr & UDCCR_RESIR) ? " resir" : "", |
| 178 | (udccr & UDCCR_RSM) ? " rsm" : "", |
| 179 | (udccr & UDCCR_UDA) ? " uda" : "", |
| 180 | (udccr & UDCCR_UDE) ? " ude" : ""); |
| 181 | } |
| 182 | |
| 183 | static void __maybe_unused |
| 184 | dump_udccs0(const char *label) |
| 185 | { |
| 186 | u32 udccs0 = UDCCS0; |
| 187 | |
| 188 | DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n", |
| 189 | label, state_name[the_controller->ep0state], udccs0, |
| 190 | (udccs0 & UDCCS0_SA) ? " sa" : "", |
| 191 | (udccs0 & UDCCS0_RNE) ? " rne" : "", |
| 192 | (udccs0 & UDCCS0_FST) ? " fst" : "", |
| 193 | (udccs0 & UDCCS0_SST) ? " sst" : "", |
| 194 | (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", |
| 195 | (udccs0 & UDCCS0_FTF) ? " ftf" : "", |
| 196 | (udccs0 & UDCCS0_IPR) ? " ipr" : "", |
| 197 | (udccs0 & UDCCS0_OPR) ? " opr" : ""); |
| 198 | } |
| 199 | |
| 200 | static void __maybe_unused |
| 201 | dump_state(struct pxa25x_udc *dev) |
| 202 | { |
| 203 | u32 tmp; |
| 204 | unsigned i; |
| 205 | |
| 206 | DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", |
| 207 | state_name[dev->ep0state], |
| 208 | UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); |
| 209 | dump_udccr("udccr"); |
| 210 | if (dev->has_cfr) { |
| 211 | tmp = UDCCFR; |
| 212 | DMSG("udccfr %02X =%s%s\n", tmp, |
| 213 | (tmp & UDCCFR_AREN) ? " aren" : "", |
| 214 | (tmp & UDCCFR_ACM) ? " acm" : ""); |
| 215 | } |
| 216 | |
| 217 | if (!dev->driver) { |
| 218 | DMSG("no gadget driver bound\n"); |
| 219 | return; |
| 220 | } else |
| 221 | DMSG("ep0 driver '%s'\n", dev->driver->driver.name); |
| 222 | |
| 223 | dump_udccs0 ("udccs0"); |
| 224 | DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n", |
| 225 | dev->stats.write.bytes, dev->stats.write.ops, |
| 226 | dev->stats.read.bytes, dev->stats.read.ops); |
| 227 | |
| 228 | for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { |
| 229 | if (dev->ep[i].ep.desc == NULL) |
| 230 | continue; |
| 231 | DMSG ("udccs%d = %02x\n", i, *dev->ep->reg_udccs); |
| 232 | } |
| 233 | } |
| 234 | |
| 235 | #else |
| 236 | |
| 237 | #define dump_udccr(x) do{}while(0) |
| 238 | #define dump_udccs0(x) do{}while(0) |
| 239 | #define dump_state(x) do{}while(0) |
| 240 | |
| 241 | #define UDC_DEBUG ((unsigned)0) |
| 242 | |
| 243 | #endif |
| 244 | |
| 245 | #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0) |
| 246 | |
| 247 | #define ERR(stuff...) pr_err("udc: " stuff) |
| 248 | #define WARNING(stuff...) pr_warning("udc: " stuff) |
| 249 | #define INFO(stuff...) pr_info("udc: " stuff) |
| 250 | |
| 251 | |
| 252 | #endif /* __LINUX_USB_GADGET_PXA25X_H */ |