wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * tsec.h |
| 3 | * |
| 4 | * Driver for the Motorola Triple Speed Ethernet Controller |
| 5 | * |
| 6 | * This software may be used and distributed according to the |
| 7 | * terms of the GNU Public License, Version 2, incorporated |
| 8 | * herein by reference. |
| 9 | * |
Andy Fleming | 81f481c | 2007-04-23 02:24:28 -0500 | [diff] [blame] | 10 | * Copyright 2004, 2007 Freescale Semiconductor, Inc. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 11 | * (C) Copyright 2003, Motorola, Inc. |
| 12 | * maintained by Xianghua Xiao (x.xiao@motorola.com) |
| 13 | * author Andy Fleming |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #ifndef __TSEC_H |
| 18 | #define __TSEC_H |
| 19 | |
| 20 | #include <net.h> |
Eran Liberty | f046ccd | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 21 | #include <config.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 22 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #ifndef CONFIG_SYS_TSEC1_OFFSET |
| 24 | #define CONFIG_SYS_TSEC1_OFFSET (0x24000) |
Eran Liberty | f046ccd | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 25 | #endif |
| 26 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 27 | #define TSEC_SIZE 0x01000 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 28 | |
Eran Liberty | f046ccd | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 29 | /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 30 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ |
Peter Tyser | 0f89860 | 2009-05-22 17:23:24 -0500 | [diff] [blame^] | 31 | || defined(CONFIG_MPC83xx) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 32 | #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
Eran Liberty | f046ccd | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 33 | #endif |
| 34 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 35 | #define STD_TSEC_INFO(num) \ |
| 36 | { \ |
| 37 | .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ |
| 38 | .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ |
| 39 | .devname = CONFIG_TSEC##num##_NAME, \ |
| 40 | .phyaddr = TSEC##num##_PHY_ADDR, \ |
| 41 | .flags = TSEC##num##_FLAGS \ |
| 42 | } |
| 43 | |
| 44 | #define SET_STD_TSEC_INFO(x, num) \ |
| 45 | { \ |
| 46 | x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ |
| 47 | x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ |
| 48 | x.devname = CONFIG_TSEC##num##_NAME; \ |
| 49 | x.phyaddr = TSEC##num##_PHY_ADDR; \ |
| 50 | x.flags = TSEC##num##_FLAGS;\ |
| 51 | } |
| 52 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 53 | #define MAC_ADDR_LEN 6 |
| 54 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 55 | /* #define TSEC_TIMEOUT 1000000 */ |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 56 | #define TSEC_TIMEOUT 1000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 57 | #define TOUT_LOOP 1000000 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 58 | |
Stefan Roese | 5810dc3 | 2005-09-21 18:20:22 +0200 | [diff] [blame] | 59 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ |
| 60 | |
Andy Fleming | 2abe361 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 61 | /* TBI register addresses */ |
| 62 | #define TBI_CR 0x00 |
| 63 | #define TBI_SR 0x01 |
| 64 | #define TBI_ANA 0x04 |
| 65 | #define TBI_ANLPBPA 0x05 |
| 66 | #define TBI_ANEX 0x06 |
| 67 | #define TBI_TBICON 0x11 |
| 68 | |
| 69 | /* TBI MDIO register bit fields*/ |
| 70 | #define TBICON_CLK_SELECT 0x0020 |
| 71 | #define TBIANA_ASYMMETRIC_PAUSE 0x0100 |
| 72 | #define TBIANA_SYMMETRIC_PAUSE 0x0080 |
| 73 | #define TBIANA_HALF_DUPLEX 0x0040 |
| 74 | #define TBIANA_FULL_DUPLEX 0x0020 |
| 75 | #define TBICR_PHY_RESET 0x8000 |
| 76 | #define TBICR_ANEG_ENABLE 0x1000 |
| 77 | #define TBICR_RESTART_ANEG 0x0200 |
| 78 | #define TBICR_FULL_DUPLEX 0x0100 |
| 79 | #define TBICR_SPEED1_SET 0x0040 |
| 80 | |
| 81 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 82 | /* MAC register bits */ |
| 83 | #define MACCFG1_SOFT_RESET 0x80000000 |
| 84 | #define MACCFG1_RESET_RX_MC 0x00080000 |
| 85 | #define MACCFG1_RESET_TX_MC 0x00040000 |
| 86 | #define MACCFG1_RESET_RX_FUN 0x00020000 |
| 87 | #define MACCFG1_RESET_TX_FUN 0x00010000 |
| 88 | #define MACCFG1_LOOPBACK 0x00000100 |
| 89 | #define MACCFG1_RX_FLOW 0x00000020 |
| 90 | #define MACCFG1_TX_FLOW 0x00000010 |
| 91 | #define MACCFG1_SYNCD_RX_EN 0x00000008 |
| 92 | #define MACCFG1_RX_EN 0x00000004 |
| 93 | #define MACCFG1_SYNCD_TX_EN 0x00000002 |
| 94 | #define MACCFG1_TX_EN 0x00000001 |
| 95 | |
| 96 | #define MACCFG2_INIT_SETTINGS 0x00007205 |
| 97 | #define MACCFG2_FULL_DUPLEX 0x00000001 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 98 | #define MACCFG2_IF 0x00000300 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 99 | #define MACCFG2_GMII 0x00000200 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 100 | #define MACCFG2_MII 0x00000100 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 101 | |
| 102 | #define ECNTRL_INIT_SETTINGS 0x00001000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 103 | #define ECNTRL_TBI_MODE 0x00000020 |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 104 | #define ECNTRL_R100 0x00000008 |
Andy Fleming | 81f481c | 2007-04-23 02:24:28 -0500 | [diff] [blame] | 105 | #define ECNTRL_SGMII_MODE 0x00000002 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 106 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 107 | #define miim_end -2 |
| 108 | #define miim_read -1 |
| 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #ifndef CONFIG_SYS_TBIPA_VALUE |
| 111 | #define CONFIG_SYS_TBIPA_VALUE 0x1f |
Joe Hamman | dcb84b7 | 2007-08-09 09:08:18 -0500 | [diff] [blame] | 112 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 113 | #define MIIMCFG_INIT_VALUE 0x00000003 |
| 114 | #define MIIMCFG_RESET 0x80000000 |
| 115 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 116 | #define MIIMIND_BUSY 0x00000001 |
| 117 | #define MIIMIND_NOTVALID 0x00000004 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 118 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 119 | #define MIIM_CONTROL 0x00 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 120 | #define MIIM_CONTROL_RESET 0x00009140 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 121 | #define MIIM_CONTROL_INIT 0x00001140 |
| 122 | #define MIIM_CONTROL_RESTART 0x00001340 |
| 123 | #define MIIM_ANEN 0x00001000 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 124 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 125 | #define MIIM_CR 0x00 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 126 | #define MIIM_CR_RST 0x00008000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 127 | #define MIIM_CR_INIT 0x00001000 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 128 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 129 | #define MIIM_STATUS 0x1 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 130 | #define MIIM_STATUS_AN_DONE 0x00000020 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 131 | #define MIIM_STATUS_LINK 0x0004 |
Stefan Roese | 5810dc3 | 2005-09-21 18:20:22 +0200 | [diff] [blame] | 132 | #define PHY_BMSR_AUTN_ABLE 0x0008 |
| 133 | #define PHY_BMSR_AUTN_COMP 0x0020 |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 134 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 135 | #define MIIM_PHYIR1 0x2 |
| 136 | #define MIIM_PHYIR2 0x3 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 137 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 138 | #define MIIM_ANAR 0x4 |
| 139 | #define MIIM_ANAR_INIT 0x1e1 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 140 | |
| 141 | #define MIIM_TBI_ANLPBPA 0x5 |
| 142 | #define MIIM_TBI_ANLPBPA_HALF 0x00000040 |
| 143 | #define MIIM_TBI_ANLPBPA_FULL 0x00000020 |
| 144 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 145 | #define MIIM_TBI_ANEX 0x6 |
| 146 | #define MIIM_TBI_ANEX_NP 0x00000004 |
| 147 | #define MIIM_TBI_ANEX_PRX 0x00000002 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 148 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 149 | #define MIIM_GBIT_CONTROL 0x9 |
| 150 | #define MIIM_GBIT_CONTROL_INIT 0xe00 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 151 | |
Andre Schwarz | 9acde12 | 2008-04-29 19:18:32 +0200 | [diff] [blame] | 152 | #define MIIM_EXT_PAGE_ACCESS 0x1f |
| 153 | |
Paul Gortmaker | 91e2576 | 2007-01-16 11:38:14 -0500 | [diff] [blame] | 154 | /* Broadcom BCM54xx -- taken from linux sungem_phy */ |
| 155 | #define MIIM_BCM54xx_AUXSTATUS 0x19 |
| 156 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 |
| 157 | #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 |
| 158 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 159 | /* Cicada Auxiliary Control/Status Register */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 160 | #define MIIM_CIS8201_AUX_CONSTAT 0x1c |
| 161 | #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 |
| 162 | #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 |
| 163 | #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 |
| 164 | #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 |
| 165 | #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 166 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 167 | /* Cicada Extended Control Register 1 */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 168 | #define MIIM_CIS8201_EXT_CON1 0x17 |
| 169 | #define MIIM_CIS8201_EXTCON1_INIT 0x0000 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 170 | |
| 171 | /* Cicada 8204 Extended PHY Control Register 1 */ |
| 172 | #define MIIM_CIS8204_EPHY_CON 0x17 |
| 173 | #define MIIM_CIS8204_EPHYCON_INIT 0x0006 |
Wolfgang Denk | 0346983 | 2006-03-12 18:09:47 +0100 | [diff] [blame] | 174 | #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 175 | |
| 176 | /* Cicada 8204 Serial LED Control Register */ |
| 177 | #define MIIM_CIS8204_SLED_CON 0x1b |
| 178 | #define MIIM_CIS8204_SLEDCON_INIT 0x1115 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 179 | |
| 180 | #define MIIM_GBIT_CON 0x09 |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 181 | #define MIIM_GBIT_CON_ADVERT 0x0e00 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 182 | |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 183 | /* Entry for Vitesse VSC8244 regs starts here */ |
| 184 | /* Vitesse VSC8244 Auxiliary Control/Status Register */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 185 | #define MIIM_VSC8244_AUX_CONSTAT 0x1c |
| 186 | #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 |
| 187 | #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 |
| 188 | #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 |
| 189 | #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 |
| 190 | #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 |
| 191 | #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 192 | |
| 193 | /* Vitesse VSC8244 Extended PHY Control Register 1 */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 194 | #define MIIM_VSC8244_EPHY_CON 0x17 |
| 195 | #define MIIM_VSC8244_EPHYCON_INIT 0x0006 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 196 | |
| 197 | /* Vitesse VSC8244 Serial LED Control Register */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 198 | #define MIIM_VSC8244_LED_CON 0x1b |
| 199 | #define MIIM_VSC8244_LEDCON_INIT 0xF011 |
Jon Loeliger | debb735 | 2006-04-26 17:58:56 -0500 | [diff] [blame] | 200 | |
Tor Krill | 2d934ea | 2008-03-28 15:29:45 +0100 | [diff] [blame] | 201 | /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ |
| 202 | /* Vitesse VSC8601 Extended PHY Control Register 1 */ |
Andre Schwarz | 9acde12 | 2008-04-29 19:18:32 +0200 | [diff] [blame] | 203 | #define MIIM_VSC8601_EPHY_CON 0x17 |
Tor Krill | 2d934ea | 2008-03-28 15:29:45 +0100 | [diff] [blame] | 204 | #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 |
Andre Schwarz | 9acde12 | 2008-04-29 19:18:32 +0200 | [diff] [blame] | 205 | #define MIIM_VSC8601_SKEW_CTRL 0x1c |
Tor Krill | 2d934ea | 2008-03-28 15:29:45 +0100 | [diff] [blame] | 206 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 207 | /* 88E1011 PHY Status Register */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 208 | #define MIIM_88E1011_PHY_STATUS 0x11 |
| 209 | #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 |
| 210 | #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 |
| 211 | #define MIIM_88E1011_PHYSTAT_100 0x4000 |
| 212 | #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 213 | #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 |
| 214 | #define MIIM_88E1011_PHYSTAT_LINK 0x0400 |
| 215 | |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 216 | #define MIIM_88E1011_PHY_SCR 0x10 |
| 217 | #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 |
| 218 | |
| 219 | /* 88E1111 PHY LED Control Register */ |
Andre Schwarz | 9acde12 | 2008-04-29 19:18:32 +0200 | [diff] [blame] | 220 | #define MIIM_88E1111_PHY_LED_CONTROL 24 |
| 221 | #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 |
| 222 | #define MIIM_88E1111_PHY_LED_COMBINE 0x411C |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 223 | |
Sergei Poselenov | d23dc39 | 2008-06-06 15:52:44 +0200 | [diff] [blame] | 224 | /* 88E1121 PHY LED Control Register */ |
| 225 | #define MIIM_88E1121_PHY_LED_CTRL 16 |
| 226 | #define MIIM_88E1121_PHY_LED_PAGE 3 |
| 227 | #define MIIM_88E1121_PHY_LED_DEF 0x0030 |
| 228 | |
Anatolij Gustschin | 23afaba | 2008-12-02 10:31:04 +0100 | [diff] [blame] | 229 | /* 88E1121 PHY IRQ Enable/Status Register */ |
| 230 | #define MIIM_88E1121_PHY_IRQ_EN 18 |
| 231 | #define MIIM_88E1121_PHY_IRQ_STATUS 19 |
| 232 | |
Sergei Poselenov | d23dc39 | 2008-06-06 15:52:44 +0200 | [diff] [blame] | 233 | #define MIIM_88E1121_PHY_PAGE 22 |
| 234 | |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 235 | /* 88E1145 Extended PHY Specific Control Register */ |
| 236 | #define MIIM_88E1145_PHY_EXT_CR 20 |
| 237 | #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 |
| 238 | #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 |
| 239 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 240 | #define MIIM_88E1145_PHY_PAGE 29 |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 241 | #define MIIM_88E1145_PHY_CAL_OV 30 |
| 242 | |
Dave Liu | 18ee320 | 2008-01-11 18:45:28 +0800 | [diff] [blame] | 243 | /* RTL8211B PHY Status Register */ |
| 244 | #define MIIM_RTL8211B_PHY_STATUS 0x11 |
| 245 | #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 |
| 246 | #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 |
| 247 | #define MIIM_RTL8211B_PHYSTAT_100 0x4000 |
| 248 | #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 |
| 249 | #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 |
| 250 | #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 |
Andy Fleming | 09f3e09 | 2006-09-13 10:34:18 -0500 | [diff] [blame] | 251 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 252 | /* DM9161 Control register values */ |
| 253 | #define MIIM_DM9161_CR_STOP 0x0400 |
| 254 | #define MIIM_DM9161_CR_RSTAN 0x1200 |
| 255 | |
| 256 | #define MIIM_DM9161_SCR 0x10 |
| 257 | #define MIIM_DM9161_SCR_INIT 0x0610 |
| 258 | |
| 259 | /* DM9161 Specified Configuration and Status Register */ |
| 260 | #define MIIM_DM9161_SCSR 0x11 |
| 261 | #define MIIM_DM9161_SCSR_100F 0x8000 |
| 262 | #define MIIM_DM9161_SCSR_100H 0x4000 |
| 263 | #define MIIM_DM9161_SCSR_10F 0x2000 |
| 264 | #define MIIM_DM9161_SCSR_10H 0x1000 |
| 265 | |
| 266 | /* DM9161 10BT Configuration/Status */ |
| 267 | #define MIIM_DM9161_10BTCSR 0x12 |
| 268 | #define MIIM_DM9161_10BTCSR_INIT 0x7800 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 269 | |
wdenk | 3dd7f0f | 2005-04-04 23:43:44 +0000 | [diff] [blame] | 270 | /* LXT971 Status 2 registers */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 271 | #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ |
Wolfgang Denk | d8169c9 | 2006-03-12 18:06:37 +0100 | [diff] [blame] | 272 | #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 273 | #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ |
| 274 | #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ |
| 275 | #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ |
| 276 | #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ |
wdenk | 3dd7f0f | 2005-04-04 23:43:44 +0000 | [diff] [blame] | 277 | |
Wolfgang Denk | be5048f | 2006-03-12 22:50:55 +0100 | [diff] [blame] | 278 | /* DP83865 Control register values */ |
| 279 | #define MIIM_DP83865_CR_INIT 0x9200 |
| 280 | |
| 281 | /* DP83865 Link and Auto-Neg Status Register */ |
| 282 | #define MIIM_DP83865_LANR 0x11 |
| 283 | #define MIIM_DP83865_SPD_MASK 0x0018 |
| 284 | #define MIIM_DP83865_SPD_1000 0x0010 |
| 285 | #define MIIM_DP83865_SPD_100 0x0008 |
| 286 | #define MIIM_DP83865_DPX_FULL 0x0002 |
| 287 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 288 | #define MIIM_READ_COMMAND 0x00000001 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 289 | |
| 290 | #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN |
| 291 | |
| 292 | #define MINFLR_INIT_SETTINGS 0x00000040 |
| 293 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 294 | #define DMACTRL_INIT_SETTINGS 0x000000c3 |
| 295 | #define DMACTRL_GRS 0x00000010 |
| 296 | #define DMACTRL_GTS 0x00000008 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 297 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 298 | #define TSTAT_CLEAR_THALT 0x80000000 |
| 299 | #define RSTAT_CLEAR_RHALT 0x00800000 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 300 | |
wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 301 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 302 | #define IEVENT_INIT_CLEAR 0xffffffff |
| 303 | #define IEVENT_BABR 0x80000000 |
| 304 | #define IEVENT_RXC 0x40000000 |
| 305 | #define IEVENT_BSY 0x20000000 |
| 306 | #define IEVENT_EBERR 0x10000000 |
| 307 | #define IEVENT_MSRO 0x04000000 |
| 308 | #define IEVENT_GTSC 0x02000000 |
| 309 | #define IEVENT_BABT 0x01000000 |
| 310 | #define IEVENT_TXC 0x00800000 |
| 311 | #define IEVENT_TXE 0x00400000 |
| 312 | #define IEVENT_TXB 0x00200000 |
| 313 | #define IEVENT_TXF 0x00100000 |
| 314 | #define IEVENT_IE 0x00080000 |
| 315 | #define IEVENT_LC 0x00040000 |
| 316 | #define IEVENT_CRL 0x00020000 |
| 317 | #define IEVENT_XFUN 0x00010000 |
| 318 | #define IEVENT_RXB0 0x00008000 |
| 319 | #define IEVENT_GRSC 0x00000100 |
| 320 | #define IEVENT_RXF0 0x00000080 |
| 321 | |
| 322 | #define IMASK_INIT_CLEAR 0x00000000 |
| 323 | #define IMASK_TXEEN 0x00400000 |
| 324 | #define IMASK_TXBEN 0x00200000 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 325 | #define IMASK_TXFEN 0x00100000 |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 326 | #define IMASK_RXFEN0 0x00000080 |
| 327 | |
| 328 | |
| 329 | /* Default Attribute fields */ |
| 330 | #define ATTR_INIT_SETTINGS 0x000000c0 |
| 331 | #define ATTRELI_INIT_SETTINGS 0x00000000 |
| 332 | |
| 333 | |
| 334 | /* TxBD status field bits */ |
| 335 | #define TXBD_READY 0x8000 |
| 336 | #define TXBD_PADCRC 0x4000 |
| 337 | #define TXBD_WRAP 0x2000 |
| 338 | #define TXBD_INTERRUPT 0x1000 |
| 339 | #define TXBD_LAST 0x0800 |
| 340 | #define TXBD_CRC 0x0400 |
| 341 | #define TXBD_DEF 0x0200 |
| 342 | #define TXBD_HUGEFRAME 0x0080 |
| 343 | #define TXBD_LATECOLLISION 0x0080 |
| 344 | #define TXBD_RETRYLIMIT 0x0040 |
| 345 | #define TXBD_RETRYCOUNTMASK 0x003c |
| 346 | #define TXBD_UNDERRUN 0x0002 |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 347 | #define TXBD_STATS 0x03ff |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 348 | |
| 349 | /* RxBD status field bits */ |
| 350 | #define RXBD_EMPTY 0x8000 |
| 351 | #define RXBD_RO1 0x4000 |
| 352 | #define RXBD_WRAP 0x2000 |
| 353 | #define RXBD_INTERRUPT 0x1000 |
| 354 | #define RXBD_LAST 0x0800 |
| 355 | #define RXBD_FIRST 0x0400 |
| 356 | #define RXBD_MISS 0x0100 |
| 357 | #define RXBD_BROADCAST 0x0080 |
| 358 | #define RXBD_MULTICAST 0x0040 |
| 359 | #define RXBD_LARGE 0x0020 |
| 360 | #define RXBD_NONOCTET 0x0010 |
| 361 | #define RXBD_SHORT 0x0008 |
| 362 | #define RXBD_CRCERR 0x0004 |
| 363 | #define RXBD_OVERRUN 0x0002 |
| 364 | #define RXBD_TRUNCATED 0x0001 |
| 365 | #define RXBD_STATS 0x003f |
| 366 | |
| 367 | typedef struct txbd8 |
| 368 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 369 | ushort status; /* Status Fields */ |
| 370 | ushort length; /* Buffer length */ |
| 371 | uint bufPtr; /* Buffer Pointer */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 372 | } txbd8_t; |
| 373 | |
| 374 | typedef struct rxbd8 |
| 375 | { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 376 | ushort status; /* Status Fields */ |
| 377 | ushort length; /* Buffer Length */ |
| 378 | uint bufPtr; /* Buffer Pointer */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 379 | } rxbd8_t; |
| 380 | |
| 381 | typedef struct rmon_mib |
| 382 | { |
| 383 | /* Transmit and Receive Counters */ |
| 384 | uint tr64; /* Transmit and Receive 64-byte Frame Counter */ |
| 385 | uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ |
| 386 | uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ |
| 387 | uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ |
| 388 | uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ |
| 389 | uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ |
| 390 | uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ |
| 391 | /* Receive Counters */ |
| 392 | uint rbyt; /* Receive Byte Counter */ |
| 393 | uint rpkt; /* Receive Packet Counter */ |
| 394 | uint rfcs; /* Receive FCS Error Counter */ |
| 395 | uint rmca; /* Receive Multicast Packet (Counter) */ |
| 396 | uint rbca; /* Receive Broadcast Packet */ |
| 397 | uint rxcf; /* Receive Control Frame Packet */ |
| 398 | uint rxpf; /* Receive Pause Frame Packet */ |
| 399 | uint rxuo; /* Receive Unknown OP Code */ |
| 400 | uint raln; /* Receive Alignment Error */ |
| 401 | uint rflr; /* Receive Frame Length Error */ |
| 402 | uint rcde; /* Receive Code Error */ |
| 403 | uint rcse; /* Receive Carrier Sense Error */ |
| 404 | uint rund; /* Receive Undersize Packet */ |
| 405 | uint rovr; /* Receive Oversize Packet */ |
| 406 | uint rfrg; /* Receive Fragments */ |
| 407 | uint rjbr; /* Receive Jabber */ |
| 408 | uint rdrp; /* Receive Drop */ |
| 409 | /* Transmit Counters */ |
| 410 | uint tbyt; /* Transmit Byte Counter */ |
| 411 | uint tpkt; /* Transmit Packet */ |
| 412 | uint tmca; /* Transmit Multicast Packet */ |
| 413 | uint tbca; /* Transmit Broadcast Packet */ |
| 414 | uint txpf; /* Transmit Pause Control Frame */ |
| 415 | uint tdfr; /* Transmit Deferral Packet */ |
| 416 | uint tedf; /* Transmit Excessive Deferral Packet */ |
| 417 | uint tscl; /* Transmit Single Collision Packet */ |
| 418 | /* (0x2_n700) */ |
| 419 | uint tmcl; /* Transmit Multiple Collision Packet */ |
| 420 | uint tlcl; /* Transmit Late Collision Packet */ |
| 421 | uint txcl; /* Transmit Excessive Collision Packet */ |
| 422 | uint tncl; /* Transmit Total Collision */ |
| 423 | |
| 424 | uint res2; |
| 425 | |
| 426 | uint tdrp; /* Transmit Drop Frame */ |
| 427 | uint tjbr; /* Transmit Jabber Frame */ |
| 428 | uint tfcs; /* Transmit FCS Error */ |
| 429 | uint txcf; /* Transmit Control Frame */ |
| 430 | uint tovr; /* Transmit Oversize Frame */ |
| 431 | uint tund; /* Transmit Undersize Frame */ |
| 432 | uint tfrg; /* Transmit Fragments Frame */ |
| 433 | /* General Registers */ |
| 434 | uint car1; /* Carry Register One */ |
| 435 | uint car2; /* Carry Register Two */ |
| 436 | uint cam1; /* Carry Register One Mask */ |
| 437 | uint cam2; /* Carry Register Two Mask */ |
| 438 | } rmon_mib_t; |
| 439 | |
| 440 | typedef struct tsec_hash_regs |
| 441 | { |
| 442 | uint iaddr0; /* Individual Address Register 0 */ |
| 443 | uint iaddr1; /* Individual Address Register 1 */ |
| 444 | uint iaddr2; /* Individual Address Register 2 */ |
| 445 | uint iaddr3; /* Individual Address Register 3 */ |
| 446 | uint iaddr4; /* Individual Address Register 4 */ |
| 447 | uint iaddr5; /* Individual Address Register 5 */ |
| 448 | uint iaddr6; /* Individual Address Register 6 */ |
| 449 | uint iaddr7; /* Individual Address Register 7 */ |
| 450 | uint res1[24]; |
| 451 | uint gaddr0; /* Group Address Register 0 */ |
| 452 | uint gaddr1; /* Group Address Register 1 */ |
| 453 | uint gaddr2; /* Group Address Register 2 */ |
| 454 | uint gaddr3; /* Group Address Register 3 */ |
| 455 | uint gaddr4; /* Group Address Register 4 */ |
| 456 | uint gaddr5; /* Group Address Register 5 */ |
| 457 | uint gaddr6; /* Group Address Register 6 */ |
| 458 | uint gaddr7; /* Group Address Register 7 */ |
| 459 | uint res2[24]; |
| 460 | } tsec_hash_t; |
| 461 | |
| 462 | typedef struct tsec |
| 463 | { |
| 464 | /* General Control and Status Registers (0x2_n000) */ |
| 465 | uint res000[4]; |
| 466 | |
| 467 | uint ievent; /* Interrupt Event */ |
| 468 | uint imask; /* Interrupt Mask */ |
| 469 | uint edis; /* Error Disabled */ |
| 470 | uint res01c; |
| 471 | uint ecntrl; /* Ethernet Control */ |
| 472 | uint minflr; /* Minimum Frame Length */ |
| 473 | uint ptv; /* Pause Time Value */ |
| 474 | uint dmactrl; /* DMA Control */ |
| 475 | uint tbipa; /* TBI PHY Address */ |
| 476 | |
| 477 | uint res034[3]; |
| 478 | uint res040[48]; |
| 479 | |
| 480 | /* Transmit Control and Status Registers (0x2_n100) */ |
| 481 | uint tctrl; /* Transmit Control */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 482 | uint tstat; /* Transmit Status */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 483 | uint res108; |
| 484 | uint tbdlen; /* Tx BD Data Length */ |
| 485 | uint res110[5]; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 486 | uint ctbptr; /* Current TxBD Pointer */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 487 | uint res128[23]; |
| 488 | uint tbptr; /* TxBD Pointer */ |
| 489 | uint res188[30]; |
| 490 | /* (0x2_n200) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 491 | uint res200; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 492 | uint tbase; /* TxBD Base Address */ |
| 493 | uint res208[42]; |
| 494 | uint ostbd; /* Out of Sequence TxBD */ |
| 495 | uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 496 | uint res2b8[18]; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 497 | |
| 498 | /* Receive Control and Status Registers (0x2_n300) */ |
| 499 | uint rctrl; /* Receive Control */ |
| 500 | uint rstat; /* Receive Status */ |
| 501 | uint res308; |
| 502 | uint rbdlen; /* RxBD Data Length */ |
| 503 | uint res310[4]; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 504 | uint res320; |
| 505 | uint crbptr; /* Current Receive Buffer Pointer */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 506 | uint res328[6]; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 507 | uint mrblr; /* Maximum Receive Buffer Length */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 508 | uint res344[16]; |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 509 | uint rbptr; /* RxBD Pointer */ |
| 510 | uint res388[30]; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 511 | /* (0x2_n400) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 512 | uint res400; |
| 513 | uint rbase; /* RxBD Base Address */ |
| 514 | uint res408[62]; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 515 | |
| 516 | /* MAC Registers (0x2_n500) */ |
| 517 | uint maccfg1; /* MAC Configuration #1 */ |
| 518 | uint maccfg2; /* MAC Configuration #2 */ |
| 519 | uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ |
| 520 | uint hafdup; /* Half-duplex */ |
| 521 | uint maxfrm; /* Maximum Frame */ |
| 522 | uint res514; |
| 523 | uint res518; |
| 524 | |
| 525 | uint res51c; |
| 526 | |
| 527 | uint miimcfg; /* MII Management: Configuration */ |
| 528 | uint miimcom; /* MII Management: Command */ |
| 529 | uint miimadd; /* MII Management: Address */ |
| 530 | uint miimcon; /* MII Management: Control */ |
| 531 | uint miimstat; /* MII Management: Status */ |
| 532 | uint miimind; /* MII Management: Indicators */ |
| 533 | |
| 534 | uint res538; |
| 535 | |
| 536 | uint ifstat; /* Interface Status */ |
| 537 | uint macstnaddr1; /* Station Address, part 1 */ |
| 538 | uint macstnaddr2; /* Station Address, part 2 */ |
| 539 | uint res548[46]; |
| 540 | |
| 541 | /* (0x2_n600) */ |
| 542 | uint res600[32]; |
| 543 | |
| 544 | /* RMON MIB Registers (0x2_n680-0x2_n73c) */ |
| 545 | rmon_mib_t rmon; |
| 546 | uint res740[48]; |
| 547 | |
| 548 | /* Hash Function Registers (0x2_n800) */ |
| 549 | tsec_hash_t hash; |
| 550 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 551 | uint res900[128]; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 552 | |
| 553 | /* Pattern Registers (0x2_nb00) */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 554 | uint resb00[62]; |
| 555 | uint attr; /* Default Attribute Register */ |
| 556 | uint attreli; /* Default Attribute Extract Length and Index */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 557 | |
| 558 | /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ |
| 559 | uint resc00[256]; |
| 560 | } tsec_t; |
| 561 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 562 | #define TSEC_GIGABIT (1) |
| 563 | |
| 564 | /* This flag currently only has |
| 565 | * meaning if we're using the eTSEC */ |
Andy Fleming | 2abe361 | 2008-08-31 16:33:27 -0500 | [diff] [blame] | 566 | #define TSEC_REDUCED (1 << 1) |
| 567 | |
| 568 | #define TSEC_SGMII (1 << 2) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 569 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 570 | struct tsec_private { |
| 571 | volatile tsec_t *regs; |
| 572 | volatile tsec_t *phyregs; |
| 573 | struct phy_info *phyinfo; |
| 574 | uint phyaddr; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 575 | u32 flags; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 576 | uint link; |
| 577 | uint duplexity; |
| 578 | uint speed; |
| 579 | }; |
| 580 | |
| 581 | |
| 582 | /* |
| 583 | * struct phy_cmd: A command for reading or writing a PHY register |
| 584 | * |
| 585 | * mii_reg: The register to read or write |
| 586 | * |
| 587 | * mii_data: For writes, the value to put in the register. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 588 | * A value of -1 indicates this is a read. |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 589 | * |
| 590 | * funct: A function pointer which is invoked for each command. |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 591 | * For reads, this function will be passed the value read |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 592 | * from the PHY, and process it. |
| 593 | * For writes, the result of this function will be written |
| 594 | * to the PHY register |
| 595 | */ |
| 596 | struct phy_cmd { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 597 | uint mii_reg; |
| 598 | uint mii_data; |
| 599 | uint (*funct) (uint mii_reg, struct tsec_private * priv); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 600 | }; |
| 601 | |
| 602 | /* struct phy_info: a structure which defines attributes for a PHY |
| 603 | * |
| 604 | * id will contain a number which represents the PHY. During |
| 605 | * startup, the driver will poll the PHY to find out what its |
| 606 | * UID--as defined by registers 2 and 3--is. The 32-bit result |
| 607 | * gotten from the PHY will be shifted right by "shift" bits to |
| 608 | * discard any bits which may change based on revision numbers |
| 609 | * unimportant to functionality |
| 610 | * |
| 611 | * The struct phy_cmd entries represent pointers to an arrays of |
| 612 | * commands which tell the driver what to do to the PHY. |
| 613 | */ |
| 614 | struct phy_info { |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 615 | uint id; |
| 616 | char *name; |
| 617 | uint shift; |
| 618 | /* Called to configure the PHY, and modify the controller |
| 619 | * based on the results */ |
| 620 | struct phy_cmd *config; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 621 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 622 | /* Called when starting up the controller */ |
| 623 | struct phy_cmd *startup; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 624 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 625 | /* Called when bringing down the controller */ |
| 626 | struct phy_cmd *shutdown; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 627 | }; |
| 628 | |
Andy Fleming | dd3d1f5 | 2008-08-31 16:33:25 -0500 | [diff] [blame] | 629 | struct tsec_info_struct { |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 630 | tsec_t *regs; |
| 631 | tsec_t *miiregs; |
| 632 | char *devname; |
Andy Fleming | dd3d1f5 | 2008-08-31 16:33:25 -0500 | [diff] [blame] | 633 | unsigned int phyaddr; |
| 634 | u32 flags; |
Andy Fleming | dd3d1f5 | 2008-08-31 16:33:25 -0500 | [diff] [blame] | 635 | }; |
| 636 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 637 | int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); |
| 638 | int tsec_standard_init(bd_t *bis); |
| 639 | int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); |
| 640 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 641 | #endif /* __TSEC_H */ |