| Prabhu Jayakumar | a700195 | 2016-11-14 18:58:54 +0530 | [diff] [blame] | 1 | /* |
| Prabhu Jayakumar | 4f520fb | 2017-01-09 17:05:45 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. |
| Prabhu Jayakumar | a700195 | 2016-11-14 18:58:54 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _QCA953X_H |
| 16 | #define _QCA953X_H |
| 17 | |
| 18 | #ifndef __ASSEMBLY__ |
| 19 | #include <asm/mipsregs.h> |
| 20 | #include <asm/addrspace.h> |
| 21 | #include <asm/types.h> |
| 22 | #include <linux/types.h> |
| 23 | #endif /* __ASSEMBLY__ */ |
| 24 | |
| 25 | #undef is_qca953x |
| 26 | #undef is_hb |
| 27 | |
| 28 | #define is_qca953x() (1) |
| 29 | #define is_hb() (1) |
| 30 | |
| 31 | |
| 32 | #define CPU_PLL_CONFIG_UPDATING_MSB 31 |
| 33 | #define CPU_PLL_CONFIG_UPDATING_LSB 31 |
| 34 | #define CPU_PLL_CONFIG_UPDATING_MASK 0x80000000 |
| 35 | #define CPU_PLL_CONFIG_UPDATING_GET(x) (((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB) |
| 36 | #define CPU_PLL_CONFIG_UPDATING_SET(x) (((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK) |
| 37 | #define CPU_PLL_CONFIG_UPDATING_RESET 0x1 // 1 |
| 38 | #define CPU_PLL_CONFIG_PLLPWD_MSB 30 |
| 39 | #define CPU_PLL_CONFIG_PLLPWD_LSB 30 |
| 40 | #define CPU_PLL_CONFIG_PLLPWD_MASK 0x40000000 |
| 41 | #define CPU_PLL_CONFIG_PLLPWD_GET(x) (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB) |
| 42 | #define CPU_PLL_CONFIG_PLLPWD_SET(x) (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK) |
| 43 | #define CPU_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 |
| 44 | #define CPU_PLL_CONFIG_SPARE_MSB 29 |
| 45 | #define CPU_PLL_CONFIG_SPARE_LSB 22 |
| 46 | #define CPU_PLL_CONFIG_SPARE_MASK 0x3fc00000 |
| 47 | #define CPU_PLL_CONFIG_SPARE_GET(x) (((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB) |
| 48 | #define CPU_PLL_CONFIG_SPARE_SET(x) (((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK) |
| 49 | #define CPU_PLL_CONFIG_SPARE_RESET 0x0 // 0 |
| 50 | #define CPU_PLL_CONFIG_OUTDIV_MSB 21 |
| 51 | #define CPU_PLL_CONFIG_OUTDIV_LSB 19 |
| 52 | #define CPU_PLL_CONFIG_OUTDIV_MASK 0x00380000 |
| 53 | #define CPU_PLL_CONFIG_OUTDIV_GET(x) (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB) |
| 54 | #define CPU_PLL_CONFIG_OUTDIV_SET(x) (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK) |
| 55 | #define CPU_PLL_CONFIG_OUTDIV_RESET 0x0 // 0 |
| 56 | #define CPU_PLL_CONFIG_RANGE_MSB 18 |
| 57 | #define CPU_PLL_CONFIG_RANGE_LSB 17 |
| 58 | #define CPU_PLL_CONFIG_RANGE_MASK 0x00060000 |
| 59 | #define CPU_PLL_CONFIG_RANGE_GET(x) (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB) |
| 60 | #define CPU_PLL_CONFIG_RANGE_SET(x) (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK) |
| 61 | #define CPU_PLL_CONFIG_RANGE_RESET 0x3 // 3 |
| 62 | #define CPU_PLL_CONFIG_REFDIV_MSB 16 |
| 63 | #define CPU_PLL_CONFIG_REFDIV_LSB 12 |
| 64 | #define CPU_PLL_CONFIG_REFDIV_MASK 0x0001f000 |
| 65 | #define CPU_PLL_CONFIG_REFDIV_GET(x) (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB) |
| 66 | #define CPU_PLL_CONFIG_REFDIV_SET(x) (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK) |
| 67 | #define CPU_PLL_CONFIG_REFDIV_RESET 0x2 // 2 |
| 68 | #define CPU_PLL_CONFIG_NINT_MSB 11 |
| 69 | #define CPU_PLL_CONFIG_NINT_LSB 6 |
| 70 | #define CPU_PLL_CONFIG_NINT_MASK 0x00000fc0 |
| 71 | #define CPU_PLL_CONFIG_NINT_GET(x) (((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB) |
| 72 | #define CPU_PLL_CONFIG_NINT_SET(x) (((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK) |
| 73 | #define CPU_PLL_CONFIG_NINT_RESET 0x14 // 20 |
| 74 | #define CPU_PLL_CONFIG_NFRAC_MSB 5 |
| 75 | #define CPU_PLL_CONFIG_NFRAC_LSB 0 |
| 76 | #define CPU_PLL_CONFIG_NFRAC_MASK 0x0000003f |
| 77 | #define CPU_PLL_CONFIG_NFRAC_GET(x) (((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB) |
| 78 | #define CPU_PLL_CONFIG_NFRAC_SET(x) (((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK) |
| 79 | #define CPU_PLL_CONFIG_NFRAC_RESET 0x10 // 16 |
| 80 | #define CPU_PLL_CONFIG_ADDRESS 0x18050000 |
| 81 | #define DDR_PLL_CONFIG_UPDATING_MSB 31 |
| 82 | #define DDR_PLL_CONFIG_UPDATING_LSB 31 |
| 83 | #define DDR_PLL_CONFIG_UPDATING_MASK 0x80000000 |
| 84 | #define DDR_PLL_CONFIG_UPDATING_GET(x) (((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB) |
| 85 | #define DDR_PLL_CONFIG_UPDATING_SET(x) (((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK) |
| 86 | #define DDR_PLL_CONFIG_UPDATING_RESET 0x1 // 1 |
| 87 | #define DDR_PLL_CONFIG_PLLPWD_MSB 30 |
| 88 | #define DDR_PLL_CONFIG_PLLPWD_LSB 30 |
| 89 | #define DDR_PLL_CONFIG_PLLPWD_MASK 0x40000000 |
| 90 | #define DDR_PLL_CONFIG_PLLPWD_GET(x) (((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB) |
| 91 | #define DDR_PLL_CONFIG_PLLPWD_SET(x) (((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK) |
| 92 | #define DDR_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 |
| 93 | #define DDR_PLL_CONFIG_SPARE_MSB 29 |
| 94 | #define DDR_PLL_CONFIG_SPARE_LSB 26 |
| 95 | #define DDR_PLL_CONFIG_SPARE_MASK 0x3c000000 |
| 96 | #define DDR_PLL_CONFIG_SPARE_GET(x) (((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB) |
| 97 | #define DDR_PLL_CONFIG_SPARE_SET(x) (((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK) |
| 98 | #define DDR_PLL_CONFIG_SPARE_RESET 0x0 // 0 |
| 99 | #define DDR_PLL_CONFIG_OUTDIV_MSB 25 |
| 100 | #define DDR_PLL_CONFIG_OUTDIV_LSB 23 |
| 101 | #define DDR_PLL_CONFIG_OUTDIV_MASK 0x03800000 |
| 102 | #define DDR_PLL_CONFIG_OUTDIV_GET(x) (((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB) |
| 103 | #define DDR_PLL_CONFIG_OUTDIV_SET(x) (((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK) |
| 104 | #define DDR_PLL_CONFIG_OUTDIV_RESET 0x0 // 0 |
| 105 | #define DDR_PLL_CONFIG_RANGE_MSB 22 |
| 106 | #define DDR_PLL_CONFIG_RANGE_LSB 21 |
| 107 | #define DDR_PLL_CONFIG_RANGE_MASK 0x00600000 |
| 108 | #define DDR_PLL_CONFIG_RANGE_GET(x) (((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB) |
| 109 | #define DDR_PLL_CONFIG_RANGE_SET(x) (((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK) |
| 110 | #define DDR_PLL_CONFIG_RANGE_RESET 0x3 // 3 |
| 111 | #define DDR_PLL_CONFIG_REFDIV_MSB 20 |
| 112 | #define DDR_PLL_CONFIG_REFDIV_LSB 16 |
| 113 | #define DDR_PLL_CONFIG_REFDIV_MASK 0x001f0000 |
| 114 | #define DDR_PLL_CONFIG_REFDIV_GET(x) (((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB) |
| 115 | #define DDR_PLL_CONFIG_REFDIV_SET(x) (((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK) |
| 116 | #define DDR_PLL_CONFIG_REFDIV_RESET 0x2 // 2 |
| 117 | #define DDR_PLL_CONFIG_NINT_MSB 15 |
| 118 | #define DDR_PLL_CONFIG_NINT_LSB 10 |
| 119 | #define DDR_PLL_CONFIG_NINT_MASK 0x0000fc00 |
| 120 | #define DDR_PLL_CONFIG_NINT_GET(x) (((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB) |
| 121 | #define DDR_PLL_CONFIG_NINT_SET(x) (((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK) |
| 122 | #define DDR_PLL_CONFIG_NINT_RESET 0x14 // 20 |
| 123 | #define DDR_PLL_CONFIG_NFRAC_MSB 9 |
| 124 | #define DDR_PLL_CONFIG_NFRAC_LSB 0 |
| 125 | #define DDR_PLL_CONFIG_NFRAC_MASK 0x000003ff |
| 126 | #define DDR_PLL_CONFIG_NFRAC_GET(x) (((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB) |
| 127 | #define DDR_PLL_CONFIG_NFRAC_SET(x) (((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK) |
| 128 | #define DDR_PLL_CONFIG_NFRAC_RESET 0x200 // 512 |
| 129 | #define DDR_PLL_CONFIG_ADDRESS 0x18050004 |
| 130 | |
| 131 | #define DDR_CTL_CONFIG_SRAM_TSEL_MSB 31 |
| 132 | #define DDR_CTL_CONFIG_SRAM_TSEL_LSB 30 |
| 133 | #define DDR_CTL_CONFIG_SRAM_TSEL_MASK 0xc0000000 |
| 134 | #define DDR_CTL_CONFIG_SRAM_TSEL_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB) |
| 135 | #define DDR_CTL_CONFIG_SRAM_TSEL_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) |
| 136 | #define DDR_CTL_CONFIG_SRAM_TSEL_RESET 0x1 // 1 |
| 137 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB 29 |
| 138 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB 21 |
| 139 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK 0x3fe00000 |
| 140 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x) (((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) |
| 141 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x) (((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) |
| 142 | #define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET 0x0 // 0 |
| 143 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB 20 |
| 144 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB 20 |
| 145 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK 0x00100000 |
| 146 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) |
| 147 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) |
| 148 | #define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET 0x1 // 1 |
| 149 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB 19 |
| 150 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB 19 |
| 151 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK 0x00080000 |
| 152 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) |
| 153 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) |
| 154 | #define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET 0x1 // 1 |
| 155 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB 18 |
| 156 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB 18 |
| 157 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK 0x00040000 |
| 158 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) |
| 159 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) |
| 160 | #define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET 0x1 // 1 |
| 161 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB 17 |
| 162 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB 17 |
| 163 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK 0x00020000 |
| 164 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) |
| 165 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) |
| 166 | #define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET 0x1 // 1 |
| 167 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB 16 |
| 168 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB 16 |
| 169 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK 0x00010000 |
| 170 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) |
| 171 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) |
| 172 | #define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET 0x1 // 1 |
| 173 | #define DDR_CTL_CONFIG_SPARE_MSB 13 |
| 174 | #define DDR_CTL_CONFIG_SPARE_LSB 7 |
| 175 | #define DDR_CTL_CONFIG_SPARE_MASK 0x00003f80 |
| 176 | #define DDR_CTL_CONFIG_SPARE_GET(x) (((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB) |
| 177 | #define DDR_CTL_CONFIG_SPARE_SET(x) (((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK) |
| 178 | #define DDR_CTL_CONFIG_SPARE_RESET 0x0 // 0 |
| 179 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB 6 |
| 180 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB 6 |
| 181 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK 0x00000040 |
| 182 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x) (((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) |
| 183 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x) (((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) |
| 184 | #define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET 0x0 // 0 |
| 185 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB 4 |
| 186 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB 4 |
| 187 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK 0x00000010 |
| 188 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x) (((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) |
| 189 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x) (((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) |
| 190 | #define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET 0x0 // 0 |
| 191 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB 3 |
| 192 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB 3 |
| 193 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK 0x00000008 |
| 194 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x) (((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) |
| 195 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x) (((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) |
| 196 | #define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET 0x0 // 0 |
| 197 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB 2 |
| 198 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB 2 |
| 199 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK 0x00000004 |
| 200 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x) (((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) |
| 201 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x) (((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) |
| 202 | #define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET 0x0 // 0 |
| 203 | #define DDR_CTL_CONFIG_HALF_WIDTH_MSB 1 |
| 204 | #define DDR_CTL_CONFIG_HALF_WIDTH_LSB 1 |
| 205 | #define DDR_CTL_CONFIG_HALF_WIDTH_MASK 0x00000002 |
| 206 | #define DDR_CTL_CONFIG_HALF_WIDTH_GET(x) (((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB) |
| 207 | #define DDR_CTL_CONFIG_HALF_WIDTH_SET(x) (((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) |
| 208 | #define DDR_CTL_CONFIG_HALF_WIDTH_RESET 0x1 // 1 |
| 209 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB 0 |
| 210 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB 0 |
| 211 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK 0x00000001 |
| 212 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x) (((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) |
| 213 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x) (((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) |
| 214 | #define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET 0x0 // 0 |
| 215 | #define DDR_CTL_CONFIG_ADDRESS 0x18000108 |
| 216 | |
| 217 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MSB 31 |
| 218 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB 31 |
| 219 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK 0x80000000 |
| 220 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) |
| 221 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_MASK) |
| 222 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQ_RESET 0x0 // 0 |
| 223 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MSB 30 |
| 224 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB 30 |
| 225 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK 0x40000000 |
| 226 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_GET(x) (((x) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) >> DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) |
| 227 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_SET(x) (((x) << DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_LSB) & DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_MASK) |
| 228 | #define DDR_DEBUG_RD_CNTL_FORCE_WR_DQS_RESET 0x0 // 0 |
| 229 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MSB 29 |
| 230 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB 29 |
| 231 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK 0x20000000 |
| 232 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_GET(x) (((x) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) >> DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) |
| 233 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_SET(x) (((x) << DDR_DEBUG_RD_CNTL_USE_LB_CLK_LSB) & DDR_DEBUG_RD_CNTL_USE_LB_CLK_MASK) |
| 234 | #define DDR_DEBUG_RD_CNTL_USE_LB_CLK_RESET 0x0 // 0 |
| 235 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MSB 28 |
| 236 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB 28 |
| 237 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK 0x10000000 |
| 238 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_GET(x) (((x) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) >> DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) |
| 239 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_SET(x) (((x) << DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_LSB) & DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_MASK) |
| 240 | #define DDR_DEBUG_RD_CNTL_LB_SRC_CK_P_RESET 0x1 // 1 |
| 241 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MSB 27 |
| 242 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB 27 |
| 243 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK 0x08000000 |
| 244 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_GET(x) (((x) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) >> DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) |
| 245 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_SET(x) (((x) << DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_LSB) & DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_MASK) |
| 246 | #define DDR_DEBUG_RD_CNTL_EN_RD_ON_WR_RESET 0x0 // 0 |
| 247 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MSB 16 |
| 248 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB 16 |
| 249 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK 0x00010000 |
| 250 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) |
| 251 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_MASK) |
| 252 | #define DDR_DEBUG_RD_CNTL_CK_P_PDLY_BYP_RESET 0x0 // 0 |
| 253 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MSB 15 |
| 254 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB 15 |
| 255 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK 0x00008000 |
| 256 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) |
| 257 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_LSB) & DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_MASK) |
| 258 | #define DDR_DEBUG_RD_CNTL_GATE_OPEN_PDLY_BYP_RESET 0x0 // 0 |
| 259 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MSB 14 |
| 260 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB 13 |
| 261 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK 0x00006000 |
| 262 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) |
| 263 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_MASK) |
| 264 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_PDLY_RESET 0x0 // 0 |
| 265 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_MSB 12 |
| 266 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_LSB 8 |
| 267 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_MASK 0x00001f00 |
| 268 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) >> DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) |
| 269 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_GATE_TAP_LSB) & DDR_DEBUG_RD_CNTL_GATE_TAP_MASK) |
| 270 | #define DDR_DEBUG_RD_CNTL_GATE_TAP_RESET 0x1 // 1 |
| 271 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MSB 6 |
| 272 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB 5 |
| 273 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK 0x00000060 |
| 274 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) |
| 275 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_MASK) |
| 276 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_PDLY_RESET 0x0 // 0 |
| 277 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_MSB 4 |
| 278 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB 0 |
| 279 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK 0x0000001f |
| 280 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_GET(x) (((x) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) >> DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) |
| 281 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_SET(x) (((x) << DDR_DEBUG_RD_CNTL_CK_P_TAP_LSB) & DDR_DEBUG_RD_CNTL_CK_P_TAP_MASK) |
| 282 | #define DDR_DEBUG_RD_CNTL_CK_P_TAP_RESET 0x1 // 1 |
| 283 | #define DDR_DEBUG_RD_CNTL_ADDRESS 0x18000118 |
| 284 | |
| 285 | #define DDR2_CONFIG_DDR2_TWL_MSB 13 |
| 286 | #define DDR2_CONFIG_DDR2_TWL_LSB 10 |
| 287 | #define DDR2_CONFIG_DDR2_TWL_MASK 0x00003c00 |
| 288 | #define DDR2_CONFIG_DDR2_TWL_GET(x) (((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB) |
| 289 | #define DDR2_CONFIG_DDR2_TWL_SET(x) (((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK) |
| 290 | #define DDR2_CONFIG_DDR2_TWL_RESET 0x1 // 1 |
| 291 | #define DDR2_CONFIG_DDR2_ODT_MSB 9 |
| 292 | #define DDR2_CONFIG_DDR2_ODT_LSB 9 |
| 293 | #define DDR2_CONFIG_DDR2_ODT_MASK 0x00000200 |
| 294 | #define DDR2_CONFIG_DDR2_ODT_GET(x) (((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB) |
| 295 | #define DDR2_CONFIG_DDR2_ODT_SET(x) (((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK) |
| 296 | #define DDR2_CONFIG_DDR2_ODT_RESET 0x1 // 1 |
| 297 | #define DDR2_CONFIG_TFAW_MSB 7 |
| 298 | #define DDR2_CONFIG_TFAW_LSB 2 |
| 299 | #define DDR2_CONFIG_TFAW_MASK 0x000000fc |
| 300 | #define DDR2_CONFIG_TFAW_GET(x) (((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB) |
| 301 | #define DDR2_CONFIG_TFAW_SET(x) (((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK) |
| 302 | #define DDR2_CONFIG_TFAW_RESET 0x16 // 22 |
| 303 | #define DDR2_CONFIG_ENABLE_DDR2_MSB 0 |
| 304 | #define DDR2_CONFIG_ENABLE_DDR2_LSB 0 |
| 305 | #define DDR2_CONFIG_ENABLE_DDR2_MASK 0x00000001 |
| 306 | #define DDR2_CONFIG_ENABLE_DDR2_GET(x) (((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB) |
| 307 | #define DDR2_CONFIG_ENABLE_DDR2_SET(x) (((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK) |
| 308 | #define DDR2_CONFIG_ENABLE_DDR2_RESET 0x0 // 0 |
| 309 | #define DDR2_CONFIG_ADDRESS 0x180000b8 |
| 310 | |
| 311 | #define DDR_CONTROL_EMR3S_MSB 5 |
| 312 | #define DDR_CONTROL_EMR3S_LSB 5 |
| 313 | #define DDR_CONTROL_EMR3S_MASK 0x00000020 |
| 314 | #define DDR_CONTROL_EMR3S_GET(x) (((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB) |
| 315 | #define DDR_CONTROL_EMR3S_SET(x) (((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK) |
| 316 | #define DDR_CONTROL_EMR3S_RESET 0x0 // 0 |
| 317 | #define DDR_CONTROL_EMR2S_MSB 4 |
| 318 | #define DDR_CONTROL_EMR2S_LSB 4 |
| 319 | #define DDR_CONTROL_EMR2S_MASK 0x00000010 |
| 320 | #define DDR_CONTROL_EMR2S_GET(x) (((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB) |
| 321 | #define DDR_CONTROL_EMR2S_SET(x) (((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK) |
| 322 | #define DDR_CONTROL_EMR2S_RESET 0x0 // 0 |
| 323 | #define DDR_CONTROL_PREA_MSB 3 |
| 324 | #define DDR_CONTROL_PREA_LSB 3 |
| 325 | #define DDR_CONTROL_PREA_MASK 0x00000008 |
| 326 | #define DDR_CONTROL_PREA_GET(x) (((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB) |
| 327 | #define DDR_CONTROL_PREA_SET(x) (((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK) |
| 328 | #define DDR_CONTROL_PREA_RESET 0x0 // 0 |
| 329 | #define DDR_CONTROL_REF_MSB 2 |
| 330 | #define DDR_CONTROL_REF_LSB 2 |
| 331 | #define DDR_CONTROL_REF_MASK 0x00000004 |
| 332 | #define DDR_CONTROL_REF_GET(x) (((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB) |
| 333 | #define DDR_CONTROL_REF_SET(x) (((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK) |
| 334 | #define DDR_CONTROL_REF_RESET 0x0 // 0 |
| 335 | #define DDR_CONTROL_EMRS_MSB 1 |
| 336 | #define DDR_CONTROL_EMRS_LSB 1 |
| 337 | #define DDR_CONTROL_EMRS_MASK 0x00000002 |
| 338 | #define DDR_CONTROL_EMRS_GET(x) (((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB) |
| 339 | #define DDR_CONTROL_EMRS_SET(x) (((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK) |
| 340 | #define DDR_CONTROL_EMRS_RESET 0x0 // 0 |
| 341 | #define DDR_CONTROL_MRS_MSB 0 |
| 342 | #define DDR_CONTROL_MRS_LSB 0 |
| 343 | #define DDR_CONTROL_MRS_MASK 0x00000001 |
| 344 | #define DDR_CONTROL_MRS_GET(x) (((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB) |
| 345 | #define DDR_CONTROL_MRS_SET(x) (((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK) |
| 346 | #define DDR_CONTROL_MRS_RESET 0x0 // 0 |
| 347 | #define DDR_CONTROL_ADDRESS 0x18000010 |
| 348 | |
| 349 | #define DDR_CONFIG_CAS_LATENCY_MSB_MSB 31 |
| 350 | #define DDR_CONFIG_CAS_LATENCY_MSB_LSB 31 |
| 351 | #define DDR_CONFIG_CAS_LATENCY_MSB_MASK 0x80000000 |
| 352 | #define DDR_CONFIG_CAS_LATENCY_MSB_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB) |
| 353 | #define DDR_CONFIG_CAS_LATENCY_MSB_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) |
| 354 | #define DDR_CONFIG_CAS_LATENCY_MSB_RESET 0x0 // 0 |
| 355 | #define DDR_CONFIG_OPEN_PAGE_MSB 30 |
| 356 | #define DDR_CONFIG_OPEN_PAGE_LSB 30 |
| 357 | #define DDR_CONFIG_OPEN_PAGE_MASK 0x40000000 |
| 358 | #define DDR_CONFIG_OPEN_PAGE_GET(x) (((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB) |
| 359 | #define DDR_CONFIG_OPEN_PAGE_SET(x) (((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK) |
| 360 | #define DDR_CONFIG_OPEN_PAGE_RESET 0x1 // 1 |
| 361 | #define DDR_CONFIG_CAS_LATENCY_MSB 29 |
| 362 | #define DDR_CONFIG_CAS_LATENCY_LSB 27 |
| 363 | #define DDR_CONFIG_CAS_LATENCY_MASK 0x38000000 |
| 364 | #define DDR_CONFIG_CAS_LATENCY_GET(x) (((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB) |
| 365 | #define DDR_CONFIG_CAS_LATENCY_SET(x) (((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK) |
| 366 | #define DDR_CONFIG_CAS_LATENCY_RESET 0x6 // 6 |
| 367 | #define DDR_CONFIG_TMRD_MSB 26 |
| 368 | #define DDR_CONFIG_TMRD_LSB 23 |
| 369 | #define DDR_CONFIG_TMRD_MASK 0x07800000 |
| 370 | #define DDR_CONFIG_TMRD_GET(x) (((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB) |
| 371 | #define DDR_CONFIG_TMRD_SET(x) (((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK) |
| 372 | #define DDR_CONFIG_TMRD_RESET 0xf // 15 |
| 373 | #define DDR_CONFIG_TRFC_MSB 22 |
| 374 | #define DDR_CONFIG_TRFC_LSB 17 |
| 375 | #define DDR_CONFIG_TRFC_MASK 0x007e0000 |
| 376 | #define DDR_CONFIG_TRFC_GET(x) (((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB) |
| 377 | #define DDR_CONFIG_TRFC_SET(x) (((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK) |
| 378 | #define DDR_CONFIG_TRFC_RESET 0x24 // 36 |
| 379 | #define DDR_CONFIG_TRRD_MSB 16 |
| 380 | #define DDR_CONFIG_TRRD_LSB 13 |
| 381 | #define DDR_CONFIG_TRRD_MASK 0x0001e000 |
| 382 | #define DDR_CONFIG_TRRD_GET(x) (((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB) |
| 383 | #define DDR_CONFIG_TRRD_SET(x) (((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK) |
| 384 | #define DDR_CONFIG_TRRD_RESET 0x4 // 4 |
| 385 | #define DDR_CONFIG_TRP_MSB 12 |
| 386 | #define DDR_CONFIG_TRP_LSB 9 |
| 387 | #define DDR_CONFIG_TRP_MASK 0x00001e00 |
| 388 | #define DDR_CONFIG_TRP_GET(x) (((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB) |
| 389 | #define DDR_CONFIG_TRP_SET(x) (((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK) |
| 390 | #define DDR_CONFIG_TRP_RESET 0x6 // 6 |
| 391 | #define DDR_CONFIG_TRCD_MSB 8 |
| 392 | #define DDR_CONFIG_TRCD_LSB 5 |
| 393 | #define DDR_CONFIG_TRCD_MASK 0x000001e0 |
| 394 | #define DDR_CONFIG_TRCD_GET(x) (((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB) |
| 395 | #define DDR_CONFIG_TRCD_SET(x) (((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK) |
| 396 | #define DDR_CONFIG_TRCD_RESET 0x6 // 6 |
| 397 | #define DDR_CONFIG_TRAS_MSB 4 |
| 398 | #define DDR_CONFIG_TRAS_LSB 0 |
| 399 | #define DDR_CONFIG_TRAS_MASK 0x0000001f |
| 400 | #define DDR_CONFIG_TRAS_GET(x) (((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB) |
| 401 | #define DDR_CONFIG_TRAS_SET(x) (((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK) |
| 402 | #define DDR_CONFIG_TRAS_RESET 0x10 // 16 |
| 403 | #define DDR_CONFIG_ADDRESS 0x18000000 |
| 404 | |
| 405 | #define DDR_CONFIG2_HALF_WIDTH_LOW_MSB 31 |
| 406 | #define DDR_CONFIG2_HALF_WIDTH_LOW_LSB 31 |
| 407 | #define DDR_CONFIG2_HALF_WIDTH_LOW_MASK 0x80000000 |
| 408 | #define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x) (((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB) |
| 409 | #define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x) (((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) |
| 410 | #define DDR_CONFIG2_HALF_WIDTH_LOW_RESET 0x1 // 1 |
| 411 | #define DDR_CONFIG2_SWAP_A26_A27_MSB 30 |
| 412 | #define DDR_CONFIG2_SWAP_A26_A27_LSB 30 |
| 413 | #define DDR_CONFIG2_SWAP_A26_A27_MASK 0x40000000 |
| 414 | #define DDR_CONFIG2_SWAP_A26_A27_GET(x) (((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB) |
| 415 | #define DDR_CONFIG2_SWAP_A26_A27_SET(x) (((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK) |
| 416 | #define DDR_CONFIG2_SWAP_A26_A27_RESET 0x0 // 0 |
| 417 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB 29 |
| 418 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB 26 |
| 419 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK 0x3c000000 |
| 420 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x) (((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) |
| 421 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x) (((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) |
| 422 | #define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET 0x6 // 6 |
| 423 | #define DDR_CONFIG2_TWTR_MSB 25 |
| 424 | #define DDR_CONFIG2_TWTR_LSB 21 |
| 425 | #define DDR_CONFIG2_TWTR_MASK 0x03e00000 |
| 426 | #define DDR_CONFIG2_TWTR_GET(x) (((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB) |
| 427 | #define DDR_CONFIG2_TWTR_SET(x) (((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK) |
| 428 | #define DDR_CONFIG2_TWTR_RESET 0xe // 14 |
| 429 | #define DDR_CONFIG2_TRTP_MSB 20 |
| 430 | #define DDR_CONFIG2_TRTP_LSB 17 |
| 431 | #define DDR_CONFIG2_TRTP_MASK 0x001e0000 |
| 432 | #define DDR_CONFIG2_TRTP_GET(x) (((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB) |
| 433 | #define DDR_CONFIG2_TRTP_SET(x) (((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK) |
| 434 | #define DDR_CONFIG2_TRTP_RESET 0x8 // 8 |
| 435 | #define DDR_CONFIG2_TRTW_MSB 16 |
| 436 | #define DDR_CONFIG2_TRTW_LSB 12 |
| 437 | #define DDR_CONFIG2_TRTW_MASK 0x0001f000 |
| 438 | #define DDR_CONFIG2_TRTW_GET(x) (((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB) |
| 439 | #define DDR_CONFIG2_TRTW_SET(x) (((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK) |
| 440 | #define DDR_CONFIG2_TRTW_RESET 0x10 // 16 |
| 441 | #define DDR_CONFIG2_TWR_MSB 11 |
| 442 | #define DDR_CONFIG2_TWR_LSB 8 |
| 443 | #define DDR_CONFIG2_TWR_MASK 0x00000f00 |
| 444 | #define DDR_CONFIG2_TWR_GET(x) (((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB) |
| 445 | #define DDR_CONFIG2_TWR_SET(x) (((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK) |
| 446 | #define DDR_CONFIG2_TWR_RESET 0x6 // 6 |
| 447 | #define DDR_CONFIG2_CKE_MSB 7 |
| 448 | #define DDR_CONFIG2_CKE_LSB 7 |
| 449 | #define DDR_CONFIG2_CKE_MASK 0x00000080 |
| 450 | #define DDR_CONFIG2_CKE_GET(x) (((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB) |
| 451 | #define DDR_CONFIG2_CKE_SET(x) (((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK) |
| 452 | #define DDR_CONFIG2_CKE_RESET 0x0 // 0 |
| 453 | #define DDR_CONFIG2_PHASE_SELECT_MSB 6 |
| 454 | #define DDR_CONFIG2_PHASE_SELECT_LSB 6 |
| 455 | #define DDR_CONFIG2_PHASE_SELECT_MASK 0x00000040 |
| 456 | #define DDR_CONFIG2_PHASE_SELECT_GET(x) (((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB) |
| 457 | #define DDR_CONFIG2_PHASE_SELECT_SET(x) (((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK) |
| 458 | #define DDR_CONFIG2_PHASE_SELECT_RESET 0x0 // 0 |
| 459 | #define DDR_CONFIG2_CNTL_OE_EN_MSB 5 |
| 460 | #define DDR_CONFIG2_CNTL_OE_EN_LSB 5 |
| 461 | #define DDR_CONFIG2_CNTL_OE_EN_MASK 0x00000020 |
| 462 | #define DDR_CONFIG2_CNTL_OE_EN_GET(x) (((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB) |
| 463 | #define DDR_CONFIG2_CNTL_OE_EN_SET(x) (((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK) |
| 464 | #define DDR_CONFIG2_CNTL_OE_EN_RESET 0x1 // 1 |
| 465 | #define DDR_CONFIG2_BURST_TYPE_MSB 4 |
| 466 | #define DDR_CONFIG2_BURST_TYPE_LSB 4 |
| 467 | #define DDR_CONFIG2_BURST_TYPE_MASK 0x00000010 |
| 468 | #define DDR_CONFIG2_BURST_TYPE_GET(x) (((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB) |
| 469 | #define DDR_CONFIG2_BURST_TYPE_SET(x) (((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK) |
| 470 | #define DDR_CONFIG2_BURST_TYPE_RESET 0x0 // 0 |
| 471 | #define DDR_CONFIG2_BURST_LENGTH_MSB 3 |
| 472 | #define DDR_CONFIG2_BURST_LENGTH_LSB 0 |
| 473 | #define DDR_CONFIG2_BURST_LENGTH_MASK 0x0000000f |
| 474 | #define DDR_CONFIG2_BURST_LENGTH_GET(x) (((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB) |
| 475 | #define DDR_CONFIG2_BURST_LENGTH_SET(x) (((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK) |
| 476 | #define DDR_CONFIG2_BURST_LENGTH_RESET 0x8 // 8 |
| 477 | #define DDR_CONFIG2_ADDRESS 0x18000004 |
| 478 | |
| 479 | #define DDR_CONFIG_3_SPARE_MSB 31 |
| 480 | #define DDR_CONFIG_3_SPARE_LSB 4 |
| 481 | #define DDR_CONFIG_3_SPARE_MASK 0xfffffff0 |
| 482 | #define DDR_CONFIG_3_SPARE_GET(x) (((x) & DDR_CONFIG_3_SPARE_MASK) >> DDR_CONFIG_3_SPARE_LSB) |
| 483 | #define DDR_CONFIG_3_SPARE_SET(x) (((x) << DDR_CONFIG_3_SPARE_LSB) & DDR_CONFIG_3_SPARE_MASK) |
| 484 | #define DDR_CONFIG_3_SPARE_RESET 0x0 // 0 |
| 485 | #define DDR_CONFIG_3_TWR_MSB_MSB 3 |
| 486 | #define DDR_CONFIG_3_TWR_MSB_LSB 3 |
| 487 | #define DDR_CONFIG_3_TWR_MSB_MASK 0x00000008 |
| 488 | #define DDR_CONFIG_3_TWR_MSB_GET(x) (((x) & DDR_CONFIG_3_TWR_MSB_MASK) >> DDR_CONFIG_3_TWR_MSB_LSB) |
| 489 | #define DDR_CONFIG_3_TWR_MSB_SET(x) (((x) << DDR_CONFIG_3_TWR_MSB_LSB) & DDR_CONFIG_3_TWR_MSB_MASK) |
| 490 | #define DDR_CONFIG_3_TWR_MSB_RESET 0x0 // 0 |
| 491 | #define DDR_CONFIG_3_TRAS_MSB_MSB 2 |
| 492 | #define DDR_CONFIG_3_TRAS_MSB_LSB 2 |
| 493 | #define DDR_CONFIG_3_TRAS_MSB_MASK 0x00000004 |
| 494 | #define DDR_CONFIG_3_TRAS_MSB_GET(x) (((x) & DDR_CONFIG_3_TRAS_MSB_MASK) >> DDR_CONFIG_3_TRAS_MSB_LSB) |
| 495 | #define DDR_CONFIG_3_TRAS_MSB_SET(x) (((x) << DDR_CONFIG_3_TRAS_MSB_LSB) & DDR_CONFIG_3_TRAS_MSB_MASK) |
| 496 | #define DDR_CONFIG_3_TRAS_MSB_RESET 0x0 // 0 |
| 497 | #define DDR_CONFIG_3_TRFC_LSB_MSB 1 |
| 498 | #define DDR_CONFIG_3_TRFC_LSB_LSB 0 |
| 499 | #define DDR_CONFIG_3_TRFC_LSB_MASK 0x00000003 |
| 500 | #define DDR_CONFIG_3_TRFC_LSB_GET(x) (((x) & DDR_CONFIG_3_TRFC_LSB_MASK) >> DDR_CONFIG_3_TRFC_LSB_LSB) |
| 501 | #define DDR_CONFIG_3_TRFC_LSB_SET(x) (((x) << DDR_CONFIG_3_TRFC_LSB_LSB) & DDR_CONFIG_3_TRFC_LSB_MASK) |
| 502 | #define DDR_CONFIG_3_TRFC_LSB_RESET 0x0 // 0 |
| 503 | #define DDR_CONFIG_3_ADDRESS 0x1800015c |
| 504 | |
| 505 | #define DDR_MODE_REGISTER_VALUE_MSB 13 |
| 506 | #define DDR_MODE_REGISTER_VALUE_LSB 0 |
| 507 | #define DDR_MODE_REGISTER_VALUE_MASK 0x00003fff |
| 508 | #define DDR_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB) |
| 509 | #define DDR_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK) |
| 510 | #define DDR_MODE_REGISTER_VALUE_RESET 0x133 // 307 |
| 511 | #define DDR_MODE_REGISTER_ADDRESS 0x18000008 |
| 512 | |
| 513 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB 13 |
| 514 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB 0 |
| 515 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK 0x00003fff |
| 516 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x) (((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) |
| 517 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x) (((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) |
| 518 | #define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET 0x2 // 2 |
| 519 | #define DDR_EXTENDED_MODE_REGISTER_ADDRESS 0x1800000c |
| 520 | |
| 521 | #define DDR_REFRESH_ENABLE_MSB 14 |
| 522 | #define DDR_REFRESH_ENABLE_LSB 14 |
| 523 | #define DDR_REFRESH_ENABLE_MASK 0x00004000 |
| 524 | #define DDR_REFRESH_ENABLE_GET(x) (((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB) |
| 525 | #define DDR_REFRESH_ENABLE_SET(x) (((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK) |
| 526 | #define DDR_REFRESH_ENABLE_RESET 0x0 // 0 |
| 527 | #define DDR_REFRESH_PERIOD_MSB 13 |
| 528 | #define DDR_REFRESH_PERIOD_LSB 0 |
| 529 | #define DDR_REFRESH_PERIOD_MASK 0x00003fff |
| 530 | #define DDR_REFRESH_PERIOD_GET(x) (((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB) |
| 531 | #define DDR_REFRESH_PERIOD_SET(x) (((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK) |
| 532 | #define DDR_REFRESH_PERIOD_RESET 0x12c // 300 |
| 533 | #define DDR_REFRESH_ADDRESS 0x18000014 |
| 534 | |
| 535 | #define BB_DPLL2_LOCAL_PLL_MSB 31 |
| 536 | #define BB_DPLL2_LOCAL_PLL_LSB 31 |
| 537 | #define BB_DPLL2_LOCAL_PLL_MASK 0x80000000 |
| 538 | #define BB_DPLL2_LOCAL_PLL_GET(x) (((x) & BB_DPLL2_LOCAL_PLL_MASK) >> BB_DPLL2_LOCAL_PLL_LSB) |
| 539 | #define BB_DPLL2_LOCAL_PLL_SET(x) (((x) << BB_DPLL2_LOCAL_PLL_LSB) & BB_DPLL2_LOCAL_PLL_MASK) |
| 540 | #define BB_DPLL2_LOCAL_PLL_RESET 0x0 // 0 |
| 541 | #define BB_DPLL2_KI_MSB 30 |
| 542 | #define BB_DPLL2_KI_LSB 29 |
| 543 | #define BB_DPLL2_KI_MASK 0x60000000 |
| 544 | #define BB_DPLL2_KI_GET(x) (((x) & BB_DPLL2_KI_MASK) >> BB_DPLL2_KI_LSB) |
| 545 | #define BB_DPLL2_KI_SET(x) (((x) << BB_DPLL2_KI_LSB) & BB_DPLL2_KI_MASK) |
| 546 | #define BB_DPLL2_KI_RESET 0x2 // 2 |
| 547 | #define BB_DPLL2_KD_MSB 28 |
| 548 | #define BB_DPLL2_KD_LSB 25 |
| 549 | #define BB_DPLL2_KD_MASK 0x1e000000 |
| 550 | #define BB_DPLL2_KD_GET(x) (((x) & BB_DPLL2_KD_MASK) >> BB_DPLL2_KD_LSB) |
| 551 | #define BB_DPLL2_KD_SET(x) (((x) << BB_DPLL2_KD_LSB) & BB_DPLL2_KD_MASK) |
| 552 | #define BB_DPLL2_KD_RESET 0xa // 10 |
| 553 | #define BB_DPLL2_EN_NEGTRIG_MSB 24 |
| 554 | #define BB_DPLL2_EN_NEGTRIG_LSB 24 |
| 555 | #define BB_DPLL2_EN_NEGTRIG_MASK 0x01000000 |
| 556 | #define BB_DPLL2_EN_NEGTRIG_GET(x) (((x) & BB_DPLL2_EN_NEGTRIG_MASK) >> BB_DPLL2_EN_NEGTRIG_LSB) |
| 557 | #define BB_DPLL2_EN_NEGTRIG_SET(x) (((x) << BB_DPLL2_EN_NEGTRIG_LSB) & BB_DPLL2_EN_NEGTRIG_MASK) |
| 558 | #define BB_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 |
| 559 | #define BB_DPLL2_SEL_1SDM_MSB 23 |
| 560 | #define BB_DPLL2_SEL_1SDM_LSB 23 |
| 561 | #define BB_DPLL2_SEL_1SDM_MASK 0x00800000 |
| 562 | #define BB_DPLL2_SEL_1SDM_GET(x) (((x) & BB_DPLL2_SEL_1SDM_MASK) >> BB_DPLL2_SEL_1SDM_LSB) |
| 563 | #define BB_DPLL2_SEL_1SDM_SET(x) (((x) << BB_DPLL2_SEL_1SDM_LSB) & BB_DPLL2_SEL_1SDM_MASK) |
| 564 | #define BB_DPLL2_SEL_1SDM_RESET 0x0 // 0 |
| 565 | #define BB_DPLL2_PLL_PWD_MSB 22 |
| 566 | #define BB_DPLL2_PLL_PWD_LSB 22 |
| 567 | #define BB_DPLL2_PLL_PWD_MASK 0x00400000 |
| 568 | #define BB_DPLL2_PLL_PWD_GET(x) (((x) & BB_DPLL2_PLL_PWD_MASK) >> BB_DPLL2_PLL_PWD_LSB) |
| 569 | #define BB_DPLL2_PLL_PWD_SET(x) (((x) << BB_DPLL2_PLL_PWD_LSB) & BB_DPLL2_PLL_PWD_MASK) |
| 570 | #define BB_DPLL2_PLL_PWD_RESET 0x1 // 1 |
| 571 | #define BB_DPLL2_OUTDIV_MSB 21 |
| 572 | #define BB_DPLL2_OUTDIV_LSB 19 |
| 573 | #define BB_DPLL2_OUTDIV_MASK 0x00380000 |
| 574 | #define BB_DPLL2_OUTDIV_GET(x) (((x) & BB_DPLL2_OUTDIV_MASK) >> BB_DPLL2_OUTDIV_LSB) |
| 575 | #define BB_DPLL2_OUTDIV_SET(x) (((x) << BB_DPLL2_OUTDIV_LSB) & BB_DPLL2_OUTDIV_MASK) |
| 576 | #define BB_DPLL2_OUTDIV_RESET 0x1 // 1 |
| 577 | #define BB_DPLL2_PHASE_SHIFT_MSB 18 |
| 578 | #define BB_DPLL2_PHASE_SHIFT_LSB 12 |
| 579 | #define BB_DPLL2_PHASE_SHIFT_MASK 0x0007f000 |
| 580 | #define BB_DPLL2_PHASE_SHIFT_GET(x) (((x) & BB_DPLL2_PHASE_SHIFT_MASK) >> BB_DPLL2_PHASE_SHIFT_LSB) |
| 581 | #define BB_DPLL2_PHASE_SHIFT_SET(x) (((x) << BB_DPLL2_PHASE_SHIFT_LSB) & BB_DPLL2_PHASE_SHIFT_MASK) |
| 582 | #define BB_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 |
| 583 | #define BB_DPLL2_TESTIN_MSB 11 |
| 584 | #define BB_DPLL2_TESTIN_LSB 2 |
| 585 | #define BB_DPLL2_TESTIN_MASK 0x00000ffc |
| 586 | #define BB_DPLL2_TESTIN_GET(x) (((x) & BB_DPLL2_TESTIN_MASK) >> BB_DPLL2_TESTIN_LSB) |
| 587 | #define BB_DPLL2_TESTIN_SET(x) (((x) << BB_DPLL2_TESTIN_LSB) & BB_DPLL2_TESTIN_MASK) |
| 588 | #define BB_DPLL2_TESTIN_RESET 0x0 // 0 |
| 589 | #define BB_DPLL2_SEL_COUNT_MSB 1 |
| 590 | #define BB_DPLL2_SEL_COUNT_LSB 1 |
| 591 | #define BB_DPLL2_SEL_COUNT_MASK 0x00000002 |
| 592 | #define BB_DPLL2_SEL_COUNT_GET(x) (((x) & BB_DPLL2_SEL_COUNT_MASK) >> BB_DPLL2_SEL_COUNT_LSB) |
| 593 | #define BB_DPLL2_SEL_COUNT_SET(x) (((x) << BB_DPLL2_SEL_COUNT_LSB) & BB_DPLL2_SEL_COUNT_MASK) |
| 594 | #define BB_DPLL2_SEL_COUNT_RESET 0x0 // 0 |
| 595 | #define BB_DPLL2_RESET_TEST_MSB 0 |
| 596 | #define BB_DPLL2_RESET_TEST_LSB 0 |
| 597 | #define BB_DPLL2_RESET_TEST_MASK 0x00000001 |
| 598 | #define BB_DPLL2_RESET_TEST_GET(x) (((x) & BB_DPLL2_RESET_TEST_MASK) >> BB_DPLL2_RESET_TEST_LSB) |
| 599 | #define BB_DPLL2_RESET_TEST_SET(x) (((x) << BB_DPLL2_RESET_TEST_LSB) & BB_DPLL2_RESET_TEST_MASK) |
| 600 | #define BB_DPLL2_RESET_TEST_RESET 0x0 // 0 |
| 601 | #define BB_DPLL2_ADDRESS 0x18116184 |
| 602 | |
| 603 | #define PCIe_DPLL2_LOCAL_PLL_MSB 31 |
| 604 | #define PCIe_DPLL2_LOCAL_PLL_LSB 31 |
| 605 | #define PCIe_DPLL2_LOCAL_PLL_MASK 0x80000000 |
| 606 | #define PCIe_DPLL2_LOCAL_PLL_GET(x) (((x) & PCIe_DPLL2_LOCAL_PLL_MASK) >> PCIe_DPLL2_LOCAL_PLL_LSB) |
| 607 | #define PCIe_DPLL2_LOCAL_PLL_SET(x) (((x) << PCIe_DPLL2_LOCAL_PLL_LSB) & PCIe_DPLL2_LOCAL_PLL_MASK) |
| 608 | #define PCIe_DPLL2_LOCAL_PLL_RESET 0x0 // 0 |
| 609 | #define PCIe_DPLL2_KI_MSB 30 |
| 610 | #define PCIe_DPLL2_KI_LSB 29 |
| 611 | #define PCIe_DPLL2_KI_MASK 0x60000000 |
| 612 | #define PCIe_DPLL2_KI_GET(x) (((x) & PCIe_DPLL2_KI_MASK) >> PCIe_DPLL2_KI_LSB) |
| 613 | #define PCIe_DPLL2_KI_SET(x) (((x) << PCIe_DPLL2_KI_LSB) & PCIe_DPLL2_KI_MASK) |
| 614 | #define PCIe_DPLL2_KI_RESET 0x2 // 2 |
| 615 | #define PCIe_DPLL2_KD_MSB 28 |
| 616 | #define PCIe_DPLL2_KD_LSB 25 |
| 617 | #define PCIe_DPLL2_KD_MASK 0x1e000000 |
| 618 | #define PCIe_DPLL2_KD_GET(x) (((x) & PCIe_DPLL2_KD_MASK) >> PCIe_DPLL2_KD_LSB) |
| 619 | #define PCIe_DPLL2_KD_SET(x) (((x) << PCIe_DPLL2_KD_LSB) & PCIe_DPLL2_KD_MASK) |
| 620 | #define PCIe_DPLL2_KD_RESET 0xa // 10 |
| 621 | #define PCIe_DPLL2_EN_NEGTRIG_MSB 24 |
| 622 | #define PCIe_DPLL2_EN_NEGTRIG_LSB 24 |
| 623 | #define PCIe_DPLL2_EN_NEGTRIG_MASK 0x01000000 |
| 624 | #define PCIe_DPLL2_EN_NEGTRIG_GET(x) (((x) & PCIe_DPLL2_EN_NEGTRIG_MASK) >> PCIe_DPLL2_EN_NEGTRIG_LSB) |
| 625 | #define PCIe_DPLL2_EN_NEGTRIG_SET(x) (((x) << PCIe_DPLL2_EN_NEGTRIG_LSB) & PCIe_DPLL2_EN_NEGTRIG_MASK) |
| 626 | #define PCIe_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 |
| 627 | #define PCIe_DPLL2_SEL_1SDM_MSB 23 |
| 628 | #define PCIe_DPLL2_SEL_1SDM_LSB 23 |
| 629 | #define PCIe_DPLL2_SEL_1SDM_MASK 0x00800000 |
| 630 | #define PCIe_DPLL2_SEL_1SDM_GET(x) (((x) & PCIe_DPLL2_SEL_1SDM_MASK) >> PCIe_DPLL2_SEL_1SDM_LSB) |
| 631 | #define PCIe_DPLL2_SEL_1SDM_SET(x) (((x) << PCIe_DPLL2_SEL_1SDM_LSB) & PCIe_DPLL2_SEL_1SDM_MASK) |
| 632 | #define PCIe_DPLL2_SEL_1SDM_RESET 0x0 // 0 |
| 633 | #define PCIe_DPLL2_PLL_PWD_MSB 22 |
| 634 | #define PCIe_DPLL2_PLL_PWD_LSB 22 |
| 635 | #define PCIe_DPLL2_PLL_PWD_MASK 0x00400000 |
| 636 | #define PCIe_DPLL2_PLL_PWD_GET(x) (((x) & PCIe_DPLL2_PLL_PWD_MASK) >> PCIe_DPLL2_PLL_PWD_LSB) |
| 637 | #define PCIe_DPLL2_PLL_PWD_SET(x) (((x) << PCIe_DPLL2_PLL_PWD_LSB) & PCIe_DPLL2_PLL_PWD_MASK) |
| 638 | #define PCIe_DPLL2_PLL_PWD_RESET 0x1 // 1 |
| 639 | #define PCIe_DPLL2_OUTDIV_MSB 21 |
| 640 | #define PCIe_DPLL2_OUTDIV_LSB 19 |
| 641 | #define PCIe_DPLL2_OUTDIV_MASK 0x00380000 |
| 642 | #define PCIe_DPLL2_OUTDIV_GET(x) (((x) & PCIe_DPLL2_OUTDIV_MASK) >> PCIe_DPLL2_OUTDIV_LSB) |
| 643 | #define PCIe_DPLL2_OUTDIV_SET(x) (((x) << PCIe_DPLL2_OUTDIV_LSB) & PCIe_DPLL2_OUTDIV_MASK) |
| 644 | #define PCIe_DPLL2_OUTDIV_RESET 0x1 // 1 |
| 645 | #define PCIe_DPLL2_PHASE_SHIFT_MSB 18 |
| 646 | #define PCIe_DPLL2_PHASE_SHIFT_LSB 12 |
| 647 | #define PCIe_DPLL2_PHASE_SHIFT_MASK 0x0007f000 |
| 648 | #define PCIe_DPLL2_PHASE_SHIFT_GET(x) (((x) & PCIe_DPLL2_PHASE_SHIFT_MASK) >> PCIe_DPLL2_PHASE_SHIFT_LSB) |
| 649 | #define PCIe_DPLL2_PHASE_SHIFT_SET(x) (((x) << PCIe_DPLL2_PHASE_SHIFT_LSB) & PCIe_DPLL2_PHASE_SHIFT_MASK) |
| 650 | #define PCIe_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 |
| 651 | #define PCIe_DPLL2_TESTIN_MSB 11 |
| 652 | #define PCIe_DPLL2_TESTIN_LSB 2 |
| 653 | #define PCIe_DPLL2_TESTIN_MASK 0x00000ffc |
| 654 | #define PCIe_DPLL2_TESTIN_GET(x) (((x) & PCIe_DPLL2_TESTIN_MASK) >> PCIe_DPLL2_TESTIN_LSB) |
| 655 | #define PCIe_DPLL2_TESTIN_SET(x) (((x) << PCIe_DPLL2_TESTIN_LSB) & PCIe_DPLL2_TESTIN_MASK) |
| 656 | #define PCIe_DPLL2_TESTIN_RESET 0x0 // 0 |
| 657 | #define PCIe_DPLL2_SEL_COUNT_MSB 1 |
| 658 | #define PCIe_DPLL2_SEL_COUNT_LSB 1 |
| 659 | #define PCIe_DPLL2_SEL_COUNT_MASK 0x00000002 |
| 660 | #define PCIe_DPLL2_SEL_COUNT_GET(x) (((x) & PCIe_DPLL2_SEL_COUNT_MASK) >> PCIe_DPLL2_SEL_COUNT_LSB) |
| 661 | #define PCIe_DPLL2_SEL_COUNT_SET(x) (((x) << PCIe_DPLL2_SEL_COUNT_LSB) & PCIe_DPLL2_SEL_COUNT_MASK) |
| 662 | #define PCIe_DPLL2_SEL_COUNT_RESET 0x0 // 0 |
| 663 | #define PCIe_DPLL2_RESET_TEST_MSB 0 |
| 664 | #define PCIe_DPLL2_RESET_TEST_LSB 0 |
| 665 | #define PCIe_DPLL2_RESET_TEST_MASK 0x00000001 |
| 666 | #define PCIe_DPLL2_RESET_TEST_GET(x) (((x) & PCIe_DPLL2_RESET_TEST_MASK) >> PCIe_DPLL2_RESET_TEST_LSB) |
| 667 | #define PCIe_DPLL2_RESET_TEST_SET(x) (((x) << PCIe_DPLL2_RESET_TEST_LSB) & PCIe_DPLL2_RESET_TEST_MASK) |
| 668 | #define PCIe_DPLL2_RESET_TEST_RESET 0x0 // 0 |
| 669 | #define PCIe_DPLL2_ADDRESS 0x18116c04 |
| 670 | |
| 671 | #define PCIE_DPLL3_DO_MEAS_MSB 31 |
| 672 | #define PCIE_DPLL3_DO_MEAS_LSB 31 |
| 673 | #define PCIE_DPLL3_DO_MEAS_MASK 0x80000000 |
| 674 | #define PCIE_DPLL3_DO_MEAS_GET(x) (((x) & PCIE_DPLL3_DO_MEAS_MASK) >> PCIE_DPLL3_DO_MEAS_LSB) |
| 675 | #define PCIE_DPLL3_DO_MEAS_SET(x) (((x) << PCIE_DPLL3_DO_MEAS_LSB) & PCIE_DPLL3_DO_MEAS_MASK) |
| 676 | #define PCIE_DPLL3_DO_MEAS_RESET 0x0 // 0 |
| 677 | #define PCIE_DPLL3_VC_MEAS0_MSB 30 |
| 678 | #define PCIE_DPLL3_VC_MEAS0_LSB 13 |
| 679 | #define PCIE_DPLL3_VC_MEAS0_MASK 0x7fffe000 |
| 680 | #define PCIE_DPLL3_VC_MEAS0_GET(x) (((x) & PCIE_DPLL3_VC_MEAS0_MASK) >> PCIE_DPLL3_VC_MEAS0_LSB) |
| 681 | #define PCIE_DPLL3_VC_MEAS0_SET(x) (((x) << PCIE_DPLL3_VC_MEAS0_LSB) & PCIE_DPLL3_VC_MEAS0_MASK) |
| 682 | #define PCIE_DPLL3_VC_MEAS0_RESET 0x0 // 0 |
| 683 | #define PCIE_DPLL3_VC_DIFF0_MSB 12 |
| 684 | #define PCIE_DPLL3_VC_DIFF0_LSB 3 |
| 685 | #define PCIE_DPLL3_VC_DIFF0_MASK 0x00001ff8 |
| 686 | #define PCIE_DPLL3_VC_DIFF0_GET(x) (((x) & PCIE_DPLL3_VC_DIFF0_MASK) >> PCIE_DPLL3_VC_DIFF0_LSB) |
| 687 | #define PCIE_DPLL3_VC_DIFF0_SET(x) (((x) << PCIE_DPLL3_VC_DIFF0_LSB) & PCIE_DPLL3_VC_DIFF0_MASK) |
| 688 | #define PCIE_DPLL3_VC_DIFF0_RESET 0x0 // 0 |
| 689 | #define PCIE_DPLL3_LOCAL_PLL_PWD_MSB 2 |
| 690 | #define PCIE_DPLL3_LOCAL_PLL_PWD_LSB 2 |
| 691 | #define PCIE_DPLL3_LOCAL_PLL_PWD_MASK 0x00000004 |
| 692 | #define PCIE_DPLL3_LOCAL_PLL_PWD_GET(x) (((x) & PCIE_DPLL3_LOCAL_PLL_PWD_MASK) >> PCIE_DPLL3_LOCAL_PLL_PWD_LSB) |
| 693 | #define PCIE_DPLL3_LOCAL_PLL_PWD_SET(x) (((x) << PCIE_DPLL3_LOCAL_PLL_PWD_LSB) & PCIE_DPLL3_LOCAL_PLL_PWD_MASK) |
| 694 | #define PCIE_DPLL3_LOCAL_PLL_PWD_RESET 0x0 // 0 |
| 695 | #define PCIE_DPLL3_SPARE_MSB 1 |
| 696 | #define PCIE_DPLL3_SPARE_LSB 0 |
| 697 | #define PCIE_DPLL3_SPARE_MASK 0x00000003 |
| 698 | #define PCIE_DPLL3_SPARE_GET(x) (((x) & PCIE_DPLL3_SPARE_MASK) >> PCIE_DPLL3_SPARE_LSB) |
| 699 | #define PCIE_DPLL3_SPARE_SET(x) (((x) << PCIE_DPLL3_SPARE_LSB) & PCIE_DPLL3_SPARE_MASK) |
| 700 | #define PCIE_DPLL3_SPARE_RESET 0x0 // 0 |
| 701 | #define PCIE_DPLL3_ADDR 0x0008 |
| 702 | #define PCIE_DPLL3_OFFSET 0x0008 |
| 703 | #define PCIE_DPLL3_SW_MASK 0xffffffff |
| 704 | #define PCIE_DPLL3_RSTMASK 0xffffffff |
| 705 | #define PCIE_DPLL3_RESET 0x00000000 |
| 706 | #define PCIE_DPLL3_ADDRESS 0x18116c08 |
| 707 | |
| 708 | #define PCIE_DPLL1_REFDIV_MSB 31 |
| 709 | #define PCIE_DPLL1_REFDIV_LSB 27 |
| 710 | #define PCIE_DPLL1_REFDIV_MASK 0xf8000000 |
| 711 | #define PCIE_DPLL1_REFDIV_GET(x) (((x) & PCIE_DPLL1_REFDIV_MASK) >> PCIE_DPLL1_REFDIV_LSB) |
| 712 | #define PCIE_DPLL1_REFDIV_SET(x) (((x) << PCIE_DPLL1_REFDIV_LSB) & PCIE_DPLL1_REFDIV_MASK) |
| 713 | #define PCIE_DPLL1_REFDIV_RESET 0x1 // 1 |
| 714 | #define PCIE_DPLL1_NINT_MSB 26 |
| 715 | #define PCIE_DPLL1_NINT_LSB 18 |
| 716 | #define PCIE_DPLL1_NINT_MASK 0x07fc0000 |
| 717 | #define PCIE_DPLL1_NINT_GET(x) (((x) & PCIE_DPLL1_NINT_MASK) >> PCIE_DPLL1_NINT_LSB) |
| 718 | #define PCIE_DPLL1_NINT_SET(x) (((x) << PCIE_DPLL1_NINT_LSB) & PCIE_DPLL1_NINT_MASK) |
| 719 | #define PCIE_DPLL1_NINT_RESET 0x10 // 16 |
| 720 | #define PCIE_DPLL1_NFRAC_MSB 17 |
| 721 | #define PCIE_DPLL1_NFRAC_LSB 0 |
| 722 | #define PCIE_DPLL1_NFRAC_MASK 0x0003ffff |
| 723 | #define PCIE_DPLL1_NFRAC_GET(x) (((x) & PCIE_DPLL1_NFRAC_MASK) >> PCIE_DPLL1_NFRAC_LSB) |
| 724 | #define PCIE_DPLL1_NFRAC_SET(x) (((x) << PCIE_DPLL1_NFRAC_LSB) & PCIE_DPLL1_NFRAC_MASK) |
| 725 | #define PCIE_DPLL1_NFRAC_RESET 0x0 // 0 |
| 726 | #define PCIE_DPLL1_ADDR 0x0000 |
| 727 | #define PCIE_DPLL1_OFFSET 0x0000 |
| 728 | #define PCIE_DPLL1_SW_MASK 0xffffffff |
| 729 | #define PCIE_DPLL1_RSTMASK 0xffffffff |
| 730 | #define PCIE_DPLL1_RESET 0x08400000 |
| 731 | #define PCIE_DPLL1_ADDRESS 0x18116c00 |
| 732 | |
| 733 | #define DDR_DPLL2_LOCAL_PLL_MSB 31 |
| 734 | #define DDR_DPLL2_LOCAL_PLL_LSB 31 |
| 735 | #define DDR_DPLL2_LOCAL_PLL_MASK 0x80000000 |
| 736 | #define DDR_DPLL2_LOCAL_PLL_GET(x) (((x) & DDR_DPLL2_LOCAL_PLL_MASK) >> DDR_DPLL2_LOCAL_PLL_LSB) |
| 737 | #define DDR_DPLL2_LOCAL_PLL_SET(x) (((x) << DDR_DPLL2_LOCAL_PLL_LSB) & DDR_DPLL2_LOCAL_PLL_MASK) |
| 738 | #define DDR_DPLL2_LOCAL_PLL_RESET 0x0 // 0 |
| 739 | #define DDR_DPLL2_KI_MSB 30 |
| 740 | #define DDR_DPLL2_KI_LSB 29 |
| 741 | #define DDR_DPLL2_KI_MASK 0x60000000 |
| 742 | #define DDR_DPLL2_KI_GET(x) (((x) & DDR_DPLL2_KI_MASK) >> DDR_DPLL2_KI_LSB) |
| 743 | #define DDR_DPLL2_KI_SET(x) (((x) << DDR_DPLL2_KI_LSB) & DDR_DPLL2_KI_MASK) |
| 744 | #define DDR_DPLL2_KI_RESET 0x2 // 2 |
| 745 | #define DDR_DPLL2_KD_MSB 28 |
| 746 | #define DDR_DPLL2_KD_LSB 25 |
| 747 | #define DDR_DPLL2_KD_MASK 0x1e000000 |
| 748 | #define DDR_DPLL2_KD_GET(x) (((x) & DDR_DPLL2_KD_MASK) >> DDR_DPLL2_KD_LSB) |
| 749 | #define DDR_DPLL2_KD_SET(x) (((x) << DDR_DPLL2_KD_LSB) & DDR_DPLL2_KD_MASK) |
| 750 | #define DDR_DPLL2_KD_RESET 0xa // 10 |
| 751 | #define DDR_DPLL2_EN_NEGTRIG_MSB 24 |
| 752 | #define DDR_DPLL2_EN_NEGTRIG_LSB 24 |
| 753 | #define DDR_DPLL2_EN_NEGTRIG_MASK 0x01000000 |
| 754 | #define DDR_DPLL2_EN_NEGTRIG_GET(x) (((x) & DDR_DPLL2_EN_NEGTRIG_MASK) >> DDR_DPLL2_EN_NEGTRIG_LSB) |
| 755 | #define DDR_DPLL2_EN_NEGTRIG_SET(x) (((x) << DDR_DPLL2_EN_NEGTRIG_LSB) & DDR_DPLL2_EN_NEGTRIG_MASK) |
| 756 | #define DDR_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 |
| 757 | #define DDR_DPLL2_SEL_1SDM_MSB 23 |
| 758 | #define DDR_DPLL2_SEL_1SDM_LSB 23 |
| 759 | #define DDR_DPLL2_SEL_1SDM_MASK 0x00800000 |
| 760 | #define DDR_DPLL2_SEL_1SDM_GET(x) (((x) & DDR_DPLL2_SEL_1SDM_MASK) >> DDR_DPLL2_SEL_1SDM_LSB) |
| 761 | #define DDR_DPLL2_SEL_1SDM_SET(x) (((x) << DDR_DPLL2_SEL_1SDM_LSB) & DDR_DPLL2_SEL_1SDM_MASK) |
| 762 | #define DDR_DPLL2_SEL_1SDM_RESET 0x0 // 0 |
| 763 | #define DDR_DPLL2_PLL_PWD_MSB 22 |
| 764 | #define DDR_DPLL2_PLL_PWD_LSB 22 |
| 765 | #define DDR_DPLL2_PLL_PWD_MASK 0x00400000 |
| 766 | #define DDR_DPLL2_PLL_PWD_GET(x) (((x) & DDR_DPLL2_PLL_PWD_MASK) >> DDR_DPLL2_PLL_PWD_LSB) |
| 767 | #define DDR_DPLL2_PLL_PWD_SET(x) (((x) << DDR_DPLL2_PLL_PWD_LSB) & DDR_DPLL2_PLL_PWD_MASK) |
| 768 | #define DDR_DPLL2_PLL_PWD_RESET 0x1 // 1 |
| 769 | #define DDR_DPLL2_OUTDIV_MSB 21 |
| 770 | #define DDR_DPLL2_OUTDIV_LSB 19 |
| 771 | #define DDR_DPLL2_OUTDIV_MASK 0x00380000 |
| 772 | #define DDR_DPLL2_OUTDIV_GET(x) (((x) & DDR_DPLL2_OUTDIV_MASK) >> DDR_DPLL2_OUTDIV_LSB) |
| 773 | #define DDR_DPLL2_OUTDIV_SET(x) (((x) << DDR_DPLL2_OUTDIV_LSB) & DDR_DPLL2_OUTDIV_MASK) |
| 774 | #define DDR_DPLL2_OUTDIV_RESET 0x1 // 1 |
| 775 | #define DDR_DPLL2_PHASE_SHIFT_MSB 18 |
| 776 | #define DDR_DPLL2_PHASE_SHIFT_LSB 12 |
| 777 | #define DDR_DPLL2_PHASE_SHIFT_MASK 0x0007f000 |
| 778 | #define DDR_DPLL2_PHASE_SHIFT_GET(x) (((x) & DDR_DPLL2_PHASE_SHIFT_MASK) >> DDR_DPLL2_PHASE_SHIFT_LSB) |
| 779 | #define DDR_DPLL2_PHASE_SHIFT_SET(x) (((x) << DDR_DPLL2_PHASE_SHIFT_LSB) & DDR_DPLL2_PHASE_SHIFT_MASK) |
| 780 | #define DDR_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 |
| 781 | #define DDR_DPLL2_TESTIN_MSB 11 |
| 782 | #define DDR_DPLL2_TESTIN_LSB 2 |
| 783 | #define DDR_DPLL2_TESTIN_MASK 0x00000ffc |
| 784 | #define DDR_DPLL2_TESTIN_GET(x) (((x) & DDR_DPLL2_TESTIN_MASK) >> DDR_DPLL2_TESTIN_LSB) |
| 785 | #define DDR_DPLL2_TESTIN_SET(x) (((x) << DDR_DPLL2_TESTIN_LSB) & DDR_DPLL2_TESTIN_MASK) |
| 786 | #define DDR_DPLL2_TESTIN_RESET 0x0 // 0 |
| 787 | #define DDR_DPLL2_SEL_COUNT_MSB 1 |
| 788 | #define DDR_DPLL2_SEL_COUNT_LSB 1 |
| 789 | #define DDR_DPLL2_SEL_COUNT_MASK 0x00000002 |
| 790 | #define DDR_DPLL2_SEL_COUNT_GET(x) (((x) & DDR_DPLL2_SEL_COUNT_MASK) >> DDR_DPLL2_SEL_COUNT_LSB) |
| 791 | #define DDR_DPLL2_SEL_COUNT_SET(x) (((x) << DDR_DPLL2_SEL_COUNT_LSB) & DDR_DPLL2_SEL_COUNT_MASK) |
| 792 | #define DDR_DPLL2_SEL_COUNT_RESET 0x0 // 0 |
| 793 | #define DDR_DPLL2_RESET_TEST_MSB 0 |
| 794 | #define DDR_DPLL2_RESET_TEST_LSB 0 |
| 795 | #define DDR_DPLL2_RESET_TEST_MASK 0x00000001 |
| 796 | #define DDR_DPLL2_RESET_TEST_GET(x) (((x) & DDR_DPLL2_RESET_TEST_MASK) >> DDR_DPLL2_RESET_TEST_LSB) |
| 797 | #define DDR_DPLL2_RESET_TEST_SET(x) (((x) << DDR_DPLL2_RESET_TEST_LSB) & DDR_DPLL2_RESET_TEST_MASK) |
| 798 | #define DDR_DPLL2_RESET_TEST_RESET 0x0 // 0 |
| 799 | #define DDR_DPLL2_ADDRESS 0x18116244 |
| 800 | |
| 801 | #define CPU_DPLL2_LOCAL_PLL_MSB 31 |
| 802 | #define CPU_DPLL2_LOCAL_PLL_LSB 31 |
| 803 | #define CPU_DPLL2_LOCAL_PLL_MASK 0x80000000 |
| 804 | #define CPU_DPLL2_LOCAL_PLL_GET(x) (((x) & CPU_DPLL2_LOCAL_PLL_MASK) >> CPU_DPLL2_LOCAL_PLL_LSB) |
| 805 | #define CPU_DPLL2_LOCAL_PLL_SET(x) (((x) << CPU_DPLL2_LOCAL_PLL_LSB) & CPU_DPLL2_LOCAL_PLL_MASK) |
| 806 | #define CPU_DPLL2_LOCAL_PLL_RESET 0x0 // 0 |
| 807 | #define CPU_DPLL2_KI_MSB 30 |
| 808 | #define CPU_DPLL2_KI_LSB 29 |
| 809 | #define CPU_DPLL2_KI_MASK 0x60000000 |
| 810 | #define CPU_DPLL2_KI_GET(x) (((x) & CPU_DPLL2_KI_MASK) >> CPU_DPLL2_KI_LSB) |
| 811 | #define CPU_DPLL2_KI_SET(x) (((x) << CPU_DPLL2_KI_LSB) & CPU_DPLL2_KI_MASK) |
| 812 | #define CPU_DPLL2_KI_RESET 0x2 // 2 |
| 813 | #define CPU_DPLL2_KD_MSB 28 |
| 814 | #define CPU_DPLL2_KD_LSB 25 |
| 815 | #define CPU_DPLL2_KD_MASK 0x1e000000 |
| 816 | #define CPU_DPLL2_KD_GET(x) (((x) & CPU_DPLL2_KD_MASK) >> CPU_DPLL2_KD_LSB) |
| 817 | #define CPU_DPLL2_KD_SET(x) (((x) << CPU_DPLL2_KD_LSB) & CPU_DPLL2_KD_MASK) |
| 818 | #define CPU_DPLL2_KD_RESET 0xa // 10 |
| 819 | #define CPU_DPLL2_EN_NEGTRIG_MSB 24 |
| 820 | #define CPU_DPLL2_EN_NEGTRIG_LSB 24 |
| 821 | #define CPU_DPLL2_EN_NEGTRIG_MASK 0x01000000 |
| 822 | #define CPU_DPLL2_EN_NEGTRIG_GET(x) (((x) & CPU_DPLL2_EN_NEGTRIG_MASK) >> CPU_DPLL2_EN_NEGTRIG_LSB) |
| 823 | #define CPU_DPLL2_EN_NEGTRIG_SET(x) (((x) << CPU_DPLL2_EN_NEGTRIG_LSB) & CPU_DPLL2_EN_NEGTRIG_MASK) |
| 824 | #define CPU_DPLL2_EN_NEGTRIG_RESET 0x0 // 0 |
| 825 | #define CPU_DPLL2_SEL_1SDM_MSB 23 |
| 826 | #define CPU_DPLL2_SEL_1SDM_LSB 23 |
| 827 | #define CPU_DPLL2_SEL_1SDM_MASK 0x00800000 |
| 828 | #define CPU_DPLL2_SEL_1SDM_GET(x) (((x) & CPU_DPLL2_SEL_1SDM_MASK) >> CPU_DPLL2_SEL_1SDM_LSB) |
| 829 | #define CPU_DPLL2_SEL_1SDM_SET(x) (((x) << CPU_DPLL2_SEL_1SDM_LSB) & CPU_DPLL2_SEL_1SDM_MASK) |
| 830 | #define CPU_DPLL2_SEL_1SDM_RESET 0x0 // 0 |
| 831 | #define CPU_DPLL2_PLL_PWD_MSB 22 |
| 832 | #define CPU_DPLL2_PLL_PWD_LSB 22 |
| 833 | #define CPU_DPLL2_PLL_PWD_MASK 0x00400000 |
| 834 | #define CPU_DPLL2_PLL_PWD_GET(x) (((x) & CPU_DPLL2_PLL_PWD_MASK) >> CPU_DPLL2_PLL_PWD_LSB) |
| 835 | #define CPU_DPLL2_PLL_PWD_SET(x) (((x) << CPU_DPLL2_PLL_PWD_LSB) & CPU_DPLL2_PLL_PWD_MASK) |
| 836 | #define CPU_DPLL2_PLL_PWD_RESET 0x1 // 1 |
| 837 | #define CPU_DPLL2_OUTDIV_MSB 21 |
| 838 | #define CPU_DPLL2_OUTDIV_LSB 19 |
| 839 | #define CPU_DPLL2_OUTDIV_MASK 0x00380000 |
| 840 | #define CPU_DPLL2_OUTDIV_GET(x) (((x) & CPU_DPLL2_OUTDIV_MASK) >> CPU_DPLL2_OUTDIV_LSB) |
| 841 | #define CPU_DPLL2_OUTDIV_SET(x) (((x) << CPU_DPLL2_OUTDIV_LSB) & CPU_DPLL2_OUTDIV_MASK) |
| 842 | #define CPU_DPLL2_OUTDIV_RESET 0x1 // 1 |
| 843 | #define CPU_DPLL2_PHASE_SHIFT_MSB 18 |
| 844 | #define CPU_DPLL2_PHASE_SHIFT_LSB 12 |
| 845 | #define CPU_DPLL2_PHASE_SHIFT_MASK 0x0007f000 |
| 846 | #define CPU_DPLL2_PHASE_SHIFT_GET(x) (((x) & CPU_DPLL2_PHASE_SHIFT_MASK) >> CPU_DPLL2_PHASE_SHIFT_LSB) |
| 847 | #define CPU_DPLL2_PHASE_SHIFT_SET(x) (((x) << CPU_DPLL2_PHASE_SHIFT_LSB) & CPU_DPLL2_PHASE_SHIFT_MASK) |
| 848 | #define CPU_DPLL2_PHASE_SHIFT_RESET 0x0 // 0 |
| 849 | #define CPU_DPLL2_TESTIN_MSB 11 |
| 850 | #define CPU_DPLL2_TESTIN_LSB 2 |
| 851 | #define CPU_DPLL2_TESTIN_MASK 0x00000ffc |
| 852 | #define CPU_DPLL2_TESTIN_GET(x) (((x) & CPU_DPLL2_TESTIN_MASK) >> CPU_DPLL2_TESTIN_LSB) |
| 853 | #define CPU_DPLL2_TESTIN_SET(x) (((x) << CPU_DPLL2_TESTIN_LSB) & CPU_DPLL2_TESTIN_MASK) |
| 854 | #define CPU_DPLL2_TESTIN_RESET 0x0 // 0 |
| 855 | #define CPU_DPLL2_SEL_COUNT_MSB 1 |
| 856 | #define CPU_DPLL2_SEL_COUNT_LSB 1 |
| 857 | #define CPU_DPLL2_SEL_COUNT_MASK 0x00000002 |
| 858 | #define CPU_DPLL2_SEL_COUNT_GET(x) (((x) & CPU_DPLL2_SEL_COUNT_MASK) >> CPU_DPLL2_SEL_COUNT_LSB) |
| 859 | #define CPU_DPLL2_SEL_COUNT_SET(x) (((x) << CPU_DPLL2_SEL_COUNT_LSB) & CPU_DPLL2_SEL_COUNT_MASK) |
| 860 | #define CPU_DPLL2_SEL_COUNT_RESET 0x0 // 0 |
| 861 | #define CPU_DPLL2_RESET_TEST_MSB 0 |
| 862 | #define CPU_DPLL2_RESET_TEST_LSB 0 |
| 863 | #define CPU_DPLL2_RESET_TEST_MASK 0x00000001 |
| 864 | #define CPU_DPLL2_RESET_TEST_GET(x) (((x) & CPU_DPLL2_RESET_TEST_MASK) >> CPU_DPLL2_RESET_TEST_LSB) |
| 865 | #define CPU_DPLL2_RESET_TEST_SET(x) (((x) << CPU_DPLL2_RESET_TEST_LSB) & CPU_DPLL2_RESET_TEST_MASK) |
| 866 | #define CPU_DPLL2_RESET_TEST_RESET 0x0 // 0 |
| 867 | #define CPU_DPLL2_ADDRESS 0x181161c4 |
| 868 | |
| 869 | #define DDR_RD_DATA_THIS_CYCLE_ADDRESS 0x18000018 |
| 870 | |
| Prabhu Jayakumar | 4f520fb | 2017-01-09 17:05:45 +0530 | [diff] [blame] | 871 | #define TAP_CONTROL_0_ADDRESS 0x1800001c |
| Prabhu Jayakumar | a700195 | 2016-11-14 18:58:54 +0530 | [diff] [blame] | 872 | #define TAP_CONTROL_1_ADDRESS 0x18000020 |
| 873 | #define TAP_CONTROL_2_ADDRESS 0x18000024 |
| 874 | #define TAP_CONTROL_3_ADDRESS 0x18000028 |
| 875 | |
| 876 | #define DDR_BURST_CPU_PRIORITY_MSB 31 |
| 877 | #define DDR_BURST_CPU_PRIORITY_LSB 31 |
| 878 | #define DDR_BURST_CPU_PRIORITY_MASK 0x80000000 |
| 879 | #define DDR_BURST_CPU_PRIORITY_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB) |
| 880 | #define DDR_BURST_CPU_PRIORITY_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK) |
| 881 | #define DDR_BURST_CPU_PRIORITY_RESET 0x0 // 0 |
| 882 | #define DDR_BURST_CPU_PRIORITY_BE_MSB 30 |
| 883 | #define DDR_BURST_CPU_PRIORITY_BE_LSB 30 |
| 884 | #define DDR_BURST_CPU_PRIORITY_BE_MASK 0x40000000 |
| 885 | #define DDR_BURST_CPU_PRIORITY_BE_GET(x) (((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB) |
| 886 | #define DDR_BURST_CPU_PRIORITY_BE_SET(x) (((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK) |
| 887 | #define DDR_BURST_CPU_PRIORITY_BE_RESET 0x1 // 1 |
| 888 | #define DDR_BURST_ENABLE_RWP_MASK_MSB 29 |
| 889 | #define DDR_BURST_ENABLE_RWP_MASK_LSB 28 |
| 890 | #define DDR_BURST_ENABLE_RWP_MASK_MASK 0x30000000 |
| 891 | #define DDR_BURST_ENABLE_RWP_MASK_GET(x) (((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB) |
| 892 | #define DDR_BURST_ENABLE_RWP_MASK_SET(x) (((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK) |
| 893 | #define DDR_BURST_ENABLE_RWP_MASK_RESET 0x3 // 3 |
| 894 | #define DDR_BURST_MAX_WRITE_BURST_MSB 27 |
| 895 | #define DDR_BURST_MAX_WRITE_BURST_LSB 24 |
| 896 | #define DDR_BURST_MAX_WRITE_BURST_MASK 0x0f000000 |
| 897 | #define DDR_BURST_MAX_WRITE_BURST_GET(x) (((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB) |
| 898 | #define DDR_BURST_MAX_WRITE_BURST_SET(x) (((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK) |
| 899 | #define DDR_BURST_MAX_WRITE_BURST_RESET 0x4 // 4 |
| 900 | #define DDR_BURST_MAX_READ_BURST_MSB 23 |
| 901 | #define DDR_BURST_MAX_READ_BURST_LSB 20 |
| 902 | #define DDR_BURST_MAX_READ_BURST_MASK 0x00f00000 |
| 903 | #define DDR_BURST_MAX_READ_BURST_GET(x) (((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB) |
| 904 | #define DDR_BURST_MAX_READ_BURST_SET(x) (((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK) |
| 905 | #define DDR_BURST_MAX_READ_BURST_RESET 0x4 // 4 |
| 906 | #define DDR_BURST_CPU_MAX_BL_MSB 19 |
| 907 | #define DDR_BURST_CPU_MAX_BL_LSB 16 |
| 908 | #define DDR_BURST_CPU_MAX_BL_MASK 0x000f0000 |
| 909 | #define DDR_BURST_CPU_MAX_BL_GET(x) (((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB) |
| 910 | #define DDR_BURST_CPU_MAX_BL_SET(x) (((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK) |
| 911 | #define DDR_BURST_CPU_MAX_BL_RESET 0x3 // 3 |
| 912 | #define DDR_BURST_USB_MAX_BL_MSB 15 |
| 913 | #define DDR_BURST_USB_MAX_BL_LSB 12 |
| 914 | #define DDR_BURST_USB_MAX_BL_MASK 0x0000f000 |
| 915 | #define DDR_BURST_USB_MAX_BL_GET(x) (((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB) |
| 916 | #define DDR_BURST_USB_MAX_BL_SET(x) (((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK) |
| 917 | #define DDR_BURST_USB_MAX_BL_RESET 0x4 // 4 |
| 918 | #define DDR_BURST_PCIE_MAX_BL_MSB 11 |
| 919 | #define DDR_BURST_PCIE_MAX_BL_LSB 8 |
| 920 | #define DDR_BURST_PCIE_MAX_BL_MASK 0x00000f00 |
| 921 | #define DDR_BURST_PCIE_MAX_BL_GET(x) (((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB) |
| 922 | #define DDR_BURST_PCIE_MAX_BL_SET(x) (((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK) |
| 923 | #define DDR_BURST_PCIE_MAX_BL_RESET 0x3 // 3 |
| 924 | #define DDR_BURST_GE1_MAX_BL_MSB 7 |
| 925 | #define DDR_BURST_GE1_MAX_BL_LSB 4 |
| 926 | #define DDR_BURST_GE1_MAX_BL_MASK 0x000000f0 |
| 927 | #define DDR_BURST_GE1_MAX_BL_GET(x) (((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB) |
| 928 | #define DDR_BURST_GE1_MAX_BL_SET(x) (((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK) |
| 929 | #define DDR_BURST_GE1_MAX_BL_RESET 0x3 // 3 |
| 930 | #define DDR_BURST_GE0_MAX_BL_MSB 3 |
| 931 | #define DDR_BURST_GE0_MAX_BL_LSB 0 |
| 932 | #define DDR_BURST_GE0_MAX_BL_MASK 0x0000000f |
| 933 | #define DDR_BURST_GE0_MAX_BL_GET(x) (((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB) |
| 934 | #define DDR_BURST_GE0_MAX_BL_SET(x) (((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK) |
| 935 | #define DDR_BURST_GE0_MAX_BL_RESET 0x3 // 3 |
| 936 | #define DDR_BURST_ADDRESS 0x180000c4 |
| 937 | |
| 938 | #define DDR_BURST2_WMAC_MAX_BL_MSB 3 |
| 939 | #define DDR_BURST2_WMAC_MAX_BL_LSB 0 |
| 940 | #define DDR_BURST2_WMAC_MAX_BL_MASK 0x0000000f |
| 941 | #define DDR_BURST2_WMAC_MAX_BL_GET(x) (((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB) |
| 942 | #define DDR_BURST2_WMAC_MAX_BL_SET(x) (((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK) |
| 943 | #define DDR_BURST2_WMAC_MAX_BL_RESET 0x3 // 3 |
| 944 | #define DDR_BURST2_ADDRESS 0x180000c8 |
| 945 | |
| 946 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB 19 |
| 947 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB 0 |
| 948 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK 0x000fffff |
| 949 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x) (((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) |
| 950 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x) (((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) |
| 951 | #define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_RESET 0x8000 // 32768 |
| 952 | #define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS 0x180000cc |
| 953 | |
| 954 | #define PMU1_ADDRESS 0x18116c40 |
| 955 | |
| 956 | #define PMU2_SWREGMSB_MSB 31 |
| 957 | #define PMU2_SWREGMSB_LSB 22 |
| 958 | #define PMU2_SWREGMSB_MASK 0xffc00000 |
| 959 | #define PMU2_SWREGMSB_GET(x) (((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB) |
| 960 | #define PMU2_SWREGMSB_SET(x) (((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK) |
| 961 | #define PMU2_SWREGMSB_RESET 0x0 // 0 |
| 962 | #define PMU2_PGM_MSB 21 |
| 963 | #define PMU2_PGM_LSB 21 |
| 964 | #define PMU2_PGM_MASK 0x00200000 |
| 965 | #define PMU2_PGM_GET(x) (((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB) |
| 966 | #define PMU2_PGM_SET(x) (((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK) |
| 967 | #define PMU2_PGM_RESET 0x0 // 0 |
| 968 | #define PMU2_LDO_TUNE_MSB 20 |
| 969 | #define PMU2_LDO_TUNE_LSB 19 |
| 970 | #define PMU2_LDO_TUNE_MASK 0x00180000 |
| 971 | #define PMU2_LDO_TUNE_GET(x) (((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB) |
| 972 | #define PMU2_LDO_TUNE_SET(x) (((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK) |
| 973 | #define PMU2_LDO_TUNE_RESET 0x0 // 0 |
| 974 | #define PMU2_PWDLDO_DDR_MSB 18 |
| 975 | #define PMU2_PWDLDO_DDR_LSB 18 |
| 976 | #define PMU2_PWDLDO_DDR_MASK 0x00040000 |
| 977 | #define PMU2_PWDLDO_DDR_GET(x) (((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB) |
| 978 | #define PMU2_PWDLDO_DDR_SET(x) (((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK) |
| 979 | #define PMU2_PWDLDO_DDR_RESET 0x0 // 0 |
| 980 | #define PMU2_LPOPWD_MSB 17 |
| 981 | #define PMU2_LPOPWD_LSB 17 |
| 982 | #define PMU2_LPOPWD_MASK 0x00020000 |
| 983 | #define PMU2_LPOPWD_GET(x) (((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB) |
| 984 | #define PMU2_LPOPWD_SET(x) (((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK) |
| 985 | #define PMU2_LPOPWD_RESET 0x0 // 0 |
| 986 | #define PMU2_SPARE_MSB 16 |
| 987 | #define PMU2_SPARE_LSB 0 |
| 988 | #define PMU2_SPARE_MASK 0x0001ffff |
| 989 | #define PMU2_SPARE_GET(x) (((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB) |
| 990 | #define PMU2_SPARE_SET(x) (((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK) |
| 991 | #define PMU2_SPARE_RESET 0x0 // 0 |
| 992 | #define PMU2_ADDRESS 0x18116c44 |
| 993 | |
| 994 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_MSB 31 |
| 995 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_LSB 24 |
| 996 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_MASK 0xff000000 |
| 997 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_GET(x) (((x) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) >> PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) |
| 998 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_SET(x) (((x) << PHY_CTRL0_LOOPBACK_ERR_CNT_LSB) & PHY_CTRL0_LOOPBACK_ERR_CNT_MASK) |
| 999 | #define PHY_CTRL0_LOOPBACK_ERR_CNT_RESET 0x0 // 0 |
| 1000 | #define PHY_CTRL0_DIG_LOOPBACK_EN_MSB 23 |
| 1001 | #define PHY_CTRL0_DIG_LOOPBACK_EN_LSB 23 |
| 1002 | #define PHY_CTRL0_DIG_LOOPBACK_EN_MASK 0x00800000 |
| 1003 | #define PHY_CTRL0_DIG_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) >> PHY_CTRL0_DIG_LOOPBACK_EN_LSB) |
| 1004 | #define PHY_CTRL0_DIG_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_DIG_LOOPBACK_EN_LSB) & PHY_CTRL0_DIG_LOOPBACK_EN_MASK) |
| 1005 | #define PHY_CTRL0_DIG_LOOPBACK_EN_RESET 0x0 // 0 |
| 1006 | #define PHY_CTRL0_ANA_LOOPBACK_EN_MSB 22 |
| 1007 | #define PHY_CTRL0_ANA_LOOPBACK_EN_LSB 22 |
| 1008 | #define PHY_CTRL0_ANA_LOOPBACK_EN_MASK 0x00400000 |
| 1009 | #define PHY_CTRL0_ANA_LOOPBACK_EN_GET(x) (((x) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) >> PHY_CTRL0_ANA_LOOPBACK_EN_LSB) |
| 1010 | #define PHY_CTRL0_ANA_LOOPBACK_EN_SET(x) (((x) << PHY_CTRL0_ANA_LOOPBACK_EN_LSB) & PHY_CTRL0_ANA_LOOPBACK_EN_MASK) |
| 1011 | #define PHY_CTRL0_ANA_LOOPBACK_EN_RESET 0x0 // 0 |
| 1012 | #define PHY_CTRL0_TX_PATTERN_EN_MSB 21 |
| 1013 | #define PHY_CTRL0_TX_PATTERN_EN_LSB 21 |
| 1014 | #define PHY_CTRL0_TX_PATTERN_EN_MASK 0x00200000 |
| 1015 | #define PHY_CTRL0_TX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_TX_PATTERN_EN_MASK) >> PHY_CTRL0_TX_PATTERN_EN_LSB) |
| 1016 | #define PHY_CTRL0_TX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_TX_PATTERN_EN_LSB) & PHY_CTRL0_TX_PATTERN_EN_MASK) |
| 1017 | #define PHY_CTRL0_TX_PATTERN_EN_RESET 0x0 // 0 |
| 1018 | #define PHY_CTRL0_RX_PATTERN_EN_MSB 20 |
| 1019 | #define PHY_CTRL0_RX_PATTERN_EN_LSB 20 |
| 1020 | #define PHY_CTRL0_RX_PATTERN_EN_MASK 0x00100000 |
| 1021 | #define PHY_CTRL0_RX_PATTERN_EN_GET(x) (((x) & PHY_CTRL0_RX_PATTERN_EN_MASK) >> PHY_CTRL0_RX_PATTERN_EN_LSB) |
| 1022 | #define PHY_CTRL0_RX_PATTERN_EN_SET(x) (((x) << PHY_CTRL0_RX_PATTERN_EN_LSB) & PHY_CTRL0_RX_PATTERN_EN_MASK) |
| 1023 | #define PHY_CTRL0_RX_PATTERN_EN_RESET 0x0 // 0 |
| 1024 | #define PHY_CTRL0_TEST_SPEED_SELECT_MSB 19 |
| 1025 | #define PHY_CTRL0_TEST_SPEED_SELECT_LSB 19 |
| 1026 | #define PHY_CTRL0_TEST_SPEED_SELECT_MASK 0x00080000 |
| 1027 | #define PHY_CTRL0_TEST_SPEED_SELECT_GET(x) (((x) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) >> PHY_CTRL0_TEST_SPEED_SELECT_LSB) |
| 1028 | #define PHY_CTRL0_TEST_SPEED_SELECT_SET(x) (((x) << PHY_CTRL0_TEST_SPEED_SELECT_LSB) & PHY_CTRL0_TEST_SPEED_SELECT_MASK) |
| 1029 | #define PHY_CTRL0_TEST_SPEED_SELECT_RESET 0x0 // 0 |
| 1030 | #define PHY_CTRL0_PLL_OVERIDE_MSB 18 |
| 1031 | #define PHY_CTRL0_PLL_OVERIDE_LSB 18 |
| 1032 | #define PHY_CTRL0_PLL_OVERIDE_MASK 0x00040000 |
| 1033 | #define PHY_CTRL0_PLL_OVERIDE_GET(x) (((x) & PHY_CTRL0_PLL_OVERIDE_MASK) >> PHY_CTRL0_PLL_OVERIDE_LSB) |
| 1034 | #define PHY_CTRL0_PLL_OVERIDE_SET(x) (((x) << PHY_CTRL0_PLL_OVERIDE_LSB) & PHY_CTRL0_PLL_OVERIDE_MASK) |
| 1035 | #define PHY_CTRL0_PLL_OVERIDE_RESET 0x0 // 0 |
| 1036 | #define PHY_CTRL0_PLL_MOD_MSB 17 |
| 1037 | #define PHY_CTRL0_PLL_MOD_LSB 15 |
| 1038 | #define PHY_CTRL0_PLL_MOD_MASK 0x00038000 |
| 1039 | #define PHY_CTRL0_PLL_MOD_GET(x) (((x) & PHY_CTRL0_PLL_MOD_MASK) >> PHY_CTRL0_PLL_MOD_LSB) |
| 1040 | #define PHY_CTRL0_PLL_MOD_SET(x) (((x) << PHY_CTRL0_PLL_MOD_LSB) & PHY_CTRL0_PLL_MOD_MASK) |
| 1041 | #define PHY_CTRL0_PLL_MOD_RESET 0x0 // 0 |
| 1042 | #define PHY_CTRL0_PLL_DIV_MSB 14 |
| 1043 | #define PHY_CTRL0_PLL_DIV_LSB 6 |
| 1044 | #define PHY_CTRL0_PLL_DIV_MASK 0x00007fc0 |
| 1045 | #define PHY_CTRL0_PLL_DIV_GET(x) (((x) & PHY_CTRL0_PLL_DIV_MASK) >> PHY_CTRL0_PLL_DIV_LSB) |
| 1046 | #define PHY_CTRL0_PLL_DIV_SET(x) (((x) << PHY_CTRL0_PLL_DIV_LSB) & PHY_CTRL0_PLL_DIV_MASK) |
| 1047 | #define PHY_CTRL0_PLL_DIV_RESET 0x0 // 0 |
| 1048 | #define PHY_CTRL0_PLL_RS_MSB 5 |
| 1049 | #define PHY_CTRL0_PLL_RS_LSB 3 |
| 1050 | #define PHY_CTRL0_PLL_RS_MASK 0x00000038 |
| 1051 | #define PHY_CTRL0_PLL_RS_GET(x) (((x) & PHY_CTRL0_PLL_RS_MASK) >> PHY_CTRL0_PLL_RS_LSB) |
| 1052 | #define PHY_CTRL0_PLL_RS_SET(x) (((x) << PHY_CTRL0_PLL_RS_LSB) & PHY_CTRL0_PLL_RS_MASK) |
| 1053 | #define PHY_CTRL0_PLL_RS_RESET 0x2 // 2 |
| 1054 | #define PHY_CTRL0_PLL_ICP_MSB 2 |
| 1055 | #define PHY_CTRL0_PLL_ICP_LSB 0 |
| 1056 | #define PHY_CTRL0_PLL_ICP_MASK 0x00000007 |
| 1057 | #define PHY_CTRL0_PLL_ICP_GET(x) (((x) & PHY_CTRL0_PLL_ICP_MASK) >> PHY_CTRL0_PLL_ICP_LSB) |
| 1058 | #define PHY_CTRL0_PLL_ICP_SET(x) (((x) << PHY_CTRL0_PLL_ICP_LSB) & PHY_CTRL0_PLL_ICP_MASK) |
| 1059 | #define PHY_CTRL0_PLL_ICP_RESET 0x5 // 5 |
| 1060 | #define PHY_CTRL0_ADDRESS 0x18116c80 |
| 1061 | #define PHY_CTRL0_OFFSET 0x0000 |
| 1062 | // SW modifiable bits |
| 1063 | #define PHY_CTRL0_SW_MASK 0xffffffff |
| 1064 | // bits defined at reset |
| 1065 | #define PHY_CTRL0_RSTMASK 0xffffffff |
| 1066 | // reset value (ignore bits undefined at reset) |
| 1067 | #define PHY_CTRL0_RESET 0x00000015 |
| 1068 | |
| 1069 | #define PHY_CTRL1_PLL_OBS_MODE_N_MSB 31 |
| 1070 | #define PHY_CTRL1_PLL_OBS_MODE_N_LSB 31 |
| 1071 | #define PHY_CTRL1_PLL_OBS_MODE_N_MASK 0x80000000 |
| 1072 | #define PHY_CTRL1_PLL_OBS_MODE_N_GET(x) (((x) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) >> PHY_CTRL1_PLL_OBS_MODE_N_LSB) |
| 1073 | #define PHY_CTRL1_PLL_OBS_MODE_N_SET(x) (((x) << PHY_CTRL1_PLL_OBS_MODE_N_LSB) & PHY_CTRL1_PLL_OBS_MODE_N_MASK) |
| 1074 | #define PHY_CTRL1_PLL_OBS_MODE_N_RESET 0x1 // 1 |
| 1075 | #define PHY_CTRL1_DISABLE_CLK_GATING_MSB 27 |
| 1076 | #define PHY_CTRL1_DISABLE_CLK_GATING_LSB 27 |
| 1077 | #define PHY_CTRL1_DISABLE_CLK_GATING_MASK 0x08000000 |
| 1078 | #define PHY_CTRL1_DISABLE_CLK_GATING_GET(x) (((x) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) >> PHY_CTRL1_DISABLE_CLK_GATING_LSB) |
| 1079 | #define PHY_CTRL1_DISABLE_CLK_GATING_SET(x) (((x) << PHY_CTRL1_DISABLE_CLK_GATING_LSB) & PHY_CTRL1_DISABLE_CLK_GATING_MASK) |
| 1080 | #define PHY_CTRL1_DISABLE_CLK_GATING_RESET 0x0 // 0 |
| 1081 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_MSB 26 |
| 1082 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_LSB 26 |
| 1083 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_MASK 0x04000000 |
| 1084 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_GET(x) (((x) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) >> PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) |
| 1085 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_SET(x) (((x) << PHY_CTRL1_ENABLE_REFCLK_GATE_LSB) & PHY_CTRL1_ENABLE_REFCLK_GATE_MASK) |
| 1086 | #define PHY_CTRL1_ENABLE_REFCLK_GATE_RESET 0x1 // 1 |
| 1087 | #define PHY_CTRL1_CLKOBS_SEL_MSB 25 |
| 1088 | #define PHY_CTRL1_CLKOBS_SEL_LSB 23 |
| 1089 | #define PHY_CTRL1_CLKOBS_SEL_MASK 0x03800000 |
| 1090 | #define PHY_CTRL1_CLKOBS_SEL_GET(x) (((x) & PHY_CTRL1_CLKOBS_SEL_MASK) >> PHY_CTRL1_CLKOBS_SEL_LSB) |
| 1091 | #define PHY_CTRL1_CLKOBS_SEL_SET(x) (((x) << PHY_CTRL1_CLKOBS_SEL_LSB) & PHY_CTRL1_CLKOBS_SEL_MASK) |
| 1092 | #define PHY_CTRL1_CLKOBS_SEL_RESET 0x0 // 0 |
| 1093 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MSB 22 |
| 1094 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB 21 |
| 1095 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK 0x00600000 |
| 1096 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) >> PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) |
| 1097 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_LSB) & PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_MASK) |
| 1098 | #define PHY_CTRL1_USE_PLL_LOCK_DLY_SEL_RESET 0x3 // 3 |
| 1099 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_MSB 20 |
| 1100 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_LSB 20 |
| 1101 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_MASK 0x00100000 |
| 1102 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_GET(x) (((x) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) >> PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) |
| 1103 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_SET(x) (((x) << PHY_CTRL1_USE_PLL_LOCKDETECT_LSB) & PHY_CTRL1_USE_PLL_LOCKDETECT_MASK) |
| 1104 | #define PHY_CTRL1_USE_PLL_LOCKDETECT_RESET 0x0 // 0 |
| 1105 | #define PHY_CTRL1_TX_PATTERN_SEL_MSB 19 |
| 1106 | #define PHY_CTRL1_TX_PATTERN_SEL_LSB 18 |
| 1107 | #define PHY_CTRL1_TX_PATTERN_SEL_MASK 0x000c0000 |
| 1108 | #define PHY_CTRL1_TX_PATTERN_SEL_GET(x) (((x) & PHY_CTRL1_TX_PATTERN_SEL_MASK) >> PHY_CTRL1_TX_PATTERN_SEL_LSB) |
| 1109 | #define PHY_CTRL1_TX_PATTERN_SEL_SET(x) (((x) << PHY_CTRL1_TX_PATTERN_SEL_LSB) & PHY_CTRL1_TX_PATTERN_SEL_MASK) |
| 1110 | #define PHY_CTRL1_TX_PATTERN_SEL_RESET 0x0 // 0 |
| 1111 | #define PHY_CTRL1_FORCE_SUSPEND_MSB 13 |
| 1112 | #define PHY_CTRL1_FORCE_SUSPEND_LSB 13 |
| 1113 | #define PHY_CTRL1_FORCE_SUSPEND_MASK 0x00002000 |
| 1114 | #define PHY_CTRL1_FORCE_SUSPEND_GET(x) (((x) & PHY_CTRL1_FORCE_SUSPEND_MASK) >> PHY_CTRL1_FORCE_SUSPEND_LSB) |
| 1115 | #define PHY_CTRL1_FORCE_SUSPEND_SET(x) (((x) << PHY_CTRL1_FORCE_SUSPEND_LSB) & PHY_CTRL1_FORCE_SUSPEND_MASK) |
| 1116 | #define PHY_CTRL1_FORCE_SUSPEND_RESET 0x0 // 0 |
| 1117 | #define PHY_CTRL1_NO_PLL_PWD_MSB 12 |
| 1118 | #define PHY_CTRL1_NO_PLL_PWD_LSB 12 |
| 1119 | #define PHY_CTRL1_NO_PLL_PWD_MASK 0x00001000 |
| 1120 | #define PHY_CTRL1_NO_PLL_PWD_GET(x) (((x) & PHY_CTRL1_NO_PLL_PWD_MASK) >> PHY_CTRL1_NO_PLL_PWD_LSB) |
| 1121 | #define PHY_CTRL1_NO_PLL_PWD_SET(x) (((x) << PHY_CTRL1_NO_PLL_PWD_LSB) & PHY_CTRL1_NO_PLL_PWD_MASK) |
| 1122 | #define PHY_CTRL1_NO_PLL_PWD_RESET 0x0 // 0 |
| 1123 | #define PHY_CTRL1_RX_RSVD_MSB 11 |
| 1124 | #define PHY_CTRL1_RX_RSVD_LSB 9 |
| 1125 | #define PHY_CTRL1_RX_RSVD_MASK 0x00000e00 |
| 1126 | #define PHY_CTRL1_RX_RSVD_GET(x) (((x) & PHY_CTRL1_RX_RSVD_MASK) >> PHY_CTRL1_RX_RSVD_LSB) |
| 1127 | #define PHY_CTRL1_RX_RSVD_SET(x) (((x) << PHY_CTRL1_RX_RSVD_LSB) & PHY_CTRL1_RX_RSVD_MASK) |
| 1128 | #define PHY_CTRL1_RX_RSVD_RESET 0x0 // 0 |
| 1129 | #define PHY_CTRL1_RX_SELVREF0P25_MSB 8 |
| 1130 | #define PHY_CTRL1_RX_SELVREF0P25_LSB 8 |
| 1131 | #define PHY_CTRL1_RX_SELVREF0P25_MASK 0x00000100 |
| 1132 | #define PHY_CTRL1_RX_SELVREF0P25_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P25_MASK) >> PHY_CTRL1_RX_SELVREF0P25_LSB) |
| 1133 | #define PHY_CTRL1_RX_SELVREF0P25_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P25_LSB) & PHY_CTRL1_RX_SELVREF0P25_MASK) |
| 1134 | #define PHY_CTRL1_RX_SELVREF0P25_RESET 0x0 // 0 |
| 1135 | #define PHY_CTRL1_RX_SELVREF0P6_MSB 7 |
| 1136 | #define PHY_CTRL1_RX_SELVREF0P6_LSB 7 |
| 1137 | #define PHY_CTRL1_RX_SELVREF0P6_MASK 0x00000080 |
| 1138 | #define PHY_CTRL1_RX_SELVREF0P6_GET(x) (((x) & PHY_CTRL1_RX_SELVREF0P6_MASK) >> PHY_CTRL1_RX_SELVREF0P6_LSB) |
| 1139 | #define PHY_CTRL1_RX_SELVREF0P6_SET(x) (((x) << PHY_CTRL1_RX_SELVREF0P6_LSB) & PHY_CTRL1_RX_SELVREF0P6_MASK) |
| 1140 | #define PHY_CTRL1_RX_SELVREF0P6_RESET 0x1 // 1 |
| 1141 | #define PHY_CTRL1_RX_SELIR_100M_MSB 6 |
| 1142 | #define PHY_CTRL1_RX_SELIR_100M_LSB 5 |
| 1143 | #define PHY_CTRL1_RX_SELIR_100M_MASK 0x00000060 |
| 1144 | #define PHY_CTRL1_RX_SELIR_100M_GET(x) (((x) & PHY_CTRL1_RX_SELIR_100M_MASK) >> PHY_CTRL1_RX_SELIR_100M_LSB) |
| 1145 | #define PHY_CTRL1_RX_SELIR_100M_SET(x) (((x) << PHY_CTRL1_RX_SELIR_100M_LSB) & PHY_CTRL1_RX_SELIR_100M_MASK) |
| 1146 | #define PHY_CTRL1_RX_SELIR_100M_RESET 0x0 // 0 |
| 1147 | #define PHY_CTRL1_RX_LOWR_PDET_MSB 4 |
| 1148 | #define PHY_CTRL1_RX_LOWR_PDET_LSB 4 |
| 1149 | #define PHY_CTRL1_RX_LOWR_PDET_MASK 0x00000010 |
| 1150 | #define PHY_CTRL1_RX_LOWR_PDET_GET(x) (((x) & PHY_CTRL1_RX_LOWR_PDET_MASK) >> PHY_CTRL1_RX_LOWR_PDET_LSB) |
| 1151 | #define PHY_CTRL1_RX_LOWR_PDET_SET(x) (((x) << PHY_CTRL1_RX_LOWR_PDET_LSB) & PHY_CTRL1_RX_LOWR_PDET_MASK) |
| 1152 | #define PHY_CTRL1_RX_LOWR_PDET_RESET 0x1 // 1 |
| 1153 | #define PHY_CTRL1_RX_BYPASSEQ_MSB 3 |
| 1154 | #define PHY_CTRL1_RX_BYPASSEQ_LSB 3 |
| 1155 | #define PHY_CTRL1_RX_BYPASSEQ_MASK 0x00000008 |
| 1156 | #define PHY_CTRL1_RX_BYPASSEQ_GET(x) (((x) & PHY_CTRL1_RX_BYPASSEQ_MASK) >> PHY_CTRL1_RX_BYPASSEQ_LSB) |
| 1157 | #define PHY_CTRL1_RX_BYPASSEQ_SET(x) (((x) << PHY_CTRL1_RX_BYPASSEQ_LSB) & PHY_CTRL1_RX_BYPASSEQ_MASK) |
| 1158 | #define PHY_CTRL1_RX_BYPASSEQ_RESET 0x0 // 0 |
| 1159 | #define PHY_CTRL1_RX_FORCERXON_MSB 2 |
| 1160 | #define PHY_CTRL1_RX_FORCERXON_LSB 2 |
| 1161 | #define PHY_CTRL1_RX_FORCERXON_MASK 0x00000004 |
| 1162 | #define PHY_CTRL1_RX_FORCERXON_GET(x) (((x) & PHY_CTRL1_RX_FORCERXON_MASK) >> PHY_CTRL1_RX_FORCERXON_LSB) |
| 1163 | #define PHY_CTRL1_RX_FORCERXON_SET(x) (((x) << PHY_CTRL1_RX_FORCERXON_LSB) & PHY_CTRL1_RX_FORCERXON_MASK) |
| 1164 | #define PHY_CTRL1_RX_FORCERXON_RESET 0x1 // 1 |
| 1165 | #define PHY_CTRL1_RX_FILBW_SEL_MSB 1 |
| 1166 | #define PHY_CTRL1_RX_FILBW_SEL_LSB 0 |
| 1167 | #define PHY_CTRL1_RX_FILBW_SEL_MASK 0x00000003 |
| 1168 | #define PHY_CTRL1_RX_FILBW_SEL_GET(x) (((x) & PHY_CTRL1_RX_FILBW_SEL_MASK) >> PHY_CTRL1_RX_FILBW_SEL_LSB) |
| 1169 | #define PHY_CTRL1_RX_FILBW_SEL_SET(x) (((x) << PHY_CTRL1_RX_FILBW_SEL_LSB) & PHY_CTRL1_RX_FILBW_SEL_MASK) |
| 1170 | #define PHY_CTRL1_RX_FILBW_SEL_RESET 0x1 // 1 |
| 1171 | #define PHY_CTRL1_ADDRESS 0x18116c84 |
| 1172 | #define PHY_CTRL1_OFFSET 0x0004 |
| 1173 | // SW modifiable bits |
| 1174 | #define PHY_CTRL1_SW_MASK 0x8ffc3fff |
| 1175 | // bits defined at reset |
| 1176 | #define PHY_CTRL1_RSTMASK 0xffffffff |
| 1177 | // reset value (ignore bits undefined at reset) |
| 1178 | #define PHY_CTRL1_RESET 0x84600095 |
| 1179 | |
| 1180 | #define PHY_CTRL2_PWD_EXTBIAS_MSB 31 |
| 1181 | #define PHY_CTRL2_PWD_EXTBIAS_LSB 31 |
| 1182 | #define PHY_CTRL2_PWD_EXTBIAS_MASK 0x80000000 |
| 1183 | #define PHY_CTRL2_PWD_EXTBIAS_GET(x) (((x) & PHY_CTRL2_PWD_EXTBIAS_MASK) >> PHY_CTRL2_PWD_EXTBIAS_LSB) |
| 1184 | #define PHY_CTRL2_PWD_EXTBIAS_SET(x) (((x) << PHY_CTRL2_PWD_EXTBIAS_LSB) & PHY_CTRL2_PWD_EXTBIAS_MASK) |
| 1185 | #define PHY_CTRL2_PWD_EXTBIAS_RESET 0x0 // 0 |
| 1186 | #define PHY_CTRL2_TX_RSVD_MSB 30 |
| 1187 | #define PHY_CTRL2_TX_RSVD_LSB 27 |
| 1188 | #define PHY_CTRL2_TX_RSVD_MASK 0x78000000 |
| 1189 | #define PHY_CTRL2_TX_RSVD_GET(x) (((x) & PHY_CTRL2_TX_RSVD_MASK) >> PHY_CTRL2_TX_RSVD_LSB) |
| 1190 | #define PHY_CTRL2_TX_RSVD_SET(x) (((x) << PHY_CTRL2_TX_RSVD_LSB) & PHY_CTRL2_TX_RSVD_MASK) |
| 1191 | #define PHY_CTRL2_TX_RSVD_RESET 0x0 // 0 |
| 1192 | #define PHY_CTRL2_TX_LCKDET_OVR_MSB 26 |
| 1193 | #define PHY_CTRL2_TX_LCKDET_OVR_LSB 26 |
| 1194 | #define PHY_CTRL2_TX_LCKDET_OVR_MASK 0x04000000 |
| 1195 | #define PHY_CTRL2_TX_LCKDET_OVR_GET(x) (((x) & PHY_CTRL2_TX_LCKDET_OVR_MASK) >> PHY_CTRL2_TX_LCKDET_OVR_LSB) |
| 1196 | #define PHY_CTRL2_TX_LCKDET_OVR_SET(x) (((x) << PHY_CTRL2_TX_LCKDET_OVR_LSB) & PHY_CTRL2_TX_LCKDET_OVR_MASK) |
| 1197 | #define PHY_CTRL2_TX_LCKDET_OVR_RESET 0x0 // 0 |
| 1198 | #define PHY_CTRL2_TX_MAN_CAL_MSB 25 |
| 1199 | #define PHY_CTRL2_TX_MAN_CAL_LSB 22 |
| 1200 | #define PHY_CTRL2_TX_MAN_CAL_MASK 0x03c00000 |
| 1201 | #define PHY_CTRL2_TX_MAN_CAL_GET(x) (((x) & PHY_CTRL2_TX_MAN_CAL_MASK) >> PHY_CTRL2_TX_MAN_CAL_LSB) |
| 1202 | #define PHY_CTRL2_TX_MAN_CAL_SET(x) (((x) << PHY_CTRL2_TX_MAN_CAL_LSB) & PHY_CTRL2_TX_MAN_CAL_MASK) |
| 1203 | #define PHY_CTRL2_TX_MAN_CAL_RESET 0x3 // 3 |
| 1204 | #define PHY_CTRL2_TX_CAL_SEL_MSB 21 |
| 1205 | #define PHY_CTRL2_TX_CAL_SEL_LSB 21 |
| 1206 | #define PHY_CTRL2_TX_CAL_SEL_MASK 0x00200000 |
| 1207 | #define PHY_CTRL2_TX_CAL_SEL_GET(x) (((x) & PHY_CTRL2_TX_CAL_SEL_MASK) >> PHY_CTRL2_TX_CAL_SEL_LSB) |
| 1208 | #define PHY_CTRL2_TX_CAL_SEL_SET(x) (((x) << PHY_CTRL2_TX_CAL_SEL_LSB) & PHY_CTRL2_TX_CAL_SEL_MASK) |
| 1209 | #define PHY_CTRL2_TX_CAL_SEL_RESET 0x1 // 1 |
| 1210 | #define PHY_CTRL2_TX_CAL_EN_MSB 20 |
| 1211 | #define PHY_CTRL2_TX_CAL_EN_LSB 20 |
| 1212 | #define PHY_CTRL2_TX_CAL_EN_MASK 0x00100000 |
| 1213 | #define PHY_CTRL2_TX_CAL_EN_GET(x) (((x) & PHY_CTRL2_TX_CAL_EN_MASK) >> PHY_CTRL2_TX_CAL_EN_LSB) |
| 1214 | #define PHY_CTRL2_TX_CAL_EN_SET(x) (((x) << PHY_CTRL2_TX_CAL_EN_LSB) & PHY_CTRL2_TX_CAL_EN_MASK) |
| 1215 | #define PHY_CTRL2_TX_CAL_EN_RESET 0x1 // 1 |
| 1216 | #define PHY_CTRL2_PWD_ISP_MSB 13 |
| 1217 | #define PHY_CTRL2_PWD_ISP_LSB 8 |
| 1218 | #define PHY_CTRL2_PWD_ISP_MASK 0x00003f00 |
| 1219 | #define PHY_CTRL2_PWD_ISP_GET(x) (((x) & PHY_CTRL2_PWD_ISP_MASK) >> PHY_CTRL2_PWD_ISP_LSB) |
| 1220 | #define PHY_CTRL2_PWD_ISP_SET(x) (((x) << PHY_CTRL2_PWD_ISP_LSB) & PHY_CTRL2_PWD_ISP_MASK) |
| 1221 | #define PHY_CTRL2_PWD_ISP_RESET 0x1b // 27 |
| 1222 | #define PHY_CTRL2_PWD_IPLL_MSB 7 |
| 1223 | #define PHY_CTRL2_PWD_IPLL_LSB 2 |
| 1224 | #define PHY_CTRL2_PWD_IPLL_MASK 0x000000fc |
| 1225 | #define PHY_CTRL2_PWD_IPLL_GET(x) (((x) & PHY_CTRL2_PWD_IPLL_MASK) >> PHY_CTRL2_PWD_IPLL_LSB) |
| 1226 | #define PHY_CTRL2_PWD_IPLL_SET(x) (((x) << PHY_CTRL2_PWD_IPLL_LSB) & PHY_CTRL2_PWD_IPLL_MASK) |
| 1227 | #define PHY_CTRL2_PWD_IPLL_RESET 0x1b // 27 |
| 1228 | #define PHY_CTRL2_HSRXPHASE_PS_EN_MSB 1 |
| 1229 | #define PHY_CTRL2_HSRXPHASE_PS_EN_LSB 1 |
| 1230 | #define PHY_CTRL2_HSRXPHASE_PS_EN_MASK 0x00000002 |
| 1231 | #define PHY_CTRL2_HSRXPHASE_PS_EN_GET(x) (((x) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> PHY_CTRL2_HSRXPHASE_PS_EN_LSB) |
| 1232 | #define PHY_CTRL2_HSRXPHASE_PS_EN_SET(x) (((x) << PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & PHY_CTRL2_HSRXPHASE_PS_EN_MASK) |
| 1233 | #define PHY_CTRL2_HSRXPHASE_PS_EN_RESET 0x0 // 0 |
| 1234 | #define PHY_CTRL2_HSTXBIAS_PS_EN_MSB 0 |
| 1235 | #define PHY_CTRL2_HSTXBIAS_PS_EN_LSB 0 |
| 1236 | #define PHY_CTRL2_HSTXBIAS_PS_EN_MASK 0x00000001 |
| 1237 | #define PHY_CTRL2_HSTXBIAS_PS_EN_GET(x) (((x) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> PHY_CTRL2_HSTXBIAS_PS_EN_LSB) |
| 1238 | #define PHY_CTRL2_HSTXBIAS_PS_EN_SET(x) (((x) << PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & PHY_CTRL2_HSTXBIAS_PS_EN_MASK) |
| 1239 | #define PHY_CTRL2_HSTXBIAS_PS_EN_RESET 0x0 // 0 |
| 1240 | #define PHY_CTRL2_ADDRESS 0x18116c88 |
| 1241 | #define PHY_CTRL2_OFFSET 0x0008 |
| 1242 | // SW modifiable bits |
| 1243 | #define PHY_CTRL2_SW_MASK 0xfff03fff |
| 1244 | // bits defined at reset |
| 1245 | #define PHY_CTRL2_RSTMASK 0xffffffff |
| 1246 | // reset value (ignore bits undefined at reset) |
| 1247 | #define PHY_CTRL2_RESET 0x00f01b6c |
| 1248 | |
| 1249 | #define PHY_CTRL3_SPARE_BITS_MSB 31 |
| 1250 | #define PHY_CTRL3_SPARE_BITS_LSB 27 |
| 1251 | #define PHY_CTRL3_SPARE_BITS_MASK 0xf8000000 |
| 1252 | #define PHY_CTRL3_SPARE_BITS_GET(x) (((x) & PHY_CTRL3_SPARE_BITS_MASK) >> PHY_CTRL3_SPARE_BITS_LSB) |
| 1253 | #define PHY_CTRL3_SPARE_BITS_SET(x) (((x) << PHY_CTRL3_SPARE_BITS_LSB) & PHY_CTRL3_SPARE_BITS_MASK) |
| 1254 | #define PHY_CTRL3_SPARE_BITS_RESET 0x0 // 0 |
| 1255 | #define PHY_CTRL3_SUS_RES_FIX_DIS_MSB 26 |
| 1256 | #define PHY_CTRL3_SUS_RES_FIX_DIS_LSB 26 |
| 1257 | #define PHY_CTRL3_SUS_RES_FIX_DIS_MASK 0x04000000 |
| 1258 | #define PHY_CTRL3_SUS_RES_FIX_DIS_GET(x) (((x) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) >> PHY_CTRL3_SUS_RES_FIX_DIS_LSB) |
| 1259 | #define PHY_CTRL3_SUS_RES_FIX_DIS_SET(x) (((x) << PHY_CTRL3_SUS_RES_FIX_DIS_LSB) & PHY_CTRL3_SUS_RES_FIX_DIS_MASK) |
| 1260 | #define PHY_CTRL3_SUS_RES_FIX_DIS_RESET 0x0 // 0 |
| 1261 | #define PHY_CTRL3_TX_STARTCAL_MSB 25 |
| 1262 | #define PHY_CTRL3_TX_STARTCAL_LSB 25 |
| 1263 | #define PHY_CTRL3_TX_STARTCAL_MASK 0x02000000 |
| 1264 | #define PHY_CTRL3_TX_STARTCAL_GET(x) (((x) & PHY_CTRL3_TX_STARTCAL_MASK) >> PHY_CTRL3_TX_STARTCAL_LSB) |
| 1265 | #define PHY_CTRL3_TX_STARTCAL_SET(x) (((x) << PHY_CTRL3_TX_STARTCAL_LSB) & PHY_CTRL3_TX_STARTCAL_MASK) |
| 1266 | #define PHY_CTRL3_TX_STARTCAL_RESET 0x0 // 0 |
| 1267 | #define PHY_CTRL3_TX_SELTEST_MSB 24 |
| 1268 | #define PHY_CTRL3_TX_SELTEST_LSB 22 |
| 1269 | #define PHY_CTRL3_TX_SELTEST_MASK 0x01c00000 |
| 1270 | #define PHY_CTRL3_TX_SELTEST_GET(x) (((x) & PHY_CTRL3_TX_SELTEST_MASK) >> PHY_CTRL3_TX_SELTEST_LSB) |
| 1271 | #define PHY_CTRL3_TX_SELTEST_SET(x) (((x) << PHY_CTRL3_TX_SELTEST_LSB) & PHY_CTRL3_TX_SELTEST_MASK) |
| 1272 | #define PHY_CTRL3_TX_SELTEST_RESET 0x0 // 0 |
| 1273 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_MSB 21 |
| 1274 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB 21 |
| 1275 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK 0x00200000 |
| 1276 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_GET(x) (((x) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) >> PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) |
| 1277 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_SET(x) (((x) << PHY_CTRL3_TX_DISABLE_SHORT_DET_LSB) & PHY_CTRL3_TX_DISABLE_SHORT_DET_MASK) |
| 1278 | #define PHY_CTRL3_TX_DISABLE_SHORT_DET_RESET 0x0 // 0 |
| 1279 | #define PHY_CTRL3_PWD_ITX_MSB 18 |
| 1280 | #define PHY_CTRL3_PWD_ITX_LSB 0 |
| 1281 | #define PHY_CTRL3_PWD_ITX_MASK 0x0007ffff |
| 1282 | #define PHY_CTRL3_PWD_ITX_GET(x) (((x) & PHY_CTRL3_PWD_ITX_MASK) >> PHY_CTRL3_PWD_ITX_LSB) |
| 1283 | #define PHY_CTRL3_PWD_ITX_SET(x) (((x) << PHY_CTRL3_PWD_ITX_LSB) & PHY_CTRL3_PWD_ITX_MASK) |
| 1284 | #define PHY_CTRL3_PWD_ITX_RESET 0x14765 // 83813 |
| 1285 | #define PHY_CTRL3_ADDRESS 0x18116c8c |
| 1286 | #define PHY_CTRL3_OFFSET 0x000c |
| 1287 | // SW modifiable bits |
| 1288 | #define PHY_CTRL3_SW_MASK 0xffe7ffff |
| 1289 | // bits defined at reset |
| 1290 | #define PHY_CTRL3_RSTMASK 0xffffffff |
| 1291 | // reset value (ignore bits undefined at reset) |
| 1292 | #define PHY_CTRL3_RESET 0x00014765 |
| 1293 | |
| 1294 | #define PHY_CTRL4_PPRBS_ERR_CNT_MSB 31 |
| 1295 | #define PHY_CTRL4_PPRBS_ERR_CNT_LSB 24 |
| 1296 | #define PHY_CTRL4_PPRBS_ERR_CNT_MASK 0xff000000 |
| 1297 | #define PHY_CTRL4_PPRBS_ERR_CNT_GET(x) (((x) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) >> PHY_CTRL4_PPRBS_ERR_CNT_LSB) |
| 1298 | #define PHY_CTRL4_PPRBS_ERR_CNT_SET(x) (((x) << PHY_CTRL4_PPRBS_ERR_CNT_LSB) & PHY_CTRL4_PPRBS_ERR_CNT_MASK) |
| 1299 | #define PHY_CTRL4_PPRBS_ERR_CNT_RESET 0x0 // 0 |
| 1300 | #define PHY_CTRL4_LS_PRBS_EN_MSB 21 |
| 1301 | #define PHY_CTRL4_LS_PRBS_EN_LSB 21 |
| 1302 | #define PHY_CTRL4_LS_PRBS_EN_MASK 0x00200000 |
| 1303 | #define PHY_CTRL4_LS_PRBS_EN_GET(x) (((x) & PHY_CTRL4_LS_PRBS_EN_MASK) >> PHY_CTRL4_LS_PRBS_EN_LSB) |
| 1304 | #define PHY_CTRL4_LS_PRBS_EN_SET(x) (((x) << PHY_CTRL4_LS_PRBS_EN_LSB) & PHY_CTRL4_LS_PRBS_EN_MASK) |
| 1305 | #define PHY_CTRL4_LS_PRBS_EN_RESET 0x0 // 0 |
| 1306 | #define PHY_CTRL4_PPRBS_TERM_SEL_MSB 20 |
| 1307 | #define PHY_CTRL4_PPRBS_TERM_SEL_LSB 20 |
| 1308 | #define PHY_CTRL4_PPRBS_TERM_SEL_MASK 0x00100000 |
| 1309 | #define PHY_CTRL4_PPRBS_TERM_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) >> PHY_CTRL4_PPRBS_TERM_SEL_LSB) |
| 1310 | #define PHY_CTRL4_PPRBS_TERM_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_TERM_SEL_LSB) & PHY_CTRL4_PPRBS_TERM_SEL_MASK) |
| 1311 | #define PHY_CTRL4_PPRBS_TERM_SEL_RESET 0x0 // 0 |
| 1312 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MSB 19 |
| 1313 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB 19 |
| 1314 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK 0x00080000 |
| 1315 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) |
| 1316 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_DIG_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_DIG_LPBK_EN_MASK) |
| 1317 | #define PHY_CTRL4_PPRBS_DIG_LPBK_EN_RESET 0x0 // 0 |
| 1318 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MSB 18 |
| 1319 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB 18 |
| 1320 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK 0x00040000 |
| 1321 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) >> PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) |
| 1322 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_ANA_LPBK_EN_LSB) & PHY_CTRL4_PPRBS_ANA_LPBK_EN_MASK) |
| 1323 | #define PHY_CTRL4_PPRBS_ANA_LPBK_EN_RESET 0x0 // 0 |
| 1324 | #define PHY_CTRL4_PPRBS_PAT_SEL_MSB 17 |
| 1325 | #define PHY_CTRL4_PPRBS_PAT_SEL_LSB 16 |
| 1326 | #define PHY_CTRL4_PPRBS_PAT_SEL_MASK 0x00030000 |
| 1327 | #define PHY_CTRL4_PPRBS_PAT_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) >> PHY_CTRL4_PPRBS_PAT_SEL_LSB) |
| 1328 | #define PHY_CTRL4_PPRBS_PAT_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_PAT_SEL_LSB) & PHY_CTRL4_PPRBS_PAT_SEL_MASK) |
| 1329 | #define PHY_CTRL4_PPRBS_PAT_SEL_RESET 0x0 // 0 |
| 1330 | #define PHY_CTRL4_PPRBS_TX_EN_MSB 15 |
| 1331 | #define PHY_CTRL4_PPRBS_TX_EN_LSB 15 |
| 1332 | #define PHY_CTRL4_PPRBS_TX_EN_MASK 0x00008000 |
| 1333 | #define PHY_CTRL4_PPRBS_TX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_TX_EN_MASK) >> PHY_CTRL4_PPRBS_TX_EN_LSB) |
| 1334 | #define PHY_CTRL4_PPRBS_TX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_TX_EN_LSB) & PHY_CTRL4_PPRBS_TX_EN_MASK) |
| 1335 | #define PHY_CTRL4_PPRBS_TX_EN_RESET 0x0 // 0 |
| 1336 | #define PHY_CTRL4_PPRBS_RX_EN_MSB 14 |
| 1337 | #define PHY_CTRL4_PPRBS_RX_EN_LSB 14 |
| 1338 | #define PHY_CTRL4_PPRBS_RX_EN_MASK 0x00004000 |
| 1339 | #define PHY_CTRL4_PPRBS_RX_EN_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_EN_MASK) >> PHY_CTRL4_PPRBS_RX_EN_LSB) |
| 1340 | #define PHY_CTRL4_PPRBS_RX_EN_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_EN_LSB) & PHY_CTRL4_PPRBS_RX_EN_MASK) |
| 1341 | #define PHY_CTRL4_PPRBS_RX_EN_RESET 0x0 // 0 |
| 1342 | #define PHY_CTRL4_PPRBS_SPEED_SEL_MSB 13 |
| 1343 | #define PHY_CTRL4_PPRBS_SPEED_SEL_LSB 13 |
| 1344 | #define PHY_CTRL4_PPRBS_SPEED_SEL_MASK 0x00002000 |
| 1345 | #define PHY_CTRL4_PPRBS_SPEED_SEL_GET(x) (((x) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) >> PHY_CTRL4_PPRBS_SPEED_SEL_LSB) |
| 1346 | #define PHY_CTRL4_PPRBS_SPEED_SEL_SET(x) (((x) << PHY_CTRL4_PPRBS_SPEED_SEL_LSB) & PHY_CTRL4_PPRBS_SPEED_SEL_MASK) |
| 1347 | #define PHY_CTRL4_PPRBS_SPEED_SEL_RESET 0x0 // 0 |
| 1348 | #define PHY_CTRL4_PPRBS_RX_INV_MSB 12 |
| 1349 | #define PHY_CTRL4_PPRBS_RX_INV_LSB 12 |
| 1350 | #define PHY_CTRL4_PPRBS_RX_INV_MASK 0x00001000 |
| 1351 | #define PHY_CTRL4_PPRBS_RX_INV_GET(x) (((x) & PHY_CTRL4_PPRBS_RX_INV_MASK) >> PHY_CTRL4_PPRBS_RX_INV_LSB) |
| 1352 | #define PHY_CTRL4_PPRBS_RX_INV_SET(x) (((x) << PHY_CTRL4_PPRBS_RX_INV_LSB) & PHY_CTRL4_PPRBS_RX_INV_MASK) |
| 1353 | #define PHY_CTRL4_PPRBS_RX_INV_RESET 0x0 // 0 |
| 1354 | #define PHY_CTRL4_PWD_IRX_MSB 11 |
| 1355 | #define PHY_CTRL4_PWD_IRX_LSB 0 |
| 1356 | #define PHY_CTRL4_PWD_IRX_MASK 0x00000fff |
| 1357 | #define PHY_CTRL4_PWD_IRX_GET(x) (((x) & PHY_CTRL4_PWD_IRX_MASK) >> PHY_CTRL4_PWD_IRX_LSB) |
| 1358 | #define PHY_CTRL4_PWD_IRX_SET(x) (((x) << PHY_CTRL4_PWD_IRX_LSB) & PHY_CTRL4_PWD_IRX_MASK) |
| 1359 | #define PHY_CTRL4_PWD_IRX_RESET 0x6dd // 1757 |
| 1360 | #define PHY_CTRL4_ADDRESS 0x18116c90 |
| 1361 | #define PHY_CTRL4_OFFSET 0x0010 |
| 1362 | // SW modifiable bits |
| 1363 | #define PHY_CTRL4_SW_MASK 0xff3fffff |
| 1364 | // bits defined at reset |
| 1365 | #define PHY_CTRL4_RSTMASK 0xffffffff |
| 1366 | // reset value (ignore bits undefined at reset) |
| 1367 | #define PHY_CTRL4_RESET 0x000006dd |
| 1368 | |
| 1369 | #define PHY_CTRL5_SPARE_BITS_MSB 31 |
| 1370 | #define PHY_CTRL5_SPARE_BITS_LSB 30 |
| 1371 | #define PHY_CTRL5_SPARE_BITS_MASK 0xc0000000 |
| 1372 | #define PHY_CTRL5_SPARE_BITS_GET(x) (((x) & PHY_CTRL5_SPARE_BITS_MASK) >> PHY_CTRL5_SPARE_BITS_LSB) |
| 1373 | #define PHY_CTRL5_SPARE_BITS_SET(x) (((x) << PHY_CTRL5_SPARE_BITS_LSB) & PHY_CTRL5_SPARE_BITS_MASK) |
| 1374 | #define PHY_CTRL5_SPARE_BITS_RESET 0x0 // 0 |
| 1375 | #define PHY_CTRL5_HOST_RES_FIX_EN_MSB 29 |
| 1376 | #define PHY_CTRL5_HOST_RES_FIX_EN_LSB 29 |
| 1377 | #define PHY_CTRL5_HOST_RES_FIX_EN_MASK 0x20000000 |
| 1378 | #define PHY_CTRL5_HOST_RES_FIX_EN_GET(x) (((x) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) >> PHY_CTRL5_HOST_RES_FIX_EN_LSB) |
| 1379 | #define PHY_CTRL5_HOST_RES_FIX_EN_SET(x) (((x) << PHY_CTRL5_HOST_RES_FIX_EN_LSB) & PHY_CTRL5_HOST_RES_FIX_EN_MASK) |
| 1380 | #define PHY_CTRL5_HOST_RES_FIX_EN_RESET 0x1 // 1 |
| 1381 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MSB 28 |
| 1382 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB 26 |
| 1383 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK 0x1c000000 |
| 1384 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) >> PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) |
| 1385 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_LSB) & PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_MASK) |
| 1386 | #define PHY_CTRL5_HOST_DISCON_SAMPLE_WIDTH_RESET 0x6 // 6 |
| 1387 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_MSB 25 |
| 1388 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB 25 |
| 1389 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK 0x02000000 |
| 1390 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) >> PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) |
| 1391 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_DETECT_ON_LSB) & PHY_CTRL5_HOST_DISCON_DETECT_ON_MASK) |
| 1392 | #define PHY_CTRL5_HOST_DISCON_DETECT_ON_RESET 0x1 // 1 |
| 1393 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_MSB 24 |
| 1394 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_LSB 24 |
| 1395 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_MASK 0x01000000 |
| 1396 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_GET(x) (((x) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) >> PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) |
| 1397 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_SET(x) (((x) << PHY_CTRL5_HOST_DISCON_FIX_ON_LSB) & PHY_CTRL5_HOST_DISCON_FIX_ON_MASK) |
| 1398 | #define PHY_CTRL5_HOST_DISCON_FIX_ON_RESET 0x1 // 1 |
| 1399 | #define PHY_CTRL5_DM_PULLDOWN_MSB 23 |
| 1400 | #define PHY_CTRL5_DM_PULLDOWN_LSB 23 |
| 1401 | #define PHY_CTRL5_DM_PULLDOWN_MASK 0x00800000 |
| 1402 | #define PHY_CTRL5_DM_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DM_PULLDOWN_MASK) >> PHY_CTRL5_DM_PULLDOWN_LSB) |
| 1403 | #define PHY_CTRL5_DM_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DM_PULLDOWN_LSB) & PHY_CTRL5_DM_PULLDOWN_MASK) |
| 1404 | #define PHY_CTRL5_DM_PULLDOWN_RESET 0x0 // 0 |
| 1405 | #define PHY_CTRL5_DP_PULLDOWN_MSB 22 |
| 1406 | #define PHY_CTRL5_DP_PULLDOWN_LSB 22 |
| 1407 | #define PHY_CTRL5_DP_PULLDOWN_MASK 0x00400000 |
| 1408 | #define PHY_CTRL5_DP_PULLDOWN_GET(x) (((x) & PHY_CTRL5_DP_PULLDOWN_MASK) >> PHY_CTRL5_DP_PULLDOWN_LSB) |
| 1409 | #define PHY_CTRL5_DP_PULLDOWN_SET(x) (((x) << PHY_CTRL5_DP_PULLDOWN_LSB) & PHY_CTRL5_DP_PULLDOWN_MASK) |
| 1410 | #define PHY_CTRL5_DP_PULLDOWN_RESET 0x0 // 0 |
| 1411 | #define PHY_CTRL5_SUSPEND_N_MSB 21 |
| 1412 | #define PHY_CTRL5_SUSPEND_N_LSB 21 |
| 1413 | #define PHY_CTRL5_SUSPEND_N_MASK 0x00200000 |
| 1414 | #define PHY_CTRL5_SUSPEND_N_GET(x) (((x) & PHY_CTRL5_SUSPEND_N_MASK) >> PHY_CTRL5_SUSPEND_N_LSB) |
| 1415 | #define PHY_CTRL5_SUSPEND_N_SET(x) (((x) << PHY_CTRL5_SUSPEND_N_LSB) & PHY_CTRL5_SUSPEND_N_MASK) |
| 1416 | #define PHY_CTRL5_SUSPEND_N_RESET 0x1 // 1 |
| 1417 | #define PHY_CTRL5_TERM_SEL_MSB 20 |
| 1418 | #define PHY_CTRL5_TERM_SEL_LSB 20 |
| 1419 | #define PHY_CTRL5_TERM_SEL_MASK 0x00100000 |
| 1420 | #define PHY_CTRL5_TERM_SEL_GET(x) (((x) & PHY_CTRL5_TERM_SEL_MASK) >> PHY_CTRL5_TERM_SEL_LSB) |
| 1421 | #define PHY_CTRL5_TERM_SEL_SET(x) (((x) << PHY_CTRL5_TERM_SEL_LSB) & PHY_CTRL5_TERM_SEL_MASK) |
| 1422 | #define PHY_CTRL5_TERM_SEL_RESET 0x0 // 0 |
| 1423 | #define PHY_CTRL5_XCVR_SEL_MSB 19 |
| 1424 | #define PHY_CTRL5_XCVR_SEL_LSB 18 |
| 1425 | #define PHY_CTRL5_XCVR_SEL_MASK 0x000c0000 |
| 1426 | #define PHY_CTRL5_XCVR_SEL_GET(x) (((x) & PHY_CTRL5_XCVR_SEL_MASK) >> PHY_CTRL5_XCVR_SEL_LSB) |
| 1427 | #define PHY_CTRL5_XCVR_SEL_SET(x) (((x) << PHY_CTRL5_XCVR_SEL_LSB) & PHY_CTRL5_XCVR_SEL_MASK) |
| 1428 | #define PHY_CTRL5_XCVR_SEL_RESET 0x0 // 0 |
| 1429 | #define PHY_CTRL5_TEST_JK_OVERRIDE_MSB 17 |
| 1430 | #define PHY_CTRL5_TEST_JK_OVERRIDE_LSB 17 |
| 1431 | #define PHY_CTRL5_TEST_JK_OVERRIDE_MASK 0x00020000 |
| 1432 | #define PHY_CTRL5_TEST_JK_OVERRIDE_GET(x) (((x) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) >> PHY_CTRL5_TEST_JK_OVERRIDE_LSB) |
| 1433 | #define PHY_CTRL5_TEST_JK_OVERRIDE_SET(x) (((x) << PHY_CTRL5_TEST_JK_OVERRIDE_LSB) & PHY_CTRL5_TEST_JK_OVERRIDE_MASK) |
| 1434 | #define PHY_CTRL5_TEST_JK_OVERRIDE_RESET 0x0 // 0 |
| 1435 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_MSB 16 |
| 1436 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB 16 |
| 1437 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK 0x00010000 |
| 1438 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) >> PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) |
| 1439 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_SE0_NAK_LSB) & PHY_CTRL5_FORCE_TEST_SE0_NAK_MASK) |
| 1440 | #define PHY_CTRL5_FORCE_TEST_SE0_NAK_RESET 0x0 // 0 |
| 1441 | #define PHY_CTRL5_FORCE_TEST_K_MSB 15 |
| 1442 | #define PHY_CTRL5_FORCE_TEST_K_LSB 15 |
| 1443 | #define PHY_CTRL5_FORCE_TEST_K_MASK 0x00008000 |
| 1444 | #define PHY_CTRL5_FORCE_TEST_K_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_K_MASK) >> PHY_CTRL5_FORCE_TEST_K_LSB) |
| 1445 | #define PHY_CTRL5_FORCE_TEST_K_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_K_LSB) & PHY_CTRL5_FORCE_TEST_K_MASK) |
| 1446 | #define PHY_CTRL5_FORCE_TEST_K_RESET 0x0 // 0 |
| 1447 | #define PHY_CTRL5_FORCE_TEST_J_MSB 14 |
| 1448 | #define PHY_CTRL5_FORCE_TEST_J_LSB 14 |
| 1449 | #define PHY_CTRL5_FORCE_TEST_J_MASK 0x00004000 |
| 1450 | #define PHY_CTRL5_FORCE_TEST_J_GET(x) (((x) & PHY_CTRL5_FORCE_TEST_J_MASK) >> PHY_CTRL5_FORCE_TEST_J_LSB) |
| 1451 | #define PHY_CTRL5_FORCE_TEST_J_SET(x) (((x) << PHY_CTRL5_FORCE_TEST_J_LSB) & PHY_CTRL5_FORCE_TEST_J_MASK) |
| 1452 | #define PHY_CTRL5_FORCE_TEST_J_RESET 0x0 // 0 |
| 1453 | #define PHY_CTRL5_FORCE_IDDQ_MSB 13 |
| 1454 | #define PHY_CTRL5_FORCE_IDDQ_LSB 13 |
| 1455 | #define PHY_CTRL5_FORCE_IDDQ_MASK 0x00002000 |
| 1456 | #define PHY_CTRL5_FORCE_IDDQ_GET(x) (((x) & PHY_CTRL5_FORCE_IDDQ_MASK) >> PHY_CTRL5_FORCE_IDDQ_LSB) |
| 1457 | #define PHY_CTRL5_FORCE_IDDQ_SET(x) (((x) << PHY_CTRL5_FORCE_IDDQ_LSB) & PHY_CTRL5_FORCE_IDDQ_MASK) |
| 1458 | #define PHY_CTRL5_FORCE_IDDQ_RESET 0x0 // 0 |
| 1459 | #define PHY_CTRL5_EB_WATERMARK_MSB 12 |
| 1460 | #define PHY_CTRL5_EB_WATERMARK_LSB 7 |
| 1461 | #define PHY_CTRL5_EB_WATERMARK_MASK 0x00001f80 |
| 1462 | #define PHY_CTRL5_EB_WATERMARK_GET(x) (((x) & PHY_CTRL5_EB_WATERMARK_MASK) >> PHY_CTRL5_EB_WATERMARK_LSB) |
| 1463 | #define PHY_CTRL5_EB_WATERMARK_SET(x) (((x) << PHY_CTRL5_EB_WATERMARK_LSB) & PHY_CTRL5_EB_WATERMARK_MASK) |
| 1464 | #define PHY_CTRL5_EB_WATERMARK_RESET 0x14 // 20 |
| 1465 | #define PHY_CTRL5_TX_BIAS_DELAY_MSB 6 |
| 1466 | #define PHY_CTRL5_TX_BIAS_DELAY_LSB 0 |
| 1467 | #define PHY_CTRL5_TX_BIAS_DELAY_MASK 0x0000007f |
| 1468 | #define PHY_CTRL5_TX_BIAS_DELAY_GET(x) (((x) & PHY_CTRL5_TX_BIAS_DELAY_MASK) >> PHY_CTRL5_TX_BIAS_DELAY_LSB) |
| 1469 | #define PHY_CTRL5_TX_BIAS_DELAY_SET(x) (((x) << PHY_CTRL5_TX_BIAS_DELAY_LSB) & PHY_CTRL5_TX_BIAS_DELAY_MASK) |
| 1470 | #define PHY_CTRL5_TX_BIAS_DELAY_RESET 0x32 // 50 |
| 1471 | #define PHY_CTRL5_ADDRESS 0x18116c94 |
| 1472 | #define PHY_CTRL5_OFFSET 0x0014 |
| 1473 | // SW modifiable bits |
| 1474 | #define PHY_CTRL5_SW_MASK 0xffffffff |
| 1475 | // bits defined at reset |
| 1476 | #define PHY_CTRL5_RSTMASK 0xffffffff |
| 1477 | // reset value (ignore bits undefined at reset) |
| 1478 | #define PHY_CTRL5_RESET 0x3b200a32 |
| 1479 | #define PHY_CTRL5_RESET_1 0x3b202a58 |
| 1480 | |
| 1481 | #define PHY_CTRL6_SPARE_BITS_MSB 31 |
| 1482 | #define PHY_CTRL6_SPARE_BITS_LSB 9 |
| 1483 | #define PHY_CTRL6_SPARE_BITS_MASK 0xfffffe00 |
| 1484 | #define PHY_CTRL6_SPARE_BITS_GET(x) (((x) & PHY_CTRL6_SPARE_BITS_MASK) >> PHY_CTRL6_SPARE_BITS_LSB) |
| 1485 | #define PHY_CTRL6_SPARE_BITS_SET(x) (((x) << PHY_CTRL6_SPARE_BITS_LSB) & PHY_CTRL6_SPARE_BITS_MASK) |
| 1486 | #define PHY_CTRL6_SPARE_BITS_RESET 0x0 // 0 |
| 1487 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MSB 8 |
| 1488 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB 8 |
| 1489 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK 0x00000100 |
| 1490 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_GET(x) (((x) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) >> PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) |
| 1491 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_SET(x) (((x) << PHY_CTRL6_DIS_SETUP_RETRY_FIX_LSB) & PHY_CTRL6_DIS_SETUP_RETRY_FIX_MASK) |
| 1492 | #define PHY_CTRL6_DIS_SETUP_RETRY_FIX_RESET 0x0 // 0 |
| 1493 | #define PHY_CTRL6_XCVR_SEL_MSB 7 |
| 1494 | #define PHY_CTRL6_XCVR_SEL_LSB 6 |
| 1495 | #define PHY_CTRL6_XCVR_SEL_MASK 0x000000c0 |
| 1496 | #define PHY_CTRL6_XCVR_SEL_GET(x) (((x) & PHY_CTRL6_XCVR_SEL_MASK) >> PHY_CTRL6_XCVR_SEL_LSB) |
| 1497 | #define PHY_CTRL6_XCVR_SEL_SET(x) (((x) << PHY_CTRL6_XCVR_SEL_LSB) & PHY_CTRL6_XCVR_SEL_MASK) |
| 1498 | #define PHY_CTRL6_XCVR_SEL_RESET 0x0 // 0 |
| 1499 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_MSB 5 |
| 1500 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_LSB 5 |
| 1501 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_MASK 0x00000020 |
| 1502 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_GET(x) (((x) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) >> PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) |
| 1503 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_SET(x) (((x) << PHY_CTRL6_XCVRSEL_OVERRIDE_LSB) & PHY_CTRL6_XCVRSEL_OVERRIDE_MASK) |
| 1504 | #define PHY_CTRL6_XCVRSEL_OVERRIDE_RESET 0x0 // 0 |
| 1505 | #define PHY_CTRL6_IDDIG_MSB 4 |
| 1506 | #define PHY_CTRL6_IDDIG_LSB 4 |
| 1507 | #define PHY_CTRL6_IDDIG_MASK 0x00000010 |
| 1508 | #define PHY_CTRL6_IDDIG_GET(x) (((x) & PHY_CTRL6_IDDIG_MASK) >> PHY_CTRL6_IDDIG_LSB) |
| 1509 | #define PHY_CTRL6_IDDIG_SET(x) (((x) << PHY_CTRL6_IDDIG_LSB) & PHY_CTRL6_IDDIG_MASK) |
| 1510 | #define PHY_CTRL6_IDDIG_RESET 0x0 // 0 |
| 1511 | #define PHY_CTRL6_SESSEND_MSB 3 |
| 1512 | #define PHY_CTRL6_SESSEND_LSB 3 |
| 1513 | #define PHY_CTRL6_SESSEND_MASK 0x00000008 |
| 1514 | #define PHY_CTRL6_SESSEND_GET(x) (((x) & PHY_CTRL6_SESSEND_MASK) >> PHY_CTRL6_SESSEND_LSB) |
| 1515 | #define PHY_CTRL6_SESSEND_SET(x) (((x) << PHY_CTRL6_SESSEND_LSB) & PHY_CTRL6_SESSEND_MASK) |
| 1516 | #define PHY_CTRL6_SESSEND_RESET 0x0 // 0 |
| 1517 | #define PHY_CTRL6_VBUSVALID_MSB 2 |
| 1518 | #define PHY_CTRL6_VBUSVALID_LSB 2 |
| 1519 | #define PHY_CTRL6_VBUSVALID_MASK 0x00000004 |
| 1520 | #define PHY_CTRL6_VBUSVALID_GET(x) (((x) & PHY_CTRL6_VBUSVALID_MASK) >> PHY_CTRL6_VBUSVALID_LSB) |
| 1521 | #define PHY_CTRL6_VBUSVALID_SET(x) (((x) << PHY_CTRL6_VBUSVALID_LSB) & PHY_CTRL6_VBUSVALID_MASK) |
| 1522 | #define PHY_CTRL6_VBUSVALID_RESET 0x1 // 1 |
| 1523 | #define PHY_CTRL6_BVALID_MSB 1 |
| 1524 | #define PHY_CTRL6_BVALID_LSB 1 |
| 1525 | #define PHY_CTRL6_BVALID_MASK 0x00000002 |
| 1526 | #define PHY_CTRL6_BVALID_GET(x) (((x) & PHY_CTRL6_BVALID_MASK) >> PHY_CTRL6_BVALID_LSB) |
| 1527 | #define PHY_CTRL6_BVALID_SET(x) (((x) << PHY_CTRL6_BVALID_LSB) & PHY_CTRL6_BVALID_MASK) |
| 1528 | #define PHY_CTRL6_BVALID_RESET 0x1 // 1 |
| 1529 | #define PHY_CTRL6_AVALID_MSB 0 |
| 1530 | #define PHY_CTRL6_AVALID_LSB 0 |
| 1531 | #define PHY_CTRL6_AVALID_MASK 0x00000001 |
| 1532 | #define PHY_CTRL6_AVALID_GET(x) (((x) & PHY_CTRL6_AVALID_MASK) >> PHY_CTRL6_AVALID_LSB) |
| 1533 | #define PHY_CTRL6_AVALID_SET(x) (((x) << PHY_CTRL6_AVALID_LSB) & PHY_CTRL6_AVALID_MASK) |
| 1534 | #define PHY_CTRL6_AVALID_RESET 0x1 // 1 |
| 1535 | #define PHY_CTRL6_ADDRESS 0x18116c98 |
| 1536 | #define PHY_CTRL6_OFFSET 0x0018 |
| 1537 | // SW modifiable bits |
| 1538 | #define PHY_CTRL6_SW_MASK 0xffffffff |
| 1539 | // bits defined at reset |
| 1540 | #define PHY_CTRL6_RSTMASK 0xffffffff |
| 1541 | // reset value (ignore bits undefined at reset) |
| 1542 | #define PHY_CTRL6_RESET 0x00000007 |
| 1543 | |
| 1544 | #define PHY_STATUS_TX_CAL_MSB 3 |
| 1545 | #define PHY_STATUS_TX_CAL_LSB 0 |
| 1546 | #define PHY_STATUS_TX_CAL_MASK 0x0000000f |
| 1547 | #define PHY_STATUS_TX_CAL_GET(x) (((x) & PHY_STATUS_TX_CAL_MASK) >> PHY_STATUS_TX_CAL_LSB) |
| 1548 | #define PHY_STATUS_TX_CAL_SET(x) (((x) << PHY_STATUS_TX_CAL_LSB) & PHY_STATUS_TX_CAL_MASK) |
| 1549 | #define PHY_STATUS_TX_CAL_RESET 0x0 // 0 |
| 1550 | #define PHY_STATUS_ADDRESS 0x18116c9c |
| 1551 | #define PHY_STATUS_OFFSET 0x001c |
| 1552 | // SW modifiable bits |
| 1553 | #define PHY_STATUS_SW_MASK 0x0000000f |
| 1554 | // bits defined at reset |
| 1555 | #define PHY_STATUS_RSTMASK 0xffffffff |
| 1556 | // reset value (ignore bits undefined at reset) |
| 1557 | #define PHY_STATUS_RESET 0x00000000 |
| 1558 | |
| 1559 | #define PHY_CTRL7_PPRBS_ERROR_RATE_MSB 31 |
| 1560 | #define PHY_CTRL7_PPRBS_ERROR_RATE_LSB 11 |
| 1561 | #define PHY_CTRL7_PPRBS_ERROR_RATE_MASK 0xfffff800 |
| 1562 | #define PHY_CTRL7_PPRBS_ERROR_RATE_GET(x) (((x) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) >> PHY_CTRL7_PPRBS_ERROR_RATE_LSB) |
| 1563 | #define PHY_CTRL7_PPRBS_ERROR_RATE_SET(x) (((x) << PHY_CTRL7_PPRBS_ERROR_RATE_LSB) & PHY_CTRL7_PPRBS_ERROR_RATE_MASK) |
| 1564 | #define PHY_CTRL7_PPRBS_ERROR_RATE_RESET 0xa000 // 40960 |
| 1565 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MSB 10 |
| 1566 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB 1 |
| 1567 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe |
| 1568 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) >> PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) |
| 1569 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_LSB) & PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_MASK) |
| 1570 | #define PHY_CTRL7_PPRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0 |
| 1571 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MSB 0 |
| 1572 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB 0 |
| 1573 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK 0x00000001 |
| 1574 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_GET(x) (((x) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) >> PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) |
| 1575 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_SET(x) (((x) << PHY_CTRL7_PPRBS_TRIGGER_ERROR_LSB) & PHY_CTRL7_PPRBS_TRIGGER_ERROR_MASK) |
| 1576 | #define PHY_CTRL7_PPRBS_TRIGGER_ERROR_RESET 0x0 // 0 |
| 1577 | #define PHY_CTRL7_ADDRESS 0x18116ca0 |
| 1578 | #define PHY_CTRL7_OFFSET 0x0020 |
| 1579 | // SW modifiable bits |
| 1580 | #define PHY_CTRL7_SW_MASK 0xffffffff |
| 1581 | // bits defined at reset |
| 1582 | #define PHY_CTRL7_RSTMASK 0xffffffff |
| 1583 | // reset value (ignore bits undefined at reset) |
| 1584 | #define PHY_CTRL7_RESET 0x05000000 |
| 1585 | |
| 1586 | #define PHY_CTRL8_USBPLL_PWD_MSB 7 |
| 1587 | #define PHY_CTRL8_USBPLL_PWD_LSB 7 |
| 1588 | #define PHY_CTRL8_USBPLL_PWD_MASK 0x00000080 |
| 1589 | #define PHY_CTRL8_USBPLL_PWD_GET(x) (((x) & PHY_CTRL8_USBPLL_PWD_MASK) >> PHY_CTRL8_USBPLL_PWD_LSB) |
| 1590 | #define PHY_CTRL8_USBPLL_PWD_SET(x) (((x) << PHY_CTRL8_USBPLL_PWD_LSB) & PHY_CTRL8_USBPLL_PWD_MASK) |
| 1591 | #define PHY_CTRL8_USBPLL_PWD_RESET 0x0 // 0 |
| 1592 | #define PHY_CTRL8_TX_FASTRISE_MSB 6 |
| 1593 | #define PHY_CTRL8_TX_FASTRISE_LSB 4 |
| 1594 | #define PHY_CTRL8_TX_FASTRISE_MASK 0x00000070 |
| 1595 | #define PHY_CTRL8_TX_FASTRISE_GET(x) (((x) & PHY_CTRL8_TX_FASTRISE_MASK) >> PHY_CTRL8_TX_FASTRISE_LSB) |
| 1596 | #define PHY_CTRL8_TX_FASTRISE_SET(x) (((x) << PHY_CTRL8_TX_FASTRISE_LSB) & PHY_CTRL8_TX_FASTRISE_MASK) |
| 1597 | #define PHY_CTRL8_TX_FASTRISE_RESET 0x5 // 5 |
| 1598 | #define PHY_CTRL8_TX_ENPRE_MSB 3 |
| 1599 | #define PHY_CTRL8_TX_ENPRE_LSB 2 |
| 1600 | #define PHY_CTRL8_TX_ENPRE_MASK 0x0000000c |
| 1601 | #define PHY_CTRL8_TX_ENPRE_GET(x) (((x) & PHY_CTRL8_TX_ENPRE_MASK) >> PHY_CTRL8_TX_ENPRE_LSB) |
| 1602 | #define PHY_CTRL8_TX_ENPRE_SET(x) (((x) << PHY_CTRL8_TX_ENPRE_LSB) & PHY_CTRL8_TX_ENPRE_MASK) |
| 1603 | #define PHY_CTRL8_TX_ENPRE_RESET 0x0 // 0 |
| 1604 | #define PHY_CTRL8_RX_SQ_HYST_EN_MSB 1 |
| 1605 | #define PHY_CTRL8_RX_SQ_HYST_EN_LSB 1 |
| 1606 | #define PHY_CTRL8_RX_SQ_HYST_EN_MASK 0x00000002 |
| 1607 | #define PHY_CTRL8_RX_SQ_HYST_EN_GET(x) (((x) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) >> PHY_CTRL8_RX_SQ_HYST_EN_LSB) |
| 1608 | #define PHY_CTRL8_RX_SQ_HYST_EN_SET(x) (((x) << PHY_CTRL8_RX_SQ_HYST_EN_LSB) & PHY_CTRL8_RX_SQ_HYST_EN_MASK) |
| 1609 | #define PHY_CTRL8_RX_SQ_HYST_EN_RESET 0x0 // 0 |
| 1610 | #define PHY_CTRL8_RX_SKIP2_MSB 0 |
| 1611 | #define PHY_CTRL8_RX_SKIP2_LSB 0 |
| 1612 | #define PHY_CTRL8_RX_SKIP2_MASK 0x00000001 |
| 1613 | #define PHY_CTRL8_RX_SKIP2_GET(x) (((x) & PHY_CTRL8_RX_SKIP2_MASK) >> PHY_CTRL8_RX_SKIP2_LSB) |
| 1614 | #define PHY_CTRL8_RX_SKIP2_SET(x) (((x) << PHY_CTRL8_RX_SKIP2_LSB) & PHY_CTRL8_RX_SKIP2_MASK) |
| 1615 | #define PHY_CTRL8_RX_SKIP2_RESET 0x0 // 0 |
| 1616 | #define PHY_CTRL8_ADDRESS 0x18116ca4 |
| 1617 | #define PHY_CTRL8_OFFSET 0x0024 |
| 1618 | // SW modifiable bits |
| 1619 | #define PHY_CTRL8_SW_MASK 0x000000ff |
| 1620 | // bits defined at reset |
| 1621 | #define PHY_CTRL8_RSTMASK 0xffffffff |
| 1622 | // reset value (ignore bits undefined at reset) |
| 1623 | #define PHY_CTRL8_RESET 0x00000050 |
| 1624 | #define CPU_DDR_CLOCK_CONTROL_SPARE_MSB 31 |
| 1625 | #define CPU_DDR_CLOCK_CONTROL_SPARE_LSB 25 |
| 1626 | #define CPU_DDR_CLOCK_CONTROL_SPARE_MASK 0xfe000000 |
| 1627 | #define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB) |
| 1628 | #define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) |
| 1629 | #define CPU_DDR_CLOCK_CONTROL_SPARE_RESET 0x0 // 0 |
| 1630 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB 24 |
| 1631 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB 24 |
| 1632 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK 0x01000000 |
| 1633 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) |
| 1634 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) |
| 1635 | #define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 0x1 // 1 |
| 1636 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23 |
| 1637 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23 |
| 1638 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000 |
| 1639 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) |
| 1640 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) |
| 1641 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0x0 // 0 |
| 1642 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22 |
| 1643 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22 |
| 1644 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000 |
| 1645 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) |
| 1646 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) |
| 1647 | #define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0 // 0 |
| 1648 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MSB 21 |
| 1649 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB 21 |
| 1650 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK 0x00200000 |
| 1651 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) |
| 1652 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_MASK) |
| 1653 | #define CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_RESET 0x1 // 1 |
| 1654 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MSB 20 |
| 1655 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB 20 |
| 1656 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK 0x00100000 |
| 1657 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) |
| 1658 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_MASK) |
| 1659 | #define CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_RESET 0x1 // 1 |
| 1660 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19 |
| 1661 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15 |
| 1662 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000 |
| 1663 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) |
| 1664 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) |
| 1665 | #define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0x0 // 0 |
| 1666 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14 |
| 1667 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10 |
| 1668 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00 |
| 1669 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) |
| 1670 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) |
| 1671 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0x0 // 0 |
| 1672 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9 |
| 1673 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5 |
| 1674 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0 |
| 1675 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) |
| 1676 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) |
| 1677 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0x0 // 0 |
| 1678 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4 |
| 1679 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4 |
| 1680 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010 |
| 1681 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) |
| 1682 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) |
| 1683 | #define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 0x1 // 1 |
| 1684 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3 |
| 1685 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3 |
| 1686 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008 |
| 1687 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) |
| 1688 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) |
| 1689 | #define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 0x1 // 1 |
| 1690 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2 |
| 1691 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2 |
| 1692 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004 |
| 1693 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) |
| 1694 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) |
| 1695 | #define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 0x1 // 1 |
| 1696 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1 |
| 1697 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1 |
| 1698 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002 |
| 1699 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) |
| 1700 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) |
| 1701 | #define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0x0 // 0 |
| 1702 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0 |
| 1703 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0 |
| 1704 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001 |
| 1705 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) |
| 1706 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) |
| 1707 | #define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0x0 // 0 |
| 1708 | #define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050008 |
| 1709 | |
| 1710 | #define PCIE_PLL_CONFIG_UPDATING_MSB 31 |
| 1711 | #define PCIE_PLL_CONFIG_UPDATING_LSB 31 |
| 1712 | #define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000 |
| 1713 | #define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB) |
| 1714 | #define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK) |
| 1715 | #define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0 |
| 1716 | #define PCIE_PLL_CONFIG_PLLPWD_MSB 30 |
| 1717 | #define PCIE_PLL_CONFIG_PLLPWD_LSB 30 |
| 1718 | #define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000 |
| 1719 | #define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB) |
| 1720 | #define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK) |
| 1721 | #define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 |
| 1722 | #define PCIE_PLL_CONFIG_BYPASS_MSB 16 |
| 1723 | #define PCIE_PLL_CONFIG_BYPASS_LSB 16 |
| 1724 | #define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000 |
| 1725 | #define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB) |
| 1726 | #define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK) |
| 1727 | #define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1 |
| 1728 | #define PCIE_PLL_CONFIG_REFDIV_MSB 14 |
| 1729 | #define PCIE_PLL_CONFIG_REFDIV_LSB 10 |
| 1730 | #define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00 |
| 1731 | #define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB) |
| 1732 | #define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK) |
| 1733 | #define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1 |
| 1734 | #define PCIE_PLL_CONFIG_ADDRESS 0x18050010 |
| 1735 | |
| 1736 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31 |
| 1737 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31 |
| 1738 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000 |
| 1739 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) |
| 1740 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) |
| 1741 | #define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1 |
| 1742 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30 |
| 1743 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30 |
| 1744 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000 |
| 1745 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) |
| 1746 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) |
| 1747 | #define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1 |
| 1748 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20 |
| 1749 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15 |
| 1750 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000 |
| 1751 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) |
| 1752 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) |
| 1753 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19 |
| 1754 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14 |
| 1755 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1 |
| 1756 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe |
| 1757 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) |
| 1758 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) |
| 1759 | #define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383 |
| 1760 | #define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050014 |
| 1761 | |
| 1762 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20 |
| 1763 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15 |
| 1764 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000 |
| 1765 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) |
| 1766 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) |
| 1767 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19 |
| 1768 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14 |
| 1769 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1 |
| 1770 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe |
| 1771 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) |
| 1772 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) |
| 1773 | #define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749 |
| 1774 | #define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x18050018 |
| 1775 | |
| 1776 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31 |
| 1777 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28 |
| 1778 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000 |
| 1779 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) |
| 1780 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) |
| 1781 | #define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0 |
| 1782 | #define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24 |
| 1783 | #define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15 |
| 1784 | #define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000 |
| 1785 | #define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB) |
| 1786 | #define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) |
| 1787 | #define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0 |
| 1788 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14 |
| 1789 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1 |
| 1790 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe |
| 1791 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) |
| 1792 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) |
| 1793 | #define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10 |
| 1794 | #define PCIE_PLL_DITHER_STEP_ADDRESS 0x1805001c |
| 1795 | |
| 1796 | |
| 1797 | |
| 1798 | // 32'h180f0008 (PCIE_PWR_MGMT) |
| 1799 | #define PCIE_PWR_MGMT_PME_INT_MSB 8 |
| 1800 | #define PCIE_PWR_MGMT_PME_INT_LSB 8 |
| 1801 | #define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100 |
| 1802 | #define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB) |
| 1803 | #define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK) |
| 1804 | #define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0 |
| 1805 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7 |
| 1806 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7 |
| 1807 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080 |
| 1808 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) |
| 1809 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) |
| 1810 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0 |
| 1811 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6 |
| 1812 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6 |
| 1813 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040 |
| 1814 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) |
| 1815 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) |
| 1816 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0 |
| 1817 | #define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5 |
| 1818 | #define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5 |
| 1819 | #define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020 |
| 1820 | #define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB) |
| 1821 | #define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) |
| 1822 | #define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0 |
| 1823 | #define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4 |
| 1824 | #define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4 |
| 1825 | #define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010 |
| 1826 | #define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB) |
| 1827 | #define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) |
| 1828 | #define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0 |
| 1829 | #define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3 |
| 1830 | #define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3 |
| 1831 | #define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008 |
| 1832 | #define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB) |
| 1833 | #define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) |
| 1834 | #define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0 |
| 1835 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2 |
| 1836 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2 |
| 1837 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004 |
| 1838 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) |
| 1839 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) |
| 1840 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0 |
| 1841 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1 |
| 1842 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1 |
| 1843 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002 |
| 1844 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) |
| 1845 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) |
| 1846 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0 |
| 1847 | #define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0 |
| 1848 | #define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0 |
| 1849 | #define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001 |
| 1850 | #define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB) |
| 1851 | #define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) |
| 1852 | #define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0 |
| 1853 | #define PCIE_PWR_MGMT_ADDRESS 0x180f0008 |
| 1854 | #define PCIE_PWR_MGMT_OFFSET 0x0008 |
| 1855 | // SW modifiable bits |
| 1856 | #define PCIE_PWR_MGMT_SW_MASK 0x000001ff |
| 1857 | // bits defined at reset |
| 1858 | #define PCIE_PWR_MGMT_RSTMASK 0xffffffff |
| 1859 | // reset value (ignore bits undefined at reset) |
| 1860 | #define PCIE_PWR_MGMT_RESET 0x00000000 |
| 1861 | |
| 1862 | |
| 1863 | // 32'h180600c0 (RST_CLKGAT_EN) |
| 1864 | #define RST_CLKGAT_EN_SPARE_MSB 31 |
| 1865 | #define RST_CLKGAT_EN_SPARE_LSB 12 |
| 1866 | #define RST_CLKGAT_EN_SPARE_MASK 0xfffff000 |
| 1867 | #define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB) |
| 1868 | #define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK) |
| 1869 | #define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0 |
| 1870 | #define RST_CLKGAT_EN_WMAC_MSB 9 |
| 1871 | #define RST_CLKGAT_EN_WMAC_LSB 9 |
| 1872 | #define RST_CLKGAT_EN_WMAC_MASK 0x00000200 |
| 1873 | #define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB) |
| 1874 | #define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK) |
| 1875 | #define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1 |
| 1876 | #define RST_CLKGAT_EN_USB1_MSB 7 |
| 1877 | #define RST_CLKGAT_EN_USB1_LSB 7 |
| 1878 | #define RST_CLKGAT_EN_USB1_MASK 0x00000080 |
| 1879 | #define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB) |
| 1880 | #define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK) |
| 1881 | #define RST_CLKGAT_EN_USB1_RESET 0x1 // 1 |
| 1882 | #define RST_CLKGAT_EN_GE1_MSB 6 |
| 1883 | #define RST_CLKGAT_EN_GE1_LSB 6 |
| 1884 | #define RST_CLKGAT_EN_GE1_MASK 0x00000040 |
| 1885 | #define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB) |
| 1886 | #define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK) |
| 1887 | #define RST_CLKGAT_EN_GE1_RESET 0x1 // 1 |
| 1888 | #define RST_CLKGAT_EN_GE0_MSB 5 |
| 1889 | #define RST_CLKGAT_EN_GE0_LSB 5 |
| 1890 | #define RST_CLKGAT_EN_GE0_MASK 0x00000020 |
| 1891 | #define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB) |
| 1892 | #define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK) |
| 1893 | #define RST_CLKGAT_EN_GE0_RESET 0x1 // 1 |
| 1894 | #define RST_CLKGAT_EN_PCIE_RC_MSB 1 |
| 1895 | #define RST_CLKGAT_EN_PCIE_RC_LSB 1 |
| 1896 | #define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002 |
| 1897 | #define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB) |
| 1898 | #define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK) |
| 1899 | #define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1 |
| 1900 | #define RST_CLKGAT_EN_ADDRESS 0x180600c0 |
| 1901 | #define RST_CLKGAT_EN_OFFSET 0x00c0 |
| 1902 | // SW modifiable bits |
| 1903 | #define RST_CLKGAT_EN_SW_MASK 0xfffff2e2 |
| 1904 | // bits defined at reset |
| 1905 | #define RST_CLKGAT_EN_RSTMASK 0xffffffff |
| 1906 | // reset value (ignore bits undefined at reset) |
| 1907 | #define RST_CLKGAT_EN_RESET 0x000002e2 |
| 1908 | |
| 1909 | |
| 1910 | |
| 1911 | #define PCIE_PHY_REG_1_ADDRESS 0x18116cc0 |
| 1912 | #define PCIE_PHY_REG_3_ADDRESS 0x18116cc8 |
| 1913 | |
| 1914 | |
| 1915 | |
| 1916 | |
| 1917 | |
| 1918 | #define LDO_POWER_CONTROL_PKG_SEL_MSB 5 |
| 1919 | #define LDO_POWER_CONTROL_PKG_SEL_LSB 5 |
| 1920 | #define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020 |
| 1921 | #define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB) |
| 1922 | #define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK) |
| 1923 | #define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0 |
| 1924 | #define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4 |
| 1925 | #define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4 |
| 1926 | #define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010 |
| 1927 | #define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB) |
| 1928 | #define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) |
| 1929 | #define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0 |
| 1930 | #define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3 |
| 1931 | #define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3 |
| 1932 | #define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008 |
| 1933 | #define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB) |
| 1934 | #define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) |
| 1935 | #define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0 |
| 1936 | #define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2 |
| 1937 | #define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1 |
| 1938 | #define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006 |
| 1939 | #define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB) |
| 1940 | #define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) |
| 1941 | #define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3 |
| 1942 | #define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0 |
| 1943 | #define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0 |
| 1944 | #define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001 |
| 1945 | #define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB) |
| 1946 | #define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) |
| 1947 | #define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0 |
| 1948 | #define LDO_POWER_CONTROL_ADDRESS 0x18050020 |
| 1949 | |
| 1950 | #define SWITCH_CLOCK_SPARE_SPARE_MSB 31 |
| 1951 | #define SWITCH_CLOCK_SPARE_SPARE_LSB 12 |
| 1952 | #define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfffff000 |
| 1953 | #define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB) |
| 1954 | #define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK) |
| 1955 | #define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0 |
| 1956 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11 |
| 1957 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8 |
| 1958 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00 |
| 1959 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) |
| 1960 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) |
| 1961 | #define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5 |
| 1962 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7 |
| 1963 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7 |
| 1964 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080 |
| 1965 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) |
| 1966 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) |
| 1967 | #define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0 |
| 1968 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MSB 6 |
| 1969 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB 6 |
| 1970 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK 0x00000040 |
| 1971 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) |
| 1972 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_MASK) |
| 1973 | #define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL_RESET 0x0 // 0 |
| 1974 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 5 |
| 1975 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 5 |
| 1976 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00000020 |
| 1977 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) |
| 1978 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) |
| 1979 | #define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1 |
| 1980 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 4 |
| 1981 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 4 |
| 1982 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00000010 |
| 1983 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) |
| 1984 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) |
| 1985 | #define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1 |
| 1986 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 3 |
| 1987 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 3 |
| 1988 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00000008 |
| 1989 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) |
| 1990 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) |
| 1991 | #define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0 |
| 1992 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MSB 2 |
| 1993 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB 2 |
| 1994 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK 0x00000004 |
| 1995 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) |
| 1996 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_MASK) |
| 1997 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_FROM_PYTHON_OFF_RESET 0x0 // 0 |
| 1998 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 1 |
| 1999 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 1 |
| 2000 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00000002 |
| 2001 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) |
| 2002 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) |
| 2003 | #define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0 |
| 2004 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 0 |
| 2005 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 0 |
| 2006 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00000001 |
| 2007 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) |
| 2008 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) |
| 2009 | #define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1 |
| 2010 | #define SWITCH_CLOCK_SPARE_ADDRESS 0x18050024 |
| 2011 | |
| 2012 | #define CURRENT_PCIE_PLL_DITHER_INT_MSB 20 |
| 2013 | #define CURRENT_PCIE_PLL_DITHER_INT_LSB 15 |
| 2014 | #define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000 |
| 2015 | #define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB) |
| 2016 | #define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK) |
| 2017 | #define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1 |
| 2018 | #define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13 |
| 2019 | #define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0 |
| 2020 | #define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff |
| 2021 | #define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB) |
| 2022 | #define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) |
| 2023 | #define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0 |
| 2024 | #define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x18050028 |
| 2025 | |
| 2026 | #define ETH_XMII_TX_INVERT_MSB 31 |
| 2027 | #define ETH_XMII_TX_INVERT_LSB 31 |
| 2028 | #define ETH_XMII_TX_INVERT_MASK 0x80000000 |
| 2029 | #define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB) |
| 2030 | #define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK) |
| 2031 | #define ETH_XMII_TX_INVERT_RESET 0x0 // 0 |
| 2032 | #define ETH_XMII_GIGE_QUAD_MSB 30 |
| 2033 | #define ETH_XMII_GIGE_QUAD_LSB 30 |
| 2034 | #define ETH_XMII_GIGE_QUAD_MASK 0x40000000 |
| 2035 | #define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB) |
| 2036 | #define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK) |
| 2037 | #define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0 |
| 2038 | #define ETH_XMII_RX_DELAY_MSB 29 |
| 2039 | #define ETH_XMII_RX_DELAY_LSB 28 |
| 2040 | #define ETH_XMII_RX_DELAY_MASK 0x30000000 |
| 2041 | #define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB) |
| 2042 | #define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK) |
| 2043 | #define ETH_XMII_RX_DELAY_RESET 0x0 // 0 |
| 2044 | #define ETH_XMII_TX_DELAY_MSB 27 |
| 2045 | #define ETH_XMII_TX_DELAY_LSB 26 |
| 2046 | #define ETH_XMII_TX_DELAY_MASK 0x0c000000 |
| 2047 | #define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB) |
| 2048 | #define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK) |
| 2049 | #define ETH_XMII_TX_DELAY_RESET 0x0 // 0 |
| 2050 | #define ETH_XMII_GIGE_MSB 25 |
| 2051 | #define ETH_XMII_GIGE_LSB 25 |
| 2052 | #define ETH_XMII_GIGE_MASK 0x02000000 |
| 2053 | #define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB) |
| 2054 | #define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK) |
| 2055 | #define ETH_XMII_GIGE_RESET 0x0 // 0 |
| 2056 | #define ETH_XMII_OFFSET_PHASE_MSB 24 |
| 2057 | #define ETH_XMII_OFFSET_PHASE_LSB 24 |
| 2058 | #define ETH_XMII_OFFSET_PHASE_MASK 0x01000000 |
| 2059 | #define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB) |
| 2060 | #define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK) |
| 2061 | #define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0 |
| 2062 | #define ETH_XMII_OFFSET_COUNT_MSB 23 |
| 2063 | #define ETH_XMII_OFFSET_COUNT_LSB 16 |
| 2064 | #define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000 |
| 2065 | #define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB) |
| 2066 | #define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK) |
| 2067 | #define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0 |
| 2068 | #define ETH_XMII_PHASE1_COUNT_MSB 15 |
| 2069 | #define ETH_XMII_PHASE1_COUNT_LSB 8 |
| 2070 | #define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00 |
| 2071 | #define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB) |
| 2072 | #define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK) |
| 2073 | #define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1 |
| 2074 | #define ETH_XMII_PHASE0_COUNT_MSB 7 |
| 2075 | #define ETH_XMII_PHASE0_COUNT_LSB 0 |
| 2076 | #define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff |
| 2077 | #define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB) |
| 2078 | #define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK) |
| 2079 | #define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1 |
| 2080 | #define ETH_XMII_ADDRESS 0x1805002c |
| 2081 | |
| 2082 | #define BB_PLL_CONFIG_UPDATING_MSB 31 |
| 2083 | #define BB_PLL_CONFIG_UPDATING_LSB 31 |
| 2084 | #define BB_PLL_CONFIG_UPDATING_MASK 0x80000000 |
| 2085 | #define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB) |
| 2086 | #define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK) |
| 2087 | #define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1 |
| 2088 | #define BB_PLL_CONFIG_PLLPWD_MSB 30 |
| 2089 | #define BB_PLL_CONFIG_PLLPWD_LSB 30 |
| 2090 | #define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000 |
| 2091 | #define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB) |
| 2092 | #define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK) |
| 2093 | #define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1 |
| 2094 | #define BB_PLL_CONFIG_SPARE_MSB 29 |
| 2095 | #define BB_PLL_CONFIG_SPARE_LSB 29 |
| 2096 | #define BB_PLL_CONFIG_SPARE_MASK 0x20000000 |
| 2097 | #define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB) |
| 2098 | #define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK) |
| 2099 | #define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0 |
| 2100 | #define BB_PLL_CONFIG_REFDIV_MSB 28 |
| 2101 | #define BB_PLL_CONFIG_REFDIV_LSB 24 |
| 2102 | #define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000 |
| 2103 | #define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB) |
| 2104 | #define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK) |
| 2105 | #define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1 |
| 2106 | #define BB_PLL_CONFIG_NINT_MSB 21 |
| 2107 | #define BB_PLL_CONFIG_NINT_LSB 16 |
| 2108 | #define BB_PLL_CONFIG_NINT_MASK 0x003f0000 |
| 2109 | #define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB) |
| 2110 | #define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK) |
| 2111 | #define BB_PLL_CONFIG_NINT_RESET 0x2 // 2 |
| 2112 | #define BB_PLL_CONFIG_NFRAC_MSB 13 |
| 2113 | #define BB_PLL_CONFIG_NFRAC_LSB 0 |
| 2114 | #define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff |
| 2115 | #define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB) |
| 2116 | #define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK) |
| 2117 | #define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276 |
| 2118 | #define BB_PLL_CONFIG_ADDRESS 0x18050040 |
| 2119 | |
| 2120 | #define DDR_PLL_DITHER_DITHER_EN_MSB 31 |
| 2121 | #define DDR_PLL_DITHER_DITHER_EN_LSB 31 |
| 2122 | #define DDR_PLL_DITHER_DITHER_EN_MASK 0x80000000 |
| 2123 | #define DDR_PLL_DITHER_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB) |
| 2124 | #define DDR_PLL_DITHER_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK) |
| 2125 | #define DDR_PLL_DITHER_DITHER_EN_RESET 0x0 // 0 |
| 2126 | #define DDR_PLL_DITHER_UPDATE_COUNT_MSB 30 |
| 2127 | #define DDR_PLL_DITHER_UPDATE_COUNT_LSB 27 |
| 2128 | #define DDR_PLL_DITHER_UPDATE_COUNT_MASK 0x78000000 |
| 2129 | #define DDR_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB) |
| 2130 | #define DDR_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) |
| 2131 | #define DDR_PLL_DITHER_UPDATE_COUNT_RESET 0xf // 15 |
| 2132 | #define DDR_PLL_DITHER_NFRAC_STEP_MSB 26 |
| 2133 | #define DDR_PLL_DITHER_NFRAC_STEP_LSB 20 |
| 2134 | #define DDR_PLL_DITHER_NFRAC_STEP_MASK 0x07f00000 |
| 2135 | #define DDR_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB) |
| 2136 | #define DDR_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK) |
| 2137 | #define DDR_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1 |
| 2138 | #define DDR_PLL_DITHER_NFRAC_MIN_MSB 19 |
| 2139 | #define DDR_PLL_DITHER_NFRAC_MIN_LSB 10 |
| 2140 | #define DDR_PLL_DITHER_NFRAC_MIN_MASK 0x000ffc00 |
| 2141 | #define DDR_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB) |
| 2142 | #define DDR_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK) |
| 2143 | #define DDR_PLL_DITHER_NFRAC_MIN_RESET 0x19 // 25 |
| 2144 | #define DDR_PLL_DITHER_NFRAC_MAX_MSB 9 |
| 2145 | #define DDR_PLL_DITHER_NFRAC_MAX_LSB 0 |
| 2146 | #define DDR_PLL_DITHER_NFRAC_MAX_MASK 0x000003ff |
| 2147 | #define DDR_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB) |
| 2148 | #define DDR_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK) |
| 2149 | #define DDR_PLL_DITHER_NFRAC_MAX_RESET 0x3e8 // 1000 |
| 2150 | #define DDR_PLL_DITHER_ADDRESS 0x18050044 |
| 2151 | |
| 2152 | #define CPU_PLL_DITHER_DITHER_EN_MSB 31 |
| 2153 | #define CPU_PLL_DITHER_DITHER_EN_LSB 31 |
| 2154 | #define CPU_PLL_DITHER_DITHER_EN_MASK 0x80000000 |
| 2155 | #define CPU_PLL_DITHER_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB) |
| 2156 | #define CPU_PLL_DITHER_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK) |
| 2157 | #define CPU_PLL_DITHER_DITHER_EN_RESET 0x0 // 0 |
| 2158 | #define CPU_PLL_DITHER_UPDATE_COUNT_MSB 23 |
| 2159 | #define CPU_PLL_DITHER_UPDATE_COUNT_LSB 18 |
| 2160 | #define CPU_PLL_DITHER_UPDATE_COUNT_MASK 0x00fc0000 |
| 2161 | #define CPU_PLL_DITHER_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB) |
| 2162 | #define CPU_PLL_DITHER_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) |
| 2163 | #define CPU_PLL_DITHER_UPDATE_COUNT_RESET 0x14 // 20 |
| 2164 | #define CPU_PLL_DITHER_NFRAC_STEP_MSB 17 |
| 2165 | #define CPU_PLL_DITHER_NFRAC_STEP_LSB 12 |
| 2166 | #define CPU_PLL_DITHER_NFRAC_STEP_MASK 0x0003f000 |
| 2167 | #define CPU_PLL_DITHER_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB) |
| 2168 | #define CPU_PLL_DITHER_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK) |
| 2169 | #define CPU_PLL_DITHER_NFRAC_STEP_RESET 0x1 // 1 |
| 2170 | #define CPU_PLL_DITHER_NFRAC_MIN_MSB 11 |
| 2171 | #define CPU_PLL_DITHER_NFRAC_MIN_LSB 6 |
| 2172 | #define CPU_PLL_DITHER_NFRAC_MIN_MASK 0x00000fc0 |
| 2173 | #define CPU_PLL_DITHER_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB) |
| 2174 | #define CPU_PLL_DITHER_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK) |
| 2175 | #define CPU_PLL_DITHER_NFRAC_MIN_RESET 0x3 // 3 |
| 2176 | #define CPU_PLL_DITHER_NFRAC_MAX_MSB 5 |
| 2177 | #define CPU_PLL_DITHER_NFRAC_MAX_LSB 0 |
| 2178 | #define CPU_PLL_DITHER_NFRAC_MAX_MASK 0x0000003f |
| 2179 | #define CPU_PLL_DITHER_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB) |
| 2180 | #define CPU_PLL_DITHER_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK) |
| 2181 | #define CPU_PLL_DITHER_NFRAC_MAX_RESET 0x3c // 60 |
| 2182 | #define CPU_PLL_DITHER_ADDRESS 0x18050048 |
| 2183 | |
| 2184 | #define RST_RESET_USB_EXT_PWR_SEQ_MSB 29 |
| 2185 | #define RST_RESET_USB_EXT_PWR_SEQ_LSB 29 |
| 2186 | #define RST_RESET_USB_EXT_PWR_SEQ_MASK 0x20000000 |
| 2187 | #define RST_RESET_USB_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET_USB_EXT_PWR_SEQ_MASK) >> RST_RESET_USB_EXT_PWR_SEQ_LSB) |
| 2188 | #define RST_RESET_USB_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET_USB_EXT_PWR_SEQ_LSB) & RST_RESET_USB_EXT_PWR_SEQ_MASK) |
| 2189 | #define RST_RESET_USB_EXT_PWR_SEQ_RESET 0x1 // 1 |
| 2190 | #define RST_RESET_EXTERNAL_RESET_MSB 28 |
| 2191 | #define RST_RESET_EXTERNAL_RESET_LSB 28 |
| 2192 | #define RST_RESET_EXTERNAL_RESET_MASK 0x10000000 |
| 2193 | #define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB) |
| 2194 | #define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK) |
| 2195 | #define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0 |
| 2196 | #define RST_RESET_RTC_RESET_MSB 27 |
| 2197 | #define RST_RESET_RTC_RESET_LSB 27 |
| 2198 | #define RST_RESET_RTC_RESET_MASK 0x08000000 |
| 2199 | #define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB) |
| 2200 | #define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK) |
| 2201 | #define RST_RESET_RTC_RESET_RESET 0x1 // 1 |
| 2202 | #define RST_RESET_FULL_CHIP_RESET_MSB 24 |
| 2203 | #define RST_RESET_FULL_CHIP_RESET_LSB 24 |
| 2204 | #define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000 |
| 2205 | #define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB) |
| 2206 | #define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK) |
| 2207 | #define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0 |
| 2208 | #define RST_RESET_GE1_MDIO_RESET_MSB 23 |
| 2209 | #define RST_RESET_GE1_MDIO_RESET_LSB 23 |
| 2210 | #define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000 |
| 2211 | #define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB) |
| 2212 | #define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK) |
| 2213 | #define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1 |
| 2214 | #define RST_RESET_GE0_MDIO_RESET_MSB 22 |
| 2215 | #define RST_RESET_GE0_MDIO_RESET_LSB 22 |
| 2216 | #define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000 |
| 2217 | #define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB) |
| 2218 | #define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK) |
| 2219 | #define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1 |
| 2220 | #define RST_RESET_CPU_NMI_MSB 21 |
| 2221 | #define RST_RESET_CPU_NMI_LSB 21 |
| 2222 | #define RST_RESET_CPU_NMI_MASK 0x00200000 |
| 2223 | #define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB) |
| 2224 | #define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK) |
| 2225 | #define RST_RESET_CPU_NMI_RESET 0x0 // 0 |
| 2226 | #define RST_RESET_CPU_COLD_RESET_MSB 20 |
| 2227 | #define RST_RESET_CPU_COLD_RESET_LSB 20 |
| 2228 | #define RST_RESET_CPU_COLD_RESET_MASK 0x00100000 |
| 2229 | #define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB) |
| 2230 | #define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK) |
| 2231 | #define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0 |
| 2232 | #define RST_RESET_DDR_RESET_MSB 16 |
| 2233 | #define RST_RESET_DDR_RESET_LSB 16 |
| 2234 | #define RST_RESET_DDR_RESET_MASK 0x00010000 |
| 2235 | #define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB) |
| 2236 | #define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK) |
| 2237 | #define RST_RESET_DDR_RESET_RESET 0x0 // 0 |
| 2238 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15 |
| 2239 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15 |
| 2240 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000 |
| 2241 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) |
| 2242 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) |
| 2243 | #define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0 |
| 2244 | #define RST_RESET_GE1_MAC_RESET_MSB 13 |
| 2245 | #define RST_RESET_GE1_MAC_RESET_LSB 13 |
| 2246 | #define RST_RESET_GE1_MAC_RESET_MASK 0x00002000 |
| 2247 | #define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB) |
| 2248 | #define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK) |
| 2249 | #define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1 |
| 2250 | #define RST_RESET_ETH_SWITCH_ARESET_MSB 12 |
| 2251 | #define RST_RESET_ETH_SWITCH_ARESET_LSB 12 |
| 2252 | #define RST_RESET_ETH_SWITCH_ARESET_MASK 0x00001000 |
| 2253 | #define RST_RESET_ETH_SWITCH_ARESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ARESET_MASK) >> RST_RESET_ETH_SWITCH_ARESET_LSB) |
| 2254 | #define RST_RESET_ETH_SWITCH_ARESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ARESET_LSB) & RST_RESET_ETH_SWITCH_ARESET_MASK) |
| 2255 | #define RST_RESET_ETH_SWITCH_ARESET_RESET 0x1 // 1 |
| 2256 | #define RST_RESET_USB_PHY_ARESET_MSB 11 |
| 2257 | #define RST_RESET_USB_PHY_ARESET_LSB 11 |
| 2258 | #define RST_RESET_USB_PHY_ARESET_MASK 0x00000800 |
| 2259 | #define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB) |
| 2260 | #define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK) |
| 2261 | #define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1 |
| 2262 | #define RST_RESET_GE0_MAC_RESET_MSB 9 |
| 2263 | #define RST_RESET_GE0_MAC_RESET_LSB 9 |
| 2264 | #define RST_RESET_GE0_MAC_RESET_MASK 0x00000200 |
| 2265 | #define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB) |
| 2266 | #define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK) |
| 2267 | #define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1 |
| 2268 | #define RST_RESET_ETH_SWITCH_RESET_MSB 8 |
| 2269 | #define RST_RESET_ETH_SWITCH_RESET_LSB 8 |
| 2270 | #define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000100 |
| 2271 | #define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB) |
| 2272 | #define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK) |
| 2273 | #define RST_RESET_ETH_SWITCH_RESET_RESET 0x1 // 1 |
| 2274 | #define RST_RESET_PCIE_PHY_RESET_MSB 7 |
| 2275 | #define RST_RESET_PCIE_PHY_RESET_LSB 7 |
| 2276 | #define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080 |
| 2277 | #define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB) |
| 2278 | #define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK) |
| 2279 | #define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1 |
| 2280 | #define RST_RESET_PCIE_RESET_MSB 6 |
| 2281 | #define RST_RESET_PCIE_RESET_LSB 6 |
| 2282 | #define RST_RESET_PCIE_RESET_MASK 0x00000040 |
| 2283 | #define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB) |
| 2284 | #define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK) |
| 2285 | #define RST_RESET_PCIE_RESET_RESET 0x1 // 1 |
| 2286 | #define RST_RESET_USB_HOST_RESET_MSB 5 |
| 2287 | #define RST_RESET_USB_HOST_RESET_LSB 5 |
| 2288 | #define RST_RESET_USB_HOST_RESET_MASK 0x00000020 |
| 2289 | #define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB) |
| 2290 | #define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK) |
| 2291 | #define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1 |
| 2292 | #define RST_RESET_USB_PHY_RESET_MSB 4 |
| 2293 | #define RST_RESET_USB_PHY_RESET_LSB 4 |
| 2294 | #define RST_RESET_USB_PHY_RESET_MASK 0x00000010 |
| 2295 | #define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB) |
| 2296 | #define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK) |
| 2297 | #define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1 |
| 2298 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3 |
| 2299 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3 |
| 2300 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008 |
| 2301 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) |
| 2302 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) |
| 2303 | #define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0 |
| 2304 | #define RST_RESET_ADDRESS 0x1806001c |
| 2305 | |
| 2306 | |
| 2307 | #define RST_MISC2_SPARE_MSB 31 |
| 2308 | #define RST_MISC2_SPARE_LSB 26 |
| 2309 | #define RST_MISC2_SPARE_MASK 0xfc000000 |
| 2310 | #define RST_MISC2_SPARE_GET(x) (((x) & RST_MISC2_SPARE_MASK) >> RST_MISC2_SPARE_LSB) |
| 2311 | #define RST_MISC2_SPARE_SET(x) (((x) << RST_MISC2_SPARE_LSB) & RST_MISC2_SPARE_MASK) |
| 2312 | #define RST_MISC2_SPARE_RESET 0x0 // 0 |
| 2313 | #define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 19 |
| 2314 | #define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 19 |
| 2315 | #define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x00080000 |
| 2316 | #define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB) |
| 2317 | #define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) |
| 2318 | #define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0 |
| 2319 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18 |
| 2320 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18 |
| 2321 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000 |
| 2322 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) |
| 2323 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) |
| 2324 | #define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0 |
| 2325 | #define RST_MISC2_PERSTN_RCPHY_MSB 13 |
| 2326 | #define RST_MISC2_PERSTN_RCPHY_LSB 13 |
| 2327 | #define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000 |
| 2328 | #define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB) |
| 2329 | #define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK) |
| 2330 | #define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1 |
| 2331 | #define RST_MISC2_RESERVED_MSB 3 |
| 2332 | #define RST_MISC2_RESERVED_LSB 1 |
| 2333 | #define RST_MISC2_RESERVED_MASK 0x0000000e |
| 2334 | #define RST_MISC2_RESERVED_GET(x) (((x) & RST_MISC2_RESERVED_MASK) >> RST_MISC2_RESERVED_LSB) |
| 2335 | #define RST_MISC2_RESERVED_SET(x) (((x) << RST_MISC2_RESERVED_LSB) & RST_MISC2_RESERVED_MASK) |
| 2336 | #define RST_MISC2_RESERVED_RESET 0x0 // 0 |
| 2337 | #define RST_MISC2_ADDRESS 0x180600bc |
| 2338 | |
| 2339 | #define PCIE_APP_CFG_TYPE_MSB 21 |
| 2340 | #define PCIE_APP_CFG_TYPE_LSB 20 |
| 2341 | #define PCIE_APP_CFG_TYPE_MASK 0x00300000 |
| 2342 | #define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB) |
| 2343 | #define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK) |
| 2344 | #define PCIE_APP_CFG_TYPE_RESET 0x0 // 0 |
| 2345 | #define PCIE_APP_PCIE_BAR_MSN_MSB 19 |
| 2346 | #define PCIE_APP_PCIE_BAR_MSN_LSB 16 |
| 2347 | #define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000 |
| 2348 | #define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB) |
| 2349 | #define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK) |
| 2350 | #define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1 |
| 2351 | #define PCIE_APP_CFG_BE_MSB 15 |
| 2352 | #define PCIE_APP_CFG_BE_LSB 12 |
| 2353 | #define PCIE_APP_CFG_BE_MASK 0x0000f000 |
| 2354 | #define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB) |
| 2355 | #define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK) |
| 2356 | #define PCIE_APP_CFG_BE_RESET 0xf // 15 |
| 2357 | #define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11 |
| 2358 | #define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6 |
| 2359 | #define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0 |
| 2360 | #define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB) |
| 2361 | #define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) |
| 2362 | #define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63 |
| 2363 | #define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5 |
| 2364 | #define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4 |
| 2365 | #define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030 |
| 2366 | #define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB) |
| 2367 | #define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) |
| 2368 | #define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0 |
| 2369 | #define PCIE_APP_INIT_RST_MSB 3 |
| 2370 | #define PCIE_APP_INIT_RST_LSB 3 |
| 2371 | #define PCIE_APP_INIT_RST_MASK 0x00000008 |
| 2372 | #define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB) |
| 2373 | #define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK) |
| 2374 | #define PCIE_APP_INIT_RST_RESET 0x0 // 0 |
| 2375 | #define PCIE_APP_PM_XMT_TURNOFF_MSB 2 |
| 2376 | #define PCIE_APP_PM_XMT_TURNOFF_LSB 2 |
| 2377 | #define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004 |
| 2378 | #define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB) |
| 2379 | #define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK) |
| 2380 | #define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0 |
| 2381 | #define PCIE_APP_UNLOCK_MSG_MSB 1 |
| 2382 | #define PCIE_APP_UNLOCK_MSG_LSB 1 |
| 2383 | #define PCIE_APP_UNLOCK_MSG_MASK 0x00000002 |
| 2384 | #define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB) |
| 2385 | #define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK) |
| 2386 | #define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0 |
| 2387 | #define PCIE_APP_LTSSM_ENABLE_MSB 0 |
| 2388 | #define PCIE_APP_LTSSM_ENABLE_LSB 0 |
| 2389 | #define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001 |
| 2390 | #define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB) |
| 2391 | #define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK) |
| 2392 | #define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0 |
| 2393 | #define PCIE_APP_ADDRESS 0x180f0000 |
| 2394 | |
| 2395 | #define PCIE_PWR_MGMT_PME_INT_MSB 8 |
| 2396 | #define PCIE_PWR_MGMT_PME_INT_LSB 8 |
| 2397 | #define PCIE_PWR_MGMT_PME_INT_MASK 0x00000100 |
| 2398 | #define PCIE_PWR_MGMT_PME_INT_GET(x) (((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB) |
| 2399 | #define PCIE_PWR_MGMT_PME_INT_SET(x) (((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK) |
| 2400 | #define PCIE_PWR_MGMT_PME_INT_RESET 0x0 // 0 |
| 2401 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB 7 |
| 2402 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB 7 |
| 2403 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK 0x00000080 |
| 2404 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x) (((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) |
| 2405 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x) (((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) |
| 2406 | #define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET 0x0 // 0 |
| 2407 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB 6 |
| 2408 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB 6 |
| 2409 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK 0x00000040 |
| 2410 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) |
| 2411 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) |
| 2412 | #define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET 0x0 // 0 |
| 2413 | #define PCIE_PWR_MGMT_RADM_PM_PME_MSB 5 |
| 2414 | #define PCIE_PWR_MGMT_RADM_PM_PME_LSB 5 |
| 2415 | #define PCIE_PWR_MGMT_RADM_PM_PME_MASK 0x00000020 |
| 2416 | #define PCIE_PWR_MGMT_RADM_PM_PME_GET(x) (((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB) |
| 2417 | #define PCIE_PWR_MGMT_RADM_PM_PME_SET(x) (((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) |
| 2418 | #define PCIE_PWR_MGMT_RADM_PM_PME_RESET 0x0 // 0 |
| 2419 | #define PCIE_PWR_MGMT_AUX_PM_EN_MSB 4 |
| 2420 | #define PCIE_PWR_MGMT_AUX_PM_EN_LSB 4 |
| 2421 | #define PCIE_PWR_MGMT_AUX_PM_EN_MASK 0x00000010 |
| 2422 | #define PCIE_PWR_MGMT_AUX_PM_EN_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB) |
| 2423 | #define PCIE_PWR_MGMT_AUX_PM_EN_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) |
| 2424 | #define PCIE_PWR_MGMT_AUX_PM_EN_RESET 0x0 // 0 |
| 2425 | #define PCIE_PWR_MGMT_READY_ENTR_L23_MSB 3 |
| 2426 | #define PCIE_PWR_MGMT_READY_ENTR_L23_LSB 3 |
| 2427 | #define PCIE_PWR_MGMT_READY_ENTR_L23_MASK 0x00000008 |
| 2428 | #define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x) (((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB) |
| 2429 | #define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x) (((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) |
| 2430 | #define PCIE_PWR_MGMT_READY_ENTR_L23_RESET 0x0 // 0 |
| 2431 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB 2 |
| 2432 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB 2 |
| 2433 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK 0x00000004 |
| 2434 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) |
| 2435 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) |
| 2436 | #define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET 0x0 // 0 |
| 2437 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB 1 |
| 2438 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB 1 |
| 2439 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK 0x00000002 |
| 2440 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x) (((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) |
| 2441 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x) (((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) |
| 2442 | #define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET 0x0 // 0 |
| 2443 | #define PCIE_PWR_MGMT_AUX_PWR_DET_MSB 0 |
| 2444 | #define PCIE_PWR_MGMT_AUX_PWR_DET_LSB 0 |
| 2445 | #define PCIE_PWR_MGMT_AUX_PWR_DET_MASK 0x00000001 |
| 2446 | #define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x) (((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB) |
| 2447 | #define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x) (((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) |
| 2448 | #define PCIE_PWR_MGMT_AUX_PWR_DET_RESET 0x0 // 0 |
| 2449 | #define PCIE_PWR_MGMT_ADDRESS 0x180f0008 |
| 2450 | #define PCIE_PWR_MGMT_OFFSET 0x0008 |
| 2451 | // SW modifiable bits |
| 2452 | #define PCIE_PWR_MGMT_SW_MASK 0x000001ff |
| 2453 | // bits defined at reset |
| 2454 | #define PCIE_PWR_MGMT_RSTMASK 0xffffffff |
| 2455 | // reset value (ignore bits undefined at reset) |
| 2456 | #define PCIE_PWR_MGMT_RESET 0x00000000 |
| 2457 | |
| 2458 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31 |
| 2459 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31 |
| 2460 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000 |
| 2461 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) |
| 2462 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) |
| 2463 | #define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0 |
| 2464 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30 |
| 2465 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29 |
| 2466 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000 |
| 2467 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) |
| 2468 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) |
| 2469 | #define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0 |
| 2470 | #define PCIE_PHY_REG_1_PERSTDELAY_MSB 28 |
| 2471 | #define PCIE_PHY_REG_1_PERSTDELAY_LSB 27 |
| 2472 | #define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000 |
| 2473 | #define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB) |
| 2474 | #define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK) |
| 2475 | #define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2 |
| 2476 | #define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26 |
| 2477 | #define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25 |
| 2478 | #define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000 |
| 2479 | #define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB) |
| 2480 | #define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) |
| 2481 | #define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0 |
| 2482 | #define PCIE_PHY_REG_1_DATAOBSEN_MSB 24 |
| 2483 | #define PCIE_PHY_REG_1_DATAOBSEN_LSB 24 |
| 2484 | #define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000 |
| 2485 | #define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB) |
| 2486 | #define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK) |
| 2487 | #define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0 |
| 2488 | #define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23 |
| 2489 | #define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23 |
| 2490 | #define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000 |
| 2491 | #define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB) |
| 2492 | #define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) |
| 2493 | #define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0 |
| 2494 | #define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22 |
| 2495 | #define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22 |
| 2496 | #define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000 |
| 2497 | #define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB) |
| 2498 | #define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) |
| 2499 | #define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0 |
| 2500 | #define PCIE_PHY_REG_1_RXCLKINV_MSB 21 |
| 2501 | #define PCIE_PHY_REG_1_RXCLKINV_LSB 21 |
| 2502 | #define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000 |
| 2503 | #define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB) |
| 2504 | #define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK) |
| 2505 | #define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1 |
| 2506 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20 |
| 2507 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20 |
| 2508 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000 |
| 2509 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) |
| 2510 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) |
| 2511 | #define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0 |
| 2512 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19 |
| 2513 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19 |
| 2514 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000 |
| 2515 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) |
| 2516 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) |
| 2517 | #define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0 |
| 2518 | #define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18 |
| 2519 | #define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18 |
| 2520 | #define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000 |
| 2521 | #define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB) |
| 2522 | #define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) |
| 2523 | #define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0 |
| 2524 | #define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17 |
| 2525 | #define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17 |
| 2526 | #define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000 |
| 2527 | #define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB) |
| 2528 | #define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) |
| 2529 | #define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0 |
| 2530 | #define PCIE_PHY_REG_1_SEL_CLK_MSB 16 |
| 2531 | #define PCIE_PHY_REG_1_SEL_CLK_LSB 15 |
| 2532 | #define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000 |
| 2533 | #define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB) |
| 2534 | #define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK) |
| 2535 | #define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2 |
| 2536 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14 |
| 2537 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14 |
| 2538 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000 |
| 2539 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) |
| 2540 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) |
| 2541 | #define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0 |
| 2542 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13 |
| 2543 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13 |
| 2544 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000 |
| 2545 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) |
| 2546 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) |
| 2547 | #define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1 |
| 2548 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12 |
| 2549 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12 |
| 2550 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000 |
| 2551 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) |
| 2552 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) |
| 2553 | #define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0 |
| 2554 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11 |
| 2555 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11 |
| 2556 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800 |
| 2557 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) |
| 2558 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) |
| 2559 | #define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0 |
| 2560 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10 |
| 2561 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9 |
| 2562 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600 |
| 2563 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) |
| 2564 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) |
| 2565 | #define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3 |
| 2566 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8 |
| 2567 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7 |
| 2568 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180 |
| 2569 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) |
| 2570 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) |
| 2571 | #define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0 |
| 2572 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6 |
| 2573 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6 |
| 2574 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040 |
| 2575 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) |
| 2576 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) |
| 2577 | #define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1 |
| 2578 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5 |
| 2579 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5 |
| 2580 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020 |
| 2581 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) |
| 2582 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) |
| 2583 | #define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0 |
| 2584 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4 |
| 2585 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4 |
| 2586 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010 |
| 2587 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) |
| 2588 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) |
| 2589 | #define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1 |
| 2590 | #define PCIE_PHY_REG_1_S_MSB 3 |
| 2591 | #define PCIE_PHY_REG_1_S_LSB 0 |
| 2592 | #define PCIE_PHY_REG_1_S_MASK 0x0000000f |
| 2593 | #define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB) |
| 2594 | #define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK) |
| 2595 | #define PCIE_PHY_REG_1_S_RESET 0xe // 14 |
| 2596 | #define PCIE_PHY_REG_1_ADDRESS 0x18116cc0 |
| 2597 | #define PCIE_PHY_REG_1_OFFSET 0x0000 |
| 2598 | // SW modifiable bits |
| 2599 | #define PCIE_PHY_REG_1_SW_MASK 0xffffffff |
| 2600 | // bits defined at reset |
| 2601 | #define PCIE_PHY_REG_1_RSTMASK 0xffffffff |
| 2602 | // reset value (ignore bits undefined at reset) |
| 2603 | #define PCIE_PHY_REG_1_RESET 0x1021265e |
| 2604 | #define PCIE_PHY_REG_1_RESET_1 0x0061060e |
| 2605 | |
| 2606 | // 32'h18116cc4 (PCIE_PHY_REG_2) |
| 2607 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MSB 31 |
| 2608 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB 24 |
| 2609 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK 0xff000000 |
| 2610 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) |
| 2611 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) |
| 2612 | #define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_RESET 0x0 // 0 |
| 2613 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB 23 |
| 2614 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB 23 |
| 2615 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK 0x00800000 |
| 2616 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) |
| 2617 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) |
| 2618 | #define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET 0x0 // 0 |
| 2619 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MSB 22 |
| 2620 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB 22 |
| 2621 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK 0x00400000 |
| 2622 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x) (((x) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) |
| 2623 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x) (((x) << PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) |
| 2624 | #define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_RESET 0x0 // 0 |
| 2625 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MSB 21 |
| 2626 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB 21 |
| 2627 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK 0x00200000 |
| 2628 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) |
| 2629 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) |
| 2630 | #define PCIE_PHY_REG_2_PRBS_SCRAMBLE_RESET 0x0 // 0 |
| 2631 | #define PCIE_PHY_REG_2_PRBS_START_MSB 20 |
| 2632 | #define PCIE_PHY_REG_2_PRBS_START_LSB 20 |
| 2633 | #define PCIE_PHY_REG_2_PRBS_START_MASK 0x00100000 |
| 2634 | #define PCIE_PHY_REG_2_PRBS_START_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_START_MASK) >> PCIE_PHY_REG_2_PRBS_START_LSB) |
| 2635 | #define PCIE_PHY_REG_2_PRBS_START_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_START_LSB) & PCIE_PHY_REG_2_PRBS_START_MASK) |
| 2636 | #define PCIE_PHY_REG_2_PRBS_START_RESET 0x0 // 0 |
| 2637 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_MSB 19 |
| 2638 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_LSB 13 |
| 2639 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_MASK 0x000fe000 |
| 2640 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_GET(x) (((x) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) |
| 2641 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_SET(x) (((x) << PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) |
| 2642 | #define PCIE_PHY_REG_2_PRBS_TS_NUM_RESET 0x40 // 64 |
| 2643 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MSB 12 |
| 2644 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB 12 |
| 2645 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK 0x00001000 |
| 2646 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) |
| 2647 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) |
| 2648 | #define PCIE_PHY_REG_2_TXDETRXOVRVALUE_RESET 0x0 // 0 |
| 2649 | #define PCIE_PHY_REG_2_TXDETRXOVREN_MSB 11 |
| 2650 | #define PCIE_PHY_REG_2_TXDETRXOVREN_LSB 11 |
| 2651 | #define PCIE_PHY_REG_2_TXDETRXOVREN_MASK 0x00000800 |
| 2652 | #define PCIE_PHY_REG_2_TXDETRXOVREN_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_PHY_REG_2_TXDETRXOVREN_LSB) |
| 2653 | #define PCIE_PHY_REG_2_TXDETRXOVREN_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) |
| 2654 | #define PCIE_PHY_REG_2_TXDETRXOVREN_RESET 0x0 // 0 |
| 2655 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_MSB 10 |
| 2656 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB 10 |
| 2657 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK 0x00000400 |
| 2658 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_GET(x) (((x) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) |
| 2659 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_SET(x) (((x) << PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) |
| 2660 | #define PCIE_PHY_REG_2_DATAOBSPRBSERR_RESET 0x0 // 0 |
| 2661 | #define PCIE_PHY_REG_2_CDRREADYTIMER_MSB 9 |
| 2662 | #define PCIE_PHY_REG_2_CDRREADYTIMER_LSB 6 |
| 2663 | #define PCIE_PHY_REG_2_CDRREADYTIMER_MASK 0x000003c0 |
| 2664 | #define PCIE_PHY_REG_2_CDRREADYTIMER_GET(x) (((x) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_PHY_REG_2_CDRREADYTIMER_LSB) |
| 2665 | #define PCIE_PHY_REG_2_CDRREADYTIMER_SET(x) (((x) << PCIE_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) |
| 2666 | #define PCIE_PHY_REG_2_CDRREADYTIMER_RESET 0x7 // 7 |
| 2667 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MSB 5 |
| 2668 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB 1 |
| 2669 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK 0x0000003e |
| 2670 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_GET(x) (((x) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) |
| 2671 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_SET(x) (((x) << PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) |
| 2672 | #define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_RESET 0xc // 12 |
| 2673 | #define PCIE_PHY_REG_2_FORCEDETECT_MSB 0 |
| 2674 | #define PCIE_PHY_REG_2_FORCEDETECT_LSB 0 |
| 2675 | #define PCIE_PHY_REG_2_FORCEDETECT_MASK 0x00000001 |
| 2676 | #define PCIE_PHY_REG_2_FORCEDETECT_GET(x) (((x) & PCIE_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_PHY_REG_2_FORCEDETECT_LSB) |
| 2677 | #define PCIE_PHY_REG_2_FORCEDETECT_SET(x) (((x) << PCIE_PHY_REG_2_FORCEDETECT_LSB) & PCIE_PHY_REG_2_FORCEDETECT_MASK) |
| 2678 | #define PCIE_PHY_REG_2_FORCEDETECT_RESET 0x0 // 0 |
| 2679 | #define PCIE_PHY_REG_2_ADDRESS 0x18116cc4 |
| 2680 | #define PCIE_PHY_REG_2_OFFSET 0x0004 |
| 2681 | // SW modifiable bits |
| 2682 | #define PCIE_PHY_REG_2_SW_MASK 0xffffffff |
| 2683 | // bits defined at reset |
| 2684 | #define PCIE_PHY_REG_2_RSTMASK 0xffffffff |
| 2685 | // reset value (ignore bits undefined at reset) |
| 2686 | #define PCIE_PHY_REG_2_RESET 0x000801d8 |
| 2687 | |
| 2688 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MSB 31 |
| 2689 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB 28 |
| 2690 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK 0xf0000000 |
| 2691 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_GET(x) (((x) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) |
| 2692 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_SET(x) (((x) << PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) |
| 2693 | #define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_RESET 0x0 // 0 |
| 2694 | #define PCIE_PHY_REG_3_SPARE_MSB 27 |
| 2695 | #define PCIE_PHY_REG_3_SPARE_LSB 11 |
| 2696 | #define PCIE_PHY_REG_3_SPARE_MASK 0x0ffff800 |
| 2697 | #define PCIE_PHY_REG_3_SPARE_GET(x) (((x) & PCIE_PHY_REG_3_SPARE_MASK) >> PCIE_PHY_REG_3_SPARE_LSB) |
| 2698 | #define PCIE_PHY_REG_3_SPARE_SET(x) (((x) << PCIE_PHY_REG_3_SPARE_LSB) & PCIE_PHY_REG_3_SPARE_MASK) |
| 2699 | #define PCIE_PHY_REG_3_SPARE_RESET 0xa0b // 2571 |
| 2700 | #define PCIE_PHY_REG_3_SEL_CLK100_MSB 10 |
| 2701 | #define PCIE_PHY_REG_3_SEL_CLK100_LSB 10 |
| 2702 | #define PCIE_PHY_REG_3_SEL_CLK100_MASK 0x00000400 |
| 2703 | #define PCIE_PHY_REG_3_SEL_CLK100_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_PHY_REG_3_SEL_CLK100_LSB) |
| 2704 | #define PCIE_PHY_REG_3_SEL_CLK100_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK100_LSB) & PCIE_PHY_REG_3_SEL_CLK100_MASK) |
| 2705 | #define PCIE_PHY_REG_3_SEL_CLK100_RESET 0x0 // 0 |
| 2706 | #define PCIE_PHY_REG_3_EN_BEACONGEN_MSB 9 |
| 2707 | #define PCIE_PHY_REG_3_EN_BEACONGEN_LSB 9 |
| 2708 | #define PCIE_PHY_REG_3_EN_BEACONGEN_MASK 0x00000200 |
| 2709 | #define PCIE_PHY_REG_3_EN_BEACONGEN_GET(x) (((x) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_PHY_REG_3_EN_BEACONGEN_LSB) |
| 2710 | #define PCIE_PHY_REG_3_EN_BEACONGEN_SET(x) (((x) << PCIE_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) |
| 2711 | #define PCIE_PHY_REG_3_EN_BEACONGEN_RESET 0x0 // 0 |
| 2712 | #define PCIE_PHY_REG_3_TXELECIDLE_MSB 8 |
| 2713 | #define PCIE_PHY_REG_3_TXELECIDLE_LSB 8 |
| 2714 | #define PCIE_PHY_REG_3_TXELECIDLE_MASK 0x00000100 |
| 2715 | #define PCIE_PHY_REG_3_TXELECIDLE_GET(x) (((x) & PCIE_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_PHY_REG_3_TXELECIDLE_LSB) |
| 2716 | #define PCIE_PHY_REG_3_TXELECIDLE_SET(x) (((x) << PCIE_PHY_REG_3_TXELECIDLE_LSB) & PCIE_PHY_REG_3_TXELECIDLE_MASK) |
| 2717 | #define PCIE_PHY_REG_3_TXELECIDLE_RESET 0x0 // 0 |
| 2718 | #define PCIE_PHY_REG_3_SEL_CLK_MSB 7 |
| 2719 | #define PCIE_PHY_REG_3_SEL_CLK_LSB 6 |
| 2720 | #define PCIE_PHY_REG_3_SEL_CLK_MASK 0x000000c0 |
| 2721 | #define PCIE_PHY_REG_3_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_3_SEL_CLK_MASK) >> PCIE_PHY_REG_3_SEL_CLK_LSB) |
| 2722 | #define PCIE_PHY_REG_3_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_3_SEL_CLK_LSB) & PCIE_PHY_REG_3_SEL_CLK_MASK) |
| 2723 | #define PCIE_PHY_REG_3_SEL_CLK_RESET 0x0 // 0 |
| 2724 | #define PCIE_PHY_REG_3_RX_DET_REQ_MSB 5 |
| 2725 | #define PCIE_PHY_REG_3_RX_DET_REQ_LSB 5 |
| 2726 | #define PCIE_PHY_REG_3_RX_DET_REQ_MASK 0x00000020 |
| 2727 | #define PCIE_PHY_REG_3_RX_DET_REQ_GET(x) (((x) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_PHY_REG_3_RX_DET_REQ_LSB) |
| 2728 | #define PCIE_PHY_REG_3_RX_DET_REQ_SET(x) (((x) << PCIE_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) |
| 2729 | #define PCIE_PHY_REG_3_RX_DET_REQ_RESET 0x0 // 0 |
| 2730 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_MSB 4 |
| 2731 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_LSB 4 |
| 2732 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_MASK 0x00000010 |
| 2733 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_GET(x) (((x) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) |
| 2734 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_SET(x) (((x) << PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) |
| 2735 | #define PCIE_PHY_REG_3_MODE_OCLK_IN_RESET 0x0 // 0 |
| 2736 | #define PCIE_PHY_REG_3_EN_PLL_MSB 3 |
| 2737 | #define PCIE_PHY_REG_3_EN_PLL_LSB 3 |
| 2738 | #define PCIE_PHY_REG_3_EN_PLL_MASK 0x00000008 |
| 2739 | #define PCIE_PHY_REG_3_EN_PLL_GET(x) (((x) & PCIE_PHY_REG_3_EN_PLL_MASK) >> PCIE_PHY_REG_3_EN_PLL_LSB) |
| 2740 | #define PCIE_PHY_REG_3_EN_PLL_SET(x) (((x) << PCIE_PHY_REG_3_EN_PLL_LSB) & PCIE_PHY_REG_3_EN_PLL_MASK) |
| 2741 | #define PCIE_PHY_REG_3_EN_PLL_RESET 0x1 // 1 |
| 2742 | #define PCIE_PHY_REG_3_EN_LCKDT_MSB 2 |
| 2743 | #define PCIE_PHY_REG_3_EN_LCKDT_LSB 2 |
| 2744 | #define PCIE_PHY_REG_3_EN_LCKDT_MASK 0x00000004 |
| 2745 | #define PCIE_PHY_REG_3_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_PHY_REG_3_EN_LCKDT_LSB) |
| 2746 | #define PCIE_PHY_REG_3_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_3_EN_LCKDT_LSB) & PCIE_PHY_REG_3_EN_LCKDT_MASK) |
| 2747 | #define PCIE_PHY_REG_3_EN_LCKDT_RESET 0x1 // 1 |
| 2748 | #define PCIE_PHY_REG_3_EN_BUFS_RX_MSB 1 |
| 2749 | #define PCIE_PHY_REG_3_EN_BUFS_RX_LSB 1 |
| 2750 | #define PCIE_PHY_REG_3_EN_BUFS_RX_MASK 0x00000002 |
| 2751 | #define PCIE_PHY_REG_3_EN_BUFS_RX_GET(x) (((x) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_PHY_REG_3_EN_BUFS_RX_LSB) |
| 2752 | #define PCIE_PHY_REG_3_EN_BUFS_RX_SET(x) (((x) << PCIE_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) |
| 2753 | #define PCIE_PHY_REG_3_EN_BUFS_RX_RESET 0x0 // 0 |
| 2754 | #define PCIE_PHY_REG_3_EN_MSB 0 |
| 2755 | #define PCIE_PHY_REG_3_EN_LSB 0 |
| 2756 | #define PCIE_PHY_REG_3_EN_MASK 0x00000001 |
| 2757 | #define PCIE_PHY_REG_3_EN_GET(x) (((x) & PCIE_PHY_REG_3_EN_MASK) >> PCIE_PHY_REG_3_EN_LSB) |
| 2758 | #define PCIE_PHY_REG_3_EN_SET(x) (((x) << PCIE_PHY_REG_3_EN_LSB) & PCIE_PHY_REG_3_EN_MASK) |
| 2759 | #define PCIE_PHY_REG_3_EN_RESET 0x0 // 0 |
| 2760 | #define PCIE_PHY_REG_3_ADDRESS 0x18116cc8 |
| 2761 | #define PCIE_PHY_REG_3_OFFSET 0x0008 |
| 2762 | // SW modifiable bits |
| 2763 | #define PCIE_PHY_REG_3_SW_MASK 0xffffffff |
| 2764 | // bits defined at reset |
| 2765 | #define PCIE_PHY_REG_3_RSTMASK 0xffffffff |
| 2766 | // reset value (ignore bits undefined at reset) |
| 2767 | #define PCIE_PHY_REG_3_RESET 0x0050580c |
| 2768 | #define PCIE_PHY_REG_3_RESET_1 0x00505900 |
| 2769 | |
| 2770 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MSB 31 |
| 2771 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB 11 |
| 2772 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK 0xfffff800 |
| 2773 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) >> PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) |
| 2774 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_ERROR_RATE_LSB) & PCIE_PHY_REG_4_PRBS_ERROR_RATE_MASK) |
| 2775 | #define PCIE_PHY_REG_4_PRBS_ERROR_RATE_RESET 0xa000 // 40960 |
| 2776 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MSB 10 |
| 2777 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB 1 |
| 2778 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK 0x000007fe |
| 2779 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) >> PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) |
| 2780 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_LSB) & PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_MASK) |
| 2781 | #define PCIE_PHY_REG_4_PRBS_TOTAL_NUMOF_ERR_RESET 0x0 // 0 |
| 2782 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MSB 0 |
| 2783 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB 0 |
| 2784 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK 0x00000001 |
| 2785 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_GET(x) (((x) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) >> PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) |
| 2786 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_SET(x) (((x) << PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_LSB) & PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_MASK) |
| 2787 | #define PCIE_PHY_REG_4_PRBS_TRIGGER_ERROR_RESET 0x0 // 0 |
| 2788 | #define PCIE_PHY_REG_4_ADDRESS 0x18116ccc |
| 2789 | #define PCIE_PHY_REG_4_OFFSET 0x000c |
| 2790 | // SW modifiable bits |
| 2791 | #define PCIE_PHY_REG_4_SW_MASK 0xffffffff |
| 2792 | // bits defined at reset |
| 2793 | #define PCIE_PHY_REG_4_RSTMASK 0xffffffff |
| 2794 | // reset value (ignore bits undefined at reset) |
| 2795 | #define PCIE_PHY_REG_4_RESET 0x05000000 |
| 2796 | |
| 2797 | #define XTAL_TCXODET_MSB 31 |
| 2798 | #define XTAL_TCXODET_LSB 31 |
| 2799 | #define XTAL_TCXODET_MASK 0x80000000 |
| 2800 | #define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB) |
| 2801 | #define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK) |
| 2802 | #define XTAL_TCXODET_RESET 0x0 // 0 |
| 2803 | #define XTAL_XTAL_CAPINDAC_MSB 30 |
| 2804 | #define XTAL_XTAL_CAPINDAC_LSB 24 |
| 2805 | #define XTAL_XTAL_CAPINDAC_MASK 0x7f000000 |
| 2806 | #define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB) |
| 2807 | #define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK) |
| 2808 | #define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75 |
| 2809 | #define XTAL_XTAL_CAPOUTDAC_MSB 23 |
| 2810 | #define XTAL_XTAL_CAPOUTDAC_LSB 17 |
| 2811 | #define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000 |
| 2812 | #define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB) |
| 2813 | #define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK) |
| 2814 | #define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75 |
| 2815 | #define XTAL_XTAL_DRVSTR_MSB 16 |
| 2816 | #define XTAL_XTAL_DRVSTR_LSB 15 |
| 2817 | #define XTAL_XTAL_DRVSTR_MASK 0x00018000 |
| 2818 | #define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB) |
| 2819 | #define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK) |
| 2820 | #define XTAL_XTAL_DRVSTR_RESET 0x0 // 0 |
| 2821 | #define XTAL_XTAL_SHORTXIN_MSB 14 |
| 2822 | #define XTAL_XTAL_SHORTXIN_LSB 14 |
| 2823 | #define XTAL_XTAL_SHORTXIN_MASK 0x00004000 |
| 2824 | #define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB) |
| 2825 | #define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK) |
| 2826 | #define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0 |
| 2827 | #define XTAL_XTAL_LOCALBIAS_MSB 13 |
| 2828 | #define XTAL_XTAL_LOCALBIAS_LSB 13 |
| 2829 | #define XTAL_XTAL_LOCALBIAS_MASK 0x00002000 |
| 2830 | #define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB) |
| 2831 | #define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK) |
| 2832 | #define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1 |
| 2833 | #define XTAL_XTAL_PWDCLKD_MSB 12 |
| 2834 | #define XTAL_XTAL_PWDCLKD_LSB 12 |
| 2835 | #define XTAL_XTAL_PWDCLKD_MASK 0x00001000 |
| 2836 | #define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB) |
| 2837 | #define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK) |
| 2838 | #define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0 |
| 2839 | #define XTAL_XTAL_BIAS2X_MSB 11 |
| 2840 | #define XTAL_XTAL_BIAS2X_LSB 11 |
| 2841 | #define XTAL_XTAL_BIAS2X_MASK 0x00000800 |
| 2842 | #define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB) |
| 2843 | #define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK) |
| 2844 | #define XTAL_XTAL_BIAS2X_RESET 0x0 // 0 |
| 2845 | #define XTAL_XTAL_LBIAS2X_MSB 10 |
| 2846 | #define XTAL_XTAL_LBIAS2X_LSB 10 |
| 2847 | #define XTAL_XTAL_LBIAS2X_MASK 0x00000400 |
| 2848 | #define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB) |
| 2849 | #define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK) |
| 2850 | #define XTAL_XTAL_LBIAS2X_RESET 0x0 // 0 |
| 2851 | #define XTAL_XTAL_SELVREG_MSB 9 |
| 2852 | #define XTAL_XTAL_SELVREG_LSB 9 |
| 2853 | #define XTAL_XTAL_SELVREG_MASK 0x00000200 |
| 2854 | #define XTAL_XTAL_SELVREG_GET(x) (((x) & XTAL_XTAL_SELVREG_MASK) >> XTAL_XTAL_SELVREG_LSB) |
| 2855 | #define XTAL_XTAL_SELVREG_SET(x) (((x) << XTAL_XTAL_SELVREG_LSB) & XTAL_XTAL_SELVREG_MASK) |
| 2856 | #define XTAL_XTAL_SELVREG_RESET 0x0 // 0 |
| 2857 | #define XTAL_XTAL_OSCON_MSB 8 |
| 2858 | #define XTAL_XTAL_OSCON_LSB 8 |
| 2859 | #define XTAL_XTAL_OSCON_MASK 0x00000100 |
| 2860 | #define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB) |
| 2861 | #define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK) |
| 2862 | #define XTAL_XTAL_OSCON_RESET 0x1 // 1 |
| 2863 | #define XTAL_XTAL_PWDCLKIN_MSB 7 |
| 2864 | #define XTAL_XTAL_PWDCLKIN_LSB 7 |
| 2865 | #define XTAL_XTAL_PWDCLKIN_MASK 0x00000080 |
| 2866 | #define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB) |
| 2867 | #define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK) |
| 2868 | #define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0 |
| 2869 | #define XTAL_LOCAL_XTAL_MSB 6 |
| 2870 | #define XTAL_LOCAL_XTAL_LSB 6 |
| 2871 | #define XTAL_LOCAL_XTAL_MASK 0x00000040 |
| 2872 | #define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB) |
| 2873 | #define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK) |
| 2874 | #define XTAL_LOCAL_XTAL_RESET 0x0 // 0 |
| 2875 | #define XTAL_PWD_SWREGCLK_MSB 5 |
| 2876 | #define XTAL_PWD_SWREGCLK_LSB 5 |
| 2877 | #define XTAL_PWD_SWREGCLK_MASK 0x00000020 |
| 2878 | #define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB) |
| 2879 | #define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK) |
| 2880 | #define XTAL_PWD_SWREGCLK_RESET 0x0 // 0 |
| 2881 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_MSB 4 |
| 2882 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_LSB 4 |
| 2883 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_MASK 0x00000010 |
| 2884 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) >> XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) |
| 2885 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) |
| 2886 | #define XTAL_LOCAL_EXT_CLK_OUT_EN_RESET 0x0 // 0 |
| 2887 | #define XTAL_EXT_CLK_OUT_EN_MSB 3 |
| 2888 | #define XTAL_EXT_CLK_OUT_EN_LSB 3 |
| 2889 | #define XTAL_EXT_CLK_OUT_EN_MASK 0x00000008 |
| 2890 | #define XTAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_EXT_CLK_OUT_EN_MASK) >> XTAL_EXT_CLK_OUT_EN_LSB) |
| 2891 | #define XTAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_EXT_CLK_OUT_EN_LSB) & XTAL_EXT_CLK_OUT_EN_MASK) |
| 2892 | #define XTAL_EXT_CLK_OUT_EN_RESET 0x0 // 0 |
| 2893 | #define XTAL_XTAL_SVREG_MSB 2 |
| 2894 | #define XTAL_XTAL_SVREG_LSB 2 |
| 2895 | #define XTAL_XTAL_SVREG_MASK 0x00000004 |
| 2896 | #define XTAL_XTAL_SVREG_GET(x) (((x) & XTAL_XTAL_SVREG_MASK) >> XTAL_XTAL_SVREG_LSB) |
| 2897 | #define XTAL_XTAL_SVREG_SET(x) (((x) << XTAL_XTAL_SVREG_LSB) & XTAL_XTAL_SVREG_MASK) |
| 2898 | #define XTAL_XTAL_SVREG_RESET 0x0 // 0 |
| 2899 | #define XTAL_RBK_UDSEL_MSB 1 |
| 2900 | #define XTAL_RBK_UDSEL_LSB 1 |
| 2901 | #define XTAL_RBK_UDSEL_MASK 0x00000002 |
| 2902 | #define XTAL_RBK_UDSEL_GET(x) (((x) & XTAL_RBK_UDSEL_MASK) >> XTAL_RBK_UDSEL_LSB) |
| 2903 | #define XTAL_RBK_UDSEL_SET(x) (((x) << XTAL_RBK_UDSEL_LSB) & XTAL_RBK_UDSEL_MASK) |
| 2904 | #define XTAL_RBK_UDSEL_RESET 0x0 // 0 |
| 2905 | #define XTAL_SPARE_MSB 0 |
| 2906 | #define XTAL_SPARE_LSB 0 |
| 2907 | #define XTAL_SPARE_MASK 0x00000001 |
| 2908 | #define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB) |
| 2909 | #define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK) |
| 2910 | #define XTAL_SPARE_RESET 0x0 // 0 |
| 2911 | #define XTAL_ADDRESS 0x181162c0 |
| 2912 | |
| 2913 | #define XTAL2_TDC_COUNT_MSB 31 |
| 2914 | #define XTAL2_TDC_COUNT_LSB 26 |
| 2915 | #define XTAL2_TDC_COUNT_MASK 0xfc000000 |
| 2916 | #define XTAL2_TDC_COUNT_GET(x) (((x) & XTAL2_TDC_COUNT_MASK) >> XTAL2_TDC_COUNT_LSB) |
| 2917 | #define XTAL2_TDC_COUNT_SET(x) (((x) << XTAL2_TDC_COUNT_LSB) & XTAL2_TDC_COUNT_MASK) |
| 2918 | #define XTAL2_TDC_COUNT_RESET 0x0 // 0 |
| 2919 | #define XTAL2_TDC_PH_COUNT_MSB 25 |
| 2920 | #define XTAL2_TDC_PH_COUNT_LSB 21 |
| 2921 | #define XTAL2_TDC_PH_COUNT_MASK 0x03e00000 |
| 2922 | #define XTAL2_TDC_PH_COUNT_GET(x) (((x) & XTAL2_TDC_PH_COUNT_MASK) >> XTAL2_TDC_PH_COUNT_LSB) |
| 2923 | #define XTAL2_TDC_PH_COUNT_SET(x) (((x) << XTAL2_TDC_PH_COUNT_LSB) & XTAL2_TDC_PH_COUNT_MASK) |
| 2924 | #define XTAL2_TDC_PH_COUNT_RESET 0x0 // 0 |
| 2925 | #define XTAL2_DUTY_UP_MSB 20 |
| 2926 | #define XTAL2_DUTY_UP_LSB 16 |
| 2927 | #define XTAL2_DUTY_UP_MASK 0x001f0000 |
| 2928 | #define XTAL2_DUTY_UP_GET(x) (((x) & XTAL2_DUTY_UP_MASK) >> XTAL2_DUTY_UP_LSB) |
| 2929 | #define XTAL2_DUTY_UP_SET(x) (((x) << XTAL2_DUTY_UP_LSB) & XTAL2_DUTY_UP_MASK) |
| 2930 | #define XTAL2_DUTY_UP_RESET 0x0 // 0 |
| 2931 | #define XTAL2_DUTY_DN_MSB 15 |
| 2932 | #define XTAL2_DUTY_DN_LSB 11 |
| 2933 | #define XTAL2_DUTY_DN_MASK 0x0000f800 |
| 2934 | #define XTAL2_DUTY_DN_GET(x) (((x) & XTAL2_DUTY_DN_MASK) >> XTAL2_DUTY_DN_LSB) |
| 2935 | #define XTAL2_DUTY_DN_SET(x) (((x) << XTAL2_DUTY_DN_LSB) & XTAL2_DUTY_DN_MASK) |
| 2936 | #define XTAL2_DUTY_DN_RESET 0x0 // 0 |
| 2937 | #define XTAL2_DCA_BYPASS_MSB 10 |
| 2938 | #define XTAL2_DCA_BYPASS_LSB 10 |
| 2939 | #define XTAL2_DCA_BYPASS_MASK 0x00000400 |
| 2940 | #define XTAL2_DCA_BYPASS_GET(x) (((x) & XTAL2_DCA_BYPASS_MASK) >> XTAL2_DCA_BYPASS_LSB) |
| 2941 | #define XTAL2_DCA_BYPASS_SET(x) (((x) << XTAL2_DCA_BYPASS_LSB) & XTAL2_DCA_BYPASS_MASK) |
| 2942 | #define XTAL2_DCA_BYPASS_RESET 0x1 // 1 |
| 2943 | #define XTAL2_DCA_SWCAL_MSB 9 |
| 2944 | #define XTAL2_DCA_SWCAL_LSB 9 |
| 2945 | #define XTAL2_DCA_SWCAL_MASK 0x00000200 |
| 2946 | #define XTAL2_DCA_SWCAL_GET(x) (((x) & XTAL2_DCA_SWCAL_MASK) >> XTAL2_DCA_SWCAL_LSB) |
| 2947 | #define XTAL2_DCA_SWCAL_SET(x) (((x) << XTAL2_DCA_SWCAL_LSB) & XTAL2_DCA_SWCAL_MASK) |
| 2948 | #define XTAL2_DCA_SWCAL_RESET 0x0 // 0 |
| 2949 | #define XTAL2_FSM_UD_HOLD_MSB 8 |
| 2950 | #define XTAL2_FSM_UD_HOLD_LSB 8 |
| 2951 | #define XTAL2_FSM_UD_HOLD_MASK 0x00000100 |
| 2952 | #define XTAL2_FSM_UD_HOLD_GET(x) (((x) & XTAL2_FSM_UD_HOLD_MASK) >> XTAL2_FSM_UD_HOLD_LSB) |
| 2953 | #define XTAL2_FSM_UD_HOLD_SET(x) (((x) << XTAL2_FSM_UD_HOLD_LSB) & XTAL2_FSM_UD_HOLD_MASK) |
| 2954 | #define XTAL2_FSM_UD_HOLD_RESET 0x0 // 0 |
| 2955 | #define XTAL2_FSM_START_L_MSB 7 |
| 2956 | #define XTAL2_FSM_START_L_LSB 7 |
| 2957 | #define XTAL2_FSM_START_L_MASK 0x00000080 |
| 2958 | #define XTAL2_FSM_START_L_GET(x) (((x) & XTAL2_FSM_START_L_MASK) >> XTAL2_FSM_START_L_LSB) |
| 2959 | #define XTAL2_FSM_START_L_SET(x) (((x) << XTAL2_FSM_START_L_LSB) & XTAL2_FSM_START_L_MASK) |
| 2960 | #define XTAL2_FSM_START_L_RESET 0x1 // 1 |
| 2961 | #define XTAL2_FSM_DN_READBACK_MSB 6 |
| 2962 | #define XTAL2_FSM_DN_READBACK_LSB 2 |
| 2963 | #define XTAL2_FSM_DN_READBACK_MASK 0x0000007c |
| 2964 | #define XTAL2_FSM_DN_READBACK_GET(x) (((x) & XTAL2_FSM_DN_READBACK_MASK) >> XTAL2_FSM_DN_READBACK_LSB) |
| 2965 | #define XTAL2_FSM_DN_READBACK_SET(x) (((x) << XTAL2_FSM_DN_READBACK_LSB) & XTAL2_FSM_DN_READBACK_MASK) |
| 2966 | #define XTAL2_FSM_DN_READBACK_RESET 0x0 // 0 |
| 2967 | #define XTAL2_TDC_SAT_FLAG_MSB 1 |
| 2968 | #define XTAL2_TDC_SAT_FLAG_LSB 1 |
| 2969 | #define XTAL2_TDC_SAT_FLAG_MASK 0x00000002 |
| 2970 | #define XTAL2_TDC_SAT_FLAG_GET(x) (((x) & XTAL2_TDC_SAT_FLAG_MASK) >> XTAL2_TDC_SAT_FLAG_LSB) |
| 2971 | #define XTAL2_TDC_SAT_FLAG_SET(x) (((x) << XTAL2_TDC_SAT_FLAG_LSB) & XTAL2_TDC_SAT_FLAG_MASK) |
| 2972 | #define XTAL2_TDC_SAT_FLAG_RESET 0x0 // 0 |
| 2973 | #define XTAL2_FSM_READY_MSB 0 |
| 2974 | #define XTAL2_FSM_READY_LSB 0 |
| 2975 | #define XTAL2_FSM_READY_MASK 0x00000001 |
| 2976 | #define XTAL2_FSM_READY_GET(x) (((x) & XTAL2_FSM_READY_MASK) >> XTAL2_FSM_READY_LSB) |
| 2977 | #define XTAL2_FSM_READY_SET(x) (((x) << XTAL2_FSM_READY_LSB) & XTAL2_FSM_READY_MASK) |
| 2978 | #define XTAL2_FSM_READY_RESET 0x0 // 0 |
| 2979 | #define XTAL2_ADDRESS 0x181162c4 |
| 2980 | |
| 2981 | #define XTAL3_FSM_UP_READBACK_MSB 31 |
| 2982 | #define XTAL3_FSM_UP_READBACK_LSB 27 |
| 2983 | #define XTAL3_FSM_UP_READBACK_MASK 0xf8000000 |
| 2984 | #define XTAL3_FSM_UP_READBACK_GET(x) (((x) & XTAL3_FSM_UP_READBACK_MASK) >> XTAL3_FSM_UP_READBACK_LSB) |
| 2985 | #define XTAL3_FSM_UP_READBACK_SET(x) (((x) << XTAL3_FSM_UP_READBACK_LSB) & XTAL3_FSM_UP_READBACK_MASK) |
| 2986 | #define XTAL3_FSM_UP_READBACK_RESET 0x0 // 0 |
| 2987 | #define XTAL3_EVAL_LENGTH_MSB 26 |
| 2988 | #define XTAL3_EVAL_LENGTH_LSB 16 |
| 2989 | #define XTAL3_EVAL_LENGTH_MASK 0x07ff0000 |
| 2990 | #define XTAL3_EVAL_LENGTH_GET(x) (((x) & XTAL3_EVAL_LENGTH_MASK) >> XTAL3_EVAL_LENGTH_LSB) |
| 2991 | #define XTAL3_EVAL_LENGTH_SET(x) (((x) << XTAL3_EVAL_LENGTH_LSB) & XTAL3_EVAL_LENGTH_MASK) |
| 2992 | #define XTAL3_EVAL_LENGTH_RESET 0x400 // 1024 |
| 2993 | #define XTAL3_TDC_ERROR_FLAG_MSB 15 |
| 2994 | #define XTAL3_TDC_ERROR_FLAG_LSB 15 |
| 2995 | #define XTAL3_TDC_ERROR_FLAG_MASK 0x00008000 |
| 2996 | #define XTAL3_TDC_ERROR_FLAG_GET(x) (((x) & XTAL3_TDC_ERROR_FLAG_MASK) >> XTAL3_TDC_ERROR_FLAG_LSB) |
| 2997 | #define XTAL3_TDC_ERROR_FLAG_SET(x) (((x) << XTAL3_TDC_ERROR_FLAG_LSB) & XTAL3_TDC_ERROR_FLAG_MASK) |
| 2998 | #define XTAL3_TDC_ERROR_FLAG_RESET 0x0 // 0 |
| 2999 | #define XTAL3_HARMONIC_NUMBER_MSB 14 |
| 3000 | #define XTAL3_HARMONIC_NUMBER_LSB 2 |
| 3001 | #define XTAL3_HARMONIC_NUMBER_MASK 0x00007ffc |
| 3002 | #define XTAL3_HARMONIC_NUMBER_GET(x) (((x) & XTAL3_HARMONIC_NUMBER_MASK) >> XTAL3_HARMONIC_NUMBER_LSB) |
| 3003 | #define XTAL3_HARMONIC_NUMBER_SET(x) (((x) << XTAL3_HARMONIC_NUMBER_LSB) & XTAL3_HARMONIC_NUMBER_MASK) |
| 3004 | #define XTAL3_HARMONIC_NUMBER_RESET 0x51 // 81 |
| 3005 | #define XTAL3_SPARE_MSB 1 |
| 3006 | #define XTAL3_SPARE_LSB 0 |
| 3007 | #define XTAL3_SPARE_MASK 0x00000003 |
| 3008 | #define XTAL3_SPARE_GET(x) (((x) & XTAL3_SPARE_MASK) >> XTAL3_SPARE_LSB) |
| 3009 | #define XTAL3_SPARE_SET(x) (((x) << XTAL3_SPARE_LSB) & XTAL3_SPARE_MASK) |
| 3010 | #define XTAL3_SPARE_RESET 0x0 // 0 |
| 3011 | #define XTAL3_ADDRESS 0x181162c8 |
| 3012 | |
| 3013 | #define RST_REVISION_ID_ADDRESS 0x18060090 |
| 3014 | #define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000)) |
| 3015 | |
| 3016 | #define RST_BOOTSTRAP_RES4_MSB 15 |
| 3017 | #define RST_BOOTSTRAP_RES4_LSB 13 |
| 3018 | #define RST_BOOTSTRAP_RES4_MASK 0x0000e000 |
| 3019 | #define RST_BOOTSTRAP_RES4_GET(x) (((x) & RST_BOOTSTRAP_RES4_MASK) >> RST_BOOTSTRAP_RES4_LSB) |
| 3020 | #define RST_BOOTSTRAP_RES4_SET(x) (((x) << RST_BOOTSTRAP_RES4_LSB) & RST_BOOTSTRAP_RES4_MASK) |
| 3021 | #define RST_BOOTSTRAP_RES4_RESET 0x0 // 0 |
| 3022 | #define RST_BOOTSTRAP_SW_OPTION2_MSB 12 |
| 3023 | #define RST_BOOTSTRAP_SW_OPTION2_LSB 12 |
| 3024 | #define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000 |
| 3025 | #define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB) |
| 3026 | #define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK) |
| 3027 | #define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0 |
| 3028 | #define RST_BOOTSTRAP_SW_OPTION1_MSB 11 |
| 3029 | #define RST_BOOTSTRAP_SW_OPTION1_LSB 11 |
| 3030 | #define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800 |
| 3031 | #define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB) |
| 3032 | #define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK) |
| 3033 | #define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0 |
| 3034 | #define RST_BOOTSTRAP_TESTROM_ENABLE_MSB 10 |
| 3035 | #define RST_BOOTSTRAP_TESTROM_ENABLE_LSB 10 |
| 3036 | #define RST_BOOTSTRAP_TESTROM_ENABLE_MASK 0x00000400 |
| 3037 | #define RST_BOOTSTRAP_TESTROM_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) >> RST_BOOTSTRAP_TESTROM_ENABLE_LSB) |
| 3038 | #define RST_BOOTSTRAP_TESTROM_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_ENABLE_LSB) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) |
| 3039 | #define RST_BOOTSTRAP_TESTROM_ENABLE_RESET 0x0 // 0 |
| 3040 | #define RST_BOOTSTRAP_RES3_MSB 9 |
| 3041 | #define RST_BOOTSTRAP_RES3_LSB 9 |
| 3042 | #define RST_BOOTSTRAP_RES3_MASK 0x00000200 |
| 3043 | #define RST_BOOTSTRAP_RES3_GET(x) (((x) & RST_BOOTSTRAP_RES3_MASK) >> RST_BOOTSTRAP_RES3_LSB) |
| 3044 | #define RST_BOOTSTRAP_RES3_SET(x) (((x) << RST_BOOTSTRAP_RES3_LSB) & RST_BOOTSTRAP_RES3_MASK) |
| 3045 | #define RST_BOOTSTRAP_RES3_RESET 0x0 // 0 |
| 3046 | #define RST_BOOTSTRAP_SRIF_ENABLE_MSB 8 |
| 3047 | #define RST_BOOTSTRAP_SRIF_ENABLE_LSB 8 |
| 3048 | #define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000100 |
| 3049 | #define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB) |
| 3050 | #define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) |
| 3051 | #define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0 |
| 3052 | #define RST_BOOTSTRAP_USB_MODE_MSB 7 |
| 3053 | #define RST_BOOTSTRAP_USB_MODE_LSB 7 |
| 3054 | #define RST_BOOTSTRAP_USB_MODE_MASK 0x00000080 |
| 3055 | #define RST_BOOTSTRAP_USB_MODE_GET(x) (((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB) |
| 3056 | #define RST_BOOTSTRAP_USB_MODE_SET(x) (((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK) |
| 3057 | #define RST_BOOTSTRAP_USB_MODE_RESET 0x0 // 0 |
| 3058 | #define RST_BOOTSTRAP_RES2_MSB 6 |
| 3059 | #define RST_BOOTSTRAP_RES2_LSB 6 |
| 3060 | #define RST_BOOTSTRAP_RES2_MASK 0x00000040 |
| 3061 | #define RST_BOOTSTRAP_RES2_GET(x) (((x) & RST_BOOTSTRAP_RES2_MASK) >> RST_BOOTSTRAP_RES2_LSB) |
| 3062 | #define RST_BOOTSTRAP_RES2_SET(x) (((x) << RST_BOOTSTRAP_RES2_LSB) & RST_BOOTSTRAP_RES2_MASK) |
| 3063 | #define RST_BOOTSTRAP_RES2_RESET 0x0 // 0 |
| 3064 | #define RST_BOOTSTRAP_EJTAG_MODE_MSB 5 |
| 3065 | #define RST_BOOTSTRAP_EJTAG_MODE_LSB 5 |
| 3066 | #define RST_BOOTSTRAP_EJTAG_MODE_MASK 0x00000020 |
| 3067 | #define RST_BOOTSTRAP_EJTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_EJTAG_MODE_MASK) >> RST_BOOTSTRAP_EJTAG_MODE_LSB) |
| 3068 | #define RST_BOOTSTRAP_EJTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_EJTAG_MODE_LSB) & RST_BOOTSTRAP_EJTAG_MODE_MASK) |
| 3069 | #define RST_BOOTSTRAP_EJTAG_MODE_RESET 0x0 // 0 |
| 3070 | #define RST_BOOTSTRAP_REF_CLK_MSB 4 |
| 3071 | #define RST_BOOTSTRAP_REF_CLK_LSB 4 |
| 3072 | #define RST_BOOTSTRAP_REF_CLK_MASK 0x00000010 |
| 3073 | #define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB) |
| 3074 | #define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK) |
| 3075 | #define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0 |
| 3076 | #define RST_BOOTSTRAP_RES1_MSB 3 |
| 3077 | #define RST_BOOTSTRAP_RES1_LSB 3 |
| 3078 | #define RST_BOOTSTRAP_RES1_MASK 0x00000008 |
| 3079 | #define RST_BOOTSTRAP_RES1_GET(x) (((x) & RST_BOOTSTRAP_RES1_MASK) >> RST_BOOTSTRAP_RES1_LSB) |
| 3080 | #define RST_BOOTSTRAP_RES1_SET(x) (((x) << RST_BOOTSTRAP_RES1_LSB) & RST_BOOTSTRAP_RES1_MASK) |
| 3081 | #define RST_BOOTSTRAP_RES1_RESET 0x0 // 0 |
| 3082 | #define RST_BOOTSTRAP_RES0_MSB 2 |
| 3083 | #define RST_BOOTSTRAP_RES0_LSB 2 |
| 3084 | #define RST_BOOTSTRAP_RES0_MASK 0x00000004 |
| 3085 | #define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB) |
| 3086 | #define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK) |
| 3087 | #define RST_BOOTSTRAP_RES0_RESET 0x0 // 0 |
| 3088 | #define RST_BOOTSTRAP_SDRAM_SELECT_MSB 1 |
| 3089 | #define RST_BOOTSTRAP_SDRAM_SELECT_LSB 1 |
| 3090 | #define RST_BOOTSTRAP_SDRAM_SELECT_MASK 0x00000002 |
| 3091 | #define RST_BOOTSTRAP_SDRAM_SELECT_GET(x) (((x) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) >> RST_BOOTSTRAP_SDRAM_SELECT_LSB) |
| 3092 | #define RST_BOOTSTRAP_SDRAM_SELECT_SET(x) (((x) << RST_BOOTSTRAP_SDRAM_SELECT_LSB) & RST_BOOTSTRAP_SDRAM_SELECT_MASK) |
| 3093 | #define RST_BOOTSTRAP_SDRAM_SELECT_RESET 0x0 // 0 |
| 3094 | #define RST_BOOTSTRAP_DDR_SELECT_MSB 0 |
| 3095 | #define RST_BOOTSTRAP_DDR_SELECT_LSB 0 |
| 3096 | #define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001 |
| 3097 | #define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB) |
| 3098 | #define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK) |
| 3099 | #define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0 |
| 3100 | #define RST_BOOTSTRAP_ADDRESS 0x180600b0 |
| 3101 | |
| 3102 | #define RST_CLKGAT_EN_SPARE_MSB 31 |
| 3103 | #define RST_CLKGAT_EN_SPARE_LSB 12 |
| 3104 | #define RST_CLKGAT_EN_SPARE_MASK 0xfffff000 |
| 3105 | #define RST_CLKGAT_EN_SPARE_GET(x) (((x) & RST_CLKGAT_EN_SPARE_MASK) >> RST_CLKGAT_EN_SPARE_LSB) |
| 3106 | #define RST_CLKGAT_EN_SPARE_SET(x) (((x) << RST_CLKGAT_EN_SPARE_LSB) & RST_CLKGAT_EN_SPARE_MASK) |
| 3107 | #define RST_CLKGAT_EN_SPARE_RESET 0x0 // 0 |
| 3108 | #define RST_CLKGAT_EN_WMAC_MSB 9 |
| 3109 | #define RST_CLKGAT_EN_WMAC_LSB 9 |
| 3110 | #define RST_CLKGAT_EN_WMAC_MASK 0x00000200 |
| 3111 | #define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB) |
| 3112 | #define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK) |
| 3113 | #define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1 |
| 3114 | #define RST_CLKGAT_EN_USB1_MSB 7 |
| 3115 | #define RST_CLKGAT_EN_USB1_LSB 7 |
| 3116 | #define RST_CLKGAT_EN_USB1_MASK 0x00000080 |
| 3117 | #define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB) |
| 3118 | #define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK) |
| 3119 | #define RST_CLKGAT_EN_USB1_RESET 0x1 // 1 |
| 3120 | #define RST_CLKGAT_EN_GE1_MSB 6 |
| 3121 | #define RST_CLKGAT_EN_GE1_LSB 6 |
| 3122 | #define RST_CLKGAT_EN_GE1_MASK 0x00000040 |
| 3123 | #define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB) |
| 3124 | #define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK) |
| 3125 | #define RST_CLKGAT_EN_GE1_RESET 0x1 // 1 |
| 3126 | #define RST_CLKGAT_EN_GE0_MSB 5 |
| 3127 | #define RST_CLKGAT_EN_GE0_LSB 5 |
| 3128 | #define RST_CLKGAT_EN_GE0_MASK 0x00000020 |
| 3129 | #define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB) |
| 3130 | #define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK) |
| 3131 | #define RST_CLKGAT_EN_GE0_RESET 0x1 // 1 |
| 3132 | #define RST_CLKGAT_EN_PCIE_RC_MSB 1 |
| 3133 | #define RST_CLKGAT_EN_PCIE_RC_LSB 1 |
| 3134 | #define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002 |
| 3135 | #define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB) |
| 3136 | #define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK) |
| 3137 | #define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1 |
| 3138 | #define RST_CLKGAT_EN_ADDRESS 0x180600c0 |
| 3139 | #define RST_CLKGAT_EN_OFFSET 0x00c0 |
| 3140 | // SW modifiable bits |
| 3141 | #define RST_CLKGAT_EN_SW_MASK 0xfffff2e2 |
| 3142 | // bits defined at reset |
| 3143 | #define RST_CLKGAT_EN_RSTMASK 0xffffffff |
| 3144 | // reset value (ignore bits undefined at reset) |
| 3145 | #define RST_CLKGAT_EN_RESET 0x000002e2 |
| 3146 | |
| 3147 | #define GPIO_OE_ADDRESS 0x18040000 |
| 3148 | #define GPIO_OUT_ADDRESS 0x18040008 |
| 3149 | #define GPIO_SPARE_ADDRESS 0x18040070 |
| 3150 | |
| 3151 | |
| 3152 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB 31 |
| 3153 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB 24 |
| 3154 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK 0xff000000 |
| 3155 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) |
| 3156 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) |
| 3157 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET 0x0 // 0 |
| 3158 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB 23 |
| 3159 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB 16 |
| 3160 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK 0x00ff0000 |
| 3161 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) |
| 3162 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) |
| 3163 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET 0x0 // 0 |
| 3164 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB 15 |
| 3165 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB 8 |
| 3166 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK 0x0000ff00 |
| 3167 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) |
| 3168 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) |
| 3169 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET 0x0 // 0 |
| 3170 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB 7 |
| 3171 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB 0 |
| 3172 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK 0x000000ff |
| 3173 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) |
| 3174 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) |
| 3175 | #define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET 0x0 // 0 |
| 3176 | #define GPIO_OUT_FUNCTION0_ADDRESS 0x1804002c |
| 3177 | |
| 3178 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31 |
| 3179 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24 |
| 3180 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000 |
| 3181 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) |
| 3182 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) |
| 3183 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xc // 12 |
| 3184 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23 |
| 3185 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16 |
| 3186 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000 |
| 3187 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) |
| 3188 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) |
| 3189 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0x8 // 8 |
| 3190 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15 |
| 3191 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8 |
| 3192 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00 |
| 3193 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) |
| 3194 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) |
| 3195 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9 |
| 3196 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7 |
| 3197 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0 |
| 3198 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff |
| 3199 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) |
| 3200 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) |
| 3201 | #define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x5d // 93 |
| 3202 | #define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030 |
| 3203 | |
| 3204 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31 |
| 3205 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24 |
| 3206 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000 |
| 3207 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) |
| 3208 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) |
| 3209 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0 |
| 3210 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23 |
| 3211 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16 |
| 3212 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000 |
| 3213 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) |
| 3214 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) |
| 3215 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0 |
| 3216 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15 |
| 3217 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8 |
| 3218 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00 |
| 3219 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) |
| 3220 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) |
| 3221 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0 |
| 3222 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7 |
| 3223 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0 |
| 3224 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff |
| 3225 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) |
| 3226 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) |
| 3227 | #define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0 |
| 3228 | #define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034 |
| 3229 | |
| 3230 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31 |
| 3231 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24 |
| 3232 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000 |
| 3233 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) |
| 3234 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) |
| 3235 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0 |
| 3236 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23 |
| 3237 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16 |
| 3238 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000 |
| 3239 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) |
| 3240 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) |
| 3241 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0 |
| 3242 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15 |
| 3243 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8 |
| 3244 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00 |
| 3245 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) |
| 3246 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) |
| 3247 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0 |
| 3248 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7 |
| 3249 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0 |
| 3250 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff |
| 3251 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) |
| 3252 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) |
| 3253 | #define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0 |
| 3254 | #define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038 |
| 3255 | |
| 3256 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15 |
| 3257 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8 |
| 3258 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00 |
| 3259 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) |
| 3260 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) |
| 3261 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x1 // 1 |
| 3262 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7 |
| 3263 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0 |
| 3264 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff |
| 3265 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) |
| 3266 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) |
| 3267 | #define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0 |
| 3268 | #define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c |
| 3269 | |
| 3270 | #define GPIO_IN_ENABLE0_UART_SIN_MSB 15 |
| 3271 | #define GPIO_IN_ENABLE0_UART_SIN_LSB 8 |
| 3272 | #define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00 |
| 3273 | #define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB) |
| 3274 | #define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK) |
| 3275 | #define GPIO_IN_ENABLE0_UART_SIN_RESET 0x80 // 128 |
| 3276 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB 7 |
| 3277 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB 0 |
| 3278 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK 0x000000ff |
| 3279 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x) (((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) |
| 3280 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x) (((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) |
| 3281 | #define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET 0x8 // 8 |
| 3282 | #define GPIO_IN_ENABLE0_ADDRESS 0x18040044 |
| 3283 | |
| 3284 | #define GPIO_IN_ENABLE1_RES_MSB 31 |
| 3285 | #define GPIO_IN_ENABLE1_RES_LSB 0 |
| 3286 | #define GPIO_IN_ENABLE1_RES_MASK 0xffffffff |
| 3287 | #define GPIO_IN_ENABLE1_RES_GET(x) (((x) & GPIO_IN_ENABLE1_RES_MASK) >> GPIO_IN_ENABLE1_RES_LSB) |
| 3288 | #define GPIO_IN_ENABLE1_RES_SET(x) (((x) << GPIO_IN_ENABLE1_RES_LSB) & GPIO_IN_ENABLE1_RES_MASK) |
| 3289 | #define GPIO_IN_ENABLE1_RES_RESET 0x0 // 0 |
| 3290 | #define GPIO_IN_ENABLE1_ADDRESS 0x18040048 |
| 3291 | |
| 3292 | #define GPIO_IN_ENABLE2_RES_MSB 31 |
| 3293 | #define GPIO_IN_ENABLE2_RES_LSB 0 |
| 3294 | #define GPIO_IN_ENABLE2_RES_MASK 0xffffffff |
| 3295 | #define GPIO_IN_ENABLE2_RES_GET(x) (((x) & GPIO_IN_ENABLE2_RES_MASK) >> GPIO_IN_ENABLE2_RES_LSB) |
| 3296 | #define GPIO_IN_ENABLE2_RES_SET(x) (((x) << GPIO_IN_ENABLE2_RES_LSB) & GPIO_IN_ENABLE2_RES_MASK) |
| 3297 | #define GPIO_IN_ENABLE2_RES_RESET 0x0 // 0 |
| 3298 | #define GPIO_IN_ENABLE2_ADDRESS 0x1804004c |
| 3299 | |
| 3300 | #define GPIO_IN_ENABLE3_RES_MSB 31 |
| 3301 | #define GPIO_IN_ENABLE3_RES_LSB 0 |
| 3302 | #define GPIO_IN_ENABLE3_RES_MASK 0xffffffff |
| 3303 | #define GPIO_IN_ENABLE3_RES_GET(x) (((x) & GPIO_IN_ENABLE3_RES_MASK) >> GPIO_IN_ENABLE3_RES_LSB) |
| 3304 | #define GPIO_IN_ENABLE3_RES_SET(x) (((x) << GPIO_IN_ENABLE3_RES_LSB) & GPIO_IN_ENABLE3_RES_MASK) |
| 3305 | #define GPIO_IN_ENABLE3_RES_RESET 0x0 // 0 |
| 3306 | #define GPIO_IN_ENABLE3_ADDRESS 0x18040050 |
| 3307 | |
| 3308 | #define GPIO_IN_ENABLE4_RES_MSB 31 |
| 3309 | #define GPIO_IN_ENABLE4_RES_LSB 0 |
| 3310 | #define GPIO_IN_ENABLE4_RES_MASK 0xffffffff |
| 3311 | #define GPIO_IN_ENABLE4_RES_GET(x) (((x) & GPIO_IN_ENABLE4_RES_MASK) >> GPIO_IN_ENABLE4_RES_LSB) |
| 3312 | #define GPIO_IN_ENABLE4_RES_SET(x) (((x) << GPIO_IN_ENABLE4_RES_LSB) & GPIO_IN_ENABLE4_RES_MASK) |
| 3313 | #define GPIO_IN_ENABLE4_RES_RESET 0x0 // 0 |
| 3314 | #define GPIO_IN_ENABLE4_ADDRESS 0x18040054 |
| 3315 | |
| 3316 | #define GPIO_IN_ENABLE5_WMAC_IN3_MSB 31 |
| 3317 | #define GPIO_IN_ENABLE5_WMAC_IN3_LSB 24 |
| 3318 | #define GPIO_IN_ENABLE5_WMAC_IN3_MASK 0xff000000 |
| 3319 | #define GPIO_IN_ENABLE5_WMAC_IN3_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) >> GPIO_IN_ENABLE5_WMAC_IN3_LSB) |
| 3320 | #define GPIO_IN_ENABLE5_WMAC_IN3_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN3_LSB) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) |
| 3321 | #define GPIO_IN_ENABLE5_WMAC_IN3_RESET 0x80 // 128 |
| 3322 | #define GPIO_IN_ENABLE5_WMAC_IN2_MSB 23 |
| 3323 | #define GPIO_IN_ENABLE5_WMAC_IN2_LSB 16 |
| 3324 | #define GPIO_IN_ENABLE5_WMAC_IN2_MASK 0x00ff0000 |
| 3325 | #define GPIO_IN_ENABLE5_WMAC_IN2_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) >> GPIO_IN_ENABLE5_WMAC_IN2_LSB) |
| 3326 | #define GPIO_IN_ENABLE5_WMAC_IN2_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN2_LSB) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) |
| 3327 | #define GPIO_IN_ENABLE5_WMAC_IN2_RESET 0x80 // 128 |
| 3328 | #define GPIO_IN_ENABLE5_WMAC_IN1_MSB 15 |
| 3329 | #define GPIO_IN_ENABLE5_WMAC_IN1_LSB 8 |
| 3330 | #define GPIO_IN_ENABLE5_WMAC_IN1_MASK 0x0000ff00 |
| 3331 | #define GPIO_IN_ENABLE5_WMAC_IN1_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) >> GPIO_IN_ENABLE5_WMAC_IN1_LSB) |
| 3332 | #define GPIO_IN_ENABLE5_WMAC_IN1_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN1_LSB) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) |
| 3333 | #define GPIO_IN_ENABLE5_WMAC_IN1_RESET 0x80 // 128 |
| 3334 | #define GPIO_IN_ENABLE5_WMAC_IN0_MSB 7 |
| 3335 | #define GPIO_IN_ENABLE5_WMAC_IN0_LSB 0 |
| 3336 | #define GPIO_IN_ENABLE5_WMAC_IN0_MASK 0x000000ff |
| 3337 | #define GPIO_IN_ENABLE5_WMAC_IN0_GET(x) (((x) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) >> GPIO_IN_ENABLE5_WMAC_IN0_LSB) |
| 3338 | #define GPIO_IN_ENABLE5_WMAC_IN0_SET(x) (((x) << GPIO_IN_ENABLE5_WMAC_IN0_LSB) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) |
| 3339 | #define GPIO_IN_ENABLE5_WMAC_IN0_RESET 0x80 // 128 |
| 3340 | #define GPIO_IN_ENABLE5_ADDRESS 0x18040058 |
| 3341 | |
| 3342 | #define GPIO_IN_ENABLE6_WMAC_IN7_MSB 31 |
| 3343 | #define GPIO_IN_ENABLE6_WMAC_IN7_LSB 24 |
| 3344 | #define GPIO_IN_ENABLE6_WMAC_IN7_MASK 0xff000000 |
| 3345 | #define GPIO_IN_ENABLE6_WMAC_IN7_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) >> GPIO_IN_ENABLE6_WMAC_IN7_LSB) |
| 3346 | #define GPIO_IN_ENABLE6_WMAC_IN7_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN7_LSB) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) |
| 3347 | #define GPIO_IN_ENABLE6_WMAC_IN7_RESET 0x80 // 128 |
| 3348 | #define GPIO_IN_ENABLE6_WMAC_IN6_MSB 23 |
| 3349 | #define GPIO_IN_ENABLE6_WMAC_IN6_LSB 16 |
| 3350 | #define GPIO_IN_ENABLE6_WMAC_IN6_MASK 0x00ff0000 |
| 3351 | #define GPIO_IN_ENABLE6_WMAC_IN6_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) >> GPIO_IN_ENABLE6_WMAC_IN6_LSB) |
| 3352 | #define GPIO_IN_ENABLE6_WMAC_IN6_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN6_LSB) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) |
| 3353 | #define GPIO_IN_ENABLE6_WMAC_IN6_RESET 0x80 // 128 |
| 3354 | #define GPIO_IN_ENABLE6_WMAC_IN5_MSB 15 |
| 3355 | #define GPIO_IN_ENABLE6_WMAC_IN5_LSB 8 |
| 3356 | #define GPIO_IN_ENABLE6_WMAC_IN5_MASK 0x0000ff00 |
| 3357 | #define GPIO_IN_ENABLE6_WMAC_IN5_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) >> GPIO_IN_ENABLE6_WMAC_IN5_LSB) |
| 3358 | #define GPIO_IN_ENABLE6_WMAC_IN5_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN5_LSB) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) |
| 3359 | #define GPIO_IN_ENABLE6_WMAC_IN5_RESET 0x80 // 128 |
| 3360 | #define GPIO_IN_ENABLE6_WMAC_IN4_MSB 7 |
| 3361 | #define GPIO_IN_ENABLE6_WMAC_IN4_LSB 0 |
| 3362 | #define GPIO_IN_ENABLE6_WMAC_IN4_MASK 0x000000ff |
| 3363 | #define GPIO_IN_ENABLE6_WMAC_IN4_GET(x) (((x) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) >> GPIO_IN_ENABLE6_WMAC_IN4_LSB) |
| 3364 | #define GPIO_IN_ENABLE6_WMAC_IN4_SET(x) (((x) << GPIO_IN_ENABLE6_WMAC_IN4_LSB) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) |
| 3365 | #define GPIO_IN_ENABLE6_WMAC_IN4_RESET 0x80 // 128 |
| 3366 | #define GPIO_IN_ENABLE6_ADDRESS 0x1804005c |
| 3367 | |
| 3368 | #define GPIO_IN_ENABLE7_WMAC_IN11_MSB 31 |
| 3369 | #define GPIO_IN_ENABLE7_WMAC_IN11_LSB 24 |
| 3370 | #define GPIO_IN_ENABLE7_WMAC_IN11_MASK 0xff000000 |
| 3371 | #define GPIO_IN_ENABLE7_WMAC_IN11_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) >> GPIO_IN_ENABLE7_WMAC_IN11_LSB) |
| 3372 | #define GPIO_IN_ENABLE7_WMAC_IN11_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN11_LSB) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) |
| 3373 | #define GPIO_IN_ENABLE7_WMAC_IN11_RESET 0x80 // 128 |
| 3374 | #define GPIO_IN_ENABLE7_WMAC_IN10_MSB 23 |
| 3375 | #define GPIO_IN_ENABLE7_WMAC_IN10_LSB 16 |
| 3376 | #define GPIO_IN_ENABLE7_WMAC_IN10_MASK 0x00ff0000 |
| 3377 | #define GPIO_IN_ENABLE7_WMAC_IN10_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) >> GPIO_IN_ENABLE7_WMAC_IN10_LSB) |
| 3378 | #define GPIO_IN_ENABLE7_WMAC_IN10_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN10_LSB) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) |
| 3379 | #define GPIO_IN_ENABLE7_WMAC_IN10_RESET 0x80 // 128 |
| 3380 | #define GPIO_IN_ENABLE7_WMAC_IN9_MSB 15 |
| 3381 | #define GPIO_IN_ENABLE7_WMAC_IN9_LSB 8 |
| 3382 | #define GPIO_IN_ENABLE7_WMAC_IN9_MASK 0x0000ff00 |
| 3383 | #define GPIO_IN_ENABLE7_WMAC_IN9_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) >> GPIO_IN_ENABLE7_WMAC_IN9_LSB) |
| 3384 | #define GPIO_IN_ENABLE7_WMAC_IN9_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN9_LSB) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) |
| 3385 | #define GPIO_IN_ENABLE7_WMAC_IN9_RESET 0x80 // 128 |
| 3386 | #define GPIO_IN_ENABLE7_WMAC_IN8_MSB 7 |
| 3387 | #define GPIO_IN_ENABLE7_WMAC_IN8_LSB 0 |
| 3388 | #define GPIO_IN_ENABLE7_WMAC_IN8_MASK 0x000000ff |
| 3389 | #define GPIO_IN_ENABLE7_WMAC_IN8_GET(x) (((x) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) >> GPIO_IN_ENABLE7_WMAC_IN8_LSB) |
| 3390 | #define GPIO_IN_ENABLE7_WMAC_IN8_SET(x) (((x) << GPIO_IN_ENABLE7_WMAC_IN8_LSB) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) |
| 3391 | #define GPIO_IN_ENABLE7_WMAC_IN8_RESET 0x80 // 128 |
| 3392 | #define GPIO_IN_ENABLE7_ADDRESS 0x18040060 |
| 3393 | |
| 3394 | #define GPIO_IN_ENABLE8_SRIF_SRESET_MSB 31 |
| 3395 | #define GPIO_IN_ENABLE8_SRIF_SRESET_LSB 24 |
| 3396 | #define GPIO_IN_ENABLE8_SRIF_SRESET_MASK 0xff000000 |
| 3397 | #define GPIO_IN_ENABLE8_SRIF_SRESET_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) >> GPIO_IN_ENABLE8_SRIF_SRESET_LSB) |
| 3398 | #define GPIO_IN_ENABLE8_SRIF_SRESET_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SRESET_LSB) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) |
| 3399 | #define GPIO_IN_ENABLE8_SRIF_SRESET_RESET 0x80 // 128 |
| 3400 | #define GPIO_IN_ENABLE8_SRIF_SIN_MSB 23 |
| 3401 | #define GPIO_IN_ENABLE8_SRIF_SIN_LSB 16 |
| 3402 | #define GPIO_IN_ENABLE8_SRIF_SIN_MASK 0x00ff0000 |
| 3403 | #define GPIO_IN_ENABLE8_SRIF_SIN_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) >> GPIO_IN_ENABLE8_SRIF_SIN_LSB) |
| 3404 | #define GPIO_IN_ENABLE8_SRIF_SIN_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SIN_LSB) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) |
| 3405 | #define GPIO_IN_ENABLE8_SRIF_SIN_RESET 0x80 // 128 |
| 3406 | #define GPIO_IN_ENABLE8_SRIF_SOT_MSB 15 |
| 3407 | #define GPIO_IN_ENABLE8_SRIF_SOT_LSB 8 |
| 3408 | #define GPIO_IN_ENABLE8_SRIF_SOT_MASK 0x0000ff00 |
| 3409 | #define GPIO_IN_ENABLE8_SRIF_SOT_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) >> GPIO_IN_ENABLE8_SRIF_SOT_LSB) |
| 3410 | #define GPIO_IN_ENABLE8_SRIF_SOT_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SOT_LSB) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) |
| 3411 | #define GPIO_IN_ENABLE8_SRIF_SOT_RESET 0x80 // 128 |
| 3412 | #define GPIO_IN_ENABLE8_SRIF_SCLK_MSB 7 |
| 3413 | #define GPIO_IN_ENABLE8_SRIF_SCLK_LSB 0 |
| 3414 | #define GPIO_IN_ENABLE8_SRIF_SCLK_MASK 0x000000ff |
| 3415 | #define GPIO_IN_ENABLE8_SRIF_SCLK_GET(x) (((x) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) >> GPIO_IN_ENABLE8_SRIF_SCLK_LSB) |
| 3416 | #define GPIO_IN_ENABLE8_SRIF_SCLK_SET(x) (((x) << GPIO_IN_ENABLE8_SRIF_SCLK_LSB) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) |
| 3417 | #define GPIO_IN_ENABLE8_SRIF_SCLK_RESET 0x80 // 128 |
| 3418 | #define GPIO_IN_ENABLE8_ADDRESS 0x18040064 |
| 3419 | |
| 3420 | #define GPIO_IN_ENABLE9_RES_MSB 31 |
| 3421 | #define GPIO_IN_ENABLE9_RES_LSB 0 |
| 3422 | #define GPIO_IN_ENABLE9_RES_MASK 0xffffffff |
| 3423 | #define GPIO_IN_ENABLE9_RES_GET(x) (((x) & GPIO_IN_ENABLE9_RES_MASK) >> GPIO_IN_ENABLE9_RES_LSB) |
| 3424 | #define GPIO_IN_ENABLE9_RES_SET(x) (((x) << GPIO_IN_ENABLE9_RES_LSB) & GPIO_IN_ENABLE9_RES_MASK) |
| 3425 | #define GPIO_IN_ENABLE9_RES_RESET 0x0 // 0 |
| 3426 | #define GPIO_IN_ENABLE9_ADDRESS 0x18040068 |
| 3427 | |
| 3428 | #define GPIO_FUNCTION_EXT_MDIO_SEL_MSB 11 |
| 3429 | #define GPIO_FUNCTION_EXT_MDIO_SEL_LSB 11 |
| 3430 | #define GPIO_FUNCTION_EXT_MDIO_SEL_MASK 0x00000800 |
| 3431 | #define GPIO_FUNCTION_EXT_MDIO_SEL_GET(x) (((x) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) >> GPIO_FUNCTION_EXT_MDIO_SEL_LSB) |
| 3432 | #define GPIO_FUNCTION_EXT_MDIO_SEL_SET(x) (((x) << GPIO_FUNCTION_EXT_MDIO_SEL_LSB) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) |
| 3433 | #define GPIO_FUNCTION_EXT_MDIO_SEL_RESET 0x0 // 0 |
| 3434 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8 |
| 3435 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8 |
| 3436 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100 |
| 3437 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) |
| 3438 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) |
| 3439 | #define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0 |
| 3440 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7 |
| 3441 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7 |
| 3442 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080 |
| 3443 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) |
| 3444 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) |
| 3445 | #define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x0 // 0 |
| 3446 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6 |
| 3447 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6 |
| 3448 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040 |
| 3449 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) |
| 3450 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) |
| 3451 | #define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0 |
| 3452 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5 |
| 3453 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5 |
| 3454 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020 |
| 3455 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) |
| 3456 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) |
| 3457 | #define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x1 // 1 |
| 3458 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4 |
| 3459 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4 |
| 3460 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010 |
| 3461 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) |
| 3462 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) |
| 3463 | #define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0 |
| 3464 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3 |
| 3465 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3 |
| 3466 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008 |
| 3467 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) |
| 3468 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) |
| 3469 | #define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0 |
| 3470 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2 |
| 3471 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2 |
| 3472 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004 |
| 3473 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) |
| 3474 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) |
| 3475 | #define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0 |
| 3476 | #define GPIO_FUNCTION_DISABLE_JTAG_MSB 1 |
| 3477 | #define GPIO_FUNCTION_DISABLE_JTAG_LSB 1 |
| 3478 | #define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002 |
| 3479 | #define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB) |
| 3480 | #define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK) |
| 3481 | #define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0 |
| 3482 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0 |
| 3483 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0 |
| 3484 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001 |
| 3485 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) |
| 3486 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) |
| 3487 | #define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0 |
| 3488 | #define GPIO_FUNCTION_ADDRESS 0x1804006c |
| 3489 | |
| 3490 | #define PCIE_RESET_EP_RESET_L_MSB 2 |
| 3491 | #define PCIE_RESET_EP_RESET_L_LSB 2 |
| 3492 | #define PCIE_RESET_EP_RESET_L_MASK 0x00000004 |
| 3493 | #define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB) |
| 3494 | #define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK) |
| 3495 | #define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0 |
| 3496 | #define PCIE_RESET_LINK_REQ_RESET_MSB 1 |
| 3497 | #define PCIE_RESET_LINK_REQ_RESET_LSB 1 |
| 3498 | #define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002 |
| 3499 | #define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB) |
| 3500 | #define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK) |
| 3501 | #define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0 |
| 3502 | #define PCIE_RESET_LINK_UP_MSB 0 |
| 3503 | #define PCIE_RESET_LINK_UP_LSB 0 |
| 3504 | #define PCIE_RESET_LINK_UP_MASK 0x00000001 |
| 3505 | #define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB) |
| 3506 | #define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK) |
| 3507 | #define PCIE_RESET_LINK_UP_RESET 0x0 // 0 |
| 3508 | #define PCIE_RESET_ADDRESS 0x180f0018 |
| 3509 | |
| 3510 | #define ETH_CFG_ETH_SPARE_MSB 31 |
| 3511 | #define ETH_CFG_ETH_SPARE_LSB 22 |
| 3512 | #define ETH_CFG_ETH_SPARE_MASK 0xffc00000 |
| 3513 | #define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB) |
| 3514 | #define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK) |
| 3515 | #define ETH_CFG_ETH_SPARE_RESET 0x0 // 0 |
| 3516 | #define ETH_CFG_SW_ACC_MSB_FIRST_MSB 13 |
| 3517 | #define ETH_CFG_SW_ACC_MSB_FIRST_LSB 13 |
| 3518 | #define ETH_CFG_SW_ACC_MSB_FIRST_MASK 0x00002000 |
| 3519 | #define ETH_CFG_SW_ACC_MSB_FIRST_GET(x) (((x) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) >> ETH_CFG_SW_ACC_MSB_FIRST_LSB) |
| 3520 | #define ETH_CFG_SW_ACC_MSB_FIRST_SET(x) (((x) << ETH_CFG_SW_ACC_MSB_FIRST_LSB) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) |
| 3521 | #define ETH_CFG_SW_ACC_MSB_FIRST_RESET 0x1 // 1 |
| 3522 | #define ETH_CFG_SW_APB_ACCESS_MSB 9 |
| 3523 | #define ETH_CFG_SW_APB_ACCESS_LSB 9 |
| 3524 | #define ETH_CFG_SW_APB_ACCESS_MASK 0x00000200 |
| 3525 | #define ETH_CFG_SW_APB_ACCESS_GET(x) (((x) & ETH_CFG_SW_APB_ACCESS_MASK) >> ETH_CFG_SW_APB_ACCESS_LSB) |
| 3526 | #define ETH_CFG_SW_APB_ACCESS_SET(x) (((x) << ETH_CFG_SW_APB_ACCESS_LSB) & ETH_CFG_SW_APB_ACCESS_MASK) |
| 3527 | #define ETH_CFG_SW_APB_ACCESS_RESET 0x0 // 0 |
| 3528 | #define ETH_CFG_SW_PHY_ADDR_SWAP_MSB 8 |
| 3529 | #define ETH_CFG_SW_PHY_ADDR_SWAP_LSB 8 |
| 3530 | #define ETH_CFG_SW_PHY_ADDR_SWAP_MASK 0x00000100 |
| 3531 | #define ETH_CFG_SW_PHY_ADDR_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) >> ETH_CFG_SW_PHY_ADDR_SWAP_LSB) |
| 3532 | #define ETH_CFG_SW_PHY_ADDR_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_ADDR_SWAP_LSB) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) |
| 3533 | #define ETH_CFG_SW_PHY_ADDR_SWAP_RESET 0x0 // 0 |
| 3534 | #define ETH_CFG_SW_PHY_SWAP_MSB 7 |
| 3535 | #define ETH_CFG_SW_PHY_SWAP_LSB 7 |
| 3536 | #define ETH_CFG_SW_PHY_SWAP_MASK 0x00000080 |
| 3537 | #define ETH_CFG_SW_PHY_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_SWAP_MASK) >> ETH_CFG_SW_PHY_SWAP_LSB) |
| 3538 | #define ETH_CFG_SW_PHY_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_SWAP_LSB) & ETH_CFG_SW_PHY_SWAP_MASK) |
| 3539 | #define ETH_CFG_SW_PHY_SWAP_RESET 0x0 // 0 |
| 3540 | #define ETH_CFG_SW_ONLY_MODE_MSB 6 |
| 3541 | #define ETH_CFG_SW_ONLY_MODE_LSB 6 |
| 3542 | #define ETH_CFG_SW_ONLY_MODE_MASK 0x00000040 |
| 3543 | #define ETH_CFG_SW_ONLY_MODE_GET(x) (((x) & ETH_CFG_SW_ONLY_MODE_MASK) >> ETH_CFG_SW_ONLY_MODE_LSB) |
| 3544 | #define ETH_CFG_SW_ONLY_MODE_SET(x) (((x) << ETH_CFG_SW_ONLY_MODE_LSB) & ETH_CFG_SW_ONLY_MODE_MASK) |
| 3545 | #define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0 |
| 3546 | #define ETH_CFG_ADDRESS 0x18070000 |
| 3547 | |
| 3548 | //#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ /* Moved to qca953x defconfig */ |
| 3549 | |
| 3550 | //#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */ /* Moved to qca953x defconfig */ |
| 3551 | |
| 3552 | //#define CONFIG_BAUDRATE 115200 /* Moved to qca953x defconfig */ |
| 3553 | //#define CFG_BAUDRATE_TABLE {115200} /* Moved to qca953x defconfig */ |
| 3554 | |
| 3555 | //#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* Moved to qca953x defconfig */ |
| 3556 | |
| 3557 | #define CONFIG_ROOTFS_RD |
| 3558 | |
| 3559 | #define CONFIG_BOOTARGS_RD "console=ttyS0,115200 root=01:00 rd_start=0x802d0000 rd_size=5242880 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),4096k(rootfs),2048k(uImage)" |
| 3560 | |
| 3561 | /* XXX - putting rootfs in last partition results in jffs errors */ |
| 3562 | #define CONFIG_BOOTARGS_FL "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),2048k(uImage)" |
| 3563 | |
| 3564 | #ifdef CONFIG_ROOTFS_FLASH |
| 3565 | #define CONFIG_BOOTARGS CONFIG_BOOTARGS_FL |
| 3566 | #else |
| 3567 | #define CONFIG_BOOTARGS "" |
| 3568 | #endif |
| 3569 | |
| 3570 | /* |
| 3571 | * Miscellaneous configurable options |
| 3572 | */ |
| 3573 | #define CFG_LONGHELP /* undef to save memory */ |
| 3574 | #define CFG_PROMPT "ath> " /* Monitor Command Prompt */ |
| 3575 | #define CFG_CBSIZE 512 /* Console I/O Buffer Size */ |
| 3576 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 3577 | #define CFG_MAXARGS 16 /* max number of command args*/ |
| 3578 | |
| 3579 | //#define CFG_MALLOC_LEN (128*1024) /* Moved to qca953x defconfig under different name*/ |
| 3580 | |
| 3581 | //#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ /* Moved to qca953x defconfig under different name*/ |
| 3582 | //#define CFG_SDRAM_BASE 0xa0000000 /* Cached addr */ |
| 3583 | |
| 3584 | //#define CFG_LOAD_ADDR 0x81000000 /* default load address */ /* Moved to qca953x defconfig under different name*/ |
| 3585 | //#define CFG_LOAD_ADDR 0xa1000000 /* default load address */ |
| 3586 | |
| 3587 | #define CFG_MEMTEST_START 0x80100000 |
| 3588 | #undef CFG_MEMTEST_START |
| 3589 | #define CFG_MEMTEST_START 0x80200000 |
| 3590 | #define CFG_MEMTEST_END 0x83800000 |
| 3591 | |
| 3592 | /*------------------------------------------------------------------------ |
| 3593 | * * * JFFS2 |
| 3594 | */ |
| 3595 | #define CFG_JFFS_CUSTOM_PART /* board defined part */ |
| 3596 | #define CONFIG_JFFS2_CMDLINE |
| 3597 | #define MTDIDS_DEFAULT "nor0=ath-nor0" |
| 3598 | |
| 3599 | #define CONFIG_MEMSIZE_IN_BYTES |
| 3600 | |
| 3601 | //#define CFG_RX_ETH_BUFFER 16 /* Moved to qca953x defconfig under different name*/ |
| 3602 | |
| 3603 | |
| 3604 | /*----------------------------------------------------------------------- |
| 3605 | * Cache Configuration |
| 3606 | */ |
| 3607 | // #define CFG_DCACHE_SIZE 32768 /* Moved to qca953x defconfig under different name*/ |
| 3608 | // #define CFG_ICACHE_SIZE 65536 /* Moved to qca953x defconfig under different name*/ |
| 3609 | // #define CFG_CACHELINE_SIZE 32 /* Moved to qca953x defconfig under different name*/ |
| 3610 | |
| 3611 | /* |
| 3612 | * Address map |
| 3613 | */ |
| 3614 | #define ATH_PCI_MEM_BASE 0x10000000 /* 128M */ |
| 3615 | #define ATH_APB_BASE 0x18000000 /* 384M */ |
| 3616 | #define ATH_GE0_BASE 0x19000000 /* 16M */ |
| 3617 | #define ATH_GE1_BASE 0x1a000000 /* 16M */ |
| 3618 | #define ATH_USB_OHCI_BASE 0x1b000000 |
| 3619 | #define ATH_USB_EHCI_BASE 0x1b000000 |
| 3620 | #define ATH_USB_EHCI_BASE_1 0x1b000000 |
| 3621 | #define ATH_USB_EHCI_BASE_2 0x1b400000 |
| 3622 | #define ATH_SPI_BASE 0x1f000000 |
| 3623 | |
| 3624 | /* |
| 3625 | * Added the PCI LCL RESET register from u-boot |
| 3626 | * ath_soc.h so that we can query the PCI LCL RESET |
| 3627 | * register for the presence of WLAN H/W. |
| 3628 | */ |
| 3629 | #define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x000f0000) |
| 3630 | #define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00) |
| 3631 | #define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18) |
| 3632 | |
| 3633 | /* |
| 3634 | * APB block |
| 3635 | */ |
| 3636 | #define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000 |
| 3637 | #define ATH_CPU_BASE ATH_APB_BASE+0x00010000 |
| 3638 | #define ATH_UART_BASE ATH_APB_BASE+0x00020000 |
| 3639 | #define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000 |
| 3640 | #define ATH_GPIO_BASE ATH_APB_BASE+0x00040000 |
| 3641 | #define ATH_PLL_BASE ATH_APB_BASE+0x00050000 |
| 3642 | #define ATH_RESET_BASE ATH_APB_BASE+0x00060000 |
| 3643 | #define ATH_DMA_BASE ATH_APB_BASE+0x000A0000 |
| 3644 | #define ATH_SLIC_BASE ATH_APB_BASE+0x000A9000 |
| 3645 | #define ATH_STEREO_BASE ATH_APB_BASE+0x000B0000 |
| 3646 | #define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x000F0000 |
| 3647 | #define ATH_OTP_BASE ATH_APB_BASE+0x00130000 |
| 3648 | #define ATH_NAND_FLASH_BASE 0x1b800000u |
| 3649 | #define ATH_GPIO_OE ATH_GPIO_BASE+0x0 |
| 3650 | |
| 3651 | |
| 3652 | /* |
| 3653 | * DDR Config values |
| 3654 | */ |
| 3655 | #define ATH_DDR_CONFIG_16BIT (1 << 31) |
| 3656 | #define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30) |
| 3657 | #define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27 |
| 3658 | #define ATH_DDR_CONFIG_TMRD_SHIFT 23 |
| 3659 | #define ATH_DDR_CONFIG_TRFC_SHIFT 17 |
| 3660 | #define ATH_DDR_CONFIG_TRRD_SHIFT 13 |
| 3661 | #define ATH_DDR_CONFIG_TRP_SHIFT 9 |
| 3662 | #define ATH_DDR_CONFIG_TRCD_SHIFT 5 |
| 3663 | #define ATH_DDR_CONFIG_TRAS_SHIFT 0 |
| 3664 | |
| 3665 | #define ATH_DDR_CONFIG2_BL2 (2 << 0) |
| 3666 | #define ATH_DDR_CONFIG2_BL4 (4 << 0) |
| 3667 | #define ATH_DDR_CONFIG2_BL8 (8 << 0) |
| 3668 | |
| 3669 | #define ATH_DDR_CONFIG2_BT_IL (1 << 4) |
| 3670 | #define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5) |
| 3671 | #define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6) |
| 3672 | #define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7) |
| 3673 | #define ATH_DDR_CONFIG2_TWR_SHIFT 8 |
| 3674 | #define ATH_DDR_CONFIG2_TRTW_SHIFT 12 |
| 3675 | #define ATH_DDR_CONFIG2_TRTP_SHIFT 17 |
| 3676 | #define ATH_DDR_CONFIG2_TWTR_SHIFT 21 |
| 3677 | #define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31) |
| 3678 | |
| 3679 | #define ATH_DDR_TAP_DEFAULT 0x18 |
| 3680 | |
| 3681 | /* |
| 3682 | * DDR block, gmac flushing |
| 3683 | */ |
| 3684 | #define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c |
| 3685 | #define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0 |
| 3686 | #define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4 |
| 3687 | #define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0x88 |
| 3688 | |
| 3689 | #define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000 |
| 3690 | #define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006 |
| 3691 | |
| 3692 | /* |
| 3693 | * PLL block/CPU |
| 3694 | */ |
| 3695 | |
| 3696 | #define ATH_PLL_CONFIG ATH_PLL_BASE+0x0 |
| 3697 | #define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x8 |
| 3698 | |
| 3699 | |
| 3700 | #define PLL_DIV_SHIFT 0 |
| 3701 | #define PLL_DIV_MASK 0x3ff |
| 3702 | #define REF_DIV_SHIFT 10 |
| 3703 | #define REF_DIV_MASK 0xf |
| 3704 | #define AHB_DIV_SHIFT 19 |
| 3705 | #define AHB_DIV_MASK 0x1 |
| 3706 | #define DDR_DIV_SHIFT 22 |
| 3707 | #define DDR_DIV_MASK 0x1 |
| 3708 | #define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x4 |
| 3709 | #define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x2c |
| 3710 | #define ATH_AUDIO_PLL_CONFIG ATH_PLL_BASE+0x30 |
| 3711 | |
| 3712 | #define ATH_ETH_INT0_CLK ATH_PLL_BASE+0x14 |
| 3713 | #define ATH_ETH_INT1_CLK ATH_PLL_BASE+0x18 |
| 3714 | |
| 3715 | |
| 3716 | /* |
| 3717 | * USB block |
| 3718 | */ |
| 3719 | #define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE |
| 3720 | #define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4 |
| 3721 | #define ATH_USB_WINDOW 0x10000 |
| 3722 | #define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8 |
| 3723 | |
| 3724 | /* |
| 3725 | * PCI block |
| 3726 | */ |
| 3727 | #define ATH_PCI_WINDOW 0x8000000 /* 128MB */ |
| 3728 | #define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c |
| 3729 | #define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80 |
| 3730 | #define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84 |
| 3731 | #define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88 |
| 3732 | #define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c |
| 3733 | #define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90 |
| 3734 | #define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94 |
| 3735 | #define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98 |
| 3736 | |
| 3737 | #define ATH_PCI_WINDOW0_VAL 0x10000000 |
| 3738 | #define ATH_PCI_WINDOW1_VAL 0x11000000 |
| 3739 | #define ATH_PCI_WINDOW2_VAL 0x12000000 |
| 3740 | #define ATH_PCI_WINDOW3_VAL 0x13000000 |
| 3741 | #define ATH_PCI_WINDOW4_VAL 0x14000000 |
| 3742 | #define ATH_PCI_WINDOW5_VAL 0x15000000 |
| 3743 | #define ATH_PCI_WINDOW6_VAL 0x16000000 |
| 3744 | #define ATH_PCI_WINDOW7_VAL 0x07000000 |
| 3745 | |
| 3746 | #define ath_write_pci_window(_no) \ |
| 3747 | ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL); |
| 3748 | |
| 3749 | /* |
| 3750 | * CRP. To access the host controller config and status registers |
| 3751 | */ |
| 3752 | #define ATH_PCI_CRP 0x180c0000 |
| 3753 | #define ATH_PCI_DEV_CFGBASE 0x14000000 |
| 3754 | #define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP |
| 3755 | #define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4 |
| 3756 | #define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8 |
| 3757 | #define ATH_PCI_ERROR ATH_PCI_CRP+0x1c |
| 3758 | #define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20 |
| 3759 | #define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24 |
| 3760 | #define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28 |
| 3761 | |
| 3762 | #define ATH_CRP_CMD_WRITE 0x00010000 |
| 3763 | #define ATH_CRP_CMD_READ 0x00000000 |
| 3764 | |
| 3765 | /* |
| 3766 | * PCI CFG. To generate config cycles |
| 3767 | */ |
| 3768 | #define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc |
| 3769 | #define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10 |
| 3770 | #define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14 |
| 3771 | #define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18 |
| 3772 | #define ATH_CFG_CMD_READ 0x0000000a |
| 3773 | #define ATH_CFG_CMD_WRITE 0x0000000b |
| 3774 | |
| 3775 | #define ATH_PCI_IDSEL_ADLINE_START 17 |
| 3776 | |
| 3777 | #define ATH_SPI_FS (ATH_SPI_BASE+0x00) |
| 3778 | #define ATH_SPI_READ (ATH_SPI_BASE+0x00) |
| 3779 | #define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04) |
| 3780 | #define ATH_SPI_WRITE (ATH_SPI_BASE+0x08) |
| 3781 | #define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c) |
| 3782 | #define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10) |
| 3783 | #define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14) |
| 3784 | #define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18) |
| 3785 | #define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */ |
| 3786 | #define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */ |
| 3787 | |
| 3788 | #define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */ |
| 3789 | #define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */ |
| 3790 | #define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */ |
| 3791 | #define ATH_SPI_CS_DIS 0x70000 |
| 3792 | #define ATH_SPI_CE_LOW 0x60000 |
| 3793 | #define ATH_SPI_CE_HIGH 0x60100 |
| 3794 | |
| 3795 | #define ATH_SPI_SECTOR_SIZE (1024*64) |
| 3796 | #define ATH_SPI_PAGE_SIZE 256 |
| 3797 | |
| 3798 | #define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1) |
| 3799 | #define ATH_RESET_GE0_PHY RST_RESET_ETH_SWITCH_RESET_SET(1) |
| 3800 | #define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1) |
| 3801 | #define ATH_RESET_GE1_PHY RST_RESET_ETH_SWITCH_ARESET_SET(1) |
| 3802 | #define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1) |
| 3803 | #define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1) |
| 3804 | |
| 3805 | /* |
| 3806 | * SOC |
| 3807 | */ |
| 3808 | #define ATH_SPI_CMD_WRITE_SR 0x01 |
| 3809 | #define ATH_SPI_CMD_WREN 0x06 |
| 3810 | #define ATH_SPI_CMD_RD_STATUS 0x05 |
| 3811 | #define ATH_SPI_CMD_FAST_READ 0x0b |
| 3812 | #define ATH_SPI_CMD_PAGE_PROG 0x02 |
| 3813 | #define ATH_SPI_CMD_SECTOR_ERASE 0xd8 |
| 3814 | #define ATH_SPI_CMD_CHIP_ERASE 0xc7 |
| 3815 | #define ATH_SPI_CMD_RDID 0x9f |
| 3816 | #define ATH_SPI_CMD_WR_EXT 0xc5 |
| 3817 | #define ATH_SPI_CMD_RD_EXT 0xc8 |
| 3818 | |
| 3819 | #if defined(CFG_ATH_EMULATION) |
| 3820 | |
| 3821 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(2) // 80 MHz |
| 3822 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(1) // 40 MHz |
| 3823 | |
| 3824 | #elif (CFG_PLL_FREQ == CFG_PLL_550_400_200) |
| 3825 | |
| 3826 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3827 | |
| 3828 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) |
| 3829 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3830 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) |
| 3831 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3832 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3833 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3834 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3835 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3836 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3837 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3838 | |
| 3839 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) |
| 3840 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3841 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) |
| 3842 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3843 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3844 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3845 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 3846 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3847 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3848 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3849 | |
| 3850 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) |
| 3851 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 3852 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 3853 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 3854 | |
| 3855 | #elif (CFG_PLL_FREQ == CFG_PLL_720_600_200) |
| 3856 | |
| 3857 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3858 | |
| 3859 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) |
| 3860 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3861 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 3862 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3863 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3864 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3865 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3866 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3867 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3868 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3869 | |
| 3870 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) |
| 3871 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3872 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 3873 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3874 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3875 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3876 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 3877 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3878 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3879 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3880 | |
| 3881 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 3882 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 3883 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 3884 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 3885 | |
| 3886 | #elif (CFG_PLL_FREQ == CFG_PLL_720_600_300) |
| 3887 | |
| 3888 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3889 | |
| 3890 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) |
| 3891 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3892 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 3893 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3894 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3895 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3896 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3897 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3898 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3899 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3900 | |
| 3901 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) |
| 3902 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3903 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 3904 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3905 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3906 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3907 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 3908 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3909 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3910 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3911 | |
| 3912 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) |
| 3913 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 3914 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 3915 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 3916 | |
| 3917 | #elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) |
| 3918 | |
| 3919 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3920 | |
| 3921 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(16) |
| 3922 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3923 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 3924 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3925 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3926 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3927 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3928 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3929 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3930 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3931 | |
| 3932 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(16) |
| 3933 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3934 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 3935 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3936 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3937 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3938 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 3939 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3940 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3941 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3942 | |
| 3943 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) |
| 3944 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 3945 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 3946 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 3947 | |
| 3948 | #elif (CFG_PLL_FREQ == CFG_PLL_720_680_240) |
| 3949 | |
| 3950 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3951 | |
| 3952 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) |
| 3953 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3954 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 3955 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3956 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3957 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3958 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3959 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3960 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3961 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3962 | |
| 3963 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) |
| 3964 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3965 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 3966 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3967 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3968 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3969 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 3970 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3971 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3972 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3973 | |
| 3974 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 3975 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) |
| 3976 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 3977 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 3978 | |
| 3979 | #elif (CFG_PLL_FREQ == CFG_PLL_720_600_240) |
| 3980 | |
| 3981 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 3982 | |
| 3983 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(18) |
| 3984 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 3985 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 3986 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3987 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 3988 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 3989 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 3990 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 3991 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 3992 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 3993 | |
| 3994 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(15) |
| 3995 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 3996 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 3997 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3998 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 3999 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4000 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 4001 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4002 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4003 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4004 | |
| 4005 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4006 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) |
| 4007 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4008 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4009 | |
| 4010 | #elif (CFG_PLL_FREQ == CFG_PLL_560_450_220) |
| 4011 | |
| 4012 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 4013 | |
| 4014 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(14) |
| 4015 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4016 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 4017 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4018 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4019 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4020 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4021 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4022 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4023 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4024 | |
| 4025 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(11) |
| 4026 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4027 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 4028 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4029 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4030 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4031 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 4032 | DDR_PLL_DITHER_NFRAC_MIN_SET(0x100) | \ |
| 4033 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4034 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4035 | |
| 4036 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(1) |
| 4037 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 4038 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4039 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4040 | |
| 4041 | #elif (CFG_PLL_FREQ == CFG_PLL_680_680_226) |
| 4042 | |
| 4043 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) |
| 4044 | |
| 4045 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(17) |
| 4046 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4047 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(1) |
| 4048 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4049 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4050 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4051 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4052 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4053 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4054 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4055 | |
| 4056 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(17) |
| 4057 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4058 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(1) |
| 4059 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4060 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4061 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4062 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 4063 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4064 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4065 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4066 | |
| 4067 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4068 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 4069 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4070 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4071 | |
| 4072 | #elif (CFG_PLL_FREQ == CFG_PLL_550_600_200) |
| 4073 | |
| 4074 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 4075 | |
| 4076 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(22) |
| 4077 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4078 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) |
| 4079 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4080 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4081 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4082 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4083 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4084 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4085 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4086 | |
| 4087 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) |
| 4088 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4089 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) |
| 4090 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4091 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4092 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4093 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 4094 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4095 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4096 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4097 | |
| 4098 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4099 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 4100 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4101 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4102 | |
| 4103 | #elif (CFG_PLL_FREQ == CFG_PLL_600_600_200) |
| 4104 | |
| 4105 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(1) |
| 4106 | |
| 4107 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(24) |
| 4108 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4109 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) |
| 4110 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4111 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4112 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4113 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4114 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4115 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4116 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4117 | |
| 4118 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(24) |
| 4119 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4120 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) |
| 4121 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4122 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4123 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4124 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ff) | \ |
| 4125 | DDR_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4126 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4127 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4128 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4129 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4130 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4131 | |
| 4132 | #elif (CFG_PLL_FREQ == CFG_PLL_650_400_200) |
| 4133 | |
| 4134 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 4135 | |
| 4136 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) |
| 4137 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4138 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) |
| 4139 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4140 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4141 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4142 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4143 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4144 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4145 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4146 | |
| 4147 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0xf) |
| 4148 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4149 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) |
| 4150 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4151 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4152 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ |
| 4153 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x2FB) | \ |
| 4154 | DDR_PLL_DITHER_NFRAC_MIN_SET(0x27B) | \ |
| 4155 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4156 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4157 | |
| 4158 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4159 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) |
| 4160 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4161 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4162 | |
| 4163 | |
| 4164 | #elif (CFG_PLL_FREQ == CFG_PLL_650_600_200) |
| 4165 | #define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0) |
| 4166 | |
| 4167 | #define CPU_PLL_CONFIG_NINT_VAL CPU_PLL_CONFIG_NINT_SET(26) |
| 4168 | #define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(1) |
| 4169 | #define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0) |
| 4170 | #define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4171 | #define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0) |
| 4172 | #define CPU_PLL_DITHER_VAL CPU_PLL_DITHER_DITHER_EN_SET(0) | \ |
| 4173 | CPU_PLL_DITHER_NFRAC_MAX_SET(0x3f) | \ |
| 4174 | CPU_PLL_DITHER_NFRAC_MIN_SET(0) | \ |
| 4175 | CPU_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4176 | CPU_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4177 | |
| 4178 | #define DDR_PLL_CONFIG_NINT_VAL DDR_PLL_CONFIG_NINT_SET(0x17) |
| 4179 | #define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(1) |
| 4180 | #define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0) |
| 4181 | #define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4182 | #define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0) |
| 4183 | #define DDR_PLL_DITHER_VAL DDR_PLL_DITHER_DITHER_EN_SET(1) | \ |
| 4184 | DDR_PLL_DITHER_NFRAC_MAX_SET(0x3ae) | \ |
| 4185 | DDR_PLL_DITHER_NFRAC_MIN_SET(0x385) | \ |
| 4186 | DDR_PLL_DITHER_NFRAC_STEP_SET(1) | \ |
| 4187 | DDR_PLL_DITHER_UPDATE_COUNT_SET(0xf) |
| 4188 | |
| 4189 | #define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(2) |
| 4190 | #define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) |
| 4191 | #define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0) |
| 4192 | #define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0) |
| 4193 | #else |
| 4194 | # error "CFG_PLL_FREQ not set" |
| 4195 | #endif // CFG_PLL_FREQ |
| 4196 | |
| 4197 | #define CPU_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(0) |
| 4198 | #define CPU_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_CPUCLK_FROM_CPUPLL_SET(1) |
| 4199 | |
| 4200 | #define DDR_CLK_FROM_DDR_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(1) |
| 4201 | #define DDR_CLK_FROM_CPU_PLL CPU_DDR_CLOCK_CONTROL_DDRCLK_FROM_DDRPLL_SET(0) |
| 4202 | |
| 4203 | #if CPU_DDR_SYNC_MODE |
| 4204 | |
| 4205 | # define both_from_cpu 0 |
| 4206 | # define both_from_ddr 1 |
| 4207 | |
| 4208 | # if both_from_ddr |
| 4209 | # define CLK_SRC_CONTROL (CPU_CLK_FROM_DDR_PLL | DDR_CLK_FROM_DDR_PLL) |
| 4210 | # define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(1) |
| 4211 | # elif both_from_cpu |
| 4212 | # define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_CPU_PLL) |
| 4213 | # define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0) |
| 4214 | # else |
| 4215 | # error "Invalid sync mode settings" |
| 4216 | # endif |
| 4217 | #else |
| 4218 | # define CLK_SRC_CONTROL (CPU_CLK_FROM_CPU_PLL | DDR_CLK_FROM_DDR_PLL) |
| 4219 | #endif |
| 4220 | |
| 4221 | |
| 4222 | |
| 4223 | #define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000) |
| 4224 | #define __cpu_hz_40(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 40)) |
| 4225 | #define __cpu_hz_25(pll) (__nint_to_mhz(CPU_PLL_CONFIG_NINT_GET(pll), 25)) |
| 4226 | |
| 4227 | /* Since the count is incremented every other tick, divide by 2 */ |
| 4228 | #define CFG_HZ (__cpu_hz_25(CPU_PLL_CONFIG_NINT_VAL) / 2) |
| 4229 | |
| 4230 | /* SGMII DEFINES */ |
| 4231 | |
| 4232 | // 32'h18070034 (SGMII_CONFIG) |
| 4233 | #define SGMII_CONFIG_BERT_ENABLE_MSB 14 |
| 4234 | #define SGMII_CONFIG_BERT_ENABLE_LSB 14 |
| 4235 | #define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000 |
| 4236 | #define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB) |
| 4237 | #define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK) |
| 4238 | #define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0 |
| 4239 | #define SGMII_CONFIG_PRBS_ENABLE_MSB 13 |
| 4240 | #define SGMII_CONFIG_PRBS_ENABLE_LSB 13 |
| 4241 | #define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000 |
| 4242 | #define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB) |
| 4243 | #define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK) |
| 4244 | #define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0 |
| 4245 | #define SGMII_CONFIG_MDIO_COMPLETE_MSB 12 |
| 4246 | #define SGMII_CONFIG_MDIO_COMPLETE_LSB 12 |
| 4247 | #define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000 |
| 4248 | #define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB) |
| 4249 | #define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK) |
| 4250 | #define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0 |
| 4251 | #define SGMII_CONFIG_MDIO_PULSE_MSB 11 |
| 4252 | #define SGMII_CONFIG_MDIO_PULSE_LSB 11 |
| 4253 | #define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800 |
| 4254 | #define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB) |
| 4255 | #define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK) |
| 4256 | #define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0 |
| 4257 | #define SGMII_CONFIG_MDIO_ENABLE_MSB 10 |
| 4258 | #define SGMII_CONFIG_MDIO_ENABLE_LSB 10 |
| 4259 | #define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400 |
| 4260 | #define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB) |
| 4261 | #define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK) |
| 4262 | #define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0 |
| 4263 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9 |
| 4264 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9 |
| 4265 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200 |
| 4266 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) |
| 4267 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) |
| 4268 | #define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0 |
| 4269 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8 |
| 4270 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8 |
| 4271 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100 |
| 4272 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) |
| 4273 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) |
| 4274 | #define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0 |
| 4275 | #define SGMII_CONFIG_SPEED_MSB 7 |
| 4276 | #define SGMII_CONFIG_SPEED_LSB 6 |
| 4277 | #define SGMII_CONFIG_SPEED_MASK 0x000000c0 |
| 4278 | #define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB) |
| 4279 | #define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK) |
| 4280 | #define SGMII_CONFIG_SPEED_RESET 0x0 // 0 |
| 4281 | #define SGMII_CONFIG_FORCE_SPEED_MSB 5 |
| 4282 | #define SGMII_CONFIG_FORCE_SPEED_LSB 5 |
| 4283 | #define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020 |
| 4284 | #define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB) |
| 4285 | #define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK) |
| 4286 | #define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0 |
| 4287 | #define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4 |
| 4288 | #define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4 |
| 4289 | #define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010 |
| 4290 | #define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB) |
| 4291 | #define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) |
| 4292 | #define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0 |
| 4293 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3 |
| 4294 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3 |
| 4295 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008 |
| 4296 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) |
| 4297 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) |
| 4298 | #define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0 |
| 4299 | #define SGMII_CONFIG_MODE_CTRL_MSB 2 |
| 4300 | #define SGMII_CONFIG_MODE_CTRL_LSB 0 |
| 4301 | #define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007 |
| 4302 | #define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB) |
| 4303 | #define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK) |
| 4304 | #define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0 |
| 4305 | #define SGMII_CONFIG_ADDRESS 0x18070034 |
| 4306 | |
| 4307 | |
| 4308 | |
| 4309 | // 32'h1807001c (MR_AN_CONTROL) |
| 4310 | #define MR_AN_CONTROL_PHY_RESET_MSB 15 |
| 4311 | #define MR_AN_CONTROL_PHY_RESET_LSB 15 |
| 4312 | #define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000 |
| 4313 | #define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB) |
| 4314 | #define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK) |
| 4315 | #define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0 |
| 4316 | #define MR_AN_CONTROL_LOOPBACK_MSB 14 |
| 4317 | #define MR_AN_CONTROL_LOOPBACK_LSB 14 |
| 4318 | #define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000 |
| 4319 | #define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB) |
| 4320 | #define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK) |
| 4321 | #define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0 |
| 4322 | #define MR_AN_CONTROL_SPEED_SEL0_MSB 13 |
| 4323 | #define MR_AN_CONTROL_SPEED_SEL0_LSB 13 |
| 4324 | #define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000 |
| 4325 | #define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB) |
| 4326 | #define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK) |
| 4327 | #define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0 |
| 4328 | #define MR_AN_CONTROL_AN_ENABLE_MSB 12 |
| 4329 | #define MR_AN_CONTROL_AN_ENABLE_LSB 12 |
| 4330 | #define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000 |
| 4331 | #define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB) |
| 4332 | #define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK) |
| 4333 | #define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1 |
| 4334 | #define MR_AN_CONTROL_POWER_DOWN_MSB 11 |
| 4335 | #define MR_AN_CONTROL_POWER_DOWN_LSB 11 |
| 4336 | #define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800 |
| 4337 | #define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB) |
| 4338 | #define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK) |
| 4339 | #define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0 |
| 4340 | #define MR_AN_CONTROL_RESTART_AN_MSB 9 |
| 4341 | #define MR_AN_CONTROL_RESTART_AN_LSB 9 |
| 4342 | #define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200 |
| 4343 | #define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB) |
| 4344 | #define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK) |
| 4345 | #define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0 |
| 4346 | #define MR_AN_CONTROL_DUPLEX_MODE_MSB 8 |
| 4347 | #define MR_AN_CONTROL_DUPLEX_MODE_LSB 8 |
| 4348 | #define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100 |
| 4349 | #define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB) |
| 4350 | #define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK) |
| 4351 | #define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1 |
| 4352 | #define MR_AN_CONTROL_SPEED_SEL1_MSB 6 |
| 4353 | #define MR_AN_CONTROL_SPEED_SEL1_LSB 6 |
| 4354 | #define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040 |
| 4355 | #define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB) |
| 4356 | #define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK) |
| 4357 | #define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1 |
| 4358 | #define MR_AN_CONTROL_ADDRESS 0x1807001c |
| 4359 | |
| 4360 | |
| 4361 | |
| 4362 | |
| 4363 | |
| 4364 | // 32'h18070014 (SGMII_RESET) |
| 4365 | #define SGMII_RESET_HW_RX_125M_N_MSB 4 |
| 4366 | #define SGMII_RESET_HW_RX_125M_N_LSB 4 |
| 4367 | #define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010 |
| 4368 | #define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB) |
| 4369 | #define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK) |
| 4370 | #define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0 |
| 4371 | #define SGMII_RESET_TX_125M_N_MSB 3 |
| 4372 | #define SGMII_RESET_TX_125M_N_LSB 3 |
| 4373 | #define SGMII_RESET_TX_125M_N_MASK 0x00000008 |
| 4374 | #define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB) |
| 4375 | #define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK) |
| 4376 | #define SGMII_RESET_TX_125M_N_RESET 0x0 // 0 |
| 4377 | #define SGMII_RESET_RX_125M_N_MSB 2 |
| 4378 | #define SGMII_RESET_RX_125M_N_LSB 2 |
| 4379 | #define SGMII_RESET_RX_125M_N_MASK 0x00000004 |
| 4380 | #define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB) |
| 4381 | #define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK) |
| 4382 | #define SGMII_RESET_RX_125M_N_RESET 0x0 // 0 |
| 4383 | #define SGMII_RESET_TX_CLK_N_MSB 1 |
| 4384 | #define SGMII_RESET_TX_CLK_N_LSB 1 |
| 4385 | #define SGMII_RESET_TX_CLK_N_MASK 0x00000002 |
| 4386 | #define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB) |
| 4387 | #define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK) |
| 4388 | #define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0 |
| 4389 | #define SGMII_RESET_RX_CLK_N_MSB 0 |
| 4390 | #define SGMII_RESET_RX_CLK_N_LSB 0 |
| 4391 | #define SGMII_RESET_RX_CLK_N_MASK 0x00000001 |
| 4392 | #define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB) |
| 4393 | #define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK) |
| 4394 | #define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0 |
| 4395 | #define SGMII_RESET_ADDRESS 0x18070014 |
| 4396 | |
| 4397 | |
| 4398 | |
| 4399 | // 32'h18070038 (SGMII_MAC_RX_CONFIG) |
| 4400 | #define SGMII_MAC_RX_CONFIG_LINK_MSB 15 |
| 4401 | #define SGMII_MAC_RX_CONFIG_LINK_LSB 15 |
| 4402 | #define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000 |
| 4403 | #define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB) |
| 4404 | #define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK) |
| 4405 | #define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0 |
| 4406 | #define SGMII_MAC_RX_CONFIG_ACK_MSB 14 |
| 4407 | #define SGMII_MAC_RX_CONFIG_ACK_LSB 14 |
| 4408 | #define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000 |
| 4409 | #define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB) |
| 4410 | #define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK) |
| 4411 | #define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0 |
| 4412 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12 |
| 4413 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12 |
| 4414 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000 |
| 4415 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) |
| 4416 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) |
| 4417 | #define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0 |
| 4418 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11 |
| 4419 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10 |
| 4420 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00 |
| 4421 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) |
| 4422 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) |
| 4423 | #define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0 |
| 4424 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8 |
| 4425 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8 |
| 4426 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100 |
| 4427 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) |
| 4428 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) |
| 4429 | #define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0 |
| 4430 | #define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7 |
| 4431 | #define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7 |
| 4432 | #define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080 |
| 4433 | #define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB) |
| 4434 | #define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) |
| 4435 | #define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0 |
| 4436 | #define SGMII_MAC_RX_CONFIG_RES0_MSB 0 |
| 4437 | #define SGMII_MAC_RX_CONFIG_RES0_LSB 0 |
| 4438 | #define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001 |
| 4439 | #define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB) |
| 4440 | #define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK) |
| 4441 | #define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1 |
| 4442 | #define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038 |
| 4443 | |
| 4444 | // 32'h18070058 (SGMII_DEBUG) |
| 4445 | #define SGMII_DEBUG_ARB_STATE_MSB 27 |
| 4446 | #define SGMII_DEBUG_ARB_STATE_LSB 24 |
| 4447 | #define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000 |
| 4448 | #define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB) |
| 4449 | #define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK) |
| 4450 | #define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0 |
| 4451 | #define SGMII_DEBUG_RX_SYNC_STATE_MSB 23 |
| 4452 | #define SGMII_DEBUG_RX_SYNC_STATE_LSB 16 |
| 4453 | #define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000 |
| 4454 | #define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB) |
| 4455 | #define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK) |
| 4456 | #define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0 |
| 4457 | #define SGMII_DEBUG_RX_STATE_MSB 15 |
| 4458 | #define SGMII_DEBUG_RX_STATE_LSB 8 |
| 4459 | #define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00 |
| 4460 | #define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB) |
| 4461 | #define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK) |
| 4462 | #define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0 |
| 4463 | #define SGMII_DEBUG_TX_STATE_MSB 7 |
| 4464 | #define SGMII_DEBUG_TX_STATE_LSB 0 |
| 4465 | #define SGMII_DEBUG_TX_STATE_MASK 0x000000ff |
| 4466 | #define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB) |
| 4467 | #define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK) |
| 4468 | #define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0 |
| 4469 | #define SGMII_DEBUG_ADDRESS 0x18070058 |
| 4470 | #define SGMII_DEBUG_OFFSET 0x0058 |
| 4471 | |
| 4472 | |
| 4473 | |
| 4474 | // 32'h18070060 (SGMII_INTERRUPT_MASK) |
| 4475 | #define SGMII_INTERRUPT_MASK_MASK_MSB 7 |
| 4476 | #define SGMII_INTERRUPT_MASK_MASK_LSB 0 |
| 4477 | #define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff |
| 4478 | #define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB) |
| 4479 | #define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK) |
| 4480 | #define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0 |
| 4481 | #define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060 |
| 4482 | |
| 4483 | |
| 4484 | |
| 4485 | |
| 4486 | // 32'h1807005c (SGMII_INTERRUPT) |
| 4487 | #define SGMII_INTERRUPT_INTR_MSB 7 |
| 4488 | #define SGMII_INTERRUPT_INTR_LSB 0 |
| 4489 | #define SGMII_INTERRUPT_INTR_MASK 0x000000ff |
| 4490 | #define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB) |
| 4491 | #define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK) |
| 4492 | #define SGMII_INTERRUPT_INTR_RESET 0x0 // 0 |
| 4493 | #define SGMII_INTERRUPT_ADDRESS 0x1807005c |
| 4494 | #define SGMII_INTERRUPT_OFFSET 0x005c |
| 4495 | // SW modifiable bits |
| 4496 | #define SGMII_INTERRUPT_SW_MASK 0x000000ff |
| 4497 | // bits defined at reset |
| 4498 | #define SGMII_INTERRUPT_RSTMASK 0xffffffff |
| 4499 | // reset value (ignore bits undefined at reset) |
| 4500 | #define SGMII_INTERRUPT_RESET 0x00000000 |
| 4501 | |
| 4502 | // 32'h18070060 (SGMII_INTERRUPT_MASK) |
| 4503 | #define SGMII_INTERRUPT_MASK_MASK_MSB 7 |
| 4504 | #define SGMII_INTERRUPT_MASK_MASK_LSB 0 |
| 4505 | #define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff |
| 4506 | #define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB) |
| 4507 | #define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK) |
| 4508 | #define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0 |
| 4509 | #define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060 |
| 4510 | |
| 4511 | |
| 4512 | #define SGMII_LINK_FAIL (1 << 0) |
| 4513 | #define SGMII_DUPLEX_ERR (1 << 1) |
| 4514 | #define SGMII_MR_AN_COMPLETE (1 << 2) |
| 4515 | #define SGMII_LINK_MAC_CHANGE (1 << 3) |
| 4516 | #define SGMII_DUPLEX_MODE_CHANGE (1 << 4) |
| 4517 | #define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5) |
| 4518 | #define SGMII_RX_QUIET_CHANGE (1 << 6) |
| 4519 | #define SGMII_RX_MDIO_COMP_CHANGE (1 << 7) |
| 4520 | |
| 4521 | #define SGMII_INTR SGMII_LINK_FAIL | \ |
| 4522 | SGMII_LINK_MAC_CHANGE | \ |
| 4523 | SGMII_DUPLEX_MODE_CHANGE | \ |
| 4524 | SGMII_SPEED_MODE_MAC_CHANGE |
| 4525 | |
| 4526 | |
| 4527 | // 32'h18050048 (ETH_SGMII) |
| 4528 | #define ETH_SGMII_TX_INVERT_MSB 31 |
| 4529 | #define ETH_SGMII_TX_INVERT_LSB 31 |
| 4530 | #define ETH_SGMII_TX_INVERT_MASK 0x80000000 |
| 4531 | #define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB) |
| 4532 | #define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK) |
| 4533 | #define ETH_SGMII_TX_INVERT_RESET 0x0 // 0 |
| 4534 | #define ETH_SGMII_GIGE_QUAD_MSB 30 |
| 4535 | #define ETH_SGMII_GIGE_QUAD_LSB 30 |
| 4536 | #define ETH_SGMII_GIGE_QUAD_MASK 0x40000000 |
| 4537 | #define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB) |
| 4538 | #define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK) |
| 4539 | #define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0 |
| 4540 | #define ETH_SGMII_RX_DELAY_MSB 29 |
| 4541 | #define ETH_SGMII_RX_DELAY_LSB 28 |
| 4542 | #define ETH_SGMII_RX_DELAY_MASK 0x30000000 |
| 4543 | #define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB) |
| 4544 | #define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK) |
| 4545 | #define ETH_SGMII_RX_DELAY_RESET 0x0 // 0 |
| 4546 | #define ETH_SGMII_TX_DELAY_MSB 27 |
| 4547 | #define ETH_SGMII_TX_DELAY_LSB 26 |
| 4548 | #define ETH_SGMII_TX_DELAY_MASK 0x0c000000 |
| 4549 | #define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB) |
| 4550 | #define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK) |
| 4551 | #define ETH_SGMII_TX_DELAY_RESET 0x0 // 0 |
| 4552 | #define ETH_SGMII_CLK_SEL_MSB 25 |
| 4553 | #define ETH_SGMII_CLK_SEL_LSB 25 |
| 4554 | #define ETH_SGMII_CLK_SEL_MASK 0x02000000 |
| 4555 | #define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB) |
| 4556 | #define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK) |
| 4557 | #define ETH_SGMII_CLK_SEL_RESET 0x1 // 1 |
| 4558 | #define ETH_SGMII_GIGE_MSB 24 |
| 4559 | #define ETH_SGMII_GIGE_LSB 24 |
| 4560 | #define ETH_SGMII_GIGE_MASK 0x01000000 |
| 4561 | #define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB) |
| 4562 | #define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK) |
| 4563 | #define ETH_SGMII_GIGE_RESET 0x1 // 1 |
| 4564 | #define ETH_SGMII_PHASE1_COUNT_MSB 15 |
| 4565 | #define ETH_SGMII_PHASE1_COUNT_LSB 8 |
| 4566 | #define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00 |
| 4567 | #define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB) |
| 4568 | #define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK) |
| 4569 | #define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1 |
| 4570 | #define ETH_SGMII_PHASE0_COUNT_MSB 7 |
| 4571 | #define ETH_SGMII_PHASE0_COUNT_LSB 0 |
| 4572 | #define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff |
| 4573 | #define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB) |
| 4574 | #define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK) |
| 4575 | #define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1 |
| 4576 | #define ETH_SGMII_ADDRESS 0x18050048 |
| 4577 | |
| 4578 | #endif /* _QCA953X_H */ |