Blame - include/956x.h - codeaurora/quic/qsdk/oss/boot/u-boot-2016

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)

1082

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)

1083

#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET 1

1084

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB 23

1085

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB 23

1086

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK 0x00800000

1087

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)

1088

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)

1089

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET 0

1090

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB 22

1091

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB 22

1092

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK 0x00400000

1093

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)

1094

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)

1095

#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET 0x0

1096

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MSB 21

1097

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB 21

1098

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK 0x00200000

1099

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB)

1100

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)

1101

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_RESET 0x0

1102

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MSB 20

1103

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB 20

1104

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK 0x00100000

1105

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB)

1106

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)

1107

#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_RESET 0x0 // 0

1108

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB 19

1109

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB 15

1110

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK 0x000f8000

1111

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)

1112

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)

1113

#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET 0

1114

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB 14

1115

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB 10

1116

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK 0x00007c00

1117

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)

1118

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)

1119

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET 0

1120

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB 9

1121

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB 5

1122

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK 0x000003e0

1123

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)

1124

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)

1125

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET 0

1126

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB 4

1127

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB 4

1128

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK 0x00000010

1129

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)

1130

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)

1131

#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET 1

1132

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB 3

1133

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB 3

1134

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK 0x00000008

1135

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)

1136

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)

1137

#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET 1

1138

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB 2

1139

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB 2

1140

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK 0x00000004

1141

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)

1142

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)

1143

#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET 1

1144

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB 1

1145

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB 1

1146

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK 0x00000002

1147

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)

1148

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)

1149

#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET 0

1150

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB 0

1151

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB 0

1152

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK 0x00000001

1153

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x) (((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)

1154

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x) (((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)

1155

#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET 0

1156

#define CPU_DDR_CLOCK_CONTROL_ADDRESS 0x18050010

1157

1158

#define PCIE_PLL_CONFIG_UPDATING_MSB 31

1159

#define PCIE_PLL_CONFIG_UPDATING_LSB 31

1160

#define PCIE_PLL_CONFIG_UPDATING_MASK 0x80000000

1161

#define PCIE_PLL_CONFIG_UPDATING_GET(x) (((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)

1162

#define PCIE_PLL_CONFIG_UPDATING_SET(x) (((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)

1163

#define PCIE_PLL_CONFIG_UPDATING_RESET 0x0 // 0

1164

#define PCIE_PLL_CONFIG_PLLPWD_MSB 30

1165

#define PCIE_PLL_CONFIG_PLLPWD_LSB 30

1166

#define PCIE_PLL_CONFIG_PLLPWD_MASK 0x40000000

1167

#define PCIE_PLL_CONFIG_PLLPWD_GET(x) (((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)

1168

#define PCIE_PLL_CONFIG_PLLPWD_SET(x) (((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)

1169

#define PCIE_PLL_CONFIG_PLLPWD_RESET 0x1 // 1

1170

#define PCIE_PLL_CONFIG_BYPASS_MSB 16

1171

#define PCIE_PLL_CONFIG_BYPASS_LSB 16

1172

#define PCIE_PLL_CONFIG_BYPASS_MASK 0x00010000

1173

#define PCIE_PLL_CONFIG_BYPASS_GET(x) (((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)

1174

#define PCIE_PLL_CONFIG_BYPASS_SET(x) (((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)

1175

#define PCIE_PLL_CONFIG_BYPASS_RESET 0x1 // 1

1176

#define PCIE_PLL_CONFIG_REFDIV_MSB 14

1177

#define PCIE_PLL_CONFIG_REFDIV_LSB 10

1178

#define PCIE_PLL_CONFIG_REFDIV_MASK 0x00007c00

1179

#define PCIE_PLL_CONFIG_REFDIV_GET(x) (((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)

1180

#define PCIE_PLL_CONFIG_REFDIV_SET(x) (((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)

1181

#define PCIE_PLL_CONFIG_REFDIV_RESET 0x1 // 1

1182

#define PCIE_PLL_CONFIG_ADDRESS 0x18050014

1183

1184

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB 31

1185

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB 31

1186

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK 0x80000000

1187

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)

1188

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)

1189

#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET 0x1 // 1

1190

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB 30

1191

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB 30

1192

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK 0x40000000

1193

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)

1194

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)

1195

#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET 0x1 // 1

1196

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB 20

1197

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB 15

1198

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK 0x001f8000

1199

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)

1200

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)

1201

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_RESET 0x13 // 19

1202

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB 14

1203

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB 1

1204

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK 0x00007ffe

1205

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)

1206

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)

1207

#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_RESET 0x3fff // 16383

1208

#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS 0x18050018

1209

1210

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB 20

1211

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB 15

1212

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK 0x001f8000

1213

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)

1214

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)

1215

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_RESET 0x13 // 19

1216

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB 14

1217

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB 1

1218

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK 0x00007ffe

1219

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)

1220

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)

1221

#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_RESET 0x399d // 14749

1222

#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS 0x1805001c

1223

1224

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB 31

1225

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB 28

1226

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK 0xf0000000

1227

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)

1228

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)

1229

#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET 0x0 // 0

1230

#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB 24

1231

#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB 15

1232

#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK 0x01ff8000

1233

#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)

1234

#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)

1235

#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET 0x0 // 0

1236

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB 14

1237

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB 1

1238

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK 0x00007ffe

1239

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x) (((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)

1240

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x) (((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)

1241

#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET 0xa // 10

1242

#define PCIE_PLL_DITHER_STEP_ADDRESS 0x18050020

1243

1244

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB 31

1245

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB 31

1246

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK 0x80000000

1247

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB)

1248

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK)

1249

#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET 0x0 // 0

1250

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB 30

1251

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB 29

1252

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK 0x60000000

1253

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB)

1254

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK)

1255

#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET 0x0 // 0

1256

#define PCIE_PHY_REG_1_PERSTDELAY_MSB 28

1257

#define PCIE_PHY_REG_1_PERSTDELAY_LSB 27

1258

#define PCIE_PHY_REG_1_PERSTDELAY_MASK 0x18000000

1259

#define PCIE_PHY_REG_1_PERSTDELAY_GET(x) (((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB)

1260

#define PCIE_PHY_REG_1_PERSTDELAY_SET(x) (((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK)

1261

#define PCIE_PHY_REG_1_PERSTDELAY_RESET 0x2 // 2

1262

#define PCIE_PHY_REG_1_CLKOBSSEL_MSB 26

1263

#define PCIE_PHY_REG_1_CLKOBSSEL_LSB 25

1264

#define PCIE_PHY_REG_1_CLKOBSSEL_MASK 0x06000000

1265

#define PCIE_PHY_REG_1_CLKOBSSEL_GET(x) (((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB)

1266

#define PCIE_PHY_REG_1_CLKOBSSEL_SET(x) (((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK)

1267

#define PCIE_PHY_REG_1_CLKOBSSEL_RESET 0x0 // 0

1268

#define PCIE_PHY_REG_1_DATAOBSEN_MSB 24

1269

#define PCIE_PHY_REG_1_DATAOBSEN_LSB 24

1270

#define PCIE_PHY_REG_1_DATAOBSEN_MASK 0x01000000

1271

#define PCIE_PHY_REG_1_DATAOBSEN_GET(x) (((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB)

1272

#define PCIE_PHY_REG_1_DATAOBSEN_SET(x) (((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK)

1273

#define PCIE_PHY_REG_1_DATAOBSEN_RESET 0x0 // 0

1274

#define PCIE_PHY_REG_1_FUNCTESTEN_MSB 23

1275

#define PCIE_PHY_REG_1_FUNCTESTEN_LSB 23

1276

#define PCIE_PHY_REG_1_FUNCTESTEN_MASK 0x00800000

1277

#define PCIE_PHY_REG_1_FUNCTESTEN_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB)

1278

#define PCIE_PHY_REG_1_FUNCTESTEN_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK)

1279

#define PCIE_PHY_REG_1_FUNCTESTEN_RESET 0x0 // 0

1280

#define PCIE_PHY_REG_1_SERDES_DISABLE_MSB 22

1281

#define PCIE_PHY_REG_1_SERDES_DISABLE_LSB 22

1282

#define PCIE_PHY_REG_1_SERDES_DISABLE_MASK 0x00400000

1283

#define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB)

1284

#define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK)

1285

#define PCIE_PHY_REG_1_SERDES_DISABLE_RESET 0x0 // 0

1286

#define PCIE_PHY_REG_1_RXCLKINV_MSB 21

1287

#define PCIE_PHY_REG_1_RXCLKINV_LSB 21

1288

#define PCIE_PHY_REG_1_RXCLKINV_MASK 0x00200000

1289

#define PCIE_PHY_REG_1_RXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB)

1290

#define PCIE_PHY_REG_1_RXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK)

1291

#define PCIE_PHY_REG_1_RXCLKINV_RESET 0x1 // 1

1292

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB 20

1293

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB 20

1294

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK 0x00100000

1295

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB)

1296

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK)

1297

#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET 0x0 // 0

1298

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB 19

1299

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB 19

1300

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK 0x00080000

1301

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x) (((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB)

1302

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x) (((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK)

1303

#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET 0x0 // 0

1304

#define PCIE_PHY_REG_1_ENABLECLKREQ_MSB 18

1305

#define PCIE_PHY_REG_1_ENABLECLKREQ_LSB 18

1306

#define PCIE_PHY_REG_1_ENABLECLKREQ_MASK 0x00040000

1307

#define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x) (((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB)

1308

#define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x) (((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK)

1309

#define PCIE_PHY_REG_1_ENABLECLKREQ_RESET 0x0 // 0

1310

#define PCIE_PHY_REG_1_FORCELOOPBACK_MSB 17

1311

#define PCIE_PHY_REG_1_FORCELOOPBACK_LSB 17

1312

#define PCIE_PHY_REG_1_FORCELOOPBACK_MASK 0x00020000

1313

#define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x) (((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB)

1314

#define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x) (((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK)

1315

#define PCIE_PHY_REG_1_FORCELOOPBACK_RESET 0x0 // 0

1316

#define PCIE_PHY_REG_1_SEL_CLK_MSB 16

1317

#define PCIE_PHY_REG_1_SEL_CLK_LSB 15

1318

#define PCIE_PHY_REG_1_SEL_CLK_MASK 0x00018000

1319

#define PCIE_PHY_REG_1_SEL_CLK_GET(x) (((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB)

1320

#define PCIE_PHY_REG_1_SEL_CLK_SET(x) (((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK)

1321

#define PCIE_PHY_REG_1_SEL_CLK_RESET 0x2 // 2

1322

#define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB 14

1323

#define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB 14

1324

#define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK 0x00004000

1325

#define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB)

1326

#define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK)

1327

#define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET 0x0 // 0

1328

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB 13

1329

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB 13

1330

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK 0x00002000

1331

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB)

1332

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK)

1333

#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET 0x1 // 1

1334

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB 12

1335

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB 12

1336

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK 0x00001000

1337

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)

1338

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)

1339

#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET 0x0 // 0

1340

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB 11

1341

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB 11

1342

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK 0x00000800

1343

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB)

1344

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK)

1345

#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET 0x0 // 0

1346

#define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB 10

1347

#define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB 9

1348

#define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK 0x00000600

1349

#define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB)

1350

#define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK)

1351

#define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET 0x3 // 3

1352

#define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB 8

1353

#define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB 7

1354

#define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK 0x00000180

1355

#define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB)

1356

#define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK)

1357

#define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET 0x0 // 0

1358

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB 6

1359

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB 6

1360

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK 0x00000040

1361

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB)

1362

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK)

1363

#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET 0x1 // 1

1364

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB 5

1365

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB 5

1366

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK 0x00000020

1367

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB)

1368

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK)

1369

#define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET 0x0 // 0

1370

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB 4

1371

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB 4

1372

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK 0x00000010

1373

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x) (((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB)

1374

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x) (((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK)

1375

#define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET 0x1 // 1

1376

#define PCIE_PHY_REG_1_S_MSB 3

1377

#define PCIE_PHY_REG_1_S_LSB 0

1378

#define PCIE_PHY_REG_1_S_MASK 0x0000000f

1379

#define PCIE_PHY_REG_1_S_GET(x) (((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB)

1380

#define PCIE_PHY_REG_1_S_SET(x) (((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK)

1381

#define PCIE_PHY_REG_1_S_RESET 0x7 // 7

1382

#define PCIE_PHY_REG_1_ADDRESS 0x18116e00

1383

#define PCIE_PHY_REG_1_OFFSET 0x0000

1384

// SW modifiable bits

1385

#define PCIE_PHY_REG_1_SW_MASK 0xffffffff

1386

// bits defined at reset

1387

#define PCIE_PHY_REG_1_RSTMASK 0xffffffff

1388

// reset value (ignore bits undefined at reset)

1389

#define PCIE_PHY_REG_1_RESET 0x1021265e

1390

#define PCIE_PHY_REG_1_RESET_1 0x0061060e

1391

1392

#define LDO_POWER_CONTROL_PKG_SEL_MSB 5

1393

#define LDO_POWER_CONTROL_PKG_SEL_LSB 5

1394

#define LDO_POWER_CONTROL_PKG_SEL_MASK 0x00000020

1395

#define LDO_POWER_CONTROL_PKG_SEL_GET(x) (((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)

1396

#define LDO_POWER_CONTROL_PKG_SEL_SET(x) (((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)

1397

#define LDO_POWER_CONTROL_PKG_SEL_RESET 0x0 // 0

1398

#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB 4

1399

#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB 4

1400

#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK 0x00000010

1401

#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)

1402

#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)

1403

#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET 0x0 // 0

1404

#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB 3

1405

#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB 3

1406

#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK 0x00000008

1407

#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x) (((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)

1408

#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x) (((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)

1409

#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET 0x0 // 0

1410

#define LDO_POWER_CONTROL_CPU_REFSEL_MSB 2

1411

#define LDO_POWER_CONTROL_CPU_REFSEL_LSB 1

1412

#define LDO_POWER_CONTROL_CPU_REFSEL_MASK 0x00000006

1413

#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x) (((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)

1414

#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x) (((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)

1415

#define LDO_POWER_CONTROL_CPU_REFSEL_RESET 0x3 // 3

1416

#define LDO_POWER_CONTROL_SELECT_DDR1_MSB 0

1417

#define LDO_POWER_CONTROL_SELECT_DDR1_LSB 0

1418

#define LDO_POWER_CONTROL_SELECT_DDR1_MASK 0x00000001

1419

#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x) (((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)

1420

#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x) (((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)

1421

#define LDO_POWER_CONTROL_SELECT_DDR1_RESET 0x0 // 0

1422

#define LDO_POWER_CONTROL_ADDRESS 0x18050024

1423

1424

#define SWITCH_CLOCK_SPARE_SPARE_MSB 31

1425

#define SWITCH_CLOCK_SPARE_SPARE_LSB 20

1426

#define SWITCH_CLOCK_SPARE_SPARE_MASK 0xfff00000

1427

#define SWITCH_CLOCK_SPARE_SPARE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)

1428

#define SWITCH_CLOCK_SPARE_SPARE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)

1429

#define SWITCH_CLOCK_SPARE_SPARE_RESET 0x0 // 0

1430

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MSB 19

1431

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB 19

1432

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK 0x00080000

1433

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB)

1434

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_LSB) & SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_MASK)

1435

#define SWITCH_CLOCK_SPARE_SWITCHCLK_SEL_RESET 0x1 // 1

1436

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MSB 18

1437

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB 18

1438

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK 0x00040000

1439

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_GET(x) (((x) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK) >> SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB)

1440

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_SET(x) (((x) << SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_LSB) & SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_MASK)

1441

#define SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL_RESET 0x1 // 1

1442

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MSB 17

1443

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB 17

1444

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK 0x00020000

1445

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_GET(x) (((x) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK) >> SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB)

1446

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_SET(x) (((x) << SWITCH_CLOCK_SPARE_EEE_ENABLE_LSB) & SWITCH_CLOCK_SPARE_EEE_ENABLE_MASK)

1447

#define SWITCH_CLOCK_SPARE_EEE_ENABLE_RESET 0x0 // 0

1448

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MSB 16

1449

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB 16

1450

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK 0x00010000

1451

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_GET(x) (((x) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK) >> SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB)

1452

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_SET(x) (((x) << SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_LSB) & SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_MASK)

1453

#define SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE_RESET 0x0 // 0

1454

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MSB 15

1455

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB 15

1456

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK 0x00008000

1457

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB)

1458

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK)

1459

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_RESET 0x0 // 0

1460

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MSB 14

1461

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB 14

1462

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK 0x00004000

1463

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB)

1464

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK)

1465

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_RESET 0x0 // 0

1466

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MSB 13

1467

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB 13

1468

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK 0x00002000

1469

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB)

1470

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK)

1471

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_RESET 0x0 // 0

1472

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MSB 12

1473

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB 12

1474

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK 0x00001000

1475

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_GET(x) (((x) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK) >> SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB)

1476

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_SET(x) (((x) << SWITCH_CLOCK_SPARE_EN_PLL_TOP_LSB) & SWITCH_CLOCK_SPARE_EN_PLL_TOP_MASK)

1477

#define SWITCH_CLOCK_SPARE_EN_PLL_TOP_RESET 0x1 // 1

1478

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB 11

1479

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB 8

1480

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0x00000f00

1481

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)

1482

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)

1483

#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET 0x5 // 5

1484

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB 7

1485

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB 7

1486

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK 0x00000080

1487

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)

1488

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)

1489

#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET 0x0 // 0

1490

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MSB 6

1491

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB 6

1492

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK 0x00000040

1493

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_GET(x) (((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB)

1494

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_SET(x) (((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK)

1495

#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_RESET 0x0 // 0

1496

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MSB 5

1497

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB 5

1498

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK 0x00000020

1499

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_GET(x) (((x) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB)

1500

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_SET(x) (((x) << SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK)

1501

#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_RESET 0x0 // 0

1502

#define SWITCH_CLOCK_SPARE_SPARE_0_MSB 4

1503

#define SWITCH_CLOCK_SPARE_SPARE_0_LSB 0

1504

#define SWITCH_CLOCK_SPARE_SPARE_0_MASK 0x0000001f

1505

#define SWITCH_CLOCK_SPARE_SPARE_0_GET(x) (((x) & SWITCH_CLOCK_SPARE_SPARE_0_MASK) >> SWITCH_CLOCK_SPARE_SPARE_0_LSB)

1506

#define SWITCH_CLOCK_SPARE_SPARE_0_SET(x) (((x) << SWITCH_CLOCK_SPARE_SPARE_0_LSB) & SWITCH_CLOCK_SPARE_SPARE_0_MASK)

1507

#define SWITCH_CLOCK_SPARE_SPARE_0_RESET 0x0 // 0

1508

#define SWITCH_CLOCK_SPARE_ADDRESS 0x18050028

1509

1510

#define CURRENT_PCIE_PLL_DITHER_INT_MSB 20

1511

#define CURRENT_PCIE_PLL_DITHER_INT_LSB 15

1512

#define CURRENT_PCIE_PLL_DITHER_INT_MASK 0x001f8000

1513

#define CURRENT_PCIE_PLL_DITHER_INT_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_INT_MASK) >> CURRENT_PCIE_PLL_DITHER_INT_LSB)

1514

#define CURRENT_PCIE_PLL_DITHER_INT_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_INT_LSB) & CURRENT_PCIE_PLL_DITHER_INT_MASK)

1515

#define CURRENT_PCIE_PLL_DITHER_INT_RESET 0x1 // 1

1516

#define CURRENT_PCIE_PLL_DITHER_FRAC_MSB 13

1517

#define CURRENT_PCIE_PLL_DITHER_FRAC_LSB 0

1518

#define CURRENT_PCIE_PLL_DITHER_FRAC_MASK 0x00003fff

1519

#define CURRENT_PCIE_PLL_DITHER_FRAC_GET(x) (((x) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK) >> CURRENT_PCIE_PLL_DITHER_FRAC_LSB)

1520

#define CURRENT_PCIE_PLL_DITHER_FRAC_SET(x) (((x) << CURRENT_PCIE_PLL_DITHER_FRAC_LSB) & CURRENT_PCIE_PLL_DITHER_FRAC_MASK)

1521

#define CURRENT_PCIE_PLL_DITHER_FRAC_RESET 0x0 // 0

1522

#define CURRENT_PCIE_PLL_DITHER_ADDRESS 0x1805002c

1523

1524

#define ETH_XMII_TX_INVERT_MSB 31

1525

#define ETH_XMII_TX_INVERT_LSB 31

1526

#define ETH_XMII_TX_INVERT_MASK 0x80000000

1527

#define ETH_XMII_TX_INVERT_GET(x) (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)

1528

#define ETH_XMII_TX_INVERT_SET(x) (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)

1529

#define ETH_XMII_TX_INVERT_RESET 0x0 // 0

1530

#define ETH_XMII_GIGE_QUAD_MSB 30

1531

#define ETH_XMII_GIGE_QUAD_LSB 30

1532

#define ETH_XMII_GIGE_QUAD_MASK 0x40000000

1533

#define ETH_XMII_GIGE_QUAD_GET(x) (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)

1534

#define ETH_XMII_GIGE_QUAD_SET(x) (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)

1535

#define ETH_XMII_GIGE_QUAD_RESET 0x0 // 0

1536

#define ETH_XMII_RX_DELAY_MSB 29

1537

#define ETH_XMII_RX_DELAY_LSB 28

1538

#define ETH_XMII_RX_DELAY_MASK 0x30000000

1539

#define ETH_XMII_RX_DELAY_GET(x) (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)

1540

#define ETH_XMII_RX_DELAY_SET(x) (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)

1541

#define ETH_XMII_RX_DELAY_RESET 0x0 // 0

1542

#define ETH_XMII_TX_DELAY_MSB 27

1543

#define ETH_XMII_TX_DELAY_LSB 26

1544

#define ETH_XMII_TX_DELAY_MASK 0x0c000000

1545

#define ETH_XMII_TX_DELAY_GET(x) (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)

1546

#define ETH_XMII_TX_DELAY_SET(x) (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)

1547

#define ETH_XMII_TX_DELAY_RESET 0x0 // 0

1548

#define ETH_XMII_GIGE_MSB 25

1549

#define ETH_XMII_GIGE_LSB 25

1550

#define ETH_XMII_GIGE_MASK 0x02000000

1551

#define ETH_XMII_GIGE_GET(x) (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)

1552

#define ETH_XMII_GIGE_SET(x) (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)

1553

#define ETH_XMII_GIGE_RESET 0x0 // 0

1554

#define ETH_XMII_OFFSET_PHASE_MSB 24

1555

#define ETH_XMII_OFFSET_PHASE_LSB 24

1556

#define ETH_XMII_OFFSET_PHASE_MASK 0x01000000

1557

#define ETH_XMII_OFFSET_PHASE_GET(x) (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)

1558

#define ETH_XMII_OFFSET_PHASE_SET(x) (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)

1559

#define ETH_XMII_OFFSET_PHASE_RESET 0x0 // 0

1560

#define ETH_XMII_OFFSET_COUNT_MSB 23

1561

#define ETH_XMII_OFFSET_COUNT_LSB 16

1562

#define ETH_XMII_OFFSET_COUNT_MASK 0x00ff0000

1563

#define ETH_XMII_OFFSET_COUNT_GET(x) (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)

1564

#define ETH_XMII_OFFSET_COUNT_SET(x) (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)

1565

#define ETH_XMII_OFFSET_COUNT_RESET 0x0 // 0

1566

#define ETH_XMII_PHASE1_COUNT_MSB 15

1567

#define ETH_XMII_PHASE1_COUNT_LSB 8

1568

#define ETH_XMII_PHASE1_COUNT_MASK 0x0000ff00

1569

#define ETH_XMII_PHASE1_COUNT_GET(x) (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)

1570

#define ETH_XMII_PHASE1_COUNT_SET(x) (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)

1571

#define ETH_XMII_PHASE1_COUNT_RESET 0x1 // 1

1572

#define ETH_XMII_PHASE0_COUNT_MSB 7

1573

#define ETH_XMII_PHASE0_COUNT_LSB 0

1574

#define ETH_XMII_PHASE0_COUNT_MASK 0x000000ff

1575

#define ETH_XMII_PHASE0_COUNT_GET(x) (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)

1576

#define ETH_XMII_PHASE0_COUNT_SET(x) (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)

1577

#define ETH_XMII_PHASE0_COUNT_RESET 0x1 // 1

1578

#define ETH_XMII_ADDRESS 0x18050030

1579

1580

#define BB_PLL_CONFIG_UPDATING_MSB 31

1581

#define BB_PLL_CONFIG_UPDATING_LSB 31

1582

#define BB_PLL_CONFIG_UPDATING_MASK 0x80000000

1583

#define BB_PLL_CONFIG_UPDATING_GET(x) (((x) & BB_PLL_CONFIG_UPDATING_MASK) >> BB_PLL_CONFIG_UPDATING_LSB)

1584

#define BB_PLL_CONFIG_UPDATING_SET(x) (((x) << BB_PLL_CONFIG_UPDATING_LSB) & BB_PLL_CONFIG_UPDATING_MASK)

1585

#define BB_PLL_CONFIG_UPDATING_RESET 0x1 // 1

1586

#define BB_PLL_CONFIG_PLLPWD_MSB 30

1587

#define BB_PLL_CONFIG_PLLPWD_LSB 30

1588

#define BB_PLL_CONFIG_PLLPWD_MASK 0x40000000

1589

#define BB_PLL_CONFIG_PLLPWD_GET(x) (((x) & BB_PLL_CONFIG_PLLPWD_MASK) >> BB_PLL_CONFIG_PLLPWD_LSB)

1590

#define BB_PLL_CONFIG_PLLPWD_SET(x) (((x) << BB_PLL_CONFIG_PLLPWD_LSB) & BB_PLL_CONFIG_PLLPWD_MASK)

1591

#define BB_PLL_CONFIG_PLLPWD_RESET 0x1 // 1

1592

#define BB_PLL_CONFIG_SPARE_MSB 29

1593

#define BB_PLL_CONFIG_SPARE_LSB 29

1594

#define BB_PLL_CONFIG_SPARE_MASK 0x20000000

1595

#define BB_PLL_CONFIG_SPARE_GET(x) (((x) & BB_PLL_CONFIG_SPARE_MASK) >> BB_PLL_CONFIG_SPARE_LSB)

1596

#define BB_PLL_CONFIG_SPARE_SET(x) (((x) << BB_PLL_CONFIG_SPARE_LSB) & BB_PLL_CONFIG_SPARE_MASK)

1597

#define BB_PLL_CONFIG_SPARE_RESET 0x0 // 0

1598

#define BB_PLL_CONFIG_REFDIV_MSB 28

1599

#define BB_PLL_CONFIG_REFDIV_LSB 24

1600

#define BB_PLL_CONFIG_REFDIV_MASK 0x1f000000

1601

#define BB_PLL_CONFIG_REFDIV_GET(x) (((x) & BB_PLL_CONFIG_REFDIV_MASK) >> BB_PLL_CONFIG_REFDIV_LSB)

1602

#define BB_PLL_CONFIG_REFDIV_SET(x) (((x) << BB_PLL_CONFIG_REFDIV_LSB) & BB_PLL_CONFIG_REFDIV_MASK)

1603

#define BB_PLL_CONFIG_REFDIV_RESET 0x1 // 1

1604

#define BB_PLL_CONFIG_NINT_MSB 21

1605

#define BB_PLL_CONFIG_NINT_LSB 16

1606

#define BB_PLL_CONFIG_NINT_MASK 0x003f0000

1607

#define BB_PLL_CONFIG_NINT_GET(x) (((x) & BB_PLL_CONFIG_NINT_MASK) >> BB_PLL_CONFIG_NINT_LSB)

1608

#define BB_PLL_CONFIG_NINT_SET(x) (((x) << BB_PLL_CONFIG_NINT_LSB) & BB_PLL_CONFIG_NINT_MASK)

1609

#define BB_PLL_CONFIG_NINT_RESET 0x2 // 2

1610

#define BB_PLL_CONFIG_NFRAC_MSB 13

1611

#define BB_PLL_CONFIG_NFRAC_LSB 0

1612

#define BB_PLL_CONFIG_NFRAC_MASK 0x00003fff

1613

#define BB_PLL_CONFIG_NFRAC_GET(x) (((x) & BB_PLL_CONFIG_NFRAC_MASK) >> BB_PLL_CONFIG_NFRAC_LSB)

1614

#define BB_PLL_CONFIG_NFRAC_SET(x) (((x) << BB_PLL_CONFIG_NFRAC_LSB) & BB_PLL_CONFIG_NFRAC_MASK)

1615

#define BB_PLL_CONFIG_NFRAC_RESET 0xccc // 3276

1616

#define BB_PLL_CONFIG_ADDRESS 0x18050034

1617

1618

#define DDR_PLL_DITHER1_DITHER_EN_MSB 31

1619

#define DDR_PLL_DITHER1_DITHER_EN_LSB 31

1620

#define DDR_PLL_DITHER1_DITHER_EN_MASK 0x80000000

1621

#define DDR_PLL_DITHER1_DITHER_EN_GET(x) (((x) & DDR_PLL_DITHER1_DITHER_EN_MASK) >> DDR_PLL_DITHER1_DITHER_EN_LSB)

1622

#define DDR_PLL_DITHER1_DITHER_EN_SET(x) (((x) << DDR_PLL_DITHER1_DITHER_EN_LSB) & DDR_PLL_DITHER1_DITHER_EN_MASK)

1623

#define DDR_PLL_DITHER1_DITHER_EN_RESET 0x0 // 0

1624

#define DDR_PLL_DITHER1_UPDATE_COUNT_MSB 30

1625

#define DDR_PLL_DITHER1_UPDATE_COUNT_LSB 27

1626

#define DDR_PLL_DITHER1_UPDATE_COUNT_MASK 0x78000000

1627

#define DDR_PLL_DITHER1_UPDATE_COUNT_GET(x) (((x) & DDR_PLL_DITHER1_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER1_UPDATE_COUNT_LSB)

1628

#define DDR_PLL_DITHER1_UPDATE_COUNT_SET(x) (((x) << DDR_PLL_DITHER1_UPDATE_COUNT_LSB) & DDR_PLL_DITHER1_UPDATE_COUNT_MASK)

1629

#define DDR_PLL_DITHER1_UPDATE_COUNT_RESET 0xf // 15

1630

#define DDR_PLL_DITHER1_NFRAC_STEP_MSB 26

1631

#define DDR_PLL_DITHER1_NFRAC_STEP_LSB 20

1632

#define DDR_PLL_DITHER1_NFRAC_STEP_MASK 0x07f00000

1633

#define DDR_PLL_DITHER1_NFRAC_STEP_GET(x) (((x) & DDR_PLL_DITHER1_NFRAC_STEP_MASK) >> DDR_PLL_DITHER1_NFRAC_STEP_LSB)

1634

#define DDR_PLL_DITHER1_NFRAC_STEP_SET(x) (((x) << DDR_PLL_DITHER1_NFRAC_STEP_LSB) & DDR_PLL_DITHER1_NFRAC_STEP_MASK)

1635

#define DDR_PLL_DITHER1_NFRAC_STEP_RESET 0x1 // 1

1636

#define DDR_PLL_DITHER1_NFRAC_MIN_MSB 17

1637

#define DDR_PLL_DITHER1_NFRAC_MIN_LSB 0

1638

#define DDR_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff

1639

#define DDR_PLL_DITHER1_NFRAC_MIN_GET(x) (((x) & DDR_PLL_DITHER1_NFRAC_MIN_MASK) >> DDR_PLL_DITHER1_NFRAC_MIN_LSB)

1640

#define DDR_PLL_DITHER1_NFRAC_MIN_SET(x) (((x) << DDR_PLL_DITHER1_NFRAC_MIN_LSB) & DDR_PLL_DITHER1_NFRAC_MIN_MASK)

1641

#define DDR_PLL_DITHER1_NFRAC_MIN_RESET 0x1900 // 6400

1642

#define DDR_PLL_DITHER1_ADDRESS 0x18050038

1643

1644

#define DDR_PLL_DITHER2_NFRAC_MAX_MSB 17

1645

#define DDR_PLL_DITHER2_NFRAC_MAX_LSB 0

1646

#define DDR_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff

1647

#define DDR_PLL_DITHER2_NFRAC_MAX_GET(x) (((x) & DDR_PLL_DITHER2_NFRAC_MAX_MASK) >> DDR_PLL_DITHER2_NFRAC_MAX_LSB)

1648

#define DDR_PLL_DITHER2_NFRAC_MAX_SET(x) (((x) << DDR_PLL_DITHER2_NFRAC_MAX_LSB) & DDR_PLL_DITHER2_NFRAC_MAX_MASK)

1649

#define DDR_PLL_DITHER2_NFRAC_MAX_RESET 0x3e800 // 256000

1650

#define DDR_PLL_DITHER2_ADDRESS 0x1805003c

1651

1652

#define CPU_PLL_DITHER1_DITHER_EN_MSB 31

1653

#define CPU_PLL_DITHER1_DITHER_EN_LSB 31

1654

#define CPU_PLL_DITHER1_DITHER_EN_MASK 0x80000000

1655

#define CPU_PLL_DITHER1_DITHER_EN_GET(x) (((x) & CPU_PLL_DITHER1_DITHER_EN_MASK) >> CPU_PLL_DITHER1_DITHER_EN_LSB)

1656

#define CPU_PLL_DITHER1_DITHER_EN_SET(x) (((x) << CPU_PLL_DITHER1_DITHER_EN_LSB) & CPU_PLL_DITHER1_DITHER_EN_MASK)

1657

#define CPU_PLL_DITHER1_DITHER_EN_RESET 0x0 // 0

1658

#define CPU_PLL_DITHER1_UPDATE_COUNT_MSB 29

1659

#define CPU_PLL_DITHER1_UPDATE_COUNT_LSB 24

1660

#define CPU_PLL_DITHER1_UPDATE_COUNT_MASK 0x3f000000

1661

#define CPU_PLL_DITHER1_UPDATE_COUNT_GET(x) (((x) & CPU_PLL_DITHER1_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER1_UPDATE_COUNT_LSB)

1662

#define CPU_PLL_DITHER1_UPDATE_COUNT_SET(x) (((x) << CPU_PLL_DITHER1_UPDATE_COUNT_LSB) & CPU_PLL_DITHER1_UPDATE_COUNT_MASK)

1663

#define CPU_PLL_DITHER1_UPDATE_COUNT_RESET 0x14 // 20

1664

#define CPU_PLL_DITHER1_NFRAC_STEP_MSB 23

1665

#define CPU_PLL_DITHER1_NFRAC_STEP_LSB 18

1666

#define CPU_PLL_DITHER1_NFRAC_STEP_MASK 0x00fc0000

1667

#define CPU_PLL_DITHER1_NFRAC_STEP_GET(x) (((x) & CPU_PLL_DITHER1_NFRAC_STEP_MASK) >> CPU_PLL_DITHER1_NFRAC_STEP_LSB)

1668

#define CPU_PLL_DITHER1_NFRAC_STEP_SET(x) (((x) << CPU_PLL_DITHER1_NFRAC_STEP_LSB) & CPU_PLL_DITHER1_NFRAC_STEP_MASK)

1669

#define CPU_PLL_DITHER1_NFRAC_STEP_RESET 0x1 // 1

1670

#define CPU_PLL_DITHER1_NFRAC_MIN_MSB 17

1671

#define CPU_PLL_DITHER1_NFRAC_MIN_LSB 0

1672

#define CPU_PLL_DITHER1_NFRAC_MIN_MASK 0x0003ffff

1673

#define CPU_PLL_DITHER1_NFRAC_MIN_GET(x) (((x) & CPU_PLL_DITHER1_NFRAC_MIN_MASK) >> CPU_PLL_DITHER1_NFRAC_MIN_LSB)

1674

#define CPU_PLL_DITHER1_NFRAC_MIN_SET(x) (((x) << CPU_PLL_DITHER1_NFRAC_MIN_LSB) & CPU_PLL_DITHER1_NFRAC_MIN_MASK)

1675

#define CPU_PLL_DITHER1_NFRAC_MIN_RESET 0x3000 // 12288

1676

#define CPU_PLL_DITHER1_ADDRESS 0x18050040

1677

1678

#define CPU_PLL_DITHER2_NFRAC_MAX_MSB 17

1679

#define CPU_PLL_DITHER2_NFRAC_MAX_LSB 0

1680

#define CPU_PLL_DITHER2_NFRAC_MAX_MASK 0x0003ffff

1681

#define CPU_PLL_DITHER2_NFRAC_MAX_GET(x) (((x) & CPU_PLL_DITHER2_NFRAC_MAX_MASK) >> CPU_PLL_DITHER2_NFRAC_MAX_LSB)

1682

#define CPU_PLL_DITHER2_NFRAC_MAX_SET(x) (((x) << CPU_PLL_DITHER2_NFRAC_MAX_LSB) & CPU_PLL_DITHER2_NFRAC_MAX_MASK)

1683

#define CPU_PLL_DITHER2_NFRAC_MAX_RESET 0x3c000 // 245760

1684

#define CPU_PLL_DITHER2_ADDRESS 0x18050044

1685

1686

#define RST_RESET_HOST_RESET_MSB 31

1687

#define RST_RESET_HOST_RESET_LSB 31

1688

#define RST_RESET_HOST_RESET_MASK 0x80000000

1689

#define RST_RESET_HOST_RESET_GET(x) (((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)

1690

#define RST_RESET_HOST_RESET_SET(x) (((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)

1691

#define RST_RESET_HOST_RESET_RESET 0x0 // 0

1692

#define RST_RESET_EXTERNAL_RESET_MSB 28

1693

#define RST_RESET_EXTERNAL_RESET_LSB 28

1694

#define RST_RESET_EXTERNAL_RESET_MASK 0x10000000

1695

#define RST_RESET_EXTERNAL_RESET_GET(x) (((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)

1696

#define RST_RESET_EXTERNAL_RESET_SET(x) (((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)

1697

#define RST_RESET_EXTERNAL_RESET_RESET 0x0 // 0

1698

#define RST_RESET_RTC_RESET_MSB 27

1699

#define RST_RESET_RTC_RESET_LSB 27

1700

#define RST_RESET_RTC_RESET_MASK 0x08000000

1701

#define RST_RESET_RTC_RESET_GET(x) (((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)

1702

#define RST_RESET_RTC_RESET_SET(x) (((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)

1703

#define RST_RESET_RTC_RESET_RESET 0x1 // 1

1704

#define RST_RESET_PCIEEP_RST_INT_MSB 26

1705

#define RST_RESET_PCIEEP_RST_INT_LSB 26

1706

#define RST_RESET_PCIEEP_RST_INT_MASK 0x04000000

1707

#define RST_RESET_PCIEEP_RST_INT_GET(x) (((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)

1708

#define RST_RESET_PCIEEP_RST_INT_SET(x) (((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)

1709

#define RST_RESET_PCIEEP_RST_INT_RESET 0x0 // 0

1710

#define RST_RESET_CHKSUM_ACC_RESET_MSB 25

1711

#define RST_RESET_CHKSUM_ACC_RESET_LSB 25

1712

#define RST_RESET_CHKSUM_ACC_RESET_MASK 0x02000000

1713

#define RST_RESET_CHKSUM_ACC_RESET_GET(x) (((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB)

1714

#define RST_RESET_CHKSUM_ACC_RESET_SET(x) (((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK)

1715

#define RST_RESET_CHKSUM_ACC_RESET_RESET 0x0 // 0

1716

#define RST_RESET_FULL_CHIP_RESET_MSB 24

1717

#define RST_RESET_FULL_CHIP_RESET_LSB 24

1718

#define RST_RESET_FULL_CHIP_RESET_MASK 0x01000000

1719

#define RST_RESET_FULL_CHIP_RESET_GET(x) (((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)

1720

#define RST_RESET_FULL_CHIP_RESET_SET(x) (((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)

1721

#define RST_RESET_FULL_CHIP_RESET_RESET 0x0 // 0

1722

#define RST_RESET_GE1_MDIO_RESET_MSB 23

1723

#define RST_RESET_GE1_MDIO_RESET_LSB 23

1724

#define RST_RESET_GE1_MDIO_RESET_MASK 0x00800000

1725

#define RST_RESET_GE1_MDIO_RESET_GET(x) (((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)

1726

#define RST_RESET_GE1_MDIO_RESET_SET(x) (((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)

1727

#define RST_RESET_GE1_MDIO_RESET_RESET 0x1 // 1

1728

#define RST_RESET_GE0_MDIO_RESET_MSB 22

1729

#define RST_RESET_GE0_MDIO_RESET_LSB 22

1730

#define RST_RESET_GE0_MDIO_RESET_MASK 0x00400000

1731

#define RST_RESET_GE0_MDIO_RESET_GET(x) (((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)

1732

#define RST_RESET_GE0_MDIO_RESET_SET(x) (((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)

1733

#define RST_RESET_GE0_MDIO_RESET_RESET 0x1 // 1

1734

#define RST_RESET_CPU_NMI_MSB 21

1735

#define RST_RESET_CPU_NMI_LSB 21

1736

#define RST_RESET_CPU_NMI_MASK 0x00200000

1737

#define RST_RESET_CPU_NMI_GET(x) (((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)

1738

#define RST_RESET_CPU_NMI_SET(x) (((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)

1739

#define RST_RESET_CPU_NMI_RESET 0x0 // 0

1740

#define RST_RESET_CPU_COLD_RESET_MSB 20

1741

#define RST_RESET_CPU_COLD_RESET_LSB 20

1742

#define RST_RESET_CPU_COLD_RESET_MASK 0x00100000

1743

#define RST_RESET_CPU_COLD_RESET_GET(x) (((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)

1744

#define RST_RESET_CPU_COLD_RESET_SET(x) (((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)

1745

#define RST_RESET_CPU_COLD_RESET_RESET 0x0 // 0

1746

#define RST_RESET_HOST_RESET_INT_MSB 19

1747

#define RST_RESET_HOST_RESET_INT_LSB 19

1748

#define RST_RESET_HOST_RESET_INT_MASK 0x00080000

1749

#define RST_RESET_HOST_RESET_INT_GET(x) (((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)

1750

#define RST_RESET_HOST_RESET_INT_SET(x) (((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)

1751

#define RST_RESET_HOST_RESET_INT_RESET 0x0 // 0

1752

#define RST_RESET_PCIEEP_RESET_MSB 18

1753

#define RST_RESET_PCIEEP_RESET_LSB 18

1754

#define RST_RESET_PCIEEP_RESET_MASK 0x00040000

1755

#define RST_RESET_PCIEEP_RESET_GET(x) (((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)

1756

#define RST_RESET_PCIEEP_RESET_SET(x) (((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)

1757

#define RST_RESET_PCIEEP_RESET_RESET 0x0 // 0

1758

#define RST_RESET_UART1_RESET_MSB 17

1759

#define RST_RESET_UART1_RESET_LSB 17

1760

#define RST_RESET_UART1_RESET_MASK 0x00020000

1761

#define RST_RESET_UART1_RESET_GET(x) (((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)

1762

#define RST_RESET_UART1_RESET_SET(x) (((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)

1763

#define RST_RESET_UART1_RESET_RESET 0x0 // 0

1764

#define RST_RESET_DDR_RESET_MSB 16

1765

#define RST_RESET_DDR_RESET_LSB 16

1766

#define RST_RESET_DDR_RESET_MASK 0x00010000

1767

#define RST_RESET_DDR_RESET_GET(x) (((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)

1768

#define RST_RESET_DDR_RESET_SET(x) (((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)

1769

#define RST_RESET_DDR_RESET_RESET 0x0 // 0

1770

#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB 15

1771

#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB 15

1772

#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK 0x00008000

1773

#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x) (((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)

1774

#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x) (((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)

1775

#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET 0x0 // 0

1776

#define RST_RESET_GE1_MAC_RESET_MSB 13

1777

#define RST_RESET_GE1_MAC_RESET_LSB 13

1778

#define RST_RESET_GE1_MAC_RESET_MASK 0x00002000

1779

#define RST_RESET_GE1_MAC_RESET_GET(x) (((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)

1780

#define RST_RESET_GE1_MAC_RESET_SET(x) (((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)

1781

#define RST_RESET_GE1_MAC_RESET_RESET 0x1 // 1

1782

#define RST_RESET_ETH_SGMII_ARESET_MSB 12

1783

#define RST_RESET_ETH_SGMII_ARESET_LSB 12

1784

#define RST_RESET_ETH_SGMII_ARESET_MASK 0x00001000

1785

#define RST_RESET_ETH_SGMII_ARESET_GET(x) (((x) & RST_RESET_ETH_SGMII_ARESET_MASK) >> RST_RESET_ETH_SGMII_ARESET_LSB)

1786

#define RST_RESET_ETH_SGMII_ARESET_SET(x) (((x) << RST_RESET_ETH_SGMII_ARESET_LSB) & RST_RESET_ETH_SGMII_ARESET_MASK)

1787

#define RST_RESET_ETH_SGMII_ARESET_RESET 0x1 // 1

1788

#define RST_RESET_USB_PHY_ARESET_MSB 11

1789

#define RST_RESET_USB_PHY_ARESET_LSB 11

1790

#define RST_RESET_USB_PHY_ARESET_MASK 0x00000800

1791

#define RST_RESET_USB_PHY_ARESET_GET(x) (((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)

1792

#define RST_RESET_USB_PHY_ARESET_SET(x) (((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)

1793

#define RST_RESET_USB_PHY_ARESET_RESET 0x1 // 1

1794

#define RST_RESET_HOST_DMA_INT_MSB 10

1795

#define RST_RESET_HOST_DMA_INT_LSB 10

1796

#define RST_RESET_HOST_DMA_INT_MASK 0x00000400

1797

#define RST_RESET_HOST_DMA_INT_GET(x) (((x) & RST_RESET_HOST_DMA_INT_MASK) >> RST_RESET_HOST_DMA_INT_LSB)

1798

#define RST_RESET_HOST_DMA_INT_SET(x) (((x) << RST_RESET_HOST_DMA_INT_LSB) & RST_RESET_HOST_DMA_INT_MASK)

1799

#define RST_RESET_HOST_DMA_INT_RESET 0x0 // 0

1800

#define RST_RESET_GE0_MAC_RESET_MSB 9

1801

#define RST_RESET_GE0_MAC_RESET_LSB 9

1802

#define RST_RESET_GE0_MAC_RESET_MASK 0x00000200

1803

#define RST_RESET_GE0_MAC_RESET_GET(x) (((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)

1804

#define RST_RESET_GE0_MAC_RESET_SET(x) (((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)

1805

#define RST_RESET_GE0_MAC_RESET_RESET 0x1 // 1

1806

#define RST_RESET_ETH_SGMII_RESET_MSB 8

1807

#define RST_RESET_ETH_SGMII_RESET_LSB 8

1808

#define RST_RESET_ETH_SGMII_RESET_MASK 0x00000100

1809

#define RST_RESET_ETH_SGMII_RESET_GET(x) (((x) & RST_RESET_ETH_SGMII_RESET_MASK) >> RST_RESET_ETH_SGMII_RESET_LSB)

1810

#define RST_RESET_ETH_SGMII_RESET_SET(x) (((x) << RST_RESET_ETH_SGMII_RESET_LSB) & RST_RESET_ETH_SGMII_RESET_MASK)

1811

#define RST_RESET_ETH_SGMII_RESET_RESET 0x1 // 1

1812

#define RST_RESET_PCIE_PHY_RESET_MSB 7

1813

#define RST_RESET_PCIE_PHY_RESET_LSB 7

1814

#define RST_RESET_PCIE_PHY_RESET_MASK 0x00000080

1815

#define RST_RESET_PCIE_PHY_RESET_GET(x) (((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)

1816

#define RST_RESET_PCIE_PHY_RESET_SET(x) (((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)

1817

#define RST_RESET_PCIE_PHY_RESET_RESET 0x1 // 1

1818

#define RST_RESET_PCIE_RESET_MSB 6

1819

#define RST_RESET_PCIE_RESET_LSB 6

1820

#define RST_RESET_PCIE_RESET_MASK 0x00000040

1821

#define RST_RESET_PCIE_RESET_GET(x) (((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)

1822

#define RST_RESET_PCIE_RESET_SET(x) (((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)

1823

#define RST_RESET_PCIE_RESET_RESET 0x1 // 1

1824

#define RST_RESET_USB_HOST_RESET_MSB 5

1825

#define RST_RESET_USB_HOST_RESET_LSB 5

1826

#define RST_RESET_USB_HOST_RESET_MASK 0x00000020

1827

#define RST_RESET_USB_HOST_RESET_GET(x) (((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)

1828

#define RST_RESET_USB_HOST_RESET_SET(x) (((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)

1829

#define RST_RESET_USB_HOST_RESET_RESET 0x1 // 1

1830

#define RST_RESET_USB_PHY_RESET_MSB 4

1831

#define RST_RESET_USB_PHY_RESET_LSB 4

1832

#define RST_RESET_USB_PHY_RESET_MASK 0x00000010

1833

#define RST_RESET_USB_PHY_RESET_GET(x) (((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)

1834

#define RST_RESET_USB_PHY_RESET_SET(x) (((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)

1835

#define RST_RESET_USB_PHY_RESET_RESET 0x1 // 1

1836

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB 3

1837

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB 3

1838

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK 0x00000008

1839

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)

1840

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)

1841

#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET 0x0 // 0

1842

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_MSB 2

1843

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_LSB 2

1844

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_MASK 0x00000004

1845

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_ANALOG_RESET_MASK) >> RST_RESET_ETH_SWITCH_ANALOG_RESET_LSB)

1846

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_ANALOG_RESET_LSB) & RST_RESET_ETH_SWITCH_ANALOG_RESET_MASK)

1847

#define RST_RESET_ETH_SWITCH_ANALOG_RESET_RESET 0x1 // 1

1848

#define RST_RESET_MBOX_RESET_MSB 1

1849

#define RST_RESET_MBOX_RESET_LSB 1

1850

#define RST_RESET_MBOX_RESET_MASK 0x00000002

1851

#define RST_RESET_MBOX_RESET_GET(x) (((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)

1852

#define RST_RESET_MBOX_RESET_SET(x) (((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)

1853

#define RST_RESET_MBOX_RESET_RESET 0x0 // 0

1854

#define RST_RESET_ETH_SWITCH_RESET_MSB 0

1855

#define RST_RESET_ETH_SWITCH_RESET_LSB 0

1856

#define RST_RESET_ETH_SWITCH_RESET_MASK 0x00000001

1857

#define RST_RESET_ETH_SWITCH_RESET_GET(x) (((x) & RST_RESET_ETH_SWITCH_RESET_MASK) >> RST_RESET_ETH_SWITCH_RESET_LSB)

1858

#define RST_RESET_ETH_SWITCH_RESET_SET(x) (((x) << RST_RESET_ETH_SWITCH_RESET_LSB) & RST_RESET_ETH_SWITCH_RESET_MASK)

1859

#define RST_RESET_ETH_SWITCH_RESET_RESET 0x1 // 1

1860

#define RST_RESET_ADDRESS 0x1806001c

1861

1862

#define RST_MISC2_PCIEEP_LINK_UP_MSB 30

1863

#define RST_MISC2_PCIEEP_LINK_UP_LSB 30

1864

#define RST_MISC2_PCIEEP_LINK_UP_MASK 0x40000000

1865

#define RST_MISC2_PCIEEP_LINK_UP_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_UP_MASK) >> RST_MISC2_PCIEEP_LINK_UP_LSB)

1866

#define RST_MISC2_PCIEEP_LINK_UP_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_UP_LSB) & RST_MISC2_PCIEEP_LINK_UP_MASK)

1867

#define RST_MISC2_PCIEEP_LINK_UP_RESET 0x0 // 0

1868

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MSB 29

1869

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB 29

1870

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK 0x20000000

1871

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_GET(x) (((x) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK) >> RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB)

1872

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_SET(x) (((x) << RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK)

1873

#define RST_MISC2_PCIEEP_CLKOBS2_SEL_RESET 0x0 // 0

1874

#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB 28

1875

#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB 28

1876

#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK 0x10000000

1877

#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x) (((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)

1878

#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x) (((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)

1879

#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET 0x0 // 0

1880

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MSB 27

1881

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB 27

1882

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK 0x08000000

1883

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_GET(x) (((x) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK) >> RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB)

1884

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_SET(x) (((x) << RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK)

1885

#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_RESET 0x0 // 0

1886

#define RST_MISC2_WOW_STATUS_MSB 26

1887

#define RST_MISC2_WOW_STATUS_LSB 26

1888

#define RST_MISC2_WOW_STATUS_MASK 0x04000000

1889

#define RST_MISC2_WOW_STATUS_GET(x) (((x) & RST_MISC2_WOW_STATUS_MASK) >> RST_MISC2_WOW_STATUS_LSB)

1890

#define RST_MISC2_WOW_STATUS_SET(x) (((x) << RST_MISC2_WOW_STATUS_LSB) & RST_MISC2_WOW_STATUS_MASK)

1891

#define RST_MISC2_WOW_STATUS_RESET 0x0 // 0

1892

#define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB 25

1893

#define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB 25

1894

#define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK 0x02000000

1895

#define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB)

1896

#define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK)

1897

#define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET 0x0 // 0

1898

#define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB 24

1899

#define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB 24

1900

#define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK 0x01000000

1901

#define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB)

1902

#define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK)

1903

#define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET 0x0 // 0

1904

#define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB 23

1905

#define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB 23

1906

#define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK 0x00800000

1907

#define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB)

1908

#define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK)

1909

#define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET 0x0 // 0

1910

#define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB 22

1911

#define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB 22

1912

#define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK 0x00400000

1913

#define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB)

1914

#define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK)

1915

#define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET 0x0 // 0

1916

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB 21

1917

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB 21

1918

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK 0x00200000

1919

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB)

1920

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK)

1921

#define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET 0x0 // 0

1922

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB 20

1923

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB 20

1924

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK 0x00100000

1925

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x) (((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB)

1926

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x) (((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK)

1927

#define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET 0x0 // 0

1928

#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB 18

1929

#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB 18

1930

#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK 0x00040000

1931

#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x) (((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)

1932

#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x) (((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)

1933

#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET 0x0 // 0

1934

#define RST_MISC2_PCIEEP_RST_INT_MSB 17

1935

#define RST_MISC2_PCIEEP_RST_INT_LSB 17

1936

#define RST_MISC2_PCIEEP_RST_INT_MASK 0x00020000

1937

#define RST_MISC2_PCIEEP_RST_INT_GET(x) (((x) & RST_MISC2_PCIEEP_RST_INT_MASK) >> RST_MISC2_PCIEEP_RST_INT_LSB)

1938

#define RST_MISC2_PCIEEP_RST_INT_SET(x) (((x) << RST_MISC2_PCIEEP_RST_INT_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK)

1939

#define RST_MISC2_PCIEEP_RST_INT_RESET 0x0 // 0

1940

#define RST_MISC2_HOST_RESET_INT_MSB 16

1941

#define RST_MISC2_HOST_RESET_INT_LSB 16

1942

#define RST_MISC2_HOST_RESET_INT_MASK 0x00010000

1943

#define RST_MISC2_HOST_RESET_INT_GET(x) (((x) & RST_MISC2_HOST_RESET_INT_MASK) >> RST_MISC2_HOST_RESET_INT_LSB)

1944

#define RST_MISC2_HOST_RESET_INT_SET(x) (((x) << RST_MISC2_HOST_RESET_INT_LSB) & RST_MISC2_HOST_RESET_INT_MASK)

1945

#define RST_MISC2_HOST_RESET_INT_RESET 0x0 // 0

1946

#define RST_MISC2_CPU_HOST_WA_MSB 15

1947

#define RST_MISC2_CPU_HOST_WA_LSB 15

1948

#define RST_MISC2_CPU_HOST_WA_MASK 0x00008000

1949

#define RST_MISC2_CPU_HOST_WA_GET(x) (((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB)

1950

#define RST_MISC2_CPU_HOST_WA_SET(x) (((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK)

1951

#define RST_MISC2_CPU_HOST_WA_RESET 0x0 // 0

1952

#define RST_MISC2_PERSTN_RCPHY2_MSB 14

1953

#define RST_MISC2_PERSTN_RCPHY2_LSB 14

1954

#define RST_MISC2_PERSTN_RCPHY2_MASK 0x00004000

1955

#define RST_MISC2_PERSTN_RCPHY2_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY2_MASK) >> RST_MISC2_PERSTN_RCPHY2_LSB)

1956

#define RST_MISC2_PERSTN_RCPHY2_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY2_LSB) & RST_MISC2_PERSTN_RCPHY2_MASK)

1957

#define RST_MISC2_PERSTN_RCPHY2_RESET 0x1 // 1

1958

#define RST_MISC2_PERSTN_RCPHY_MSB 13

1959

#define RST_MISC2_PERSTN_RCPHY_LSB 13

1960

#define RST_MISC2_PERSTN_RCPHY_MASK 0x00002000

1961

#define RST_MISC2_PERSTN_RCPHY_GET(x) (((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)

1962

#define RST_MISC2_PERSTN_RCPHY_SET(x) (((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)

1963

#define RST_MISC2_PERSTN_RCPHY_RESET 0x1 // 1

1964

#define RST_MISC2_PCIEEP_LTSSM_STATE_MSB 12

1965

#define RST_MISC2_PCIEEP_LTSSM_STATE_LSB 8

1966

#define RST_MISC2_PCIEEP_LTSSM_STATE_MASK 0x00001f00

1967

#define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x) (((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB)

1968

#define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x) (((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK)

1969

#define RST_MISC2_PCIEEP_LTSSM_STATE_RESET 0x0 // 0

1970

#define RST_MISC2_PCIEEP_LINK_STATUS_MSB 4

1971

#define RST_MISC2_PCIEEP_LINK_STATUS_LSB 4

1972

#define RST_MISC2_PCIEEP_LINK_STATUS_MASK 0x00000010

1973

#define RST_MISC2_PCIEEP_LINK_STATUS_GET(x) (((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB)

1974

#define RST_MISC2_PCIEEP_LINK_STATUS_SET(x) (((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK)

1975

#define RST_MISC2_PCIEEP_LINK_STATUS_RESET 0x0 // 0

1976

#define RST_MISC2_PCIEEP_RXDETECT_DONE_MSB 2

1977

#define RST_MISC2_PCIEEP_RXDETECT_DONE_LSB 2

1978

#define RST_MISC2_PCIEEP_RXDETECT_DONE_MASK 0x00000004

1979

#define RST_MISC2_PCIEEP_RXDETECT_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK) >> RST_MISC2_PCIEEP_RXDETECT_DONE_LSB)

1980

#define RST_MISC2_PCIEEP_RXDETECT_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_RXDETECT_DONE_LSB) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK)

1981

#define RST_MISC2_PCIEEP_RXDETECT_DONE_RESET 0x0 // 0

1982

#define RST_MISC2_PCIEEP_WOW_INT_MSB 1

1983

#define RST_MISC2_PCIEEP_WOW_INT_LSB 1

1984

#define RST_MISC2_PCIEEP_WOW_INT_MASK 0x00000002

1985

#define RST_MISC2_PCIEEP_WOW_INT_GET(x) (((x) & RST_MISC2_PCIEEP_WOW_INT_MASK) >> RST_MISC2_PCIEEP_WOW_INT_LSB)

1986

#define RST_MISC2_PCIEEP_WOW_INT_SET(x) (((x) << RST_MISC2_PCIEEP_WOW_INT_LSB) & RST_MISC2_PCIEEP_WOW_INT_MASK)

1987

#define RST_MISC2_PCIEEP_WOW_INT_RESET 0x0 // 0

1988

#define RST_MISC2_PCIEEP_CFG_DONE_MSB 0

1989

#define RST_MISC2_PCIEEP_CFG_DONE_LSB 0

1990

#define RST_MISC2_PCIEEP_CFG_DONE_MASK 0x00000001

1991

#define RST_MISC2_PCIEEP_CFG_DONE_GET(x) (((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB)

1992

#define RST_MISC2_PCIEEP_CFG_DONE_SET(x) (((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK)

1993

#define RST_MISC2_PCIEEP_CFG_DONE_RESET 0x0 // 0

1994

#define RST_MISC2_ADDRESS 0x180600b8

1995

1996

#define PCIE_APP_CFG_TYPE_MSB 21

1997

#define PCIE_APP_CFG_TYPE_LSB 20

1998

#define PCIE_APP_CFG_TYPE_MASK 0x00300000

1999

#define PCIE_APP_CFG_TYPE_GET(x) (((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)

2000

#define PCIE_APP_CFG_TYPE_SET(x) (((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)

2001

#define PCIE_APP_CFG_TYPE_RESET 0x0 // 0

2002

#define PCIE_APP_PCIE_BAR_MSN_MSB 19

2003

#define PCIE_APP_PCIE_BAR_MSN_LSB 16

2004

#define PCIE_APP_PCIE_BAR_MSN_MASK 0x000f0000

2005

#define PCIE_APP_PCIE_BAR_MSN_GET(x) (((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)

2006

#define PCIE_APP_PCIE_BAR_MSN_SET(x) (((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)

2007

#define PCIE_APP_PCIE_BAR_MSN_RESET 0x1 // 1

2008

#define PCIE_APP_CFG_BE_MSB 15

2009

#define PCIE_APP_CFG_BE_LSB 12

2010

#define PCIE_APP_CFG_BE_MASK 0x0000f000

2011

#define PCIE_APP_CFG_BE_GET(x) (((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)

2012

#define PCIE_APP_CFG_BE_SET(x) (((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)

2013

#define PCIE_APP_CFG_BE_RESET 0xf // 15

2014

#define PCIE_APP_SLV_RESP_ERR_MAP_MSB 11

2015

#define PCIE_APP_SLV_RESP_ERR_MAP_LSB 6

2016

#define PCIE_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0

2017

#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)

2018

#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)

2019

#define PCIE_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63

2020

#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB 5

2021

#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB 4

2022

#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030

2023

#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)

2024

#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)

2025

#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0

2026

#define PCIE_APP_INIT_RST_MSB 3

2027

#define PCIE_APP_INIT_RST_LSB 3

2028

#define PCIE_APP_INIT_RST_MASK 0x00000008

2029

#define PCIE_APP_INIT_RST_GET(x) (((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)

2030

#define PCIE_APP_INIT_RST_SET(x) (((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)

2031

#define PCIE_APP_INIT_RST_RESET 0x0 // 0

2032

#define PCIE_APP_PM_XMT_TURNOFF_MSB 2

2033

#define PCIE_APP_PM_XMT_TURNOFF_LSB 2

2034

#define PCIE_APP_PM_XMT_TURNOFF_MASK 0x00000004

2035

#define PCIE_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)

2036

#define PCIE_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)

2037

#define PCIE_APP_PM_XMT_TURNOFF_RESET 0x0 // 0

2038

#define PCIE_APP_UNLOCK_MSG_MSB 1

2039

#define PCIE_APP_UNLOCK_MSG_LSB 1

2040

#define PCIE_APP_UNLOCK_MSG_MASK 0x00000002

2041

#define PCIE_APP_UNLOCK_MSG_GET(x) (((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)

2042

#define PCIE_APP_UNLOCK_MSG_SET(x) (((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)

2043

#define PCIE_APP_UNLOCK_MSG_RESET 0x0 // 0

2044

#define PCIE_APP_LTSSM_ENABLE_MSB 0

2045

#define PCIE_APP_LTSSM_ENABLE_LSB 0

2046

#define PCIE_APP_LTSSM_ENABLE_MASK 0x00000001

2047

#define PCIE_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)

2048

#define PCIE_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)

2049

#define PCIE_APP_LTSSM_ENABLE_RESET 0x0 // 0

2050

#define PCIE_APP_ADDRESS 0x18280000

2051

2052

#define XTAL_TCXODET_MSB 31

2053

#define XTAL_TCXODET_LSB 31

2054

#define XTAL_TCXODET_MASK 0x80000000

2055

#define XTAL_TCXODET_GET(x) (((x) & XTAL_TCXODET_MASK) >> XTAL_TCXODET_LSB)

2056

#define XTAL_TCXODET_SET(x) (((x) << XTAL_TCXODET_LSB) & XTAL_TCXODET_MASK)

2057

#define XTAL_TCXODET_RESET 0x0 // 0

2058

#define XTAL_XTAL_CAPINDAC_MSB 30

2059

#define XTAL_XTAL_CAPINDAC_LSB 24

2060

#define XTAL_XTAL_CAPINDAC_MASK 0x7f000000

2061

#define XTAL_XTAL_CAPINDAC_GET(x) (((x) & XTAL_XTAL_CAPINDAC_MASK) >> XTAL_XTAL_CAPINDAC_LSB)

2062

#define XTAL_XTAL_CAPINDAC_SET(x) (((x) << XTAL_XTAL_CAPINDAC_LSB) & XTAL_XTAL_CAPINDAC_MASK)

2063

#define XTAL_XTAL_CAPINDAC_RESET 0x4b // 75

2064

#define XTAL_XTAL_CAPOUTDAC_MSB 23

2065

#define XTAL_XTAL_CAPOUTDAC_LSB 17

2066

#define XTAL_XTAL_CAPOUTDAC_MASK 0x00fe0000

2067

#define XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & XTAL_XTAL_CAPOUTDAC_MASK) >> XTAL_XTAL_CAPOUTDAC_LSB)

2068

#define XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << XTAL_XTAL_CAPOUTDAC_LSB) & XTAL_XTAL_CAPOUTDAC_MASK)

2069

#define XTAL_XTAL_CAPOUTDAC_RESET 0x4b // 75

2070

#define XTAL_XTAL_DRVSTR_MSB 16

2071

#define XTAL_XTAL_DRVSTR_LSB 15

2072

#define XTAL_XTAL_DRVSTR_MASK 0x00018000

2073

#define XTAL_XTAL_DRVSTR_GET(x) (((x) & XTAL_XTAL_DRVSTR_MASK) >> XTAL_XTAL_DRVSTR_LSB)

2074

#define XTAL_XTAL_DRVSTR_SET(x) (((x) << XTAL_XTAL_DRVSTR_LSB) & XTAL_XTAL_DRVSTR_MASK)

2075

#define XTAL_XTAL_DRVSTR_RESET 0x0 // 0

2076

#define XTAL_XTAL_SHORTXIN_MSB 14

2077

#define XTAL_XTAL_SHORTXIN_LSB 14

2078

#define XTAL_XTAL_SHORTXIN_MASK 0x00004000

2079

#define XTAL_XTAL_SHORTXIN_GET(x) (((x) & XTAL_XTAL_SHORTXIN_MASK) >> XTAL_XTAL_SHORTXIN_LSB)

2080

#define XTAL_XTAL_SHORTXIN_SET(x) (((x) << XTAL_XTAL_SHORTXIN_LSB) & XTAL_XTAL_SHORTXIN_MASK)

2081

#define XTAL_XTAL_SHORTXIN_RESET 0x0 // 0

2082

#define XTAL_XTAL_LOCALBIAS_MSB 13

2083

#define XTAL_XTAL_LOCALBIAS_LSB 13

2084

#define XTAL_XTAL_LOCALBIAS_MASK 0x00002000

2085

#define XTAL_XTAL_LOCALBIAS_GET(x) (((x) & XTAL_XTAL_LOCALBIAS_MASK) >> XTAL_XTAL_LOCALBIAS_LSB)

2086

#define XTAL_XTAL_LOCALBIAS_SET(x) (((x) << XTAL_XTAL_LOCALBIAS_LSB) & XTAL_XTAL_LOCALBIAS_MASK)

2087

#define XTAL_XTAL_LOCALBIAS_RESET 0x1 // 1

2088

#define XTAL_XTAL_PWDCLKD_MSB 12

2089

#define XTAL_XTAL_PWDCLKD_LSB 12

2090

#define XTAL_XTAL_PWDCLKD_MASK 0x00001000

2091

#define XTAL_XTAL_PWDCLKD_GET(x) (((x) & XTAL_XTAL_PWDCLKD_MASK) >> XTAL_XTAL_PWDCLKD_LSB)

2092

#define XTAL_XTAL_PWDCLKD_SET(x) (((x) << XTAL_XTAL_PWDCLKD_LSB) & XTAL_XTAL_PWDCLKD_MASK)

2093

#define XTAL_XTAL_PWDCLKD_RESET 0x0 // 0

2094

#define XTAL_XTAL_BIAS2X_MSB 11

2095

#define XTAL_XTAL_BIAS2X_LSB 11

2096

#define XTAL_XTAL_BIAS2X_MASK 0x00000800

2097

#define XTAL_XTAL_BIAS2X_GET(x) (((x) & XTAL_XTAL_BIAS2X_MASK) >> XTAL_XTAL_BIAS2X_LSB)

2098

#define XTAL_XTAL_BIAS2X_SET(x) (((x) << XTAL_XTAL_BIAS2X_LSB) & XTAL_XTAL_BIAS2X_MASK)

2099

#define XTAL_XTAL_BIAS2X_RESET 0x1 // 1

2100

#define XTAL_XTAL_LBIAS2X_MSB 10

2101

#define XTAL_XTAL_LBIAS2X_LSB 10

2102

#define XTAL_XTAL_LBIAS2X_MASK 0x00000400

2103

#define XTAL_XTAL_LBIAS2X_GET(x) (((x) & XTAL_XTAL_LBIAS2X_MASK) >> XTAL_XTAL_LBIAS2X_LSB)

2104

#define XTAL_XTAL_LBIAS2X_SET(x) (((x) << XTAL_XTAL_LBIAS2X_LSB) & XTAL_XTAL_LBIAS2X_MASK)

2105

#define XTAL_XTAL_LBIAS2X_RESET 0x1 // 1

2106

//#define XTAL_XTAL_ATBVREG_MSB 9

2107

//#define XTAL_XTAL_ATBVREG_LSB 9

2108

//#define XTAL_XTAL_ATBVREG_MASK 0x00000200

2109

//#define XTAL_XTAL_ATBVREG_GET(x) (((x) & XTAL_XTAL_ATBVREG_MASK) >> XTAL_XTAL_ATBVREG_LSB)

2110

//#define XTAL_XTAL_ATBVREG_SET(x) (((x) << XTAL_XTAL_ATBVREG_LSB) & XTAL_XTAL_ATBVREG_MASK)

2111

//#define XTAL_XTAL_ATBVREG_RESET 0x0 // 0

2112

#define XTAL_XTAL_SELVREG_MSB 9

2113

#define XTAL_XTAL_SELVREG_LSB 9

2114

#define XTAL_XTAL_SELVREG_MASK 0x00000200

2115

#define XTAL_XTAL_SELVREG_GET(x) (((x) & XTAL_XTAL_SELVREG_MASK) >> XTAL_XTAL_SELVREG_LSB)

2116

#define XTAL_XTAL_SELVREG_SET(x) (((x) << XTAL_XTAL_SELVREG_LSB) & XTAL_XTAL_SELVREG_MASK)

2117

#define XTAL_XTAL_SELVREG_RESET 0x0 // 0

2118

#define XTAL_XTAL_OSCON_MSB 8

2119

#define XTAL_XTAL_OSCON_LSB 8

2120

#define XTAL_XTAL_OSCON_MASK 0x00000100

2121

#define XTAL_XTAL_OSCON_GET(x) (((x) & XTAL_XTAL_OSCON_MASK) >> XTAL_XTAL_OSCON_LSB)

2122

#define XTAL_XTAL_OSCON_SET(x) (((x) << XTAL_XTAL_OSCON_LSB) & XTAL_XTAL_OSCON_MASK)

2123

#define XTAL_XTAL_OSCON_RESET 0x1 // 1

2124

#define XTAL_XTAL_PWDCLKIN_MSB 7

2125

#define XTAL_XTAL_PWDCLKIN_LSB 7

2126

#define XTAL_XTAL_PWDCLKIN_MASK 0x00000080

2127

#define XTAL_XTAL_PWDCLKIN_GET(x) (((x) & XTAL_XTAL_PWDCLKIN_MASK) >> XTAL_XTAL_PWDCLKIN_LSB)

2128

#define XTAL_XTAL_PWDCLKIN_SET(x) (((x) << XTAL_XTAL_PWDCLKIN_LSB) & XTAL_XTAL_PWDCLKIN_MASK)

2129

#define XTAL_XTAL_PWDCLKIN_RESET 0x0 // 0

2130

#define XTAL_LOCAL_XTAL_MSB 6

2131

#define XTAL_LOCAL_XTAL_LSB 6

2132

#define XTAL_LOCAL_XTAL_MASK 0x00000040

2133

#define XTAL_LOCAL_XTAL_GET(x) (((x) & XTAL_LOCAL_XTAL_MASK) >> XTAL_LOCAL_XTAL_LSB)

2134

#define XTAL_LOCAL_XTAL_SET(x) (((x) << XTAL_LOCAL_XTAL_LSB) & XTAL_LOCAL_XTAL_MASK)

2135

#define XTAL_LOCAL_XTAL_RESET 0x0 // 0

2136

#define XTAL_PWD_SWREGCLK_MSB 5

2137

#define XTAL_PWD_SWREGCLK_LSB 5

2138

#define XTAL_PWD_SWREGCLK_MASK 0x00000020

2139

#define XTAL_PWD_SWREGCLK_GET(x) (((x) & XTAL_PWD_SWREGCLK_MASK) >> XTAL_PWD_SWREGCLK_LSB)

2140

#define XTAL_PWD_SWREGCLK_SET(x) (((x) << XTAL_PWD_SWREGCLK_LSB) & XTAL_PWD_SWREGCLK_MASK)

2141

#define XTAL_PWD_SWREGCLK_RESET 0x0 // 0

2142

#define XTAL_LOCAL_EXT_CLK_OUT_EN_MSB 4

2143

#define XTAL_LOCAL_EXT_CLK_OUT_EN_LSB 4

2144

#define XTAL_LOCAL_EXT_CLK_OUT_EN_MASK 0x00000010

2145

#define XTAL_LOCAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK) >> XTAL_LOCAL_EXT_CLK_OUT_EN_LSB)

2146

#define XTAL_LOCAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_LOCAL_EXT_CLK_OUT_EN_LSB) & XTAL_LOCAL_EXT_CLK_OUT_EN_MASK)

2147

#define XTAL_LOCAL_EXT_CLK_OUT_EN_RESET 0x0 // 0

2148

#define XTAL_EXT_CLK_OUT_EN_MSB 3

2149

#define XTAL_EXT_CLK_OUT_EN_LSB 3

2150

#define XTAL_EXT_CLK_OUT_EN_MASK 0x00000008

2151

#define XTAL_EXT_CLK_OUT_EN_GET(x) (((x) & XTAL_EXT_CLK_OUT_EN_MASK) >> XTAL_EXT_CLK_OUT_EN_LSB)

2152

#define XTAL_EXT_CLK_OUT_EN_SET(x) (((x) << XTAL_EXT_CLK_OUT_EN_LSB) & XTAL_EXT_CLK_OUT_EN_MASK)

2153

#define XTAL_EXT_CLK_OUT_EN_RESET 0x0 // 0

2154

#define XTAL_XTAL_SVREG_MSB 2

2155

#define XTAL_XTAL_SVREG_LSB 2

2156

#define XTAL_XTAL_SVREG_MASK 0x00000004

2157

#define XTAL_XTAL_SVREG_GET(x) (((x) & XTAL_XTAL_SVREG_MASK) >> XTAL_XTAL_SVREG_LSB)

2158

#define XTAL_XTAL_SVREG_SET(x) (((x) << XTAL_XTAL_SVREG_LSB) & XTAL_XTAL_SVREG_MASK)

2159

#define XTAL_XTAL_SVREG_RESET 0x0 // 0

2160

#define XTAL_RBK_UDSEL_MSB 1

2161

#define XTAL_RBK_UDSEL_LSB 1

2162

#define XTAL_RBK_UDSEL_MASK 0x00000002

2163

#define XTAL_RBK_UDSEL_GET(x) (((x) & XTAL_RBK_UDSEL_MASK) >> XTAL_RBK_UDSEL_LSB)

2164

#define XTAL_RBK_UDSEL_SET(x) (((x) << XTAL_RBK_UDSEL_LSB) & XTAL_RBK_UDSEL_MASK)

2165

#define XTAL_RBK_UDSEL_RESET 0x0 // 0

2166

#define XTAL_SPARE_MSB 0

2167

#define XTAL_SPARE_LSB 0

2168

#define XTAL_SPARE_MASK 0x00000001

2169

#define XTAL_SPARE_GET(x) (((x) & XTAL_SPARE_MASK) >> XTAL_SPARE_LSB)

2170

#define XTAL_SPARE_SET(x) (((x) << XTAL_SPARE_LSB) & XTAL_SPARE_MASK)

2171

#define XTAL_SPARE_RESET 0x0 // 0

2172

#define XTAL_ADDRESS 0x181162c0

2173

2174

#define XTAL2_TDC_COUNT_MSB 31

2175

#define XTAL2_TDC_COUNT_LSB 26

2176

#define XTAL2_TDC_COUNT_MASK 0xfc000000

2177

#define XTAL2_TDC_COUNT_GET(x) (((x) & XTAL2_TDC_COUNT_MASK) >> XTAL2_TDC_COUNT_LSB)

2178

#define XTAL2_TDC_COUNT_SET(x) (((x) << XTAL2_TDC_COUNT_LSB) & XTAL2_TDC_COUNT_MASK)

2179

#define XTAL2_TDC_COUNT_RESET 0x0 // 0

2180

#define XTAL2_TDC_PH_COUNT_MSB 25

2181

#define XTAL2_TDC_PH_COUNT_LSB 21

2182

#define XTAL2_TDC_PH_COUNT_MASK 0x3e00000

2183

#define XTAL2_TDC_PH_COUNT_GET(x) (((x) & XTAL2_TDC_PH_COUNT_MASK) >> XTAL2_TDC_PH_COUNT_LSB)

2184

#define XTAL2_TDC_PH_COUNT_SET(x) (((x) << XTAL2_TDC_PH_COUNT_LSB) & XTAL2_TDC_PH_COUNT_MASK)

2185

#define XTAL2_TDC_PH_COUNT_RESET 0x0 // 0

2186

#define XTAL2_DUTY_UP_MSB 20

2187

#define XTAL2_DUTY_UP_LSB 16

2188

#define XTAL2_DUTY_UP_MASK 0x1f0000

2189

#define XTAL2_DUTY_UP_GET(x) (((x) & XTAL2_DUTY_UP_MASK) >> XTAL2_DUTY_UP_LSB)

2190

#define XTAL2_DUTY_UP_SET(x) (((x) << XTAL2_DUTY_UP_LSB) & XTAL2_DUTY_UP_MASK)

2191

#define XTAL2_DUTY_UP_RESET 0x0 // 0

2192

#define XTAL2_DUTY_DN_MSB 15

2193

#define XTAL2_DUTY_DN_LSB 11

2194

#define XTAL2_DUTY_DN_MASK 0xf800

2195

#define XTAL2_DUTY_DN_GET(x) (((x) & XTAL2_DUTY_DN_MASK) >> XTAL2_DUTY_DN_LSB)

2196

#define XTAL2_DUTY_DN_SET(x) (((x) << XTAL2_DUTY_DN_LSB) & XTAL2_DUTY_DN_MASK)

2197

#define XTAL2_DUTY_DN_RESET 0x0 // 0

2198

#define XTAL2_DCA_BYPASS_MSB 10

2199

#define XTAL2_DCA_BYPASS_LSB 10

2200

#define XTAL2_DCA_BYPASS_MASK 0x400

2201

#define XTAL2_DCA_BYPASS_GET(x) (((x) & XTAL2_DCA_BYPASS_MASK) >> XTAL2_DCA_BYPASS_LSB)

2202

#define XTAL2_DCA_BYPASS_SET(x) (((x) << XTAL2_DCA_BYPASS_LSB) & XTAL2_DCA_BYPASS_MASK)

2203

#define XTAL2_DCA_BYPASS_RESET 0x1 // 1

2204

#define XTAL2_DCA_SWCAL_MSB 9

2205

#define XTAL2_DCA_SWCAL_LSB 9

2206

#define XTAL2_DCA_SWCAL_MASK 0x200

2207

#define XTAL2_DCA_SWCAL_GET(x) (((x) & XTAL2_DCA_SWCAL_MASK) >> XTAL2_DCA_SWCAL_LSB)

2208

#define XTAL2_DCA_SWCAL_SET(x) (((x) << XTAL2_DCA_SWCAL_LSB) & XTAL2_DCA_SWCAL_MASK)

2209

#define XTAL2_DCA_SWCAL_RESET 0x0 // 0

2210

#define XTAL2_FSM_UD_HOLD_MSB 8

2211

#define XTAL2_FSM_UD_HOLD_LSB 8

2212

#define XTAL2_FSM_UD_HOLD_MASK 0x100

2213

#define XTAL2_FSM_UD_HOLD_GET(x) (((x) & XTAL2_FSM_UD_HOLD_MASK) >> XTAL2_FSM_UD_HOLD_LSB)

2214

#define XTAL2_FSM_UD_HOLD_SET(x) (((x) << XTAL2_FSM_UD_HOLD_LSB) & XTAL2_FSM_UD_HOLD_MASK)

2215

#define XTAL2_FSM_UD_HOLD_RESET 0x0 // 0

2216

#define XTAL2_FSM_START_L_MSB 7

2217

#define XTAL2_FSM_START_L_LSB 7

2218

#define XTAL2_FSM_START_L_MASK 0x80

2219

#define XTAL2_FSM_START_L_GET(x) (((x) & XTAL2_FSM_START_L_MASK) >> XTAL2_FSM_START_L_LSB)

2220

#define XTAL2_FSM_START_L_SET(x) (((x) << XTAL2_FSM_START_L_LSB) & XTAL2_FSM_START_L_MASK)

2221

#define XTAL2_FSM_START_L_RESET 0x1 // 1

2222

#define XTAL2_FSM_DN_READBACK_MSB 6

2223

#define XTAL2_FSM_DN_READBACK_LSB 2

2224

#define XTAL2_FSM_DN_READBACK_MASK 0x7c

2225

#define XTAL2_FSM_DN_READBACK_GET(x) (((x) & XTAL2_FSM_DN_READBACK_MASK) >> XTAL2_FSM_DN_READBACK_LSB)

2226

#define XTAL2_FSM_DN_READBACK_SET(x) (((x) << XTAL2_FSM_DN_READBACK_LSB) & XTAL2_FSM_DN_READBACK_MASK)

2227

#define XTAL2_FSM_DN_READBACK_RESET 0x0 // 0

2228

#define XTAL2_TDC_SAT_FLAG_MSB 1

2229

#define XTAL2_TDC_SAT_FLAG_LSB 1

2230

#define XTAL2_TDC_SAT_FLAG_MASK 0x2

2231

#define XTAL2_TDC_SAT_FLAG_GET(x) (((x) & XTAL2_TDC_SAT_FLAG_MASK) >> XTAL2_TDC_SAT_FLAG_LSB)

2232

#define XTAL2_TDC_SAT_FLAG_SET(x) (((x) << XTAL2_TDC_SAT_FLAG_LSB) & XTAL2_TDC_SAT_FLAG_MASK)

2233

#define XTAL2_TDC_SAT_FLAG_RESET 0x0 // 0

2234

#define XTAL2_FSM_READY_MSB 0

2235

#define XTAL2_FSM_READY_LSB 0

2236

#define XTAL2_FSM_READY_MASK 0x1

2237

#define XTAL2_FSM_READY_GET(x) (((x) & XTAL2_FSM_READY_MASK) >> XTAL2_FSM_READY_LSB)

2238

#define XTAL2_FSM_READY_SET(x) (((x) << XTAL2_FSM_READY_LSB) & XTAL2_FSM_READY_MASK)

2239

#define XTAL2_FSM_READY_RESET 0x0 // 0

2240

#define XTAL2_ADDRESS 0x181162c4

2241

2242

#define XTAL3_FSM_UP_READBACK_MSB 31

2243

#define XTAL3_FSM_UP_READBACK_LSB 27

2244

#define XTAL3_FSM_UP_READBACK_MASK 0xf8000000

2245

#define XTAL3_FSM_UP_READBACK_GET(x) (((x) & XTAL3_FSM_UP_READBACK_MASK) >> XTAL3_FSM_UP_READBACK_LSB)

2246

#define XTAL3_FSM_UP_READBACK_SET(x) (((x) << XTAL3_FSM_UP_READBACK_LSB) & XTAL3_FSM_UP_READBACK_MASK)

2247

#define XTAL3_FSM_UP_READBACK_RESET 0x0 // 0

2248

#define XTAL3_EVAL_LENGTH_MSB 26

2249

#define XTAL3_EVAL_LENGTH_LSB 16

2250

#define XTAL3_EVAL_LENGTH_MASK 0x7ff0000

2251

#define XTAL3_EVAL_LENGTH_GET(x) (((x) & XTAL3_EVAL_LENGTH_MASK) >> XTAL3_EVAL_LENGTH_LSB)

2252

#define XTAL3_EVAL_LENGTH_SET(x) (((x) << XTAL3_EVAL_LENGTH_LSB) & XTAL3_EVAL_LENGTH_MASK)

2253

#define XTAL3_EVAL_LENGTH_RESET 0x400 // 0x400

2254

#define XTAL3_TDC_ERROR_FLAG_MSB 15

2255

#define XTAL3_TDC_ERROR_FLAG_LSB 15

2256

#define XTAL3_TDC_ERROR_FLAG_MASK 0x8000

2257

#define XTAL3_TDC_ERROR_FLAG_GET(x) (((x) & XTAL3_TDC_ERROR_FLAG_MASK) >> XTAL3_TDC_ERROR_FLAG_LSB)

2258

#define XTAL3_TDC_ERROR_FLAG_SET(x) (((x) << XTAL3_TDC_ERROR_FLAG_LSB) & XTAL3_TDC_ERROR_FLAG_MASK)

2259

#define XTAL3_TDC_ERROR_FLAG_RESET 0x0 // 0

2260

#define XTAL3_HARMONIC_NUMBER_MSB 14

2261

#define XTAL3_HARMONIC_NUMBER_LSB 2

2262

#define XTAL3_HARMONIC_NUMBER_MASK 0x7ffc

2263

#define XTAL3_HARMONIC_NUMBER_GET(x) (((x) & XTAL3_HARMONIC_NUMBER_MASK) >> XTAL3_HARMONIC_NUMBER_LSB)

2264

#define XTAL3_HARMONIC_NUMBER_SET(x) (((x) << XTAL3_HARMONIC_NUMBER_LSB) & XTAL3_HARMONIC_NUMBER_MASK)

2265

#define XTAL3_HARMONIC_NUMBER_RESET 0x51 // 0x51

2266

#define XTAL3_SPARE_MSB 1

2267

#define XTAL3_SPARE_LSB 0

2268

#define XTAL3_SPARE_MASK 0x3

2269

#define XTAL3_SPARE_GET(x) (((x) & XTAL3_SPARE_MASK) >> XTAL3_SPARE_LSB)

2270

#define XTAL3_SPARE_SET(x) (((x) << XTAL3_SPARE_LSB) & XTAL3_SPARE_MASK)

2271

#define XTAL3_SPARE_RESET 0x0 // 0x0

2272

#define XTAL3_ADDRESS 0x181162c8

2273

2274

2275

#define RST_REVISION_ID_ADDRESS 0x18060090

2276

#define is_drqfn() (!(ath_reg_rd(RST_REVISION_ID_ADDRESS) & 0x1000))

2277

2278

2279

#define RST_BOOTSTRAP_DDR_WIDTH_GET(x) 0 //0: DDR WIDTH 16, Dragonfly only support 16bit

2280

2281

#if 1 //This define is not exist in 956x, keep it just for pci common code. Need to modify

2282

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MSB 6

2283

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB 6

2284

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK 0x00000040

2285

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_GET(x) (((x) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK) >> RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB)

2286

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_SET(x) (((x) << RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)

2287

#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_RESET 0x0 // 0

2288

#endif

2289

2290

#define RST_BOOTSTRAP_RES0_MSB 15

2291

#define RST_BOOTSTRAP_RES0_LSB 13

2292

#define RST_BOOTSTRAP_RES0_MASK 0x0000e000

2293

#define RST_BOOTSTRAP_RES0_GET(x) (((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)

2294

#define RST_BOOTSTRAP_RES0_SET(x) (((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)

2295

#define RST_BOOTSTRAP_RES0_RESET 0x0 // 0

2296

#define RST_BOOTSTRAP_SW_OPTION2_MSB 12

2297

#define RST_BOOTSTRAP_SW_OPTION2_LSB 12

2298

#define RST_BOOTSTRAP_SW_OPTION2_MASK 0x00001000

2299

#define RST_BOOTSTRAP_SW_OPTION2_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)

2300

#define RST_BOOTSTRAP_SW_OPTION2_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)

2301

#define RST_BOOTSTRAP_SW_OPTION2_RESET 0x0 // 0

2302

#define RST_BOOTSTRAP_SW_OPTION1_MSB 11

2303

#define RST_BOOTSTRAP_SW_OPTION1_LSB 11

2304

#define RST_BOOTSTRAP_SW_OPTION1_MASK 0x00000800

2305

#define RST_BOOTSTRAP_SW_OPTION1_GET(x) (((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)

2306

#define RST_BOOTSTRAP_SW_OPTION1_SET(x) (((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)

2307

#define RST_BOOTSTRAP_SW_OPTION1_RESET 0x0 // 0

2308

#define RST_BOOTSTRAP_TESTROM_DISABLE_MSB 10

2309

#define RST_BOOTSTRAP_TESTROM_DISABLE_LSB 10

2310

#define RST_BOOTSTRAP_TESTROM_DISABLE_MASK 0x00000400

2311

#define RST_BOOTSTRAP_TESTROM_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK) >> RST_BOOTSTRAP_TESTROM_DISABLE_LSB)

2312

#define RST_BOOTSTRAP_TESTROM_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_TESTROM_DISABLE_LSB) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK)

2313

#define RST_BOOTSTRAP_TESTROM_DISABLE_RESET 0x1 // 1

2314

#define RST_BOOTSTRAP_SRIF_ENABLE_MSB 6

2315

#define RST_BOOTSTRAP_SRIF_ENABLE_LSB 6

2316

#define RST_BOOTSTRAP_SRIF_ENABLE_MASK 0x00000040

2317

#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x) (((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)

2318

#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x) (((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)

2319

#define RST_BOOTSTRAP_SRIF_ENABLE_RESET 0x0 // 0

2320

#define RST_BOOTSTRAP_CHAIN2_DISABLE_MSB 5

2321

#define RST_BOOTSTRAP_CHAIN2_DISABLE_LSB 5

2322

#define RST_BOOTSTRAP_CHAIN2_DISABLE_MASK 0x00000020

2323

#define RST_BOOTSTRAP_CHAIN2_DISABLE_GET(x) (((x) & RST_BOOTSTRAP_CHAIN2_DISABLE_MASK) >> RST_BOOTSTRAP_CHAIN2_DISABLE_LSB)

2324

#define RST_BOOTSTRAP_CHAIN2_DISABLE_SET(x) (((x) << RST_BOOTSTRAP_CHAIN2_DISABLE_LSB) & RST_BOOTSTRAP_CHAIN2_DISABLE_MASK)

2325

#define RST_BOOTSTRAP_CHAIN2_DISABLE_RESET 0x0 // 0

2326

#define RST_BOOTSTRAP_PKG_SEL_MSB 4

2327

#define RST_BOOTSTRAP_PKG_SEL_LSB 4

2328

#define RST_BOOTSTRAP_PKG_SEL_MASK 0x00000010

2329

#define RST_BOOTSTRAP_PKG_SEL_GET(x) (((x) & RST_BOOTSTRAP_PKG_SEL_MASK) >> RST_BOOTSTRAP_PKG_SEL_LSB)

2330

#define RST_BOOTSTRAP_PKG_SEL_SET(x) (((x) << RST_BOOTSTRAP_PKG_SEL_LSB) & RST_BOOTSTRAP_PKG_SEL_MASK)

2331

#define RST_BOOTSTRAP_PKG_SEL_RESET 0x0 // 0

2332

#define RST_BOOTSTRAP_JTAG_MODE_MSB 3

2333

#define RST_BOOTSTRAP_JTAG_MODE_LSB 3

2334

#define RST_BOOTSTRAP_JTAG_MODE_MASK 0x00000008

2335

#define RST_BOOTSTRAP_JTAG_MODE_GET(x) (((x) & RST_BOOTSTRAP_JTAG_MODE_MASK) >> RST_BOOTSTRAP_JTAG_MODE_LSB)

2336

#define RST_BOOTSTRAP_JTAG_MODE_SET(x) (((x) << RST_BOOTSTRAP_JTAG_MODE_LSB) & RST_BOOTSTRAP_JTAG_MODE_MASK)

2337

#define RST_BOOTSTRAP_JTAG_MODE_RESET 0x1 // 1

2338

#define RST_BOOTSTRAP_REF_CLK_MSB 2

2339

#define RST_BOOTSTRAP_REF_CLK_LSB 2

2340

#define RST_BOOTSTRAP_REF_CLK_MASK 0x00000004

2341

#define RST_BOOTSTRAP_REF_CLK_GET(x) (((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)

2342

#define RST_BOOTSTRAP_REF_CLK_SET(x) (((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)

2343

#define RST_BOOTSTRAP_REF_CLK_RESET 0x0 // 0

2344

#define RST_BOOTSTRAP_E_SWITCH_EN_MSB 1

2345

#define RST_BOOTSTRAP_E_SWITCH_EN_LSB 1

2346

#define RST_BOOTSTRAP_E_SWITCH_EN_MASK 0x00000002

2347

#define RST_BOOTSTRAP_E_SWITCH_EN_GET(x) (((x) & RST_BOOTSTRAP_E_SWITCH_EN_MASK) >> RST_BOOTSTRAP_E_SWITCH_EN_LSB)

2348

#define RST_BOOTSTRAP_E_SWITCH_EN_SET(x) (((x) << RST_BOOTSTRAP_E_SWITCH_EN_LSB) & RST_BOOTSTRAP_E_SWITCH_EN_MASK)

2349

#define RST_BOOTSTRAP_E_SWITCH_EN_RESET 0x0 // 0

2350

#define RST_BOOTSTRAP_DDR_SELECT_MSB 0

2351

#define RST_BOOTSTRAP_DDR_SELECT_LSB 0

2352

#define RST_BOOTSTRAP_DDR_SELECT_MASK 0x00000001

2353

#define RST_BOOTSTRAP_DDR_SELECT_GET(x) (((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)

2354

#define RST_BOOTSTRAP_DDR_SELECT_SET(x) (((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)

2355

#define RST_BOOTSTRAP_DDR_SELECT_RESET 0x0 // 0

2356

#define RST_BOOTSTRAP_ADDRESS 0x180600b0

2357

2358

#define GPIO_OE_ADDRESS 0x18040000

2359

#define GPIO_OUT_ADDRESS 0x18040008

2360

#define GPIO_SPARE_ADDRESS 0x18040028

2361

2362

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB 31

2363

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB 24

2364

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK 0xff000000

2365

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB)

2366

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK)

2367

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET 0x0 // 0

2368

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB 23

2369

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB 16

2370

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK 0x00ff0000

2371

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB)

2372

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK)

2373

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET 0x0 // 0

2374

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB 15

2375

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB 8

2376

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK 0x0000ff00

2377

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB)

2378

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK)

2379

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET 0x0 // 0

2380

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB 7

2381

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB 0

2382

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK 0x000000ff

2383

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x) (((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB)

2384

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x) (((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK)

2385

#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET 0x0 // 0

2386

#define GPIO_OUT_FUNCTION0_ADDRESS 0x1804002c

2387

2388

2389

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB 31

2390

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB 24

2391

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK 0xff000000

2392

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)

2393

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)

2394

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET 0xb // 11

2395

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB 23

2396

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB 16

2397

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK 0x00ff0000

2398

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)

2399

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)

2400

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET 0xa // 10

2401

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB 15

2402

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB 8

2403

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK 0x0000ff00

2404

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)

2405

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)

2406

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET 0x9 // 9

2407

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB 7

2408

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB 0

2409

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK 0x000000ff

2410

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x) (((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)

2411

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x) (((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)

2412

#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_RESET 0x14 // 20

2413

#define GPIO_OUT_FUNCTION1_ADDRESS 0x18040030

2414

2415

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB 31

2416

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB 24

2417

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK 0xff000000

2418

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)

2419

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)

2420

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET 0x0 // 0

2421

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB 23

2422

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB 16

2423

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK 0x00ff0000

2424

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)

2425

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)

2426

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET 0x0 // 0

2427

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB 15

2428

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB 8

2429

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK 0x0000ff00

2430

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)

2431

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)

2432

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET 0x0 // 0

2433

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB 7

2434

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB 0

2435

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK 0x000000ff

2436

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x) (((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)

2437

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x) (((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)

2438

#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET 0x0 // 0

2439

#define GPIO_OUT_FUNCTION2_ADDRESS 0x18040034

2440

2441

#define GPIO_IN_ENABLE0_UART_SIN_MSB 15

2442

#define GPIO_IN_ENABLE0_UART_SIN_LSB 8

2443

#define GPIO_IN_ENABLE0_UART_SIN_MASK 0x0000ff00

2444

#define GPIO_IN_ENABLE0_UART_SIN_GET(x) (((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)

2445

#define GPIO_IN_ENABLE0_UART_SIN_SET(x) (((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)

2446

#define GPIO_IN_ENABLE0_UART_SIN_RESET 0x80 // 128

2447

#define GPIO_IN_ENABLE0_ADDRESS 0x18040044

2448

2449

#define GPIO_IN_ENABLE3_MII_GE1_MDI_MSB 23

2450

#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB 16

2451

#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK 0x00ff0000

2452

#define GPIO_IN_ENABLE3_MII_GE1_MDI_GET(x) (((x) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) >> GPIO_IN_ENABLE3_MII_GE1_MDI_LSB)

2453

#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x) (((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)

2454

#define GPIO_IN_ENABLE3_MII_GE1_MDI_RESET 0x80 // 128

2455

#define GPIO_IN_ENABLE3_ADDRESS 0x18040050

2456

2457

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB 31

2458

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB 24

2459

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK 0xff000000

2460

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB)

2461

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK)

2462

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET 0x0 // 0

2463

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB 23

2464

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB 16

2465

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK 0x00ff0000

2466

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB)

2467

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK)

2468

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET 0x0 // 0

2469

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB 15

2470

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB 8

2471

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK 0x0000ff00

2472

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB)

2473

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK)

2474

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET 0x0 // 0

2475

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB 7

2476

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB 0

2477

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK 0x000000ff

2478

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x) (((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB)

2479

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x) (((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK)

2480

#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET 0x0 // 0

2481

#define GPIO_OUT_FUNCTION3_ADDRESS 0x18040038

2482

2483

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MSB 31

2484

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB 24

2485

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK 0xff000000

2486

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB)

2487

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)

2488

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_RESET 0x0 // 0

2489

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MSB 23

2490

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB 16

2491

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK 0x00ff0000

2492

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB)

2493

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK)

2494

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_RESET 0x0 // 0

2495

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB 15

2496

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB 8

2497

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK 0x0000ff00

2498

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)

2499

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)

2500

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET 0x0 // 0

2501

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB 7

2502

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB 0

2503

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK 0x000000ff

2504

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)

2505

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)

2506

#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET 0x0 // 0

2507

#define GPIO_OUT_FUNCTION4_ADDRESS 0x1804003c

2508

2509

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MSB 23

2510

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_LSB 16

2511

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK 0x00ff0000

2512

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB)

2513

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK)

2514

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_RESET 0x0 // 0

2515

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MSB 15

2516

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_LSB 8

2517

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MASK 0x0000ff00

2518

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)

2519

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)

2520

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_RESET 0x0 // 0

2521

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MSB 7

2522

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_LSB 0

2523

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK 0x000000ff

2524

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_GET(x) (((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)

2525

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(x) (((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)

2526

#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_RESET 0x0 // 0

2527

#define GPIO_OUT_FUNCTION5_ADDRESS 0x18040040

2528

2529

2530

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_MSB 15

2531

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_LSB 15

2532

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_MASK 0x00008000

2533

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_GET(x) (((x) & GPIO_FUNCTION_DISABLE_XPA_XLNA_MASK) >> GPIO_FUNCTION_DISABLE_XPA_XLNA_LSB)

2534

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_SET(x) (((x) << GPIO_FUNCTION_DISABLE_XPA_XLNA_LSB) & GPIO_FUNCTION_DISABLE_XPA_XLNA_MASK)

2535

#define GPIO_FUNCTION_DISABLE_XPA_XLNA_RESET 0x0 // 0

2536

#define GPIO_FUNCTION_DISABLE_SWCOM_MSB 14

2537

#define GPIO_FUNCTION_DISABLE_SWCOM_LSB 14

2538

#define GPIO_FUNCTION_DISABLE_SWCOM_MASK 0x00004000

2539

#define GPIO_FUNCTION_DISABLE_SWCOM_GET(x) (((x) & GPIO_FUNCTION_DISABLE_SWCOM_MASK) >> GPIO_FUNCTION_DISABLE_SWCOM_LSB)

2540

#define GPIO_FUNCTION_DISABLE_SWCOM_SET(x) (((x) << GPIO_FUNCTION_DISABLE_SWCOM_LSB) & GPIO_FUNCTION_DISABLE_SWCOM_MASK)

2541

#define GPIO_FUNCTION_DISABLE_SWCOM_RESET 0x0 // 0

2542

#define GPIO_FUNCTION_EXT_MDIO_SEL_MSB 13

2543

#define GPIO_FUNCTION_EXT_MDIO_SEL_LSB 13

2544

#define GPIO_FUNCTION_EXT_MDIO_SEL_MASK 0x00002000

2545

#define GPIO_FUNCTION_EXT_MDIO_SEL_GET(x) (((x) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK) >> GPIO_FUNCTION_EXT_MDIO_SEL_LSB)

2546

#define GPIO_FUNCTION_EXT_MDIO_SEL_SET(x) (((x) << GPIO_FUNCTION_EXT_MDIO_SEL_LSB) & GPIO_FUNCTION_EXT_MDIO_SEL_MASK)

2547

#define GPIO_FUNCTION_EXT_MDIO_SEL_RESET 0x0 // 0

2548

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MSB 11

2549

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB 11

2550

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK 0x00000800

2551

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB)

2552

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK)

2553

#define GPIO_FUNCTION_CLK_OBS9_ENABLE_RESET 0x0 // 0

2554

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MSB 10

2555

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB 10

2556

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK 0x00000400

2557

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB)

2558

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK)

2559

#define GPIO_FUNCTION_CLK_OBS8_ENABLE_RESET 0x0 // 0

2560

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MSB 9

2561

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB 9

2562

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK 0x00000200

2563

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB)

2564

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK)

2565

#define GPIO_FUNCTION_CLK_OBS7_ENABLE_RESET 0x0 // 0

2566

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB 8

2567

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB 8

2568

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK 0x00000100

2569

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB)

2570

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK)

2571

#define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET 0x0 // 0

2572

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB 7

2573

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB 7

2574

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK 0x00000080

2575

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB)

2576

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK)

2577

#define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET 0x1 // 1

2578

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB 6

2579

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB 6

2580

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK 0x00000040

2581

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB)

2582

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK)

2583

#define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET 0x0 // 0

2584

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB 5

2585

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB 5

2586

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK 0x00000020

2587

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB)

2588

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK)

2589

#define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET 0x0 // 0

2590

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB 4

2591

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB 4

2592

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK 0x00000010

2593

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB)

2594

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK)

2595

#define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET 0x0 // 0

2596

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB 3

2597

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB 3

2598

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK 0x00000008

2599

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB)

2600

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK)

2601

#define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET 0x0 // 0

2602

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB 2

2603

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB 2

2604

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK 0x00000004

2605

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x) (((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB)

2606

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x) (((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK)

2607

#define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET 0x0 // 0

2608

#define GPIO_FUNCTION_DISABLE_JTAG_MSB 1

2609

#define GPIO_FUNCTION_DISABLE_JTAG_LSB 1

2610

#define GPIO_FUNCTION_DISABLE_JTAG_MASK 0x00000002

2611

#define GPIO_FUNCTION_DISABLE_JTAG_GET(x) (((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB)

2612

#define GPIO_FUNCTION_DISABLE_JTAG_SET(x) (((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK)

2613

#define GPIO_FUNCTION_DISABLE_JTAG_RESET 0x0 // 0

2614

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB 0

2615

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB 0

2616

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK 0x00000001

2617

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x) (((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB)

2618

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x) (((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK)

2619

#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET 0x0 // 0

2620

#define GPIO_FUNCTION_ADDRESS 0x1804006c

2621

2622

#define PCIE_RESET_EP_RESET_L_MSB 2

2623

#define PCIE_RESET_EP_RESET_L_LSB 2

2624

#define PCIE_RESET_EP_RESET_L_MASK 0x00000004

2625

#define PCIE_RESET_EP_RESET_L_GET(x) (((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB)

2626

#define PCIE_RESET_EP_RESET_L_SET(x) (((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK)

2627

#define PCIE_RESET_EP_RESET_L_RESET 0x0 // 0

2628

#define PCIE_RESET_LINK_REQ_RESET_MSB 1

2629

#define PCIE_RESET_LINK_REQ_RESET_LSB 1

2630

#define PCIE_RESET_LINK_REQ_RESET_MASK 0x00000002

2631

#define PCIE_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB)

2632

#define PCIE_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK)

2633

#define PCIE_RESET_LINK_REQ_RESET_RESET 0x0 // 0

2634

#define PCIE_RESET_LINK_UP_MSB 0

2635

#define PCIE_RESET_LINK_UP_LSB 0

2636

#define PCIE_RESET_LINK_UP_MASK 0x00000001

2637

#define PCIE_RESET_LINK_UP_GET(x) (((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB)

2638

#define PCIE_RESET_LINK_UP_SET(x) (((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK)

2639

#define PCIE_RESET_LINK_UP_RESET 0x0 // 0

2640

#define PCIE_RESET_ADDRESS 0x18280018

2641

2642

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MSB 2

2643

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB 2

2644

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK 0x00000004

2645

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_GET(x) (((x) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK) >> ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB)

2646

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_SET(x) (((x) << ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK)

2647

#define ETH_SGMII_SERDES_EN_LOCK_DETECT_RESET 0x0 // 0

2648

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MSB 1

2649

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB 1

2650

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK 0x00000002

2651

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_GET(x) (((x) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK) >> ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB)

2652

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_SET(x) (((x) << ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK)

2653

#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_RESET 0x0 // 0

2654

#define ETH_SGMII_SERDES_EN_PLL_MSB 0

2655

#define ETH_SGMII_SERDES_EN_PLL_LSB 0

2656

#define ETH_SGMII_SERDES_EN_PLL_MASK 0x00000001

2657

#define ETH_SGMII_SERDES_EN_PLL_GET(x) (((x) & ETH_SGMII_SERDES_EN_PLL_MASK) >> ETH_SGMII_SERDES_EN_PLL_LSB)

2658

#define ETH_SGMII_SERDES_EN_PLL_SET(x) (((x) << ETH_SGMII_SERDES_EN_PLL_LSB) & ETH_SGMII_SERDES_EN_PLL_MASK)

2659

#define ETH_SGMII_SERDES_EN_PLL_RESET 0x1 // 1

2660

#define ETH_SGMII_SERDES_ADDRESS 0x1805004c

2661

2662

#define ETH_CFG_ETH_SPARE_MSB 31

2663

#define ETH_CFG_ETH_SPARE_LSB 22

2664

#define ETH_CFG_ETH_SPARE_MASK 0xffc00000

2665

#define ETH_CFG_ETH_SPARE_GET(x) (((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)

2666

#define ETH_CFG_ETH_SPARE_SET(x) (((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)

2667

#define ETH_CFG_ETH_SPARE_RESET 0x0 // 0

2668

#define ETH_CFG_ETH_TXEN_DELAY_MSB 21

2669

#define ETH_CFG_ETH_TXEN_DELAY_LSB 20

2670

#define ETH_CFG_ETH_TXEN_DELAY_MASK 0x00300000

2671

#define ETH_CFG_ETH_TXEN_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB)

2672

#define ETH_CFG_ETH_TXEN_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK)

2673

#define ETH_CFG_ETH_TXEN_DELAY_RESET 0x0 // 0

2674

#define ETH_CFG_ETH_TXD_DELAY_MSB 19

2675

#define ETH_CFG_ETH_TXD_DELAY_LSB 18

2676

#define ETH_CFG_ETH_TXD_DELAY_MASK 0x000c0000

2677

#define ETH_CFG_ETH_TXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB)

2678

#define ETH_CFG_ETH_TXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK)

2679

#define ETH_CFG_ETH_TXD_DELAY_RESET 0x0 // 0

2680

#define ETH_CFG_ETH_RXDV_DELAY_MSB 17

2681

#define ETH_CFG_ETH_RXDV_DELAY_LSB 16

2682

#define ETH_CFG_ETH_RXDV_DELAY_MASK 0x00030000

2683

#define ETH_CFG_ETH_RXDV_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB)

2684

#define ETH_CFG_ETH_RXDV_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK)

2685

#define ETH_CFG_ETH_RXDV_DELAY_RESET 0x0 // 0

2686

#define ETH_CFG_ETH_RXD_DELAY_MSB 15

2687

#define ETH_CFG_ETH_RXD_DELAY_LSB 14

2688

#define ETH_CFG_ETH_RXD_DELAY_MASK 0x0000c000

2689

#define ETH_CFG_ETH_RXD_DELAY_GET(x) (((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB)

2690

#define ETH_CFG_ETH_RXD_DELAY_SET(x) (((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK)

2691

#define ETH_CFG_ETH_RXD_DELAY_RESET 0x0 // 0

2692

#define ETH_CFG_SW_ACC_MSB_FIRST_MSB 13

2693

#define ETH_CFG_SW_ACC_MSB_FIRST_LSB 13

2694

#define ETH_CFG_SW_ACC_MSB_FIRST_MASK 0x00002000

2695

#define ETH_CFG_SW_ACC_MSB_FIRST_GET(x) (((x) & ETH_CFG_SW_ACC_MSB_FIRST_MASK) >> ETH_CFG_SW_ACC_MSB_FIRST_LSB)

2696

#define ETH_CFG_SW_ACC_MSB_FIRST_SET(x) (((x) << ETH_CFG_SW_ACC_MSB_FIRST_LSB) & ETH_CFG_SW_ACC_MSB_FIRST_MASK)

2697

#define ETH_CFG_SW_ACC_MSB_FIRST_RESET 0x1 // 1

2698

#define ETH_CFG_RMII_GE0_MASTER_MSB 12

2699

#define ETH_CFG_RMII_GE0_MASTER_LSB 12

2700

#define ETH_CFG_RMII_GE0_MASTER_MASK 0x00001000

2701

#define ETH_CFG_RMII_GE0_MASTER_GET(x) (((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB)

2702

#define ETH_CFG_RMII_GE0_MASTER_SET(x) (((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK)

2703

#define ETH_CFG_RMII_GE0_MASTER_RESET 0x1 // 1

2704

#define ETH_CFG_MII_CNTL_SPEED_MSB 11

2705

#define ETH_CFG_MII_CNTL_SPEED_LSB 11

2706

#define ETH_CFG_MII_CNTL_SPEED_MASK 0x00000800

2707

#define ETH_CFG_MII_CNTL_SPEED_GET(x) (((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB)

2708

#define ETH_CFG_MII_CNTL_SPEED_SET(x) (((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK)

2709

#define ETH_CFG_MII_CNTL_SPEED_RESET 0x0 // 0

2710

#define ETH_CFG_SW_APB_ACCESS_MSB 10

2711

#define ETH_CFG_SW_APB_ACCESS_LSB 10

2712

#define ETH_CFG_SW_APB_ACCESS_MASK 0x00000400

2713

#define ETH_CFG_SW_APB_ACCESS_GET(x) (((x) & ETH_CFG_SW_APB_ACCESS_MASK) >> ETH_CFG_SW_APB_ACCESS_LSB)

2714

#define ETH_CFG_SW_APB_ACCESS_SET(x) (((x) << ETH_CFG_SW_APB_ACCESS_LSB) & ETH_CFG_SW_APB_ACCESS_MASK)

2715

#define ETH_CFG_SW_APB_ACCESS_RESET 0x0 // 0

2716

#define ETH_CFG_SW_PHY_ADDR_SWAP_MSB 9

2717

#define ETH_CFG_SW_PHY_ADDR_SWAP_LSB 9

2718

#define ETH_CFG_SW_PHY_ADDR_SWAP_MASK 0x00000200

2719

#define ETH_CFG_SW_PHY_ADDR_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK) >> ETH_CFG_SW_PHY_ADDR_SWAP_LSB)

2720

#define ETH_CFG_SW_PHY_ADDR_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_ADDR_SWAP_LSB) & ETH_CFG_SW_PHY_ADDR_SWAP_MASK)

2721

#define ETH_CFG_SW_PHY_ADDR_SWAP_RESET 0x0 // 0

2722

#define ETH_CFG_SW_PHY_SWAP_MSB 8

2723

#define ETH_CFG_SW_PHY_SWAP_LSB 8

2724

#define ETH_CFG_SW_PHY_SWAP_MASK 0x00000100

2725

#define ETH_CFG_SW_PHY_SWAP_GET(x) (((x) & ETH_CFG_SW_PHY_SWAP_MASK) >> ETH_CFG_SW_PHY_SWAP_LSB)

2726

#define ETH_CFG_SW_PHY_SWAP_SET(x) (((x) << ETH_CFG_SW_PHY_SWAP_LSB) & ETH_CFG_SW_PHY_SWAP_MASK)

2727

#define ETH_CFG_SW_PHY_SWAP_RESET 0x0 // 0

2728

#define ETH_CFG_SW_ONLY_MODE_MSB 7

2729

#define ETH_CFG_SW_ONLY_MODE_LSB 7

2730

#define ETH_CFG_SW_ONLY_MODE_MASK 0x00000080

2731

#define ETH_CFG_SW_ONLY_MODE_GET(x) (((x) & ETH_CFG_SW_ONLY_MODE_MASK) >> ETH_CFG_SW_ONLY_MODE_LSB)

2732

#define ETH_CFG_SW_ONLY_MODE_SET(x) (((x) << ETH_CFG_SW_ONLY_MODE_LSB) & ETH_CFG_SW_ONLY_MODE_MASK)

2733

#define ETH_CFG_SW_ONLY_MODE_RESET 0x0 // 0

2734

#define ETH_CFG_GE0_SGMII_MSB 6

2735

#define ETH_CFG_GE0_SGMII_LSB 6

2736

#define ETH_CFG_GE0_SGMII_MASK 0x00000040

2737

#define ETH_CFG_GE0_SGMII_GET(x) (((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB)

2738

#define ETH_CFG_GE0_SGMII_SET(x) (((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK)

2739

#define ETH_CFG_GE0_SGMII_RESET 0x0 // 0

2740

#define ETH_CFG_GE0_ERR_EN_MSB 5

2741

#define ETH_CFG_GE0_ERR_EN_LSB 5

2742

#define ETH_CFG_GE0_ERR_EN_MASK 0x00000020

2743

#define ETH_CFG_GE0_ERR_EN_GET(x) (((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB)

2744

#define ETH_CFG_GE0_ERR_EN_SET(x) (((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK)

2745

#define ETH_CFG_GE0_ERR_EN_RESET 0x0 // 0

2746

#define ETH_CFG_MII_GE0_SLAVE_MSB 4

2747

#define ETH_CFG_MII_GE0_SLAVE_LSB 4

2748

#define ETH_CFG_MII_GE0_SLAVE_MASK 0x00000010

2749

#define ETH_CFG_MII_GE0_SLAVE_GET(x) (((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB)

2750

#define ETH_CFG_MII_GE0_SLAVE_SET(x) (((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK)

2751

#define ETH_CFG_MII_GE0_SLAVE_RESET 0x0 // 0

2752

#define ETH_CFG_MII_GE0_MASTER_MSB 3

2753

#define ETH_CFG_MII_GE0_MASTER_LSB 3

2754

#define ETH_CFG_MII_GE0_MASTER_MASK 0x00000008

2755

#define ETH_CFG_MII_GE0_MASTER_GET(x) (((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB)

2756

#define ETH_CFG_MII_GE0_MASTER_SET(x) (((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK)

2757

#define ETH_CFG_MII_GE0_MASTER_RESET 0x0 // 0

2758

#define ETH_CFG_GMII_GE0_MSB 2

2759

#define ETH_CFG_GMII_GE0_LSB 2

2760

#define ETH_CFG_GMII_GE0_MASK 0x00000004

2761

#define ETH_CFG_GMII_GE0_GET(x) (((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB)

2762

#define ETH_CFG_GMII_GE0_SET(x) (((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK)

2763

#define ETH_CFG_GMII_GE0_RESET 0x0 // 0

2764

#define ETH_CFG_MII_GE0_MSB 1

2765

#define ETH_CFG_MII_GE0_LSB 1

2766

#define ETH_CFG_MII_GE0_MASK 0x00000002

2767

#define ETH_CFG_MII_GE0_GET(x) (((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB)

2768

#define ETH_CFG_MII_GE0_SET(x) (((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK)

2769

#define ETH_CFG_MII_GE0_RESET 0x0 // 0

2770

#define ETH_CFG_RGMII_GE0_MSB 0

2771

#define ETH_CFG_RGMII_GE0_LSB 0

2772

#define ETH_CFG_RGMII_GE0_MASK 0x00000001

2773

#define ETH_CFG_RGMII_GE0_GET(x) (((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB)

2774

#define ETH_CFG_RGMII_GE0_SET(x) (((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK)

2775

#define ETH_CFG_RGMII_GE0_RESET 0x0 // 0

2776

#define ETH_CFG_ADDRESS 0x18070000

2777

2778

#define SGMII_SERDES_VCO_REG_MSB 30

2779

#define SGMII_SERDES_VCO_REG_LSB 27

2780

#define SGMII_SERDES_VCO_REG_MASK 0x78000000

2781

#define SGMII_SERDES_VCO_REG_GET(x) (((x) & SGMII_SERDES_VCO_REG_MASK) >> SGMII_SERDES_VCO_REG_LSB)

2782

#define SGMII_SERDES_VCO_REG_SET(x) (((x) << SGMII_SERDES_VCO_REG_LSB) & SGMII_SERDES_VCO_REG_MASK)

2783

#define SGMII_SERDES_VCO_REG_RESET 0x3 // 3

2784

#define SGMII_SERDES_RES_CALIBRATION_MSB 26

2785

#define SGMII_SERDES_RES_CALIBRATION_LSB 23

2786

#define SGMII_SERDES_RES_CALIBRATION_MASK 0x07800000

2787

#define SGMII_SERDES_RES_CALIBRATION_GET(x) (((x) & SGMII_SERDES_RES_CALIBRATION_MASK) >> SGMII_SERDES_RES_CALIBRATION_LSB)

2788

#define SGMII_SERDES_RES_CALIBRATION_SET(x) (((x) << SGMII_SERDES_RES_CALIBRATION_LSB) & SGMII_SERDES_RES_CALIBRATION_MASK)

2789

#define SGMII_SERDES_RES_CALIBRATION_RESET 0x0 // 0

2790

#define SGMII_SERDES_FIBER_MODE_MSB 21

2791

#define SGMII_SERDES_FIBER_MODE_LSB 20

2792

#define SGMII_SERDES_FIBER_MODE_MASK 0x00300000

2793

#define SGMII_SERDES_FIBER_MODE_GET(x) (((x) & SGMII_SERDES_FIBER_MODE_MASK) >> SGMII_SERDES_FIBER_MODE_LSB)

2794

#define SGMII_SERDES_FIBER_MODE_SET(x) (((x) << SGMII_SERDES_FIBER_MODE_LSB) & SGMII_SERDES_FIBER_MODE_MASK)

2795

#define SGMII_SERDES_FIBER_MODE_RESET 0x0 // 0

2796

#define SGMII_SERDES_THRESHOLD_CTRL_MSB 19

2797

#define SGMII_SERDES_THRESHOLD_CTRL_LSB 18

2798

#define SGMII_SERDES_THRESHOLD_CTRL_MASK 0x000c0000

2799

#define SGMII_SERDES_THRESHOLD_CTRL_GET(x) (((x) & SGMII_SERDES_THRESHOLD_CTRL_MASK) >> SGMII_SERDES_THRESHOLD_CTRL_LSB)

2800

#define SGMII_SERDES_THRESHOLD_CTRL_SET(x) (((x) << SGMII_SERDES_THRESHOLD_CTRL_LSB) & SGMII_SERDES_THRESHOLD_CTRL_MASK)

2801

#define SGMII_SERDES_THRESHOLD_CTRL_RESET 0x0 // 0

2802

#define SGMII_SERDES_FIBER_SDO_MSB 17

2803

#define SGMII_SERDES_FIBER_SDO_LSB 17

2804

#define SGMII_SERDES_FIBER_SDO_MASK 0x00020000

2805

#define SGMII_SERDES_FIBER_SDO_GET(x) (((x) & SGMII_SERDES_FIBER_SDO_MASK) >> SGMII_SERDES_FIBER_SDO_LSB)

2806

#define SGMII_SERDES_FIBER_SDO_SET(x) (((x) << SGMII_SERDES_FIBER_SDO_LSB) & SGMII_SERDES_FIBER_SDO_MASK)

2807

#define SGMII_SERDES_FIBER_SDO_RESET 0x0 // 0

2808

#define SGMII_SERDES_EN_SIGNAL_DETECT_MSB 16

2809

#define SGMII_SERDES_EN_SIGNAL_DETECT_LSB 16

2810

#define SGMII_SERDES_EN_SIGNAL_DETECT_MASK 0x00010000

2811

#define SGMII_SERDES_EN_SIGNAL_DETECT_GET(x) (((x) & SGMII_SERDES_EN_SIGNAL_DETECT_MASK) >> SGMII_SERDES_EN_SIGNAL_DETECT_LSB)

2812

#define SGMII_SERDES_EN_SIGNAL_DETECT_SET(x) (((x) << SGMII_SERDES_EN_SIGNAL_DETECT_LSB) & SGMII_SERDES_EN_SIGNAL_DETECT_MASK)

2813

#define SGMII_SERDES_EN_SIGNAL_DETECT_RESET 0x1 // 1

2814

#define SGMII_SERDES_LOCK_DETECT_STATUS_MSB 15

2815

#define SGMII_SERDES_LOCK_DETECT_STATUS_LSB 15

2816

#define SGMII_SERDES_LOCK_DETECT_STATUS_MASK 0x00008000

2817

#define SGMII_SERDES_LOCK_DETECT_STATUS_GET(x) (((x) & SGMII_SERDES_LOCK_DETECT_STATUS_MASK) >> SGMII_SERDES_LOCK_DETECT_STATUS_LSB)

2818

#define SGMII_SERDES_LOCK_DETECT_STATUS_SET(x) (((x) << SGMII_SERDES_LOCK_DETECT_STATUS_LSB) & SGMII_SERDES_LOCK_DETECT_STATUS_MASK)

2819

#define SGMII_SERDES_LOCK_DETECT_STATUS_RESET 0x0 // 0

2820

#define SGMII_SERDES_SPARE0_MSB 14

2821

#define SGMII_SERDES_SPARE0_LSB 11

2822

#define SGMII_SERDES_SPARE0_MASK 0x00007800

2823

#define SGMII_SERDES_SPARE0_GET(x) (((x) & SGMII_SERDES_SPARE0_MASK) >> SGMII_SERDES_SPARE0_LSB)

2824

#define SGMII_SERDES_SPARE0_SET(x) (((x) << SGMII_SERDES_SPARE0_LSB) & SGMII_SERDES_SPARE0_MASK)

2825

#define SGMII_SERDES_SPARE0_RESET 0x0 // 0

2826

#define SGMII_SERDES_VCO_SLOW_MSB 10

2827

#define SGMII_SERDES_VCO_SLOW_LSB 10

2828

#define SGMII_SERDES_VCO_SLOW_MASK 0x00000400

2829

#define SGMII_SERDES_VCO_SLOW_GET(x) (((x) & SGMII_SERDES_VCO_SLOW_MASK) >> SGMII_SERDES_VCO_SLOW_LSB)

2830

#define SGMII_SERDES_VCO_SLOW_SET(x) (((x) << SGMII_SERDES_VCO_SLOW_LSB) & SGMII_SERDES_VCO_SLOW_MASK)

2831

#define SGMII_SERDES_VCO_SLOW_RESET 0x0 // 0

2832

#define SGMII_SERDES_VCO_FAST_MSB 9

2833

#define SGMII_SERDES_VCO_FAST_LSB 9

2834

#define SGMII_SERDES_VCO_FAST_MASK 0x00000200

2835

#define SGMII_SERDES_VCO_FAST_GET(x) (((x) & SGMII_SERDES_VCO_FAST_MASK) >> SGMII_SERDES_VCO_FAST_LSB)

2836

#define SGMII_SERDES_VCO_FAST_SET(x) (((x) << SGMII_SERDES_VCO_FAST_LSB) & SGMII_SERDES_VCO_FAST_MASK)

2837

#define SGMII_SERDES_VCO_FAST_RESET 0x0 // 0

2838

#define SGMII_SERDES_PLL_BW_MSB 8

2839

#define SGMII_SERDES_PLL_BW_LSB 8

2840

#define SGMII_SERDES_PLL_BW_MASK 0x00000100

2841

#define SGMII_SERDES_PLL_BW_GET(x) (((x) & SGMII_SERDES_PLL_BW_MASK) >> SGMII_SERDES_PLL_BW_LSB)

2842

#define SGMII_SERDES_PLL_BW_SET(x) (((x) << SGMII_SERDES_PLL_BW_LSB) & SGMII_SERDES_PLL_BW_MASK)

2843

#define SGMII_SERDES_PLL_BW_RESET 0x1 // 1

2844

#define SGMII_SERDES_TX_IMPEDANCE_MSB 7

2845

#define SGMII_SERDES_TX_IMPEDANCE_LSB 7

2846

#define SGMII_SERDES_TX_IMPEDANCE_MASK 0x00000080

2847

#define SGMII_SERDES_TX_IMPEDANCE_GET(x) (((x) & SGMII_SERDES_TX_IMPEDANCE_MASK) >> SGMII_SERDES_TX_IMPEDANCE_LSB)

2848

#define SGMII_SERDES_TX_IMPEDANCE_SET(x) (((x) << SGMII_SERDES_TX_IMPEDANCE_LSB) & SGMII_SERDES_TX_IMPEDANCE_MASK)

2849

#define SGMII_SERDES_TX_IMPEDANCE_RESET 0x0 // 0

2850

#define SGMII_SERDES_TX_DR_CTRL_MSB 6

2851

#define SGMII_SERDES_TX_DR_CTRL_LSB 4

2852

#define SGMII_SERDES_TX_DR_CTRL_MASK 0x00000070

2853

#define SGMII_SERDES_TX_DR_CTRL_GET(x) (((x) & SGMII_SERDES_TX_DR_CTRL_MASK) >> SGMII_SERDES_TX_DR_CTRL_LSB)

2854

#define SGMII_SERDES_TX_DR_CTRL_SET(x) (((x) << SGMII_SERDES_TX_DR_CTRL_LSB) & SGMII_SERDES_TX_DR_CTRL_MASK)

2855

#define SGMII_SERDES_TX_DR_CTRL_RESET 0x1 // 1

2856

#define SGMII_SERDES_HALF_TX_MSB 3

2857

#define SGMII_SERDES_HALF_TX_LSB 3

2858

#define SGMII_SERDES_HALF_TX_MASK 0x00000008

2859

#define SGMII_SERDES_HALF_TX_GET(x) (((x) & SGMII_SERDES_HALF_TX_MASK) >> SGMII_SERDES_HALF_TX_LSB)

2860

#define SGMII_SERDES_HALF_TX_SET(x) (((x) << SGMII_SERDES_HALF_TX_LSB) & SGMII_SERDES_HALF_TX_MASK)

2861

#define SGMII_SERDES_HALF_TX_RESET 0x0 // 0

2862

#define SGMII_SERDES_CDR_BW_MSB 2

2863

#define SGMII_SERDES_CDR_BW_LSB 1

2864

#define SGMII_SERDES_CDR_BW_MASK 0x00000006

2865

#define SGMII_SERDES_CDR_BW_GET(x) (((x) & SGMII_SERDES_CDR_BW_MASK) >> SGMII_SERDES_CDR_BW_LSB)

2866

#define SGMII_SERDES_CDR_BW_SET(x) (((x) << SGMII_SERDES_CDR_BW_LSB) & SGMII_SERDES_CDR_BW_MASK)

2867

#define SGMII_SERDES_CDR_BW_RESET 0x3 // 3

2868

#define SGMII_SERDES_RX_IMPEDANCE_MSB 0

2869

#define SGMII_SERDES_RX_IMPEDANCE_LSB 0

2870

#define SGMII_SERDES_RX_IMPEDANCE_MASK 0x00000001

2871

#define SGMII_SERDES_RX_IMPEDANCE_GET(x) (((x) & SGMII_SERDES_RX_IMPEDANCE_MASK) >> SGMII_SERDES_RX_IMPEDANCE_LSB)

2872

#define SGMII_SERDES_RX_IMPEDANCE_SET(x) (((x) << SGMII_SERDES_RX_IMPEDANCE_LSB) & SGMII_SERDES_RX_IMPEDANCE_MASK)

2873

#define SGMII_SERDES_RX_IMPEDANCE_RESET 0x0 // 0

2874

#define SGMII_SERDES_ADDRESS 0x18070018

2875

2876

#define RST_RESET2_SPARE_MSB 31

2877

#define RST_RESET2_SPARE_LSB 19

2878

#define RST_RESET2_SPARE_MASK 0xfff80000

2879

#define RST_RESET2_SPARE_GET(x) (((x) & RST_RESET2_SPARE_MASK) >> RST_RESET2_SPARE_LSB)

2880

#define RST_RESET2_SPARE_SET(x) (((x) << RST_RESET2_SPARE_LSB) & RST_RESET2_SPARE_MASK)

2881

#define RST_RESET2_SPARE_RESET 0x0 // 0

2882

#define RST_RESET2_EP_MODE_MSB 18

2883

#define RST_RESET2_EP_MODE_LSB 18

2884

#define RST_RESET2_EP_MODE_MASK 0x00040000

2885

#define RST_RESET2_EP_MODE_GET(x) (((x) & RST_RESET2_EP_MODE_MASK) >> RST_RESET2_EP_MODE_LSB)

2886

#define RST_RESET2_EP_MODE_SET(x) (((x) << RST_RESET2_EP_MODE_LSB) & RST_RESET2_EP_MODE_MASK)

2887

#define RST_RESET2_EP_MODE_RESET 0x0 // 0

2888

#define RST_RESET2_USB2_EXT_PWR_SEQ_MSB 17

2889

#define RST_RESET2_USB2_EXT_PWR_SEQ_LSB 17

2890

#define RST_RESET2_USB2_EXT_PWR_SEQ_MASK 0x00020000

2891

#define RST_RESET2_USB2_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB2_EXT_PWR_SEQ_LSB)

2892

#define RST_RESET2_USB2_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET2_USB2_EXT_PWR_SEQ_LSB) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK)

2893

#define RST_RESET2_USB2_EXT_PWR_SEQ_RESET 0x1 // 1

2894

#define RST_RESET2_USB1_EXT_PWR_SEQ_MSB 16

2895

#define RST_RESET2_USB1_EXT_PWR_SEQ_LSB 16

2896

#define RST_RESET2_USB1_EXT_PWR_SEQ_MASK 0x00010000

2897

#define RST_RESET2_USB1_EXT_PWR_SEQ_GET(x) (((x) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB1_EXT_PWR_SEQ_LSB)

2898

#define RST_RESET2_USB1_EXT_PWR_SEQ_SET(x) (((x) << RST_RESET2_USB1_EXT_PWR_SEQ_LSB) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK)

2899

#define RST_RESET2_USB1_EXT_PWR_SEQ_RESET 0x1 // 1

2900

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MSB 15

2901

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB 15

2902

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK 0x00008000

2903

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_GET(x) (((x) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK) >> RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB)

2904

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(x) (((x) << RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK)

2905

#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_RESET 0x0 // 0

2906

#define RST_RESET2_USB_PHY2_ARESET_MSB 11

2907

#define RST_RESET2_USB_PHY2_ARESET_LSB 11

2908

#define RST_RESET2_USB_PHY2_ARESET_MASK 0x00000800

2909

#define RST_RESET2_USB_PHY2_ARESET_GET(x) (((x) & RST_RESET2_USB_PHY2_ARESET_MASK) >> RST_RESET2_USB_PHY2_ARESET_LSB)

2910

#define RST_RESET2_USB_PHY2_ARESET_SET(x) (((x) << RST_RESET2_USB_PHY2_ARESET_LSB) & RST_RESET2_USB_PHY2_ARESET_MASK)

2911

#define RST_RESET2_USB_PHY2_ARESET_RESET 0x1 // 1

2912

#define RST_RESET2_PCIE2_PHY_RESET_MSB 7

2913

#define RST_RESET2_PCIE2_PHY_RESET_LSB 7

2914

#define RST_RESET2_PCIE2_PHY_RESET_MASK 0x00000080

2915

#define RST_RESET2_PCIE2_PHY_RESET_GET(x) (((x) & RST_RESET2_PCIE2_PHY_RESET_MASK) >> RST_RESET2_PCIE2_PHY_RESET_LSB)

2916

#define RST_RESET2_PCIE2_PHY_RESET_SET(x) (((x) << RST_RESET2_PCIE2_PHY_RESET_LSB) & RST_RESET2_PCIE2_PHY_RESET_MASK)

2917

#define RST_RESET2_PCIE2_PHY_RESET_RESET 0x1 // 1

2918

#define RST_RESET2_PCIE2_RESET_MSB 6

2919

#define RST_RESET2_PCIE2_RESET_LSB 6

2920

#define RST_RESET2_PCIE2_RESET_MASK 0x00000040

2921

#define RST_RESET2_PCIE2_RESET_GET(x) (((x) & RST_RESET2_PCIE2_RESET_MASK) >> RST_RESET2_PCIE2_RESET_LSB)

2922

#define RST_RESET2_PCIE2_RESET_SET(x) (((x) << RST_RESET2_PCIE2_RESET_LSB) & RST_RESET2_PCIE2_RESET_MASK)

2923

#define RST_RESET2_PCIE2_RESET_RESET 0x1 // 1

2924

#define RST_RESET2_USB_HOST2_RESET_MSB 5

2925

#define RST_RESET2_USB_HOST2_RESET_LSB 5

2926

#define RST_RESET2_USB_HOST2_RESET_MASK 0x00000020

2927

#define RST_RESET2_USB_HOST2_RESET_GET(x) (((x) & RST_RESET2_USB_HOST2_RESET_MASK) >> RST_RESET2_USB_HOST2_RESET_LSB)

2928

#define RST_RESET2_USB_HOST2_RESET_SET(x) (((x) << RST_RESET2_USB_HOST2_RESET_LSB) & RST_RESET2_USB_HOST2_RESET_MASK)

2929

#define RST_RESET2_USB_HOST2_RESET_RESET 0x1 // 1

2930

#define RST_RESET2_USB_PHY2_RESET_MSB 4

2931

#define RST_RESET2_USB_PHY2_RESET_LSB 4

2932

#define RST_RESET2_USB_PHY2_RESET_MASK 0x00000010

2933

#define RST_RESET2_USB_PHY2_RESET_GET(x) (((x) & RST_RESET2_USB_PHY2_RESET_MASK) >> RST_RESET2_USB_PHY2_RESET_LSB)

2934

#define RST_RESET2_USB_PHY2_RESET_SET(x) (((x) << RST_RESET2_USB_PHY2_RESET_LSB) & RST_RESET2_USB_PHY2_RESET_MASK)

2935

#define RST_RESET2_USB_PHY2_RESET_RESET 0x1 // 1

2936

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MSB 3

2937

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB 3

2938

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK 0x00000008

2939

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_GET(x) (((x) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK) >> RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB)

2940

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_SET(x) (((x) << RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK)

2941

#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_RESET 0x0 // 0

2942

#define RST_RESET2_USB2_MODE_MSB 0

2943

#define RST_RESET2_USB2_MODE_LSB 0

2944

#define RST_RESET2_USB2_MODE_MASK 0x00000001

2945

#define RST_RESET2_USB2_MODE_GET(x) (((x) & RST_RESET2_USB2_MODE_MASK) >> RST_RESET2_USB2_MODE_LSB)

2946

#define RST_RESET2_USB2_MODE_SET(x) (((x) << RST_RESET2_USB2_MODE_LSB) & RST_RESET2_USB2_MODE_MASK)

2947

#define RST_RESET2_USB2_MODE_RESET 0x1 // 1

2948

#define RST_RESET2_ADDRESS 0x180600c0

2949

2950

#define RST_CLKGAT_EN_WMAC_MSB 9

2951

#define RST_CLKGAT_EN_WMAC_LSB 9

2952

#define RST_CLKGAT_EN_WMAC_MASK 0x00000200

2953

#define RST_CLKGAT_EN_WMAC_GET(x) (((x) & RST_CLKGAT_EN_WMAC_MASK) >> RST_CLKGAT_EN_WMAC_LSB)

2954

#define RST_CLKGAT_EN_WMAC_SET(x) (((x) << RST_CLKGAT_EN_WMAC_LSB) & RST_CLKGAT_EN_WMAC_MASK)

2955

#define RST_CLKGAT_EN_WMAC_RESET 0x1 // 1

2956

#define RST_CLKGAT_EN_USB2_MSB 8

2957

#define RST_CLKGAT_EN_USB2_LSB 8

2958

#define RST_CLKGAT_EN_USB2_MASK 0x00000100

2959

#define RST_CLKGAT_EN_USB2_GET(x) (((x) & RST_CLKGAT_EN_USB2_MASK) >> RST_CLKGAT_EN_USB2_LSB)

2960

#define RST_CLKGAT_EN_USB2_SET(x) (((x) << RST_CLKGAT_EN_USB2_LSB) & RST_CLKGAT_EN_USB2_MASK)

2961

#define RST_CLKGAT_EN_USB2_RESET 0x1 // 1

2962

#define RST_CLKGAT_EN_USB1_MSB 7

2963

#define RST_CLKGAT_EN_USB1_LSB 7

2964

#define RST_CLKGAT_EN_USB1_MASK 0x00000080

2965

#define RST_CLKGAT_EN_USB1_GET(x) (((x) & RST_CLKGAT_EN_USB1_MASK) >> RST_CLKGAT_EN_USB1_LSB)

2966

#define RST_CLKGAT_EN_USB1_SET(x) (((x) << RST_CLKGAT_EN_USB1_LSB) & RST_CLKGAT_EN_USB1_MASK)

2967

#define RST_CLKGAT_EN_USB1_RESET 0x1 // 1

2968

#define RST_CLKGAT_EN_GE1_MSB 6

2969

#define RST_CLKGAT_EN_GE1_LSB 6

2970

#define RST_CLKGAT_EN_GE1_MASK 0x00000040

2971

#define RST_CLKGAT_EN_GE1_GET(x) (((x) & RST_CLKGAT_EN_GE1_MASK) >> RST_CLKGAT_EN_GE1_LSB)

2972

#define RST_CLKGAT_EN_GE1_SET(x) (((x) << RST_CLKGAT_EN_GE1_LSB) & RST_CLKGAT_EN_GE1_MASK)

2973

#define RST_CLKGAT_EN_GE1_RESET 0x1 // 1

2974

#define RST_CLKGAT_EN_GE0_MSB 5

2975

#define RST_CLKGAT_EN_GE0_LSB 5

2976

#define RST_CLKGAT_EN_GE0_MASK 0x00000020

2977

#define RST_CLKGAT_EN_GE0_GET(x) (((x) & RST_CLKGAT_EN_GE0_MASK) >> RST_CLKGAT_EN_GE0_LSB)

2978

#define RST_CLKGAT_EN_GE0_SET(x) (((x) << RST_CLKGAT_EN_GE0_LSB) & RST_CLKGAT_EN_GE0_MASK)

2979

#define RST_CLKGAT_EN_GE0_RESET 0x1 // 1

2980

#define RST_CLKGAT_EN_CLK100_PCIERC2_MSB 4

2981

#define RST_CLKGAT_EN_CLK100_PCIERC2_LSB 4

2982

#define RST_CLKGAT_EN_CLK100_PCIERC2_MASK 0x00000010

2983

#define RST_CLKGAT_EN_CLK100_PCIERC2_GET(x) (((x) & RST_CLKGAT_EN_CLK100_PCIERC2_MASK) >> RST_CLKGAT_EN_CLK100_PCIERC2_LSB)

2984

#define RST_CLKGAT_EN_CLK100_PCIERC2_SET(x) (((x) << RST_CLKGAT_EN_CLK100_PCIERC2_LSB) & RST_CLKGAT_EN_CLK100_PCIERC2_MASK)

2985

#define RST_CLKGAT_EN_CLK100_PCIERC2_RESET 0x1 // 1

2986

#define RST_CLKGAT_EN_CLK100_PCIERC_MSB 3

2987

#define RST_CLKGAT_EN_CLK100_PCIERC_LSB 3

2988

#define RST_CLKGAT_EN_CLK100_PCIERC_MASK 0x00000008

2989

#define RST_CLKGAT_EN_CLK100_PCIERC_GET(x) (((x) & RST_CLKGAT_EN_CLK100_PCIERC_MASK) >> RST_CLKGAT_EN_CLK100_PCIERC_LSB)

2990

#define RST_CLKGAT_EN_CLK100_PCIERC_SET(x) (((x) << RST_CLKGAT_EN_CLK100_PCIERC_LSB) & RST_CLKGAT_EN_CLK100_PCIERC_MASK)

2991

#define RST_CLKGAT_EN_CLK100_PCIERC_RESET 0x1 // 1

2992

#define RST_CLKGAT_EN_PCIE_RC2_MSB 2

2993

#define RST_CLKGAT_EN_PCIE_RC2_LSB 2

2994

#define RST_CLKGAT_EN_PCIE_RC2_MASK 0x00000004

2995

#define RST_CLKGAT_EN_PCIE_RC2_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC2_MASK) >> RST_CLKGAT_EN_PCIE_RC2_LSB)

2996

#define RST_CLKGAT_EN_PCIE_RC2_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC2_LSB) & RST_CLKGAT_EN_PCIE_RC2_MASK)

2997

#define RST_CLKGAT_EN_PCIE_RC2_RESET 0x1 // 1

2998

#define RST_CLKGAT_EN_PCIE_RC_MSB 1

2999

#define RST_CLKGAT_EN_PCIE_RC_LSB 1

3000

#define RST_CLKGAT_EN_PCIE_RC_MASK 0x00000002

3001

#define RST_CLKGAT_EN_PCIE_RC_GET(x) (((x) & RST_CLKGAT_EN_PCIE_RC_MASK) >> RST_CLKGAT_EN_PCIE_RC_LSB)

3002

#define RST_CLKGAT_EN_PCIE_RC_SET(x) (((x) << RST_CLKGAT_EN_PCIE_RC_LSB) & RST_CLKGAT_EN_PCIE_RC_MASK)

3003

#define RST_CLKGAT_EN_PCIE_RC_RESET 0x1 // 1

3004

#define RST_CLKGAT_EN_PCIE_EP_MSB 0

3005

#define RST_CLKGAT_EN_PCIE_EP_LSB 0

3006

#define RST_CLKGAT_EN_PCIE_EP_MASK 0x00000001

3007

#define RST_CLKGAT_EN_PCIE_EP_GET(x) (((x) & RST_CLKGAT_EN_PCIE_EP_MASK) >> RST_CLKGAT_EN_PCIE_EP_LSB)

3008

#define RST_CLKGAT_EN_PCIE_EP_SET(x) (((x) << RST_CLKGAT_EN_PCIE_EP_LSB) & RST_CLKGAT_EN_PCIE_EP_MASK)

3009

#define RST_CLKGAT_EN_PCIE_EP_RESET 0x1 // 1

3010

#define RST_CLKGAT_EN_ADDRESS 0x180600c8

3011

3012

// blueprint don't have this address the define the same with PCIRC

3013

#if 1

3014

#define PCIE2_RESET_EP_RESET_L_MSB 2

3015

#define PCIE2_RESET_EP_RESET_L_LSB 2

3016

#define PCIE2_RESET_EP_RESET_L_MASK 0x00000004

3017

#define PCIE2_RESET_EP_RESET_L_GET(x) (((x) & PCIE2_RESET_EP_RESET_L_MASK) >> PCIE2_RESET_EP_RESET_L_LSB)

3018

#define PCIE2_RESET_EP_RESET_L_SET(x) (((x) << PCIE2_RESET_EP_RESET_L_LSB) & PCIE2_RESET_EP_RESET_L_MASK)

3019

#define PCIE2_RESET_EP_RESET_L_RESET 0x0 // 0

3020

#define PCIE2_RESET_LINK_REQ_RESET_MSB 1

3021

#define PCIE2_RESET_LINK_REQ_RESET_LSB 1

3022

#define PCIE2_RESET_LINK_REQ_RESET_MASK 0x00000002

3023

#define PCIE2_RESET_LINK_REQ_RESET_GET(x) (((x) & PCIE2_RESET_LINK_REQ_RESET_MASK) >> PCIE2_RESET_LINK_REQ_RESET_LSB)

3024

#define PCIE2_RESET_LINK_REQ_RESET_SET(x) (((x) << PCIE2_RESET_LINK_REQ_RESET_LSB) & PCIE2_RESET_LINK_REQ_RESET_MASK)

3025

#define PCIE2_RESET_LINK_REQ_RESET_RESET 0x0 // 0

3026

#define PCIE2_RESET_LINK_UP_MSB 0

3027

#define PCIE2_RESET_LINK_UP_LSB 0

3028

#define PCIE2_RESET_LINK_UP_MASK 0x00000001

3029

#define PCIE2_RESET_LINK_UP_GET(x) (((x) & PCIE2_RESET_LINK_UP_MASK) >> PCIE2_RESET_LINK_UP_LSB)

3030

#define PCIE2_RESET_LINK_UP_SET(x) (((x) << PCIE2_RESET_LINK_UP_LSB) & PCIE2_RESET_LINK_UP_MASK)

3031

#define PCIE2_RESET_LINK_UP_RESET 0x0 // 0

3032

#define PCIE2_RESET_ADDRESS 0x18280018

3033

3034

#define PCIE2_APP_CFG_TYPE_MSB 21

3035

#define PCIE2_APP_CFG_TYPE_LSB 20

3036

#define PCIE2_APP_CFG_TYPE_MASK 0x00300000

3037

#define PCIE2_APP_CFG_TYPE_GET(x) (((x) & PCIE2_APP_CFG_TYPE_MASK) >> PCIE2_APP_CFG_TYPE_LSB)

3038

#define PCIE2_APP_CFG_TYPE_SET(x) (((x) << PCIE2_APP_CFG_TYPE_LSB) & PCIE2_APP_CFG_TYPE_MASK)

3039

#define PCIE2_APP_CFG_TYPE_RESET 0x0 // 0

3040

#define PCIE2_APP_PCIE2_BAR_MSN_MSB 19

3041

#define PCIE2_APP_PCIE2_BAR_MSN_LSB 16

3042

#define PCIE2_APP_PCIE2_BAR_MSN_MASK 0x000f0000

3043

#define PCIE2_APP_PCIE2_BAR_MSN_GET(x) (((x) & PCIE2_APP_PCIE2_BAR_MSN_MASK) >> PCIE2_APP_PCIE2_BAR_MSN_LSB)

3044

#define PCIE2_APP_PCIE2_BAR_MSN_SET(x) (((x) << PCIE2_APP_PCIE2_BAR_MSN_LSB) & PCIE2_APP_PCIE2_BAR_MSN_MASK)

3045

#define PCIE2_APP_PCIE2_BAR_MSN_RESET 0x1 // 1

3046

#define PCIE2_APP_CFG_BE_MSB 15

3047

#define PCIE2_APP_CFG_BE_LSB 12

3048

#define PCIE2_APP_CFG_BE_MASK 0x0000f000

3049

#define PCIE2_APP_CFG_BE_GET(x) (((x) & PCIE2_APP_CFG_BE_MASK) >> PCIE2_APP_CFG_BE_LSB)

3050

#define PCIE2_APP_CFG_BE_SET(x) (((x) << PCIE2_APP_CFG_BE_LSB) & PCIE2_APP_CFG_BE_MASK)

3051

#define PCIE2_APP_CFG_BE_RESET 0xf // 15

3052

#define PCIE2_APP_SLV_RESP_ERR_MAP_MSB 11

3053

#define PCIE2_APP_SLV_RESP_ERR_MAP_LSB 6

3054

#define PCIE2_APP_SLV_RESP_ERR_MAP_MASK 0x00000fc0

3055

#define PCIE2_APP_SLV_RESP_ERR_MAP_GET(x) (((x) & PCIE2_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE2_APP_SLV_RESP_ERR_MAP_LSB)

3056

#define PCIE2_APP_SLV_RESP_ERR_MAP_SET(x) (((x) << PCIE2_APP_SLV_RESP_ERR_MAP_LSB) & PCIE2_APP_SLV_RESP_ERR_MAP_MASK)

3057

#define PCIE2_APP_SLV_RESP_ERR_MAP_RESET 0x3f // 63

3058

#define PCIE2_APP_MSTR_RESP_ERR_MAP_MSB 5

3059

#define PCIE2_APP_MSTR_RESP_ERR_MAP_LSB 4

3060

#define PCIE2_APP_MSTR_RESP_ERR_MAP_MASK 0x00000030

3061

#define PCIE2_APP_MSTR_RESP_ERR_MAP_GET(x) (((x) & PCIE2_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE2_APP_MSTR_RESP_ERR_MAP_LSB)

3062

#define PCIE2_APP_MSTR_RESP_ERR_MAP_SET(x) (((x) << PCIE2_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE2_APP_MSTR_RESP_ERR_MAP_MASK)

3063

#define PCIE2_APP_MSTR_RESP_ERR_MAP_RESET 0x0 // 0

3064

#define PCIE2_APP_INIT_RST_MSB 3

3065

#define PCIE2_APP_INIT_RST_LSB 3

3066

#define PCIE2_APP_INIT_RST_MASK 0x00000008

3067

#define PCIE2_APP_INIT_RST_GET(x) (((x) & PCIE2_APP_INIT_RST_MASK) >> PCIE2_APP_INIT_RST_LSB)

3068

#define PCIE2_APP_INIT_RST_SET(x) (((x) << PCIE2_APP_INIT_RST_LSB) & PCIE2_APP_INIT_RST_MASK)

3069

#define PCIE2_APP_INIT_RST_RESET 0x0 // 0

3070

#define PCIE2_APP_PM_XMT_TURNOFF_MSB 2

3071

#define PCIE2_APP_PM_XMT_TURNOFF_LSB 2

3072

#define PCIE2_APP_PM_XMT_TURNOFF_MASK 0x00000004

3073

#define PCIE2_APP_PM_XMT_TURNOFF_GET(x) (((x) & PCIE2_APP_PM_XMT_TURNOFF_MASK) >> PCIE2_APP_PM_XMT_TURNOFF_LSB)

3074

#define PCIE2_APP_PM_XMT_TURNOFF_SET(x) (((x) << PCIE2_APP_PM_XMT_TURNOFF_LSB) & PCIE2_APP_PM_XMT_TURNOFF_MASK)

3075

#define PCIE2_APP_PM_XMT_TURNOFF_RESET 0x0 // 0

3076

#define PCIE2_APP_UNLOCK_MSG_MSB 1

3077

#define PCIE2_APP_UNLOCK_MSG_LSB 1

3078

#define PCIE2_APP_UNLOCK_MSG_MASK 0x00000002

3079

#define PCIE2_APP_UNLOCK_MSG_GET(x) (((x) & PCIE2_APP_UNLOCK_MSG_MASK) >> PCIE2_APP_UNLOCK_MSG_LSB)

3080

#define PCIE2_APP_UNLOCK_MSG_SET(x) (((x) << PCIE2_APP_UNLOCK_MSG_LSB) & PCIE2_APP_UNLOCK_MSG_MASK)

3081

#define PCIE2_APP_UNLOCK_MSG_RESET 0x0 // 0

3082

#define PCIE2_APP_LTSSM_ENABLE_MSB 0

3083

#define PCIE2_APP_LTSSM_ENABLE_LSB 0

3084

#define PCIE2_APP_LTSSM_ENABLE_MASK 0x00000001

3085

#define PCIE2_APP_LTSSM_ENABLE_GET(x) (((x) & PCIE2_APP_LTSSM_ENABLE_MASK) >> PCIE2_APP_LTSSM_ENABLE_LSB)

3086

#define PCIE2_APP_LTSSM_ENABLE_SET(x) (((x) << PCIE2_APP_LTSSM_ENABLE_LSB) & PCIE2_APP_LTSSM_ENABLE_MASK)

3087

#define PCIE2_APP_LTSSM_ENABLE_RESET 0x0 // 0

3088

#define PCIE2_APP_ADDRESS 0x18280000

3089

#endif

3090

3091

#define PCIE_INT_MASK_LINK_DOWN_MSB 27

3092

#define PCIE_INT_MASK_LINK_DOWN_LSB 27

3093

#define PCIE_INT_MASK_LINK_DOWN_MASK 0x08000000

3094

#define PCIE_INT_MASK_LINK_DOWN_GET(x) (((x) & PCIE_INT_MASK_LINK_DOWN_MASK) >> PCIE_INT_MASK_LINK_DOWN_LSB)

3095

#define PCIE_INT_MASK_LINK_DOWN_SET(x) (((x) << PCIE_INT_MASK_LINK_DOWN_LSB) & PCIE_INT_MASK_LINK_DOWN_MASK)

3096

#define PCIE_INT_MASK_LINK_DOWN_RESET 0x0 // 0

3097

#define PCIE_INT_MASK_LINK_REQ_RST_MSB 26

3098

#define PCIE_INT_MASK_LINK_REQ_RST_LSB 26

3099

#define PCIE_INT_MASK_LINK_REQ_RST_MASK 0x04000000

3100

#define PCIE_INT_MASK_LINK_REQ_RST_GET(x) (((x) & PCIE_INT_MASK_LINK_REQ_RST_MASK) >> PCIE_INT_MASK_LINK_REQ_RST_LSB)

3101

#define PCIE_INT_MASK_LINK_REQ_RST_SET(x) (((x) << PCIE_INT_MASK_LINK_REQ_RST_LSB) & PCIE_INT_MASK_LINK_REQ_RST_MASK)

3102

#define PCIE_INT_MASK_LINK_REQ_RST_RESET 0x0 // 0

3103

#define PCIE_INT_MASK_INTDL_MSB 17

3104

#define PCIE_INT_MASK_INTDL_LSB 17

3105

#define PCIE_INT_MASK_INTDL_MASK 0x00020000

3106

#define PCIE_INT_MASK_INTDL_GET(x) (((x) & PCIE_INT_MASK_INTDL_MASK) >> PCIE_INT_MASK_INTDL_LSB)

3107

#define PCIE_INT_MASK_INTDL_SET(x) (((x) << PCIE_INT_MASK_INTDL_LSB) & PCIE_INT_MASK_INTDL_MASK)

3108

#define PCIE_INT_MASK_INTDL_RESET 0x0 // 0

3109

#define PCIE_INT_MASK_INTCL_MSB 16

3110

#define PCIE_INT_MASK_INTCL_LSB 16

3111

#define PCIE_INT_MASK_INTCL_MASK 0x00010000

3112

#define PCIE_INT_MASK_INTCL_GET(x) (((x) & PCIE_INT_MASK_INTCL_MASK) >> PCIE_INT_MASK_INTCL_LSB)

3113

#define PCIE_INT_MASK_INTCL_SET(x) (((x) << PCIE_INT_MASK_INTCL_LSB) & PCIE_INT_MASK_INTCL_MASK)

3114

#define PCIE_INT_MASK_INTCL_RESET 0x0 // 0

3115

#define PCIE_INT_MASK_INTBL_MSB 15

3116

#define PCIE_INT_MASK_INTBL_LSB 15

3117

#define PCIE_INT_MASK_INTBL_MASK 0x00008000

3118

#define PCIE_INT_MASK_INTBL_GET(x) (((x) & PCIE_INT_MASK_INTBL_MASK) >> PCIE_INT_MASK_INTBL_LSB)

3119

#define PCIE_INT_MASK_INTBL_SET(x) (((x) << PCIE_INT_MASK_INTBL_LSB) & PCIE_INT_MASK_INTBL_MASK)

3120

#define PCIE_INT_MASK_INTBL_RESET 0x0 // 0

3121

#define PCIE_INT_MASK_INTAL_MSB 14

3122

#define PCIE_INT_MASK_INTAL_LSB 14

3123

#define PCIE_INT_MASK_INTAL_MASK 0x00004000

3124

#define PCIE_INT_MASK_INTAL_GET(x) (((x) & PCIE_INT_MASK_INTAL_MASK) >> PCIE_INT_MASK_INTAL_LSB)

3125

#define PCIE_INT_MASK_INTAL_SET(x) (((x) << PCIE_INT_MASK_INTAL_LSB) & PCIE_INT_MASK_INTAL_MASK)

3126

#define PCIE_INT_MASK_INTAL_RESET 0x0 // 0

3127

#define PCIE_INT_MASK_SYS_ERR_MSB 13

3128

#define PCIE_INT_MASK_SYS_ERR_LSB 13

3129

#define PCIE_INT_MASK_SYS_ERR_MASK 0x00002000

3130

#define PCIE_INT_MASK_SYS_ERR_GET(x) (((x) & PCIE_INT_MASK_SYS_ERR_MASK) >> PCIE_INT_MASK_SYS_ERR_LSB)

3131

#define PCIE_INT_MASK_SYS_ERR_SET(x) (((x) << PCIE_INT_MASK_SYS_ERR_LSB) & PCIE_INT_MASK_SYS_ERR_MASK)

3132

#define PCIE_INT_MASK_SYS_ERR_RESET 0x0 // 0

3133

#define PCIE_INT_MASK_AER_MSI_MSB 12

3134

#define PCIE_INT_MASK_AER_MSI_LSB 12

3135

#define PCIE_INT_MASK_AER_MSI_MASK 0x00001000

3136

#define PCIE_INT_MASK_AER_MSI_GET(x) (((x) & PCIE_INT_MASK_AER_MSI_MASK) >> PCIE_INT_MASK_AER_MSI_LSB)

3137

#define PCIE_INT_MASK_AER_MSI_SET(x) (((x) << PCIE_INT_MASK_AER_MSI_LSB) & PCIE_INT_MASK_AER_MSI_MASK)

3138

#define PCIE_INT_MASK_AER_MSI_RESET 0x0 // 0

3139

#define PCIE_INT_MASK_AER_INT_MSB 11

3140

#define PCIE_INT_MASK_AER_INT_LSB 11

3141

#define PCIE_INT_MASK_AER_INT_MASK 0x00000800

3142

#define PCIE_INT_MASK_AER_INT_GET(x) (((x) & PCIE_INT_MASK_AER_INT_MASK) >> PCIE_INT_MASK_AER_INT_LSB)

3143

#define PCIE_INT_MASK_AER_INT_SET(x) (((x) << PCIE_INT_MASK_AER_INT_LSB) & PCIE_INT_MASK_AER_INT_MASK)

3144

#define PCIE_INT_MASK_AER_INT_RESET 0x0 // 0

3145

#define PCIE_INT_MASK_MSI_ERR_MSB 10

3146

#define PCIE_INT_MASK_MSI_ERR_LSB 10

3147

#define PCIE_INT_MASK_MSI_ERR_MASK 0x00000400

3148

#define PCIE_INT_MASK_MSI_ERR_GET(x) (((x) & PCIE_INT_MASK_MSI_ERR_MASK) >> PCIE_INT_MASK_MSI_ERR_LSB)

3149

#define PCIE_INT_MASK_MSI_ERR_SET(x) (((x) << PCIE_INT_MASK_MSI_ERR_LSB) & PCIE_INT_MASK_MSI_ERR_MASK)

3150

#define PCIE_INT_MASK_MSI_ERR_RESET 0x0 // 0

3151

#define PCIE_INT_MASK_MSI_MSB 9

3152

#define PCIE_INT_MASK_MSI_LSB 9

3153

#define PCIE_INT_MASK_MSI_MASK 0x00000200

3154

#define PCIE_INT_MASK_MSI_GET(x) (((x) & PCIE_INT_MASK_MSI_MASK) >> PCIE_INT_MASK_MSI_LSB)

3155

#define PCIE_INT_MASK_MSI_SET(x) (((x) << PCIE_INT_MASK_MSI_LSB) & PCIE_INT_MASK_MSI_MASK)

3156

#define PCIE_INT_MASK_MSI_RESET 0x0 // 0

3157

#define PCIE_INT_MASK_INTD_MSB 8

3158

#define PCIE_INT_MASK_INTD_LSB 8

3159

#define PCIE_INT_MASK_INTD_MASK 0x00000100

3160

#define PCIE_INT_MASK_INTD_GET(x) (((x) & PCIE_INT_MASK_INTD_MASK) >> PCIE_INT_MASK_INTD_LSB)

3161

#define PCIE_INT_MASK_INTD_SET(x) (((x) << PCIE_INT_MASK_INTD_LSB) & PCIE_INT_MASK_INTD_MASK)

3162

#define PCIE_INT_MASK_INTD_RESET 0x0 // 0

3163

#define PCIE_INT_MASK_INTC_MSB 7

3164

#define PCIE_INT_MASK_INTC_LSB 7

3165

#define PCIE_INT_MASK_INTC_MASK 0x00000080

3166

#define PCIE_INT_MASK_INTC_GET(x) (((x) & PCIE_INT_MASK_INTC_MASK) >> PCIE_INT_MASK_INTC_LSB)

3167

#define PCIE_INT_MASK_INTC_SET(x) (((x) << PCIE_INT_MASK_INTC_LSB) & PCIE_INT_MASK_INTC_MASK)

3168

#define PCIE_INT_MASK_INTC_RESET 0x0 // 0

3169

#define PCIE_INT_MASK_INTB_MSB 6

3170

#define PCIE_INT_MASK_INTB_LSB 6

3171

#define PCIE_INT_MASK_INTB_MASK 0x00000040

3172

#define PCIE_INT_MASK_INTB_GET(x) (((x) & PCIE_INT_MASK_INTB_MASK) >> PCIE_INT_MASK_INTB_LSB)

3173

#define PCIE_INT_MASK_INTB_SET(x) (((x) << PCIE_INT_MASK_INTB_LSB) & PCIE_INT_MASK_INTB_MASK)

3174

#define PCIE_INT_MASK_INTB_RESET 0x0 // 0

3175

#define PCIE_INT_MASK_INTA_MSB 5

3176

#define PCIE_INT_MASK_INTA_LSB 5

3177

#define PCIE_INT_MASK_INTA_MASK 0x00000020

3178

#define PCIE_INT_MASK_INTA_GET(x) (((x) & PCIE_INT_MASK_INTA_MASK) >> PCIE_INT_MASK_INTA_LSB)

3179

#define PCIE_INT_MASK_INTA_SET(x) (((x) << PCIE_INT_MASK_INTA_LSB) & PCIE_INT_MASK_INTA_MASK)

3180

#define PCIE_INT_MASK_INTA_RESET 0x0 // 0

3181

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_MSB 4

3182

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_LSB 4

3183

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_MASK 0x00000010

3184

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_GET(x) (((x) & PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_MASK) >> PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_LSB)

3185

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_SET(x) (((x) << PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_LSB) & PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_MASK)

3186

#define PCIE_INT_MASK_RADMX_COMP_LOOKUP_ERR_RESET 0x0 // 0

3187

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_MSB 3

3188

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_LSB 3

3189

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_MASK 0x00000008

3190

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_GET(x) (((x) & PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_MASK) >> PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_LSB)

3191

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_SET(x) (((x) << PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_LSB) & PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_MASK)

3192

#define PCIE_INT_MASK_GM_COMP_LOOKUP_ERR_RESET 0x0 // 0

3193

#define PCIE_INT_MASK_FATAL_ERR_MSB 2

3194

#define PCIE_INT_MASK_FATAL_ERR_LSB 2

3195

#define PCIE_INT_MASK_FATAL_ERR_MASK 0x00000004

3196

#define PCIE_INT_MASK_FATAL_ERR_GET(x) (((x) & PCIE_INT_MASK_FATAL_ERR_MASK) >> PCIE_INT_MASK_FATAL_ERR_LSB)

3197

#define PCIE_INT_MASK_FATAL_ERR_SET(x) (((x) << PCIE_INT_MASK_FATAL_ERR_LSB) & PCIE_INT_MASK_FATAL_ERR_MASK)

3198

#define PCIE_INT_MASK_FATAL_ERR_RESET 0x0 // 0

3199

#define PCIE_INT_MASK_NONFATAL_ERR_MSB 1

3200

#define PCIE_INT_MASK_NONFATAL_ERR_LSB 1

3201

#define PCIE_INT_MASK_NONFATAL_ERR_MASK 0x00000002

3202

#define PCIE_INT_MASK_NONFATAL_ERR_GET(x) (((x) & PCIE_INT_MASK_NONFATAL_ERR_MASK) >> PCIE_INT_MASK_NONFATAL_ERR_LSB)

3203

#define PCIE_INT_MASK_NONFATAL_ERR_SET(x) (((x) << PCIE_INT_MASK_NONFATAL_ERR_LSB) & PCIE_INT_MASK_NONFATAL_ERR_MASK)

3204

#define PCIE_INT_MASK_NONFATAL_ERR_RESET 0x0 // 0

3205

#define PCIE_INT_MASK_CORR_ERR_MSB 0

3206

#define PCIE_INT_MASK_CORR_ERR_LSB 0

3207

#define PCIE_INT_MASK_CORR_ERR_MASK 0x00000001

3208

#define PCIE_INT_MASK_CORR_ERR_GET(x) (((x) & PCIE_INT_MASK_CORR_ERR_MASK) >> PCIE_INT_MASK_CORR_ERR_LSB)

3209

#define PCIE_INT_MASK_CORR_ERR_SET(x) (((x) << PCIE_INT_MASK_CORR_ERR_LSB) & PCIE_INT_MASK_CORR_ERR_MASK)

3210

#define PCIE_INT_MASK_CORR_ERR_RESET 0x0 // 0

3211

#define PCIE_INT_MASK_ADDRESS 0x18280050

3212

3213

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_MSB 17

3214

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_LSB 17

3215

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_MASK 0x00020000

3216

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_GET(x) (((x) & PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_MASK) >> PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_LSB)

3217

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_SET(x) (((x) << PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_LSB) & PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_MASK)

3218

#define PCIE_DEBUG_AHB_MSTR_DATA_SWAP_EN_RESET 0x0 // 0

3219

#define PCIE_DEBUG_PCIE_PHY_READY_MSB 16

3220

#define PCIE_DEBUG_PCIE_PHY_READY_LSB 16

3221

#define PCIE_DEBUG_PCIE_PHY_READY_MASK 0x00010000

3222

#define PCIE_DEBUG_PCIE_PHY_READY_GET(x) (((x) & PCIE_DEBUG_PCIE_PHY_READY_MASK) >> PCIE_DEBUG_PCIE_PHY_READY_LSB)

3223

#define PCIE_DEBUG_PCIE_PHY_READY_SET(x) (((x) << PCIE_DEBUG_PCIE_PHY_READY_LSB) & PCIE_DEBUG_PCIE_PHY_READY_MASK)

3224

#define PCIE_DEBUG_PCIE_PHY_READY_RESET 0x0 // 0

3225

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_MSB 15

3226

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_LSB 15

3227

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_MASK 0x00008000

3228

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_GET(x) (((x) & PCIE_DEBUG_RXVALID_EXT_ENABLE_MASK) >> PCIE_DEBUG_RXVALID_EXT_ENABLE_LSB)

3229

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_SET(x) (((x) << PCIE_DEBUG_RXVALID_EXT_ENABLE_LSB) & PCIE_DEBUG_RXVALID_EXT_ENABLE_MASK)

3230

#define PCIE_DEBUG_RXVALID_EXT_ENABLE_RESET 0x0 // 0

3231

#define PCIE_DEBUG_BYTESWAP_MSB 14

3232

#define PCIE_DEBUG_BYTESWAP_LSB 14

3233

#define PCIE_DEBUG_BYTESWAP_MASK 0x00004000

3234

#define PCIE_DEBUG_BYTESWAP_GET(x) (((x) & PCIE_DEBUG_BYTESWAP_MASK) >> PCIE_DEBUG_BYTESWAP_LSB)

3235

#define PCIE_DEBUG_BYTESWAP_SET(x) (((x) << PCIE_DEBUG_BYTESWAP_LSB) & PCIE_DEBUG_BYTESWAP_MASK)

3236

#define PCIE_DEBUG_BYTESWAP_RESET 0x0 // 0

3237

#define PCIE_DEBUG_PM_STATUS_MSB 13

3238

#define PCIE_DEBUG_PM_STATUS_LSB 13

3239

#define PCIE_DEBUG_PM_STATUS_MASK 0x00002000

3240

#define PCIE_DEBUG_PM_STATUS_GET(x) (((x) & PCIE_DEBUG_PM_STATUS_MASK) >> PCIE_DEBUG_PM_STATUS_LSB)

3241

#define PCIE_DEBUG_PM_STATUS_SET(x) (((x) << PCIE_DEBUG_PM_STATUS_LSB) & PCIE_DEBUG_PM_STATUS_MASK)

3242

#define PCIE_DEBUG_PM_STATUS_RESET 0x0 // 0

3243

#define PCIE_DEBUG_PM_PME_EN_MSB 12

3244

#define PCIE_DEBUG_PM_PME_EN_LSB 12

3245

#define PCIE_DEBUG_PM_PME_EN_MASK 0x00001000

3246

#define PCIE_DEBUG_PM_PME_EN_GET(x) (((x) & PCIE_DEBUG_PM_PME_EN_MASK) >> PCIE_DEBUG_PM_PME_EN_LSB)

3247

#define PCIE_DEBUG_PM_PME_EN_SET(x) (((x) << PCIE_DEBUG_PM_PME_EN_LSB) & PCIE_DEBUG_PM_PME_EN_MASK)

3248

#define PCIE_DEBUG_PM_PME_EN_RESET 0x0 // 0

3249

#define PCIE_DEBUG_PM_DSTATE_MSB 11

3250

#define PCIE_DEBUG_PM_DSTATE_LSB 9

3251

#define PCIE_DEBUG_PM_DSTATE_MASK 0x00000e00

3252

#define PCIE_DEBUG_PM_DSTATE_GET(x) (((x) & PCIE_DEBUG_PM_DSTATE_MASK) >> PCIE_DEBUG_PM_DSTATE_LSB)

3253

#define PCIE_DEBUG_PM_DSTATE_SET(x) (((x) << PCIE_DEBUG_PM_DSTATE_LSB) & PCIE_DEBUG_PM_DSTATE_MASK)

3254

#define PCIE_DEBUG_PM_DSTATE_RESET 0x0 // 0

3255

#define PCIE_DEBUG_XMLH_LTSSM_STATE_MSB 8

3256

#define PCIE_DEBUG_XMLH_LTSSM_STATE_LSB 4

3257

#define PCIE_DEBUG_XMLH_LTSSM_STATE_MASK 0x000001f0

3258

#define PCIE_DEBUG_XMLH_LTSSM_STATE_GET(x) (((x) & PCIE_DEBUG_XMLH_LTSSM_STATE_MASK) >> PCIE_DEBUG_XMLH_LTSSM_STATE_LSB)

3259

#define PCIE_DEBUG_XMLH_LTSSM_STATE_SET(x) (((x) << PCIE_DEBUG_XMLH_LTSSM_STATE_LSB) & PCIE_DEBUG_XMLH_LTSSM_STATE_MASK)

3260

#define PCIE_DEBUG_XMLH_LTSSM_STATE_RESET 0x0 // 0

3261

#define PCIE_DEBUG_PM_CURNT_STATE_MSB 3

3262

#define PCIE_DEBUG_PM_CURNT_STATE_LSB 1

3263

#define PCIE_DEBUG_PM_CURNT_STATE_MASK 0x0000000e

3264

#define PCIE_DEBUG_PM_CURNT_STATE_GET(x) (((x) & PCIE_DEBUG_PM_CURNT_STATE_MASK) >> PCIE_DEBUG_PM_CURNT_STATE_LSB)

3265

#define PCIE_DEBUG_PM_CURNT_STATE_SET(x) (((x) << PCIE_DEBUG_PM_CURNT_STATE_LSB) & PCIE_DEBUG_PM_CURNT_STATE_MASK)

3266

#define PCIE_DEBUG_PM_CURNT_STATE_RESET 0x0 // 0

3267

#define PCIE_DEBUG_RDLH_LINK_UP_MSB 0

3268

#define PCIE_DEBUG_RDLH_LINK_UP_LSB 0

3269

#define PCIE_DEBUG_RDLH_LINK_UP_MASK 0x00000001

3270

#define PCIE_DEBUG_RDLH_LINK_UP_GET(x) (((x) & PCIE_DEBUG_RDLH_LINK_UP_MASK) >> PCIE_DEBUG_RDLH_LINK_UP_LSB)

3271

#define PCIE_DEBUG_RDLH_LINK_UP_SET(x) (((x) << PCIE_DEBUG_RDLH_LINK_UP_LSB) & PCIE_DEBUG_RDLH_LINK_UP_MASK)

3272

#define PCIE_DEBUG_RDLH_LINK_UP_RESET 0x0 // 0

3273

#define PCIE_DEBUG_ADDRESS 0x1828001c

3274

3275

#define XTAL2_SEC_TDC_COUNT_MSB 31

3276

#define XTAL2_SEC_TDC_COUNT_LSB 27

3277

#define XTAL2_SEC_TDC_COUNT_MASK 0xF8000000

3278

#define XTAL2_SEC_TDC_COUNT_GET(x) (((x) & XTAL2_SEC_TDC_COUNT_MASK) >> XTAL2_SEC_TDC_COUNT_LSB)

3279

#define XTAL2_SEC_TDC_COUNT_SET(x) (((x) << XTAL2_SEC_TDC_COUNT_LSB) & XTAL2_SEC_TDC_COUNT_MASK)

3280

#define XTAL2_SEC_TDC_COUNT_RESET 0x0 // 0

3281

#define XTAL2_SEC_TDC_PH_COUNT_MSB 26

3282

#define XTAL2_SEC_TDC_PH_COUNT_LSB 22

3283

#define XTAL2_SEC_TDC_PH_COUNT_MASK 0x007C0000

3284

#define XTAL2_SEC_TDC_PH_COUNT_GET(x) (((x) & XTAL2_SEC_TDC_PH_COUNT_MASK) >> XTAL2_SEC_TDC_PH_COUNT_LSB)

3285

#define XTAL2_SEC_TDC_PH_COUNT_SET(x) (((x) << XTAL2_SEC_TDC_PH_COUNT_LSB) & XTAL2_SEC_TDC_PH_COUNT_MASK)

3286

#define XTAL2_SEC_TDC_PH_COUNT_RESET 0x0 // 0

3287

#define XTAL2_SEC_DUTY_UP_MSB 21

3288

#define XTAL2_SEC_DUTY_UP_LSB 17

3289

#define XTAL2_SEC_DUTY_UP_MASK 0x0003E0000

3290

#define XTAL2_SEC_DUTY_UP_GET(x) (((x) & XTAL2_SEC_DUTY_UP_MASK) >> XTAL2_SEC_DUTY_UP_LSB)

3291

#define XTAL2_SEC_DUTY_UP_SET(x) (((x) << XTAL2_SEC_DUTY_UP_LSB) & XTAL2_SEC_DUTY_UP_MASK)

3292

#define XTAL2_SEC_DUTY_UP_RESET 0x0 // 0

3293

#define XTAL2_SEC_DUTY_DN_MSB 16

3294

#define XTAL2_SEC_DUTY_DN_LSB 12

3295

#define XTAL2_SEC_DUTY_DN_MASK 0x0001F000

3296

#define XTAL2_SEC_DUTY_DN_GET(x) (((x) & XTAL2_SEC_DUTY_DN_MASK) >> XTAL2_SEC_DUTY_DN_LSB)

3297

#define XTAL2_SEC_DUTY_DN_SET(x) (((x) << XTAL2_SEC_DUTY_DN_LSB) & XTAL2_SEC_DUTY_DN_MASK)

3298

#define XTAL2_SEC_DUTY_DN_RESET 0x0 // 0

3299

#define XTAL2_SEC_DCA_BYPASS_MSB 11

3300

#define XTAL2_SEC_DCA_BYPASS_LSB 11

3301

#define XTAL2_SEC_DCA_BYPASS_MASK 0x00000800

3302

#define XTAL2_SEC_DCA_BYPASS_GET(x) (((x) & XTAL2_SEC_DCA_BYPASS_MASK) >> XTAL2_SEC_DCA_BYPASS_LSB)

3303

#define XTAL2_SEC_DCA_BYPASS_SET(x) (((x) << XTAL2_SEC_DCA_BYPASS_LSB) & XTAL2_SEC_DCA_BYPASS_MASK)

3304

#define XTAL2_SEC_DCA_BYPASS_RESET 0x1 // 1

3305

#define XTAL2_SEC_DCA_SWCAL_MSB 10

3306

#define XTAL2_SEC_DCA_SWCAL_LSB 10

3307

#define XTAL2_SEC_DCA_SWCAL_MASK 0x00000400

3308

#define XTAL2_SEC_DCA_SWCAL_GET(x) (((x) & XTAL2_SEC_DCA_SWCAL_MASK) >> XTAL2_SEC_DCA_SWCAL_LSB)

3309

#define XTAL2_SEC_DCA_SWCAL_SET(x) (((x) << XTAL2_SEC_DCA_SWCAL_LSB) & XTAL2_SEC_DCA_SWCAL_MASK)

3310

#define XTAL2_SEC_DCA_SWCAL_RESET 0x0 // 0

3311

#define XTAL2_SEC_DCA_COUNT_LIMIT_MSB 9

3312

#define XTAL2_SEC_DCA_COUNT_LIMIT_LSB 9

3313

#define XTAL2_SEC_DCA_COUNT_LIMIT_MASK 0x00000200

3314

#define XTAL2_SEC_DCA_COUNT_LIMIT_GET(x) (((x) & XTAL2_SEC_DCA_COUNT_LIMIT_MASK) >> XTAL2_SEC_DCA_COUNT_LIMIT_LSB)

3315

#define XTAL2_SEC_DCA_COUNT_LIMIT_SET(x) (((x) << XTAL2_SEC_DCA_COUNT_LIMIT_LSB) & XTAL2_SEC_DCA_COUNT_LIMIT_MASK)

3316

#define XTAL2_SEC_DCA_COUNT_LIMIT_RESET 0x1 // 1

3317

#define XTAL2_SEC_DCA_COUNT_EN_MSB 8

3318

#define XTAL2_SEC_DCA_COUNT_EN_LSB 8

3319

#define XTAL2_SEC_DCA_COUNT_EN_MASK 0x00000100

3320

#define XTAL2_SEC_DCA_COUNT_EN_GET(x) (((x) & XTAL2_SEC_DCA_COUNT_EN_MASK) >> XTAL2_SEC_DCA_COUNT_EN_LSB)

3321

#define XTAL2_SEC_DCA_COUNT_EN_SET(x) (((x) << XTAL2_SEC_DCA_COUNT_EN_LSB) & XTAL2_SEC_DCA_COUNT_EN_MASK)

3322

#define XTAL2_SEC_DCA_COUNT_EN_RESET 0x1 // 1

3323

#define XTAL2_SEC_SPARE_MSB 7

3324

#define XTAL2_SEC_SPARE_LSB 0

3325

#define XTAL2_SEC_SPARE_MASK 0x000000FF

3326

#define XTAL2_SEC_SPARE_GET(x) (((x) & XTAL2_SEC_SPARE_MASK) >> XTAL2_SEC_SPARE_LSB)

3327

#define XTAL2_SEC_SPARE_SET(x) (((x) << XTAL2_SEC_SPARE_LSB) & XTAL2_SEC_SPARE_MASK)

3328

#define XTAL2_SEC_SPARE_RESET 0x0 // 0

3329

#define XTAL2_SEC_ADDRESS 0x18116294

3330

3331

//#define CONFIG_MIPS32 1 /* MIPS32 CPU core */ /* Moved to QCA956x board config */

3332

3333

//#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */ /* Moved to QCA956x board config */

3334

3335

//#define CONFIG_BAUDRATE 115200 /* Moved to QCA956x board config */

3336

//#define CFG_BAUDRATE_TABLE {115200} /* Moved to QCA956x board config */

3337

3338

//#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* Moved to QCA956x board config */

3339

3340

#define CONFIG_ROOTFS_RD

3341

3342

#define CONFIG_BOOTARGS_RD "console=ttyS0,115200 root=01:00 rd_start=0x802d0000 rd_size=5242880 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),4096k(rootfs),2048k(uImage)"

3343

3344

/* XXX - putting rootfs in last partition results in jffs errors */

3345

#define CONFIG_BOOTARGS_FL "console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),5120k(rootfs),2048k(uImage)"

3346

3347

#ifdef CONFIG_ROOTFS_FLASH

3348

#define CONFIG_BOOTARGS CONFIG_BOOTARGS_FL

3349

#else

3350

#define CONFIG_BOOTARGS ""

#endif

/*

* Miscellaneous configurable options

3355

*/

3356

#define CFG_LONGHELP /* undef to save memory */

3357

#define CFG_PROMPT "ath> " /* Monitor Command Prompt */

3358

#define CFG_CBSIZE 512 /* Console I/O Buffer Size */

3359

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */

3360

#define CFG_MAXARGS 16 /* max number of command args*/

3361

3362

/*#define CFG_MALLOC_LEN (128*1024) CONFIG_SYS_MALLOC_LEN */ /* Moved to QCA956x board config */

Prabhu Jayakumar

c4c0122

2016-05-03 18:19:18 +0530

[diff] [blame]

3363

#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */

3364

/* #define CONFIG_SYS_LOAD_ADDR 0x81000000 */ /* default load address */ /* Moved to QCA956x board config */

3365

3366

#define CFG_MEMTEST_START 0x80100000

3367

#undef CFG_MEMTEST_START

3368

#define CFG_MEMTEST_START 0x80200000

3369

#define CFG_MEMTEST_END 0x83800000

3370

3371

/*------------------------------------------------------------------------

3372

* * * JFFS2

3373

*/

3374

#define CFG_JFFS_CUSTOM_PART /* board defined part */

3375

#define CONFIG_JFFS2_CMDLINE

3376

#define MTDIDS_DEFAULT "nor0=ath-nor0"

3377

3378

#define CONFIG_MEMSIZE_IN_BYTES

/*-----------------------------------------------------------------------

3383

* Cache Configuration

3384

*/

3385

//#define CFG_DCACHE_SIZE 32768 /* Moved to QCA956x board config */

3386

//#define CFG_ICACHE_SIZE 65536 /* Moved to QCA956x board config */

3387

//#define CFG_CACHELINE_SIZE 32 /* Moved to QCA956x board config */

/*

* Address map

*/

#define ATH_PCI_MEM_BASE 0x10000000 /* 128M */

3393

#define ATH_APB_BASE 0x18000000 /* 384M */

3394

#define ATH_GE0_BASE 0x19000000 /* 16M */

3395

#define ATH_GE1_BASE 0x1a000000 /* 16M */

3396

#define ATH_USB_OHCI_BASE 0x1b000000

3397

#define ATH_USB_EHCI_BASE 0x1b000000

3398

#define ATH_USB_EHCI_BASE_1 0x1b000000

3399

#define ATH_USB_EHCI_BASE_2 0x1b400000

3400

#define ATH_SPI_BASE 0x1f000000

3401

3402

/*

3403

* Added the PCI LCL RESET register from u-boot

3404

* ath_soc.h so that we can query the PCI LCL RESET

3405

* register for the presence of WLAN H/W.

3406

*/

3407

3408

#define ATH_PCI_LCL_BASE (ATH_APB_BASE+0x00280000)

3409

#define ATH_PCI_LCL_APP (ATH_PCI_LCL_BASE+0x00)

3410

#define ATH_PCI_LCL_RESET (ATH_PCI_LCL_BASE+0x18)

/*

* APB block

*/

#define ATH_DDR_CTL_BASE ATH_APB_BASE+0x00000000

3416

#define ATH_CPU_BASE ATH_APB_BASE+0x00010000

3417

#define ATH_UART_BASE ATH_APB_BASE+0x00020000

3418

#define ATH_USB_CONFIG_BASE ATH_APB_BASE+0x00030000

3419

#define ATH_GPIO_BASE ATH_APB_BASE+0x00040000

3420

#define ATH_PLL_BASE ATH_APB_BASE+0x00050000

3421

#define ATH_RESET_BASE ATH_APB_BASE+0x00060000

3422

#define ATH_DMA_BASE ATH_APB_BASE+0x000A0000

3423

#define ATH_PCI_CTLR_BASE ATH_APB_BASE+0x00280000

3424

3425

#define ATH_NAND_FLASH_BASE 0x1b800000u

3426

#define ATH_GPIO_OE ATH_GPIO_BASE+0x0

/*

* DDR Config values

*/

#define ATH_DDR_CONFIG_16BIT (1 << 31)

3432

#define ATH_DDR_CONFIG_PAGE_OPEN (1 << 30)

3433

#define ATH_DDR_CONFIG_CAS_LAT_SHIFT 27

3434

#define ATH_DDR_CONFIG_TMRD_SHIFT 23

3435

#define ATH_DDR_CONFIG_TRFC_SHIFT 17

3436

#define ATH_DDR_CONFIG_TRRD_SHIFT 13

3437

#define ATH_DDR_CONFIG_TRP_SHIFT 9

3438

#define ATH_DDR_CONFIG_TRCD_SHIFT 5

3439

#define ATH_DDR_CONFIG_TRAS_SHIFT 0

3440

3441

#define ATH_DDR_CONFIG2_BL2 (2 << 0)

3442

#define ATH_DDR_CONFIG2_BL4 (4 << 0)

3443

#define ATH_DDR_CONFIG2_BL8 (8 << 0)

3444

3445

#define ATH_DDR_CONFIG2_BT_IL (1 << 4)

3446

#define ATH_DDR_CONFIG2_CNTL_OE_EN (1 << 5)

3447

#define ATH_DDR_CONFIG2_PHASE_SEL (1 << 6)

3448

#define ATH_DDR_CONFIG2_DRAM_CKE (1 << 7)

3449

#define ATH_DDR_CONFIG2_TWR_SHIFT 8

3450

#define ATH_DDR_CONFIG2_TRTW_SHIFT 12

3451

#define ATH_DDR_CONFIG2_TRTP_SHIFT 17

3452

#define ATH_DDR_CONFIG2_TWTR_SHIFT 21

3453

#define ATH_DDR_CONFIG2_HALF_WIDTH_L (1 << 31)

3454

3455

#define ATH_DDR_TAP_DEFAULT 0x10

3456

3457

/*

3458

* DDR block, gmac flushing

3459

*/

3460

#define ATH_DDR_GE0_FLUSH ATH_DDR_CTL_BASE+0x9c

3461

#define ATH_DDR_GE1_FLUSH ATH_DDR_CTL_BASE+0xa0

3462

#define ATH_DDR_USB_FLUSH ATH_DDR_CTL_BASE+0xa4

3463

#define ATH_DDR_PCIE_FLUSH ATH_DDR_CTL_BASE+0xa8

3464

3465

#define ATH_EEPROM_GE0_MAC_ADDR 0xbfff1000

3466

#define ATH_EEPROM_GE1_MAC_ADDR 0xbfff1006

/*

* PLL block/CPU

*/

#define ATH_PLL_CONFIG ATH_PLL_BASE+0x0

3473

#define ATH_PLL_CONFIG1 ATH_PLL_BASE+0x4

3474

#define ATH_DDR_CLK_CTRL ATH_PLL_BASE+0x10

3475

3476

#define ATH_DDR_PLL_CONFIG ATH_PLL_BASE+0x8

3477

#define ATH_DDR_PLL_CONFIG1 ATH_PLL_BASE+0xc

3478

#define ATH_ETH_XMII_CONFIG ATH_PLL_BASE+0x30

/*

* USB block

*/

#define ATH_USB_FLADJ_VAL ATH_USB_CONFIG_BASE

3485

#define ATH_USB_CONFIG ATH_USB_CONFIG_BASE+0x4

3486

#define ATH_USB_WINDOW 0x10000

3487

#define ATH_USB_MODE ATH_USB_EHCI_BASE+0x1a8

/*

* PCI block

*/

#define ATH_PCI_WINDOW 0x8000000 /* 128MB */

3493

#define ATH_PCI_WINDOW0_OFFSET ATH_DDR_CTL_BASE+0x7c

3494

#define ATH_PCI_WINDOW1_OFFSET ATH_DDR_CTL_BASE+0x80

3495

#define ATH_PCI_WINDOW2_OFFSET ATH_DDR_CTL_BASE+0x84

3496

#define ATH_PCI_WINDOW3_OFFSET ATH_DDR_CTL_BASE+0x88

3497

#define ATH_PCI_WINDOW4_OFFSET ATH_DDR_CTL_BASE+0x8c

3498

#define ATH_PCI_WINDOW5_OFFSET ATH_DDR_CTL_BASE+0x90

3499

#define ATH_PCI_WINDOW6_OFFSET ATH_DDR_CTL_BASE+0x94

3500

#define ATH_PCI_WINDOW7_OFFSET ATH_DDR_CTL_BASE+0x98

3501

3502

#define ATH_PCI_WINDOW0_VAL 0x10000000

3503

#define ATH_PCI_WINDOW1_VAL 0x11000000

3504

#define ATH_PCI_WINDOW2_VAL 0x12000000

3505

#define ATH_PCI_WINDOW3_VAL 0x13000000

3506

#define ATH_PCI_WINDOW4_VAL 0x14000000

3507

#define ATH_PCI_WINDOW5_VAL 0x15000000

3508

#define ATH_PCI_WINDOW6_VAL 0x16000000

3509

#define ATH_PCI_WINDOW7_VAL 0x07000000

3510

3511

#define ath_write_pci_window(_no) \

3512

ath_reg_wr(ATH_PCI_WINDOW##_no##_OFFSET, ATH_PCI_WINDOW##_no##_VAL);

3513

3514

/*

3515

* CRP. To access the host controller config and status registers

3516

*/

3517

3518

//#define ATH_PCI_CRP 0x180c0000

3519

//#define ATH_PCI_DEV_CFGBASE 0x14000000

3520

#define ATH_PCI_CRP 0x18250000

3521

#define ATH_PCI_DEV_CFGBASE 0x16000000

3522

#define ATH_PCI_CRP_AD_CBE ATH_PCI_CRP

3523

#define ATH_PCI_CRP_WRDATA ATH_PCI_CRP+0x4

3524

#define ATH_PCI_CRP_RDDATA ATH_PCI_CRP+0x8

3525

#define ATH_PCI_ERROR ATH_PCI_CRP+0x1c

3526

#define ATH_PCI_ERROR_ADDRESS ATH_PCI_CRP+0x20

3527

#define ATH_PCI_AHB_ERROR ATH_PCI_CRP+0x24

3528

#define ATH_PCI_AHB_ERROR_ADDRESS ATH_PCI_CRP+0x28

3529

3530

#define ATH_CRP_CMD_WRITE 0x00010000

3531

#define ATH_CRP_CMD_READ 0x00000000

3532

3533

/*

3534

* PCI CFG. To generate config cycles

3535

*/

3536

#define ATH_PCI_CFG_AD ATH_PCI_CRP+0xc

3537

#define ATH_PCI_CFG_CBE ATH_PCI_CRP+0x10

3538

#define ATH_PCI_CFG_WRDATA ATH_PCI_CRP+0x14

3539

#define ATH_PCI_CFG_RDDATA ATH_PCI_CRP+0x18

3540

#define ATH_CFG_CMD_READ 0x0000000a

3541

#define ATH_CFG_CMD_WRITE 0x0000000b

3542

3543

#define ATH_PCI_IDSEL_ADLINE_START 17

3544

3545

#define ATH_SPI_FS (ATH_SPI_BASE+0x00)

3546

#define ATH_SPI_READ (ATH_SPI_BASE+0x00)

3547

#define ATH_SPI_CLOCK (ATH_SPI_BASE+0x04)

3548

#define ATH_SPI_WRITE (ATH_SPI_BASE+0x08)

3549

#define ATH_SPI_RD_STATUS (ATH_SPI_BASE+0x0c)

3550

#define ATH_SPI_SHIFT_DO (ATH_SPI_BASE+0x10)

3551

#define ATH_SPI_SHIFT_CNT (ATH_SPI_BASE+0x14)

3552

#define ATH_SPI_SHIFT_DI (ATH_SPI_BASE+0x18)

3553

#define ATH_SPI_D0_HIGH (1<<0) /* Pin spi_do */

3554

#define ATH_SPI_CLK_HIGH (1<<8) /* Pin spi_clk */

3555

3556

#define ATH_SPI_CS_ENABLE_0 (6<<16) /* Pin gpio/cs0 (active low) */

3557

#define ATH_SPI_CS_ENABLE_1 (5<<16) /* Pin gpio/cs1 (active low) */

3558

#define ATH_SPI_CS_ENABLE_2 (3<<16) /* Pin gpio/cs2 (active low) */

3559

#define ATH_SPI_CS_DIS 0x70000

3560

#define ATH_SPI_CE_LOW 0x60000

3561

#define ATH_SPI_CE_HIGH 0x60100

3562

3563

#define ATH_SPI_SECTOR_SIZE (1024*64)

3564

#define ATH_SPI_PAGE_SIZE 256

3565

3566

#define ATH_RESET_GE0_MAC RST_RESET_GE0_MAC_RESET_SET(1)

3567

#define ATH_RESET_GE0_PHY (0) // Nothing similar to wasp??

3568

#define ATH_RESET_GE1_MAC RST_RESET_GE1_MAC_RESET_SET(1)

3569

#define ATH_RESET_GE1_PHY (0) // Nothing similar to wasp??

3570

#define ATH_RESET_GE0_MDIO RST_RESET_GE0_MDIO_RESET_SET(1)

3571

#define ATH_RESET_GE1_MDIO RST_RESET_GE1_MDIO_RESET_SET(1)

/*

* SOC

*/

#define ATH_SPI_CMD_WRITE_SR 0x01

3577

#define ATH_SPI_CMD_WREN 0x06

3578

#define ATH_SPI_CMD_RD_STATUS 0x05

3579

#define ATH_SPI_CMD_FAST_READ 0x0b

3580

#define ATH_SPI_CMD_PAGE_PROG 0x02

3581

#define ATH_SPI_CMD_SECTOR_ERASE 0xd8

3582

#define ATH_SPI_CMD_CHIP_ERASE 0xc7

3583

#define ATH_SPI_CMD_RDID 0x9f

3584

3585

#if defined(CFG_ATH_EMULATION)

3586

3587

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(2) // 80 MHz

3588

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(1) // 40 MHz

3589

3590

#elif (CFG_PLL_FREQ == CFG_PLL_750_400_250) //DDR1 CAL = 3

3591

3592

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3593

3594

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1e)

3595

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3596

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3597

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3598

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3599

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3600

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3601

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3602

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3603

3604

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3605

3606

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x20)

3607

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3608

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3609

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3610

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3611

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3612

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3613

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3614

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3615

3616

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3617

3618

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3619

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3620

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3621

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3622

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3623

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3624

3625

#define DDR_FSM_WAIT_CTRL_VAL 0xa24

3626

3627

#elif (CFG_PLL_FREQ == CFG_PLL_775_650_258) //DDR2 CAL = 5

3628

3629

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3630

3631

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1f)

3632

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3633

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3634

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3635

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3636

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3637

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3638

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3639

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3640

3641

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3642

3643

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

3644

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3645

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3646

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3647

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3648

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3649

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3650

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3651

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3652

3653

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3654

3655

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3656

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3657

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3658

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3659

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3660

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3661

3662

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3663

3664

#elif (CFG_PLL_FREQ == CFG_PLL_800_450_266) //DDR2 CAL = 4

3665

3666

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3667

3668

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3669

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3670

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3671

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3672

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3673

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3674

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3675

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3676

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3677

3678

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3679

3680

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x24)

3681

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3682

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3683

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3684

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3685

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3686

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3687

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3688

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3689

3690

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3691

3692

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3693

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3694

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3695

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3696

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3697

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3698

3699

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3700

3701

#elif (CFG_PLL_FREQ == CFG_PLL_800_533_266) //DDR2 CAL = 5

3702

3703

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3704

3705

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3706

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3707

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3708

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3709

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3710

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3711

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3712

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3713

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3714

3715

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3716

3717

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x2a)

3718

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3719

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3720

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3721

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

3722

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3723

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x28f56) | \

3724

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3725

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3726

3727

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3728

3729

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3730

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3731

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3732

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3733

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3734

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3735

3736

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3737

3738

#elif (CFG_PLL_FREQ == CFG_PLL_800_600_266) //DDR2 CAL = 5

3739

3740

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3741

3742

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3743

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3744

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3745

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3746

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3747

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3748

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3749

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3750

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3751

3752

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3753

3754

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x18)

3755

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3756

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3757

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3758

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3759

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3760

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3761

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3762

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3763

3764

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3765

3766

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3767

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3768

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3769

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3770

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3771

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3772

3773

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3774

3775

#elif (CFG_PLL_FREQ == CFG_PLL_800_600_300) //DDR2 CAL = 5

3776

3777

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3778

3779

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3780

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3781

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3782

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3783

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3784

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3785

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3786

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3787

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3788

3789

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3790

3791

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x18)

3792

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3793

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3794

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3795

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3796

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3797

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3798

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3799

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3800

3801

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3802

3803

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0x1)

3804

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3805

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3806

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x1)

3807

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3808

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3809

3810

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3811

3812

#elif (CFG_PLL_FREQ == CFG_PLL_800_666_266) //DDR2 CAL = 5

3813

3814

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3815

3816

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3817

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3818

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3819

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3820

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3821

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3822

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3823

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3824

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3825

3826

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3827

3828

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

3829

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3830

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3831

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3832

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3833

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3834

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x28f56) | \

3835

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3836

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3837

3838

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3839

3840

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3841

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3842

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3843

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3844

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3845

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3846

3847

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3848

3849

#elif (CFG_PLL_FREQ == CFG_PLL_800_667_266) //DDR2 CAL = 6

3850

3851

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3852

3853

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3854

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3855

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3856

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3857

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3858

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3859

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3860

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3861

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3862

3863

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3864

3865

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

3866

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3867

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3868

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3869

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3870

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3871

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x2b84e) | \

3872

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3873

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3874

3875

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3876

3877

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3878

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3879

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3880

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3881

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3882

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3883

3884

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3885

3886

#elif (CFG_PLL_FREQ == CFG_PLL_750_667_250) //DDR2 CAL = 6

3887

3888

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3889

3890

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1e)

3891

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3892

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3893

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3894

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3895

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3896

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3897

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3898

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3899

3900

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3901

3902

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

3903

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3904

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3905

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3906

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3907

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3908

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x2b84e) | \

3909

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3910

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3911

3912

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3913

3914

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3915

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3916

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3917

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3918

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3919

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3920

3921

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3922

3923

#elif (CFG_PLL_FREQ == CFG_PLL_800_700_266) //DDR2 CAL = 6

3924

3925

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3926

3927

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3928

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3929

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3930

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3931

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3932

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3933

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

3934

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3935

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3936

3937

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3938

3939

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1c)

3940

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3941

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3942

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3943

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3944

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3945

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x0) | \

3946

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3947

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3948

3949

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3950

3951

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3952

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3953

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3954

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3955

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3956

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3957

3958

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3959

3960

#elif (CFG_PLL_FREQ == CFG_PLL_810_666_270) //DDR2 CAL = 5

3961

3962

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

3963

3964

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

3965

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

3966

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

3967

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

3968

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

3969

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

3970

CPU_PLL_DITHER1_NFRAC_MIN_SET(0x19994) | \

3971

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3972

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3973

3974

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3975

3976

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

3977

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

3978

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

3979

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

3980

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

3981

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

3982

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x28f56) | \

3983

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

3984

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

3985

3986

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

3987

3988

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

3989

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

3990

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

3991

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

3992

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

3993

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

3994

3995

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

3996

3997

#elif (CFG_PLL_FREQ == CFG_PLL_810_700_270) //DDR2 CAL = 6

3998

3999

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

4000

4001

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

4002

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

4003

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

4004

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

4005

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

4006

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

4007

CPU_PLL_DITHER1_NFRAC_MIN_SET(0x19994) | \

4008

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4009

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4010

4011

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4012

4013

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1c)

4014

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

4015

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

4016

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0)

4017

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0)

4018

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

4019

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x0) | \

4020

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4021

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4022

4023

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4024

4025

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

4026

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

4027

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

4028

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

4029

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

4030

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

4031

4032

#define DDR_FSM_WAIT_CTRL_VAL 0xa12

4033

4034

#elif (CFG_PLL_FREQ == CFG_PLL_750_393_196) //DDR1 CAL = 3

4035

4036

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

4037

4038

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x1e)

4039

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

4040

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

4041

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

4042

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

4043

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

4044

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

4045

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4046

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4047

4048

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4049

4050

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1f)

4051

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

4052

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

4053

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4054

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4055

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

4056

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x1c28c) | \

4057

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4058

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4059

4060

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4061

4062

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0x1)

4063

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

4064

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

4065

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x1)

4066

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

4067

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

4068

4069

#define DDR_FSM_WAIT_CTRL_VAL 0xa24

4070

4071

#elif (CFG_PLL_FREQ == CFG_PLL_810_400_270) //DDR1 CAL = 3

4072

4073

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

4074

4075

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

4076

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

4077

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

4078

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

4079

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

4080

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

4081

CPU_PLL_DITHER1_NFRAC_MIN_SET(0x19994) | \

4082

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4083

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4084

4085

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4086

4087

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x20)

4088

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

4089

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

4090

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4091

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4092

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

4093

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

4094

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4095

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4096

4097

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4098

4099

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

4100

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

4101

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

4102

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

4103

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

4104

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

4105

4106

#define DDR_FSM_WAIT_CTRL_VAL 0xa24

4107

4108

#elif (CFG_PLL_FREQ == CFG_PLL_800_333_266) //DDR1 CAL = 3

4109

4110

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

4111

4112

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

4113

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

4114

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

4115

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

4116

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

4117

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

4118

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

4119

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4120

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4121

4122

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4123

4124

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x1a)

4125

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

4126

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

4127

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4128

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4129

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

4130

DDR_PLL_DITHER1_NFRAC_MIN_SET(0x28f56) | \

4131

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4132

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4133

4134

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4135

4136

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

4137

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

4138

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

4139

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

4140

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

4141

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

4142

4143

#define DDR_FSM_WAIT_CTRL_VAL 0xa24

4144

4145

#elif (CFG_PLL_FREQ == CFG_PLL_800_400_266) //DDR1 CAL = 3

4146

4147

#define CPU_DDR_SYNC_MODE DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(0)

4148

4149

#define CPU_PLL_CONFIG1_NINT_VAL CPU_PLL_CONFIG1_NINT_SET(0x20)

4150

#define CPU_PLL_CONFIG_REF_DIV_VAL CPU_PLL_CONFIG_REFDIV_SET(0x1)

4151

#define CPU_PLL_CONFIG_RANGE_VAL CPU_PLL_CONFIG_RANGE_SET(0)

4152

#define CPU_PLL_CONFIG_OUT_DIV_VAL1 CPU_PLL_CONFIG_OUTDIV_SET(0)

4153

#define CPU_PLL_CONFIG_OUT_DIV_VAL2 CPU_PLL_CONFIG_OUTDIV_SET(0)

4154

#define CPU_PLL_DITHER1_VAL CPU_PLL_DITHER1_DITHER_EN_SET(0) | \

4155

CPU_PLL_DITHER1_NFRAC_MIN_SET(0) | \

4156

CPU_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4157

CPU_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4158

4159

#define CPU_PLL_DITHER2_VAL CPU_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4160

4161

#define DDR_PLL_CONFIG1_NINT_VAL DDR_PLL_CONFIG1_NINT_SET(0x20)

4162

#define DDR_PLL_CONFIG_REF_DIV_VAL DDR_PLL_CONFIG_REFDIV_SET(0x1)

4163

#define DDR_PLL_CONFIG_RANGE_VAL DDR_PLL_CONFIG_RANGE_SET(0)

4164

#define DDR_PLL_CONFIG_OUT_DIV_VAL1 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4165

#define DDR_PLL_CONFIG_OUT_DIV_VAL2 DDR_PLL_CONFIG_OUTDIV_SET(0x1)

4166

#define DDR_PLL_DITHER1_VAL DDR_PLL_DITHER1_DITHER_EN_SET(0) | \

4167

DDR_PLL_DITHER1_NFRAC_MIN_SET(0) | \

4168

DDR_PLL_DITHER1_NFRAC_STEP_SET(0) | \

4169

DDR_PLL_DITHER1_UPDATE_COUNT_SET(0x0)

4170

4171

#define DDR_PLL_DITHER2_VAL DDR_PLL_DITHER2_NFRAC_MAX_SET(0x0)

4172

4173

#define AHB_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(0)

4174

#define CPU_AND_DDR_CLK_FROM_DDR CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(0)

4175

#define CPU_AND_DDR_CLK_FROM_CPU CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(0)

4176

#define CPU_DDR_CLOCK_CONTROL_AHB_DIV_VAL CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(0x2)

4177

#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(0)

4178

#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(0)

4179

4180

#define DDR_FSM_WAIT_CTRL_VAL 0xa24

4181

4182

#else

4183

# error "CFG_PLL_FREQ not set"

4184

#endif // CFG_PLL_FREQ

4185

4186

#if CPU_AND_DDR_CLK_FROM_DDR && CPU_AND_DDR_CLK_FROM_CPU

4187

# error "Incorrect settings. Both 'from CPU' and 'from DDR' set"

#endif

#define __nint_to_mhz(n, ref) ((n) * (ref) * 1000000)

Prabhu Jayakumar

32be07e

2017-01-06 18:58:22 +0530

[diff] [blame]

4193

#define __cpu_hz_40(val) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(val), 40))

4194

#define __cpu_hz_25(val) (__nint_to_mhz(CPU_PLL_CONFIG1_NINT_GET(val), 25))

Prabhu Jayakumar

c4c0122

2016-05-03 18:19:18 +0530

[diff] [blame]

4195

4196

/* Since the count is incremented every other tick, divide by 2 */

4197

#define CFG_HZ (__cpu_hz_25(CPU_PLL_CONFIG1_NINT_VAL) / 2)

/* SGMII DEFINES */

// 32'h18070034 (SGMII_CONFIG)

4202

#define SGMII_CONFIG_BERT_ENABLE_MSB 14

4203

#define SGMII_CONFIG_BERT_ENABLE_LSB 14

4204

#define SGMII_CONFIG_BERT_ENABLE_MASK 0x00004000

4205

#define SGMII_CONFIG_BERT_ENABLE_GET(x) (((x) & SGMII_CONFIG_BERT_ENABLE_MASK) >> SGMII_CONFIG_BERT_ENABLE_LSB)

4206

#define SGMII_CONFIG_BERT_ENABLE_SET(x) (((x) << SGMII_CONFIG_BERT_ENABLE_LSB) & SGMII_CONFIG_BERT_ENABLE_MASK)

4207

#define SGMII_CONFIG_BERT_ENABLE_RESET 0x0 // 0

4208

#define SGMII_CONFIG_PRBS_ENABLE_MSB 13

4209

#define SGMII_CONFIG_PRBS_ENABLE_LSB 13

4210

#define SGMII_CONFIG_PRBS_ENABLE_MASK 0x00002000

4211

#define SGMII_CONFIG_PRBS_ENABLE_GET(x) (((x) & SGMII_CONFIG_PRBS_ENABLE_MASK) >> SGMII_CONFIG_PRBS_ENABLE_LSB)

4212

#define SGMII_CONFIG_PRBS_ENABLE_SET(x) (((x) << SGMII_CONFIG_PRBS_ENABLE_LSB) & SGMII_CONFIG_PRBS_ENABLE_MASK)

4213

#define SGMII_CONFIG_PRBS_ENABLE_RESET 0x0 // 0

4214

#define SGMII_CONFIG_MDIO_COMPLETE_MSB 12

4215

#define SGMII_CONFIG_MDIO_COMPLETE_LSB 12

4216

#define SGMII_CONFIG_MDIO_COMPLETE_MASK 0x00001000

4217

#define SGMII_CONFIG_MDIO_COMPLETE_GET(x) (((x) & SGMII_CONFIG_MDIO_COMPLETE_MASK) >> SGMII_CONFIG_MDIO_COMPLETE_LSB)

4218

#define SGMII_CONFIG_MDIO_COMPLETE_SET(x) (((x) << SGMII_CONFIG_MDIO_COMPLETE_LSB) & SGMII_CONFIG_MDIO_COMPLETE_MASK)

4219

#define SGMII_CONFIG_MDIO_COMPLETE_RESET 0x0 // 0

4220

#define SGMII_CONFIG_MDIO_PULSE_MSB 11

4221

#define SGMII_CONFIG_MDIO_PULSE_LSB 11

4222

#define SGMII_CONFIG_MDIO_PULSE_MASK 0x00000800

4223

#define SGMII_CONFIG_MDIO_PULSE_GET(x) (((x) & SGMII_CONFIG_MDIO_PULSE_MASK) >> SGMII_CONFIG_MDIO_PULSE_LSB)

4224

#define SGMII_CONFIG_MDIO_PULSE_SET(x) (((x) << SGMII_CONFIG_MDIO_PULSE_LSB) & SGMII_CONFIG_MDIO_PULSE_MASK)

4225

#define SGMII_CONFIG_MDIO_PULSE_RESET 0x0 // 0

4226

#define SGMII_CONFIG_MDIO_ENABLE_MSB 10

4227

#define SGMII_CONFIG_MDIO_ENABLE_LSB 10

4228

#define SGMII_CONFIG_MDIO_ENABLE_MASK 0x00000400

4229

#define SGMII_CONFIG_MDIO_ENABLE_GET(x) (((x) & SGMII_CONFIG_MDIO_ENABLE_MASK) >> SGMII_CONFIG_MDIO_ENABLE_LSB)

4230

#define SGMII_CONFIG_MDIO_ENABLE_SET(x) (((x) << SGMII_CONFIG_MDIO_ENABLE_LSB) & SGMII_CONFIG_MDIO_ENABLE_MASK)

4231

#define SGMII_CONFIG_MDIO_ENABLE_RESET 0x0 // 0

4232

#define SGMII_CONFIG_NEXT_PAGE_LOADED_MSB 9

4233

#define SGMII_CONFIG_NEXT_PAGE_LOADED_LSB 9

4234

#define SGMII_CONFIG_NEXT_PAGE_LOADED_MASK 0x00000200

4235

#define SGMII_CONFIG_NEXT_PAGE_LOADED_GET(x) (((x) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK) >> SGMII_CONFIG_NEXT_PAGE_LOADED_LSB)

4236

#define SGMII_CONFIG_NEXT_PAGE_LOADED_SET(x) (((x) << SGMII_CONFIG_NEXT_PAGE_LOADED_LSB) & SGMII_CONFIG_NEXT_PAGE_LOADED_MASK)

4237

#define SGMII_CONFIG_NEXT_PAGE_LOADED_RESET 0x0 // 0

4238

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MSB 8

4239

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB 8

4240

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK 0x00000100

4241

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_GET(x) (((x) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK) >> SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB)

4242

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_SET(x) (((x) << SGMII_CONFIG_REMOTE_PHY_LOOPBACK_LSB) & SGMII_CONFIG_REMOTE_PHY_LOOPBACK_MASK)

4243

#define SGMII_CONFIG_REMOTE_PHY_LOOPBACK_RESET 0x0 // 0

4244

#define SGMII_CONFIG_SPEED_MSB 7

4245

#define SGMII_CONFIG_SPEED_LSB 6

4246

#define SGMII_CONFIG_SPEED_MASK 0x000000c0

4247

#define SGMII_CONFIG_SPEED_GET(x) (((x) & SGMII_CONFIG_SPEED_MASK) >> SGMII_CONFIG_SPEED_LSB)

4248

#define SGMII_CONFIG_SPEED_SET(x) (((x) << SGMII_CONFIG_SPEED_LSB) & SGMII_CONFIG_SPEED_MASK)

4249

#define SGMII_CONFIG_SPEED_RESET 0x0 // 0

4250

#define SGMII_CONFIG_FORCE_SPEED_MSB 5

4251

#define SGMII_CONFIG_FORCE_SPEED_LSB 5

4252

#define SGMII_CONFIG_FORCE_SPEED_MASK 0x00000020

4253

#define SGMII_CONFIG_FORCE_SPEED_GET(x) (((x) & SGMII_CONFIG_FORCE_SPEED_MASK) >> SGMII_CONFIG_FORCE_SPEED_LSB)

4254

#define SGMII_CONFIG_FORCE_SPEED_SET(x) (((x) << SGMII_CONFIG_FORCE_SPEED_LSB) & SGMII_CONFIG_FORCE_SPEED_MASK)

4255

#define SGMII_CONFIG_FORCE_SPEED_RESET 0x0 // 0

4256

#define SGMII_CONFIG_MR_REG4_CHANGED_MSB 4

4257

#define SGMII_CONFIG_MR_REG4_CHANGED_LSB 4

4258

#define SGMII_CONFIG_MR_REG4_CHANGED_MASK 0x00000010

4259

#define SGMII_CONFIG_MR_REG4_CHANGED_GET(x) (((x) & SGMII_CONFIG_MR_REG4_CHANGED_MASK) >> SGMII_CONFIG_MR_REG4_CHANGED_LSB)

4260

#define SGMII_CONFIG_MR_REG4_CHANGED_SET(x) (((x) << SGMII_CONFIG_MR_REG4_CHANGED_LSB) & SGMII_CONFIG_MR_REG4_CHANGED_MASK)

4261

#define SGMII_CONFIG_MR_REG4_CHANGED_RESET 0x0 // 0

4262

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MSB 3

4263

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB 3

4264

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK 0x00000008

4265

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_GET(x) (((x) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK) >> SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB)

4266

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_SET(x) (((x) << SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_LSB) & SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_MASK)

4267

#define SGMII_CONFIG_ENABLE_SGMII_TX_PAUSE_RESET 0x0 // 0

4268

#define SGMII_CONFIG_MODE_CTRL_MSB 2

4269

#define SGMII_CONFIG_MODE_CTRL_LSB 0

4270

#define SGMII_CONFIG_MODE_CTRL_MASK 0x00000007

4271

#define SGMII_CONFIG_MODE_CTRL_GET(x) (((x) & SGMII_CONFIG_MODE_CTRL_MASK) >> SGMII_CONFIG_MODE_CTRL_LSB)

4272

#define SGMII_CONFIG_MODE_CTRL_SET(x) (((x) << SGMII_CONFIG_MODE_CTRL_LSB) & SGMII_CONFIG_MODE_CTRL_MASK)

4273

#define SGMII_CONFIG_MODE_CTRL_RESET 0x0 // 0

4274

#define SGMII_CONFIG_ADDRESS 0x18070034

// 32'h1807001c (MR_AN_CONTROL)

4279

#define MR_AN_CONTROL_PHY_RESET_MSB 15

4280

#define MR_AN_CONTROL_PHY_RESET_LSB 15

4281

#define MR_AN_CONTROL_PHY_RESET_MASK 0x00008000

4282

#define MR_AN_CONTROL_PHY_RESET_GET(x) (((x) & MR_AN_CONTROL_PHY_RESET_MASK) >> MR_AN_CONTROL_PHY_RESET_LSB)

4283

#define MR_AN_CONTROL_PHY_RESET_SET(x) (((x) << MR_AN_CONTROL_PHY_RESET_LSB) & MR_AN_CONTROL_PHY_RESET_MASK)

4284

#define MR_AN_CONTROL_PHY_RESET_RESET 0x0 // 0

4285

#define MR_AN_CONTROL_LOOPBACK_MSB 14

4286

#define MR_AN_CONTROL_LOOPBACK_LSB 14

4287

#define MR_AN_CONTROL_LOOPBACK_MASK 0x00004000

4288

#define MR_AN_CONTROL_LOOPBACK_GET(x) (((x) & MR_AN_CONTROL_LOOPBACK_MASK) >> MR_AN_CONTROL_LOOPBACK_LSB)

4289

#define MR_AN_CONTROL_LOOPBACK_SET(x) (((x) << MR_AN_CONTROL_LOOPBACK_LSB) & MR_AN_CONTROL_LOOPBACK_MASK)

4290

#define MR_AN_CONTROL_LOOPBACK_RESET 0x0 // 0

4291

#define MR_AN_CONTROL_SPEED_SEL0_MSB 13

4292

#define MR_AN_CONTROL_SPEED_SEL0_LSB 13

4293

#define MR_AN_CONTROL_SPEED_SEL0_MASK 0x00002000

4294

#define MR_AN_CONTROL_SPEED_SEL0_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL0_MASK) >> MR_AN_CONTROL_SPEED_SEL0_LSB)

4295

#define MR_AN_CONTROL_SPEED_SEL0_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL0_LSB) & MR_AN_CONTROL_SPEED_SEL0_MASK)

4296

#define MR_AN_CONTROL_SPEED_SEL0_RESET 0x0 // 0

4297

#define MR_AN_CONTROL_AN_ENABLE_MSB 12

4298

#define MR_AN_CONTROL_AN_ENABLE_LSB 12

4299

#define MR_AN_CONTROL_AN_ENABLE_MASK 0x00001000

4300

#define MR_AN_CONTROL_AN_ENABLE_GET(x) (((x) & MR_AN_CONTROL_AN_ENABLE_MASK) >> MR_AN_CONTROL_AN_ENABLE_LSB)

4301

#define MR_AN_CONTROL_AN_ENABLE_SET(x) (((x) << MR_AN_CONTROL_AN_ENABLE_LSB) & MR_AN_CONTROL_AN_ENABLE_MASK)

4302

#define MR_AN_CONTROL_AN_ENABLE_RESET 0x1 // 1

4303

#define MR_AN_CONTROL_POWER_DOWN_MSB 11

4304

#define MR_AN_CONTROL_POWER_DOWN_LSB 11

4305

#define MR_AN_CONTROL_POWER_DOWN_MASK 0x00000800

4306

#define MR_AN_CONTROL_POWER_DOWN_GET(x) (((x) & MR_AN_CONTROL_POWER_DOWN_MASK) >> MR_AN_CONTROL_POWER_DOWN_LSB)

4307

#define MR_AN_CONTROL_POWER_DOWN_SET(x) (((x) << MR_AN_CONTROL_POWER_DOWN_LSB) & MR_AN_CONTROL_POWER_DOWN_MASK)

4308

#define MR_AN_CONTROL_POWER_DOWN_RESET 0x0 // 0

4309

#define MR_AN_CONTROL_RESTART_AN_MSB 9

4310

#define MR_AN_CONTROL_RESTART_AN_LSB 9

4311

#define MR_AN_CONTROL_RESTART_AN_MASK 0x00000200

4312

#define MR_AN_CONTROL_RESTART_AN_GET(x) (((x) & MR_AN_CONTROL_RESTART_AN_MASK) >> MR_AN_CONTROL_RESTART_AN_LSB)

4313

#define MR_AN_CONTROL_RESTART_AN_SET(x) (((x) << MR_AN_CONTROL_RESTART_AN_LSB) & MR_AN_CONTROL_RESTART_AN_MASK)

4314

#define MR_AN_CONTROL_RESTART_AN_RESET 0x0 // 0

4315

#define MR_AN_CONTROL_DUPLEX_MODE_MSB 8

4316

#define MR_AN_CONTROL_DUPLEX_MODE_LSB 8

4317

#define MR_AN_CONTROL_DUPLEX_MODE_MASK 0x00000100

4318

#define MR_AN_CONTROL_DUPLEX_MODE_GET(x) (((x) & MR_AN_CONTROL_DUPLEX_MODE_MASK) >> MR_AN_CONTROL_DUPLEX_MODE_LSB)

4319

#define MR_AN_CONTROL_DUPLEX_MODE_SET(x) (((x) << MR_AN_CONTROL_DUPLEX_MODE_LSB) & MR_AN_CONTROL_DUPLEX_MODE_MASK)

4320

#define MR_AN_CONTROL_DUPLEX_MODE_RESET 0x1 // 1

4321

#define MR_AN_CONTROL_SPEED_SEL1_MSB 6

4322

#define MR_AN_CONTROL_SPEED_SEL1_LSB 6

4323

#define MR_AN_CONTROL_SPEED_SEL1_MASK 0x00000040

4324

#define MR_AN_CONTROL_SPEED_SEL1_GET(x) (((x) & MR_AN_CONTROL_SPEED_SEL1_MASK) >> MR_AN_CONTROL_SPEED_SEL1_LSB)

4325

#define MR_AN_CONTROL_SPEED_SEL1_SET(x) (((x) << MR_AN_CONTROL_SPEED_SEL1_LSB) & MR_AN_CONTROL_SPEED_SEL1_MASK)

4326

#define MR_AN_CONTROL_SPEED_SEL1_RESET 0x1 // 1

4327

#define MR_AN_CONTROL_ADDRESS 0x1807001c

// 32'h18070014 (SGMII_RESET)

4334

#define SGMII_RESET_HW_RX_125M_N_MSB 4

4335

#define SGMII_RESET_HW_RX_125M_N_LSB 4

4336

#define SGMII_RESET_HW_RX_125M_N_MASK 0x00000010

4337

#define SGMII_RESET_HW_RX_125M_N_GET(x) (((x) & SGMII_RESET_HW_RX_125M_N_MASK) >> SGMII_RESET_HW_RX_125M_N_LSB)

4338

#define SGMII_RESET_HW_RX_125M_N_SET(x) (((x) << SGMII_RESET_HW_RX_125M_N_LSB) & SGMII_RESET_HW_RX_125M_N_MASK)

4339

#define SGMII_RESET_HW_RX_125M_N_RESET 0x0 // 0

4340

#define SGMII_RESET_TX_125M_N_MSB 3

4341

#define SGMII_RESET_TX_125M_N_LSB 3

4342

#define SGMII_RESET_TX_125M_N_MASK 0x00000008

4343

#define SGMII_RESET_TX_125M_N_GET(x) (((x) & SGMII_RESET_TX_125M_N_MASK) >> SGMII_RESET_TX_125M_N_LSB)

4344

#define SGMII_RESET_TX_125M_N_SET(x) (((x) << SGMII_RESET_TX_125M_N_LSB) & SGMII_RESET_TX_125M_N_MASK)

4345

#define SGMII_RESET_TX_125M_N_RESET 0x0 // 0

4346

#define SGMII_RESET_RX_125M_N_MSB 2

4347

#define SGMII_RESET_RX_125M_N_LSB 2

4348

#define SGMII_RESET_RX_125M_N_MASK 0x00000004

4349

#define SGMII_RESET_RX_125M_N_GET(x) (((x) & SGMII_RESET_RX_125M_N_MASK) >> SGMII_RESET_RX_125M_N_LSB)

4350

#define SGMII_RESET_RX_125M_N_SET(x) (((x) << SGMII_RESET_RX_125M_N_LSB) & SGMII_RESET_RX_125M_N_MASK)

4351

#define SGMII_RESET_RX_125M_N_RESET 0x0 // 0

4352

#define SGMII_RESET_TX_CLK_N_MSB 1

4353

#define SGMII_RESET_TX_CLK_N_LSB 1

4354

#define SGMII_RESET_TX_CLK_N_MASK 0x00000002

4355

#define SGMII_RESET_TX_CLK_N_GET(x) (((x) & SGMII_RESET_TX_CLK_N_MASK) >> SGMII_RESET_TX_CLK_N_LSB)

4356

#define SGMII_RESET_TX_CLK_N_SET(x) (((x) << SGMII_RESET_TX_CLK_N_LSB) & SGMII_RESET_TX_CLK_N_MASK)

4357

#define SGMII_RESET_TX_CLK_N_RESET 0x0 // 0

4358

#define SGMII_RESET_RX_CLK_N_MSB 0

4359

#define SGMII_RESET_RX_CLK_N_LSB 0

4360

#define SGMII_RESET_RX_CLK_N_MASK 0x00000001

4361

#define SGMII_RESET_RX_CLK_N_GET(x) (((x) & SGMII_RESET_RX_CLK_N_MASK) >> SGMII_RESET_RX_CLK_N_LSB)

4362

#define SGMII_RESET_RX_CLK_N_SET(x) (((x) << SGMII_RESET_RX_CLK_N_LSB) & SGMII_RESET_RX_CLK_N_MASK)

4363

#define SGMII_RESET_RX_CLK_N_RESET 0x0 // 0

4364

#define SGMII_RESET_ADDRESS 0x18070014

// 32'h18070038 (SGMII_MAC_RX_CONFIG)

4369

#define SGMII_MAC_RX_CONFIG_LINK_MSB 15

4370

#define SGMII_MAC_RX_CONFIG_LINK_LSB 15

4371

#define SGMII_MAC_RX_CONFIG_LINK_MASK 0x00008000

4372

#define SGMII_MAC_RX_CONFIG_LINK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_LINK_MASK) >> SGMII_MAC_RX_CONFIG_LINK_LSB)

4373

#define SGMII_MAC_RX_CONFIG_LINK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_LINK_LSB) & SGMII_MAC_RX_CONFIG_LINK_MASK)

4374

#define SGMII_MAC_RX_CONFIG_LINK_RESET 0x0 // 0

4375

#define SGMII_MAC_RX_CONFIG_ACK_MSB 14

4376

#define SGMII_MAC_RX_CONFIG_ACK_LSB 14

4377

#define SGMII_MAC_RX_CONFIG_ACK_MASK 0x00004000

4378

#define SGMII_MAC_RX_CONFIG_ACK_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ACK_MASK) >> SGMII_MAC_RX_CONFIG_ACK_LSB)

4379

#define SGMII_MAC_RX_CONFIG_ACK_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ACK_LSB) & SGMII_MAC_RX_CONFIG_ACK_MASK)

4380

#define SGMII_MAC_RX_CONFIG_ACK_RESET 0x0 // 0

4381

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MSB 12

4382

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB 12

4383

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK 0x00001000

4384

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK) >> SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB)

4385

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_DUPLEX_MODE_LSB) & SGMII_MAC_RX_CONFIG_DUPLEX_MODE_MASK)

4386

#define SGMII_MAC_RX_CONFIG_DUPLEX_MODE_RESET 0x0 // 0

4387

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MSB 11

4388

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB 10

4389

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK 0x00000c00

4390

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK) >> SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB)

4391

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_SPEED_MODE_LSB) & SGMII_MAC_RX_CONFIG_SPEED_MODE_MASK)

4392

#define SGMII_MAC_RX_CONFIG_SPEED_MODE_RESET 0x0 // 0

4393

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MSB 8

4394

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB 8

4395

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK 0x00000100

4396

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB)

4397

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_ASM_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_ASM_PAUSE_MASK)

4398

#define SGMII_MAC_RX_CONFIG_ASM_PAUSE_RESET 0x0 // 0

4399

#define SGMII_MAC_RX_CONFIG_PAUSE_MSB 7

4400

#define SGMII_MAC_RX_CONFIG_PAUSE_LSB 7

4401

#define SGMII_MAC_RX_CONFIG_PAUSE_MASK 0x00000080

4402

#define SGMII_MAC_RX_CONFIG_PAUSE_GET(x) (((x) & SGMII_MAC_RX_CONFIG_PAUSE_MASK) >> SGMII_MAC_RX_CONFIG_PAUSE_LSB)

4403

#define SGMII_MAC_RX_CONFIG_PAUSE_SET(x) (((x) << SGMII_MAC_RX_CONFIG_PAUSE_LSB) & SGMII_MAC_RX_CONFIG_PAUSE_MASK)

4404

#define SGMII_MAC_RX_CONFIG_PAUSE_RESET 0x0 // 0

4405

#define SGMII_MAC_RX_CONFIG_RES0_MSB 0

4406

#define SGMII_MAC_RX_CONFIG_RES0_LSB 0

4407

#define SGMII_MAC_RX_CONFIG_RES0_MASK 0x00000001

4408

#define SGMII_MAC_RX_CONFIG_RES0_GET(x) (((x) & SGMII_MAC_RX_CONFIG_RES0_MASK) >> SGMII_MAC_RX_CONFIG_RES0_LSB)

4409

#define SGMII_MAC_RX_CONFIG_RES0_SET(x) (((x) << SGMII_MAC_RX_CONFIG_RES0_LSB) & SGMII_MAC_RX_CONFIG_RES0_MASK)

4410

#define SGMII_MAC_RX_CONFIG_RES0_RESET 0x1 // 1

4411

#define SGMII_MAC_RX_CONFIG_ADDRESS 0x18070038

4412

4413

// 32'h18070058 (SGMII_DEBUG)

4414

#define SGMII_DEBUG_ARB_STATE_MSB 27

4415

#define SGMII_DEBUG_ARB_STATE_LSB 24

4416

#define SGMII_DEBUG_ARB_STATE_MASK 0x0f000000

4417

#define SGMII_DEBUG_ARB_STATE_GET(x) (((x) & SGMII_DEBUG_ARB_STATE_MASK) >> SGMII_DEBUG_ARB_STATE_LSB)

4418

#define SGMII_DEBUG_ARB_STATE_SET(x) (((x) << SGMII_DEBUG_ARB_STATE_LSB) & SGMII_DEBUG_ARB_STATE_MASK)

4419

#define SGMII_DEBUG_ARB_STATE_RESET 0x0 // 0

4420

#define SGMII_DEBUG_RX_SYNC_STATE_MSB 23

4421

#define SGMII_DEBUG_RX_SYNC_STATE_LSB 16

4422

#define SGMII_DEBUG_RX_SYNC_STATE_MASK 0x00ff0000

4423

#define SGMII_DEBUG_RX_SYNC_STATE_GET(x) (((x) & SGMII_DEBUG_RX_SYNC_STATE_MASK) >> SGMII_DEBUG_RX_SYNC_STATE_LSB)

4424

#define SGMII_DEBUG_RX_SYNC_STATE_SET(x) (((x) << SGMII_DEBUG_RX_SYNC_STATE_LSB) & SGMII_DEBUG_RX_SYNC_STATE_MASK)

4425

#define SGMII_DEBUG_RX_SYNC_STATE_RESET 0x0 // 0

4426

#define SGMII_DEBUG_RX_STATE_MSB 15

4427

#define SGMII_DEBUG_RX_STATE_LSB 8

4428

#define SGMII_DEBUG_RX_STATE_MASK 0x0000ff00

4429

#define SGMII_DEBUG_RX_STATE_GET(x) (((x) & SGMII_DEBUG_RX_STATE_MASK) >> SGMII_DEBUG_RX_STATE_LSB)

4430

#define SGMII_DEBUG_RX_STATE_SET(x) (((x) << SGMII_DEBUG_RX_STATE_LSB) & SGMII_DEBUG_RX_STATE_MASK)

4431

#define SGMII_DEBUG_RX_STATE_RESET 0x0 // 0

4432

#define SGMII_DEBUG_TX_STATE_MSB 7

4433

#define SGMII_DEBUG_TX_STATE_LSB 0

4434

#define SGMII_DEBUG_TX_STATE_MASK 0x000000ff

4435

#define SGMII_DEBUG_TX_STATE_GET(x) (((x) & SGMII_DEBUG_TX_STATE_MASK) >> SGMII_DEBUG_TX_STATE_LSB)

4436

#define SGMII_DEBUG_TX_STATE_SET(x) (((x) << SGMII_DEBUG_TX_STATE_LSB) & SGMII_DEBUG_TX_STATE_MASK)

4437

#define SGMII_DEBUG_TX_STATE_RESET 0x0 // 0

4438

#define SGMII_DEBUG_ADDRESS 0x18070058

4439

#define SGMII_DEBUG_OFFSET 0x0058

4440

4441

// 32'h18070060 (SGMII_INTERRUPT_MASK)

4442

#define SGMII_INTERRUPT_MASK_MASK_MSB 7

4443

#define SGMII_INTERRUPT_MASK_MASK_LSB 0

4444

#define SGMII_INTERRUPT_MASK_MASK_MASK 0x000000ff

4445

#define SGMII_INTERRUPT_MASK_MASK_GET(x) (((x) & SGMII_INTERRUPT_MASK_MASK_MASK) >> SGMII_INTERRUPT_MASK_MASK_LSB)

4446

#define SGMII_INTERRUPT_MASK_MASK_SET(x) (((x) << SGMII_INTERRUPT_MASK_MASK_LSB) & SGMII_INTERRUPT_MASK_MASK_MASK)

4447

#define SGMII_INTERRUPT_MASK_MASK_RESET 0x0 // 0

4448

#define SGMII_INTERRUPT_MASK_ADDRESS 0x18070060

4449

4450

4451

// 32'h1807005c (SGMII_INTERRUPT)

4452

#define SGMII_INTERRUPT_INTR_MSB 7

4453

#define SGMII_INTERRUPT_INTR_LSB 0

4454

#define SGMII_INTERRUPT_INTR_MASK 0x000000ff

4455

#define SGMII_INTERRUPT_INTR_GET(x) (((x) & SGMII_INTERRUPT_INTR_MASK) >> SGMII_INTERRUPT_INTR_LSB)

4456

#define SGMII_INTERRUPT_INTR_SET(x) (((x) << SGMII_INTERRUPT_INTR_LSB) & SGMII_INTERRUPT_INTR_MASK)

4457

#define SGMII_INTERRUPT_INTR_RESET 0x0 // 0

4458

#define SGMII_INTERRUPT_ADDRESS 0x1807005c

4459

#define SGMII_INTERRUPT_OFFSET 0x005c

4460

// SW modifiable bits

4461

#define SGMII_INTERRUPT_SW_MASK 0x000000ff

4462

// bits defined at reset

4463

#define SGMII_INTERRUPT_RSTMASK 0xffffffff

4464

// reset value (ignore bits undefined at reset)

4465

#define SGMII_INTERRUPT_RESET 0x00000000

4466

4467

4468

#define SGMII_LINK_FAIL (1 << 0)

4469

#define SGMII_DUPLEX_ERR (1 << 1)

4470

#define SGMII_MR_AN_COMPLETE (1 << 2)

4471

#define SGMII_LINK_MAC_CHANGE (1 << 3)

4472

#define SGMII_DUPLEX_MODE_CHANGE (1 << 4)

4473

#define SGMII_SPEED_MODE_MAC_CHANGE (1 << 5)

4474

#define SGMII_RX_QUIET_CHANGE (1 << 6)

4475

#define SGMII_RX_MDIO_COMP_CHANGE (1 << 7)

4476

4477

#define SGMII_INTR SGMII_LINK_FAIL | \

4478

SGMII_LINK_MAC_CHANGE | \

4479

SGMII_DUPLEX_MODE_CHANGE | \

4480

SGMII_SPEED_MODE_MAC_CHANGE

4481

4482

4483

// 32'h18050048 (ETH_SGMII)

4484

#define ETH_SGMII_TX_INVERT_MSB 31

4485

#define ETH_SGMII_TX_INVERT_LSB 31

4486

#define ETH_SGMII_TX_INVERT_MASK 0x80000000

4487

#define ETH_SGMII_TX_INVERT_GET(x) (((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB)

4488

#define ETH_SGMII_TX_INVERT_SET(x) (((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK)

4489

#define ETH_SGMII_TX_INVERT_RESET 0x0 // 0

4490

#define ETH_SGMII_GIGE_QUAD_MSB 30

4491

#define ETH_SGMII_GIGE_QUAD_LSB 30

4492

#define ETH_SGMII_GIGE_QUAD_MASK 0x40000000

4493

#define ETH_SGMII_GIGE_QUAD_GET(x) (((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB)

4494

#define ETH_SGMII_GIGE_QUAD_SET(x) (((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK)

4495

#define ETH_SGMII_GIGE_QUAD_RESET 0x0 // 0

4496

#define ETH_SGMII_RX_DELAY_MSB 29

4497

#define ETH_SGMII_RX_DELAY_LSB 28

4498

#define ETH_SGMII_RX_DELAY_MASK 0x30000000

4499

#define ETH_SGMII_RX_DELAY_GET(x) (((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB)

4500

#define ETH_SGMII_RX_DELAY_SET(x) (((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK)

4501

#define ETH_SGMII_RX_DELAY_RESET 0x0 // 0

4502

#define ETH_SGMII_TX_DELAY_MSB 27

4503

#define ETH_SGMII_TX_DELAY_LSB 26

4504

#define ETH_SGMII_TX_DELAY_MASK 0x0c000000

4505

#define ETH_SGMII_TX_DELAY_GET(x) (((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB)

4506

#define ETH_SGMII_TX_DELAY_SET(x) (((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK)

4507

#define ETH_SGMII_TX_DELAY_RESET 0x0 // 0

4508

#define ETH_SGMII_CLK_SEL_MSB 25

4509

#define ETH_SGMII_CLK_SEL_LSB 25

4510

#define ETH_SGMII_CLK_SEL_MASK 0x02000000

4511

#define ETH_SGMII_CLK_SEL_GET(x) (((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB)

4512

#define ETH_SGMII_CLK_SEL_SET(x) (((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK)

4513

#define ETH_SGMII_CLK_SEL_RESET 0x1 // 1

4514

#define ETH_SGMII_GIGE_MSB 24

4515

#define ETH_SGMII_GIGE_LSB 24

4516

#define ETH_SGMII_GIGE_MASK 0x01000000

4517

#define ETH_SGMII_GIGE_GET(x) (((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB)

4518

#define ETH_SGMII_GIGE_SET(x) (((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK)

4519

#define ETH_SGMII_GIGE_RESET 0x1 // 1

4520

#define ETH_SGMII_PHASE1_COUNT_MSB 15

4521

#define ETH_SGMII_PHASE1_COUNT_LSB 8

4522

#define ETH_SGMII_PHASE1_COUNT_MASK 0x0000ff00

4523

#define ETH_SGMII_PHASE1_COUNT_GET(x) (((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB)

4524

#define ETH_SGMII_PHASE1_COUNT_SET(x) (((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK)

4525

#define ETH_SGMII_PHASE1_COUNT_RESET 0x1 // 1

4526

#define ETH_SGMII_PHASE0_COUNT_MSB 7

4527

#define ETH_SGMII_PHASE0_COUNT_LSB 0

4528

#define ETH_SGMII_PHASE0_COUNT_MASK 0x000000ff

4529

#define ETH_SGMII_PHASE0_COUNT_GET(x) (((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB)

4530

#define ETH_SGMII_PHASE0_COUNT_SET(x) (((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK)

4531

#define ETH_SGMII_PHASE0_COUNT_RESET 0x1 // 1

4532

#define ETH_SGMII_ADDRESS 0x18050048

4533

4534

4535

#endif /* _QCA956X_H */